diff --git a/TD-1-test/.cproject b/TD-1-test/.cproject
index f32dbcc..64370a7 100644
--- a/TD-1-test/.cproject
+++ b/TD-1-test/.cproject
@@ -22,7 +22,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.150742750" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1339960634" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="NUCLEO-L152RE" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.2057822195" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || NUCLEO-L152RE || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32L1xx_HAL_Driver/Inc | ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32L1xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32L152xE ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L152RETX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1361567838" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="32" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1361567838" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1189683139" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/TD-1-test}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.11055888" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.894267385" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -100,7 +100,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1678200497" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1322935538" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="NUCLEO-L152RE" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.935147694" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || NUCLEO-L152RE || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32L1xx_HAL_Driver/Inc | ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32L1xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32L152xE ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L152RETX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1476195682" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="32" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1476195682" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.618366169" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/TD-1-test}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1415195972" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.860370182" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
diff --git a/TD-1-test/.mxproject b/TD-1-test/.mxproject
index 2b3d12b..fe6566c 100644
--- a/TD-1-test/.mxproject
+++ b/TD-1-test/.mxproject
@@ -1,8 +1,8 @@
 [PreviousLibFiles]
-LibFiles=Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usart.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crs.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usart.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crs.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;
+LibFiles=Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crs.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usart.h;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crs.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_usart.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;
 
 [PreviousUsedCubeIDEFiles]
-SourceFiles=Core/Src/main.c;Core/Src/stm32l1xx_it.c;Core/Src/stm32l1xx_hal_msp.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Core/Src/system_stm32l1xx.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Core/Src/system_stm32l1xx.c;;;
+SourceFiles=Core/Src/main.c;Core/Src/stm32l1xx_it.c;Core/Src/stm32l1xx_hal_msp.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Core/Src/system_stm32l1xx.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Core/Src/system_stm32l1xx.c;;;
 HeaderPath=Drivers/STM32L1xx_HAL_Driver/Inc;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L1xx/Include;Drivers/CMSIS/Include;Core/Inc;
 CDefines=USE_HAL_DRIVER;STM32L152xE;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
diff --git a/TD-1-test/Core/Inc/stm32l1xx_hal_conf.h b/TD-1-test/Core/Inc/stm32l1xx_hal_conf.h
index e60d56a..c5f82c2 100644
--- a/TD-1-test/Core/Inc/stm32l1xx_hal_conf.h
+++ b/TD-1-test/Core/Inc/stm32l1xx_hal_conf.h
@@ -52,7 +52,7 @@
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 /*#define HAL_SPI_MODULE_ENABLED   */
 /*#define HAL_SRAM_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */
 /*#define HAL_WWDG_MODULE_ENABLED   */
diff --git a/TD-1-test/Core/Inc/stm32l1xx_it.h b/TD-1-test/Core/Inc/stm32l1xx_it.h
index 85fe63d..6b2cf58 100644
--- a/TD-1-test/Core/Inc/stm32l1xx_it.h
+++ b/TD-1-test/Core/Inc/stm32l1xx_it.h
@@ -56,6 +56,7 @@ void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
 void EXTI15_10_IRQHandler(void);
+void TIM6_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
 /* USER CODE END EFP */
diff --git a/TD-1-test/Core/Src/main.c b/TD-1-test/Core/Src/main.c
index 5976798..7707d8b 100644
--- a/TD-1-test/Core/Src/main.c
+++ b/TD-1-test/Core/Src/main.c
@@ -42,6 +42,8 @@
 /* USER CODE END PM */
 
 /* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef htim6;
+
 UART_HandleTypeDef huart2;
 
 /* USER CODE BEGIN PV */
@@ -53,6 +55,7 @@ UART_HandleTypeDef huart2;
 void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
 static void MX_USART2_UART_Init(void);
+static void MX_TIM6_Init(void);
 /* USER CODE BEGIN PFP */
 
 /* USER CODE END PFP */
@@ -92,6 +95,7 @@ int main(void)
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
   MX_USART2_UART_Init();
+  MX_TIM6_Init();
   /* USER CODE BEGIN 2 */
 
   // Allume la led V1
@@ -104,6 +108,10 @@ int main(void)
 
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
+
+  //status_bouton = *((uint32_t*)0x40020810);
+  TIM6->DIER |= 1<<0;
+  TIM6->CR1 |= 1<<0;
   while (1)
   {
     /* USER CODE END WHILE */
@@ -166,10 +174,7 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     Error_Handler();
@@ -179,17 +184,55 @@ void SystemClock_Config(void)
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
   {
     Error_Handler();
   }
 }
 
+/**
+  * @brief TIM6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM6_Init(void)
+{
+
+  /* USER CODE BEGIN TIM6_Init 0 */
+
+  /* USER CODE END TIM6_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM6_Init 1 */
+
+  /* USER CODE END TIM6_Init 1 */
+  htim6.Instance = TIM6;
+  htim6.Init.Prescaler = 16000-1;
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim6.Init.Period = 1000-1;
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM6_Init 2 */
+
+  /* USER CODE END TIM6_Init 2 */
+
+}
+
 /**
   * @brief USART2 Initialization Function
   * @param None
diff --git a/TD-1-test/Core/Src/stm32l1xx_hal_msp.c b/TD-1-test/Core/Src/stm32l1xx_hal_msp.c
index fc736ab..0789a70 100644
--- a/TD-1-test/Core/Src/stm32l1xx_hal_msp.c
+++ b/TD-1-test/Core/Src/stm32l1xx_hal_msp.c
@@ -80,6 +80,57 @@ void HAL_MspInit(void)
   /* USER CODE END MspInit 1 */
 }
 
+/**
+  * @brief TIM_Base MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param htim_base: TIM_Base handle pointer
+  * @retval None
+  */
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM6)
+  {
+    /* USER CODE BEGIN TIM6_MspInit 0 */
+
+    /* USER CODE END TIM6_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM6_CLK_ENABLE();
+    /* TIM6 interrupt Init */
+    HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM6_IRQn);
+    /* USER CODE BEGIN TIM6_MspInit 1 */
+
+    /* USER CODE END TIM6_MspInit 1 */
+
+  }
+
+}
+
+/**
+  * @brief TIM_Base MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param htim_base: TIM_Base handle pointer
+  * @retval None
+  */
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+  if(htim_base->Instance==TIM6)
+  {
+    /* USER CODE BEGIN TIM6_MspDeInit 0 */
+
+    /* USER CODE END TIM6_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM6_CLK_DISABLE();
+
+    /* TIM6 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(TIM6_IRQn);
+    /* USER CODE BEGIN TIM6_MspDeInit 1 */
+
+    /* USER CODE END TIM6_MspDeInit 1 */
+  }
+
+}
+
 /**
   * @brief UART MSP Initialization
   * This function configures the hardware resources used in this example
diff --git a/TD-1-test/Core/Src/stm32l1xx_it.c b/TD-1-test/Core/Src/stm32l1xx_it.c
index 76c4590..3ea661d 100644
--- a/TD-1-test/Core/Src/stm32l1xx_it.c
+++ b/TD-1-test/Core/Src/stm32l1xx_it.c
@@ -55,7 +55,7 @@
 /* USER CODE END 0 */
 
 /* External variables --------------------------------------------------------*/
-
+extern TIM_HandleTypeDef htim6;
 /* USER CODE BEGIN EV */
 
 /* USER CODE END EV */
@@ -207,12 +207,27 @@ void EXTI15_10_IRQHandler(void)
 
   /* USER CODE END EXTI15_10_IRQn 0 */
   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
-
   /* USER CODE BEGIN EXTI15_10_IRQn 1 */
 
   /* USER CODE END EXTI15_10_IRQn 1 */
 }
 
+/**
+  * @brief This function handles TIM6 global interrupt.
+  */
+void TIM6_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM6_IRQn 0 */
+	  GPIOA->ODR ^= (1 << 5);
+
+
+  /* USER CODE END TIM6_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim6);
+  /* USER CODE BEGIN TIM6_IRQn 1 */
+
+  /* USER CODE END TIM6_IRQn 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
diff --git a/TD-1-test/Debug/Core/Src/main.cyclo b/TD-1-test/Debug/Core/Src/main.cyclo
index b1f8f1c..b030c0a 100644
--- a/TD-1-test/Debug/Core/Src/main.cyclo
+++ b/TD-1-test/Debug/Core/Src/main.cyclo
@@ -1,6 +1,7 @@
-../Core/Src/main.c:69:5:main	1
-../Core/Src/main.c:154:6:SystemClock_Config	3
-../Core/Src/main.c:198:13:MX_USART2_UART_Init	2
-../Core/Src/main.c:231:13:MX_GPIO_Init	1
-../Core/Src/main.c:270:6:HAL_GPIO_EXTI_Callback	1
-../Core/Src/main.c:281:6:Error_Handler	1
+../Core/Src/main.c:72:5:main	1
+../Core/Src/main.c:162:6:SystemClock_Config	3
+../Core/Src/main.c:203:13:MX_TIM6_Init	3
+../Core/Src/main.c:241:13:MX_USART2_UART_Init	2
+../Core/Src/main.c:274:13:MX_GPIO_Init	1
+../Core/Src/main.c:313:6:HAL_GPIO_EXTI_Callback	1
+../Core/Src/main.c:324:6:Error_Handler	1
diff --git a/TD-1-test/Debug/Core/Src/main.d b/TD-1-test/Debug/Core/Src/main.d
index 5a6ecb3..b559bd3 100644
--- a/TD-1-test/Debug/Core/Src/main.d
+++ b/TD-1-test/Debug/Core/Src/main.d
@@ -22,6 +22,8 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Core/Inc/main.h:
@@ -48,5 +50,7 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Core/Src/main.o b/TD-1-test/Debug/Core/Src/main.o
index dc43b8e..67f97d2 100644
Binary files a/TD-1-test/Debug/Core/Src/main.o and b/TD-1-test/Debug/Core/Src/main.o differ
diff --git a/TD-1-test/Debug/Core/Src/main.su b/TD-1-test/Debug/Core/Src/main.su
index 22f2bbd..f9067d6 100644
--- a/TD-1-test/Debug/Core/Src/main.su
+++ b/TD-1-test/Debug/Core/Src/main.su
@@ -1,6 +1,7 @@
-../Core/Src/main.c:69:5:main	24	static
-../Core/Src/main.c:154:6:SystemClock_Config	80	static
-../Core/Src/main.c:198:13:MX_USART2_UART_Init	8	static
-../Core/Src/main.c:231:13:MX_GPIO_Init	48	static
-../Core/Src/main.c:270:6:HAL_GPIO_EXTI_Callback	16	static
-../Core/Src/main.c:281:6:Error_Handler	4	static,ignoring_inline_asm
+../Core/Src/main.c:72:5:main	24	static
+../Core/Src/main.c:162:6:SystemClock_Config	80	static
+../Core/Src/main.c:203:13:MX_TIM6_Init	16	static
+../Core/Src/main.c:241:13:MX_USART2_UART_Init	8	static
+../Core/Src/main.c:274:13:MX_GPIO_Init	48	static
+../Core/Src/main.c:313:6:HAL_GPIO_EXTI_Callback	16	static
+../Core/Src/main.c:324:6:Error_Handler	4	static,ignoring_inline_asm
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.cyclo b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.cyclo
index 9b749c0..034fa5c 100644
--- a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.cyclo
+++ b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.cyclo
@@ -1,3 +1,5 @@
 ../Core/Src/stm32l1xx_hal_msp.c:63:6:HAL_MspInit	1
-../Core/Src/stm32l1xx_hal_msp.c:89:6:HAL_UART_MspInit	2
-../Core/Src/stm32l1xx_hal_msp.c:126:6:HAL_UART_MspDeInit	2
+../Core/Src/stm32l1xx_hal_msp.c:89:6:HAL_TIM_Base_MspInit	2
+../Core/Src/stm32l1xx_hal_msp.c:115:6:HAL_TIM_Base_MspDeInit	2
+../Core/Src/stm32l1xx_hal_msp.c:140:6:HAL_UART_MspInit	2
+../Core/Src/stm32l1xx_hal_msp.c:177:6:HAL_UART_MspDeInit	2
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.d b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.d
index 73d01ad..dc7ab85 100644
--- a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.d
+++ b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.d
@@ -22,6 +22,8 @@ Core/Src/stm32l1xx_hal_msp.o: ../Core/Src/stm32l1xx_hal_msp.c \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Core/Inc/main.h:
@@ -48,5 +50,7 @@ Core/Src/stm32l1xx_hal_msp.o: ../Core/Src/stm32l1xx_hal_msp.c \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.o b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.o
index 98c84d2..dc62b7a 100644
Binary files a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.o and b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.o differ
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.su b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.su
index 391a0a1..e1289fe 100644
--- a/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.su
+++ b/TD-1-test/Debug/Core/Src/stm32l1xx_hal_msp.su
@@ -1,3 +1,5 @@
 ../Core/Src/stm32l1xx_hal_msp.c:63:6:HAL_MspInit	24	static
-../Core/Src/stm32l1xx_hal_msp.c:89:6:HAL_UART_MspInit	48	static
-../Core/Src/stm32l1xx_hal_msp.c:126:6:HAL_UART_MspDeInit	16	static
+../Core/Src/stm32l1xx_hal_msp.c:89:6:HAL_TIM_Base_MspInit	24	static
+../Core/Src/stm32l1xx_hal_msp.c:115:6:HAL_TIM_Base_MspDeInit	16	static
+../Core/Src/stm32l1xx_hal_msp.c:140:6:HAL_UART_MspInit	48	static
+../Core/Src/stm32l1xx_hal_msp.c:177:6:HAL_UART_MspDeInit	16	static
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_it.cyclo b/TD-1-test/Debug/Core/Src/stm32l1xx_it.cyclo
index 3312dab..1877d00 100644
--- a/TD-1-test/Debug/Core/Src/stm32l1xx_it.cyclo
+++ b/TD-1-test/Debug/Core/Src/stm32l1xx_it.cyclo
@@ -8,3 +8,4 @@
 ../Core/Src/stm32l1xx_it.c:170:6:PendSV_Handler	1
 ../Core/Src/stm32l1xx_it.c:183:6:SysTick_Handler	1
 ../Core/Src/stm32l1xx_it.c:204:6:EXTI15_10_IRQHandler	1
+../Core/Src/stm32l1xx_it.c:218:6:TIM6_IRQHandler	1
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_it.d b/TD-1-test/Debug/Core/Src/stm32l1xx_it.d
index a581715..166e64a 100644
--- a/TD-1-test/Debug/Core/Src/stm32l1xx_it.d
+++ b/TD-1-test/Debug/Core/Src/stm32l1xx_it.d
@@ -22,6 +22,8 @@ Core/Src/stm32l1xx_it.o: ../Core/Src/stm32l1xx_it.c ../Core/Inc/main.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h \
  ../Core/Inc/stm32l1xx_it.h
@@ -49,6 +51,8 @@ Core/Src/stm32l1xx_it.o: ../Core/Src/stm32l1xx_it.c ../Core/Inc/main.h \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
 ../Core/Inc/stm32l1xx_it.h:
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_it.o b/TD-1-test/Debug/Core/Src/stm32l1xx_it.o
index 61f5448..bb4837c 100644
Binary files a/TD-1-test/Debug/Core/Src/stm32l1xx_it.o and b/TD-1-test/Debug/Core/Src/stm32l1xx_it.o differ
diff --git a/TD-1-test/Debug/Core/Src/stm32l1xx_it.su b/TD-1-test/Debug/Core/Src/stm32l1xx_it.su
index 536dc1c..9ea60b0 100644
--- a/TD-1-test/Debug/Core/Src/stm32l1xx_it.su
+++ b/TD-1-test/Debug/Core/Src/stm32l1xx_it.su
@@ -8,3 +8,4 @@
 ../Core/Src/stm32l1xx_it.c:170:6:PendSV_Handler	4	static
 ../Core/Src/stm32l1xx_it.c:183:6:SysTick_Handler	8	static
 ../Core/Src/stm32l1xx_it.c:204:6:EXTI15_10_IRQHandler	8	static
+../Core/Src/stm32l1xx_it.c:218:6:TIM6_IRQHandler	8	static
diff --git a/TD-1-test/Debug/Core/Src/system_stm32l1xx.d b/TD-1-test/Debug/Core/Src/system_stm32l1xx.d
index c179bc8..7b19b79 100644
--- a/TD-1-test/Debug/Core/Src/system_stm32l1xx.d
+++ b/TD-1-test/Debug/Core/Src/system_stm32l1xx.d
@@ -22,6 +22,8 @@ Core/Src/system_stm32l1xx.o: ../Core/Src/system_stm32l1xx.c \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h:
@@ -47,5 +49,7 @@ Core/Src/system_stm32l1xx.o: ../Core/Src/system_stm32l1xx.c \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Core/Src/system_stm32l1xx.o b/TD-1-test/Debug/Core/Src/system_stm32l1xx.o
index 08131d6..1e8956e 100644
Binary files a/TD-1-test/Debug/Core/Src/system_stm32l1xx.o and b/TD-1-test/Debug/Core/Src/system_stm32l1xx.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d
index 3d4f9a1..b2541aa 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
index 722a46e..3a345e4 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d
index 0fe3509..cce04ca 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
index 5289046..5c2618b 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d
index 2fe7c43..f7cd9e2 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
index 2675edc..e5beddc 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d
index a311d21..f557174 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
index 134b68d..9a5b92d 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d
index 20f2bf6..96d1ab2 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
index 7ec555a..d4d83c6 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d
index b9302a0..7cce120 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
index 5e94bab..5e4167d 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d
index 1a0067e..18b224a 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
index 93b16d8..807672b 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d
index 59a9b74..ae5349a 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
index 038ca19..c519479 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d
index 8fce0b1..f43565e 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
index ba02d94..351b5e4 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d
index 79304d0..5135b4f 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
index 9ad7763..6f1ac1e 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d
index 1438b07..4277bb2 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
index a79fc89..c9673f7 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d
index 806a5e3..02085b6 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
index 6aecc17..21b857a 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.cyclo b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.cyclo
new file mode 100644
index 0000000..f7e4537
--- /dev/null
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.cyclo
@@ -0,0 +1,119 @@
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:269:19:HAL_TIM_Base_Init	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:328:19:HAL_TIM_Base_DeInit	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:370:13:HAL_TIM_Base_MspInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:385:13:HAL_TIM_Base_MspDeInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:401:19:HAL_TIM_Base_Start	7
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:440:19:HAL_TIM_Base_Stop	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:460:19:HAL_TIM_Base_Start_IT	7
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:502:19:HAL_TIM_Base_Stop_IT	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:527:19:HAL_TIM_Base_Start_DMA	11
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:596:19:HAL_TIM_Base_Stop_DMA	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:651:19:HAL_TIM_OC_Init	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:752:13:HAL_TIM_OC_MspInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:767:13:HAL_TIM_OC_MspDeInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:788:19:HAL_TIM_OC_Start	13
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:836:19:HAL_TIM_OC_Stop	5
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:865:19:HAL_TIM_OC_Start_IT	18
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:952:19:HAL_TIM_OC_Stop_IT	10
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1023:19:HAL_TIM_OC_Start_DMA	28
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1181:19:HAL_TIM_OC_Stop_DMA	10
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1278:19:HAL_TIM_PWM_Init	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1337:19:HAL_TIM_PWM_DeInit	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1379:13:HAL_TIM_PWM_MspInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1394:13:HAL_TIM_PWM_MspDeInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1415:19:HAL_TIM_PWM_Start	13
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1463:19:HAL_TIM_PWM_Stop	5
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1492:19:HAL_TIM_PWM_Start_IT	18
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1579:19:HAL_TIM_PWM_Stop_IT	10
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1650:19:HAL_TIM_PWM_Start_DMA	28
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1807:19:HAL_TIM_PWM_Stop_DMA	10
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1904:19:HAL_TIM_IC_Init	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1963:19:HAL_TIM_IC_DeInit	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2005:13:HAL_TIM_IC_MspInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2020:13:HAL_TIM_IC_MspDeInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2041:19:HAL_TIM_IC_Start	13
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2090:19:HAL_TIM_IC_Stop	5
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2119:19:HAL_TIM_IC_Start_IT	18
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2208:19:HAL_TIM_IC_Stop_IT	10
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2279:19:HAL_TIM_IC_Start_DMA	24
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2434:19:HAL_TIM_IC_Stop_DMA	10
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2538:19:HAL_TIM_OnePulse_Init	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2605:19:HAL_TIM_OnePulse_DeInit	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2648:13:HAL_TIM_OnePulse_MspInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2663:13:HAL_TIM_OnePulse_MspDeInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2683:19:HAL_TIM_OnePulse_Start	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2728:19:HAL_TIM_OnePulse_Stop	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2763:19:HAL_TIM_OnePulse_Start_IT	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2814:19:HAL_TIM_OnePulse_Stop_IT	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2885:19:HAL_TIM_Encoder_Init	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2998:19:HAL_TIM_Encoder_DeInit	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3041:13:HAL_TIM_Encoder_MspInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3056:13:HAL_TIM_Encoder_MspDeInit	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3076:19:HAL_TIM_Encoder_Start	9
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3160:19:HAL_TIM_Encoder_Stop	9
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3217:19:HAL_TIM_Encoder_Start_IT	9
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3307:19:HAL_TIM_Encoder_Stop_IT	9
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3369:19:HAL_TIM_Encoder_Start_DMA	24
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3568:19:HAL_TIM_Encoder_Stop_DMA	9
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3642:6:HAL_TIM_IRQHandler	17
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3833:19:HAL_TIM_OC_ConfigChannel	6
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3912:19:HAL_TIM_IC_ConfigChannel	6
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4011:19:HAL_TIM_PWM_ConfigChannel	6
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4125:19:HAL_TIM_OnePulse_ConfigChannel	8
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4268:19:HAL_TIM_DMABurst_WriteStart	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4319:19:HAL_TIM_DMABurst_MultiWriteStart	22
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4485:19:HAL_TIM_DMABurst_WriteStop	12
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4579:19:HAL_TIM_DMABurst_ReadStart	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4628:19:HAL_TIM_DMABurst_MultiReadStart	22
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4794:19:HAL_TIM_DMABurst_ReadStop	12
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4867:19:HAL_TIM_GenerateEvent	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4904:19:HAL_TIM_ConfigOCrefClear	16
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5043:19:HAL_TIM_ConfigClockSource	20
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5197:19:HAL_TIM_ConfigTI1Input	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5229:19:HAL_TIM_SlaveConfigSynchro	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5269:19:HAL_TIM_SlaveConfigSynchro_IT	3
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5312:10:HAL_TIM_ReadCapturedValue	5
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5396:13:HAL_TIM_PeriodElapsedCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5411:13:HAL_TIM_PeriodElapsedHalfCpltCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5426:13:HAL_TIM_OC_DelayElapsedCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5441:13:HAL_TIM_IC_CaptureCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5456:13:HAL_TIM_IC_CaptureHalfCpltCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5471:13:HAL_TIM_PWM_PulseFinishedCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5486:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5501:13:HAL_TIM_TriggerCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5516:13:HAL_TIM_TriggerHalfCpltCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5531:13:HAL_TIM_ErrorCallback	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6005:22:HAL_TIM_Base_GetState	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6015:22:HAL_TIM_OC_GetState	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6025:22:HAL_TIM_PWM_GetState	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6035:22:HAL_TIM_IC_GetState	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6045:22:HAL_TIM_OnePulse_GetState	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6055:22:HAL_TIM_Encoder_GetState	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6065:23:HAL_TIM_GetActiveChannel	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6083:29:HAL_TIM_GetChannelState	4
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6100:30:HAL_TIM_DMABurstState	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6125:6:TIM_DMAError	5
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6168:13:TIM_DMADelayPulseCplt	9
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6227:13:TIM_DMADelayPulseHalfCplt	5
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6266:6:TIM_DMACaptureCplt	9
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6325:6:TIM_DMACaptureHalfCplt	5
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6364:13:TIM_DMAPeriodElapsedCplt	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6385:13:TIM_DMAPeriodElapsedHalfCplt	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6401:13:TIM_DMATriggerCplt	2
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6422:13:TIM_DMATriggerHalfCplt	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6439:13:TIM_Base_SetConfig	13
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6485:13:TIM_OC1_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6533:13:TIM_OC2_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6582:13:TIM_OC3_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6630:13:TIM_OC4_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6679:26:TIM_SlaveTimer_SetConfig	16
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6813:13:TIM_TI1_SetConfig	7
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6860:13:TIM_TI1_ConfigInputStage	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6903:13:TIM_TI2_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6943:13:TIM_TI2_ConfigInputStage	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6986:13:TIM_TI3_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7034:13:TIM_TI4_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7077:13:TIM_ITRx_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7107:13:TIM_ETR_SetConfig	1
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7137:13:TIM_CCxChannelCmd	1
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d
new file mode 100644
index 0000000..6b33a6b
--- /dev/null
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d
@@ -0,0 +1,56 @@
+Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o: \
+ ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \
+ ../Core/Inc/stm32l1xx_hal_conf.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \
+ ../Drivers/CMSIS/Include/core_cm3.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
+../Core/Inc/stm32l1xx_hal_conf.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h:
+../Drivers/CMSIS/Include/core_cm3.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
new file mode 100644
index 0000000..c12daa2
Binary files /dev/null and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.su b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.su
new file mode 100644
index 0000000..27501f4
--- /dev/null
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.su
@@ -0,0 +1,119 @@
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:269:19:HAL_TIM_Base_Init	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:328:19:HAL_TIM_Base_DeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:370:13:HAL_TIM_Base_MspInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:385:13:HAL_TIM_Base_MspDeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:401:19:HAL_TIM_Base_Start	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:440:19:HAL_TIM_Base_Stop	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:460:19:HAL_TIM_Base_Start_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:502:19:HAL_TIM_Base_Stop_IT	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:527:19:HAL_TIM_Base_Start_DMA	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:596:19:HAL_TIM_Base_Stop_DMA	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:651:19:HAL_TIM_OC_Init	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:710:19:HAL_TIM_OC_DeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:752:13:HAL_TIM_OC_MspInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:767:13:HAL_TIM_OC_MspDeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:788:19:HAL_TIM_OC_Start	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:836:19:HAL_TIM_OC_Stop	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:865:19:HAL_TIM_OC_Start_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:952:19:HAL_TIM_OC_Stop_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1023:19:HAL_TIM_OC_Start_DMA	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1181:19:HAL_TIM_OC_Stop_DMA	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1278:19:HAL_TIM_PWM_Init	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1337:19:HAL_TIM_PWM_DeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1379:13:HAL_TIM_PWM_MspInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1394:13:HAL_TIM_PWM_MspDeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1415:19:HAL_TIM_PWM_Start	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1463:19:HAL_TIM_PWM_Stop	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1492:19:HAL_TIM_PWM_Start_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1579:19:HAL_TIM_PWM_Stop_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1650:19:HAL_TIM_PWM_Start_DMA	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1807:19:HAL_TIM_PWM_Stop_DMA	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1904:19:HAL_TIM_IC_Init	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:1963:19:HAL_TIM_IC_DeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2005:13:HAL_TIM_IC_MspInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2020:13:HAL_TIM_IC_MspDeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2041:19:HAL_TIM_IC_Start	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2090:19:HAL_TIM_IC_Stop	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2119:19:HAL_TIM_IC_Start_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2208:19:HAL_TIM_IC_Stop_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2279:19:HAL_TIM_IC_Start_DMA	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2434:19:HAL_TIM_IC_Stop_DMA	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2538:19:HAL_TIM_OnePulse_Init	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2605:19:HAL_TIM_OnePulse_DeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2648:13:HAL_TIM_OnePulse_MspInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2663:13:HAL_TIM_OnePulse_MspDeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2683:19:HAL_TIM_OnePulse_Start	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2728:19:HAL_TIM_OnePulse_Stop	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2763:19:HAL_TIM_OnePulse_Start_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2814:19:HAL_TIM_OnePulse_Stop_IT	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2885:19:HAL_TIM_Encoder_Init	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:2998:19:HAL_TIM_Encoder_DeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3041:13:HAL_TIM_Encoder_MspInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3056:13:HAL_TIM_Encoder_MspDeInit	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3076:19:HAL_TIM_Encoder_Start	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3160:19:HAL_TIM_Encoder_Stop	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3217:19:HAL_TIM_Encoder_Start_IT	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3307:19:HAL_TIM_Encoder_Stop_IT	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3369:19:HAL_TIM_Encoder_Start_DMA	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3568:19:HAL_TIM_Encoder_Stop_DMA	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3642:6:HAL_TIM_IRQHandler	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3833:19:HAL_TIM_OC_ConfigChannel	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:3912:19:HAL_TIM_IC_ConfigChannel	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4011:19:HAL_TIM_PWM_ConfigChannel	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4125:19:HAL_TIM_OnePulse_ConfigChannel	48	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4268:19:HAL_TIM_DMABurst_WriteStart	40	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4319:19:HAL_TIM_DMABurst_MultiWriteStart	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4485:19:HAL_TIM_DMABurst_WriteStop	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4579:19:HAL_TIM_DMABurst_ReadStart	40	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4628:19:HAL_TIM_DMABurst_MultiReadStart	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4794:19:HAL_TIM_DMABurst_ReadStop	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4867:19:HAL_TIM_GenerateEvent	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:4904:19:HAL_TIM_ConfigOCrefClear	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5043:19:HAL_TIM_ConfigClockSource	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5197:19:HAL_TIM_ConfigTI1Input	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5229:19:HAL_TIM_SlaveConfigSynchro	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5269:19:HAL_TIM_SlaveConfigSynchro_IT	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5312:10:HAL_TIM_ReadCapturedValue	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5396:13:HAL_TIM_PeriodElapsedCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5411:13:HAL_TIM_PeriodElapsedHalfCpltCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5426:13:HAL_TIM_OC_DelayElapsedCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5441:13:HAL_TIM_IC_CaptureCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5456:13:HAL_TIM_IC_CaptureHalfCpltCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5471:13:HAL_TIM_PWM_PulseFinishedCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5486:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5501:13:HAL_TIM_TriggerCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5516:13:HAL_TIM_TriggerHalfCpltCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:5531:13:HAL_TIM_ErrorCallback	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6005:22:HAL_TIM_Base_GetState	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6015:22:HAL_TIM_OC_GetState	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6025:22:HAL_TIM_PWM_GetState	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6035:22:HAL_TIM_IC_GetState	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6045:22:HAL_TIM_OnePulse_GetState	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6055:22:HAL_TIM_Encoder_GetState	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6065:23:HAL_TIM_GetActiveChannel	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6083:29:HAL_TIM_GetChannelState	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6100:30:HAL_TIM_DMABurstState	16	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6125:6:TIM_DMAError	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6168:13:TIM_DMADelayPulseCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6227:13:TIM_DMADelayPulseHalfCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6266:6:TIM_DMACaptureCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6325:6:TIM_DMACaptureHalfCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6364:13:TIM_DMAPeriodElapsedCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6385:13:TIM_DMAPeriodElapsedHalfCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6401:13:TIM_DMATriggerCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6422:13:TIM_DMATriggerHalfCplt	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6439:13:TIM_Base_SetConfig	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6485:13:TIM_OC1_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6533:13:TIM_OC2_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6582:13:TIM_OC3_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6630:13:TIM_OC4_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6679:26:TIM_SlaveTimer_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6813:13:TIM_TI1_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6860:13:TIM_TI1_ConfigInputStage	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6903:13:TIM_TI2_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6943:13:TIM_TI2_ConfigInputStage	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:6986:13:TIM_TI3_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7034:13:TIM_TI4_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7077:13:TIM_ITRx_SetConfig	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7107:13:TIM_ETR_SetConfig	32	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c:7137:13:TIM_CCxChannelCmd	32	static
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.cyclo b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.cyclo
new file mode 100644
index 0000000..f2ac232
--- /dev/null
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.cyclo
@@ -0,0 +1,2 @@
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c:83:19:HAL_TIMEx_MasterConfigSynchronization	6
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c:194:19:HAL_TIMEx_RemapConfig	2
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d
new file mode 100644
index 0000000..e178cc8
--- /dev/null
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d
@@ -0,0 +1,56 @@
+Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o: \
+ ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \
+ ../Core/Inc/stm32l1xx_hal_conf.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \
+ ../Drivers/CMSIS/Include/core_cm3.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
+../Core/Inc/stm32l1xx_hal_conf.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h:
+../Drivers/CMSIS/Include/core_cm3.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
new file mode 100644
index 0000000..5b0f4b4
Binary files /dev/null and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.su b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.su
new file mode 100644
index 0000000..1dd0bad
--- /dev/null
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.su
@@ -0,0 +1,2 @@
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c:83:19:HAL_TIMEx_MasterConfigSynchronization	24	static
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c:194:19:HAL_TIMEx_RemapConfig	16	static
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d
index 6c8509c..258a854 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d
@@ -23,6 +23,8 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o: \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \
  ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
@@ -48,5 +50,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o: \
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h:
 ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
index 1950bca..dd4c63a 100644
Binary files a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o and b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o differ
diff --git a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk
index 1492d0a..e5dd349 100644
--- a/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk
+++ b/TD-1-test/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk
@@ -17,6 +17,8 @@ C_SRCS += \
 ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c \
 ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c \
 ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c \
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c \
+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c \
 ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c 
 
 OBJS += \
@@ -32,6 +34,8 @@ OBJS += \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o \
+./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o \
+./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o 
 
 C_DEPS += \
@@ -47,6 +51,8 @@ C_DEPS += \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d \
+./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d \
+./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d \
 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d 
 
 
@@ -57,7 +63,7 @@ Drivers/STM32L1xx_HAL_Driver/Src/%.o Drivers/STM32L1xx_HAL_Driver/Src/%.su Drive
 clean: clean-Drivers-2f-STM32L1xx_HAL_Driver-2f-Src
 
 clean-Drivers-2f-STM32L1xx_HAL_Driver-2f-Src:
-	-$(RM) ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.su
+	-$(RM) ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.su ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.cyclo ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.su
 
 .PHONY: clean-Drivers-2f-STM32L1xx_HAL_Driver-2f-Src
 
diff --git a/TD-1-test/Debug/TD-1-test.elf b/TD-1-test/Debug/TD-1-test.elf
index fa4a2eb..36ef24d 100755
Binary files a/TD-1-test/Debug/TD-1-test.elf and b/TD-1-test/Debug/TD-1-test.elf differ
diff --git a/TD-1-test/Debug/TD-1-test.list b/TD-1-test/Debug/TD-1-test.list
index 4de49dc..9cc6291 100644
--- a/TD-1-test/Debug/TD-1-test.list
+++ b/TD-1-test/Debug/TD-1-test.list
@@ -5,47 +5,47 @@ Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
   0 .isr_vector   0000013c  08000000  08000000  00001000  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  1 .text         00001c7c  0800013c  0800013c  0000113c  2**2
+  1 .text         00002180  0800013c  0800013c  0000113c  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .rodata       00000024  08001db8  08001db8  00002db8  2**2
+  2 .rodata       00000024  080022bc  080022bc  000032bc  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  3 .ARM.extab    00000000  08001ddc  08001ddc  0000300c  2**0
+  3 .ARM.extab    00000000  080022e0  080022e0  0000400c  2**0
                   CONTENTS, READONLY
-  4 .ARM          00000008  08001ddc  08001ddc  00002ddc  2**2
+  4 .ARM          00000008  080022e0  080022e0  000032e0  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  5 .preinit_array 00000000  08001de4  08001de4  0000300c  2**0
+  5 .preinit_array 00000000  080022e8  080022e8  0000400c  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  6 .init_array   00000004  08001de4  08001de4  00002de4  2**2
+  6 .init_array   00000004  080022e8  080022e8  000032e8  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  7 .fini_array   00000004  08001de8  08001de8  00002de8  2**2
+  7 .fini_array   00000004  080022ec  080022ec  000032ec  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  8 .data         0000000c  20000000  08001dec  00003000  2**2
+  8 .data         0000000c  20000000  080022f0  00004000  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  9 .bss          00000068  2000000c  08001df8  0000300c  2**2
+  9 .bss          000000a8  2000000c  080022fc  0000400c  2**2
                   ALLOC
- 10 ._user_heap_stack 00000604  20000074  08001df8  00003074  2**0
+ 10 ._user_heap_stack 00000604  200000b4  080022fc  000040b4  2**0
                   ALLOC
- 11 .ARM.attributes 00000029  00000000  00000000  0000300c  2**0
+ 11 .ARM.attributes 00000029  00000000  00000000  0000400c  2**0
                   CONTENTS, READONLY
- 12 .debug_info   00006afc  00000000  00000000  00003035  2**0
+ 12 .debug_info   0000a8cd  00000000  00000000  00004035  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 13 .debug_abbrev 0000130c  00000000  00000000  00009b31  2**0
+ 13 .debug_abbrev 0000182d  00000000  00000000  0000e902  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 14 .debug_aranges 00000628  00000000  00000000  0000ae40  2**3
+ 14 .debug_aranges 00000a40  00000000  00000000  00010130  2**3
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 15 .debug_rnglists 000004b3  00000000  00000000  0000b468  2**0
+ 15 .debug_rnglists 000007ec  00000000  00000000  00010b70  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 16 .debug_macro  00014879  00000000  00000000  0000b91b  2**0
+ 16 .debug_macro  000154c6  00000000  00000000  0001135c  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 17 .debug_line   00007071  00000000  00000000  00020194  2**0
+ 17 .debug_line   0000a9dc  00000000  00000000  00026822  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 18 .debug_str    000819bb  00000000  00000000  00027205  2**0
+ 18 .debug_str    00088e84  00000000  00000000  000311fe  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 19 .comment      00000043  00000000  00000000  000a8bc0  2**0
+ 19 .comment      00000043  00000000  00000000  000ba082  2**0
                   CONTENTS, READONLY
- 20 .debug_frame  0000184c  00000000  00000000  000a8c04  2**2
+ 20 .debug_frame  00002ae8  00000000  00000000  000ba0c8  2**2
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 21 .debug_line_str 00000069  00000000  00000000  000aa450  2**0
+ 21 .debug_line_str 00000069  00000000  00000000  000bcbb0  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
 
 Disassembly of section .text:
@@ -64,7 +64,7 @@ Disassembly of section .text:
  8000152:	bd10      	pop	{r4, pc}
  8000154:	2000000c 	.word	0x2000000c
  8000158:	00000000 	.word	0x00000000
- 800015c:	08001da0 	.word	0x08001da0
+ 800015c:	080022a4 	.word	0x080022a4
 
 08000160 <frame_dummy>:
  8000160:	b508      	push	{r3, lr}
@@ -76,7 +76,7 @@ Disassembly of section .text:
  800016e:	bd08      	pop	{r3, pc}
  8000170:	00000000 	.word	0x00000000
  8000174:	20000010 	.word	0x20000010
- 8000178:	08001da0 	.word	0x08001da0
+ 8000178:	080022a4 	.word	0x080022a4
 
 0800017c <__aeabi_uldivmod>:
  800017c:	b953      	cbnz	r3, 8000194 <__aeabi_uldivmod+0x18>
@@ -386,4451 +386,5440 @@ int main(void)
 
   /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
   HAL_Init();
- 80004b6:	f000 f9e0 	bl	800087a <HAL_Init>
+ 80004b6:	f000 fa56 	bl	8000966 <HAL_Init>
   /* USER CODE BEGIN Init */
 
   /* USER CODE END Init */
 
   /* Configure the system clock */
   SystemClock_Config();
- 80004ba:	f000 f80d 	bl	80004d8 <SystemClock_Config>
+ 80004ba:	f000 f81d 	bl	80004f8 <SystemClock_Config>
   /* USER CODE BEGIN SysInit */
 
   /* USER CODE END SysInit */
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
- 80004be:	f000 f883 	bl	80005c8 <MX_GPIO_Init>
+ 80004be:	f000 f8c1 	bl	8000644 <MX_GPIO_Init>
   MX_USART2_UART_Init();
- 80004c2:	f000 f857 	bl	8000574 <MX_USART2_UART_Init>
+ 80004c2:	f000 f895 	bl	80005f0 <MX_USART2_UART_Init>
+  MX_TIM6_Init();
+ 80004c6:	f000 f85d 	bl	8000584 <MX_TIM6_Init>
   /* USER CODE BEGIN 2 */
 
   // Allume la led V1
   //*((uint32_t *)0x40020014) |= (1 << 5);
 
   uint32_t bouton_bleu = 0;
- 80004c6:	2300      	movs	r3, #0
- 80004c8:	60fb      	str	r3, [r7, #12]
-  uint32_t led = 0;
  80004ca:	2300      	movs	r3, #0
- 80004cc:	60bb      	str	r3, [r7, #8]
-  uint8_t v = 0;
+ 80004cc:	60fb      	str	r3, [r7, #12]
+  uint32_t led = 0;
  80004ce:	2300      	movs	r3, #0
- 80004d0:	71fb      	strb	r3, [r7, #7]
-  /* USER CODE END 2 */
+ 80004d0:	60bb      	str	r3, [r7, #8]
+  uint8_t v = 0;
+ 80004d2:	2300      	movs	r3, #0
+ 80004d4:	71fb      	strb	r3, [r7, #7]
 
   /* Infinite loop */
   /* USER CODE BEGIN WHILE */
-  while (1)
- 80004d2:	bf00      	nop
- 80004d4:	e7fd      	b.n	80004d2 <main+0x22>
-	...
 
-080004d8 <SystemClock_Config>:
+  //status_bouton = *((uint32_t*)0x40020810);
+  TIM6->DIER |= 1<<0;
+ 80004d6:	4b07      	ldr	r3, [pc, #28]	@ (80004f4 <main+0x44>)
+ 80004d8:	68db      	ldr	r3, [r3, #12]
+ 80004da:	4a06      	ldr	r2, [pc, #24]	@ (80004f4 <main+0x44>)
+ 80004dc:	f043 0301 	orr.w	r3, r3, #1
+ 80004e0:	60d3      	str	r3, [r2, #12]
+  TIM6->CR1 |= 1<<0;
+ 80004e2:	4b04      	ldr	r3, [pc, #16]	@ (80004f4 <main+0x44>)
+ 80004e4:	681b      	ldr	r3, [r3, #0]
+ 80004e6:	4a03      	ldr	r2, [pc, #12]	@ (80004f4 <main+0x44>)
+ 80004e8:	f043 0301 	orr.w	r3, r3, #1
+ 80004ec:	6013      	str	r3, [r2, #0]
+  while (1)
+ 80004ee:	bf00      	nop
+ 80004f0:	e7fd      	b.n	80004ee <main+0x3e>
+ 80004f2:	bf00      	nop
+ 80004f4:	40001000 	.word	0x40001000
+
+080004f8 <SystemClock_Config>:
 /**
   * @brief System Clock Configuration
   * @retval None
   */
 void SystemClock_Config(void)
 {
- 80004d8:	b580      	push	{r7, lr}
- 80004da:	b092      	sub	sp, #72	@ 0x48
- 80004dc:	af00      	add	r7, sp, #0
+ 80004f8:	b580      	push	{r7, lr}
+ 80004fa:	b092      	sub	sp, #72	@ 0x48
+ 80004fc:	af00      	add	r7, sp, #0
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 80004de:	f107 0314 	add.w	r3, r7, #20
- 80004e2:	2234      	movs	r2, #52	@ 0x34
- 80004e4:	2100      	movs	r1, #0
- 80004e6:	4618      	mov	r0, r3
- 80004e8:	f001 fc2e 	bl	8001d48 <memset>
+ 80004fe:	f107 0314 	add.w	r3, r7, #20
+ 8000502:	2234      	movs	r2, #52	@ 0x34
+ 8000504:	2100      	movs	r1, #0
+ 8000506:	4618      	mov	r0, r3
+ 8000508:	f001 fea0 	bl	800224c <memset>
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 80004ec:	463b      	mov	r3, r7
- 80004ee:	2200      	movs	r2, #0
- 80004f0:	601a      	str	r2, [r3, #0]
- 80004f2:	605a      	str	r2, [r3, #4]
- 80004f4:	609a      	str	r2, [r3, #8]
- 80004f6:	60da      	str	r2, [r3, #12]
- 80004f8:	611a      	str	r2, [r3, #16]
+ 800050c:	463b      	mov	r3, r7
+ 800050e:	2200      	movs	r2, #0
+ 8000510:	601a      	str	r2, [r3, #0]
+ 8000512:	605a      	str	r2, [r3, #4]
+ 8000514:	609a      	str	r2, [r3, #8]
+ 8000516:	60da      	str	r2, [r3, #12]
+ 8000518:	611a      	str	r2, [r3, #16]
 
   /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
- 80004fa:	4b1d      	ldr	r3, [pc, #116]	@ (8000570 <SystemClock_Config+0x98>)
- 80004fc:	681b      	ldr	r3, [r3, #0]
- 80004fe:	f423 53c0 	bic.w	r3, r3, #6144	@ 0x1800
- 8000502:	4a1b      	ldr	r2, [pc, #108]	@ (8000570 <SystemClock_Config+0x98>)
- 8000504:	f443 6300 	orr.w	r3, r3, #2048	@ 0x800
- 8000508:	6013      	str	r3, [r2, #0]
+ 800051a:	4b19      	ldr	r3, [pc, #100]	@ (8000580 <SystemClock_Config+0x88>)
+ 800051c:	681b      	ldr	r3, [r3, #0]
+ 800051e:	f423 53c0 	bic.w	r3, r3, #6144	@ 0x1800
+ 8000522:	4a17      	ldr	r2, [pc, #92]	@ (8000580 <SystemClock_Config+0x88>)
+ 8000524:	f443 6300 	orr.w	r3, r3, #2048	@ 0x800
+ 8000528:	6013      	str	r3, [r2, #0]
 
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 800050a:	2302      	movs	r3, #2
- 800050c:	617b      	str	r3, [r7, #20]
+ 800052a:	2302      	movs	r3, #2
+ 800052c:	617b      	str	r3, [r7, #20]
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 800050e:	2301      	movs	r3, #1
- 8000510:	623b      	str	r3, [r7, #32]
+ 800052e:	2301      	movs	r3, #1
+ 8000530:	623b      	str	r3, [r7, #32]
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 8000512:	2310      	movs	r3, #16
- 8000514:	627b      	str	r3, [r7, #36]	@ 0x24
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- 8000516:	2302      	movs	r3, #2
- 8000518:	63bb      	str	r3, [r7, #56]	@ 0x38
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- 800051a:	2300      	movs	r3, #0
- 800051c:	63fb      	str	r3, [r7, #60]	@ 0x3c
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
- 800051e:	f44f 2300 	mov.w	r3, #524288	@ 0x80000
- 8000522:	643b      	str	r3, [r7, #64]	@ 0x40
-  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
- 8000524:	f44f 0300 	mov.w	r3, #8388608	@ 0x800000
- 8000528:	647b      	str	r3, [r7, #68]	@ 0x44
+ 8000532:	2310      	movs	r3, #16
+ 8000534:	627b      	str	r3, [r7, #36]	@ 0x24
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ 8000536:	2300      	movs	r3, #0
+ 8000538:	63bb      	str	r3, [r7, #56]	@ 0x38
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 800052a:	f107 0314 	add.w	r3, r7, #20
- 800052e:	4618      	mov	r0, r3
- 8000530:	f000 fce0 	bl	8000ef4 <HAL_RCC_OscConfig>
- 8000534:	4603      	mov	r3, r0
- 8000536:	2b00      	cmp	r3, #0
- 8000538:	d001      	beq.n	800053e <SystemClock_Config+0x66>
+ 800053a:	f107 0314 	add.w	r3, r7, #20
+ 800053e:	4618      	mov	r0, r3
+ 8000540:	f000 fd4e 	bl	8000fe0 <HAL_RCC_OscConfig>
+ 8000544:	4603      	mov	r3, r0
+ 8000546:	2b00      	cmp	r3, #0
+ 8000548:	d001      	beq.n	800054e <SystemClock_Config+0x56>
   {
     Error_Handler();
- 800053a:	f000 f8c5 	bl	80006c8 <Error_Handler>
+ 800054a:	f000 f8fb 	bl	8000744 <Error_Handler>
   }
 
   /** Initializes the CPU, AHB and APB buses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 800053e:	230f      	movs	r3, #15
- 8000540:	603b      	str	r3, [r7, #0]
+ 800054e:	230f      	movs	r3, #15
+ 8000550:	603b      	str	r3, [r7, #0]
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- 8000542:	2303      	movs	r3, #3
- 8000544:	607b      	str	r3, [r7, #4]
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ 8000552:	2301      	movs	r3, #1
+ 8000554:	607b      	str	r3, [r7, #4]
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000546:	2300      	movs	r3, #0
- 8000548:	60bb      	str	r3, [r7, #8]
+ 8000556:	2300      	movs	r3, #0
+ 8000558:	60bb      	str	r3, [r7, #8]
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 800054a:	2300      	movs	r3, #0
- 800054c:	60fb      	str	r3, [r7, #12]
+ 800055a:	2300      	movs	r3, #0
+ 800055c:	60fb      	str	r3, [r7, #12]
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 800054e:	2300      	movs	r3, #0
- 8000550:	613b      	str	r3, [r7, #16]
+ 800055e:	2300      	movs	r3, #0
+ 8000560:	613b      	str	r3, [r7, #16]
 
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
- 8000552:	463b      	mov	r3, r7
- 8000554:	2101      	movs	r1, #1
- 8000556:	4618      	mov	r0, r3
- 8000558:	f000 fffc 	bl	8001554 <HAL_RCC_ClockConfig>
- 800055c:	4603      	mov	r3, r0
- 800055e:	2b00      	cmp	r3, #0
- 8000560:	d001      	beq.n	8000566 <SystemClock_Config+0x8e>
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ 8000562:	463b      	mov	r3, r7
+ 8000564:	2100      	movs	r1, #0
+ 8000566:	4618      	mov	r0, r3
+ 8000568:	f001 f86a 	bl	8001640 <HAL_RCC_ClockConfig>
+ 800056c:	4603      	mov	r3, r0
+ 800056e:	2b00      	cmp	r3, #0
+ 8000570:	d001      	beq.n	8000576 <SystemClock_Config+0x7e>
   {
     Error_Handler();
- 8000562:	f000 f8b1 	bl	80006c8 <Error_Handler>
+ 8000572:	f000 f8e7 	bl	8000744 <Error_Handler>
   }
 }
- 8000566:	bf00      	nop
- 8000568:	3748      	adds	r7, #72	@ 0x48
- 800056a:	46bd      	mov	sp, r7
- 800056c:	bd80      	pop	{r7, pc}
- 800056e:	bf00      	nop
- 8000570:	40007000 	.word	0x40007000
+ 8000576:	bf00      	nop
+ 8000578:	3748      	adds	r7, #72	@ 0x48
+ 800057a:	46bd      	mov	sp, r7
+ 800057c:	bd80      	pop	{r7, pc}
+ 800057e:	bf00      	nop
+ 8000580:	40007000 	.word	0x40007000
 
-08000574 <MX_USART2_UART_Init>:
+08000584 <MX_TIM6_Init>:
+  * @brief TIM6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM6_Init(void)
+{
+ 8000584:	b580      	push	{r7, lr}
+ 8000586:	b082      	sub	sp, #8
+ 8000588:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN TIM6_Init 0 */
+
+  /* USER CODE END TIM6_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 800058a:	463b      	mov	r3, r7
+ 800058c:	2200      	movs	r2, #0
+ 800058e:	601a      	str	r2, [r3, #0]
+ 8000590:	605a      	str	r2, [r3, #4]
+
+  /* USER CODE BEGIN TIM6_Init 1 */
+
+  /* USER CODE END TIM6_Init 1 */
+  htim6.Instance = TIM6;
+ 8000592:	4b15      	ldr	r3, [pc, #84]	@ (80005e8 <MX_TIM6_Init+0x64>)
+ 8000594:	4a15      	ldr	r2, [pc, #84]	@ (80005ec <MX_TIM6_Init+0x68>)
+ 8000596:	601a      	str	r2, [r3, #0]
+  htim6.Init.Prescaler = 16000-1;
+ 8000598:	4b13      	ldr	r3, [pc, #76]	@ (80005e8 <MX_TIM6_Init+0x64>)
+ 800059a:	f643 627f 	movw	r2, #15999	@ 0x3e7f
+ 800059e:	605a      	str	r2, [r3, #4]
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 80005a0:	4b11      	ldr	r3, [pc, #68]	@ (80005e8 <MX_TIM6_Init+0x64>)
+ 80005a2:	2200      	movs	r2, #0
+ 80005a4:	609a      	str	r2, [r3, #8]
+  htim6.Init.Period = 1000-1;
+ 80005a6:	4b10      	ldr	r3, [pc, #64]	@ (80005e8 <MX_TIM6_Init+0x64>)
+ 80005a8:	f240 32e7 	movw	r2, #999	@ 0x3e7
+ 80005ac:	60da      	str	r2, [r3, #12]
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 80005ae:	4b0e      	ldr	r3, [pc, #56]	@ (80005e8 <MX_TIM6_Init+0x64>)
+ 80005b0:	2200      	movs	r2, #0
+ 80005b2:	615a      	str	r2, [r3, #20]
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
+ 80005b4:	480c      	ldr	r0, [pc, #48]	@ (80005e8 <MX_TIM6_Init+0x64>)
+ 80005b6:	f001 fb09 	bl	8001bcc <HAL_TIM_Base_Init>
+ 80005ba:	4603      	mov	r3, r0
+ 80005bc:	2b00      	cmp	r3, #0
+ 80005be:	d001      	beq.n	80005c4 <MX_TIM6_Init+0x40>
+  {
+    Error_Handler();
+ 80005c0:	f000 f8c0 	bl	8000744 <Error_Handler>
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 80005c4:	2300      	movs	r3, #0
+ 80005c6:	603b      	str	r3, [r7, #0]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 80005c8:	2300      	movs	r3, #0
+ 80005ca:	607b      	str	r3, [r7, #4]
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
+ 80005cc:	463b      	mov	r3, r7
+ 80005ce:	4619      	mov	r1, r3
+ 80005d0:	4805      	ldr	r0, [pc, #20]	@ (80005e8 <MX_TIM6_Init+0x64>)
+ 80005d2:	f001 fca9 	bl	8001f28 <HAL_TIMEx_MasterConfigSynchronization>
+ 80005d6:	4603      	mov	r3, r0
+ 80005d8:	2b00      	cmp	r3, #0
+ 80005da:	d001      	beq.n	80005e0 <MX_TIM6_Init+0x5c>
+  {
+    Error_Handler();
+ 80005dc:	f000 f8b2 	bl	8000744 <Error_Handler>
+  }
+  /* USER CODE BEGIN TIM6_Init 2 */
+
+  /* USER CODE END TIM6_Init 2 */
+
+}
+ 80005e0:	bf00      	nop
+ 80005e2:	3708      	adds	r7, #8
+ 80005e4:	46bd      	mov	sp, r7
+ 80005e6:	bd80      	pop	{r7, pc}
+ 80005e8:	20000028 	.word	0x20000028
+ 80005ec:	40001000 	.word	0x40001000
+
+080005f0 <MX_USART2_UART_Init>:
   * @brief USART2 Initialization Function
   * @param None
   * @retval None
   */
 static void MX_USART2_UART_Init(void)
 {
- 8000574:	b580      	push	{r7, lr}
- 8000576:	af00      	add	r7, sp, #0
+ 80005f0:	b580      	push	{r7, lr}
+ 80005f2:	af00      	add	r7, sp, #0
   /* USER CODE END USART2_Init 0 */
 
   /* USER CODE BEGIN USART2_Init 1 */
 
   /* USER CODE END USART2_Init 1 */
   huart2.Instance = USART2;
- 8000578:	4b11      	ldr	r3, [pc, #68]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 800057a:	4a12      	ldr	r2, [pc, #72]	@ (80005c4 <MX_USART2_UART_Init+0x50>)
- 800057c:	601a      	str	r2, [r3, #0]
+ 80005f4:	4b11      	ldr	r3, [pc, #68]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 80005f6:	4a12      	ldr	r2, [pc, #72]	@ (8000640 <MX_USART2_UART_Init+0x50>)
+ 80005f8:	601a      	str	r2, [r3, #0]
   huart2.Init.BaudRate = 115200;
- 800057e:	4b10      	ldr	r3, [pc, #64]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 8000580:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
- 8000584:	605a      	str	r2, [r3, #4]
+ 80005fa:	4b10      	ldr	r3, [pc, #64]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 80005fc:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
+ 8000600:	605a      	str	r2, [r3, #4]
   huart2.Init.WordLength = UART_WORDLENGTH_8B;
- 8000586:	4b0e      	ldr	r3, [pc, #56]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 8000588:	2200      	movs	r2, #0
- 800058a:	609a      	str	r2, [r3, #8]
+ 8000602:	4b0e      	ldr	r3, [pc, #56]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 8000604:	2200      	movs	r2, #0
+ 8000606:	609a      	str	r2, [r3, #8]
   huart2.Init.StopBits = UART_STOPBITS_1;
- 800058c:	4b0c      	ldr	r3, [pc, #48]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 800058e:	2200      	movs	r2, #0
- 8000590:	60da      	str	r2, [r3, #12]
+ 8000608:	4b0c      	ldr	r3, [pc, #48]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 800060a:	2200      	movs	r2, #0
+ 800060c:	60da      	str	r2, [r3, #12]
   huart2.Init.Parity = UART_PARITY_NONE;
- 8000592:	4b0b      	ldr	r3, [pc, #44]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 8000594:	2200      	movs	r2, #0
- 8000596:	611a      	str	r2, [r3, #16]
+ 800060e:	4b0b      	ldr	r3, [pc, #44]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 8000610:	2200      	movs	r2, #0
+ 8000612:	611a      	str	r2, [r3, #16]
   huart2.Init.Mode = UART_MODE_TX_RX;
- 8000598:	4b09      	ldr	r3, [pc, #36]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 800059a:	220c      	movs	r2, #12
- 800059c:	615a      	str	r2, [r3, #20]
+ 8000614:	4b09      	ldr	r3, [pc, #36]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 8000616:	220c      	movs	r2, #12
+ 8000618:	615a      	str	r2, [r3, #20]
   huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 800059e:	4b08      	ldr	r3, [pc, #32]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 80005a0:	2200      	movs	r2, #0
- 80005a2:	619a      	str	r2, [r3, #24]
+ 800061a:	4b08      	ldr	r3, [pc, #32]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 800061c:	2200      	movs	r2, #0
+ 800061e:	619a      	str	r2, [r3, #24]
   huart2.Init.OverSampling = UART_OVERSAMPLING_16;
- 80005a4:	4b06      	ldr	r3, [pc, #24]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 80005a6:	2200      	movs	r2, #0
- 80005a8:	61da      	str	r2, [r3, #28]
+ 8000620:	4b06      	ldr	r3, [pc, #24]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 8000622:	2200      	movs	r2, #0
+ 8000624:	61da      	str	r2, [r3, #28]
   if (HAL_UART_Init(&huart2) != HAL_OK)
- 80005aa:	4805      	ldr	r0, [pc, #20]	@ (80005c0 <MX_USART2_UART_Init+0x4c>)
- 80005ac:	f001 fa98 	bl	8001ae0 <HAL_UART_Init>
- 80005b0:	4603      	mov	r3, r0
- 80005b2:	2b00      	cmp	r3, #0
- 80005b4:	d001      	beq.n	80005ba <MX_USART2_UART_Init+0x46>
+ 8000626:	4805      	ldr	r0, [pc, #20]	@ (800063c <MX_USART2_UART_Init+0x4c>)
+ 8000628:	f001 fcdc 	bl	8001fe4 <HAL_UART_Init>
+ 800062c:	4603      	mov	r3, r0
+ 800062e:	2b00      	cmp	r3, #0
+ 8000630:	d001      	beq.n	8000636 <MX_USART2_UART_Init+0x46>
   {
     Error_Handler();
- 80005b6:	f000 f887 	bl	80006c8 <Error_Handler>
+ 8000632:	f000 f887 	bl	8000744 <Error_Handler>
   }
   /* USER CODE BEGIN USART2_Init 2 */
 
   /* USER CODE END USART2_Init 2 */
 
 }
- 80005ba:	bf00      	nop
- 80005bc:	bd80      	pop	{r7, pc}
- 80005be:	bf00      	nop
- 80005c0:	20000028 	.word	0x20000028
- 80005c4:	40004400 	.word	0x40004400
+ 8000636:	bf00      	nop
+ 8000638:	bd80      	pop	{r7, pc}
+ 800063a:	bf00      	nop
+ 800063c:	20000068 	.word	0x20000068
+ 8000640:	40004400 	.word	0x40004400
 
-080005c8 <MX_GPIO_Init>:
+08000644 <MX_GPIO_Init>:
   * @brief GPIO Initialization Function
   * @param None
   * @retval None
   */
 static void MX_GPIO_Init(void)
 {
- 80005c8:	b580      	push	{r7, lr}
- 80005ca:	b08a      	sub	sp, #40	@ 0x28
- 80005cc:	af00      	add	r7, sp, #0
+ 8000644:	b580      	push	{r7, lr}
+ 8000646:	b08a      	sub	sp, #40	@ 0x28
+ 8000648:	af00      	add	r7, sp, #0
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80005ce:	f107 0314 	add.w	r3, r7, #20
- 80005d2:	2200      	movs	r2, #0
- 80005d4:	601a      	str	r2, [r3, #0]
- 80005d6:	605a      	str	r2, [r3, #4]
- 80005d8:	609a      	str	r2, [r3, #8]
- 80005da:	60da      	str	r2, [r3, #12]
- 80005dc:	611a      	str	r2, [r3, #16]
+ 800064a:	f107 0314 	add.w	r3, r7, #20
+ 800064e:	2200      	movs	r2, #0
+ 8000650:	601a      	str	r2, [r3, #0]
+ 8000652:	605a      	str	r2, [r3, #4]
+ 8000654:	609a      	str	r2, [r3, #8]
+ 8000656:	60da      	str	r2, [r3, #12]
+ 8000658:	611a      	str	r2, [r3, #16]
   /* USER CODE BEGIN MX_GPIO_Init_1 */
 
   /* USER CODE END MX_GPIO_Init_1 */
 
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOC_CLK_ENABLE();
- 80005de:	4b2e      	ldr	r3, [pc, #184]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 80005e0:	69db      	ldr	r3, [r3, #28]
- 80005e2:	4a2d      	ldr	r2, [pc, #180]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 80005e4:	f043 0304 	orr.w	r3, r3, #4
- 80005e8:	61d3      	str	r3, [r2, #28]
- 80005ea:	4b2b      	ldr	r3, [pc, #172]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 80005ec:	69db      	ldr	r3, [r3, #28]
- 80005ee:	f003 0304 	and.w	r3, r3, #4
- 80005f2:	613b      	str	r3, [r7, #16]
- 80005f4:	693b      	ldr	r3, [r7, #16]
+ 800065a:	4b2e      	ldr	r3, [pc, #184]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 800065c:	69db      	ldr	r3, [r3, #28]
+ 800065e:	4a2d      	ldr	r2, [pc, #180]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 8000660:	f043 0304 	orr.w	r3, r3, #4
+ 8000664:	61d3      	str	r3, [r2, #28]
+ 8000666:	4b2b      	ldr	r3, [pc, #172]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 8000668:	69db      	ldr	r3, [r3, #28]
+ 800066a:	f003 0304 	and.w	r3, r3, #4
+ 800066e:	613b      	str	r3, [r7, #16]
+ 8000670:	693b      	ldr	r3, [r7, #16]
   __HAL_RCC_GPIOH_CLK_ENABLE();
- 80005f6:	4b28      	ldr	r3, [pc, #160]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 80005f8:	69db      	ldr	r3, [r3, #28]
- 80005fa:	4a27      	ldr	r2, [pc, #156]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 80005fc:	f043 0320 	orr.w	r3, r3, #32
- 8000600:	61d3      	str	r3, [r2, #28]
- 8000602:	4b25      	ldr	r3, [pc, #148]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 8000604:	69db      	ldr	r3, [r3, #28]
- 8000606:	f003 0320 	and.w	r3, r3, #32
- 800060a:	60fb      	str	r3, [r7, #12]
- 800060c:	68fb      	ldr	r3, [r7, #12]
+ 8000672:	4b28      	ldr	r3, [pc, #160]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 8000674:	69db      	ldr	r3, [r3, #28]
+ 8000676:	4a27      	ldr	r2, [pc, #156]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 8000678:	f043 0320 	orr.w	r3, r3, #32
+ 800067c:	61d3      	str	r3, [r2, #28]
+ 800067e:	4b25      	ldr	r3, [pc, #148]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 8000680:	69db      	ldr	r3, [r3, #28]
+ 8000682:	f003 0320 	and.w	r3, r3, #32
+ 8000686:	60fb      	str	r3, [r7, #12]
+ 8000688:	68fb      	ldr	r3, [r7, #12]
   __HAL_RCC_GPIOA_CLK_ENABLE();
- 800060e:	4b22      	ldr	r3, [pc, #136]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 8000610:	69db      	ldr	r3, [r3, #28]
- 8000612:	4a21      	ldr	r2, [pc, #132]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 8000614:	f043 0301 	orr.w	r3, r3, #1
- 8000618:	61d3      	str	r3, [r2, #28]
- 800061a:	4b1f      	ldr	r3, [pc, #124]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 800061c:	69db      	ldr	r3, [r3, #28]
- 800061e:	f003 0301 	and.w	r3, r3, #1
- 8000622:	60bb      	str	r3, [r7, #8]
- 8000624:	68bb      	ldr	r3, [r7, #8]
+ 800068a:	4b22      	ldr	r3, [pc, #136]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 800068c:	69db      	ldr	r3, [r3, #28]
+ 800068e:	4a21      	ldr	r2, [pc, #132]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 8000690:	f043 0301 	orr.w	r3, r3, #1
+ 8000694:	61d3      	str	r3, [r2, #28]
+ 8000696:	4b1f      	ldr	r3, [pc, #124]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 8000698:	69db      	ldr	r3, [r3, #28]
+ 800069a:	f003 0301 	and.w	r3, r3, #1
+ 800069e:	60bb      	str	r3, [r7, #8]
+ 80006a0:	68bb      	ldr	r3, [r7, #8]
   __HAL_RCC_GPIOB_CLK_ENABLE();
- 8000626:	4b1c      	ldr	r3, [pc, #112]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 8000628:	69db      	ldr	r3, [r3, #28]
- 800062a:	4a1b      	ldr	r2, [pc, #108]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 800062c:	f043 0302 	orr.w	r3, r3, #2
- 8000630:	61d3      	str	r3, [r2, #28]
- 8000632:	4b19      	ldr	r3, [pc, #100]	@ (8000698 <MX_GPIO_Init+0xd0>)
- 8000634:	69db      	ldr	r3, [r3, #28]
- 8000636:	f003 0302 	and.w	r3, r3, #2
- 800063a:	607b      	str	r3, [r7, #4]
- 800063c:	687b      	ldr	r3, [r7, #4]
+ 80006a2:	4b1c      	ldr	r3, [pc, #112]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 80006a4:	69db      	ldr	r3, [r3, #28]
+ 80006a6:	4a1b      	ldr	r2, [pc, #108]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 80006a8:	f043 0302 	orr.w	r3, r3, #2
+ 80006ac:	61d3      	str	r3, [r2, #28]
+ 80006ae:	4b19      	ldr	r3, [pc, #100]	@ (8000714 <MX_GPIO_Init+0xd0>)
+ 80006b0:	69db      	ldr	r3, [r3, #28]
+ 80006b2:	f003 0302 	and.w	r3, r3, #2
+ 80006b6:	607b      	str	r3, [r7, #4]
+ 80006b8:	687b      	ldr	r3, [r7, #4]
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
- 800063e:	2200      	movs	r2, #0
- 8000640:	2120      	movs	r1, #32
- 8000642:	4816      	ldr	r0, [pc, #88]	@ (800069c <MX_GPIO_Init+0xd4>)
- 8000644:	f000 fc26 	bl	8000e94 <HAL_GPIO_WritePin>
+ 80006ba:	2200      	movs	r2, #0
+ 80006bc:	2120      	movs	r1, #32
+ 80006be:	4816      	ldr	r0, [pc, #88]	@ (8000718 <MX_GPIO_Init+0xd4>)
+ 80006c0:	f000 fc5e 	bl	8000f80 <HAL_GPIO_WritePin>
 
   /*Configure GPIO pin : PC13 */
   GPIO_InitStruct.Pin = GPIO_PIN_13;
- 8000648:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
- 800064c:	617b      	str	r3, [r7, #20]
+ 80006c4:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
+ 80006c8:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
- 800064e:	f44f 1304 	mov.w	r3, #2162688	@ 0x210000
- 8000652:	61bb      	str	r3, [r7, #24]
+ 80006ca:	f44f 1304 	mov.w	r3, #2162688	@ 0x210000
+ 80006ce:	61bb      	str	r3, [r7, #24]
   GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8000654:	2300      	movs	r3, #0
- 8000656:	61fb      	str	r3, [r7, #28]
+ 80006d0:	2300      	movs	r3, #0
+ 80006d2:	61fb      	str	r3, [r7, #28]
   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8000658:	f107 0314 	add.w	r3, r7, #20
- 800065c:	4619      	mov	r1, r3
- 800065e:	4810      	ldr	r0, [pc, #64]	@ (80006a0 <MX_GPIO_Init+0xd8>)
- 8000660:	f000 fa88 	bl	8000b74 <HAL_GPIO_Init>
+ 80006d4:	f107 0314 	add.w	r3, r7, #20
+ 80006d8:	4619      	mov	r1, r3
+ 80006da:	4810      	ldr	r0, [pc, #64]	@ (800071c <MX_GPIO_Init+0xd8>)
+ 80006dc:	f000 fac0 	bl	8000c60 <HAL_GPIO_Init>
 
   /*Configure GPIO pin : LD2_Pin */
   GPIO_InitStruct.Pin = LD2_Pin;
- 8000664:	2320      	movs	r3, #32
- 8000666:	617b      	str	r3, [r7, #20]
+ 80006e0:	2320      	movs	r3, #32
+ 80006e2:	617b      	str	r3, [r7, #20]
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 8000668:	2301      	movs	r3, #1
- 800066a:	61bb      	str	r3, [r7, #24]
+ 80006e4:	2301      	movs	r3, #1
+ 80006e6:	61bb      	str	r3, [r7, #24]
   GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800066c:	2300      	movs	r3, #0
- 800066e:	61fb      	str	r3, [r7, #28]
+ 80006e8:	2300      	movs	r3, #0
+ 80006ea:	61fb      	str	r3, [r7, #28]
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8000670:	2300      	movs	r3, #0
- 8000672:	623b      	str	r3, [r7, #32]
+ 80006ec:	2300      	movs	r3, #0
+ 80006ee:	623b      	str	r3, [r7, #32]
   HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
- 8000674:	f107 0314 	add.w	r3, r7, #20
- 8000678:	4619      	mov	r1, r3
- 800067a:	4808      	ldr	r0, [pc, #32]	@ (800069c <MX_GPIO_Init+0xd4>)
- 800067c:	f000 fa7a 	bl	8000b74 <HAL_GPIO_Init>
+ 80006f0:	f107 0314 	add.w	r3, r7, #20
+ 80006f4:	4619      	mov	r1, r3
+ 80006f6:	4808      	ldr	r0, [pc, #32]	@ (8000718 <MX_GPIO_Init+0xd4>)
+ 80006f8:	f000 fab2 	bl	8000c60 <HAL_GPIO_Init>
 
   /* EXTI interrupt init*/
   HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
- 8000680:	2200      	movs	r2, #0
- 8000682:	2100      	movs	r1, #0
- 8000684:	2028      	movs	r0, #40	@ 0x28
- 8000686:	f000 fa3e 	bl	8000b06 <HAL_NVIC_SetPriority>
+ 80006fc:	2200      	movs	r2, #0
+ 80006fe:	2100      	movs	r1, #0
+ 8000700:	2028      	movs	r0, #40	@ 0x28
+ 8000702:	f000 fa76 	bl	8000bf2 <HAL_NVIC_SetPriority>
   HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
- 800068a:	2028      	movs	r0, #40	@ 0x28
- 800068c:	f000 fa57 	bl	8000b3e <HAL_NVIC_EnableIRQ>
+ 8000706:	2028      	movs	r0, #40	@ 0x28
+ 8000708:	f000 fa8f 	bl	8000c2a <HAL_NVIC_EnableIRQ>
 
   /* USER CODE BEGIN MX_GPIO_Init_2 */
 
   /* USER CODE END MX_GPIO_Init_2 */
 }
- 8000690:	bf00      	nop
- 8000692:	3728      	adds	r7, #40	@ 0x28
- 8000694:	46bd      	mov	sp, r7
- 8000696:	bd80      	pop	{r7, pc}
- 8000698:	40023800 	.word	0x40023800
- 800069c:	40020000 	.word	0x40020000
- 80006a0:	40020800 	.word	0x40020800
+ 800070c:	bf00      	nop
+ 800070e:	3728      	adds	r7, #40	@ 0x28
+ 8000710:	46bd      	mov	sp, r7
+ 8000712:	bd80      	pop	{r7, pc}
+ 8000714:	40023800 	.word	0x40023800
+ 8000718:	40020000 	.word	0x40020000
+ 800071c:	40020800 	.word	0x40020800
 
-080006a4 <HAL_GPIO_EXTI_Callback>:
+08000720 <HAL_GPIO_EXTI_Callback>:
 
 /* USER CODE BEGIN 4 */
 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
- 80006a4:	b480      	push	{r7}
- 80006a6:	b083      	sub	sp, #12
- 80006a8:	af00      	add	r7, sp, #0
- 80006aa:	4603      	mov	r3, r0
- 80006ac:	80fb      	strh	r3, [r7, #6]
+ 8000720:	b480      	push	{r7}
+ 8000722:	b083      	sub	sp, #12
+ 8000724:	af00      	add	r7, sp, #0
+ 8000726:	4603      	mov	r3, r0
+ 8000728:	80fb      	strh	r3, [r7, #6]
 	  //*(volatile uint32_t *)0x40020014 ^= (1 << 5);
 	  GPIOA->ODR ^= (1 << 5);
- 80006ae:	4b05      	ldr	r3, [pc, #20]	@ (80006c4 <HAL_GPIO_EXTI_Callback+0x20>)
- 80006b0:	695b      	ldr	r3, [r3, #20]
- 80006b2:	4a04      	ldr	r2, [pc, #16]	@ (80006c4 <HAL_GPIO_EXTI_Callback+0x20>)
- 80006b4:	f083 0320 	eor.w	r3, r3, #32
- 80006b8:	6153      	str	r3, [r2, #20]
+ 800072a:	4b05      	ldr	r3, [pc, #20]	@ (8000740 <HAL_GPIO_EXTI_Callback+0x20>)
+ 800072c:	695b      	ldr	r3, [r3, #20]
+ 800072e:	4a04      	ldr	r2, [pc, #16]	@ (8000740 <HAL_GPIO_EXTI_Callback+0x20>)
+ 8000730:	f083 0320 	eor.w	r3, r3, #32
+ 8000734:	6153      	str	r3, [r2, #20]
 }
- 80006ba:	bf00      	nop
- 80006bc:	370c      	adds	r7, #12
- 80006be:	46bd      	mov	sp, r7
- 80006c0:	bc80      	pop	{r7}
- 80006c2:	4770      	bx	lr
- 80006c4:	40020000 	.word	0x40020000
+ 8000736:	bf00      	nop
+ 8000738:	370c      	adds	r7, #12
+ 800073a:	46bd      	mov	sp, r7
+ 800073c:	bc80      	pop	{r7}
+ 800073e:	4770      	bx	lr
+ 8000740:	40020000 	.word	0x40020000
 
-080006c8 <Error_Handler>:
+08000744 <Error_Handler>:
 /**
   * @brief  This function is executed in case of error occurrence.
   * @retval None
   */
 void Error_Handler(void)
 {
- 80006c8:	b480      	push	{r7}
- 80006ca:	af00      	add	r7, sp, #0
+ 8000744:	b480      	push	{r7}
+ 8000746:	af00      	add	r7, sp, #0
   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __disable_irq(void)
 {
   __ASM volatile ("cpsid i" : : : "memory");
- 80006cc:	b672      	cpsid	i
+ 8000748:	b672      	cpsid	i
 }
- 80006ce:	bf00      	nop
+ 800074a:	bf00      	nop
   /* USER CODE BEGIN Error_Handler_Debug */
   /* User can add his own implementation to report the HAL error return state */
   __disable_irq();
   while (1)
- 80006d0:	bf00      	nop
- 80006d2:	e7fd      	b.n	80006d0 <Error_Handler+0x8>
+ 800074c:	bf00      	nop
+ 800074e:	e7fd      	b.n	800074c <Error_Handler+0x8>
 
-080006d4 <HAL_MspInit>:
+08000750 <HAL_MspInit>:
 /* USER CODE END 0 */
 /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
 {
- 80006d4:	b580      	push	{r7, lr}
- 80006d6:	b084      	sub	sp, #16
- 80006d8:	af00      	add	r7, sp, #0
+ 8000750:	b580      	push	{r7, lr}
+ 8000752:	b084      	sub	sp, #16
+ 8000754:	af00      	add	r7, sp, #0
 
   /* USER CODE BEGIN MspInit 0 */
 
   /* USER CODE END MspInit 0 */
 
   __HAL_RCC_COMP_CLK_ENABLE();
- 80006da:	4b15      	ldr	r3, [pc, #84]	@ (8000730 <HAL_MspInit+0x5c>)
- 80006dc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 80006de:	4a14      	ldr	r2, [pc, #80]	@ (8000730 <HAL_MspInit+0x5c>)
- 80006e0:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
- 80006e4:	6253      	str	r3, [r2, #36]	@ 0x24
- 80006e6:	4b12      	ldr	r3, [pc, #72]	@ (8000730 <HAL_MspInit+0x5c>)
- 80006e8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 80006ea:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
- 80006ee:	60fb      	str	r3, [r7, #12]
- 80006f0:	68fb      	ldr	r3, [r7, #12]
+ 8000756:	4b15      	ldr	r3, [pc, #84]	@ (80007ac <HAL_MspInit+0x5c>)
+ 8000758:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800075a:	4a14      	ldr	r2, [pc, #80]	@ (80007ac <HAL_MspInit+0x5c>)
+ 800075c:	f043 4300 	orr.w	r3, r3, #2147483648	@ 0x80000000
+ 8000760:	6253      	str	r3, [r2, #36]	@ 0x24
+ 8000762:	4b12      	ldr	r3, [pc, #72]	@ (80007ac <HAL_MspInit+0x5c>)
+ 8000764:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8000766:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
+ 800076a:	60fb      	str	r3, [r7, #12]
+ 800076c:	68fb      	ldr	r3, [r7, #12]
   __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80006f2:	4b0f      	ldr	r3, [pc, #60]	@ (8000730 <HAL_MspInit+0x5c>)
- 80006f4:	6a1b      	ldr	r3, [r3, #32]
- 80006f6:	4a0e      	ldr	r2, [pc, #56]	@ (8000730 <HAL_MspInit+0x5c>)
- 80006f8:	f043 0301 	orr.w	r3, r3, #1
- 80006fc:	6213      	str	r3, [r2, #32]
- 80006fe:	4b0c      	ldr	r3, [pc, #48]	@ (8000730 <HAL_MspInit+0x5c>)
- 8000700:	6a1b      	ldr	r3, [r3, #32]
- 8000702:	f003 0301 	and.w	r3, r3, #1
- 8000706:	60bb      	str	r3, [r7, #8]
- 8000708:	68bb      	ldr	r3, [r7, #8]
+ 800076e:	4b0f      	ldr	r3, [pc, #60]	@ (80007ac <HAL_MspInit+0x5c>)
+ 8000770:	6a1b      	ldr	r3, [r3, #32]
+ 8000772:	4a0e      	ldr	r2, [pc, #56]	@ (80007ac <HAL_MspInit+0x5c>)
+ 8000774:	f043 0301 	orr.w	r3, r3, #1
+ 8000778:	6213      	str	r3, [r2, #32]
+ 800077a:	4b0c      	ldr	r3, [pc, #48]	@ (80007ac <HAL_MspInit+0x5c>)
+ 800077c:	6a1b      	ldr	r3, [r3, #32]
+ 800077e:	f003 0301 	and.w	r3, r3, #1
+ 8000782:	60bb      	str	r3, [r7, #8]
+ 8000784:	68bb      	ldr	r3, [r7, #8]
   __HAL_RCC_PWR_CLK_ENABLE();
- 800070a:	4b09      	ldr	r3, [pc, #36]	@ (8000730 <HAL_MspInit+0x5c>)
- 800070c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 800070e:	4a08      	ldr	r2, [pc, #32]	@ (8000730 <HAL_MspInit+0x5c>)
- 8000710:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
- 8000714:	6253      	str	r3, [r2, #36]	@ 0x24
- 8000716:	4b06      	ldr	r3, [pc, #24]	@ (8000730 <HAL_MspInit+0x5c>)
- 8000718:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 800071a:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 800071e:	607b      	str	r3, [r7, #4]
- 8000720:	687b      	ldr	r3, [r7, #4]
+ 8000786:	4b09      	ldr	r3, [pc, #36]	@ (80007ac <HAL_MspInit+0x5c>)
+ 8000788:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800078a:	4a08      	ldr	r2, [pc, #32]	@ (80007ac <HAL_MspInit+0x5c>)
+ 800078c:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 8000790:	6253      	str	r3, [r2, #36]	@ 0x24
+ 8000792:	4b06      	ldr	r3, [pc, #24]	@ (80007ac <HAL_MspInit+0x5c>)
+ 8000794:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8000796:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 800079a:	607b      	str	r3, [r7, #4]
+ 800079c:	687b      	ldr	r3, [r7, #4]
 
   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
- 8000722:	2007      	movs	r0, #7
- 8000724:	f000 f9e4 	bl	8000af0 <HAL_NVIC_SetPriorityGrouping>
+ 800079e:	2007      	movs	r0, #7
+ 80007a0:	f000 fa1c 	bl	8000bdc <HAL_NVIC_SetPriorityGrouping>
   /* System interrupt init*/
 
   /* USER CODE BEGIN MspInit 1 */
 
   /* USER CODE END MspInit 1 */
 }
- 8000728:	bf00      	nop
- 800072a:	3710      	adds	r7, #16
- 800072c:	46bd      	mov	sp, r7
- 800072e:	bd80      	pop	{r7, pc}
- 8000730:	40023800 	.word	0x40023800
+ 80007a4:	bf00      	nop
+ 80007a6:	3710      	adds	r7, #16
+ 80007a8:	46bd      	mov	sp, r7
+ 80007aa:	bd80      	pop	{r7, pc}
+ 80007ac:	40023800 	.word	0x40023800
 
-08000734 <HAL_UART_MspInit>:
+080007b0 <HAL_TIM_Base_MspInit>:
+  * This function configures the hardware resources used in this example
+  * @param htim_base: TIM_Base handle pointer
+  * @retval None
+  */
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+ 80007b0:	b580      	push	{r7, lr}
+ 80007b2:	b084      	sub	sp, #16
+ 80007b4:	af00      	add	r7, sp, #0
+ 80007b6:	6078      	str	r0, [r7, #4]
+  if(htim_base->Instance==TIM6)
+ 80007b8:	687b      	ldr	r3, [r7, #4]
+ 80007ba:	681b      	ldr	r3, [r3, #0]
+ 80007bc:	4a0d      	ldr	r2, [pc, #52]	@ (80007f4 <HAL_TIM_Base_MspInit+0x44>)
+ 80007be:	4293      	cmp	r3, r2
+ 80007c0:	d113      	bne.n	80007ea <HAL_TIM_Base_MspInit+0x3a>
+  {
+    /* USER CODE BEGIN TIM6_MspInit 0 */
+
+    /* USER CODE END TIM6_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM6_CLK_ENABLE();
+ 80007c2:	4b0d      	ldr	r3, [pc, #52]	@ (80007f8 <HAL_TIM_Base_MspInit+0x48>)
+ 80007c4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80007c6:	4a0c      	ldr	r2, [pc, #48]	@ (80007f8 <HAL_TIM_Base_MspInit+0x48>)
+ 80007c8:	f043 0310 	orr.w	r3, r3, #16
+ 80007cc:	6253      	str	r3, [r2, #36]	@ 0x24
+ 80007ce:	4b0a      	ldr	r3, [pc, #40]	@ (80007f8 <HAL_TIM_Base_MspInit+0x48>)
+ 80007d0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80007d2:	f003 0310 	and.w	r3, r3, #16
+ 80007d6:	60fb      	str	r3, [r7, #12]
+ 80007d8:	68fb      	ldr	r3, [r7, #12]
+    /* TIM6 interrupt Init */
+    HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
+ 80007da:	2200      	movs	r2, #0
+ 80007dc:	2100      	movs	r1, #0
+ 80007de:	202b      	movs	r0, #43	@ 0x2b
+ 80007e0:	f000 fa07 	bl	8000bf2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(TIM6_IRQn);
+ 80007e4:	202b      	movs	r0, #43	@ 0x2b
+ 80007e6:	f000 fa20 	bl	8000c2a <HAL_NVIC_EnableIRQ>
+
+    /* USER CODE END TIM6_MspInit 1 */
+
+  }
+
+}
+ 80007ea:	bf00      	nop
+ 80007ec:	3710      	adds	r7, #16
+ 80007ee:	46bd      	mov	sp, r7
+ 80007f0:	bd80      	pop	{r7, pc}
+ 80007f2:	bf00      	nop
+ 80007f4:	40001000 	.word	0x40001000
+ 80007f8:	40023800 	.word	0x40023800
+
+080007fc <HAL_UART_MspInit>:
   * This function configures the hardware resources used in this example
   * @param huart: UART handle pointer
   * @retval None
   */
 void HAL_UART_MspInit(UART_HandleTypeDef* huart)
 {
- 8000734:	b580      	push	{r7, lr}
- 8000736:	b08a      	sub	sp, #40	@ 0x28
- 8000738:	af00      	add	r7, sp, #0
- 800073a:	6078      	str	r0, [r7, #4]
+ 80007fc:	b580      	push	{r7, lr}
+ 80007fe:	b08a      	sub	sp, #40	@ 0x28
+ 8000800:	af00      	add	r7, sp, #0
+ 8000802:	6078      	str	r0, [r7, #4]
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800073c:	f107 0314 	add.w	r3, r7, #20
- 8000740:	2200      	movs	r2, #0
- 8000742:	601a      	str	r2, [r3, #0]
- 8000744:	605a      	str	r2, [r3, #4]
- 8000746:	609a      	str	r2, [r3, #8]
- 8000748:	60da      	str	r2, [r3, #12]
- 800074a:	611a      	str	r2, [r3, #16]
+ 8000804:	f107 0314 	add.w	r3, r7, #20
+ 8000808:	2200      	movs	r2, #0
+ 800080a:	601a      	str	r2, [r3, #0]
+ 800080c:	605a      	str	r2, [r3, #4]
+ 800080e:	609a      	str	r2, [r3, #8]
+ 8000810:	60da      	str	r2, [r3, #12]
+ 8000812:	611a      	str	r2, [r3, #16]
   if(huart->Instance==USART2)
- 800074c:	687b      	ldr	r3, [r7, #4]
- 800074e:	681b      	ldr	r3, [r3, #0]
- 8000750:	4a17      	ldr	r2, [pc, #92]	@ (80007b0 <HAL_UART_MspInit+0x7c>)
- 8000752:	4293      	cmp	r3, r2
- 8000754:	d127      	bne.n	80007a6 <HAL_UART_MspInit+0x72>
+ 8000814:	687b      	ldr	r3, [r7, #4]
+ 8000816:	681b      	ldr	r3, [r3, #0]
+ 8000818:	4a17      	ldr	r2, [pc, #92]	@ (8000878 <HAL_UART_MspInit+0x7c>)
+ 800081a:	4293      	cmp	r3, r2
+ 800081c:	d127      	bne.n	800086e <HAL_UART_MspInit+0x72>
   {
     /* USER CODE BEGIN USART2_MspInit 0 */
 
     /* USER CODE END USART2_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_USART2_CLK_ENABLE();
- 8000756:	4b17      	ldr	r3, [pc, #92]	@ (80007b4 <HAL_UART_MspInit+0x80>)
- 8000758:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 800075a:	4a16      	ldr	r2, [pc, #88]	@ (80007b4 <HAL_UART_MspInit+0x80>)
- 800075c:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
- 8000760:	6253      	str	r3, [r2, #36]	@ 0x24
- 8000762:	4b14      	ldr	r3, [pc, #80]	@ (80007b4 <HAL_UART_MspInit+0x80>)
- 8000764:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8000766:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 800076a:	613b      	str	r3, [r7, #16]
- 800076c:	693b      	ldr	r3, [r7, #16]
+ 800081e:	4b17      	ldr	r3, [pc, #92]	@ (800087c <HAL_UART_MspInit+0x80>)
+ 8000820:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8000822:	4a16      	ldr	r2, [pc, #88]	@ (800087c <HAL_UART_MspInit+0x80>)
+ 8000824:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 8000828:	6253      	str	r3, [r2, #36]	@ 0x24
+ 800082a:	4b14      	ldr	r3, [pc, #80]	@ (800087c <HAL_UART_MspInit+0x80>)
+ 800082c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800082e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8000832:	613b      	str	r3, [r7, #16]
+ 8000834:	693b      	ldr	r3, [r7, #16]
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
- 800076e:	4b11      	ldr	r3, [pc, #68]	@ (80007b4 <HAL_UART_MspInit+0x80>)
- 8000770:	69db      	ldr	r3, [r3, #28]
- 8000772:	4a10      	ldr	r2, [pc, #64]	@ (80007b4 <HAL_UART_MspInit+0x80>)
- 8000774:	f043 0301 	orr.w	r3, r3, #1
- 8000778:	61d3      	str	r3, [r2, #28]
- 800077a:	4b0e      	ldr	r3, [pc, #56]	@ (80007b4 <HAL_UART_MspInit+0x80>)
- 800077c:	69db      	ldr	r3, [r3, #28]
- 800077e:	f003 0301 	and.w	r3, r3, #1
- 8000782:	60fb      	str	r3, [r7, #12]
- 8000784:	68fb      	ldr	r3, [r7, #12]
+ 8000836:	4b11      	ldr	r3, [pc, #68]	@ (800087c <HAL_UART_MspInit+0x80>)
+ 8000838:	69db      	ldr	r3, [r3, #28]
+ 800083a:	4a10      	ldr	r2, [pc, #64]	@ (800087c <HAL_UART_MspInit+0x80>)
+ 800083c:	f043 0301 	orr.w	r3, r3, #1
+ 8000840:	61d3      	str	r3, [r2, #28]
+ 8000842:	4b0e      	ldr	r3, [pc, #56]	@ (800087c <HAL_UART_MspInit+0x80>)
+ 8000844:	69db      	ldr	r3, [r3, #28]
+ 8000846:	f003 0301 	and.w	r3, r3, #1
+ 800084a:	60fb      	str	r3, [r7, #12]
+ 800084c:	68fb      	ldr	r3, [r7, #12]
     /**USART2 GPIO Configuration
     PA2     ------> USART2_TX
     PA3     ------> USART2_RX
     */
     GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
- 8000786:	230c      	movs	r3, #12
- 8000788:	617b      	str	r3, [r7, #20]
+ 800084e:	230c      	movs	r3, #12
+ 8000850:	617b      	str	r3, [r7, #20]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800078a:	2302      	movs	r3, #2
- 800078c:	61bb      	str	r3, [r7, #24]
+ 8000852:	2302      	movs	r3, #2
+ 8000854:	61bb      	str	r3, [r7, #24]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800078e:	2300      	movs	r3, #0
- 8000790:	61fb      	str	r3, [r7, #28]
+ 8000856:	2300      	movs	r3, #0
+ 8000858:	61fb      	str	r3, [r7, #28]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8000792:	2303      	movs	r3, #3
- 8000794:	623b      	str	r3, [r7, #32]
+ 800085a:	2303      	movs	r3, #3
+ 800085c:	623b      	str	r3, [r7, #32]
     GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
- 8000796:	2307      	movs	r3, #7
- 8000798:	627b      	str	r3, [r7, #36]	@ 0x24
+ 800085e:	2307      	movs	r3, #7
+ 8000860:	627b      	str	r3, [r7, #36]	@ 0x24
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 800079a:	f107 0314 	add.w	r3, r7, #20
- 800079e:	4619      	mov	r1, r3
- 80007a0:	4805      	ldr	r0, [pc, #20]	@ (80007b8 <HAL_UART_MspInit+0x84>)
- 80007a2:	f000 f9e7 	bl	8000b74 <HAL_GPIO_Init>
+ 8000862:	f107 0314 	add.w	r3, r7, #20
+ 8000866:	4619      	mov	r1, r3
+ 8000868:	4805      	ldr	r0, [pc, #20]	@ (8000880 <HAL_UART_MspInit+0x84>)
+ 800086a:	f000 f9f9 	bl	8000c60 <HAL_GPIO_Init>
 
     /* USER CODE END USART2_MspInit 1 */
 
   }
 
 }
- 80007a6:	bf00      	nop
- 80007a8:	3728      	adds	r7, #40	@ 0x28
- 80007aa:	46bd      	mov	sp, r7
- 80007ac:	bd80      	pop	{r7, pc}
- 80007ae:	bf00      	nop
- 80007b0:	40004400 	.word	0x40004400
- 80007b4:	40023800 	.word	0x40023800
- 80007b8:	40020000 	.word	0x40020000
+ 800086e:	bf00      	nop
+ 8000870:	3728      	adds	r7, #40	@ 0x28
+ 8000872:	46bd      	mov	sp, r7
+ 8000874:	bd80      	pop	{r7, pc}
+ 8000876:	bf00      	nop
+ 8000878:	40004400 	.word	0x40004400
+ 800087c:	40023800 	.word	0x40023800
+ 8000880:	40020000 	.word	0x40020000
 
-080007bc <NMI_Handler>:
+08000884 <NMI_Handler>:
 /******************************************************************************/
 /**
   * @brief This function handles Non maskable interrupt.
   */
 void NMI_Handler(void)
 {
- 80007bc:	b480      	push	{r7}
- 80007be:	af00      	add	r7, sp, #0
+ 8000884:	b480      	push	{r7}
+ 8000886:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
 
   /* USER CODE END NonMaskableInt_IRQn 0 */
   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
    while (1)
- 80007c0:	bf00      	nop
- 80007c2:	e7fd      	b.n	80007c0 <NMI_Handler+0x4>
+ 8000888:	bf00      	nop
+ 800088a:	e7fd      	b.n	8000888 <NMI_Handler+0x4>
 
-080007c4 <HardFault_Handler>:
+0800088c <HardFault_Handler>:
 
 /**
   * @brief This function handles Hard fault interrupt.
   */
 void HardFault_Handler(void)
 {
- 80007c4:	b480      	push	{r7}
- 80007c6:	af00      	add	r7, sp, #0
+ 800088c:	b480      	push	{r7}
+ 800088e:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN HardFault_IRQn 0 */
 
   /* USER CODE END HardFault_IRQn 0 */
   while (1)
- 80007c8:	bf00      	nop
- 80007ca:	e7fd      	b.n	80007c8 <HardFault_Handler+0x4>
+ 8000890:	bf00      	nop
+ 8000892:	e7fd      	b.n	8000890 <HardFault_Handler+0x4>
 
-080007cc <MemManage_Handler>:
+08000894 <MemManage_Handler>:
 
 /**
   * @brief This function handles Memory management fault.
   */
 void MemManage_Handler(void)
 {
- 80007cc:	b480      	push	{r7}
- 80007ce:	af00      	add	r7, sp, #0
+ 8000894:	b480      	push	{r7}
+ 8000896:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN MemoryManagement_IRQn 0 */
 
   /* USER CODE END MemoryManagement_IRQn 0 */
   while (1)
- 80007d0:	bf00      	nop
- 80007d2:	e7fd      	b.n	80007d0 <MemManage_Handler+0x4>
+ 8000898:	bf00      	nop
+ 800089a:	e7fd      	b.n	8000898 <MemManage_Handler+0x4>
 
-080007d4 <BusFault_Handler>:
+0800089c <BusFault_Handler>:
 
 /**
   * @brief This function handles Pre-fetch fault, memory access fault.
   */
 void BusFault_Handler(void)
 {
- 80007d4:	b480      	push	{r7}
- 80007d6:	af00      	add	r7, sp, #0
+ 800089c:	b480      	push	{r7}
+ 800089e:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN BusFault_IRQn 0 */
 
   /* USER CODE END BusFault_IRQn 0 */
   while (1)
- 80007d8:	bf00      	nop
- 80007da:	e7fd      	b.n	80007d8 <BusFault_Handler+0x4>
+ 80008a0:	bf00      	nop
+ 80008a2:	e7fd      	b.n	80008a0 <BusFault_Handler+0x4>
 
-080007dc <UsageFault_Handler>:
+080008a4 <UsageFault_Handler>:
 
 /**
   * @brief This function handles Undefined instruction or illegal state.
   */
 void UsageFault_Handler(void)
 {
- 80007dc:	b480      	push	{r7}
- 80007de:	af00      	add	r7, sp, #0
+ 80008a4:	b480      	push	{r7}
+ 80008a6:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN UsageFault_IRQn 0 */
 
   /* USER CODE END UsageFault_IRQn 0 */
   while (1)
- 80007e0:	bf00      	nop
- 80007e2:	e7fd      	b.n	80007e0 <UsageFault_Handler+0x4>
+ 80008a8:	bf00      	nop
+ 80008aa:	e7fd      	b.n	80008a8 <UsageFault_Handler+0x4>
 
-080007e4 <SVC_Handler>:
+080008ac <SVC_Handler>:
 
 /**
   * @brief This function handles System service call via SWI instruction.
   */
 void SVC_Handler(void)
 {
- 80007e4:	b480      	push	{r7}
- 80007e6:	af00      	add	r7, sp, #0
+ 80008ac:	b480      	push	{r7}
+ 80008ae:	af00      	add	r7, sp, #0
 
   /* USER CODE END SVC_IRQn 0 */
   /* USER CODE BEGIN SVC_IRQn 1 */
 
   /* USER CODE END SVC_IRQn 1 */
 }
- 80007e8:	bf00      	nop
- 80007ea:	46bd      	mov	sp, r7
- 80007ec:	bc80      	pop	{r7}
- 80007ee:	4770      	bx	lr
+ 80008b0:	bf00      	nop
+ 80008b2:	46bd      	mov	sp, r7
+ 80008b4:	bc80      	pop	{r7}
+ 80008b6:	4770      	bx	lr
 
-080007f0 <DebugMon_Handler>:
+080008b8 <DebugMon_Handler>:
 
 /**
   * @brief This function handles Debug monitor.
   */
 void DebugMon_Handler(void)
 {
- 80007f0:	b480      	push	{r7}
- 80007f2:	af00      	add	r7, sp, #0
+ 80008b8:	b480      	push	{r7}
+ 80008ba:	af00      	add	r7, sp, #0
 
   /* USER CODE END DebugMonitor_IRQn 0 */
   /* USER CODE BEGIN DebugMonitor_IRQn 1 */
 
   /* USER CODE END DebugMonitor_IRQn 1 */
 }
- 80007f4:	bf00      	nop
- 80007f6:	46bd      	mov	sp, r7
- 80007f8:	bc80      	pop	{r7}
- 80007fa:	4770      	bx	lr
+ 80008bc:	bf00      	nop
+ 80008be:	46bd      	mov	sp, r7
+ 80008c0:	bc80      	pop	{r7}
+ 80008c2:	4770      	bx	lr
 
-080007fc <PendSV_Handler>:
+080008c4 <PendSV_Handler>:
 
 /**
   * @brief This function handles Pendable request for system service.
   */
 void PendSV_Handler(void)
 {
- 80007fc:	b480      	push	{r7}
- 80007fe:	af00      	add	r7, sp, #0
+ 80008c4:	b480      	push	{r7}
+ 80008c6:	af00      	add	r7, sp, #0
 
   /* USER CODE END PendSV_IRQn 0 */
   /* USER CODE BEGIN PendSV_IRQn 1 */
 
   /* USER CODE END PendSV_IRQn 1 */
 }
- 8000800:	bf00      	nop
- 8000802:	46bd      	mov	sp, r7
- 8000804:	bc80      	pop	{r7}
- 8000806:	4770      	bx	lr
+ 80008c8:	bf00      	nop
+ 80008ca:	46bd      	mov	sp, r7
+ 80008cc:	bc80      	pop	{r7}
+ 80008ce:	4770      	bx	lr
 
-08000808 <SysTick_Handler>:
+080008d0 <SysTick_Handler>:
 
 /**
   * @brief This function handles System tick timer.
   */
 void SysTick_Handler(void)
 {
- 8000808:	b580      	push	{r7, lr}
- 800080a:	af00      	add	r7, sp, #0
+ 80008d0:	b580      	push	{r7, lr}
+ 80008d2:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN SysTick_IRQn 0 */
 
   /* USER CODE END SysTick_IRQn 0 */
   HAL_IncTick();
- 800080c:	f000 f888 	bl	8000920 <HAL_IncTick>
+ 80008d4:	f000 f89a 	bl	8000a0c <HAL_IncTick>
   /* USER CODE BEGIN SysTick_IRQn 1 */
 
   /* USER CODE END SysTick_IRQn 1 */
 }
- 8000810:	bf00      	nop
- 8000812:	bd80      	pop	{r7, pc}
+ 80008d8:	bf00      	nop
+ 80008da:	bd80      	pop	{r7, pc}
 
-08000814 <EXTI15_10_IRQHandler>:
+080008dc <EXTI15_10_IRQHandler>:
 
 /**
   * @brief This function handles EXTI line[15:10] interrupts.
   */
 void EXTI15_10_IRQHandler(void)
 {
- 8000814:	b580      	push	{r7, lr}
- 8000816:	af00      	add	r7, sp, #0
+ 80008dc:	b580      	push	{r7, lr}
+ 80008de:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN EXTI15_10_IRQn 0 */
 
   /* USER CODE END EXTI15_10_IRQn 0 */
   HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
- 8000818:	f44f 5000 	mov.w	r0, #8192	@ 0x2000
- 800081c:	f000 fb52 	bl	8000ec4 <HAL_GPIO_EXTI_IRQHandler>
-
+ 80008e0:	f44f 5000 	mov.w	r0, #8192	@ 0x2000
+ 80008e4:	f000 fb64 	bl	8000fb0 <HAL_GPIO_EXTI_IRQHandler>
   /* USER CODE BEGIN EXTI15_10_IRQn 1 */
 
   /* USER CODE END EXTI15_10_IRQn 1 */
 }
- 8000820:	bf00      	nop
- 8000822:	bd80      	pop	{r7, pc}
+ 80008e8:	bf00      	nop
+ 80008ea:	bd80      	pop	{r7, pc}
 
-08000824 <SystemInit>:
+080008ec <TIM6_IRQHandler>:
+
+/**
+  * @brief This function handles TIM6 global interrupt.
+  */
+void TIM6_IRQHandler(void)
+{
+ 80008ec:	b580      	push	{r7, lr}
+ 80008ee:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN TIM6_IRQn 0 */
+	  GPIOA->ODR ^= (1 << 5);
+ 80008f0:	4b05      	ldr	r3, [pc, #20]	@ (8000908 <TIM6_IRQHandler+0x1c>)
+ 80008f2:	695b      	ldr	r3, [r3, #20]
+ 80008f4:	4a04      	ldr	r2, [pc, #16]	@ (8000908 <TIM6_IRQHandler+0x1c>)
+ 80008f6:	f083 0320 	eor.w	r3, r3, #32
+ 80008fa:	6153      	str	r3, [r2, #20]
+
+
+  /* USER CODE END TIM6_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim6);
+ 80008fc:	4803      	ldr	r0, [pc, #12]	@ (800090c <TIM6_IRQHandler+0x20>)
+ 80008fe:	f001 f9a4 	bl	8001c4a <HAL_TIM_IRQHandler>
+  /* USER CODE BEGIN TIM6_IRQn 1 */
+
+  /* USER CODE END TIM6_IRQn 1 */
+}
+ 8000902:	bf00      	nop
+ 8000904:	bd80      	pop	{r7, pc}
+ 8000906:	bf00      	nop
+ 8000908:	40020000 	.word	0x40020000
+ 800090c:	20000028 	.word	0x20000028
+
+08000910 <SystemInit>:
   *         SystemCoreClock variable.
   * @param  None
   * @retval None
   */
 void SystemInit (void)
 {
- 8000824:	b480      	push	{r7}
- 8000826:	af00      	add	r7, sp, #0
+ 8000910:	b480      	push	{r7}
+ 8000912:	af00      	add	r7, sp, #0
     
   /* Configure the Vector Table location -------------------------------------*/
 #if defined(USER_VECT_TAB_ADDRESS)
   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 #endif /* USER_VECT_TAB_ADDRESS */
 }
- 8000828:	bf00      	nop
- 800082a:	46bd      	mov	sp, r7
- 800082c:	bc80      	pop	{r7}
- 800082e:	4770      	bx	lr
+ 8000914:	bf00      	nop
+ 8000916:	46bd      	mov	sp, r7
+ 8000918:	bc80      	pop	{r7}
+ 800091a:	4770      	bx	lr
 
-08000830 <Reset_Handler>:
+0800091c <Reset_Handler>:
   .type Reset_Handler, %function
 Reset_Handler:
 
 
 /* Call the clock system initialization function.*/
     bl  SystemInit
- 8000830:	f7ff fff8 	bl	8000824 <SystemInit>
+ 800091c:	f7ff fff8 	bl	8000910 <SystemInit>
 
 /* Copy the data segment initializers from flash to SRAM */
   ldr r0, =_sdata
- 8000834:	480b      	ldr	r0, [pc, #44]	@ (8000864 <LoopFillZerobss+0xe>)
+ 8000920:	480b      	ldr	r0, [pc, #44]	@ (8000950 <LoopFillZerobss+0xe>)
   ldr r1, =_edata
- 8000836:	490c      	ldr	r1, [pc, #48]	@ (8000868 <LoopFillZerobss+0x12>)
+ 8000922:	490c      	ldr	r1, [pc, #48]	@ (8000954 <LoopFillZerobss+0x12>)
   ldr r2, =_sidata
- 8000838:	4a0c      	ldr	r2, [pc, #48]	@ (800086c <LoopFillZerobss+0x16>)
+ 8000924:	4a0c      	ldr	r2, [pc, #48]	@ (8000958 <LoopFillZerobss+0x16>)
   movs r3, #0
- 800083a:	2300      	movs	r3, #0
+ 8000926:	2300      	movs	r3, #0
   b LoopCopyDataInit
- 800083c:	e002      	b.n	8000844 <LoopCopyDataInit>
+ 8000928:	e002      	b.n	8000930 <LoopCopyDataInit>
 
-0800083e <CopyDataInit>:
+0800092a <CopyDataInit>:
 
 CopyDataInit:
   ldr r4, [r2, r3]
- 800083e:	58d4      	ldr	r4, [r2, r3]
+ 800092a:	58d4      	ldr	r4, [r2, r3]
   str r4, [r0, r3]
- 8000840:	50c4      	str	r4, [r0, r3]
+ 800092c:	50c4      	str	r4, [r0, r3]
   adds r3, r3, #4
- 8000842:	3304      	adds	r3, #4
+ 800092e:	3304      	adds	r3, #4
 
-08000844 <LoopCopyDataInit>:
+08000930 <LoopCopyDataInit>:
 
 LoopCopyDataInit:
   adds r4, r0, r3
- 8000844:	18c4      	adds	r4, r0, r3
+ 8000930:	18c4      	adds	r4, r0, r3
   cmp r4, r1
- 8000846:	428c      	cmp	r4, r1
+ 8000932:	428c      	cmp	r4, r1
   bcc CopyDataInit
- 8000848:	d3f9      	bcc.n	800083e <CopyDataInit>
+ 8000934:	d3f9      	bcc.n	800092a <CopyDataInit>
   
 /* Zero fill the bss segment. */
   ldr r2, =_sbss
- 800084a:	4a09      	ldr	r2, [pc, #36]	@ (8000870 <LoopFillZerobss+0x1a>)
+ 8000936:	4a09      	ldr	r2, [pc, #36]	@ (800095c <LoopFillZerobss+0x1a>)
   ldr r4, =_ebss
- 800084c:	4c09      	ldr	r4, [pc, #36]	@ (8000874 <LoopFillZerobss+0x1e>)
+ 8000938:	4c09      	ldr	r4, [pc, #36]	@ (8000960 <LoopFillZerobss+0x1e>)
   movs r3, #0
- 800084e:	2300      	movs	r3, #0
+ 800093a:	2300      	movs	r3, #0
   b LoopFillZerobss
- 8000850:	e001      	b.n	8000856 <LoopFillZerobss>
+ 800093c:	e001      	b.n	8000942 <LoopFillZerobss>
 
-08000852 <FillZerobss>:
+0800093e <FillZerobss>:
 
 FillZerobss:
   str  r3, [r2]
- 8000852:	6013      	str	r3, [r2, #0]
+ 800093e:	6013      	str	r3, [r2, #0]
   adds r2, r2, #4
- 8000854:	3204      	adds	r2, #4
+ 8000940:	3204      	adds	r2, #4
 
-08000856 <LoopFillZerobss>:
+08000942 <LoopFillZerobss>:
 
 LoopFillZerobss:
   cmp r2, r4
- 8000856:	42a2      	cmp	r2, r4
+ 8000942:	42a2      	cmp	r2, r4
   bcc FillZerobss
- 8000858:	d3fb      	bcc.n	8000852 <FillZerobss>
+ 8000944:	d3fb      	bcc.n	800093e <FillZerobss>
 
 /* Call static constructors */
     bl __libc_init_array
- 800085a:	f001 fa7d 	bl	8001d58 <__libc_init_array>
+ 8000946:	f001 fc89 	bl	800225c <__libc_init_array>
 /* Call the application's entry point.*/
   bl main
- 800085e:	f7ff fe27 	bl	80004b0 <main>
+ 800094a:	f7ff fdb1 	bl	80004b0 <main>
   bx lr
- 8000862:	4770      	bx	lr
+ 800094e:	4770      	bx	lr
   ldr r0, =_sdata
- 8000864:	20000000 	.word	0x20000000
+ 8000950:	20000000 	.word	0x20000000
   ldr r1, =_edata
- 8000868:	2000000c 	.word	0x2000000c
+ 8000954:	2000000c 	.word	0x2000000c
   ldr r2, =_sidata
- 800086c:	08001dec 	.word	0x08001dec
+ 8000958:	080022f0 	.word	0x080022f0
   ldr r2, =_sbss
- 8000870:	2000000c 	.word	0x2000000c
+ 800095c:	2000000c 	.word	0x2000000c
   ldr r4, =_ebss
- 8000874:	20000074 	.word	0x20000074
+ 8000960:	200000b4 	.word	0x200000b4
 
-08000878 <ADC1_IRQHandler>:
+08000964 <ADC1_IRQHandler>:
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
- 8000878:	e7fe      	b.n	8000878 <ADC1_IRQHandler>
+ 8000964:	e7fe      	b.n	8000964 <ADC1_IRQHandler>
 
-0800087a <HAL_Init>:
+08000966 <HAL_Init>:
   *        In the default implementation,Systick is used as source of time base.
   *        the tick variable is incremented each 1ms in its ISR.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_Init(void)
 {
- 800087a:	b580      	push	{r7, lr}
- 800087c:	b082      	sub	sp, #8
- 800087e:	af00      	add	r7, sp, #0
+ 8000966:	b580      	push	{r7, lr}
+ 8000968:	b082      	sub	sp, #8
+ 800096a:	af00      	add	r7, sp, #0
   HAL_StatusTypeDef  status = HAL_OK;
- 8000880:	2300      	movs	r3, #0
- 8000882:	71fb      	strb	r3, [r7, #7]
+ 800096c:	2300      	movs	r3, #0
+ 800096e:	71fb      	strb	r3, [r7, #7]
 #if (PREFETCH_ENABLE != 0)
   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 #endif /* PREFETCH_ENABLE */
 
   /* Set Interrupt Group Priority */
   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8000884:	2003      	movs	r0, #3
- 8000886:	f000 f933 	bl	8000af0 <HAL_NVIC_SetPriorityGrouping>
+ 8000970:	2003      	movs	r0, #3
+ 8000972:	f000 f933 	bl	8000bdc <HAL_NVIC_SetPriorityGrouping>
 
   /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
   if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
- 800088a:	2000      	movs	r0, #0
- 800088c:	f000 f80e 	bl	80008ac <HAL_InitTick>
- 8000890:	4603      	mov	r3, r0
- 8000892:	2b00      	cmp	r3, #0
- 8000894:	d002      	beq.n	800089c <HAL_Init+0x22>
+ 8000976:	2000      	movs	r0, #0
+ 8000978:	f000 f80e 	bl	8000998 <HAL_InitTick>
+ 800097c:	4603      	mov	r3, r0
+ 800097e:	2b00      	cmp	r3, #0
+ 8000980:	d002      	beq.n	8000988 <HAL_Init+0x22>
   {
     status = HAL_ERROR;
- 8000896:	2301      	movs	r3, #1
- 8000898:	71fb      	strb	r3, [r7, #7]
- 800089a:	e001      	b.n	80008a0 <HAL_Init+0x26>
+ 8000982:	2301      	movs	r3, #1
+ 8000984:	71fb      	strb	r3, [r7, #7]
+ 8000986:	e001      	b.n	800098c <HAL_Init+0x26>
   }
   else
   {
     /* Init the low level hardware */
     HAL_MspInit();
- 800089c:	f7ff ff1a 	bl	80006d4 <HAL_MspInit>
+ 8000988:	f7ff fee2 	bl	8000750 <HAL_MspInit>
   }
 
   /* Return function status */
   return status;
- 80008a0:	79fb      	ldrb	r3, [r7, #7]
+ 800098c:	79fb      	ldrb	r3, [r7, #7]
 }
- 80008a2:	4618      	mov	r0, r3
- 80008a4:	3708      	adds	r7, #8
- 80008a6:	46bd      	mov	sp, r7
- 80008a8:	bd80      	pop	{r7, pc}
+ 800098e:	4618      	mov	r0, r3
+ 8000990:	3708      	adds	r7, #8
+ 8000992:	46bd      	mov	sp, r7
+ 8000994:	bd80      	pop	{r7, pc}
 	...
 
-080008ac <HAL_InitTick>:
+08000998 <HAL_InitTick>:
   *       implementation  in user file.
   * @param TickPriority Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
- 80008ac:	b580      	push	{r7, lr}
- 80008ae:	b084      	sub	sp, #16
- 80008b0:	af00      	add	r7, sp, #0
- 80008b2:	6078      	str	r0, [r7, #4]
+ 8000998:	b580      	push	{r7, lr}
+ 800099a:	b084      	sub	sp, #16
+ 800099c:	af00      	add	r7, sp, #0
+ 800099e:	6078      	str	r0, [r7, #4]
   HAL_StatusTypeDef  status = HAL_OK;
- 80008b4:	2300      	movs	r3, #0
- 80008b6:	73fb      	strb	r3, [r7, #15]
+ 80009a0:	2300      	movs	r3, #0
+ 80009a2:	73fb      	strb	r3, [r7, #15]
 
   if (uwTickFreq != 0U)
- 80008b8:	4b16      	ldr	r3, [pc, #88]	@ (8000914 <HAL_InitTick+0x68>)
- 80008ba:	681b      	ldr	r3, [r3, #0]
- 80008bc:	2b00      	cmp	r3, #0
- 80008be:	d022      	beq.n	8000906 <HAL_InitTick+0x5a>
+ 80009a4:	4b16      	ldr	r3, [pc, #88]	@ (8000a00 <HAL_InitTick+0x68>)
+ 80009a6:	681b      	ldr	r3, [r3, #0]
+ 80009a8:	2b00      	cmp	r3, #0
+ 80009aa:	d022      	beq.n	80009f2 <HAL_InitTick+0x5a>
   {
     /*Configure the SysTick to have interrupt in 1ms time basis*/
     if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
- 80008c0:	4b15      	ldr	r3, [pc, #84]	@ (8000918 <HAL_InitTick+0x6c>)
- 80008c2:	681a      	ldr	r2, [r3, #0]
- 80008c4:	4b13      	ldr	r3, [pc, #76]	@ (8000914 <HAL_InitTick+0x68>)
- 80008c6:	681b      	ldr	r3, [r3, #0]
- 80008c8:	f44f 717a 	mov.w	r1, #1000	@ 0x3e8
- 80008cc:	fbb1 f3f3 	udiv	r3, r1, r3
- 80008d0:	fbb2 f3f3 	udiv	r3, r2, r3
- 80008d4:	4618      	mov	r0, r3
- 80008d6:	f000 f940 	bl	8000b5a <HAL_SYSTICK_Config>
- 80008da:	4603      	mov	r3, r0
- 80008dc:	2b00      	cmp	r3, #0
- 80008de:	d10f      	bne.n	8000900 <HAL_InitTick+0x54>
+ 80009ac:	4b15      	ldr	r3, [pc, #84]	@ (8000a04 <HAL_InitTick+0x6c>)
+ 80009ae:	681a      	ldr	r2, [r3, #0]
+ 80009b0:	4b13      	ldr	r3, [pc, #76]	@ (8000a00 <HAL_InitTick+0x68>)
+ 80009b2:	681b      	ldr	r3, [r3, #0]
+ 80009b4:	f44f 717a 	mov.w	r1, #1000	@ 0x3e8
+ 80009b8:	fbb1 f3f3 	udiv	r3, r1, r3
+ 80009bc:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80009c0:	4618      	mov	r0, r3
+ 80009c2:	f000 f940 	bl	8000c46 <HAL_SYSTICK_Config>
+ 80009c6:	4603      	mov	r3, r0
+ 80009c8:	2b00      	cmp	r3, #0
+ 80009ca:	d10f      	bne.n	80009ec <HAL_InitTick+0x54>
     {
       /* Configure the SysTick IRQ priority */
       if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 80008e0:	687b      	ldr	r3, [r7, #4]
- 80008e2:	2b0f      	cmp	r3, #15
- 80008e4:	d809      	bhi.n	80008fa <HAL_InitTick+0x4e>
+ 80009cc:	687b      	ldr	r3, [r7, #4]
+ 80009ce:	2b0f      	cmp	r3, #15
+ 80009d0:	d809      	bhi.n	80009e6 <HAL_InitTick+0x4e>
       {
         HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 80008e6:	2200      	movs	r2, #0
- 80008e8:	6879      	ldr	r1, [r7, #4]
- 80008ea:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
- 80008ee:	f000 f90a 	bl	8000b06 <HAL_NVIC_SetPriority>
+ 80009d2:	2200      	movs	r2, #0
+ 80009d4:	6879      	ldr	r1, [r7, #4]
+ 80009d6:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
+ 80009da:	f000 f90a 	bl	8000bf2 <HAL_NVIC_SetPriority>
         uwTickPrio = TickPriority;
- 80008f2:	4a0a      	ldr	r2, [pc, #40]	@ (800091c <HAL_InitTick+0x70>)
- 80008f4:	687b      	ldr	r3, [r7, #4]
- 80008f6:	6013      	str	r3, [r2, #0]
- 80008f8:	e007      	b.n	800090a <HAL_InitTick+0x5e>
+ 80009de:	4a0a      	ldr	r2, [pc, #40]	@ (8000a08 <HAL_InitTick+0x70>)
+ 80009e0:	687b      	ldr	r3, [r7, #4]
+ 80009e2:	6013      	str	r3, [r2, #0]
+ 80009e4:	e007      	b.n	80009f6 <HAL_InitTick+0x5e>
       }
       else
       {
         status = HAL_ERROR;
- 80008fa:	2301      	movs	r3, #1
- 80008fc:	73fb      	strb	r3, [r7, #15]
- 80008fe:	e004      	b.n	800090a <HAL_InitTick+0x5e>
+ 80009e6:	2301      	movs	r3, #1
+ 80009e8:	73fb      	strb	r3, [r7, #15]
+ 80009ea:	e004      	b.n	80009f6 <HAL_InitTick+0x5e>
       }
     }
     else
     {
       status = HAL_ERROR;
- 8000900:	2301      	movs	r3, #1
- 8000902:	73fb      	strb	r3, [r7, #15]
- 8000904:	e001      	b.n	800090a <HAL_InitTick+0x5e>
+ 80009ec:	2301      	movs	r3, #1
+ 80009ee:	73fb      	strb	r3, [r7, #15]
+ 80009f0:	e001      	b.n	80009f6 <HAL_InitTick+0x5e>
     }
   }
   else
   {
     status = HAL_ERROR;
- 8000906:	2301      	movs	r3, #1
- 8000908:	73fb      	strb	r3, [r7, #15]
+ 80009f2:	2301      	movs	r3, #1
+ 80009f4:	73fb      	strb	r3, [r7, #15]
   }
 
   /* Return function status */
   return status;
- 800090a:	7bfb      	ldrb	r3, [r7, #15]
+ 80009f6:	7bfb      	ldrb	r3, [r7, #15]
 }
- 800090c:	4618      	mov	r0, r3
- 800090e:	3710      	adds	r7, #16
- 8000910:	46bd      	mov	sp, r7
- 8000912:	bd80      	pop	{r7, pc}
- 8000914:	20000008 	.word	0x20000008
- 8000918:	20000000 	.word	0x20000000
- 800091c:	20000004 	.word	0x20000004
+ 80009f8:	4618      	mov	r0, r3
+ 80009fa:	3710      	adds	r7, #16
+ 80009fc:	46bd      	mov	sp, r7
+ 80009fe:	bd80      	pop	{r7, pc}
+ 8000a00:	20000008 	.word	0x20000008
+ 8000a04:	20000000 	.word	0x20000000
+ 8000a08:	20000004 	.word	0x20000004
 
-08000920 <HAL_IncTick>:
+08000a0c <HAL_IncTick>:
  * @note This function is declared as __weak to be overwritten in case of other
   *      implementations in user file.
   * @retval None
   */
 __weak void HAL_IncTick(void)
 {
- 8000920:	b480      	push	{r7}
- 8000922:	af00      	add	r7, sp, #0
+ 8000a0c:	b480      	push	{r7}
+ 8000a0e:	af00      	add	r7, sp, #0
   uwTick += uwTickFreq;
- 8000924:	4b05      	ldr	r3, [pc, #20]	@ (800093c <HAL_IncTick+0x1c>)
- 8000926:	681a      	ldr	r2, [r3, #0]
- 8000928:	4b05      	ldr	r3, [pc, #20]	@ (8000940 <HAL_IncTick+0x20>)
- 800092a:	681b      	ldr	r3, [r3, #0]
- 800092c:	4413      	add	r3, r2
- 800092e:	4a03      	ldr	r2, [pc, #12]	@ (800093c <HAL_IncTick+0x1c>)
- 8000930:	6013      	str	r3, [r2, #0]
+ 8000a10:	4b05      	ldr	r3, [pc, #20]	@ (8000a28 <HAL_IncTick+0x1c>)
+ 8000a12:	681a      	ldr	r2, [r3, #0]
+ 8000a14:	4b05      	ldr	r3, [pc, #20]	@ (8000a2c <HAL_IncTick+0x20>)
+ 8000a16:	681b      	ldr	r3, [r3, #0]
+ 8000a18:	4413      	add	r3, r2
+ 8000a1a:	4a03      	ldr	r2, [pc, #12]	@ (8000a28 <HAL_IncTick+0x1c>)
+ 8000a1c:	6013      	str	r3, [r2, #0]
 }
- 8000932:	bf00      	nop
- 8000934:	46bd      	mov	sp, r7
- 8000936:	bc80      	pop	{r7}
- 8000938:	4770      	bx	lr
- 800093a:	bf00      	nop
- 800093c:	20000070 	.word	0x20000070
- 8000940:	20000008 	.word	0x20000008
+ 8000a1e:	bf00      	nop
+ 8000a20:	46bd      	mov	sp, r7
+ 8000a22:	bc80      	pop	{r7}
+ 8000a24:	4770      	bx	lr
+ 8000a26:	bf00      	nop
+ 8000a28:	200000b0 	.word	0x200000b0
+ 8000a2c:	20000008 	.word	0x20000008
 
-08000944 <HAL_GetTick>:
+08000a30 <HAL_GetTick>:
   * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
   * @retval tick value
   */
 __weak uint32_t HAL_GetTick(void)
 {
- 8000944:	b480      	push	{r7}
- 8000946:	af00      	add	r7, sp, #0
+ 8000a30:	b480      	push	{r7}
+ 8000a32:	af00      	add	r7, sp, #0
   return uwTick;
- 8000948:	4b02      	ldr	r3, [pc, #8]	@ (8000954 <HAL_GetTick+0x10>)
- 800094a:	681b      	ldr	r3, [r3, #0]
+ 8000a34:	4b02      	ldr	r3, [pc, #8]	@ (8000a40 <HAL_GetTick+0x10>)
+ 8000a36:	681b      	ldr	r3, [r3, #0]
 }
- 800094c:	4618      	mov	r0, r3
- 800094e:	46bd      	mov	sp, r7
- 8000950:	bc80      	pop	{r7}
- 8000952:	4770      	bx	lr
- 8000954:	20000070 	.word	0x20000070
+ 8000a38:	4618      	mov	r0, r3
+ 8000a3a:	46bd      	mov	sp, r7
+ 8000a3c:	bc80      	pop	{r7}
+ 8000a3e:	4770      	bx	lr
+ 8000a40:	200000b0 	.word	0x200000b0
 
-08000958 <__NVIC_SetPriorityGrouping>:
+08000a44 <__NVIC_SetPriorityGrouping>:
            In case of a conflict between priority grouping and available
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
  */
 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
- 8000958:	b480      	push	{r7}
- 800095a:	b085      	sub	sp, #20
- 800095c:	af00      	add	r7, sp, #0
- 800095e:	6078      	str	r0, [r7, #4]
+ 8000a44:	b480      	push	{r7}
+ 8000a46:	b085      	sub	sp, #20
+ 8000a48:	af00      	add	r7, sp, #0
+ 8000a4a:	6078      	str	r0, [r7, #4]
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
- 8000960:	687b      	ldr	r3, [r7, #4]
- 8000962:	f003 0307 	and.w	r3, r3, #7
- 8000966:	60fb      	str	r3, [r7, #12]
+ 8000a4c:	687b      	ldr	r3, [r7, #4]
+ 8000a4e:	f003 0307 	and.w	r3, r3, #7
+ 8000a52:	60fb      	str	r3, [r7, #12]
 
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
- 8000968:	4b0c      	ldr	r3, [pc, #48]	@ (800099c <__NVIC_SetPriorityGrouping+0x44>)
- 800096a:	68db      	ldr	r3, [r3, #12]
- 800096c:	60bb      	str	r3, [r7, #8]
+ 8000a54:	4b0c      	ldr	r3, [pc, #48]	@ (8000a88 <__NVIC_SetPriorityGrouping+0x44>)
+ 8000a56:	68db      	ldr	r3, [r3, #12]
+ 8000a58:	60bb      	str	r3, [r7, #8]
   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
- 800096e:	68ba      	ldr	r2, [r7, #8]
- 8000970:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
- 8000974:	4013      	ands	r3, r2
- 8000976:	60bb      	str	r3, [r7, #8]
+ 8000a5a:	68ba      	ldr	r2, [r7, #8]
+ 8000a5c:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
+ 8000a60:	4013      	ands	r3, r2
+ 8000a62:	60bb      	str	r3, [r7, #8]
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
- 8000978:	68fb      	ldr	r3, [r7, #12]
- 800097a:	021a      	lsls	r2, r3, #8
+ 8000a64:	68fb      	ldr	r3, [r7, #12]
+ 8000a66:	021a      	lsls	r2, r3, #8
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 800097c:	68bb      	ldr	r3, [r7, #8]
- 800097e:	4313      	orrs	r3, r2
+ 8000a68:	68bb      	ldr	r3, [r7, #8]
+ 8000a6a:	4313      	orrs	r3, r2
   reg_value  =  (reg_value                                   |
- 8000980:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
- 8000984:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
- 8000988:	60bb      	str	r3, [r7, #8]
+ 8000a6c:	f043 63bf 	orr.w	r3, r3, #100139008	@ 0x5f80000
+ 8000a70:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 8000a74:	60bb      	str	r3, [r7, #8]
   SCB->AIRCR =  reg_value;
- 800098a:	4a04      	ldr	r2, [pc, #16]	@ (800099c <__NVIC_SetPriorityGrouping+0x44>)
- 800098c:	68bb      	ldr	r3, [r7, #8]
- 800098e:	60d3      	str	r3, [r2, #12]
+ 8000a76:	4a04      	ldr	r2, [pc, #16]	@ (8000a88 <__NVIC_SetPriorityGrouping+0x44>)
+ 8000a78:	68bb      	ldr	r3, [r7, #8]
+ 8000a7a:	60d3      	str	r3, [r2, #12]
 }
- 8000990:	bf00      	nop
- 8000992:	3714      	adds	r7, #20
- 8000994:	46bd      	mov	sp, r7
- 8000996:	bc80      	pop	{r7}
- 8000998:	4770      	bx	lr
- 800099a:	bf00      	nop
- 800099c:	e000ed00 	.word	0xe000ed00
+ 8000a7c:	bf00      	nop
+ 8000a7e:	3714      	adds	r7, #20
+ 8000a80:	46bd      	mov	sp, r7
+ 8000a82:	bc80      	pop	{r7}
+ 8000a84:	4770      	bx	lr
+ 8000a86:	bf00      	nop
+ 8000a88:	e000ed00 	.word	0xe000ed00
 
-080009a0 <__NVIC_GetPriorityGrouping>:
+08000a8c <__NVIC_GetPriorityGrouping>:
   \brief   Get Priority Grouping
   \details Reads the priority grouping field from the NVIC Interrupt Controller.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
- 80009a0:	b480      	push	{r7}
- 80009a2:	af00      	add	r7, sp, #0
+ 8000a8c:	b480      	push	{r7}
+ 8000a8e:	af00      	add	r7, sp, #0
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 80009a4:	4b04      	ldr	r3, [pc, #16]	@ (80009b8 <__NVIC_GetPriorityGrouping+0x18>)
- 80009a6:	68db      	ldr	r3, [r3, #12]
- 80009a8:	0a1b      	lsrs	r3, r3, #8
- 80009aa:	f003 0307 	and.w	r3, r3, #7
+ 8000a90:	4b04      	ldr	r3, [pc, #16]	@ (8000aa4 <__NVIC_GetPriorityGrouping+0x18>)
+ 8000a92:	68db      	ldr	r3, [r3, #12]
+ 8000a94:	0a1b      	lsrs	r3, r3, #8
+ 8000a96:	f003 0307 	and.w	r3, r3, #7
 }
- 80009ae:	4618      	mov	r0, r3
- 80009b0:	46bd      	mov	sp, r7
- 80009b2:	bc80      	pop	{r7}
- 80009b4:	4770      	bx	lr
- 80009b6:	bf00      	nop
- 80009b8:	e000ed00 	.word	0xe000ed00
+ 8000a9a:	4618      	mov	r0, r3
+ 8000a9c:	46bd      	mov	sp, r7
+ 8000a9e:	bc80      	pop	{r7}
+ 8000aa0:	4770      	bx	lr
+ 8000aa2:	bf00      	nop
+ 8000aa4:	e000ed00 	.word	0xe000ed00
 
-080009bc <__NVIC_EnableIRQ>:
+08000aa8 <__NVIC_EnableIRQ>:
   \details Enables a device specific interrupt in the NVIC interrupt controller.
   \param [in]      IRQn  Device specific interrupt number.
   \note    IRQn must not be negative.
  */
 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
- 80009bc:	b480      	push	{r7}
- 80009be:	b083      	sub	sp, #12
- 80009c0:	af00      	add	r7, sp, #0
- 80009c2:	4603      	mov	r3, r0
- 80009c4:	71fb      	strb	r3, [r7, #7]
+ 8000aa8:	b480      	push	{r7}
+ 8000aaa:	b083      	sub	sp, #12
+ 8000aac:	af00      	add	r7, sp, #0
+ 8000aae:	4603      	mov	r3, r0
+ 8000ab0:	71fb      	strb	r3, [r7, #7]
   if ((int32_t)(IRQn) >= 0)
- 80009c6:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80009ca:	2b00      	cmp	r3, #0
- 80009cc:	db0b      	blt.n	80009e6 <__NVIC_EnableIRQ+0x2a>
+ 8000ab2:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8000ab6:	2b00      	cmp	r3, #0
+ 8000ab8:	db0b      	blt.n	8000ad2 <__NVIC_EnableIRQ+0x2a>
   {
     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 80009ce:	79fb      	ldrb	r3, [r7, #7]
- 80009d0:	f003 021f 	and.w	r2, r3, #31
- 80009d4:	4906      	ldr	r1, [pc, #24]	@ (80009f0 <__NVIC_EnableIRQ+0x34>)
- 80009d6:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80009da:	095b      	lsrs	r3, r3, #5
- 80009dc:	2001      	movs	r0, #1
- 80009de:	fa00 f202 	lsl.w	r2, r0, r2
- 80009e2:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+ 8000aba:	79fb      	ldrb	r3, [r7, #7]
+ 8000abc:	f003 021f 	and.w	r2, r3, #31
+ 8000ac0:	4906      	ldr	r1, [pc, #24]	@ (8000adc <__NVIC_EnableIRQ+0x34>)
+ 8000ac2:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8000ac6:	095b      	lsrs	r3, r3, #5
+ 8000ac8:	2001      	movs	r0, #1
+ 8000aca:	fa00 f202 	lsl.w	r2, r0, r2
+ 8000ace:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
   }
 }
- 80009e6:	bf00      	nop
- 80009e8:	370c      	adds	r7, #12
- 80009ea:	46bd      	mov	sp, r7
- 80009ec:	bc80      	pop	{r7}
- 80009ee:	4770      	bx	lr
- 80009f0:	e000e100 	.word	0xe000e100
+ 8000ad2:	bf00      	nop
+ 8000ad4:	370c      	adds	r7, #12
+ 8000ad6:	46bd      	mov	sp, r7
+ 8000ad8:	bc80      	pop	{r7}
+ 8000ada:	4770      	bx	lr
+ 8000adc:	e000e100 	.word	0xe000e100
 
-080009f4 <__NVIC_SetPriority>:
+08000ae0 <__NVIC_SetPriority>:
   \param [in]      IRQn  Interrupt number.
   \param [in]  priority  Priority to set.
   \note    The priority cannot be set for every processor exception.
  */
 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
- 80009f4:	b480      	push	{r7}
- 80009f6:	b083      	sub	sp, #12
- 80009f8:	af00      	add	r7, sp, #0
- 80009fa:	4603      	mov	r3, r0
- 80009fc:	6039      	str	r1, [r7, #0]
- 80009fe:	71fb      	strb	r3, [r7, #7]
+ 8000ae0:	b480      	push	{r7}
+ 8000ae2:	b083      	sub	sp, #12
+ 8000ae4:	af00      	add	r7, sp, #0
+ 8000ae6:	4603      	mov	r3, r0
+ 8000ae8:	6039      	str	r1, [r7, #0]
+ 8000aea:	71fb      	strb	r3, [r7, #7]
   if ((int32_t)(IRQn) >= 0)
- 8000a00:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8000a04:	2b00      	cmp	r3, #0
- 8000a06:	db0a      	blt.n	8000a1e <__NVIC_SetPriority+0x2a>
+ 8000aec:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8000af0:	2b00      	cmp	r3, #0
+ 8000af2:	db0a      	blt.n	8000b0a <__NVIC_SetPriority+0x2a>
   {
     NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8000a08:	683b      	ldr	r3, [r7, #0]
- 8000a0a:	b2da      	uxtb	r2, r3
- 8000a0c:	490c      	ldr	r1, [pc, #48]	@ (8000a40 <__NVIC_SetPriority+0x4c>)
- 8000a0e:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8000a12:	0112      	lsls	r2, r2, #4
- 8000a14:	b2d2      	uxtb	r2, r2
- 8000a16:	440b      	add	r3, r1
- 8000a18:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
+ 8000af4:	683b      	ldr	r3, [r7, #0]
+ 8000af6:	b2da      	uxtb	r2, r3
+ 8000af8:	490c      	ldr	r1, [pc, #48]	@ (8000b2c <__NVIC_SetPriority+0x4c>)
+ 8000afa:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8000afe:	0112      	lsls	r2, r2, #4
+ 8000b00:	b2d2      	uxtb	r2, r2
+ 8000b02:	440b      	add	r3, r1
+ 8000b04:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
   }
   else
   {
     SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
   }
 }
- 8000a1c:	e00a      	b.n	8000a34 <__NVIC_SetPriority+0x40>
+ 8000b08:	e00a      	b.n	8000b20 <__NVIC_SetPriority+0x40>
     SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 8000a1e:	683b      	ldr	r3, [r7, #0]
- 8000a20:	b2da      	uxtb	r2, r3
- 8000a22:	4908      	ldr	r1, [pc, #32]	@ (8000a44 <__NVIC_SetPriority+0x50>)
- 8000a24:	79fb      	ldrb	r3, [r7, #7]
- 8000a26:	f003 030f 	and.w	r3, r3, #15
- 8000a2a:	3b04      	subs	r3, #4
- 8000a2c:	0112      	lsls	r2, r2, #4
- 8000a2e:	b2d2      	uxtb	r2, r2
- 8000a30:	440b      	add	r3, r1
- 8000a32:	761a      	strb	r2, [r3, #24]
+ 8000b0a:	683b      	ldr	r3, [r7, #0]
+ 8000b0c:	b2da      	uxtb	r2, r3
+ 8000b0e:	4908      	ldr	r1, [pc, #32]	@ (8000b30 <__NVIC_SetPriority+0x50>)
+ 8000b10:	79fb      	ldrb	r3, [r7, #7]
+ 8000b12:	f003 030f 	and.w	r3, r3, #15
+ 8000b16:	3b04      	subs	r3, #4
+ 8000b18:	0112      	lsls	r2, r2, #4
+ 8000b1a:	b2d2      	uxtb	r2, r2
+ 8000b1c:	440b      	add	r3, r1
+ 8000b1e:	761a      	strb	r2, [r3, #24]
 }
- 8000a34:	bf00      	nop
- 8000a36:	370c      	adds	r7, #12
- 8000a38:	46bd      	mov	sp, r7
- 8000a3a:	bc80      	pop	{r7}
- 8000a3c:	4770      	bx	lr
- 8000a3e:	bf00      	nop
- 8000a40:	e000e100 	.word	0xe000e100
- 8000a44:	e000ed00 	.word	0xe000ed00
+ 8000b20:	bf00      	nop
+ 8000b22:	370c      	adds	r7, #12
+ 8000b24:	46bd      	mov	sp, r7
+ 8000b26:	bc80      	pop	{r7}
+ 8000b28:	4770      	bx	lr
+ 8000b2a:	bf00      	nop
+ 8000b2c:	e000e100 	.word	0xe000e100
+ 8000b30:	e000ed00 	.word	0xe000ed00
 
-08000a48 <NVIC_EncodePriority>:
+08000b34 <NVIC_EncodePriority>:
   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
   \param [in]       SubPriority  Subpriority value (starting from 0).
   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
- 8000a48:	b480      	push	{r7}
- 8000a4a:	b089      	sub	sp, #36	@ 0x24
- 8000a4c:	af00      	add	r7, sp, #0
- 8000a4e:	60f8      	str	r0, [r7, #12]
- 8000a50:	60b9      	str	r1, [r7, #8]
- 8000a52:	607a      	str	r2, [r7, #4]
+ 8000b34:	b480      	push	{r7}
+ 8000b36:	b089      	sub	sp, #36	@ 0x24
+ 8000b38:	af00      	add	r7, sp, #0
+ 8000b3a:	60f8      	str	r0, [r7, #12]
+ 8000b3c:	60b9      	str	r1, [r7, #8]
+ 8000b3e:	607a      	str	r2, [r7, #4]
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
- 8000a54:	68fb      	ldr	r3, [r7, #12]
- 8000a56:	f003 0307 	and.w	r3, r3, #7
- 8000a5a:	61fb      	str	r3, [r7, #28]
+ 8000b40:	68fb      	ldr	r3, [r7, #12]
+ 8000b42:	f003 0307 	and.w	r3, r3, #7
+ 8000b46:	61fb      	str	r3, [r7, #28]
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;
 
   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8000a5c:	69fb      	ldr	r3, [r7, #28]
- 8000a5e:	f1c3 0307 	rsb	r3, r3, #7
- 8000a62:	2b04      	cmp	r3, #4
- 8000a64:	bf28      	it	cs
- 8000a66:	2304      	movcs	r3, #4
- 8000a68:	61bb      	str	r3, [r7, #24]
+ 8000b48:	69fb      	ldr	r3, [r7, #28]
+ 8000b4a:	f1c3 0307 	rsb	r3, r3, #7
+ 8000b4e:	2b04      	cmp	r3, #4
+ 8000b50:	bf28      	it	cs
+ 8000b52:	2304      	movcs	r3, #4
+ 8000b54:	61bb      	str	r3, [r7, #24]
   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 8000a6a:	69fb      	ldr	r3, [r7, #28]
- 8000a6c:	3304      	adds	r3, #4
- 8000a6e:	2b06      	cmp	r3, #6
- 8000a70:	d902      	bls.n	8000a78 <NVIC_EncodePriority+0x30>
- 8000a72:	69fb      	ldr	r3, [r7, #28]
- 8000a74:	3b03      	subs	r3, #3
- 8000a76:	e000      	b.n	8000a7a <NVIC_EncodePriority+0x32>
- 8000a78:	2300      	movs	r3, #0
- 8000a7a:	617b      	str	r3, [r7, #20]
+ 8000b56:	69fb      	ldr	r3, [r7, #28]
+ 8000b58:	3304      	adds	r3, #4
+ 8000b5a:	2b06      	cmp	r3, #6
+ 8000b5c:	d902      	bls.n	8000b64 <NVIC_EncodePriority+0x30>
+ 8000b5e:	69fb      	ldr	r3, [r7, #28]
+ 8000b60:	3b03      	subs	r3, #3
+ 8000b62:	e000      	b.n	8000b66 <NVIC_EncodePriority+0x32>
+ 8000b64:	2300      	movs	r3, #0
+ 8000b66:	617b      	str	r3, [r7, #20]
 
   return (
            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000a7c:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
- 8000a80:	69bb      	ldr	r3, [r7, #24]
- 8000a82:	fa02 f303 	lsl.w	r3, r2, r3
- 8000a86:	43da      	mvns	r2, r3
- 8000a88:	68bb      	ldr	r3, [r7, #8]
- 8000a8a:	401a      	ands	r2, r3
- 8000a8c:	697b      	ldr	r3, [r7, #20]
- 8000a8e:	409a      	lsls	r2, r3
+ 8000b68:	f04f 32ff 	mov.w	r2, #4294967295	@ 0xffffffff
+ 8000b6c:	69bb      	ldr	r3, [r7, #24]
+ 8000b6e:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000b72:	43da      	mvns	r2, r3
+ 8000b74:	68bb      	ldr	r3, [r7, #8]
+ 8000b76:	401a      	ands	r2, r3
+ 8000b78:	697b      	ldr	r3, [r7, #20]
+ 8000b7a:	409a      	lsls	r2, r3
            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
- 8000a90:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
- 8000a94:	697b      	ldr	r3, [r7, #20]
- 8000a96:	fa01 f303 	lsl.w	r3, r1, r3
- 8000a9a:	43d9      	mvns	r1, r3
- 8000a9c:	687b      	ldr	r3, [r7, #4]
- 8000a9e:	400b      	ands	r3, r1
+ 8000b7c:	f04f 31ff 	mov.w	r1, #4294967295	@ 0xffffffff
+ 8000b80:	697b      	ldr	r3, [r7, #20]
+ 8000b82:	fa01 f303 	lsl.w	r3, r1, r3
+ 8000b86:	43d9      	mvns	r1, r3
+ 8000b88:	687b      	ldr	r3, [r7, #4]
+ 8000b8a:	400b      	ands	r3, r1
            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8000aa0:	4313      	orrs	r3, r2
+ 8000b8c:	4313      	orrs	r3, r2
          );
 }
- 8000aa2:	4618      	mov	r0, r3
- 8000aa4:	3724      	adds	r7, #36	@ 0x24
- 8000aa6:	46bd      	mov	sp, r7
- 8000aa8:	bc80      	pop	{r7}
- 8000aaa:	4770      	bx	lr
+ 8000b8e:	4618      	mov	r0, r3
+ 8000b90:	3724      	adds	r7, #36	@ 0x24
+ 8000b92:	46bd      	mov	sp, r7
+ 8000b94:	bc80      	pop	{r7}
+ 8000b96:	4770      	bx	lr
 
-08000aac <SysTick_Config>:
+08000b98 <SysTick_Config>:
   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
            must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
- 8000aac:	b580      	push	{r7, lr}
- 8000aae:	b082      	sub	sp, #8
- 8000ab0:	af00      	add	r7, sp, #0
- 8000ab2:	6078      	str	r0, [r7, #4]
+ 8000b98:	b580      	push	{r7, lr}
+ 8000b9a:	b082      	sub	sp, #8
+ 8000b9c:	af00      	add	r7, sp, #0
+ 8000b9e:	6078      	str	r0, [r7, #4]
   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8000ab4:	687b      	ldr	r3, [r7, #4]
- 8000ab6:	3b01      	subs	r3, #1
- 8000ab8:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
- 8000abc:	d301      	bcc.n	8000ac2 <SysTick_Config+0x16>
+ 8000ba0:	687b      	ldr	r3, [r7, #4]
+ 8000ba2:	3b01      	subs	r3, #1
+ 8000ba4:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 8000ba8:	d301      	bcc.n	8000bae <SysTick_Config+0x16>
   {
     return (1UL);                                                   /* Reload value impossible */
- 8000abe:	2301      	movs	r3, #1
- 8000ac0:	e00f      	b.n	8000ae2 <SysTick_Config+0x36>
+ 8000baa:	2301      	movs	r3, #1
+ 8000bac:	e00f      	b.n	8000bce <SysTick_Config+0x36>
   }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
- 8000ac2:	4a0a      	ldr	r2, [pc, #40]	@ (8000aec <SysTick_Config+0x40>)
- 8000ac4:	687b      	ldr	r3, [r7, #4]
- 8000ac6:	3b01      	subs	r3, #1
- 8000ac8:	6053      	str	r3, [r2, #4]
+ 8000bae:	4a0a      	ldr	r2, [pc, #40]	@ (8000bd8 <SysTick_Config+0x40>)
+ 8000bb0:	687b      	ldr	r3, [r7, #4]
+ 8000bb2:	3b01      	subs	r3, #1
+ 8000bb4:	6053      	str	r3, [r2, #4]
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8000aca:	210f      	movs	r1, #15
- 8000acc:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
- 8000ad0:	f7ff ff90 	bl	80009f4 <__NVIC_SetPriority>
+ 8000bb6:	210f      	movs	r1, #15
+ 8000bb8:	f04f 30ff 	mov.w	r0, #4294967295	@ 0xffffffff
+ 8000bbc:	f7ff ff90 	bl	8000ae0 <__NVIC_SetPriority>
   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
- 8000ad4:	4b05      	ldr	r3, [pc, #20]	@ (8000aec <SysTick_Config+0x40>)
- 8000ad6:	2200      	movs	r2, #0
- 8000ad8:	609a      	str	r2, [r3, #8]
+ 8000bc0:	4b05      	ldr	r3, [pc, #20]	@ (8000bd8 <SysTick_Config+0x40>)
+ 8000bc2:	2200      	movs	r2, #0
+ 8000bc4:	609a      	str	r2, [r3, #8]
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
- 8000ada:	4b04      	ldr	r3, [pc, #16]	@ (8000aec <SysTick_Config+0x40>)
- 8000adc:	2207      	movs	r2, #7
- 8000ade:	601a      	str	r2, [r3, #0]
+ 8000bc6:	4b04      	ldr	r3, [pc, #16]	@ (8000bd8 <SysTick_Config+0x40>)
+ 8000bc8:	2207      	movs	r2, #7
+ 8000bca:	601a      	str	r2, [r3, #0]
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
   return (0UL);                                                     /* Function successful */
- 8000ae0:	2300      	movs	r3, #0
+ 8000bcc:	2300      	movs	r3, #0
 }
- 8000ae2:	4618      	mov	r0, r3
- 8000ae4:	3708      	adds	r7, #8
- 8000ae6:	46bd      	mov	sp, r7
- 8000ae8:	bd80      	pop	{r7, pc}
- 8000aea:	bf00      	nop
- 8000aec:	e000e010 	.word	0xe000e010
+ 8000bce:	4618      	mov	r0, r3
+ 8000bd0:	3708      	adds	r7, #8
+ 8000bd2:	46bd      	mov	sp, r7
+ 8000bd4:	bd80      	pop	{r7, pc}
+ 8000bd6:	bf00      	nop
+ 8000bd8:	e000e010 	.word	0xe000e010
 
-08000af0 <HAL_NVIC_SetPriorityGrouping>:
+08000bdc <HAL_NVIC_SetPriorityGrouping>:
   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
   *         The pending IRQ priority will be managed only by the subpriority. 
   * @retval None
   */
 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
- 8000af0:	b580      	push	{r7, lr}
- 8000af2:	b082      	sub	sp, #8
- 8000af4:	af00      	add	r7, sp, #0
- 8000af6:	6078      	str	r0, [r7, #4]
+ 8000bdc:	b580      	push	{r7, lr}
+ 8000bde:	b082      	sub	sp, #8
+ 8000be0:	af00      	add	r7, sp, #0
+ 8000be2:	6078      	str	r0, [r7, #4]
   /* Check the parameters */
   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
   
   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
   NVIC_SetPriorityGrouping(PriorityGroup);
- 8000af8:	6878      	ldr	r0, [r7, #4]
- 8000afa:	f7ff ff2d 	bl	8000958 <__NVIC_SetPriorityGrouping>
+ 8000be4:	6878      	ldr	r0, [r7, #4]
+ 8000be6:	f7ff ff2d 	bl	8000a44 <__NVIC_SetPriorityGrouping>
 }
- 8000afe:	bf00      	nop
- 8000b00:	3708      	adds	r7, #8
- 8000b02:	46bd      	mov	sp, r7
- 8000b04:	bd80      	pop	{r7, pc}
+ 8000bea:	bf00      	nop
+ 8000bec:	3708      	adds	r7, #8
+ 8000bee:	46bd      	mov	sp, r7
+ 8000bf0:	bd80      	pop	{r7, pc}
 
-08000b06 <HAL_NVIC_SetPriority>:
+08000bf2 <HAL_NVIC_SetPriority>:
   *         This parameter can be a value between 0 and 15
   *         A lower priority value indicates a higher priority.          
   * @retval None
   */
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 {
- 8000b06:	b580      	push	{r7, lr}
- 8000b08:	b086      	sub	sp, #24
- 8000b0a:	af00      	add	r7, sp, #0
- 8000b0c:	4603      	mov	r3, r0
- 8000b0e:	60b9      	str	r1, [r7, #8]
- 8000b10:	607a      	str	r2, [r7, #4]
- 8000b12:	73fb      	strb	r3, [r7, #15]
+ 8000bf2:	b580      	push	{r7, lr}
+ 8000bf4:	b086      	sub	sp, #24
+ 8000bf6:	af00      	add	r7, sp, #0
+ 8000bf8:	4603      	mov	r3, r0
+ 8000bfa:	60b9      	str	r1, [r7, #8]
+ 8000bfc:	607a      	str	r2, [r7, #4]
+ 8000bfe:	73fb      	strb	r3, [r7, #15]
   uint32_t prioritygroup = 0x00;
- 8000b14:	2300      	movs	r3, #0
- 8000b16:	617b      	str	r3, [r7, #20]
+ 8000c00:	2300      	movs	r3, #0
+ 8000c02:	617b      	str	r3, [r7, #20]
   
   /* Check the parameters */
   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
   
   prioritygroup = NVIC_GetPriorityGrouping();
- 8000b18:	f7ff ff42 	bl	80009a0 <__NVIC_GetPriorityGrouping>
- 8000b1c:	6178      	str	r0, [r7, #20]
+ 8000c04:	f7ff ff42 	bl	8000a8c <__NVIC_GetPriorityGrouping>
+ 8000c08:	6178      	str	r0, [r7, #20]
   
   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 8000b1e:	687a      	ldr	r2, [r7, #4]
- 8000b20:	68b9      	ldr	r1, [r7, #8]
- 8000b22:	6978      	ldr	r0, [r7, #20]
- 8000b24:	f7ff ff90 	bl	8000a48 <NVIC_EncodePriority>
- 8000b28:	4602      	mov	r2, r0
- 8000b2a:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 8000b2e:	4611      	mov	r1, r2
- 8000b30:	4618      	mov	r0, r3
- 8000b32:	f7ff ff5f 	bl	80009f4 <__NVIC_SetPriority>
+ 8000c0a:	687a      	ldr	r2, [r7, #4]
+ 8000c0c:	68b9      	ldr	r1, [r7, #8]
+ 8000c0e:	6978      	ldr	r0, [r7, #20]
+ 8000c10:	f7ff ff90 	bl	8000b34 <NVIC_EncodePriority>
+ 8000c14:	4602      	mov	r2, r0
+ 8000c16:	f997 300f 	ldrsb.w	r3, [r7, #15]
+ 8000c1a:	4611      	mov	r1, r2
+ 8000c1c:	4618      	mov	r0, r3
+ 8000c1e:	f7ff ff5f 	bl	8000ae0 <__NVIC_SetPriority>
 }
- 8000b36:	bf00      	nop
- 8000b38:	3718      	adds	r7, #24
- 8000b3a:	46bd      	mov	sp, r7
- 8000b3c:	bd80      	pop	{r7, pc}
+ 8000c22:	bf00      	nop
+ 8000c24:	3718      	adds	r7, #24
+ 8000c26:	46bd      	mov	sp, r7
+ 8000c28:	bd80      	pop	{r7, pc}
 
-08000b3e <HAL_NVIC_EnableIRQ>:
+08000c2a <HAL_NVIC_EnableIRQ>:
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
   * @retval None
   */
 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
 {
- 8000b3e:	b580      	push	{r7, lr}
- 8000b40:	b082      	sub	sp, #8
- 8000b42:	af00      	add	r7, sp, #0
- 8000b44:	4603      	mov	r3, r0
- 8000b46:	71fb      	strb	r3, [r7, #7]
+ 8000c2a:	b580      	push	{r7, lr}
+ 8000c2c:	b082      	sub	sp, #8
+ 8000c2e:	af00      	add	r7, sp, #0
+ 8000c30:	4603      	mov	r3, r0
+ 8000c32:	71fb      	strb	r3, [r7, #7]
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
   
   /* Enable interrupt */
   NVIC_EnableIRQ(IRQn);
- 8000b48:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 8000b4c:	4618      	mov	r0, r3
- 8000b4e:	f7ff ff35 	bl	80009bc <__NVIC_EnableIRQ>
+ 8000c34:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 8000c38:	4618      	mov	r0, r3
+ 8000c3a:	f7ff ff35 	bl	8000aa8 <__NVIC_EnableIRQ>
 }
- 8000b52:	bf00      	nop
- 8000b54:	3708      	adds	r7, #8
- 8000b56:	46bd      	mov	sp, r7
- 8000b58:	bd80      	pop	{r7, pc}
+ 8000c3e:	bf00      	nop
+ 8000c40:	3708      	adds	r7, #8
+ 8000c42:	46bd      	mov	sp, r7
+ 8000c44:	bd80      	pop	{r7, pc}
 
-08000b5a <HAL_SYSTICK_Config>:
+08000c46 <HAL_SYSTICK_Config>:
   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
   * @retval status:  - 0  Function succeeded.
   *                  - 1  Function failed.
   */
 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
 {
- 8000b5a:	b580      	push	{r7, lr}
- 8000b5c:	b082      	sub	sp, #8
- 8000b5e:	af00      	add	r7, sp, #0
- 8000b60:	6078      	str	r0, [r7, #4]
+ 8000c46:	b580      	push	{r7, lr}
+ 8000c48:	b082      	sub	sp, #8
+ 8000c4a:	af00      	add	r7, sp, #0
+ 8000c4c:	6078      	str	r0, [r7, #4]
    return SysTick_Config(TicksNumb);
- 8000b62:	6878      	ldr	r0, [r7, #4]
- 8000b64:	f7ff ffa2 	bl	8000aac <SysTick_Config>
- 8000b68:	4603      	mov	r3, r0
+ 8000c4e:	6878      	ldr	r0, [r7, #4]
+ 8000c50:	f7ff ffa2 	bl	8000b98 <SysTick_Config>
+ 8000c54:	4603      	mov	r3, r0
 }
- 8000b6a:	4618      	mov	r0, r3
- 8000b6c:	3708      	adds	r7, #8
- 8000b6e:	46bd      	mov	sp, r7
- 8000b70:	bd80      	pop	{r7, pc}
+ 8000c56:	4618      	mov	r0, r3
+ 8000c58:	3708      	adds	r7, #8
+ 8000c5a:	46bd      	mov	sp, r7
+ 8000c5c:	bd80      	pop	{r7, pc}
 	...
 
-08000b74 <HAL_GPIO_Init>:
+08000c60 <HAL_GPIO_Init>:
   * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
   *         the configuration information for the specified GPIO peripheral.
   * @retval None
   */
 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 {
- 8000b74:	b480      	push	{r7}
- 8000b76:	b087      	sub	sp, #28
- 8000b78:	af00      	add	r7, sp, #0
- 8000b7a:	6078      	str	r0, [r7, #4]
- 8000b7c:	6039      	str	r1, [r7, #0]
+ 8000c60:	b480      	push	{r7}
+ 8000c62:	b087      	sub	sp, #28
+ 8000c64:	af00      	add	r7, sp, #0
+ 8000c66:	6078      	str	r0, [r7, #4]
+ 8000c68:	6039      	str	r1, [r7, #0]
   uint32_t position = 0x00;
- 8000b7e:	2300      	movs	r3, #0
- 8000b80:	617b      	str	r3, [r7, #20]
+ 8000c6a:	2300      	movs	r3, #0
+ 8000c6c:	617b      	str	r3, [r7, #20]
   uint32_t iocurrent = 0x00;
- 8000b82:	2300      	movs	r3, #0
- 8000b84:	60fb      	str	r3, [r7, #12]
+ 8000c6e:	2300      	movs	r3, #0
+ 8000c70:	60fb      	str	r3, [r7, #12]
   uint32_t temp = 0x00;
- 8000b86:	2300      	movs	r3, #0
- 8000b88:	613b      	str	r3, [r7, #16]
+ 8000c72:	2300      	movs	r3, #0
+ 8000c74:	613b      	str	r3, [r7, #16]
   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
 
   /* Configure the port pins */
   while (((GPIO_Init->Pin) >> position) != 0)
- 8000b8a:	e160      	b.n	8000e4e <HAL_GPIO_Init+0x2da>
+ 8000c76:	e160      	b.n	8000f3a <HAL_GPIO_Init+0x2da>
   {
     /* Get current io position */
     iocurrent = (GPIO_Init->Pin) & (1U << position);
- 8000b8c:	683b      	ldr	r3, [r7, #0]
- 8000b8e:	681a      	ldr	r2, [r3, #0]
- 8000b90:	2101      	movs	r1, #1
- 8000b92:	697b      	ldr	r3, [r7, #20]
- 8000b94:	fa01 f303 	lsl.w	r3, r1, r3
- 8000b98:	4013      	ands	r3, r2
- 8000b9a:	60fb      	str	r3, [r7, #12]
+ 8000c78:	683b      	ldr	r3, [r7, #0]
+ 8000c7a:	681a      	ldr	r2, [r3, #0]
+ 8000c7c:	2101      	movs	r1, #1
+ 8000c7e:	697b      	ldr	r3, [r7, #20]
+ 8000c80:	fa01 f303 	lsl.w	r3, r1, r3
+ 8000c84:	4013      	ands	r3, r2
+ 8000c86:	60fb      	str	r3, [r7, #12]
 
     if (iocurrent)
- 8000b9c:	68fb      	ldr	r3, [r7, #12]
- 8000b9e:	2b00      	cmp	r3, #0
- 8000ba0:	f000 8152 	beq.w	8000e48 <HAL_GPIO_Init+0x2d4>
+ 8000c88:	68fb      	ldr	r3, [r7, #12]
+ 8000c8a:	2b00      	cmp	r3, #0
+ 8000c8c:	f000 8152 	beq.w	8000f34 <HAL_GPIO_Init+0x2d4>
     {
       /*--------------------- GPIO Mode Configuration ------------------------*/
       /* In case of Output or Alternate function mode selection */
       if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
- 8000ba4:	683b      	ldr	r3, [r7, #0]
- 8000ba6:	685b      	ldr	r3, [r3, #4]
- 8000ba8:	f003 0303 	and.w	r3, r3, #3
- 8000bac:	2b01      	cmp	r3, #1
- 8000bae:	d005      	beq.n	8000bbc <HAL_GPIO_Init+0x48>
+ 8000c90:	683b      	ldr	r3, [r7, #0]
+ 8000c92:	685b      	ldr	r3, [r3, #4]
+ 8000c94:	f003 0303 	and.w	r3, r3, #3
+ 8000c98:	2b01      	cmp	r3, #1
+ 8000c9a:	d005      	beq.n	8000ca8 <HAL_GPIO_Init+0x48>
           ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
- 8000bb0:	683b      	ldr	r3, [r7, #0]
- 8000bb2:	685b      	ldr	r3, [r3, #4]
- 8000bb4:	f003 0303 	and.w	r3, r3, #3
+ 8000c9c:	683b      	ldr	r3, [r7, #0]
+ 8000c9e:	685b      	ldr	r3, [r3, #4]
+ 8000ca0:	f003 0303 	and.w	r3, r3, #3
       if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
- 8000bb8:	2b02      	cmp	r3, #2
- 8000bba:	d130      	bne.n	8000c1e <HAL_GPIO_Init+0xaa>
+ 8000ca4:	2b02      	cmp	r3, #2
+ 8000ca6:	d130      	bne.n	8000d0a <HAL_GPIO_Init+0xaa>
       {
         /* Check the Speed parameter */
         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
         /* Configure the IO Speed */
         temp = GPIOx->OSPEEDR;
- 8000bbc:	687b      	ldr	r3, [r7, #4]
- 8000bbe:	689b      	ldr	r3, [r3, #8]
- 8000bc0:	613b      	str	r3, [r7, #16]
+ 8000ca8:	687b      	ldr	r3, [r7, #4]
+ 8000caa:	689b      	ldr	r3, [r3, #8]
+ 8000cac:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- 8000bc2:	697b      	ldr	r3, [r7, #20]
- 8000bc4:	005b      	lsls	r3, r3, #1
- 8000bc6:	2203      	movs	r2, #3
- 8000bc8:	fa02 f303 	lsl.w	r3, r2, r3
- 8000bcc:	43db      	mvns	r3, r3
- 8000bce:	693a      	ldr	r2, [r7, #16]
- 8000bd0:	4013      	ands	r3, r2
- 8000bd2:	613b      	str	r3, [r7, #16]
+ 8000cae:	697b      	ldr	r3, [r7, #20]
+ 8000cb0:	005b      	lsls	r3, r3, #1
+ 8000cb2:	2203      	movs	r2, #3
+ 8000cb4:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000cb8:	43db      	mvns	r3, r3
+ 8000cba:	693a      	ldr	r2, [r7, #16]
+ 8000cbc:	4013      	ands	r3, r2
+ 8000cbe:	613b      	str	r3, [r7, #16]
         SET_BIT(temp, GPIO_Init->Speed << (position * 2));
- 8000bd4:	683b      	ldr	r3, [r7, #0]
- 8000bd6:	68da      	ldr	r2, [r3, #12]
- 8000bd8:	697b      	ldr	r3, [r7, #20]
- 8000bda:	005b      	lsls	r3, r3, #1
- 8000bdc:	fa02 f303 	lsl.w	r3, r2, r3
- 8000be0:	693a      	ldr	r2, [r7, #16]
- 8000be2:	4313      	orrs	r3, r2
- 8000be4:	613b      	str	r3, [r7, #16]
+ 8000cc0:	683b      	ldr	r3, [r7, #0]
+ 8000cc2:	68da      	ldr	r2, [r3, #12]
+ 8000cc4:	697b      	ldr	r3, [r7, #20]
+ 8000cc6:	005b      	lsls	r3, r3, #1
+ 8000cc8:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000ccc:	693a      	ldr	r2, [r7, #16]
+ 8000cce:	4313      	orrs	r3, r2
+ 8000cd0:	613b      	str	r3, [r7, #16]
         GPIOx->OSPEEDR = temp;
- 8000be6:	687b      	ldr	r3, [r7, #4]
- 8000be8:	693a      	ldr	r2, [r7, #16]
- 8000bea:	609a      	str	r2, [r3, #8]
+ 8000cd2:	687b      	ldr	r3, [r7, #4]
+ 8000cd4:	693a      	ldr	r2, [r7, #16]
+ 8000cd6:	609a      	str	r2, [r3, #8]
 
         /* Configure the IO Output Type */
         temp = GPIOx->OTYPER;
- 8000bec:	687b      	ldr	r3, [r7, #4]
- 8000bee:	685b      	ldr	r3, [r3, #4]
- 8000bf0:	613b      	str	r3, [r7, #16]
+ 8000cd8:	687b      	ldr	r3, [r7, #4]
+ 8000cda:	685b      	ldr	r3, [r3, #4]
+ 8000cdc:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
- 8000bf2:	2201      	movs	r2, #1
- 8000bf4:	697b      	ldr	r3, [r7, #20]
- 8000bf6:	fa02 f303 	lsl.w	r3, r2, r3
- 8000bfa:	43db      	mvns	r3, r3
- 8000bfc:	693a      	ldr	r2, [r7, #16]
- 8000bfe:	4013      	ands	r3, r2
- 8000c00:	613b      	str	r3, [r7, #16]
+ 8000cde:	2201      	movs	r2, #1
+ 8000ce0:	697b      	ldr	r3, [r7, #20]
+ 8000ce2:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000ce6:	43db      	mvns	r3, r3
+ 8000ce8:	693a      	ldr	r2, [r7, #16]
+ 8000cea:	4013      	ands	r3, r2
+ 8000cec:	613b      	str	r3, [r7, #16]
         SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
- 8000c02:	683b      	ldr	r3, [r7, #0]
- 8000c04:	685b      	ldr	r3, [r3, #4]
- 8000c06:	091b      	lsrs	r3, r3, #4
- 8000c08:	f003 0201 	and.w	r2, r3, #1
- 8000c0c:	697b      	ldr	r3, [r7, #20]
- 8000c0e:	fa02 f303 	lsl.w	r3, r2, r3
- 8000c12:	693a      	ldr	r2, [r7, #16]
- 8000c14:	4313      	orrs	r3, r2
- 8000c16:	613b      	str	r3, [r7, #16]
+ 8000cee:	683b      	ldr	r3, [r7, #0]
+ 8000cf0:	685b      	ldr	r3, [r3, #4]
+ 8000cf2:	091b      	lsrs	r3, r3, #4
+ 8000cf4:	f003 0201 	and.w	r2, r3, #1
+ 8000cf8:	697b      	ldr	r3, [r7, #20]
+ 8000cfa:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000cfe:	693a      	ldr	r2, [r7, #16]
+ 8000d00:	4313      	orrs	r3, r2
+ 8000d02:	613b      	str	r3, [r7, #16]
         GPIOx->OTYPER = temp;
- 8000c18:	687b      	ldr	r3, [r7, #4]
- 8000c1a:	693a      	ldr	r2, [r7, #16]
- 8000c1c:	605a      	str	r2, [r3, #4]
+ 8000d04:	687b      	ldr	r3, [r7, #4]
+ 8000d06:	693a      	ldr	r2, [r7, #16]
+ 8000d08:	605a      	str	r2, [r3, #4]
       }
 
       if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
- 8000c1e:	683b      	ldr	r3, [r7, #0]
- 8000c20:	685b      	ldr	r3, [r3, #4]
- 8000c22:	f003 0303 	and.w	r3, r3, #3
- 8000c26:	2b03      	cmp	r3, #3
- 8000c28:	d017      	beq.n	8000c5a <HAL_GPIO_Init+0xe6>
+ 8000d0a:	683b      	ldr	r3, [r7, #0]
+ 8000d0c:	685b      	ldr	r3, [r3, #4]
+ 8000d0e:	f003 0303 	and.w	r3, r3, #3
+ 8000d12:	2b03      	cmp	r3, #3
+ 8000d14:	d017      	beq.n	8000d46 <HAL_GPIO_Init+0xe6>
       {
         /* Check the Pull parameter */
         assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
 
         /* Activate the Pull-up or Pull down resistor for the current IO */
         temp = GPIOx->PUPDR;
- 8000c2a:	687b      	ldr	r3, [r7, #4]
- 8000c2c:	68db      	ldr	r3, [r3, #12]
- 8000c2e:	613b      	str	r3, [r7, #16]
+ 8000d16:	687b      	ldr	r3, [r7, #4]
+ 8000d18:	68db      	ldr	r3, [r3, #12]
+ 8000d1a:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
- 8000c30:	697b      	ldr	r3, [r7, #20]
- 8000c32:	005b      	lsls	r3, r3, #1
- 8000c34:	2203      	movs	r2, #3
- 8000c36:	fa02 f303 	lsl.w	r3, r2, r3
- 8000c3a:	43db      	mvns	r3, r3
- 8000c3c:	693a      	ldr	r2, [r7, #16]
- 8000c3e:	4013      	ands	r3, r2
- 8000c40:	613b      	str	r3, [r7, #16]
+ 8000d1c:	697b      	ldr	r3, [r7, #20]
+ 8000d1e:	005b      	lsls	r3, r3, #1
+ 8000d20:	2203      	movs	r2, #3
+ 8000d22:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000d26:	43db      	mvns	r3, r3
+ 8000d28:	693a      	ldr	r2, [r7, #16]
+ 8000d2a:	4013      	ands	r3, r2
+ 8000d2c:	613b      	str	r3, [r7, #16]
         SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
- 8000c42:	683b      	ldr	r3, [r7, #0]
- 8000c44:	689a      	ldr	r2, [r3, #8]
- 8000c46:	697b      	ldr	r3, [r7, #20]
- 8000c48:	005b      	lsls	r3, r3, #1
- 8000c4a:	fa02 f303 	lsl.w	r3, r2, r3
- 8000c4e:	693a      	ldr	r2, [r7, #16]
- 8000c50:	4313      	orrs	r3, r2
- 8000c52:	613b      	str	r3, [r7, #16]
+ 8000d2e:	683b      	ldr	r3, [r7, #0]
+ 8000d30:	689a      	ldr	r2, [r3, #8]
+ 8000d32:	697b      	ldr	r3, [r7, #20]
+ 8000d34:	005b      	lsls	r3, r3, #1
+ 8000d36:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000d3a:	693a      	ldr	r2, [r7, #16]
+ 8000d3c:	4313      	orrs	r3, r2
+ 8000d3e:	613b      	str	r3, [r7, #16]
         GPIOx->PUPDR = temp;
- 8000c54:	687b      	ldr	r3, [r7, #4]
- 8000c56:	693a      	ldr	r2, [r7, #16]
- 8000c58:	60da      	str	r2, [r3, #12]
+ 8000d40:	687b      	ldr	r3, [r7, #4]
+ 8000d42:	693a      	ldr	r2, [r7, #16]
+ 8000d44:	60da      	str	r2, [r3, #12]
       }
 
       /* In case of Alternate function mode selection */
       if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
- 8000c5a:	683b      	ldr	r3, [r7, #0]
- 8000c5c:	685b      	ldr	r3, [r3, #4]
- 8000c5e:	f003 0303 	and.w	r3, r3, #3
- 8000c62:	2b02      	cmp	r3, #2
- 8000c64:	d123      	bne.n	8000cae <HAL_GPIO_Init+0x13a>
+ 8000d46:	683b      	ldr	r3, [r7, #0]
+ 8000d48:	685b      	ldr	r3, [r3, #4]
+ 8000d4a:	f003 0303 	and.w	r3, r3, #3
+ 8000d4e:	2b02      	cmp	r3, #2
+ 8000d50:	d123      	bne.n	8000d9a <HAL_GPIO_Init+0x13a>
         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
 
         /* Configure Alternate function mapped with the current IO */
         /* Identify AFRL or AFRH register based on IO position*/
         temp = GPIOx->AFR[position >> 3];
- 8000c66:	697b      	ldr	r3, [r7, #20]
- 8000c68:	08da      	lsrs	r2, r3, #3
- 8000c6a:	687b      	ldr	r3, [r7, #4]
- 8000c6c:	3208      	adds	r2, #8
- 8000c6e:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 8000c72:	613b      	str	r3, [r7, #16]
+ 8000d52:	697b      	ldr	r3, [r7, #20]
+ 8000d54:	08da      	lsrs	r2, r3, #3
+ 8000d56:	687b      	ldr	r3, [r7, #4]
+ 8000d58:	3208      	adds	r2, #8
+ 8000d5a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 8000d5e:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
- 8000c74:	697b      	ldr	r3, [r7, #20]
- 8000c76:	f003 0307 	and.w	r3, r3, #7
- 8000c7a:	009b      	lsls	r3, r3, #2
- 8000c7c:	220f      	movs	r2, #15
- 8000c7e:	fa02 f303 	lsl.w	r3, r2, r3
- 8000c82:	43db      	mvns	r3, r3
- 8000c84:	693a      	ldr	r2, [r7, #16]
- 8000c86:	4013      	ands	r3, r2
- 8000c88:	613b      	str	r3, [r7, #16]
+ 8000d60:	697b      	ldr	r3, [r7, #20]
+ 8000d62:	f003 0307 	and.w	r3, r3, #7
+ 8000d66:	009b      	lsls	r3, r3, #2
+ 8000d68:	220f      	movs	r2, #15
+ 8000d6a:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000d6e:	43db      	mvns	r3, r3
+ 8000d70:	693a      	ldr	r2, [r7, #16]
+ 8000d72:	4013      	ands	r3, r2
+ 8000d74:	613b      	str	r3, [r7, #16]
         SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
- 8000c8a:	683b      	ldr	r3, [r7, #0]
- 8000c8c:	691a      	ldr	r2, [r3, #16]
- 8000c8e:	697b      	ldr	r3, [r7, #20]
- 8000c90:	f003 0307 	and.w	r3, r3, #7
- 8000c94:	009b      	lsls	r3, r3, #2
- 8000c96:	fa02 f303 	lsl.w	r3, r2, r3
- 8000c9a:	693a      	ldr	r2, [r7, #16]
- 8000c9c:	4313      	orrs	r3, r2
- 8000c9e:	613b      	str	r3, [r7, #16]
+ 8000d76:	683b      	ldr	r3, [r7, #0]
+ 8000d78:	691a      	ldr	r2, [r3, #16]
+ 8000d7a:	697b      	ldr	r3, [r7, #20]
+ 8000d7c:	f003 0307 	and.w	r3, r3, #7
+ 8000d80:	009b      	lsls	r3, r3, #2
+ 8000d82:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000d86:	693a      	ldr	r2, [r7, #16]
+ 8000d88:	4313      	orrs	r3, r2
+ 8000d8a:	613b      	str	r3, [r7, #16]
         GPIOx->AFR[position >> 3] = temp;
- 8000ca0:	697b      	ldr	r3, [r7, #20]
- 8000ca2:	08da      	lsrs	r2, r3, #3
- 8000ca4:	687b      	ldr	r3, [r7, #4]
- 8000ca6:	3208      	adds	r2, #8
- 8000ca8:	6939      	ldr	r1, [r7, #16]
- 8000caa:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
+ 8000d8c:	697b      	ldr	r3, [r7, #20]
+ 8000d8e:	08da      	lsrs	r2, r3, #3
+ 8000d90:	687b      	ldr	r3, [r7, #4]
+ 8000d92:	3208      	adds	r2, #8
+ 8000d94:	6939      	ldr	r1, [r7, #16]
+ 8000d96:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
       }
 
       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
       temp = GPIOx->MODER;
- 8000cae:	687b      	ldr	r3, [r7, #4]
- 8000cb0:	681b      	ldr	r3, [r3, #0]
- 8000cb2:	613b      	str	r3, [r7, #16]
+ 8000d9a:	687b      	ldr	r3, [r7, #4]
+ 8000d9c:	681b      	ldr	r3, [r3, #0]
+ 8000d9e:	613b      	str	r3, [r7, #16]
       CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
- 8000cb4:	697b      	ldr	r3, [r7, #20]
- 8000cb6:	005b      	lsls	r3, r3, #1
- 8000cb8:	2203      	movs	r2, #3
- 8000cba:	fa02 f303 	lsl.w	r3, r2, r3
- 8000cbe:	43db      	mvns	r3, r3
- 8000cc0:	693a      	ldr	r2, [r7, #16]
- 8000cc2:	4013      	ands	r3, r2
- 8000cc4:	613b      	str	r3, [r7, #16]
+ 8000da0:	697b      	ldr	r3, [r7, #20]
+ 8000da2:	005b      	lsls	r3, r3, #1
+ 8000da4:	2203      	movs	r2, #3
+ 8000da6:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000daa:	43db      	mvns	r3, r3
+ 8000dac:	693a      	ldr	r2, [r7, #16]
+ 8000dae:	4013      	ands	r3, r2
+ 8000db0:	613b      	str	r3, [r7, #16]
       SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
- 8000cc6:	683b      	ldr	r3, [r7, #0]
- 8000cc8:	685b      	ldr	r3, [r3, #4]
- 8000cca:	f003 0203 	and.w	r2, r3, #3
- 8000cce:	697b      	ldr	r3, [r7, #20]
- 8000cd0:	005b      	lsls	r3, r3, #1
- 8000cd2:	fa02 f303 	lsl.w	r3, r2, r3
- 8000cd6:	693a      	ldr	r2, [r7, #16]
- 8000cd8:	4313      	orrs	r3, r2
- 8000cda:	613b      	str	r3, [r7, #16]
+ 8000db2:	683b      	ldr	r3, [r7, #0]
+ 8000db4:	685b      	ldr	r3, [r3, #4]
+ 8000db6:	f003 0203 	and.w	r2, r3, #3
+ 8000dba:	697b      	ldr	r3, [r7, #20]
+ 8000dbc:	005b      	lsls	r3, r3, #1
+ 8000dbe:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000dc2:	693a      	ldr	r2, [r7, #16]
+ 8000dc4:	4313      	orrs	r3, r2
+ 8000dc6:	613b      	str	r3, [r7, #16]
       GPIOx->MODER = temp;
- 8000cdc:	687b      	ldr	r3, [r7, #4]
- 8000cde:	693a      	ldr	r2, [r7, #16]
- 8000ce0:	601a      	str	r2, [r3, #0]
+ 8000dc8:	687b      	ldr	r3, [r7, #4]
+ 8000dca:	693a      	ldr	r2, [r7, #16]
+ 8000dcc:	601a      	str	r2, [r3, #0]
 
       /*--------------------- EXTI Mode Configuration ------------------------*/
       /* Configure the External Interrupt or event for the current IO */
       if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
- 8000ce2:	683b      	ldr	r3, [r7, #0]
- 8000ce4:	685b      	ldr	r3, [r3, #4]
- 8000ce6:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
- 8000cea:	2b00      	cmp	r3, #0
- 8000cec:	f000 80ac 	beq.w	8000e48 <HAL_GPIO_Init+0x2d4>
+ 8000dce:	683b      	ldr	r3, [r7, #0]
+ 8000dd0:	685b      	ldr	r3, [r3, #4]
+ 8000dd2:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
+ 8000dd6:	2b00      	cmp	r3, #0
+ 8000dd8:	f000 80ac 	beq.w	8000f34 <HAL_GPIO_Init+0x2d4>
       {
         /* Enable SYSCFG Clock */
         __HAL_RCC_SYSCFG_CLK_ENABLE();
- 8000cf0:	4b5e      	ldr	r3, [pc, #376]	@ (8000e6c <HAL_GPIO_Init+0x2f8>)
- 8000cf2:	6a1b      	ldr	r3, [r3, #32]
- 8000cf4:	4a5d      	ldr	r2, [pc, #372]	@ (8000e6c <HAL_GPIO_Init+0x2f8>)
- 8000cf6:	f043 0301 	orr.w	r3, r3, #1
- 8000cfa:	6213      	str	r3, [r2, #32]
- 8000cfc:	4b5b      	ldr	r3, [pc, #364]	@ (8000e6c <HAL_GPIO_Init+0x2f8>)
- 8000cfe:	6a1b      	ldr	r3, [r3, #32]
- 8000d00:	f003 0301 	and.w	r3, r3, #1
- 8000d04:	60bb      	str	r3, [r7, #8]
- 8000d06:	68bb      	ldr	r3, [r7, #8]
+ 8000ddc:	4b5e      	ldr	r3, [pc, #376]	@ (8000f58 <HAL_GPIO_Init+0x2f8>)
+ 8000dde:	6a1b      	ldr	r3, [r3, #32]
+ 8000de0:	4a5d      	ldr	r2, [pc, #372]	@ (8000f58 <HAL_GPIO_Init+0x2f8>)
+ 8000de2:	f043 0301 	orr.w	r3, r3, #1
+ 8000de6:	6213      	str	r3, [r2, #32]
+ 8000de8:	4b5b      	ldr	r3, [pc, #364]	@ (8000f58 <HAL_GPIO_Init+0x2f8>)
+ 8000dea:	6a1b      	ldr	r3, [r3, #32]
+ 8000dec:	f003 0301 	and.w	r3, r3, #1
+ 8000df0:	60bb      	str	r3, [r7, #8]
+ 8000df2:	68bb      	ldr	r3, [r7, #8]
 
         temp = SYSCFG->EXTICR[position >> 2];
- 8000d08:	4a59      	ldr	r2, [pc, #356]	@ (8000e70 <HAL_GPIO_Init+0x2fc>)
- 8000d0a:	697b      	ldr	r3, [r7, #20]
- 8000d0c:	089b      	lsrs	r3, r3, #2
- 8000d0e:	3302      	adds	r3, #2
- 8000d10:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 8000d14:	613b      	str	r3, [r7, #16]
+ 8000df4:	4a59      	ldr	r2, [pc, #356]	@ (8000f5c <HAL_GPIO_Init+0x2fc>)
+ 8000df6:	697b      	ldr	r3, [r7, #20]
+ 8000df8:	089b      	lsrs	r3, r3, #2
+ 8000dfa:	3302      	adds	r3, #2
+ 8000dfc:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8000e00:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
- 8000d16:	697b      	ldr	r3, [r7, #20]
- 8000d18:	f003 0303 	and.w	r3, r3, #3
- 8000d1c:	009b      	lsls	r3, r3, #2
- 8000d1e:	220f      	movs	r2, #15
- 8000d20:	fa02 f303 	lsl.w	r3, r2, r3
- 8000d24:	43db      	mvns	r3, r3
- 8000d26:	693a      	ldr	r2, [r7, #16]
- 8000d28:	4013      	ands	r3, r2
- 8000d2a:	613b      	str	r3, [r7, #16]
+ 8000e02:	697b      	ldr	r3, [r7, #20]
+ 8000e04:	f003 0303 	and.w	r3, r3, #3
+ 8000e08:	009b      	lsls	r3, r3, #2
+ 8000e0a:	220f      	movs	r2, #15
+ 8000e0c:	fa02 f303 	lsl.w	r3, r2, r3
+ 8000e10:	43db      	mvns	r3, r3
+ 8000e12:	693a      	ldr	r2, [r7, #16]
+ 8000e14:	4013      	ands	r3, r2
+ 8000e16:	613b      	str	r3, [r7, #16]
         SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- 8000d2c:	687b      	ldr	r3, [r7, #4]
- 8000d2e:	4a51      	ldr	r2, [pc, #324]	@ (8000e74 <HAL_GPIO_Init+0x300>)
- 8000d30:	4293      	cmp	r3, r2
- 8000d32:	d025      	beq.n	8000d80 <HAL_GPIO_Init+0x20c>
- 8000d34:	687b      	ldr	r3, [r7, #4]
- 8000d36:	4a50      	ldr	r2, [pc, #320]	@ (8000e78 <HAL_GPIO_Init+0x304>)
- 8000d38:	4293      	cmp	r3, r2
- 8000d3a:	d01f      	beq.n	8000d7c <HAL_GPIO_Init+0x208>
- 8000d3c:	687b      	ldr	r3, [r7, #4]
- 8000d3e:	4a4f      	ldr	r2, [pc, #316]	@ (8000e7c <HAL_GPIO_Init+0x308>)
- 8000d40:	4293      	cmp	r3, r2
- 8000d42:	d019      	beq.n	8000d78 <HAL_GPIO_Init+0x204>
- 8000d44:	687b      	ldr	r3, [r7, #4]
- 8000d46:	4a4e      	ldr	r2, [pc, #312]	@ (8000e80 <HAL_GPIO_Init+0x30c>)
- 8000d48:	4293      	cmp	r3, r2
- 8000d4a:	d013      	beq.n	8000d74 <HAL_GPIO_Init+0x200>
- 8000d4c:	687b      	ldr	r3, [r7, #4]
- 8000d4e:	4a4d      	ldr	r2, [pc, #308]	@ (8000e84 <HAL_GPIO_Init+0x310>)
- 8000d50:	4293      	cmp	r3, r2
- 8000d52:	d00d      	beq.n	8000d70 <HAL_GPIO_Init+0x1fc>
- 8000d54:	687b      	ldr	r3, [r7, #4]
- 8000d56:	4a4c      	ldr	r2, [pc, #304]	@ (8000e88 <HAL_GPIO_Init+0x314>)
- 8000d58:	4293      	cmp	r3, r2
- 8000d5a:	d007      	beq.n	8000d6c <HAL_GPIO_Init+0x1f8>
- 8000d5c:	687b      	ldr	r3, [r7, #4]
- 8000d5e:	4a4b      	ldr	r2, [pc, #300]	@ (8000e8c <HAL_GPIO_Init+0x318>)
- 8000d60:	4293      	cmp	r3, r2
- 8000d62:	d101      	bne.n	8000d68 <HAL_GPIO_Init+0x1f4>
- 8000d64:	2306      	movs	r3, #6
- 8000d66:	e00c      	b.n	8000d82 <HAL_GPIO_Init+0x20e>
- 8000d68:	2307      	movs	r3, #7
- 8000d6a:	e00a      	b.n	8000d82 <HAL_GPIO_Init+0x20e>
- 8000d6c:	2305      	movs	r3, #5
- 8000d6e:	e008      	b.n	8000d82 <HAL_GPIO_Init+0x20e>
- 8000d70:	2304      	movs	r3, #4
- 8000d72:	e006      	b.n	8000d82 <HAL_GPIO_Init+0x20e>
- 8000d74:	2303      	movs	r3, #3
- 8000d76:	e004      	b.n	8000d82 <HAL_GPIO_Init+0x20e>
- 8000d78:	2302      	movs	r3, #2
- 8000d7a:	e002      	b.n	8000d82 <HAL_GPIO_Init+0x20e>
- 8000d7c:	2301      	movs	r3, #1
- 8000d7e:	e000      	b.n	8000d82 <HAL_GPIO_Init+0x20e>
- 8000d80:	2300      	movs	r3, #0
- 8000d82:	697a      	ldr	r2, [r7, #20]
- 8000d84:	f002 0203 	and.w	r2, r2, #3
- 8000d88:	0092      	lsls	r2, r2, #2
- 8000d8a:	4093      	lsls	r3, r2
- 8000d8c:	693a      	ldr	r2, [r7, #16]
- 8000d8e:	4313      	orrs	r3, r2
- 8000d90:	613b      	str	r3, [r7, #16]
+ 8000e18:	687b      	ldr	r3, [r7, #4]
+ 8000e1a:	4a51      	ldr	r2, [pc, #324]	@ (8000f60 <HAL_GPIO_Init+0x300>)
+ 8000e1c:	4293      	cmp	r3, r2
+ 8000e1e:	d025      	beq.n	8000e6c <HAL_GPIO_Init+0x20c>
+ 8000e20:	687b      	ldr	r3, [r7, #4]
+ 8000e22:	4a50      	ldr	r2, [pc, #320]	@ (8000f64 <HAL_GPIO_Init+0x304>)
+ 8000e24:	4293      	cmp	r3, r2
+ 8000e26:	d01f      	beq.n	8000e68 <HAL_GPIO_Init+0x208>
+ 8000e28:	687b      	ldr	r3, [r7, #4]
+ 8000e2a:	4a4f      	ldr	r2, [pc, #316]	@ (8000f68 <HAL_GPIO_Init+0x308>)
+ 8000e2c:	4293      	cmp	r3, r2
+ 8000e2e:	d019      	beq.n	8000e64 <HAL_GPIO_Init+0x204>
+ 8000e30:	687b      	ldr	r3, [r7, #4]
+ 8000e32:	4a4e      	ldr	r2, [pc, #312]	@ (8000f6c <HAL_GPIO_Init+0x30c>)
+ 8000e34:	4293      	cmp	r3, r2
+ 8000e36:	d013      	beq.n	8000e60 <HAL_GPIO_Init+0x200>
+ 8000e38:	687b      	ldr	r3, [r7, #4]
+ 8000e3a:	4a4d      	ldr	r2, [pc, #308]	@ (8000f70 <HAL_GPIO_Init+0x310>)
+ 8000e3c:	4293      	cmp	r3, r2
+ 8000e3e:	d00d      	beq.n	8000e5c <HAL_GPIO_Init+0x1fc>
+ 8000e40:	687b      	ldr	r3, [r7, #4]
+ 8000e42:	4a4c      	ldr	r2, [pc, #304]	@ (8000f74 <HAL_GPIO_Init+0x314>)
+ 8000e44:	4293      	cmp	r3, r2
+ 8000e46:	d007      	beq.n	8000e58 <HAL_GPIO_Init+0x1f8>
+ 8000e48:	687b      	ldr	r3, [r7, #4]
+ 8000e4a:	4a4b      	ldr	r2, [pc, #300]	@ (8000f78 <HAL_GPIO_Init+0x318>)
+ 8000e4c:	4293      	cmp	r3, r2
+ 8000e4e:	d101      	bne.n	8000e54 <HAL_GPIO_Init+0x1f4>
+ 8000e50:	2306      	movs	r3, #6
+ 8000e52:	e00c      	b.n	8000e6e <HAL_GPIO_Init+0x20e>
+ 8000e54:	2307      	movs	r3, #7
+ 8000e56:	e00a      	b.n	8000e6e <HAL_GPIO_Init+0x20e>
+ 8000e58:	2305      	movs	r3, #5
+ 8000e5a:	e008      	b.n	8000e6e <HAL_GPIO_Init+0x20e>
+ 8000e5c:	2304      	movs	r3, #4
+ 8000e5e:	e006      	b.n	8000e6e <HAL_GPIO_Init+0x20e>
+ 8000e60:	2303      	movs	r3, #3
+ 8000e62:	e004      	b.n	8000e6e <HAL_GPIO_Init+0x20e>
+ 8000e64:	2302      	movs	r3, #2
+ 8000e66:	e002      	b.n	8000e6e <HAL_GPIO_Init+0x20e>
+ 8000e68:	2301      	movs	r3, #1
+ 8000e6a:	e000      	b.n	8000e6e <HAL_GPIO_Init+0x20e>
+ 8000e6c:	2300      	movs	r3, #0
+ 8000e6e:	697a      	ldr	r2, [r7, #20]
+ 8000e70:	f002 0203 	and.w	r2, r2, #3
+ 8000e74:	0092      	lsls	r2, r2, #2
+ 8000e76:	4093      	lsls	r3, r2
+ 8000e78:	693a      	ldr	r2, [r7, #16]
+ 8000e7a:	4313      	orrs	r3, r2
+ 8000e7c:	613b      	str	r3, [r7, #16]
         SYSCFG->EXTICR[position >> 2] = temp;
- 8000d92:	4937      	ldr	r1, [pc, #220]	@ (8000e70 <HAL_GPIO_Init+0x2fc>)
- 8000d94:	697b      	ldr	r3, [r7, #20]
- 8000d96:	089b      	lsrs	r3, r3, #2
- 8000d98:	3302      	adds	r3, #2
- 8000d9a:	693a      	ldr	r2, [r7, #16]
- 8000d9c:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+ 8000e7e:	4937      	ldr	r1, [pc, #220]	@ (8000f5c <HAL_GPIO_Init+0x2fc>)
+ 8000e80:	697b      	ldr	r3, [r7, #20]
+ 8000e82:	089b      	lsrs	r3, r3, #2
+ 8000e84:	3302      	adds	r3, #2
+ 8000e86:	693a      	ldr	r2, [r7, #16]
+ 8000e88:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
 
         /* Clear Rising Falling edge configuration */
         temp = EXTI->RTSR;
- 8000da0:	4b3b      	ldr	r3, [pc, #236]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000da2:	689b      	ldr	r3, [r3, #8]
- 8000da4:	613b      	str	r3, [r7, #16]
+ 8000e8c:	4b3b      	ldr	r3, [pc, #236]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000e8e:	689b      	ldr	r3, [r3, #8]
+ 8000e90:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, (uint32_t)iocurrent);
- 8000da6:	68fb      	ldr	r3, [r7, #12]
- 8000da8:	43db      	mvns	r3, r3
- 8000daa:	693a      	ldr	r2, [r7, #16]
- 8000dac:	4013      	ands	r3, r2
- 8000dae:	613b      	str	r3, [r7, #16]
+ 8000e92:	68fb      	ldr	r3, [r7, #12]
+ 8000e94:	43db      	mvns	r3, r3
+ 8000e96:	693a      	ldr	r2, [r7, #16]
+ 8000e98:	4013      	ands	r3, r2
+ 8000e9a:	613b      	str	r3, [r7, #16]
         if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
- 8000db0:	683b      	ldr	r3, [r7, #0]
- 8000db2:	685b      	ldr	r3, [r3, #4]
- 8000db4:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
- 8000db8:	2b00      	cmp	r3, #0
- 8000dba:	d003      	beq.n	8000dc4 <HAL_GPIO_Init+0x250>
+ 8000e9c:	683b      	ldr	r3, [r7, #0]
+ 8000e9e:	685b      	ldr	r3, [r3, #4]
+ 8000ea0:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
+ 8000ea4:	2b00      	cmp	r3, #0
+ 8000ea6:	d003      	beq.n	8000eb0 <HAL_GPIO_Init+0x250>
         {
           SET_BIT(temp, iocurrent);
- 8000dbc:	693a      	ldr	r2, [r7, #16]
- 8000dbe:	68fb      	ldr	r3, [r7, #12]
- 8000dc0:	4313      	orrs	r3, r2
- 8000dc2:	613b      	str	r3, [r7, #16]
+ 8000ea8:	693a      	ldr	r2, [r7, #16]
+ 8000eaa:	68fb      	ldr	r3, [r7, #12]
+ 8000eac:	4313      	orrs	r3, r2
+ 8000eae:	613b      	str	r3, [r7, #16]
         }
         EXTI->RTSR = temp;
- 8000dc4:	4a32      	ldr	r2, [pc, #200]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000dc6:	693b      	ldr	r3, [r7, #16]
- 8000dc8:	6093      	str	r3, [r2, #8]
+ 8000eb0:	4a32      	ldr	r2, [pc, #200]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000eb2:	693b      	ldr	r3, [r7, #16]
+ 8000eb4:	6093      	str	r3, [r2, #8]
 
         temp = EXTI->FTSR;
- 8000dca:	4b31      	ldr	r3, [pc, #196]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000dcc:	68db      	ldr	r3, [r3, #12]
- 8000dce:	613b      	str	r3, [r7, #16]
+ 8000eb6:	4b31      	ldr	r3, [pc, #196]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000eb8:	68db      	ldr	r3, [r3, #12]
+ 8000eba:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, (uint32_t)iocurrent);
- 8000dd0:	68fb      	ldr	r3, [r7, #12]
- 8000dd2:	43db      	mvns	r3, r3
- 8000dd4:	693a      	ldr	r2, [r7, #16]
- 8000dd6:	4013      	ands	r3, r2
- 8000dd8:	613b      	str	r3, [r7, #16]
+ 8000ebc:	68fb      	ldr	r3, [r7, #12]
+ 8000ebe:	43db      	mvns	r3, r3
+ 8000ec0:	693a      	ldr	r2, [r7, #16]
+ 8000ec2:	4013      	ands	r3, r2
+ 8000ec4:	613b      	str	r3, [r7, #16]
         if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
- 8000dda:	683b      	ldr	r3, [r7, #0]
- 8000ddc:	685b      	ldr	r3, [r3, #4]
- 8000dde:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
- 8000de2:	2b00      	cmp	r3, #0
- 8000de4:	d003      	beq.n	8000dee <HAL_GPIO_Init+0x27a>
+ 8000ec6:	683b      	ldr	r3, [r7, #0]
+ 8000ec8:	685b      	ldr	r3, [r3, #4]
+ 8000eca:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
+ 8000ece:	2b00      	cmp	r3, #0
+ 8000ed0:	d003      	beq.n	8000eda <HAL_GPIO_Init+0x27a>
         {
           SET_BIT(temp, iocurrent);
- 8000de6:	693a      	ldr	r2, [r7, #16]
- 8000de8:	68fb      	ldr	r3, [r7, #12]
- 8000dea:	4313      	orrs	r3, r2
- 8000dec:	613b      	str	r3, [r7, #16]
+ 8000ed2:	693a      	ldr	r2, [r7, #16]
+ 8000ed4:	68fb      	ldr	r3, [r7, #12]
+ 8000ed6:	4313      	orrs	r3, r2
+ 8000ed8:	613b      	str	r3, [r7, #16]
         }
         EXTI->FTSR = temp;
- 8000dee:	4a28      	ldr	r2, [pc, #160]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000df0:	693b      	ldr	r3, [r7, #16]
- 8000df2:	60d3      	str	r3, [r2, #12]
+ 8000eda:	4a28      	ldr	r2, [pc, #160]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000edc:	693b      	ldr	r3, [r7, #16]
+ 8000ede:	60d3      	str	r3, [r2, #12]
 
         temp = EXTI->EMR;
- 8000df4:	4b26      	ldr	r3, [pc, #152]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000df6:	685b      	ldr	r3, [r3, #4]
- 8000df8:	613b      	str	r3, [r7, #16]
+ 8000ee0:	4b26      	ldr	r3, [pc, #152]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000ee2:	685b      	ldr	r3, [r3, #4]
+ 8000ee4:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, (uint32_t)iocurrent);
- 8000dfa:	68fb      	ldr	r3, [r7, #12]
- 8000dfc:	43db      	mvns	r3, r3
- 8000dfe:	693a      	ldr	r2, [r7, #16]
- 8000e00:	4013      	ands	r3, r2
- 8000e02:	613b      	str	r3, [r7, #16]
+ 8000ee6:	68fb      	ldr	r3, [r7, #12]
+ 8000ee8:	43db      	mvns	r3, r3
+ 8000eea:	693a      	ldr	r2, [r7, #16]
+ 8000eec:	4013      	ands	r3, r2
+ 8000eee:	613b      	str	r3, [r7, #16]
         if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
- 8000e04:	683b      	ldr	r3, [r7, #0]
- 8000e06:	685b      	ldr	r3, [r3, #4]
- 8000e08:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 8000e0c:	2b00      	cmp	r3, #0
- 8000e0e:	d003      	beq.n	8000e18 <HAL_GPIO_Init+0x2a4>
+ 8000ef0:	683b      	ldr	r3, [r7, #0]
+ 8000ef2:	685b      	ldr	r3, [r3, #4]
+ 8000ef4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8000ef8:	2b00      	cmp	r3, #0
+ 8000efa:	d003      	beq.n	8000f04 <HAL_GPIO_Init+0x2a4>
         {
           SET_BIT(temp, iocurrent);
- 8000e10:	693a      	ldr	r2, [r7, #16]
- 8000e12:	68fb      	ldr	r3, [r7, #12]
- 8000e14:	4313      	orrs	r3, r2
- 8000e16:	613b      	str	r3, [r7, #16]
+ 8000efc:	693a      	ldr	r2, [r7, #16]
+ 8000efe:	68fb      	ldr	r3, [r7, #12]
+ 8000f00:	4313      	orrs	r3, r2
+ 8000f02:	613b      	str	r3, [r7, #16]
         }
         EXTI->EMR = temp;
- 8000e18:	4a1d      	ldr	r2, [pc, #116]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000e1a:	693b      	ldr	r3, [r7, #16]
- 8000e1c:	6053      	str	r3, [r2, #4]
+ 8000f04:	4a1d      	ldr	r2, [pc, #116]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000f06:	693b      	ldr	r3, [r7, #16]
+ 8000f08:	6053      	str	r3, [r2, #4]
 
         /* Clear EXTI line configuration */
         temp = EXTI->IMR;
- 8000e1e:	4b1c      	ldr	r3, [pc, #112]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000e20:	681b      	ldr	r3, [r3, #0]
- 8000e22:	613b      	str	r3, [r7, #16]
+ 8000f0a:	4b1c      	ldr	r3, [pc, #112]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000f0c:	681b      	ldr	r3, [r3, #0]
+ 8000f0e:	613b      	str	r3, [r7, #16]
         CLEAR_BIT(temp, (uint32_t)iocurrent);
- 8000e24:	68fb      	ldr	r3, [r7, #12]
- 8000e26:	43db      	mvns	r3, r3
- 8000e28:	693a      	ldr	r2, [r7, #16]
- 8000e2a:	4013      	ands	r3, r2
- 8000e2c:	613b      	str	r3, [r7, #16]
+ 8000f10:	68fb      	ldr	r3, [r7, #12]
+ 8000f12:	43db      	mvns	r3, r3
+ 8000f14:	693a      	ldr	r2, [r7, #16]
+ 8000f16:	4013      	ands	r3, r2
+ 8000f18:	613b      	str	r3, [r7, #16]
         if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
- 8000e2e:	683b      	ldr	r3, [r7, #0]
- 8000e30:	685b      	ldr	r3, [r3, #4]
- 8000e32:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
- 8000e36:	2b00      	cmp	r3, #0
- 8000e38:	d003      	beq.n	8000e42 <HAL_GPIO_Init+0x2ce>
+ 8000f1a:	683b      	ldr	r3, [r7, #0]
+ 8000f1c:	685b      	ldr	r3, [r3, #4]
+ 8000f1e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8000f22:	2b00      	cmp	r3, #0
+ 8000f24:	d003      	beq.n	8000f2e <HAL_GPIO_Init+0x2ce>
         {
           SET_BIT(temp, iocurrent);
- 8000e3a:	693a      	ldr	r2, [r7, #16]
- 8000e3c:	68fb      	ldr	r3, [r7, #12]
- 8000e3e:	4313      	orrs	r3, r2
- 8000e40:	613b      	str	r3, [r7, #16]
+ 8000f26:	693a      	ldr	r2, [r7, #16]
+ 8000f28:	68fb      	ldr	r3, [r7, #12]
+ 8000f2a:	4313      	orrs	r3, r2
+ 8000f2c:	613b      	str	r3, [r7, #16]
         }
         EXTI->IMR = temp;
- 8000e42:	4a13      	ldr	r2, [pc, #76]	@ (8000e90 <HAL_GPIO_Init+0x31c>)
- 8000e44:	693b      	ldr	r3, [r7, #16]
- 8000e46:	6013      	str	r3, [r2, #0]
+ 8000f2e:	4a13      	ldr	r2, [pc, #76]	@ (8000f7c <HAL_GPIO_Init+0x31c>)
+ 8000f30:	693b      	ldr	r3, [r7, #16]
+ 8000f32:	6013      	str	r3, [r2, #0]
       }
     }
 
     position++;
- 8000e48:	697b      	ldr	r3, [r7, #20]
- 8000e4a:	3301      	adds	r3, #1
- 8000e4c:	617b      	str	r3, [r7, #20]
+ 8000f34:	697b      	ldr	r3, [r7, #20]
+ 8000f36:	3301      	adds	r3, #1
+ 8000f38:	617b      	str	r3, [r7, #20]
   while (((GPIO_Init->Pin) >> position) != 0)
- 8000e4e:	683b      	ldr	r3, [r7, #0]
- 8000e50:	681a      	ldr	r2, [r3, #0]
- 8000e52:	697b      	ldr	r3, [r7, #20]
- 8000e54:	fa22 f303 	lsr.w	r3, r2, r3
- 8000e58:	2b00      	cmp	r3, #0
- 8000e5a:	f47f ae97 	bne.w	8000b8c <HAL_GPIO_Init+0x18>
+ 8000f3a:	683b      	ldr	r3, [r7, #0]
+ 8000f3c:	681a      	ldr	r2, [r3, #0]
+ 8000f3e:	697b      	ldr	r3, [r7, #20]
+ 8000f40:	fa22 f303 	lsr.w	r3, r2, r3
+ 8000f44:	2b00      	cmp	r3, #0
+ 8000f46:	f47f ae97 	bne.w	8000c78 <HAL_GPIO_Init+0x18>
   }
 }
- 8000e5e:	bf00      	nop
- 8000e60:	bf00      	nop
- 8000e62:	371c      	adds	r7, #28
- 8000e64:	46bd      	mov	sp, r7
- 8000e66:	bc80      	pop	{r7}
- 8000e68:	4770      	bx	lr
- 8000e6a:	bf00      	nop
- 8000e6c:	40023800 	.word	0x40023800
- 8000e70:	40010000 	.word	0x40010000
- 8000e74:	40020000 	.word	0x40020000
- 8000e78:	40020400 	.word	0x40020400
- 8000e7c:	40020800 	.word	0x40020800
- 8000e80:	40020c00 	.word	0x40020c00
- 8000e84:	40021000 	.word	0x40021000
- 8000e88:	40021400 	.word	0x40021400
- 8000e8c:	40021800 	.word	0x40021800
- 8000e90:	40010400 	.word	0x40010400
+ 8000f4a:	bf00      	nop
+ 8000f4c:	bf00      	nop
+ 8000f4e:	371c      	adds	r7, #28
+ 8000f50:	46bd      	mov	sp, r7
+ 8000f52:	bc80      	pop	{r7}
+ 8000f54:	4770      	bx	lr
+ 8000f56:	bf00      	nop
+ 8000f58:	40023800 	.word	0x40023800
+ 8000f5c:	40010000 	.word	0x40010000
+ 8000f60:	40020000 	.word	0x40020000
+ 8000f64:	40020400 	.word	0x40020400
+ 8000f68:	40020800 	.word	0x40020800
+ 8000f6c:	40020c00 	.word	0x40020c00
+ 8000f70:	40021000 	.word	0x40021000
+ 8000f74:	40021400 	.word	0x40021400
+ 8000f78:	40021800 	.word	0x40021800
+ 8000f7c:	40010400 	.word	0x40010400
 
-08000e94 <HAL_GPIO_WritePin>:
+08000f80 <HAL_GPIO_WritePin>:
   *            @arg GPIO_PIN_RESET: to clear the port pin
   *            @arg GPIO_PIN_SET: to set the port pin
   * @retval None
   */
 void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
 {
- 8000e94:	b480      	push	{r7}
- 8000e96:	b083      	sub	sp, #12
- 8000e98:	af00      	add	r7, sp, #0
- 8000e9a:	6078      	str	r0, [r7, #4]
- 8000e9c:	460b      	mov	r3, r1
- 8000e9e:	807b      	strh	r3, [r7, #2]
- 8000ea0:	4613      	mov	r3, r2
- 8000ea2:	707b      	strb	r3, [r7, #1]
+ 8000f80:	b480      	push	{r7}
+ 8000f82:	b083      	sub	sp, #12
+ 8000f84:	af00      	add	r7, sp, #0
+ 8000f86:	6078      	str	r0, [r7, #4]
+ 8000f88:	460b      	mov	r3, r1
+ 8000f8a:	807b      	strh	r3, [r7, #2]
+ 8000f8c:	4613      	mov	r3, r2
+ 8000f8e:	707b      	strb	r3, [r7, #1]
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
   assert_param(IS_GPIO_PIN_ACTION(PinState));
 
   if (PinState != GPIO_PIN_RESET)
- 8000ea4:	787b      	ldrb	r3, [r7, #1]
- 8000ea6:	2b00      	cmp	r3, #0
- 8000ea8:	d003      	beq.n	8000eb2 <HAL_GPIO_WritePin+0x1e>
+ 8000f90:	787b      	ldrb	r3, [r7, #1]
+ 8000f92:	2b00      	cmp	r3, #0
+ 8000f94:	d003      	beq.n	8000f9e <HAL_GPIO_WritePin+0x1e>
   {
     GPIOx->BSRR = (uint32_t)GPIO_Pin;
- 8000eaa:	887a      	ldrh	r2, [r7, #2]
- 8000eac:	687b      	ldr	r3, [r7, #4]
- 8000eae:	619a      	str	r2, [r3, #24]
+ 8000f96:	887a      	ldrh	r2, [r7, #2]
+ 8000f98:	687b      	ldr	r3, [r7, #4]
+ 8000f9a:	619a      	str	r2, [r3, #24]
   }
   else
   {
     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
   }
 }
- 8000eb0:	e003      	b.n	8000eba <HAL_GPIO_WritePin+0x26>
+ 8000f9c:	e003      	b.n	8000fa6 <HAL_GPIO_WritePin+0x26>
     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
- 8000eb2:	887b      	ldrh	r3, [r7, #2]
- 8000eb4:	041a      	lsls	r2, r3, #16
- 8000eb6:	687b      	ldr	r3, [r7, #4]
- 8000eb8:	619a      	str	r2, [r3, #24]
+ 8000f9e:	887b      	ldrh	r3, [r7, #2]
+ 8000fa0:	041a      	lsls	r2, r3, #16
+ 8000fa2:	687b      	ldr	r3, [r7, #4]
+ 8000fa4:	619a      	str	r2, [r3, #24]
 }
- 8000eba:	bf00      	nop
- 8000ebc:	370c      	adds	r7, #12
- 8000ebe:	46bd      	mov	sp, r7
- 8000ec0:	bc80      	pop	{r7}
- 8000ec2:	4770      	bx	lr
+ 8000fa6:	bf00      	nop
+ 8000fa8:	370c      	adds	r7, #12
+ 8000faa:	46bd      	mov	sp, r7
+ 8000fac:	bc80      	pop	{r7}
+ 8000fae:	4770      	bx	lr
 
-08000ec4 <HAL_GPIO_EXTI_IRQHandler>:
+08000fb0 <HAL_GPIO_EXTI_IRQHandler>:
   * @brief  This function handles EXTI interrupt request.
   * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
   * @retval None
   */
 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 {
- 8000ec4:	b580      	push	{r7, lr}
- 8000ec6:	b082      	sub	sp, #8
- 8000ec8:	af00      	add	r7, sp, #0
- 8000eca:	4603      	mov	r3, r0
- 8000ecc:	80fb      	strh	r3, [r7, #6]
+ 8000fb0:	b580      	push	{r7, lr}
+ 8000fb2:	b082      	sub	sp, #8
+ 8000fb4:	af00      	add	r7, sp, #0
+ 8000fb6:	4603      	mov	r3, r0
+ 8000fb8:	80fb      	strh	r3, [r7, #6]
   /* EXTI line interrupt detected */
   if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- 8000ece:	4b08      	ldr	r3, [pc, #32]	@ (8000ef0 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 8000ed0:	695a      	ldr	r2, [r3, #20]
- 8000ed2:	88fb      	ldrh	r3, [r7, #6]
- 8000ed4:	4013      	ands	r3, r2
- 8000ed6:	2b00      	cmp	r3, #0
- 8000ed8:	d006      	beq.n	8000ee8 <HAL_GPIO_EXTI_IRQHandler+0x24>
+ 8000fba:	4b08      	ldr	r3, [pc, #32]	@ (8000fdc <HAL_GPIO_EXTI_IRQHandler+0x2c>)
+ 8000fbc:	695a      	ldr	r2, [r3, #20]
+ 8000fbe:	88fb      	ldrh	r3, [r7, #6]
+ 8000fc0:	4013      	ands	r3, r2
+ 8000fc2:	2b00      	cmp	r3, #0
+ 8000fc4:	d006      	beq.n	8000fd4 <HAL_GPIO_EXTI_IRQHandler+0x24>
   {
     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
- 8000eda:	4a05      	ldr	r2, [pc, #20]	@ (8000ef0 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
- 8000edc:	88fb      	ldrh	r3, [r7, #6]
- 8000ede:	6153      	str	r3, [r2, #20]
+ 8000fc6:	4a05      	ldr	r2, [pc, #20]	@ (8000fdc <HAL_GPIO_EXTI_IRQHandler+0x2c>)
+ 8000fc8:	88fb      	ldrh	r3, [r7, #6]
+ 8000fca:	6153      	str	r3, [r2, #20]
     HAL_GPIO_EXTI_Callback(GPIO_Pin);
- 8000ee0:	88fb      	ldrh	r3, [r7, #6]
- 8000ee2:	4618      	mov	r0, r3
- 8000ee4:	f7ff fbde 	bl	80006a4 <HAL_GPIO_EXTI_Callback>
+ 8000fcc:	88fb      	ldrh	r3, [r7, #6]
+ 8000fce:	4618      	mov	r0, r3
+ 8000fd0:	f7ff fba6 	bl	8000720 <HAL_GPIO_EXTI_Callback>
   }
 }
- 8000ee8:	bf00      	nop
- 8000eea:	3708      	adds	r7, #8
- 8000eec:	46bd      	mov	sp, r7
- 8000eee:	bd80      	pop	{r7, pc}
- 8000ef0:	40010400 	.word	0x40010400
+ 8000fd4:	bf00      	nop
+ 8000fd6:	3708      	adds	r7, #8
+ 8000fd8:	46bd      	mov	sp, r7
+ 8000fda:	bd80      	pop	{r7, pc}
+ 8000fdc:	40010400 	.word	0x40010400
 
-08000ef4 <HAL_RCC_OscConfig>:
+08000fe0 <HAL_RCC_OscConfig>:
   *         supported by this macro. User should request a transition to HSE Off
   *         first and then HSE On or HSE Bypass.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
- 8000ef4:	b580      	push	{r7, lr}
- 8000ef6:	b088      	sub	sp, #32
- 8000ef8:	af00      	add	r7, sp, #0
- 8000efa:	6078      	str	r0, [r7, #4]
+ 8000fe0:	b580      	push	{r7, lr}
+ 8000fe2:	b088      	sub	sp, #32
+ 8000fe4:	af00      	add	r7, sp, #0
+ 8000fe6:	6078      	str	r0, [r7, #4]
   uint32_t tickstart;
   HAL_StatusTypeDef status;
   uint32_t sysclk_source, pll_config;
 
   /* Check the parameters */
   if(RCC_OscInitStruct == NULL)
- 8000efc:	687b      	ldr	r3, [r7, #4]
- 8000efe:	2b00      	cmp	r3, #0
- 8000f00:	d101      	bne.n	8000f06 <HAL_RCC_OscConfig+0x12>
+ 8000fe8:	687b      	ldr	r3, [r7, #4]
+ 8000fea:	2b00      	cmp	r3, #0
+ 8000fec:	d101      	bne.n	8000ff2 <HAL_RCC_OscConfig+0x12>
   {
     return HAL_ERROR;
- 8000f02:	2301      	movs	r3, #1
- 8000f04:	e31d      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 8000fee:	2301      	movs	r3, #1
+ 8000ff0:	e31d      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
   }
 
   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
 
   sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
- 8000f06:	4b94      	ldr	r3, [pc, #592]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f08:	689b      	ldr	r3, [r3, #8]
- 8000f0a:	f003 030c 	and.w	r3, r3, #12
- 8000f0e:	61bb      	str	r3, [r7, #24]
+ 8000ff2:	4b94      	ldr	r3, [pc, #592]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8000ff4:	689b      	ldr	r3, [r3, #8]
+ 8000ff6:	f003 030c 	and.w	r3, r3, #12
+ 8000ffa:	61bb      	str	r3, [r7, #24]
   pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
- 8000f10:	4b91      	ldr	r3, [pc, #580]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f12:	689b      	ldr	r3, [r3, #8]
- 8000f14:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
- 8000f18:	617b      	str	r3, [r7, #20]
+ 8000ffc:	4b91      	ldr	r3, [pc, #580]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8000ffe:	689b      	ldr	r3, [r3, #8]
+ 8001000:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8001004:	617b      	str	r3, [r7, #20]
 
   /*------------------------------- HSE Configuration ------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8000f1a:	687b      	ldr	r3, [r7, #4]
- 8000f1c:	681b      	ldr	r3, [r3, #0]
- 8000f1e:	f003 0301 	and.w	r3, r3, #1
- 8000f22:	2b00      	cmp	r3, #0
- 8000f24:	d07b      	beq.n	800101e <HAL_RCC_OscConfig+0x12a>
+ 8001006:	687b      	ldr	r3, [r7, #4]
+ 8001008:	681b      	ldr	r3, [r3, #0]
+ 800100a:	f003 0301 	and.w	r3, r3, #1
+ 800100e:	2b00      	cmp	r3, #0
+ 8001010:	d07b      	beq.n	800110a <HAL_RCC_OscConfig+0x12a>
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
 
     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
     if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8000f26:	69bb      	ldr	r3, [r7, #24]
- 8000f28:	2b08      	cmp	r3, #8
- 8000f2a:	d006      	beq.n	8000f3a <HAL_RCC_OscConfig+0x46>
+ 8001012:	69bb      	ldr	r3, [r7, #24]
+ 8001014:	2b08      	cmp	r3, #8
+ 8001016:	d006      	beq.n	8001026 <HAL_RCC_OscConfig+0x46>
        || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
- 8000f2c:	69bb      	ldr	r3, [r7, #24]
- 8000f2e:	2b0c      	cmp	r3, #12
- 8000f30:	d10f      	bne.n	8000f52 <HAL_RCC_OscConfig+0x5e>
- 8000f32:	697b      	ldr	r3, [r7, #20]
- 8000f34:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
- 8000f38:	d10b      	bne.n	8000f52 <HAL_RCC_OscConfig+0x5e>
+ 8001018:	69bb      	ldr	r3, [r7, #24]
+ 800101a:	2b0c      	cmp	r3, #12
+ 800101c:	d10f      	bne.n	800103e <HAL_RCC_OscConfig+0x5e>
+ 800101e:	697b      	ldr	r3, [r7, #20]
+ 8001020:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 8001024:	d10b      	bne.n	800103e <HAL_RCC_OscConfig+0x5e>
     {
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8000f3a:	4b87      	ldr	r3, [pc, #540]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f3c:	681b      	ldr	r3, [r3, #0]
- 8000f3e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 8000f42:	2b00      	cmp	r3, #0
- 8000f44:	d06a      	beq.n	800101c <HAL_RCC_OscConfig+0x128>
- 8000f46:	687b      	ldr	r3, [r7, #4]
- 8000f48:	685b      	ldr	r3, [r3, #4]
- 8000f4a:	2b00      	cmp	r3, #0
- 8000f4c:	d166      	bne.n	800101c <HAL_RCC_OscConfig+0x128>
+ 8001026:	4b87      	ldr	r3, [pc, #540]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001028:	681b      	ldr	r3, [r3, #0]
+ 800102a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 800102e:	2b00      	cmp	r3, #0
+ 8001030:	d06a      	beq.n	8001108 <HAL_RCC_OscConfig+0x128>
+ 8001032:	687b      	ldr	r3, [r7, #4]
+ 8001034:	685b      	ldr	r3, [r3, #4]
+ 8001036:	2b00      	cmp	r3, #0
+ 8001038:	d166      	bne.n	8001108 <HAL_RCC_OscConfig+0x128>
       {
         return HAL_ERROR;
- 8000f4e:	2301      	movs	r3, #1
- 8000f50:	e2f7      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 800103a:	2301      	movs	r3, #1
+ 800103c:	e2f7      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       }
     }
     else
     {
       /* Set the new HSE configuration ---------------------------------------*/
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 8000f52:	687b      	ldr	r3, [r7, #4]
- 8000f54:	685b      	ldr	r3, [r3, #4]
- 8000f56:	2b01      	cmp	r3, #1
- 8000f58:	d106      	bne.n	8000f68 <HAL_RCC_OscConfig+0x74>
- 8000f5a:	4b7f      	ldr	r3, [pc, #508]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f5c:	681b      	ldr	r3, [r3, #0]
- 8000f5e:	4a7e      	ldr	r2, [pc, #504]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f60:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
- 8000f64:	6013      	str	r3, [r2, #0]
- 8000f66:	e02d      	b.n	8000fc4 <HAL_RCC_OscConfig+0xd0>
- 8000f68:	687b      	ldr	r3, [r7, #4]
- 8000f6a:	685b      	ldr	r3, [r3, #4]
- 8000f6c:	2b00      	cmp	r3, #0
- 8000f6e:	d10c      	bne.n	8000f8a <HAL_RCC_OscConfig+0x96>
- 8000f70:	4b79      	ldr	r3, [pc, #484]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f72:	681b      	ldr	r3, [r3, #0]
- 8000f74:	4a78      	ldr	r2, [pc, #480]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f76:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
- 8000f7a:	6013      	str	r3, [r2, #0]
- 8000f7c:	4b76      	ldr	r3, [pc, #472]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f7e:	681b      	ldr	r3, [r3, #0]
- 8000f80:	4a75      	ldr	r2, [pc, #468]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f82:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
- 8000f86:	6013      	str	r3, [r2, #0]
- 8000f88:	e01c      	b.n	8000fc4 <HAL_RCC_OscConfig+0xd0>
- 8000f8a:	687b      	ldr	r3, [r7, #4]
- 8000f8c:	685b      	ldr	r3, [r3, #4]
- 8000f8e:	2b05      	cmp	r3, #5
- 8000f90:	d10c      	bne.n	8000fac <HAL_RCC_OscConfig+0xb8>
- 8000f92:	4b71      	ldr	r3, [pc, #452]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f94:	681b      	ldr	r3, [r3, #0]
- 8000f96:	4a70      	ldr	r2, [pc, #448]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000f98:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
- 8000f9c:	6013      	str	r3, [r2, #0]
- 8000f9e:	4b6e      	ldr	r3, [pc, #440]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000fa0:	681b      	ldr	r3, [r3, #0]
- 8000fa2:	4a6d      	ldr	r2, [pc, #436]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000fa4:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
- 8000fa8:	6013      	str	r3, [r2, #0]
- 8000faa:	e00b      	b.n	8000fc4 <HAL_RCC_OscConfig+0xd0>
- 8000fac:	4b6a      	ldr	r3, [pc, #424]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000fae:	681b      	ldr	r3, [r3, #0]
- 8000fb0:	4a69      	ldr	r2, [pc, #420]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000fb2:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
- 8000fb6:	6013      	str	r3, [r2, #0]
- 8000fb8:	4b67      	ldr	r3, [pc, #412]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000fba:	681b      	ldr	r3, [r3, #0]
- 8000fbc:	4a66      	ldr	r2, [pc, #408]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000fbe:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
- 8000fc2:	6013      	str	r3, [r2, #0]
+ 800103e:	687b      	ldr	r3, [r7, #4]
+ 8001040:	685b      	ldr	r3, [r3, #4]
+ 8001042:	2b01      	cmp	r3, #1
+ 8001044:	d106      	bne.n	8001054 <HAL_RCC_OscConfig+0x74>
+ 8001046:	4b7f      	ldr	r3, [pc, #508]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001048:	681b      	ldr	r3, [r3, #0]
+ 800104a:	4a7e      	ldr	r2, [pc, #504]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800104c:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 8001050:	6013      	str	r3, [r2, #0]
+ 8001052:	e02d      	b.n	80010b0 <HAL_RCC_OscConfig+0xd0>
+ 8001054:	687b      	ldr	r3, [r7, #4]
+ 8001056:	685b      	ldr	r3, [r3, #4]
+ 8001058:	2b00      	cmp	r3, #0
+ 800105a:	d10c      	bne.n	8001076 <HAL_RCC_OscConfig+0x96>
+ 800105c:	4b79      	ldr	r3, [pc, #484]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800105e:	681b      	ldr	r3, [r3, #0]
+ 8001060:	4a78      	ldr	r2, [pc, #480]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001062:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 8001066:	6013      	str	r3, [r2, #0]
+ 8001068:	4b76      	ldr	r3, [pc, #472]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800106a:	681b      	ldr	r3, [r3, #0]
+ 800106c:	4a75      	ldr	r2, [pc, #468]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800106e:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
+ 8001072:	6013      	str	r3, [r2, #0]
+ 8001074:	e01c      	b.n	80010b0 <HAL_RCC_OscConfig+0xd0>
+ 8001076:	687b      	ldr	r3, [r7, #4]
+ 8001078:	685b      	ldr	r3, [r3, #4]
+ 800107a:	2b05      	cmp	r3, #5
+ 800107c:	d10c      	bne.n	8001098 <HAL_RCC_OscConfig+0xb8>
+ 800107e:	4b71      	ldr	r3, [pc, #452]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001080:	681b      	ldr	r3, [r3, #0]
+ 8001082:	4a70      	ldr	r2, [pc, #448]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001084:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
+ 8001088:	6013      	str	r3, [r2, #0]
+ 800108a:	4b6e      	ldr	r3, [pc, #440]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800108c:	681b      	ldr	r3, [r3, #0]
+ 800108e:	4a6d      	ldr	r2, [pc, #436]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001090:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 8001094:	6013      	str	r3, [r2, #0]
+ 8001096:	e00b      	b.n	80010b0 <HAL_RCC_OscConfig+0xd0>
+ 8001098:	4b6a      	ldr	r3, [pc, #424]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800109a:	681b      	ldr	r3, [r3, #0]
+ 800109c:	4a69      	ldr	r2, [pc, #420]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800109e:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 80010a2:	6013      	str	r3, [r2, #0]
+ 80010a4:	4b67      	ldr	r3, [pc, #412]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 80010a6:	681b      	ldr	r3, [r3, #0]
+ 80010a8:	4a66      	ldr	r2, [pc, #408]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 80010aa:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
+ 80010ae:	6013      	str	r3, [r2, #0]
 
       /* Check the HSE State */
       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8000fc4:	687b      	ldr	r3, [r7, #4]
- 8000fc6:	685b      	ldr	r3, [r3, #4]
- 8000fc8:	2b00      	cmp	r3, #0
- 8000fca:	d013      	beq.n	8000ff4 <HAL_RCC_OscConfig+0x100>
+ 80010b0:	687b      	ldr	r3, [r7, #4]
+ 80010b2:	685b      	ldr	r3, [r3, #4]
+ 80010b4:	2b00      	cmp	r3, #0
+ 80010b6:	d013      	beq.n	80010e0 <HAL_RCC_OscConfig+0x100>
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8000fcc:	f7ff fcba 	bl	8000944 <HAL_GetTick>
- 8000fd0:	6138      	str	r0, [r7, #16]
+ 80010b8:	f7ff fcba 	bl	8000a30 <HAL_GetTick>
+ 80010bc:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSE is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8000fd2:	e008      	b.n	8000fe6 <HAL_RCC_OscConfig+0xf2>
+ 80010be:	e008      	b.n	80010d2 <HAL_RCC_OscConfig+0xf2>
         {
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8000fd4:	f7ff fcb6 	bl	8000944 <HAL_GetTick>
- 8000fd8:	4602      	mov	r2, r0
- 8000fda:	693b      	ldr	r3, [r7, #16]
- 8000fdc:	1ad3      	subs	r3, r2, r3
- 8000fde:	2b64      	cmp	r3, #100	@ 0x64
- 8000fe0:	d901      	bls.n	8000fe6 <HAL_RCC_OscConfig+0xf2>
+ 80010c0:	f7ff fcb6 	bl	8000a30 <HAL_GetTick>
+ 80010c4:	4602      	mov	r2, r0
+ 80010c6:	693b      	ldr	r3, [r7, #16]
+ 80010c8:	1ad3      	subs	r3, r2, r3
+ 80010ca:	2b64      	cmp	r3, #100	@ 0x64
+ 80010cc:	d901      	bls.n	80010d2 <HAL_RCC_OscConfig+0xf2>
           {
             return HAL_TIMEOUT;
- 8000fe2:	2303      	movs	r3, #3
- 8000fe4:	e2ad      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80010ce:	2303      	movs	r3, #3
+ 80010d0:	e2ad      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8000fe6:	4b5c      	ldr	r3, [pc, #368]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8000fe8:	681b      	ldr	r3, [r3, #0]
- 8000fea:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 8000fee:	2b00      	cmp	r3, #0
- 8000ff0:	d0f0      	beq.n	8000fd4 <HAL_RCC_OscConfig+0xe0>
- 8000ff2:	e014      	b.n	800101e <HAL_RCC_OscConfig+0x12a>
+ 80010d2:	4b5c      	ldr	r3, [pc, #368]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 80010d4:	681b      	ldr	r3, [r3, #0]
+ 80010d6:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 80010da:	2b00      	cmp	r3, #0
+ 80010dc:	d0f0      	beq.n	80010c0 <HAL_RCC_OscConfig+0xe0>
+ 80010de:	e014      	b.n	800110a <HAL_RCC_OscConfig+0x12a>
         }
       }
       else
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8000ff4:	f7ff fca6 	bl	8000944 <HAL_GetTick>
- 8000ff8:	6138      	str	r0, [r7, #16]
+ 80010e0:	f7ff fca6 	bl	8000a30 <HAL_GetTick>
+ 80010e4:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSE is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
- 8000ffa:	e008      	b.n	800100e <HAL_RCC_OscConfig+0x11a>
+ 80010e6:	e008      	b.n	80010fa <HAL_RCC_OscConfig+0x11a>
         {
            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8000ffc:	f7ff fca2 	bl	8000944 <HAL_GetTick>
- 8001000:	4602      	mov	r2, r0
- 8001002:	693b      	ldr	r3, [r7, #16]
- 8001004:	1ad3      	subs	r3, r2, r3
- 8001006:	2b64      	cmp	r3, #100	@ 0x64
- 8001008:	d901      	bls.n	800100e <HAL_RCC_OscConfig+0x11a>
+ 80010e8:	f7ff fca2 	bl	8000a30 <HAL_GetTick>
+ 80010ec:	4602      	mov	r2, r0
+ 80010ee:	693b      	ldr	r3, [r7, #16]
+ 80010f0:	1ad3      	subs	r3, r2, r3
+ 80010f2:	2b64      	cmp	r3, #100	@ 0x64
+ 80010f4:	d901      	bls.n	80010fa <HAL_RCC_OscConfig+0x11a>
           {
             return HAL_TIMEOUT;
- 800100a:	2303      	movs	r3, #3
- 800100c:	e299      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80010f6:	2303      	movs	r3, #3
+ 80010f8:	e299      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
- 800100e:	4b52      	ldr	r3, [pc, #328]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001010:	681b      	ldr	r3, [r3, #0]
- 8001012:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 8001016:	2b00      	cmp	r3, #0
- 8001018:	d1f0      	bne.n	8000ffc <HAL_RCC_OscConfig+0x108>
- 800101a:	e000      	b.n	800101e <HAL_RCC_OscConfig+0x12a>
+ 80010fa:	4b52      	ldr	r3, [pc, #328]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 80010fc:	681b      	ldr	r3, [r3, #0]
+ 80010fe:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8001102:	2b00      	cmp	r3, #0
+ 8001104:	d1f0      	bne.n	80010e8 <HAL_RCC_OscConfig+0x108>
+ 8001106:	e000      	b.n	800110a <HAL_RCC_OscConfig+0x12a>
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 800101c:	bf00      	nop
+ 8001108:	bf00      	nop
         }
       }
     }
   }
   /*----------------------------- HSI Configuration --------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 800101e:	687b      	ldr	r3, [r7, #4]
- 8001020:	681b      	ldr	r3, [r3, #0]
- 8001022:	f003 0302 	and.w	r3, r3, #2
- 8001026:	2b00      	cmp	r3, #0
- 8001028:	d05a      	beq.n	80010e0 <HAL_RCC_OscConfig+0x1ec>
+ 800110a:	687b      	ldr	r3, [r7, #4]
+ 800110c:	681b      	ldr	r3, [r3, #0]
+ 800110e:	f003 0302 	and.w	r3, r3, #2
+ 8001112:	2b00      	cmp	r3, #0
+ 8001114:	d05a      	beq.n	80011cc <HAL_RCC_OscConfig+0x1ec>
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
 
     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
     if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
- 800102a:	69bb      	ldr	r3, [r7, #24]
- 800102c:	2b04      	cmp	r3, #4
- 800102e:	d005      	beq.n	800103c <HAL_RCC_OscConfig+0x148>
+ 8001116:	69bb      	ldr	r3, [r7, #24]
+ 8001118:	2b04      	cmp	r3, #4
+ 800111a:	d005      	beq.n	8001128 <HAL_RCC_OscConfig+0x148>
        || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
- 8001030:	69bb      	ldr	r3, [r7, #24]
- 8001032:	2b0c      	cmp	r3, #12
- 8001034:	d119      	bne.n	800106a <HAL_RCC_OscConfig+0x176>
- 8001036:	697b      	ldr	r3, [r7, #20]
- 8001038:	2b00      	cmp	r3, #0
- 800103a:	d116      	bne.n	800106a <HAL_RCC_OscConfig+0x176>
+ 800111c:	69bb      	ldr	r3, [r7, #24]
+ 800111e:	2b0c      	cmp	r3, #12
+ 8001120:	d119      	bne.n	8001156 <HAL_RCC_OscConfig+0x176>
+ 8001122:	697b      	ldr	r3, [r7, #20]
+ 8001124:	2b00      	cmp	r3, #0
+ 8001126:	d116      	bne.n	8001156 <HAL_RCC_OscConfig+0x176>
     {
       /* When HSI is used as system clock it will not disabled */
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 800103c:	4b46      	ldr	r3, [pc, #280]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 800103e:	681b      	ldr	r3, [r3, #0]
- 8001040:	f003 0302 	and.w	r3, r3, #2
- 8001044:	2b00      	cmp	r3, #0
- 8001046:	d005      	beq.n	8001054 <HAL_RCC_OscConfig+0x160>
- 8001048:	687b      	ldr	r3, [r7, #4]
- 800104a:	68db      	ldr	r3, [r3, #12]
- 800104c:	2b01      	cmp	r3, #1
- 800104e:	d001      	beq.n	8001054 <HAL_RCC_OscConfig+0x160>
+ 8001128:	4b46      	ldr	r3, [pc, #280]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800112a:	681b      	ldr	r3, [r3, #0]
+ 800112c:	f003 0302 	and.w	r3, r3, #2
+ 8001130:	2b00      	cmp	r3, #0
+ 8001132:	d005      	beq.n	8001140 <HAL_RCC_OscConfig+0x160>
+ 8001134:	687b      	ldr	r3, [r7, #4]
+ 8001136:	68db      	ldr	r3, [r3, #12]
+ 8001138:	2b01      	cmp	r3, #1
+ 800113a:	d001      	beq.n	8001140 <HAL_RCC_OscConfig+0x160>
       {
         return HAL_ERROR;
- 8001050:	2301      	movs	r3, #1
- 8001052:	e276      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 800113c:	2301      	movs	r3, #1
+ 800113e:	e276      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       }
       /* Otherwise, just the calibration is allowed */
       else
       {
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8001054:	4b40      	ldr	r3, [pc, #256]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001056:	685b      	ldr	r3, [r3, #4]
- 8001058:	f423 52f8 	bic.w	r2, r3, #7936	@ 0x1f00
- 800105c:	687b      	ldr	r3, [r7, #4]
- 800105e:	691b      	ldr	r3, [r3, #16]
- 8001060:	021b      	lsls	r3, r3, #8
- 8001062:	493d      	ldr	r1, [pc, #244]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001064:	4313      	orrs	r3, r2
- 8001066:	604b      	str	r3, [r1, #4]
+ 8001140:	4b40      	ldr	r3, [pc, #256]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001142:	685b      	ldr	r3, [r3, #4]
+ 8001144:	f423 52f8 	bic.w	r2, r3, #7936	@ 0x1f00
+ 8001148:	687b      	ldr	r3, [r7, #4]
+ 800114a:	691b      	ldr	r3, [r3, #16]
+ 800114c:	021b      	lsls	r3, r3, #8
+ 800114e:	493d      	ldr	r1, [pc, #244]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001150:	4313      	orrs	r3, r2
+ 8001152:	604b      	str	r3, [r1, #4]
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8001068:	e03a      	b.n	80010e0 <HAL_RCC_OscConfig+0x1ec>
+ 8001154:	e03a      	b.n	80011cc <HAL_RCC_OscConfig+0x1ec>
       }
     }
     else
     {
       /* Check the HSI State */
       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- 800106a:	687b      	ldr	r3, [r7, #4]
- 800106c:	68db      	ldr	r3, [r3, #12]
- 800106e:	2b00      	cmp	r3, #0
- 8001070:	d020      	beq.n	80010b4 <HAL_RCC_OscConfig+0x1c0>
+ 8001156:	687b      	ldr	r3, [r7, #4]
+ 8001158:	68db      	ldr	r3, [r3, #12]
+ 800115a:	2b00      	cmp	r3, #0
+ 800115c:	d020      	beq.n	80011a0 <HAL_RCC_OscConfig+0x1c0>
       {
         /* Enable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_ENABLE();
- 8001072:	4b3a      	ldr	r3, [pc, #232]	@ (800115c <HAL_RCC_OscConfig+0x268>)
- 8001074:	2201      	movs	r2, #1
- 8001076:	601a      	str	r2, [r3, #0]
+ 800115e:	4b3a      	ldr	r3, [pc, #232]	@ (8001248 <HAL_RCC_OscConfig+0x268>)
+ 8001160:	2201      	movs	r2, #1
+ 8001162:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8001078:	f7ff fc64 	bl	8000944 <HAL_GetTick>
- 800107c:	6138      	str	r0, [r7, #16]
+ 8001164:	f7ff fc64 	bl	8000a30 <HAL_GetTick>
+ 8001168:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 800107e:	e008      	b.n	8001092 <HAL_RCC_OscConfig+0x19e>
+ 800116a:	e008      	b.n	800117e <HAL_RCC_OscConfig+0x19e>
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8001080:	f7ff fc60 	bl	8000944 <HAL_GetTick>
- 8001084:	4602      	mov	r2, r0
- 8001086:	693b      	ldr	r3, [r7, #16]
- 8001088:	1ad3      	subs	r3, r2, r3
- 800108a:	2b02      	cmp	r3, #2
- 800108c:	d901      	bls.n	8001092 <HAL_RCC_OscConfig+0x19e>
+ 800116c:	f7ff fc60 	bl	8000a30 <HAL_GetTick>
+ 8001170:	4602      	mov	r2, r0
+ 8001172:	693b      	ldr	r3, [r7, #16]
+ 8001174:	1ad3      	subs	r3, r2, r3
+ 8001176:	2b02      	cmp	r3, #2
+ 8001178:	d901      	bls.n	800117e <HAL_RCC_OscConfig+0x19e>
           {
             return HAL_TIMEOUT;
- 800108e:	2303      	movs	r3, #3
- 8001090:	e257      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 800117a:	2303      	movs	r3, #3
+ 800117c:	e257      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 8001092:	4b31      	ldr	r3, [pc, #196]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001094:	681b      	ldr	r3, [r3, #0]
- 8001096:	f003 0302 	and.w	r3, r3, #2
- 800109a:	2b00      	cmp	r3, #0
- 800109c:	d0f0      	beq.n	8001080 <HAL_RCC_OscConfig+0x18c>
+ 800117e:	4b31      	ldr	r3, [pc, #196]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001180:	681b      	ldr	r3, [r3, #0]
+ 8001182:	f003 0302 	and.w	r3, r3, #2
+ 8001186:	2b00      	cmp	r3, #0
+ 8001188:	d0f0      	beq.n	800116c <HAL_RCC_OscConfig+0x18c>
           }
         }
 
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 800109e:	4b2e      	ldr	r3, [pc, #184]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 80010a0:	685b      	ldr	r3, [r3, #4]
- 80010a2:	f423 52f8 	bic.w	r2, r3, #7936	@ 0x1f00
- 80010a6:	687b      	ldr	r3, [r7, #4]
- 80010a8:	691b      	ldr	r3, [r3, #16]
- 80010aa:	021b      	lsls	r3, r3, #8
- 80010ac:	492a      	ldr	r1, [pc, #168]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 80010ae:	4313      	orrs	r3, r2
- 80010b0:	604b      	str	r3, [r1, #4]
- 80010b2:	e015      	b.n	80010e0 <HAL_RCC_OscConfig+0x1ec>
+ 800118a:	4b2e      	ldr	r3, [pc, #184]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800118c:	685b      	ldr	r3, [r3, #4]
+ 800118e:	f423 52f8 	bic.w	r2, r3, #7936	@ 0x1f00
+ 8001192:	687b      	ldr	r3, [r7, #4]
+ 8001194:	691b      	ldr	r3, [r3, #16]
+ 8001196:	021b      	lsls	r3, r3, #8
+ 8001198:	492a      	ldr	r1, [pc, #168]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800119a:	4313      	orrs	r3, r2
+ 800119c:	604b      	str	r3, [r1, #4]
+ 800119e:	e015      	b.n	80011cc <HAL_RCC_OscConfig+0x1ec>
       }
       else
       {
         /* Disable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_DISABLE();
- 80010b4:	4b29      	ldr	r3, [pc, #164]	@ (800115c <HAL_RCC_OscConfig+0x268>)
- 80010b6:	2200      	movs	r2, #0
- 80010b8:	601a      	str	r2, [r3, #0]
+ 80011a0:	4b29      	ldr	r3, [pc, #164]	@ (8001248 <HAL_RCC_OscConfig+0x268>)
+ 80011a2:	2200      	movs	r2, #0
+ 80011a4:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 80010ba:	f7ff fc43 	bl	8000944 <HAL_GetTick>
- 80010be:	6138      	str	r0, [r7, #16]
+ 80011a6:	f7ff fc43 	bl	8000a30 <HAL_GetTick>
+ 80011aa:	6138      	str	r0, [r7, #16]
 
         /* Wait till HSI is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
- 80010c0:	e008      	b.n	80010d4 <HAL_RCC_OscConfig+0x1e0>
+ 80011ac:	e008      	b.n	80011c0 <HAL_RCC_OscConfig+0x1e0>
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80010c2:	f7ff fc3f 	bl	8000944 <HAL_GetTick>
- 80010c6:	4602      	mov	r2, r0
- 80010c8:	693b      	ldr	r3, [r7, #16]
- 80010ca:	1ad3      	subs	r3, r2, r3
- 80010cc:	2b02      	cmp	r3, #2
- 80010ce:	d901      	bls.n	80010d4 <HAL_RCC_OscConfig+0x1e0>
+ 80011ae:	f7ff fc3f 	bl	8000a30 <HAL_GetTick>
+ 80011b2:	4602      	mov	r2, r0
+ 80011b4:	693b      	ldr	r3, [r7, #16]
+ 80011b6:	1ad3      	subs	r3, r2, r3
+ 80011b8:	2b02      	cmp	r3, #2
+ 80011ba:	d901      	bls.n	80011c0 <HAL_RCC_OscConfig+0x1e0>
           {
             return HAL_TIMEOUT;
- 80010d0:	2303      	movs	r3, #3
- 80010d2:	e236      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80011bc:	2303      	movs	r3, #3
+ 80011be:	e236      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
- 80010d4:	4b20      	ldr	r3, [pc, #128]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 80010d6:	681b      	ldr	r3, [r3, #0]
- 80010d8:	f003 0302 	and.w	r3, r3, #2
- 80010dc:	2b00      	cmp	r3, #0
- 80010de:	d1f0      	bne.n	80010c2 <HAL_RCC_OscConfig+0x1ce>
+ 80011c0:	4b20      	ldr	r3, [pc, #128]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 80011c2:	681b      	ldr	r3, [r3, #0]
+ 80011c4:	f003 0302 	and.w	r3, r3, #2
+ 80011c8:	2b00      	cmp	r3, #0
+ 80011ca:	d1f0      	bne.n	80011ae <HAL_RCC_OscConfig+0x1ce>
         }
       }
     }
   }
   /*----------------------------- MSI Configuration --------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
- 80010e0:	687b      	ldr	r3, [r7, #4]
- 80010e2:	681b      	ldr	r3, [r3, #0]
- 80010e4:	f003 0310 	and.w	r3, r3, #16
- 80010e8:	2b00      	cmp	r3, #0
- 80010ea:	f000 80b8 	beq.w	800125e <HAL_RCC_OscConfig+0x36a>
+ 80011cc:	687b      	ldr	r3, [r7, #4]
+ 80011ce:	681b      	ldr	r3, [r3, #0]
+ 80011d0:	f003 0310 	and.w	r3, r3, #16
+ 80011d4:	2b00      	cmp	r3, #0
+ 80011d6:	f000 80b8 	beq.w	800134a <HAL_RCC_OscConfig+0x36a>
   {
     /* When the MSI is used as system clock it will not be disabled */
     if(sysclk_source == RCC_CFGR_SWS_MSI)
- 80010ee:	69bb      	ldr	r3, [r7, #24]
- 80010f0:	2b00      	cmp	r3, #0
- 80010f2:	d170      	bne.n	80011d6 <HAL_RCC_OscConfig+0x2e2>
+ 80011da:	69bb      	ldr	r3, [r7, #24]
+ 80011dc:	2b00      	cmp	r3, #0
+ 80011de:	d170      	bne.n	80012c2 <HAL_RCC_OscConfig+0x2e2>
     {
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
- 80010f4:	4b18      	ldr	r3, [pc, #96]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 80010f6:	681b      	ldr	r3, [r3, #0]
- 80010f8:	f403 7300 	and.w	r3, r3, #512	@ 0x200
- 80010fc:	2b00      	cmp	r3, #0
- 80010fe:	d005      	beq.n	800110c <HAL_RCC_OscConfig+0x218>
- 8001100:	687b      	ldr	r3, [r7, #4]
- 8001102:	699b      	ldr	r3, [r3, #24]
- 8001104:	2b00      	cmp	r3, #0
- 8001106:	d101      	bne.n	800110c <HAL_RCC_OscConfig+0x218>
+ 80011e0:	4b18      	ldr	r3, [pc, #96]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 80011e2:	681b      	ldr	r3, [r3, #0]
+ 80011e4:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 80011e8:	2b00      	cmp	r3, #0
+ 80011ea:	d005      	beq.n	80011f8 <HAL_RCC_OscConfig+0x218>
+ 80011ec:	687b      	ldr	r3, [r7, #4]
+ 80011ee:	699b      	ldr	r3, [r3, #24]
+ 80011f0:	2b00      	cmp	r3, #0
+ 80011f2:	d101      	bne.n	80011f8 <HAL_RCC_OscConfig+0x218>
       {
         return HAL_ERROR;
- 8001108:	2301      	movs	r3, #1
- 800110a:	e21a      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80011f4:	2301      	movs	r3, #1
+ 80011f6:	e21a      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
 
         /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
            must be correctly programmed according to the frequency of the CPU clock
            (HCLK) and the supply voltage of the device. */
         if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
- 800110c:	687b      	ldr	r3, [r7, #4]
- 800110e:	6a1a      	ldr	r2, [r3, #32]
- 8001110:	4b11      	ldr	r3, [pc, #68]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001112:	685b      	ldr	r3, [r3, #4]
- 8001114:	f403 4360 	and.w	r3, r3, #57344	@ 0xe000
- 8001118:	429a      	cmp	r2, r3
- 800111a:	d921      	bls.n	8001160 <HAL_RCC_OscConfig+0x26c>
+ 80011f8:	687b      	ldr	r3, [r7, #4]
+ 80011fa:	6a1a      	ldr	r2, [r3, #32]
+ 80011fc:	4b11      	ldr	r3, [pc, #68]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 80011fe:	685b      	ldr	r3, [r3, #4]
+ 8001200:	f403 4360 	and.w	r3, r3, #57344	@ 0xe000
+ 8001204:	429a      	cmp	r2, r3
+ 8001206:	d921      	bls.n	800124c <HAL_RCC_OscConfig+0x26c>
         {
           /* First increase number of wait states update if necessary */
           if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
- 800111c:	687b      	ldr	r3, [r7, #4]
- 800111e:	6a1b      	ldr	r3, [r3, #32]
- 8001120:	4618      	mov	r0, r3
- 8001122:	f000 fc7d 	bl	8001a20 <RCC_SetFlashLatencyFromMSIRange>
- 8001126:	4603      	mov	r3, r0
- 8001128:	2b00      	cmp	r3, #0
- 800112a:	d001      	beq.n	8001130 <HAL_RCC_OscConfig+0x23c>
+ 8001208:	687b      	ldr	r3, [r7, #4]
+ 800120a:	6a1b      	ldr	r3, [r3, #32]
+ 800120c:	4618      	mov	r0, r3
+ 800120e:	f000 fc7d 	bl	8001b0c <RCC_SetFlashLatencyFromMSIRange>
+ 8001212:	4603      	mov	r3, r0
+ 8001214:	2b00      	cmp	r3, #0
+ 8001216:	d001      	beq.n	800121c <HAL_RCC_OscConfig+0x23c>
           {
             return HAL_ERROR;
- 800112c:	2301      	movs	r3, #1
- 800112e:	e208      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 8001218:	2301      	movs	r3, #1
+ 800121a:	e208      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
           }
 
           /* Selects the Multiple Speed oscillator (MSI) clock range .*/
           __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- 8001130:	4b09      	ldr	r3, [pc, #36]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001132:	685b      	ldr	r3, [r3, #4]
- 8001134:	f423 4260 	bic.w	r2, r3, #57344	@ 0xe000
- 8001138:	687b      	ldr	r3, [r7, #4]
- 800113a:	6a1b      	ldr	r3, [r3, #32]
- 800113c:	4906      	ldr	r1, [pc, #24]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 800113e:	4313      	orrs	r3, r2
- 8001140:	604b      	str	r3, [r1, #4]
+ 800121c:	4b09      	ldr	r3, [pc, #36]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800121e:	685b      	ldr	r3, [r3, #4]
+ 8001220:	f423 4260 	bic.w	r2, r3, #57344	@ 0xe000
+ 8001224:	687b      	ldr	r3, [r7, #4]
+ 8001226:	6a1b      	ldr	r3, [r3, #32]
+ 8001228:	4906      	ldr	r1, [pc, #24]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800122a:	4313      	orrs	r3, r2
+ 800122c:	604b      	str	r3, [r1, #4]
           /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
           __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
- 8001142:	4b05      	ldr	r3, [pc, #20]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001144:	685b      	ldr	r3, [r3, #4]
- 8001146:	f023 427f 	bic.w	r2, r3, #4278190080	@ 0xff000000
- 800114a:	687b      	ldr	r3, [r7, #4]
- 800114c:	69db      	ldr	r3, [r3, #28]
- 800114e:	061b      	lsls	r3, r3, #24
- 8001150:	4901      	ldr	r1, [pc, #4]	@ (8001158 <HAL_RCC_OscConfig+0x264>)
- 8001152:	4313      	orrs	r3, r2
- 8001154:	604b      	str	r3, [r1, #4]
- 8001156:	e020      	b.n	800119a <HAL_RCC_OscConfig+0x2a6>
- 8001158:	40023800 	.word	0x40023800
- 800115c:	42470000 	.word	0x42470000
+ 800122e:	4b05      	ldr	r3, [pc, #20]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 8001230:	685b      	ldr	r3, [r3, #4]
+ 8001232:	f023 427f 	bic.w	r2, r3, #4278190080	@ 0xff000000
+ 8001236:	687b      	ldr	r3, [r7, #4]
+ 8001238:	69db      	ldr	r3, [r3, #28]
+ 800123a:	061b      	lsls	r3, r3, #24
+ 800123c:	4901      	ldr	r1, [pc, #4]	@ (8001244 <HAL_RCC_OscConfig+0x264>)
+ 800123e:	4313      	orrs	r3, r2
+ 8001240:	604b      	str	r3, [r1, #4]
+ 8001242:	e020      	b.n	8001286 <HAL_RCC_OscConfig+0x2a6>
+ 8001244:	40023800 	.word	0x40023800
+ 8001248:	42470000 	.word	0x42470000
         }
         else
         {
           /* Else, keep current flash latency while decreasing applies */
           /* Selects the Multiple Speed oscillator (MSI) clock range .*/
           __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- 8001160:	4b99      	ldr	r3, [pc, #612]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001162:	685b      	ldr	r3, [r3, #4]
- 8001164:	f423 4260 	bic.w	r2, r3, #57344	@ 0xe000
- 8001168:	687b      	ldr	r3, [r7, #4]
- 800116a:	6a1b      	ldr	r3, [r3, #32]
- 800116c:	4996      	ldr	r1, [pc, #600]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 800116e:	4313      	orrs	r3, r2
- 8001170:	604b      	str	r3, [r1, #4]
+ 800124c:	4b99      	ldr	r3, [pc, #612]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800124e:	685b      	ldr	r3, [r3, #4]
+ 8001250:	f423 4260 	bic.w	r2, r3, #57344	@ 0xe000
+ 8001254:	687b      	ldr	r3, [r7, #4]
+ 8001256:	6a1b      	ldr	r3, [r3, #32]
+ 8001258:	4996      	ldr	r1, [pc, #600]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800125a:	4313      	orrs	r3, r2
+ 800125c:	604b      	str	r3, [r1, #4]
           /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
           __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
- 8001172:	4b95      	ldr	r3, [pc, #596]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001174:	685b      	ldr	r3, [r3, #4]
- 8001176:	f023 427f 	bic.w	r2, r3, #4278190080	@ 0xff000000
- 800117a:	687b      	ldr	r3, [r7, #4]
- 800117c:	69db      	ldr	r3, [r3, #28]
- 800117e:	061b      	lsls	r3, r3, #24
- 8001180:	4991      	ldr	r1, [pc, #580]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001182:	4313      	orrs	r3, r2
- 8001184:	604b      	str	r3, [r1, #4]
+ 800125e:	4b95      	ldr	r3, [pc, #596]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001260:	685b      	ldr	r3, [r3, #4]
+ 8001262:	f023 427f 	bic.w	r2, r3, #4278190080	@ 0xff000000
+ 8001266:	687b      	ldr	r3, [r7, #4]
+ 8001268:	69db      	ldr	r3, [r3, #28]
+ 800126a:	061b      	lsls	r3, r3, #24
+ 800126c:	4991      	ldr	r1, [pc, #580]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800126e:	4313      	orrs	r3, r2
+ 8001270:	604b      	str	r3, [r1, #4]
 
           /* Decrease number of wait states update if necessary */
           if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
- 8001186:	687b      	ldr	r3, [r7, #4]
- 8001188:	6a1b      	ldr	r3, [r3, #32]
- 800118a:	4618      	mov	r0, r3
- 800118c:	f000 fc48 	bl	8001a20 <RCC_SetFlashLatencyFromMSIRange>
- 8001190:	4603      	mov	r3, r0
- 8001192:	2b00      	cmp	r3, #0
- 8001194:	d001      	beq.n	800119a <HAL_RCC_OscConfig+0x2a6>
+ 8001272:	687b      	ldr	r3, [r7, #4]
+ 8001274:	6a1b      	ldr	r3, [r3, #32]
+ 8001276:	4618      	mov	r0, r3
+ 8001278:	f000 fc48 	bl	8001b0c <RCC_SetFlashLatencyFromMSIRange>
+ 800127c:	4603      	mov	r3, r0
+ 800127e:	2b00      	cmp	r3, #0
+ 8001280:	d001      	beq.n	8001286 <HAL_RCC_OscConfig+0x2a6>
           {
             return HAL_ERROR;
- 8001196:	2301      	movs	r3, #1
- 8001198:	e1d3      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 8001282:	2301      	movs	r3, #1
+ 8001284:	e1d3      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
           }
         }
 
         /* Update the SystemCoreClock global variable */
         SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
- 800119a:	687b      	ldr	r3, [r7, #4]
- 800119c:	6a1b      	ldr	r3, [r3, #32]
- 800119e:	0b5b      	lsrs	r3, r3, #13
- 80011a0:	3301      	adds	r3, #1
- 80011a2:	f44f 4200 	mov.w	r2, #32768	@ 0x8000
- 80011a6:	fa02 f303 	lsl.w	r3, r2, r3
+ 8001286:	687b      	ldr	r3, [r7, #4]
+ 8001288:	6a1b      	ldr	r3, [r3, #32]
+ 800128a:	0b5b      	lsrs	r3, r3, #13
+ 800128c:	3301      	adds	r3, #1
+ 800128e:	f44f 4200 	mov.w	r2, #32768	@ 0x8000
+ 8001292:	fa02 f303 	lsl.w	r3, r2, r3
                            >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
- 80011aa:	4a87      	ldr	r2, [pc, #540]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80011ac:	6892      	ldr	r2, [r2, #8]
- 80011ae:	0912      	lsrs	r2, r2, #4
- 80011b0:	f002 020f 	and.w	r2, r2, #15
- 80011b4:	4985      	ldr	r1, [pc, #532]	@ (80013cc <HAL_RCC_OscConfig+0x4d8>)
- 80011b6:	5c8a      	ldrb	r2, [r1, r2]
- 80011b8:	40d3      	lsrs	r3, r2
+ 8001296:	4a87      	ldr	r2, [pc, #540]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001298:	6892      	ldr	r2, [r2, #8]
+ 800129a:	0912      	lsrs	r2, r2, #4
+ 800129c:	f002 020f 	and.w	r2, r2, #15
+ 80012a0:	4985      	ldr	r1, [pc, #532]	@ (80014b8 <HAL_RCC_OscConfig+0x4d8>)
+ 80012a2:	5c8a      	ldrb	r2, [r1, r2]
+ 80012a4:	40d3      	lsrs	r3, r2
         SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
- 80011ba:	4a85      	ldr	r2, [pc, #532]	@ (80013d0 <HAL_RCC_OscConfig+0x4dc>)
- 80011bc:	6013      	str	r3, [r2, #0]
+ 80012a6:	4a85      	ldr	r2, [pc, #532]	@ (80014bc <HAL_RCC_OscConfig+0x4dc>)
+ 80012a8:	6013      	str	r3, [r2, #0]
 
         /* Configure the source of time base considering new system clocks settings*/
         status = HAL_InitTick(uwTickPrio);
- 80011be:	4b85      	ldr	r3, [pc, #532]	@ (80013d4 <HAL_RCC_OscConfig+0x4e0>)
- 80011c0:	681b      	ldr	r3, [r3, #0]
- 80011c2:	4618      	mov	r0, r3
- 80011c4:	f7ff fb72 	bl	80008ac <HAL_InitTick>
- 80011c8:	4603      	mov	r3, r0
- 80011ca:	73fb      	strb	r3, [r7, #15]
+ 80012aa:	4b85      	ldr	r3, [pc, #532]	@ (80014c0 <HAL_RCC_OscConfig+0x4e0>)
+ 80012ac:	681b      	ldr	r3, [r3, #0]
+ 80012ae:	4618      	mov	r0, r3
+ 80012b0:	f7ff fb72 	bl	8000998 <HAL_InitTick>
+ 80012b4:	4603      	mov	r3, r0
+ 80012b6:	73fb      	strb	r3, [r7, #15]
         if(status != HAL_OK)
- 80011cc:	7bfb      	ldrb	r3, [r7, #15]
- 80011ce:	2b00      	cmp	r3, #0
- 80011d0:	d045      	beq.n	800125e <HAL_RCC_OscConfig+0x36a>
+ 80012b8:	7bfb      	ldrb	r3, [r7, #15]
+ 80012ba:	2b00      	cmp	r3, #0
+ 80012bc:	d045      	beq.n	800134a <HAL_RCC_OscConfig+0x36a>
         {
           return status;
- 80011d2:	7bfb      	ldrb	r3, [r7, #15]
- 80011d4:	e1b5      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80012be:	7bfb      	ldrb	r3, [r7, #15]
+ 80012c0:	e1b5      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
     {
       /* Check MSI State */
       assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
 
       /* Check the MSI State */
       if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
- 80011d6:	687b      	ldr	r3, [r7, #4]
- 80011d8:	699b      	ldr	r3, [r3, #24]
- 80011da:	2b00      	cmp	r3, #0
- 80011dc:	d029      	beq.n	8001232 <HAL_RCC_OscConfig+0x33e>
+ 80012c2:	687b      	ldr	r3, [r7, #4]
+ 80012c4:	699b      	ldr	r3, [r3, #24]
+ 80012c6:	2b00      	cmp	r3, #0
+ 80012c8:	d029      	beq.n	800131e <HAL_RCC_OscConfig+0x33e>
       {
         /* Enable the Multi Speed oscillator (MSI). */
         __HAL_RCC_MSI_ENABLE();
- 80011de:	4b7e      	ldr	r3, [pc, #504]	@ (80013d8 <HAL_RCC_OscConfig+0x4e4>)
- 80011e0:	2201      	movs	r2, #1
- 80011e2:	601a      	str	r2, [r3, #0]
+ 80012ca:	4b7e      	ldr	r3, [pc, #504]	@ (80014c4 <HAL_RCC_OscConfig+0x4e4>)
+ 80012cc:	2201      	movs	r2, #1
+ 80012ce:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 80011e4:	f7ff fbae 	bl	8000944 <HAL_GetTick>
- 80011e8:	6138      	str	r0, [r7, #16]
+ 80012d0:	f7ff fbae 	bl	8000a30 <HAL_GetTick>
+ 80012d4:	6138      	str	r0, [r7, #16]
 
         /* Wait till MSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
- 80011ea:	e008      	b.n	80011fe <HAL_RCC_OscConfig+0x30a>
+ 80012d6:	e008      	b.n	80012ea <HAL_RCC_OscConfig+0x30a>
         {
           if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
- 80011ec:	f7ff fbaa 	bl	8000944 <HAL_GetTick>
- 80011f0:	4602      	mov	r2, r0
- 80011f2:	693b      	ldr	r3, [r7, #16]
- 80011f4:	1ad3      	subs	r3, r2, r3
- 80011f6:	2b02      	cmp	r3, #2
- 80011f8:	d901      	bls.n	80011fe <HAL_RCC_OscConfig+0x30a>
+ 80012d8:	f7ff fbaa 	bl	8000a30 <HAL_GetTick>
+ 80012dc:	4602      	mov	r2, r0
+ 80012de:	693b      	ldr	r3, [r7, #16]
+ 80012e0:	1ad3      	subs	r3, r2, r3
+ 80012e2:	2b02      	cmp	r3, #2
+ 80012e4:	d901      	bls.n	80012ea <HAL_RCC_OscConfig+0x30a>
           {
             return HAL_TIMEOUT;
- 80011fa:	2303      	movs	r3, #3
- 80011fc:	e1a1      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80012e6:	2303      	movs	r3, #3
+ 80012e8:	e1a1      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
- 80011fe:	4b72      	ldr	r3, [pc, #456]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001200:	681b      	ldr	r3, [r3, #0]
- 8001202:	f403 7300 	and.w	r3, r3, #512	@ 0x200
- 8001206:	2b00      	cmp	r3, #0
- 8001208:	d0f0      	beq.n	80011ec <HAL_RCC_OscConfig+0x2f8>
+ 80012ea:	4b72      	ldr	r3, [pc, #456]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 80012ec:	681b      	ldr	r3, [r3, #0]
+ 80012ee:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 80012f2:	2b00      	cmp	r3, #0
+ 80012f4:	d0f0      	beq.n	80012d8 <HAL_RCC_OscConfig+0x2f8>
         /* Check MSICalibrationValue and MSIClockRange input parameters */
         assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
         assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
 
         /* Selects the Multiple Speed oscillator (MSI) clock range .*/
         __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- 800120a:	4b6f      	ldr	r3, [pc, #444]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 800120c:	685b      	ldr	r3, [r3, #4]
- 800120e:	f423 4260 	bic.w	r2, r3, #57344	@ 0xe000
- 8001212:	687b      	ldr	r3, [r7, #4]
- 8001214:	6a1b      	ldr	r3, [r3, #32]
- 8001216:	496c      	ldr	r1, [pc, #432]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001218:	4313      	orrs	r3, r2
- 800121a:	604b      	str	r3, [r1, #4]
+ 80012f6:	4b6f      	ldr	r3, [pc, #444]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 80012f8:	685b      	ldr	r3, [r3, #4]
+ 80012fa:	f423 4260 	bic.w	r2, r3, #57344	@ 0xe000
+ 80012fe:	687b      	ldr	r3, [r7, #4]
+ 8001300:	6a1b      	ldr	r3, [r3, #32]
+ 8001302:	496c      	ldr	r1, [pc, #432]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001304:	4313      	orrs	r3, r2
+ 8001306:	604b      	str	r3, [r1, #4]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
         __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
- 800121c:	4b6a      	ldr	r3, [pc, #424]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 800121e:	685b      	ldr	r3, [r3, #4]
- 8001220:	f023 427f 	bic.w	r2, r3, #4278190080	@ 0xff000000
- 8001224:	687b      	ldr	r3, [r7, #4]
- 8001226:	69db      	ldr	r3, [r3, #28]
- 8001228:	061b      	lsls	r3, r3, #24
- 800122a:	4967      	ldr	r1, [pc, #412]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 800122c:	4313      	orrs	r3, r2
- 800122e:	604b      	str	r3, [r1, #4]
- 8001230:	e015      	b.n	800125e <HAL_RCC_OscConfig+0x36a>
+ 8001308:	4b6a      	ldr	r3, [pc, #424]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800130a:	685b      	ldr	r3, [r3, #4]
+ 800130c:	f023 427f 	bic.w	r2, r3, #4278190080	@ 0xff000000
+ 8001310:	687b      	ldr	r3, [r7, #4]
+ 8001312:	69db      	ldr	r3, [r3, #28]
+ 8001314:	061b      	lsls	r3, r3, #24
+ 8001316:	4967      	ldr	r1, [pc, #412]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001318:	4313      	orrs	r3, r2
+ 800131a:	604b      	str	r3, [r1, #4]
+ 800131c:	e015      	b.n	800134a <HAL_RCC_OscConfig+0x36a>
 
       }
       else
       {
         /* Disable the Multi Speed oscillator (MSI). */
         __HAL_RCC_MSI_DISABLE();
- 8001232:	4b69      	ldr	r3, [pc, #420]	@ (80013d8 <HAL_RCC_OscConfig+0x4e4>)
- 8001234:	2200      	movs	r2, #0
- 8001236:	601a      	str	r2, [r3, #0]
+ 800131e:	4b69      	ldr	r3, [pc, #420]	@ (80014c4 <HAL_RCC_OscConfig+0x4e4>)
+ 8001320:	2200      	movs	r2, #0
+ 8001322:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8001238:	f7ff fb84 	bl	8000944 <HAL_GetTick>
- 800123c:	6138      	str	r0, [r7, #16]
+ 8001324:	f7ff fb84 	bl	8000a30 <HAL_GetTick>
+ 8001328:	6138      	str	r0, [r7, #16]
 
         /* Wait till MSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
- 800123e:	e008      	b.n	8001252 <HAL_RCC_OscConfig+0x35e>
+ 800132a:	e008      	b.n	800133e <HAL_RCC_OscConfig+0x35e>
         {
           if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
- 8001240:	f7ff fb80 	bl	8000944 <HAL_GetTick>
- 8001244:	4602      	mov	r2, r0
- 8001246:	693b      	ldr	r3, [r7, #16]
- 8001248:	1ad3      	subs	r3, r2, r3
- 800124a:	2b02      	cmp	r3, #2
- 800124c:	d901      	bls.n	8001252 <HAL_RCC_OscConfig+0x35e>
+ 800132c:	f7ff fb80 	bl	8000a30 <HAL_GetTick>
+ 8001330:	4602      	mov	r2, r0
+ 8001332:	693b      	ldr	r3, [r7, #16]
+ 8001334:	1ad3      	subs	r3, r2, r3
+ 8001336:	2b02      	cmp	r3, #2
+ 8001338:	d901      	bls.n	800133e <HAL_RCC_OscConfig+0x35e>
           {
             return HAL_TIMEOUT;
- 800124e:	2303      	movs	r3, #3
- 8001250:	e177      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 800133a:	2303      	movs	r3, #3
+ 800133c:	e177      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
- 8001252:	4b5d      	ldr	r3, [pc, #372]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001254:	681b      	ldr	r3, [r3, #0]
- 8001256:	f403 7300 	and.w	r3, r3, #512	@ 0x200
- 800125a:	2b00      	cmp	r3, #0
- 800125c:	d1f0      	bne.n	8001240 <HAL_RCC_OscConfig+0x34c>
+ 800133e:	4b5d      	ldr	r3, [pc, #372]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001340:	681b      	ldr	r3, [r3, #0]
+ 8001342:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 8001346:	2b00      	cmp	r3, #0
+ 8001348:	d1f0      	bne.n	800132c <HAL_RCC_OscConfig+0x34c>
         }
       }
     }
   }
   /*------------------------------ LSI Configuration -------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 800125e:	687b      	ldr	r3, [r7, #4]
- 8001260:	681b      	ldr	r3, [r3, #0]
- 8001262:	f003 0308 	and.w	r3, r3, #8
- 8001266:	2b00      	cmp	r3, #0
- 8001268:	d030      	beq.n	80012cc <HAL_RCC_OscConfig+0x3d8>
+ 800134a:	687b      	ldr	r3, [r7, #4]
+ 800134c:	681b      	ldr	r3, [r3, #0]
+ 800134e:	f003 0308 	and.w	r3, r3, #8
+ 8001352:	2b00      	cmp	r3, #0
+ 8001354:	d030      	beq.n	80013b8 <HAL_RCC_OscConfig+0x3d8>
   {
     /* Check the parameters */
     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
 
     /* Check the LSI State */
     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- 800126a:	687b      	ldr	r3, [r7, #4]
- 800126c:	695b      	ldr	r3, [r3, #20]
- 800126e:	2b00      	cmp	r3, #0
- 8001270:	d016      	beq.n	80012a0 <HAL_RCC_OscConfig+0x3ac>
+ 8001356:	687b      	ldr	r3, [r7, #4]
+ 8001358:	695b      	ldr	r3, [r3, #20]
+ 800135a:	2b00      	cmp	r3, #0
+ 800135c:	d016      	beq.n	800138c <HAL_RCC_OscConfig+0x3ac>
     {
       /* Enable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_ENABLE();
- 8001272:	4b5a      	ldr	r3, [pc, #360]	@ (80013dc <HAL_RCC_OscConfig+0x4e8>)
- 8001274:	2201      	movs	r2, #1
- 8001276:	601a      	str	r2, [r3, #0]
+ 800135e:	4b5a      	ldr	r3, [pc, #360]	@ (80014c8 <HAL_RCC_OscConfig+0x4e8>)
+ 8001360:	2201      	movs	r2, #1
+ 8001362:	601a      	str	r2, [r3, #0]
 
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8001278:	f7ff fb64 	bl	8000944 <HAL_GetTick>
- 800127c:	6138      	str	r0, [r7, #16]
+ 8001364:	f7ff fb64 	bl	8000a30 <HAL_GetTick>
+ 8001368:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSI is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
- 800127e:	e008      	b.n	8001292 <HAL_RCC_OscConfig+0x39e>
+ 800136a:	e008      	b.n	800137e <HAL_RCC_OscConfig+0x39e>
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8001280:	f7ff fb60 	bl	8000944 <HAL_GetTick>
- 8001284:	4602      	mov	r2, r0
- 8001286:	693b      	ldr	r3, [r7, #16]
- 8001288:	1ad3      	subs	r3, r2, r3
- 800128a:	2b02      	cmp	r3, #2
- 800128c:	d901      	bls.n	8001292 <HAL_RCC_OscConfig+0x39e>
+ 800136c:	f7ff fb60 	bl	8000a30 <HAL_GetTick>
+ 8001370:	4602      	mov	r2, r0
+ 8001372:	693b      	ldr	r3, [r7, #16]
+ 8001374:	1ad3      	subs	r3, r2, r3
+ 8001376:	2b02      	cmp	r3, #2
+ 8001378:	d901      	bls.n	800137e <HAL_RCC_OscConfig+0x39e>
         {
           return HAL_TIMEOUT;
- 800128e:	2303      	movs	r3, #3
- 8001290:	e157      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 800137a:	2303      	movs	r3, #3
+ 800137c:	e157      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
- 8001292:	4b4d      	ldr	r3, [pc, #308]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001294:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001296:	f003 0302 	and.w	r3, r3, #2
- 800129a:	2b00      	cmp	r3, #0
- 800129c:	d0f0      	beq.n	8001280 <HAL_RCC_OscConfig+0x38c>
- 800129e:	e015      	b.n	80012cc <HAL_RCC_OscConfig+0x3d8>
+ 800137e:	4b4d      	ldr	r3, [pc, #308]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001380:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8001382:	f003 0302 	and.w	r3, r3, #2
+ 8001386:	2b00      	cmp	r3, #0
+ 8001388:	d0f0      	beq.n	800136c <HAL_RCC_OscConfig+0x38c>
+ 800138a:	e015      	b.n	80013b8 <HAL_RCC_OscConfig+0x3d8>
       }
     }
     else
     {
       /* Disable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_DISABLE();
- 80012a0:	4b4e      	ldr	r3, [pc, #312]	@ (80013dc <HAL_RCC_OscConfig+0x4e8>)
- 80012a2:	2200      	movs	r2, #0
- 80012a4:	601a      	str	r2, [r3, #0]
+ 800138c:	4b4e      	ldr	r3, [pc, #312]	@ (80014c8 <HAL_RCC_OscConfig+0x4e8>)
+ 800138e:	2200      	movs	r2, #0
+ 8001390:	601a      	str	r2, [r3, #0]
 
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 80012a6:	f7ff fb4d 	bl	8000944 <HAL_GetTick>
- 80012aa:	6138      	str	r0, [r7, #16]
+ 8001392:	f7ff fb4d 	bl	8000a30 <HAL_GetTick>
+ 8001396:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSI is disabled */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
- 80012ac:	e008      	b.n	80012c0 <HAL_RCC_OscConfig+0x3cc>
+ 8001398:	e008      	b.n	80013ac <HAL_RCC_OscConfig+0x3cc>
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 80012ae:	f7ff fb49 	bl	8000944 <HAL_GetTick>
- 80012b2:	4602      	mov	r2, r0
- 80012b4:	693b      	ldr	r3, [r7, #16]
- 80012b6:	1ad3      	subs	r3, r2, r3
- 80012b8:	2b02      	cmp	r3, #2
- 80012ba:	d901      	bls.n	80012c0 <HAL_RCC_OscConfig+0x3cc>
+ 800139a:	f7ff fb49 	bl	8000a30 <HAL_GetTick>
+ 800139e:	4602      	mov	r2, r0
+ 80013a0:	693b      	ldr	r3, [r7, #16]
+ 80013a2:	1ad3      	subs	r3, r2, r3
+ 80013a4:	2b02      	cmp	r3, #2
+ 80013a6:	d901      	bls.n	80013ac <HAL_RCC_OscConfig+0x3cc>
         {
           return HAL_TIMEOUT;
- 80012bc:	2303      	movs	r3, #3
- 80012be:	e140      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80013a8:	2303      	movs	r3, #3
+ 80013aa:	e140      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
- 80012c0:	4b41      	ldr	r3, [pc, #260]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80012c2:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 80012c4:	f003 0302 	and.w	r3, r3, #2
- 80012c8:	2b00      	cmp	r3, #0
- 80012ca:	d1f0      	bne.n	80012ae <HAL_RCC_OscConfig+0x3ba>
+ 80013ac:	4b41      	ldr	r3, [pc, #260]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 80013ae:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80013b0:	f003 0302 	and.w	r3, r3, #2
+ 80013b4:	2b00      	cmp	r3, #0
+ 80013b6:	d1f0      	bne.n	800139a <HAL_RCC_OscConfig+0x3ba>
         }
       }
     }
   }
   /*------------------------------ LSE Configuration -------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 80012cc:	687b      	ldr	r3, [r7, #4]
- 80012ce:	681b      	ldr	r3, [r3, #0]
- 80012d0:	f003 0304 	and.w	r3, r3, #4
- 80012d4:	2b00      	cmp	r3, #0
- 80012d6:	f000 80b5 	beq.w	8001444 <HAL_RCC_OscConfig+0x550>
+ 80013b8:	687b      	ldr	r3, [r7, #4]
+ 80013ba:	681b      	ldr	r3, [r3, #0]
+ 80013bc:	f003 0304 	and.w	r3, r3, #4
+ 80013c0:	2b00      	cmp	r3, #0
+ 80013c2:	f000 80b5 	beq.w	8001530 <HAL_RCC_OscConfig+0x550>
   {
     FlagStatus       pwrclkchanged = RESET;
- 80012da:	2300      	movs	r3, #0
- 80012dc:	77fb      	strb	r3, [r7, #31]
+ 80013c6:	2300      	movs	r3, #0
+ 80013c8:	77fb      	strb	r3, [r7, #31]
     /* Check the parameters */
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 
     /* Update LSE configuration in Backup Domain control register    */
     /* Requires to enable write access to Backup Domain of necessary */
     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80012de:	4b3a      	ldr	r3, [pc, #232]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80012e0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 80012e2:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 80012e6:	2b00      	cmp	r3, #0
- 80012e8:	d10d      	bne.n	8001306 <HAL_RCC_OscConfig+0x412>
+ 80013ca:	4b3a      	ldr	r3, [pc, #232]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 80013cc:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80013ce:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 80013d2:	2b00      	cmp	r3, #0
+ 80013d4:	d10d      	bne.n	80013f2 <HAL_RCC_OscConfig+0x412>
     {
       __HAL_RCC_PWR_CLK_ENABLE();
- 80012ea:	4b37      	ldr	r3, [pc, #220]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80012ec:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 80012ee:	4a36      	ldr	r2, [pc, #216]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80012f0:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
- 80012f4:	6253      	str	r3, [r2, #36]	@ 0x24
- 80012f6:	4b34      	ldr	r3, [pc, #208]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80012f8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 80012fa:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 80012fe:	60bb      	str	r3, [r7, #8]
- 8001300:	68bb      	ldr	r3, [r7, #8]
+ 80013d6:	4b37      	ldr	r3, [pc, #220]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 80013d8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80013da:	4a36      	ldr	r2, [pc, #216]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 80013dc:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 80013e0:	6253      	str	r3, [r2, #36]	@ 0x24
+ 80013e2:	4b34      	ldr	r3, [pc, #208]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 80013e4:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80013e6:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 80013ea:	60bb      	str	r3, [r7, #8]
+ 80013ec:	68bb      	ldr	r3, [r7, #8]
       pwrclkchanged = SET;
- 8001302:	2301      	movs	r3, #1
- 8001304:	77fb      	strb	r3, [r7, #31]
+ 80013ee:	2301      	movs	r3, #1
+ 80013f0:	77fb      	strb	r3, [r7, #31]
     }
 
     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8001306:	4b36      	ldr	r3, [pc, #216]	@ (80013e0 <HAL_RCC_OscConfig+0x4ec>)
- 8001308:	681b      	ldr	r3, [r3, #0]
- 800130a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 800130e:	2b00      	cmp	r3, #0
- 8001310:	d118      	bne.n	8001344 <HAL_RCC_OscConfig+0x450>
+ 80013f2:	4b36      	ldr	r3, [pc, #216]	@ (80014cc <HAL_RCC_OscConfig+0x4ec>)
+ 80013f4:	681b      	ldr	r3, [r3, #0]
+ 80013f6:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 80013fa:	2b00      	cmp	r3, #0
+ 80013fc:	d118      	bne.n	8001430 <HAL_RCC_OscConfig+0x450>
     {
       /* Enable write access to Backup domain */
       SET_BIT(PWR->CR, PWR_CR_DBP);
- 8001312:	4b33      	ldr	r3, [pc, #204]	@ (80013e0 <HAL_RCC_OscConfig+0x4ec>)
- 8001314:	681b      	ldr	r3, [r3, #0]
- 8001316:	4a32      	ldr	r2, [pc, #200]	@ (80013e0 <HAL_RCC_OscConfig+0x4ec>)
- 8001318:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
- 800131c:	6013      	str	r3, [r2, #0]
+ 80013fe:	4b33      	ldr	r3, [pc, #204]	@ (80014cc <HAL_RCC_OscConfig+0x4ec>)
+ 8001400:	681b      	ldr	r3, [r3, #0]
+ 8001402:	4a32      	ldr	r2, [pc, #200]	@ (80014cc <HAL_RCC_OscConfig+0x4ec>)
+ 8001404:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 8001408:	6013      	str	r3, [r2, #0]
 
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
- 800131e:	f7ff fb11 	bl	8000944 <HAL_GetTick>
- 8001322:	6138      	str	r0, [r7, #16]
+ 800140a:	f7ff fb11 	bl	8000a30 <HAL_GetTick>
+ 800140e:	6138      	str	r0, [r7, #16]
 
       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8001324:	e008      	b.n	8001338 <HAL_RCC_OscConfig+0x444>
+ 8001410:	e008      	b.n	8001424 <HAL_RCC_OscConfig+0x444>
       {
         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8001326:	f7ff fb0d 	bl	8000944 <HAL_GetTick>
- 800132a:	4602      	mov	r2, r0
- 800132c:	693b      	ldr	r3, [r7, #16]
- 800132e:	1ad3      	subs	r3, r2, r3
- 8001330:	2b64      	cmp	r3, #100	@ 0x64
- 8001332:	d901      	bls.n	8001338 <HAL_RCC_OscConfig+0x444>
+ 8001412:	f7ff fb0d 	bl	8000a30 <HAL_GetTick>
+ 8001416:	4602      	mov	r2, r0
+ 8001418:	693b      	ldr	r3, [r7, #16]
+ 800141a:	1ad3      	subs	r3, r2, r3
+ 800141c:	2b64      	cmp	r3, #100	@ 0x64
+ 800141e:	d901      	bls.n	8001424 <HAL_RCC_OscConfig+0x444>
         {
           return HAL_TIMEOUT;
- 8001334:	2303      	movs	r3, #3
- 8001336:	e104      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 8001420:	2303      	movs	r3, #3
+ 8001422:	e104      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8001338:	4b29      	ldr	r3, [pc, #164]	@ (80013e0 <HAL_RCC_OscConfig+0x4ec>)
- 800133a:	681b      	ldr	r3, [r3, #0]
- 800133c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
- 8001340:	2b00      	cmp	r3, #0
- 8001342:	d0f0      	beq.n	8001326 <HAL_RCC_OscConfig+0x432>
+ 8001424:	4b29      	ldr	r3, [pc, #164]	@ (80014cc <HAL_RCC_OscConfig+0x4ec>)
+ 8001426:	681b      	ldr	r3, [r3, #0]
+ 8001428:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 800142c:	2b00      	cmp	r3, #0
+ 800142e:	d0f0      	beq.n	8001412 <HAL_RCC_OscConfig+0x432>
         }
       }
     }
 
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8001344:	687b      	ldr	r3, [r7, #4]
- 8001346:	689b      	ldr	r3, [r3, #8]
- 8001348:	2b01      	cmp	r3, #1
- 800134a:	d106      	bne.n	800135a <HAL_RCC_OscConfig+0x466>
- 800134c:	4b1e      	ldr	r3, [pc, #120]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 800134e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001350:	4a1d      	ldr	r2, [pc, #116]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001352:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
- 8001356:	6353      	str	r3, [r2, #52]	@ 0x34
- 8001358:	e02d      	b.n	80013b6 <HAL_RCC_OscConfig+0x4c2>
- 800135a:	687b      	ldr	r3, [r7, #4]
- 800135c:	689b      	ldr	r3, [r3, #8]
- 800135e:	2b00      	cmp	r3, #0
- 8001360:	d10c      	bne.n	800137c <HAL_RCC_OscConfig+0x488>
- 8001362:	4b19      	ldr	r3, [pc, #100]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001364:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001366:	4a18      	ldr	r2, [pc, #96]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001368:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
- 800136c:	6353      	str	r3, [r2, #52]	@ 0x34
- 800136e:	4b16      	ldr	r3, [pc, #88]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001370:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001372:	4a15      	ldr	r2, [pc, #84]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001374:	f423 6380 	bic.w	r3, r3, #1024	@ 0x400
- 8001378:	6353      	str	r3, [r2, #52]	@ 0x34
- 800137a:	e01c      	b.n	80013b6 <HAL_RCC_OscConfig+0x4c2>
- 800137c:	687b      	ldr	r3, [r7, #4]
- 800137e:	689b      	ldr	r3, [r3, #8]
- 8001380:	2b05      	cmp	r3, #5
- 8001382:	d10c      	bne.n	800139e <HAL_RCC_OscConfig+0x4aa>
- 8001384:	4b10      	ldr	r3, [pc, #64]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001386:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001388:	4a0f      	ldr	r2, [pc, #60]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 800138a:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
- 800138e:	6353      	str	r3, [r2, #52]	@ 0x34
- 8001390:	4b0d      	ldr	r3, [pc, #52]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001392:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001394:	4a0c      	ldr	r2, [pc, #48]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 8001396:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
- 800139a:	6353      	str	r3, [r2, #52]	@ 0x34
- 800139c:	e00b      	b.n	80013b6 <HAL_RCC_OscConfig+0x4c2>
- 800139e:	4b0a      	ldr	r3, [pc, #40]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80013a0:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 80013a2:	4a09      	ldr	r2, [pc, #36]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80013a4:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
- 80013a8:	6353      	str	r3, [r2, #52]	@ 0x34
- 80013aa:	4b07      	ldr	r3, [pc, #28]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80013ac:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 80013ae:	4a06      	ldr	r2, [pc, #24]	@ (80013c8 <HAL_RCC_OscConfig+0x4d4>)
- 80013b0:	f423 6380 	bic.w	r3, r3, #1024	@ 0x400
- 80013b4:	6353      	str	r3, [r2, #52]	@ 0x34
+ 8001430:	687b      	ldr	r3, [r7, #4]
+ 8001432:	689b      	ldr	r3, [r3, #8]
+ 8001434:	2b01      	cmp	r3, #1
+ 8001436:	d106      	bne.n	8001446 <HAL_RCC_OscConfig+0x466>
+ 8001438:	4b1e      	ldr	r3, [pc, #120]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800143a:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 800143c:	4a1d      	ldr	r2, [pc, #116]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800143e:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 8001442:	6353      	str	r3, [r2, #52]	@ 0x34
+ 8001444:	e02d      	b.n	80014a2 <HAL_RCC_OscConfig+0x4c2>
+ 8001446:	687b      	ldr	r3, [r7, #4]
+ 8001448:	689b      	ldr	r3, [r3, #8]
+ 800144a:	2b00      	cmp	r3, #0
+ 800144c:	d10c      	bne.n	8001468 <HAL_RCC_OscConfig+0x488>
+ 800144e:	4b19      	ldr	r3, [pc, #100]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001450:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8001452:	4a18      	ldr	r2, [pc, #96]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001454:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
+ 8001458:	6353      	str	r3, [r2, #52]	@ 0x34
+ 800145a:	4b16      	ldr	r3, [pc, #88]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800145c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 800145e:	4a15      	ldr	r2, [pc, #84]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001460:	f423 6380 	bic.w	r3, r3, #1024	@ 0x400
+ 8001464:	6353      	str	r3, [r2, #52]	@ 0x34
+ 8001466:	e01c      	b.n	80014a2 <HAL_RCC_OscConfig+0x4c2>
+ 8001468:	687b      	ldr	r3, [r7, #4]
+ 800146a:	689b      	ldr	r3, [r3, #8]
+ 800146c:	2b05      	cmp	r3, #5
+ 800146e:	d10c      	bne.n	800148a <HAL_RCC_OscConfig+0x4aa>
+ 8001470:	4b10      	ldr	r3, [pc, #64]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001472:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8001474:	4a0f      	ldr	r2, [pc, #60]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001476:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
+ 800147a:	6353      	str	r3, [r2, #52]	@ 0x34
+ 800147c:	4b0d      	ldr	r3, [pc, #52]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800147e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8001480:	4a0c      	ldr	r2, [pc, #48]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001482:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 8001486:	6353      	str	r3, [r2, #52]	@ 0x34
+ 8001488:	e00b      	b.n	80014a2 <HAL_RCC_OscConfig+0x4c2>
+ 800148a:	4b0a      	ldr	r3, [pc, #40]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800148c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 800148e:	4a09      	ldr	r2, [pc, #36]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001490:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
+ 8001494:	6353      	str	r3, [r2, #52]	@ 0x34
+ 8001496:	4b07      	ldr	r3, [pc, #28]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 8001498:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 800149a:	4a06      	ldr	r2, [pc, #24]	@ (80014b4 <HAL_RCC_OscConfig+0x4d4>)
+ 800149c:	f423 6380 	bic.w	r3, r3, #1024	@ 0x400
+ 80014a0:	6353      	str	r3, [r2, #52]	@ 0x34
     /* Check the LSE State */
     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- 80013b6:	687b      	ldr	r3, [r7, #4]
- 80013b8:	689b      	ldr	r3, [r3, #8]
- 80013ba:	2b00      	cmp	r3, #0
- 80013bc:	d024      	beq.n	8001408 <HAL_RCC_OscConfig+0x514>
+ 80014a2:	687b      	ldr	r3, [r7, #4]
+ 80014a4:	689b      	ldr	r3, [r3, #8]
+ 80014a6:	2b00      	cmp	r3, #0
+ 80014a8:	d024      	beq.n	80014f4 <HAL_RCC_OscConfig+0x514>
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 80013be:	f7ff fac1 	bl	8000944 <HAL_GetTick>
- 80013c2:	6138      	str	r0, [r7, #16]
+ 80014aa:	f7ff fac1 	bl	8000a30 <HAL_GetTick>
+ 80014ae:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSE is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 80013c4:	e019      	b.n	80013fa <HAL_RCC_OscConfig+0x506>
- 80013c6:	bf00      	nop
- 80013c8:	40023800 	.word	0x40023800
- 80013cc:	08001dc4 	.word	0x08001dc4
- 80013d0:	20000000 	.word	0x20000000
- 80013d4:	20000004 	.word	0x20000004
- 80013d8:	42470020 	.word	0x42470020
- 80013dc:	42470680 	.word	0x42470680
- 80013e0:	40007000 	.word	0x40007000
+ 80014b0:	e019      	b.n	80014e6 <HAL_RCC_OscConfig+0x506>
+ 80014b2:	bf00      	nop
+ 80014b4:	40023800 	.word	0x40023800
+ 80014b8:	080022c8 	.word	0x080022c8
+ 80014bc:	20000000 	.word	0x20000000
+ 80014c0:	20000004 	.word	0x20000004
+ 80014c4:	42470020 	.word	0x42470020
+ 80014c8:	42470680 	.word	0x42470680
+ 80014cc:	40007000 	.word	0x40007000
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80013e4:	f7ff faae 	bl	8000944 <HAL_GetTick>
- 80013e8:	4602      	mov	r2, r0
- 80013ea:	693b      	ldr	r3, [r7, #16]
- 80013ec:	1ad3      	subs	r3, r2, r3
- 80013ee:	f241 3288 	movw	r2, #5000	@ 0x1388
- 80013f2:	4293      	cmp	r3, r2
- 80013f4:	d901      	bls.n	80013fa <HAL_RCC_OscConfig+0x506>
+ 80014d0:	f7ff faae 	bl	8000a30 <HAL_GetTick>
+ 80014d4:	4602      	mov	r2, r0
+ 80014d6:	693b      	ldr	r3, [r7, #16]
+ 80014d8:	1ad3      	subs	r3, r2, r3
+ 80014da:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 80014de:	4293      	cmp	r3, r2
+ 80014e0:	d901      	bls.n	80014e6 <HAL_RCC_OscConfig+0x506>
         {
           return HAL_TIMEOUT;
- 80013f6:	2303      	movs	r3, #3
- 80013f8:	e0a3      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80014e2:	2303      	movs	r3, #3
+ 80014e4:	e0a3      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 80013fa:	4b54      	ldr	r3, [pc, #336]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 80013fc:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 80013fe:	f403 7300 	and.w	r3, r3, #512	@ 0x200
- 8001402:	2b00      	cmp	r3, #0
- 8001404:	d0ee      	beq.n	80013e4 <HAL_RCC_OscConfig+0x4f0>
- 8001406:	e014      	b.n	8001432 <HAL_RCC_OscConfig+0x53e>
+ 80014e6:	4b54      	ldr	r3, [pc, #336]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 80014e8:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80014ea:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 80014ee:	2b00      	cmp	r3, #0
+ 80014f0:	d0ee      	beq.n	80014d0 <HAL_RCC_OscConfig+0x4f0>
+ 80014f2:	e014      	b.n	800151e <HAL_RCC_OscConfig+0x53e>
       }
     }
     else
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
- 8001408:	f7ff fa9c 	bl	8000944 <HAL_GetTick>
- 800140c:	6138      	str	r0, [r7, #16]
+ 80014f4:	f7ff fa9c 	bl	8000a30 <HAL_GetTick>
+ 80014f8:	6138      	str	r0, [r7, #16]
 
       /* Wait till LSE is disabled */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
- 800140e:	e00a      	b.n	8001426 <HAL_RCC_OscConfig+0x532>
+ 80014fa:	e00a      	b.n	8001512 <HAL_RCC_OscConfig+0x532>
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001410:	f7ff fa98 	bl	8000944 <HAL_GetTick>
- 8001414:	4602      	mov	r2, r0
- 8001416:	693b      	ldr	r3, [r7, #16]
- 8001418:	1ad3      	subs	r3, r2, r3
- 800141a:	f241 3288 	movw	r2, #5000	@ 0x1388
- 800141e:	4293      	cmp	r3, r2
- 8001420:	d901      	bls.n	8001426 <HAL_RCC_OscConfig+0x532>
+ 80014fc:	f7ff fa98 	bl	8000a30 <HAL_GetTick>
+ 8001500:	4602      	mov	r2, r0
+ 8001502:	693b      	ldr	r3, [r7, #16]
+ 8001504:	1ad3      	subs	r3, r2, r3
+ 8001506:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 800150a:	4293      	cmp	r3, r2
+ 800150c:	d901      	bls.n	8001512 <HAL_RCC_OscConfig+0x532>
         {
           return HAL_TIMEOUT;
- 8001422:	2303      	movs	r3, #3
- 8001424:	e08d      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 800150e:	2303      	movs	r3, #3
+ 8001510:	e08d      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
- 8001426:	4b49      	ldr	r3, [pc, #292]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 8001428:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 800142a:	f403 7300 	and.w	r3, r3, #512	@ 0x200
- 800142e:	2b00      	cmp	r3, #0
- 8001430:	d1ee      	bne.n	8001410 <HAL_RCC_OscConfig+0x51c>
+ 8001512:	4b49      	ldr	r3, [pc, #292]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 8001514:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8001516:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 800151a:	2b00      	cmp	r3, #0
+ 800151c:	d1ee      	bne.n	80014fc <HAL_RCC_OscConfig+0x51c>
         }
       }
     }
 
     /* Require to disable power clock if necessary */
     if(pwrclkchanged == SET)
- 8001432:	7ffb      	ldrb	r3, [r7, #31]
- 8001434:	2b01      	cmp	r3, #1
- 8001436:	d105      	bne.n	8001444 <HAL_RCC_OscConfig+0x550>
+ 800151e:	7ffb      	ldrb	r3, [r7, #31]
+ 8001520:	2b01      	cmp	r3, #1
+ 8001522:	d105      	bne.n	8001530 <HAL_RCC_OscConfig+0x550>
     {
       __HAL_RCC_PWR_CLK_DISABLE();
- 8001438:	4b44      	ldr	r3, [pc, #272]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 800143a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 800143c:	4a43      	ldr	r2, [pc, #268]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 800143e:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
- 8001442:	6253      	str	r3, [r2, #36]	@ 0x24
+ 8001524:	4b44      	ldr	r3, [pc, #272]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 8001526:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8001528:	4a43      	ldr	r2, [pc, #268]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 800152a:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
+ 800152e:	6253      	str	r3, [r2, #36]	@ 0x24
   }
 
   /*-------------------------------- PLL Configuration -----------------------*/
   /* Check the parameters */
   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8001444:	687b      	ldr	r3, [r7, #4]
- 8001446:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8001448:	2b00      	cmp	r3, #0
- 800144a:	d079      	beq.n	8001540 <HAL_RCC_OscConfig+0x64c>
+ 8001530:	687b      	ldr	r3, [r7, #4]
+ 8001532:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8001534:	2b00      	cmp	r3, #0
+ 8001536:	d079      	beq.n	800162c <HAL_RCC_OscConfig+0x64c>
   {
     /* Check if the PLL is used as system clock or not */
     if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 800144c:	69bb      	ldr	r3, [r7, #24]
- 800144e:	2b0c      	cmp	r3, #12
- 8001450:	d056      	beq.n	8001500 <HAL_RCC_OscConfig+0x60c>
+ 8001538:	69bb      	ldr	r3, [r7, #24]
+ 800153a:	2b0c      	cmp	r3, #12
+ 800153c:	d056      	beq.n	80015ec <HAL_RCC_OscConfig+0x60c>
     {
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8001452:	687b      	ldr	r3, [r7, #4]
- 8001454:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8001456:	2b02      	cmp	r3, #2
- 8001458:	d13b      	bne.n	80014d2 <HAL_RCC_OscConfig+0x5de>
+ 800153e:	687b      	ldr	r3, [r7, #4]
+ 8001540:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8001542:	2b02      	cmp	r3, #2
+ 8001544:	d13b      	bne.n	80015be <HAL_RCC_OscConfig+0x5de>
         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
         assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
 
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 800145a:	4b3d      	ldr	r3, [pc, #244]	@ (8001550 <HAL_RCC_OscConfig+0x65c>)
- 800145c:	2200      	movs	r2, #0
- 800145e:	601a      	str	r2, [r3, #0]
+ 8001546:	4b3d      	ldr	r3, [pc, #244]	@ (800163c <HAL_RCC_OscConfig+0x65c>)
+ 8001548:	2200      	movs	r2, #0
+ 800154a:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 8001460:	f7ff fa70 	bl	8000944 <HAL_GetTick>
- 8001464:	6138      	str	r0, [r7, #16]
+ 800154c:	f7ff fa70 	bl	8000a30 <HAL_GetTick>
+ 8001550:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 8001466:	e008      	b.n	800147a <HAL_RCC_OscConfig+0x586>
+ 8001552:	e008      	b.n	8001566 <HAL_RCC_OscConfig+0x586>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001468:	f7ff fa6c 	bl	8000944 <HAL_GetTick>
- 800146c:	4602      	mov	r2, r0
- 800146e:	693b      	ldr	r3, [r7, #16]
- 8001470:	1ad3      	subs	r3, r2, r3
- 8001472:	2b02      	cmp	r3, #2
- 8001474:	d901      	bls.n	800147a <HAL_RCC_OscConfig+0x586>
+ 8001554:	f7ff fa6c 	bl	8000a30 <HAL_GetTick>
+ 8001558:	4602      	mov	r2, r0
+ 800155a:	693b      	ldr	r3, [r7, #16]
+ 800155c:	1ad3      	subs	r3, r2, r3
+ 800155e:	2b02      	cmp	r3, #2
+ 8001560:	d901      	bls.n	8001566 <HAL_RCC_OscConfig+0x586>
           {
             return HAL_TIMEOUT;
- 8001476:	2303      	movs	r3, #3
- 8001478:	e063      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 8001562:	2303      	movs	r3, #3
+ 8001564:	e063      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 800147a:	4b34      	ldr	r3, [pc, #208]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 800147c:	681b      	ldr	r3, [r3, #0]
- 800147e:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 8001482:	2b00      	cmp	r3, #0
- 8001484:	d1f0      	bne.n	8001468 <HAL_RCC_OscConfig+0x574>
+ 8001566:	4b34      	ldr	r3, [pc, #208]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 8001568:	681b      	ldr	r3, [r3, #0]
+ 800156a:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 800156e:	2b00      	cmp	r3, #0
+ 8001570:	d1f0      	bne.n	8001554 <HAL_RCC_OscConfig+0x574>
           }
         }
 
         /* Configure the main PLL clock source, multiplication and division factors. */
         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8001486:	4b31      	ldr	r3, [pc, #196]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 8001488:	689b      	ldr	r3, [r3, #8]
- 800148a:	f423 027d 	bic.w	r2, r3, #16580608	@ 0xfd0000
- 800148e:	687b      	ldr	r3, [r7, #4]
- 8001490:	6a99      	ldr	r1, [r3, #40]	@ 0x28
- 8001492:	687b      	ldr	r3, [r7, #4]
- 8001494:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8001496:	4319      	orrs	r1, r3
- 8001498:	687b      	ldr	r3, [r7, #4]
- 800149a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 800149c:	430b      	orrs	r3, r1
- 800149e:	492b      	ldr	r1, [pc, #172]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 80014a0:	4313      	orrs	r3, r2
- 80014a2:	608b      	str	r3, [r1, #8]
+ 8001572:	4b31      	ldr	r3, [pc, #196]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 8001574:	689b      	ldr	r3, [r3, #8]
+ 8001576:	f423 027d 	bic.w	r2, r3, #16580608	@ 0xfd0000
+ 800157a:	687b      	ldr	r3, [r7, #4]
+ 800157c:	6a99      	ldr	r1, [r3, #40]	@ 0x28
+ 800157e:	687b      	ldr	r3, [r7, #4]
+ 8001580:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8001582:	4319      	orrs	r1, r3
+ 8001584:	687b      	ldr	r3, [r7, #4]
+ 8001586:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8001588:	430b      	orrs	r3, r1
+ 800158a:	492b      	ldr	r1, [pc, #172]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 800158c:	4313      	orrs	r3, r2
+ 800158e:	608b      	str	r3, [r1, #8]
                              RCC_OscInitStruct->PLL.PLLMUL,
                              RCC_OscInitStruct->PLL.PLLDIV);
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
- 80014a4:	4b2a      	ldr	r3, [pc, #168]	@ (8001550 <HAL_RCC_OscConfig+0x65c>)
- 80014a6:	2201      	movs	r2, #1
- 80014a8:	601a      	str	r2, [r3, #0]
+ 8001590:	4b2a      	ldr	r3, [pc, #168]	@ (800163c <HAL_RCC_OscConfig+0x65c>)
+ 8001592:	2201      	movs	r2, #1
+ 8001594:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 80014aa:	f7ff fa4b 	bl	8000944 <HAL_GetTick>
- 80014ae:	6138      	str	r0, [r7, #16]
+ 8001596:	f7ff fa4b 	bl	8000a30 <HAL_GetTick>
+ 800159a:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 80014b0:	e008      	b.n	80014c4 <HAL_RCC_OscConfig+0x5d0>
+ 800159c:	e008      	b.n	80015b0 <HAL_RCC_OscConfig+0x5d0>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80014b2:	f7ff fa47 	bl	8000944 <HAL_GetTick>
- 80014b6:	4602      	mov	r2, r0
- 80014b8:	693b      	ldr	r3, [r7, #16]
- 80014ba:	1ad3      	subs	r3, r2, r3
- 80014bc:	2b02      	cmp	r3, #2
- 80014be:	d901      	bls.n	80014c4 <HAL_RCC_OscConfig+0x5d0>
+ 800159e:	f7ff fa47 	bl	8000a30 <HAL_GetTick>
+ 80015a2:	4602      	mov	r2, r0
+ 80015a4:	693b      	ldr	r3, [r7, #16]
+ 80015a6:	1ad3      	subs	r3, r2, r3
+ 80015a8:	2b02      	cmp	r3, #2
+ 80015aa:	d901      	bls.n	80015b0 <HAL_RCC_OscConfig+0x5d0>
           {
             return HAL_TIMEOUT;
- 80014c0:	2303      	movs	r3, #3
- 80014c2:	e03e      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80015ac:	2303      	movs	r3, #3
+ 80015ae:	e03e      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 80014c4:	4b21      	ldr	r3, [pc, #132]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 80014c6:	681b      	ldr	r3, [r3, #0]
- 80014c8:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 80014cc:	2b00      	cmp	r3, #0
- 80014ce:	d0f0      	beq.n	80014b2 <HAL_RCC_OscConfig+0x5be>
- 80014d0:	e036      	b.n	8001540 <HAL_RCC_OscConfig+0x64c>
+ 80015b0:	4b21      	ldr	r3, [pc, #132]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 80015b2:	681b      	ldr	r3, [r3, #0]
+ 80015b4:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 80015b8:	2b00      	cmp	r3, #0
+ 80015ba:	d0f0      	beq.n	800159e <HAL_RCC_OscConfig+0x5be>
+ 80015bc:	e036      	b.n	800162c <HAL_RCC_OscConfig+0x64c>
         }
       }
       else
       {
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 80014d2:	4b1f      	ldr	r3, [pc, #124]	@ (8001550 <HAL_RCC_OscConfig+0x65c>)
- 80014d4:	2200      	movs	r2, #0
- 80014d6:	601a      	str	r2, [r3, #0]
+ 80015be:	4b1f      	ldr	r3, [pc, #124]	@ (800163c <HAL_RCC_OscConfig+0x65c>)
+ 80015c0:	2200      	movs	r2, #0
+ 80015c2:	601a      	str	r2, [r3, #0]
 
         /* Get Start Tick */
         tickstart = HAL_GetTick();
- 80014d8:	f7ff fa34 	bl	8000944 <HAL_GetTick>
- 80014dc:	6138      	str	r0, [r7, #16]
+ 80015c4:	f7ff fa34 	bl	8000a30 <HAL_GetTick>
+ 80015c8:	6138      	str	r0, [r7, #16]
 
         /* Wait till PLL is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80014de:	e008      	b.n	80014f2 <HAL_RCC_OscConfig+0x5fe>
+ 80015ca:	e008      	b.n	80015de <HAL_RCC_OscConfig+0x5fe>
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80014e0:	f7ff fa30 	bl	8000944 <HAL_GetTick>
- 80014e4:	4602      	mov	r2, r0
- 80014e6:	693b      	ldr	r3, [r7, #16]
- 80014e8:	1ad3      	subs	r3, r2, r3
- 80014ea:	2b02      	cmp	r3, #2
- 80014ec:	d901      	bls.n	80014f2 <HAL_RCC_OscConfig+0x5fe>
+ 80015cc:	f7ff fa30 	bl	8000a30 <HAL_GetTick>
+ 80015d0:	4602      	mov	r2, r0
+ 80015d2:	693b      	ldr	r3, [r7, #16]
+ 80015d4:	1ad3      	subs	r3, r2, r3
+ 80015d6:	2b02      	cmp	r3, #2
+ 80015d8:	d901      	bls.n	80015de <HAL_RCC_OscConfig+0x5fe>
           {
             return HAL_TIMEOUT;
- 80014ee:	2303      	movs	r3, #3
- 80014f0:	e027      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80015da:	2303      	movs	r3, #3
+ 80015dc:	e027      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80014f2:	4b16      	ldr	r3, [pc, #88]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 80014f4:	681b      	ldr	r3, [r3, #0]
- 80014f6:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 80014fa:	2b00      	cmp	r3, #0
- 80014fc:	d1f0      	bne.n	80014e0 <HAL_RCC_OscConfig+0x5ec>
- 80014fe:	e01f      	b.n	8001540 <HAL_RCC_OscConfig+0x64c>
+ 80015de:	4b16      	ldr	r3, [pc, #88]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 80015e0:	681b      	ldr	r3, [r3, #0]
+ 80015e2:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 80015e6:	2b00      	cmp	r3, #0
+ 80015e8:	d1f0      	bne.n	80015cc <HAL_RCC_OscConfig+0x5ec>
+ 80015ea:	e01f      	b.n	800162c <HAL_RCC_OscConfig+0x64c>
       }
     }
     else
     {
       /* Check if there is a request to disable the PLL used as System clock source */
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- 8001500:	687b      	ldr	r3, [r7, #4]
- 8001502:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8001504:	2b01      	cmp	r3, #1
- 8001506:	d101      	bne.n	800150c <HAL_RCC_OscConfig+0x618>
+ 80015ec:	687b      	ldr	r3, [r7, #4]
+ 80015ee:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80015f0:	2b01      	cmp	r3, #1
+ 80015f2:	d101      	bne.n	80015f8 <HAL_RCC_OscConfig+0x618>
       {
         return HAL_ERROR;
- 8001508:	2301      	movs	r3, #1
- 800150a:	e01a      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 80015f4:	2301      	movs	r3, #1
+ 80015f6:	e01a      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
       }
       else
       {
         /* Do not return HAL_ERROR if request repeats the current configuration */
         pll_config = RCC->CFGR;
- 800150c:	4b0f      	ldr	r3, [pc, #60]	@ (800154c <HAL_RCC_OscConfig+0x658>)
- 800150e:	689b      	ldr	r3, [r3, #8]
- 8001510:	617b      	str	r3, [r7, #20]
+ 80015f8:	4b0f      	ldr	r3, [pc, #60]	@ (8001638 <HAL_RCC_OscConfig+0x658>)
+ 80015fa:	689b      	ldr	r3, [r3, #8]
+ 80015fc:	617b      	str	r3, [r7, #20]
         if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 8001512:	697b      	ldr	r3, [r7, #20]
- 8001514:	f403 3280 	and.w	r2, r3, #65536	@ 0x10000
- 8001518:	687b      	ldr	r3, [r7, #4]
- 800151a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 800151c:	429a      	cmp	r2, r3
- 800151e:	d10d      	bne.n	800153c <HAL_RCC_OscConfig+0x648>
+ 80015fe:	697b      	ldr	r3, [r7, #20]
+ 8001600:	f403 3280 	and.w	r2, r3, #65536	@ 0x10000
+ 8001604:	687b      	ldr	r3, [r7, #4]
+ 8001606:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8001608:	429a      	cmp	r2, r3
+ 800160a:	d10d      	bne.n	8001628 <HAL_RCC_OscConfig+0x648>
            (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
- 8001520:	697b      	ldr	r3, [r7, #20]
- 8001522:	f403 1270 	and.w	r2, r3, #3932160	@ 0x3c0000
- 8001526:	687b      	ldr	r3, [r7, #4]
- 8001528:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 800160c:	697b      	ldr	r3, [r7, #20]
+ 800160e:	f403 1270 	and.w	r2, r3, #3932160	@ 0x3c0000
+ 8001612:	687b      	ldr	r3, [r7, #4]
+ 8001614:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
         if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 800152a:	429a      	cmp	r2, r3
- 800152c:	d106      	bne.n	800153c <HAL_RCC_OscConfig+0x648>
+ 8001616:	429a      	cmp	r2, r3
+ 8001618:	d106      	bne.n	8001628 <HAL_RCC_OscConfig+0x648>
            (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
- 800152e:	697b      	ldr	r3, [r7, #20]
- 8001530:	f403 0240 	and.w	r2, r3, #12582912	@ 0xc00000
- 8001534:	687b      	ldr	r3, [r7, #4]
- 8001536:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 800161a:	697b      	ldr	r3, [r7, #20]
+ 800161c:	f403 0240 	and.w	r2, r3, #12582912	@ 0xc00000
+ 8001620:	687b      	ldr	r3, [r7, #4]
+ 8001622:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
            (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
- 8001538:	429a      	cmp	r2, r3
- 800153a:	d001      	beq.n	8001540 <HAL_RCC_OscConfig+0x64c>
+ 8001624:	429a      	cmp	r2, r3
+ 8001626:	d001      	beq.n	800162c <HAL_RCC_OscConfig+0x64c>
         {
           return HAL_ERROR;
- 800153c:	2301      	movs	r3, #1
- 800153e:	e000      	b.n	8001542 <HAL_RCC_OscConfig+0x64e>
+ 8001628:	2301      	movs	r3, #1
+ 800162a:	e000      	b.n	800162e <HAL_RCC_OscConfig+0x64e>
         }
       }
     }
   }
 
   return HAL_OK;
- 8001540:	2300      	movs	r3, #0
+ 800162c:	2300      	movs	r3, #0
 }
- 8001542:	4618      	mov	r0, r3
- 8001544:	3720      	adds	r7, #32
- 8001546:	46bd      	mov	sp, r7
- 8001548:	bd80      	pop	{r7, pc}
- 800154a:	bf00      	nop
- 800154c:	40023800 	.word	0x40023800
- 8001550:	42470060 	.word	0x42470060
+ 800162e:	4618      	mov	r0, r3
+ 8001630:	3720      	adds	r7, #32
+ 8001632:	46bd      	mov	sp, r7
+ 8001634:	bd80      	pop	{r7, pc}
+ 8001636:	bf00      	nop
+ 8001638:	40023800 	.word	0x40023800
+ 800163c:	42470060 	.word	0x42470060
 
-08001554 <HAL_RCC_ClockConfig>:
+08001640 <HAL_RCC_ClockConfig>:
   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
   *         (for more details refer to section above "Initialization/de-initialization functions")
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 {
- 8001554:	b580      	push	{r7, lr}
- 8001556:	b084      	sub	sp, #16
- 8001558:	af00      	add	r7, sp, #0
- 800155a:	6078      	str	r0, [r7, #4]
- 800155c:	6039      	str	r1, [r7, #0]
+ 8001640:	b580      	push	{r7, lr}
+ 8001642:	b084      	sub	sp, #16
+ 8001644:	af00      	add	r7, sp, #0
+ 8001646:	6078      	str	r0, [r7, #4]
+ 8001648:	6039      	str	r1, [r7, #0]
   uint32_t tickstart;
   HAL_StatusTypeDef status;
 
   /* Check the parameters */
   if(RCC_ClkInitStruct == NULL)
- 800155e:	687b      	ldr	r3, [r7, #4]
- 8001560:	2b00      	cmp	r3, #0
- 8001562:	d101      	bne.n	8001568 <HAL_RCC_ClockConfig+0x14>
+ 800164a:	687b      	ldr	r3, [r7, #4]
+ 800164c:	2b00      	cmp	r3, #0
+ 800164e:	d101      	bne.n	8001654 <HAL_RCC_ClockConfig+0x14>
   {
     return HAL_ERROR;
- 8001564:	2301      	movs	r3, #1
- 8001566:	e11a      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 8001650:	2301      	movs	r3, #1
+ 8001652:	e11a      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
   must be correctly programmed according to the frequency of the CPU clock
   (HCLK) and the supply voltage of the device. */
 
   /* Increasing the number of wait states because of higher CPU frequency */
   if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8001568:	4b8f      	ldr	r3, [pc, #572]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 800156a:	681b      	ldr	r3, [r3, #0]
- 800156c:	f003 0301 	and.w	r3, r3, #1
- 8001570:	683a      	ldr	r2, [r7, #0]
- 8001572:	429a      	cmp	r2, r3
- 8001574:	d919      	bls.n	80015aa <HAL_RCC_ClockConfig+0x56>
+ 8001654:	4b8f      	ldr	r3, [pc, #572]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 8001656:	681b      	ldr	r3, [r3, #0]
+ 8001658:	f003 0301 	and.w	r3, r3, #1
+ 800165c:	683a      	ldr	r2, [r7, #0]
+ 800165e:	429a      	cmp	r2, r3
+ 8001660:	d919      	bls.n	8001696 <HAL_RCC_ClockConfig+0x56>
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 8001576:	683b      	ldr	r3, [r7, #0]
- 8001578:	2b01      	cmp	r3, #1
- 800157a:	d105      	bne.n	8001588 <HAL_RCC_ClockConfig+0x34>
- 800157c:	4b8a      	ldr	r3, [pc, #552]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 800157e:	681b      	ldr	r3, [r3, #0]
- 8001580:	4a89      	ldr	r2, [pc, #548]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 8001582:	f043 0304 	orr.w	r3, r3, #4
- 8001586:	6013      	str	r3, [r2, #0]
- 8001588:	4b87      	ldr	r3, [pc, #540]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 800158a:	681b      	ldr	r3, [r3, #0]
- 800158c:	f023 0201 	bic.w	r2, r3, #1
- 8001590:	4985      	ldr	r1, [pc, #532]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 8001592:	683b      	ldr	r3, [r7, #0]
- 8001594:	4313      	orrs	r3, r2
- 8001596:	600b      	str	r3, [r1, #0]
+ 8001662:	683b      	ldr	r3, [r7, #0]
+ 8001664:	2b01      	cmp	r3, #1
+ 8001666:	d105      	bne.n	8001674 <HAL_RCC_ClockConfig+0x34>
+ 8001668:	4b8a      	ldr	r3, [pc, #552]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 800166a:	681b      	ldr	r3, [r3, #0]
+ 800166c:	4a89      	ldr	r2, [pc, #548]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 800166e:	f043 0304 	orr.w	r3, r3, #4
+ 8001672:	6013      	str	r3, [r2, #0]
+ 8001674:	4b87      	ldr	r3, [pc, #540]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 8001676:	681b      	ldr	r3, [r3, #0]
+ 8001678:	f023 0201 	bic.w	r2, r3, #1
+ 800167c:	4985      	ldr	r1, [pc, #532]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 800167e:	683b      	ldr	r3, [r7, #0]
+ 8001680:	4313      	orrs	r3, r2
+ 8001682:	600b      	str	r3, [r1, #0]
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8001598:	4b83      	ldr	r3, [pc, #524]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 800159a:	681b      	ldr	r3, [r3, #0]
- 800159c:	f003 0301 	and.w	r3, r3, #1
- 80015a0:	683a      	ldr	r2, [r7, #0]
- 80015a2:	429a      	cmp	r2, r3
- 80015a4:	d001      	beq.n	80015aa <HAL_RCC_ClockConfig+0x56>
+ 8001684:	4b83      	ldr	r3, [pc, #524]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 8001686:	681b      	ldr	r3, [r3, #0]
+ 8001688:	f003 0301 	and.w	r3, r3, #1
+ 800168c:	683a      	ldr	r2, [r7, #0]
+ 800168e:	429a      	cmp	r2, r3
+ 8001690:	d001      	beq.n	8001696 <HAL_RCC_ClockConfig+0x56>
     {
       return HAL_ERROR;
- 80015a6:	2301      	movs	r3, #1
- 80015a8:	e0f9      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 8001692:	2301      	movs	r3, #1
+ 8001694:	e0f9      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
     }
   }
 
   /*-------------------------- HCLK Configuration --------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 80015aa:	687b      	ldr	r3, [r7, #4]
- 80015ac:	681b      	ldr	r3, [r3, #0]
- 80015ae:	f003 0302 	and.w	r3, r3, #2
- 80015b2:	2b00      	cmp	r3, #0
- 80015b4:	d008      	beq.n	80015c8 <HAL_RCC_ClockConfig+0x74>
+ 8001696:	687b      	ldr	r3, [r7, #4]
+ 8001698:	681b      	ldr	r3, [r3, #0]
+ 800169a:	f003 0302 	and.w	r3, r3, #2
+ 800169e:	2b00      	cmp	r3, #0
+ 80016a0:	d008      	beq.n	80016b4 <HAL_RCC_ClockConfig+0x74>
   {
     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 80015b6:	4b7d      	ldr	r3, [pc, #500]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 80015b8:	689b      	ldr	r3, [r3, #8]
- 80015ba:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
- 80015be:	687b      	ldr	r3, [r7, #4]
- 80015c0:	689b      	ldr	r3, [r3, #8]
- 80015c2:	497a      	ldr	r1, [pc, #488]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 80015c4:	4313      	orrs	r3, r2
- 80015c6:	608b      	str	r3, [r1, #8]
+ 80016a2:	4b7d      	ldr	r3, [pc, #500]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 80016a4:	689b      	ldr	r3, [r3, #8]
+ 80016a6:	f023 02f0 	bic.w	r2, r3, #240	@ 0xf0
+ 80016aa:	687b      	ldr	r3, [r7, #4]
+ 80016ac:	689b      	ldr	r3, [r3, #8]
+ 80016ae:	497a      	ldr	r1, [pc, #488]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 80016b0:	4313      	orrs	r3, r2
+ 80016b2:	608b      	str	r3, [r1, #8]
   }
 
   /*------------------------- SYSCLK Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 80015c8:	687b      	ldr	r3, [r7, #4]
- 80015ca:	681b      	ldr	r3, [r3, #0]
- 80015cc:	f003 0301 	and.w	r3, r3, #1
- 80015d0:	2b00      	cmp	r3, #0
- 80015d2:	f000 808e 	beq.w	80016f2 <HAL_RCC_ClockConfig+0x19e>
+ 80016b4:	687b      	ldr	r3, [r7, #4]
+ 80016b6:	681b      	ldr	r3, [r3, #0]
+ 80016b8:	f003 0301 	and.w	r3, r3, #1
+ 80016bc:	2b00      	cmp	r3, #0
+ 80016be:	f000 808e 	beq.w	80017de <HAL_RCC_ClockConfig+0x19e>
   {
     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 
     /* HSE is selected as System Clock Source */
     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 80015d6:	687b      	ldr	r3, [r7, #4]
- 80015d8:	685b      	ldr	r3, [r3, #4]
- 80015da:	2b02      	cmp	r3, #2
- 80015dc:	d107      	bne.n	80015ee <HAL_RCC_ClockConfig+0x9a>
+ 80016c2:	687b      	ldr	r3, [r7, #4]
+ 80016c4:	685b      	ldr	r3, [r3, #4]
+ 80016c6:	2b02      	cmp	r3, #2
+ 80016c8:	d107      	bne.n	80016da <HAL_RCC_ClockConfig+0x9a>
     {
       /* Check the HSE ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 80015de:	4b73      	ldr	r3, [pc, #460]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 80015e0:	681b      	ldr	r3, [r3, #0]
- 80015e2:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
- 80015e6:	2b00      	cmp	r3, #0
- 80015e8:	d121      	bne.n	800162e <HAL_RCC_ClockConfig+0xda>
+ 80016ca:	4b73      	ldr	r3, [pc, #460]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 80016cc:	681b      	ldr	r3, [r3, #0]
+ 80016ce:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 80016d2:	2b00      	cmp	r3, #0
+ 80016d4:	d121      	bne.n	800171a <HAL_RCC_ClockConfig+0xda>
       {
         return HAL_ERROR;
- 80015ea:	2301      	movs	r3, #1
- 80015ec:	e0d7      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 80016d6:	2301      	movs	r3, #1
+ 80016d8:	e0d7      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
       }
     }
     /* PLL is selected as System Clock Source */
     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 80015ee:	687b      	ldr	r3, [r7, #4]
- 80015f0:	685b      	ldr	r3, [r3, #4]
- 80015f2:	2b03      	cmp	r3, #3
- 80015f4:	d107      	bne.n	8001606 <HAL_RCC_ClockConfig+0xb2>
+ 80016da:	687b      	ldr	r3, [r7, #4]
+ 80016dc:	685b      	ldr	r3, [r3, #4]
+ 80016de:	2b03      	cmp	r3, #3
+ 80016e0:	d107      	bne.n	80016f2 <HAL_RCC_ClockConfig+0xb2>
     {
       /* Check the PLL ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 80015f6:	4b6d      	ldr	r3, [pc, #436]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 80015f8:	681b      	ldr	r3, [r3, #0]
- 80015fa:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
- 80015fe:	2b00      	cmp	r3, #0
- 8001600:	d115      	bne.n	800162e <HAL_RCC_ClockConfig+0xda>
+ 80016e2:	4b6d      	ldr	r3, [pc, #436]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 80016e4:	681b      	ldr	r3, [r3, #0]
+ 80016e6:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 80016ea:	2b00      	cmp	r3, #0
+ 80016ec:	d115      	bne.n	800171a <HAL_RCC_ClockConfig+0xda>
       {
         return HAL_ERROR;
- 8001602:	2301      	movs	r3, #1
- 8001604:	e0cb      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 80016ee:	2301      	movs	r3, #1
+ 80016f0:	e0cb      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
       }
     }
     /* HSI is selected as System Clock Source */
     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
- 8001606:	687b      	ldr	r3, [r7, #4]
- 8001608:	685b      	ldr	r3, [r3, #4]
- 800160a:	2b01      	cmp	r3, #1
- 800160c:	d107      	bne.n	800161e <HAL_RCC_ClockConfig+0xca>
+ 80016f2:	687b      	ldr	r3, [r7, #4]
+ 80016f4:	685b      	ldr	r3, [r3, #4]
+ 80016f6:	2b01      	cmp	r3, #1
+ 80016f8:	d107      	bne.n	800170a <HAL_RCC_ClockConfig+0xca>
     {
       /* Check the HSI ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 800160e:	4b67      	ldr	r3, [pc, #412]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 8001610:	681b      	ldr	r3, [r3, #0]
- 8001612:	f003 0302 	and.w	r3, r3, #2
- 8001616:	2b00      	cmp	r3, #0
- 8001618:	d109      	bne.n	800162e <HAL_RCC_ClockConfig+0xda>
+ 80016fa:	4b67      	ldr	r3, [pc, #412]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 80016fc:	681b      	ldr	r3, [r3, #0]
+ 80016fe:	f003 0302 	and.w	r3, r3, #2
+ 8001702:	2b00      	cmp	r3, #0
+ 8001704:	d109      	bne.n	800171a <HAL_RCC_ClockConfig+0xda>
       {
         return HAL_ERROR;
- 800161a:	2301      	movs	r3, #1
- 800161c:	e0bf      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 8001706:	2301      	movs	r3, #1
+ 8001708:	e0bf      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
     }
     /* MSI is selected as System Clock Source */
     else
     {
       /* Check the MSI ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
- 800161e:	4b63      	ldr	r3, [pc, #396]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 8001620:	681b      	ldr	r3, [r3, #0]
- 8001622:	f403 7300 	and.w	r3, r3, #512	@ 0x200
- 8001626:	2b00      	cmp	r3, #0
- 8001628:	d101      	bne.n	800162e <HAL_RCC_ClockConfig+0xda>
+ 800170a:	4b63      	ldr	r3, [pc, #396]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 800170c:	681b      	ldr	r3, [r3, #0]
+ 800170e:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 8001712:	2b00      	cmp	r3, #0
+ 8001714:	d101      	bne.n	800171a <HAL_RCC_ClockConfig+0xda>
       {
         return HAL_ERROR;
- 800162a:	2301      	movs	r3, #1
- 800162c:	e0b7      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 8001716:	2301      	movs	r3, #1
+ 8001718:	e0b7      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
       }
     }
     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 800162e:	4b5f      	ldr	r3, [pc, #380]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 8001630:	689b      	ldr	r3, [r3, #8]
- 8001632:	f023 0203 	bic.w	r2, r3, #3
- 8001636:	687b      	ldr	r3, [r7, #4]
- 8001638:	685b      	ldr	r3, [r3, #4]
- 800163a:	495c      	ldr	r1, [pc, #368]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 800163c:	4313      	orrs	r3, r2
- 800163e:	608b      	str	r3, [r1, #8]
+ 800171a:	4b5f      	ldr	r3, [pc, #380]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 800171c:	689b      	ldr	r3, [r3, #8]
+ 800171e:	f023 0203 	bic.w	r2, r3, #3
+ 8001722:	687b      	ldr	r3, [r7, #4]
+ 8001724:	685b      	ldr	r3, [r3, #4]
+ 8001726:	495c      	ldr	r1, [pc, #368]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 8001728:	4313      	orrs	r3, r2
+ 800172a:	608b      	str	r3, [r1, #8]
 
     /* Get Start Tick */
     tickstart = HAL_GetTick();
- 8001640:	f7ff f980 	bl	8000944 <HAL_GetTick>
- 8001644:	60f8      	str	r0, [r7, #12]
+ 800172c:	f7ff f980 	bl	8000a30 <HAL_GetTick>
+ 8001730:	60f8      	str	r0, [r7, #12]
 
     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8001646:	687b      	ldr	r3, [r7, #4]
- 8001648:	685b      	ldr	r3, [r3, #4]
- 800164a:	2b02      	cmp	r3, #2
- 800164c:	d112      	bne.n	8001674 <HAL_RCC_ClockConfig+0x120>
+ 8001732:	687b      	ldr	r3, [r7, #4]
+ 8001734:	685b      	ldr	r3, [r3, #4]
+ 8001736:	2b02      	cmp	r3, #2
+ 8001738:	d112      	bne.n	8001760 <HAL_RCC_ClockConfig+0x120>
     {
       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- 800164e:	e00a      	b.n	8001666 <HAL_RCC_ClockConfig+0x112>
+ 800173a:	e00a      	b.n	8001752 <HAL_RCC_ClockConfig+0x112>
       {
         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8001650:	f7ff f978 	bl	8000944 <HAL_GetTick>
- 8001654:	4602      	mov	r2, r0
- 8001656:	68fb      	ldr	r3, [r7, #12]
- 8001658:	1ad3      	subs	r3, r2, r3
- 800165a:	f241 3288 	movw	r2, #5000	@ 0x1388
- 800165e:	4293      	cmp	r3, r2
- 8001660:	d901      	bls.n	8001666 <HAL_RCC_ClockConfig+0x112>
+ 800173c:	f7ff f978 	bl	8000a30 <HAL_GetTick>
+ 8001740:	4602      	mov	r2, r0
+ 8001742:	68fb      	ldr	r3, [r7, #12]
+ 8001744:	1ad3      	subs	r3, r2, r3
+ 8001746:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 800174a:	4293      	cmp	r3, r2
+ 800174c:	d901      	bls.n	8001752 <HAL_RCC_ClockConfig+0x112>
         {
           return HAL_TIMEOUT;
- 8001662:	2303      	movs	r3, #3
- 8001664:	e09b      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 800174e:	2303      	movs	r3, #3
+ 8001750:	e09b      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- 8001666:	4b51      	ldr	r3, [pc, #324]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 8001668:	689b      	ldr	r3, [r3, #8]
- 800166a:	f003 030c 	and.w	r3, r3, #12
- 800166e:	2b08      	cmp	r3, #8
- 8001670:	d1ee      	bne.n	8001650 <HAL_RCC_ClockConfig+0xfc>
- 8001672:	e03e      	b.n	80016f2 <HAL_RCC_ClockConfig+0x19e>
+ 8001752:	4b51      	ldr	r3, [pc, #324]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 8001754:	689b      	ldr	r3, [r3, #8]
+ 8001756:	f003 030c 	and.w	r3, r3, #12
+ 800175a:	2b08      	cmp	r3, #8
+ 800175c:	d1ee      	bne.n	800173c <HAL_RCC_ClockConfig+0xfc>
+ 800175e:	e03e      	b.n	80017de <HAL_RCC_ClockConfig+0x19e>
         }
       }
     }
     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 8001674:	687b      	ldr	r3, [r7, #4]
- 8001676:	685b      	ldr	r3, [r3, #4]
- 8001678:	2b03      	cmp	r3, #3
- 800167a:	d112      	bne.n	80016a2 <HAL_RCC_ClockConfig+0x14e>
+ 8001760:	687b      	ldr	r3, [r7, #4]
+ 8001762:	685b      	ldr	r3, [r3, #4]
+ 8001764:	2b03      	cmp	r3, #3
+ 8001766:	d112      	bne.n	800178e <HAL_RCC_ClockConfig+0x14e>
     {
       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 800167c:	e00a      	b.n	8001694 <HAL_RCC_ClockConfig+0x140>
+ 8001768:	e00a      	b.n	8001780 <HAL_RCC_ClockConfig+0x140>
       {
         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 800167e:	f7ff f961 	bl	8000944 <HAL_GetTick>
- 8001682:	4602      	mov	r2, r0
- 8001684:	68fb      	ldr	r3, [r7, #12]
- 8001686:	1ad3      	subs	r3, r2, r3
- 8001688:	f241 3288 	movw	r2, #5000	@ 0x1388
- 800168c:	4293      	cmp	r3, r2
- 800168e:	d901      	bls.n	8001694 <HAL_RCC_ClockConfig+0x140>
+ 800176a:	f7ff f961 	bl	8000a30 <HAL_GetTick>
+ 800176e:	4602      	mov	r2, r0
+ 8001770:	68fb      	ldr	r3, [r7, #12]
+ 8001772:	1ad3      	subs	r3, r2, r3
+ 8001774:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 8001778:	4293      	cmp	r3, r2
+ 800177a:	d901      	bls.n	8001780 <HAL_RCC_ClockConfig+0x140>
         {
           return HAL_TIMEOUT;
- 8001690:	2303      	movs	r3, #3
- 8001692:	e084      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 800177c:	2303      	movs	r3, #3
+ 800177e:	e084      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 8001694:	4b45      	ldr	r3, [pc, #276]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 8001696:	689b      	ldr	r3, [r3, #8]
- 8001698:	f003 030c 	and.w	r3, r3, #12
- 800169c:	2b0c      	cmp	r3, #12
- 800169e:	d1ee      	bne.n	800167e <HAL_RCC_ClockConfig+0x12a>
- 80016a0:	e027      	b.n	80016f2 <HAL_RCC_ClockConfig+0x19e>
+ 8001780:	4b45      	ldr	r3, [pc, #276]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 8001782:	689b      	ldr	r3, [r3, #8]
+ 8001784:	f003 030c 	and.w	r3, r3, #12
+ 8001788:	2b0c      	cmp	r3, #12
+ 800178a:	d1ee      	bne.n	800176a <HAL_RCC_ClockConfig+0x12a>
+ 800178c:	e027      	b.n	80017de <HAL_RCC_ClockConfig+0x19e>
         }
       }
     }
     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
- 80016a2:	687b      	ldr	r3, [r7, #4]
- 80016a4:	685b      	ldr	r3, [r3, #4]
- 80016a6:	2b01      	cmp	r3, #1
- 80016a8:	d11d      	bne.n	80016e6 <HAL_RCC_ClockConfig+0x192>
+ 800178e:	687b      	ldr	r3, [r7, #4]
+ 8001790:	685b      	ldr	r3, [r3, #4]
+ 8001792:	2b01      	cmp	r3, #1
+ 8001794:	d11d      	bne.n	80017d2 <HAL_RCC_ClockConfig+0x192>
     {
       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- 80016aa:	e00a      	b.n	80016c2 <HAL_RCC_ClockConfig+0x16e>
+ 8001796:	e00a      	b.n	80017ae <HAL_RCC_ClockConfig+0x16e>
       {
         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 80016ac:	f7ff f94a 	bl	8000944 <HAL_GetTick>
- 80016b0:	4602      	mov	r2, r0
- 80016b2:	68fb      	ldr	r3, [r7, #12]
- 80016b4:	1ad3      	subs	r3, r2, r3
- 80016b6:	f241 3288 	movw	r2, #5000	@ 0x1388
- 80016ba:	4293      	cmp	r3, r2
- 80016bc:	d901      	bls.n	80016c2 <HAL_RCC_ClockConfig+0x16e>
+ 8001798:	f7ff f94a 	bl	8000a30 <HAL_GetTick>
+ 800179c:	4602      	mov	r2, r0
+ 800179e:	68fb      	ldr	r3, [r7, #12]
+ 80017a0:	1ad3      	subs	r3, r2, r3
+ 80017a2:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 80017a6:	4293      	cmp	r3, r2
+ 80017a8:	d901      	bls.n	80017ae <HAL_RCC_ClockConfig+0x16e>
         {
           return HAL_TIMEOUT;
- 80016be:	2303      	movs	r3, #3
- 80016c0:	e06d      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 80017aa:	2303      	movs	r3, #3
+ 80017ac:	e06d      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- 80016c2:	4b3a      	ldr	r3, [pc, #232]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 80016c4:	689b      	ldr	r3, [r3, #8]
- 80016c6:	f003 030c 	and.w	r3, r3, #12
- 80016ca:	2b04      	cmp	r3, #4
- 80016cc:	d1ee      	bne.n	80016ac <HAL_RCC_ClockConfig+0x158>
- 80016ce:	e010      	b.n	80016f2 <HAL_RCC_ClockConfig+0x19e>
+ 80017ae:	4b3a      	ldr	r3, [pc, #232]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 80017b0:	689b      	ldr	r3, [r3, #8]
+ 80017b2:	f003 030c 	and.w	r3, r3, #12
+ 80017b6:	2b04      	cmp	r3, #4
+ 80017b8:	d1ee      	bne.n	8001798 <HAL_RCC_ClockConfig+0x158>
+ 80017ba:	e010      	b.n	80017de <HAL_RCC_ClockConfig+0x19e>
     }
     else
     {
       while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
       {
         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 80016d0:	f7ff f938 	bl	8000944 <HAL_GetTick>
- 80016d4:	4602      	mov	r2, r0
- 80016d6:	68fb      	ldr	r3, [r7, #12]
- 80016d8:	1ad3      	subs	r3, r2, r3
- 80016da:	f241 3288 	movw	r2, #5000	@ 0x1388
- 80016de:	4293      	cmp	r3, r2
- 80016e0:	d901      	bls.n	80016e6 <HAL_RCC_ClockConfig+0x192>
+ 80017bc:	f7ff f938 	bl	8000a30 <HAL_GetTick>
+ 80017c0:	4602      	mov	r2, r0
+ 80017c2:	68fb      	ldr	r3, [r7, #12]
+ 80017c4:	1ad3      	subs	r3, r2, r3
+ 80017c6:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 80017ca:	4293      	cmp	r3, r2
+ 80017cc:	d901      	bls.n	80017d2 <HAL_RCC_ClockConfig+0x192>
         {
           return HAL_TIMEOUT;
- 80016e2:	2303      	movs	r3, #3
- 80016e4:	e05b      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 80017ce:	2303      	movs	r3, #3
+ 80017d0:	e05b      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
       while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
- 80016e6:	4b31      	ldr	r3, [pc, #196]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 80016e8:	689b      	ldr	r3, [r3, #8]
- 80016ea:	f003 030c 	and.w	r3, r3, #12
- 80016ee:	2b00      	cmp	r3, #0
- 80016f0:	d1ee      	bne.n	80016d0 <HAL_RCC_ClockConfig+0x17c>
+ 80017d2:	4b31      	ldr	r3, [pc, #196]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 80017d4:	689b      	ldr	r3, [r3, #8]
+ 80017d6:	f003 030c 	and.w	r3, r3, #12
+ 80017da:	2b00      	cmp	r3, #0
+ 80017dc:	d1ee      	bne.n	80017bc <HAL_RCC_ClockConfig+0x17c>
         }
       }
     }
   }
   /* Decreasing the number of wait states because of lower CPU frequency */
   if(FLatency < __HAL_FLASH_GET_LATENCY())
- 80016f2:	4b2d      	ldr	r3, [pc, #180]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 80016f4:	681b      	ldr	r3, [r3, #0]
- 80016f6:	f003 0301 	and.w	r3, r3, #1
- 80016fa:	683a      	ldr	r2, [r7, #0]
- 80016fc:	429a      	cmp	r2, r3
- 80016fe:	d219      	bcs.n	8001734 <HAL_RCC_ClockConfig+0x1e0>
+ 80017de:	4b2d      	ldr	r3, [pc, #180]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 80017e0:	681b      	ldr	r3, [r3, #0]
+ 80017e2:	f003 0301 	and.w	r3, r3, #1
+ 80017e6:	683a      	ldr	r2, [r7, #0]
+ 80017e8:	429a      	cmp	r2, r3
+ 80017ea:	d219      	bcs.n	8001820 <HAL_RCC_ClockConfig+0x1e0>
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
- 8001700:	683b      	ldr	r3, [r7, #0]
- 8001702:	2b01      	cmp	r3, #1
- 8001704:	d105      	bne.n	8001712 <HAL_RCC_ClockConfig+0x1be>
- 8001706:	4b28      	ldr	r3, [pc, #160]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 8001708:	681b      	ldr	r3, [r3, #0]
- 800170a:	4a27      	ldr	r2, [pc, #156]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 800170c:	f043 0304 	orr.w	r3, r3, #4
- 8001710:	6013      	str	r3, [r2, #0]
- 8001712:	4b25      	ldr	r3, [pc, #148]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 8001714:	681b      	ldr	r3, [r3, #0]
- 8001716:	f023 0201 	bic.w	r2, r3, #1
- 800171a:	4923      	ldr	r1, [pc, #140]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 800171c:	683b      	ldr	r3, [r7, #0]
- 800171e:	4313      	orrs	r3, r2
- 8001720:	600b      	str	r3, [r1, #0]
+ 80017ec:	683b      	ldr	r3, [r7, #0]
+ 80017ee:	2b01      	cmp	r3, #1
+ 80017f0:	d105      	bne.n	80017fe <HAL_RCC_ClockConfig+0x1be>
+ 80017f2:	4b28      	ldr	r3, [pc, #160]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 80017f4:	681b      	ldr	r3, [r3, #0]
+ 80017f6:	4a27      	ldr	r2, [pc, #156]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 80017f8:	f043 0304 	orr.w	r3, r3, #4
+ 80017fc:	6013      	str	r3, [r2, #0]
+ 80017fe:	4b25      	ldr	r3, [pc, #148]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 8001800:	681b      	ldr	r3, [r3, #0]
+ 8001802:	f023 0201 	bic.w	r2, r3, #1
+ 8001806:	4923      	ldr	r1, [pc, #140]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 8001808:	683b      	ldr	r3, [r7, #0]
+ 800180a:	4313      	orrs	r3, r2
+ 800180c:	600b      	str	r3, [r1, #0]
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8001722:	4b21      	ldr	r3, [pc, #132]	@ (80017a8 <HAL_RCC_ClockConfig+0x254>)
- 8001724:	681b      	ldr	r3, [r3, #0]
- 8001726:	f003 0301 	and.w	r3, r3, #1
- 800172a:	683a      	ldr	r2, [r7, #0]
- 800172c:	429a      	cmp	r2, r3
- 800172e:	d001      	beq.n	8001734 <HAL_RCC_ClockConfig+0x1e0>
+ 800180e:	4b21      	ldr	r3, [pc, #132]	@ (8001894 <HAL_RCC_ClockConfig+0x254>)
+ 8001810:	681b      	ldr	r3, [r3, #0]
+ 8001812:	f003 0301 	and.w	r3, r3, #1
+ 8001816:	683a      	ldr	r2, [r7, #0]
+ 8001818:	429a      	cmp	r2, r3
+ 800181a:	d001      	beq.n	8001820 <HAL_RCC_ClockConfig+0x1e0>
     {
       return HAL_ERROR;
- 8001730:	2301      	movs	r3, #1
- 8001732:	e034      	b.n	800179e <HAL_RCC_ClockConfig+0x24a>
+ 800181c:	2301      	movs	r3, #1
+ 800181e:	e034      	b.n	800188a <HAL_RCC_ClockConfig+0x24a>
     }
   }
 
   /*-------------------------- PCLK1 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001734:	687b      	ldr	r3, [r7, #4]
- 8001736:	681b      	ldr	r3, [r3, #0]
- 8001738:	f003 0304 	and.w	r3, r3, #4
- 800173c:	2b00      	cmp	r3, #0
- 800173e:	d008      	beq.n	8001752 <HAL_RCC_ClockConfig+0x1fe>
+ 8001820:	687b      	ldr	r3, [r7, #4]
+ 8001822:	681b      	ldr	r3, [r3, #0]
+ 8001824:	f003 0304 	and.w	r3, r3, #4
+ 8001828:	2b00      	cmp	r3, #0
+ 800182a:	d008      	beq.n	800183e <HAL_RCC_ClockConfig+0x1fe>
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8001740:	4b1a      	ldr	r3, [pc, #104]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 8001742:	689b      	ldr	r3, [r3, #8]
- 8001744:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
- 8001748:	687b      	ldr	r3, [r7, #4]
- 800174a:	68db      	ldr	r3, [r3, #12]
- 800174c:	4917      	ldr	r1, [pc, #92]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 800174e:	4313      	orrs	r3, r2
- 8001750:	608b      	str	r3, [r1, #8]
+ 800182c:	4b1a      	ldr	r3, [pc, #104]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 800182e:	689b      	ldr	r3, [r3, #8]
+ 8001830:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
+ 8001834:	687b      	ldr	r3, [r7, #4]
+ 8001836:	68db      	ldr	r3, [r3, #12]
+ 8001838:	4917      	ldr	r1, [pc, #92]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 800183a:	4313      	orrs	r3, r2
+ 800183c:	608b      	str	r3, [r1, #8]
   }
 
   /*-------------------------- PCLK2 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8001752:	687b      	ldr	r3, [r7, #4]
- 8001754:	681b      	ldr	r3, [r3, #0]
- 8001756:	f003 0308 	and.w	r3, r3, #8
- 800175a:	2b00      	cmp	r3, #0
- 800175c:	d009      	beq.n	8001772 <HAL_RCC_ClockConfig+0x21e>
+ 800183e:	687b      	ldr	r3, [r7, #4]
+ 8001840:	681b      	ldr	r3, [r3, #0]
+ 8001842:	f003 0308 	and.w	r3, r3, #8
+ 8001846:	2b00      	cmp	r3, #0
+ 8001848:	d009      	beq.n	800185e <HAL_RCC_ClockConfig+0x21e>
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
- 800175e:	4b13      	ldr	r3, [pc, #76]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 8001760:	689b      	ldr	r3, [r3, #8]
- 8001762:	f423 5260 	bic.w	r2, r3, #14336	@ 0x3800
- 8001766:	687b      	ldr	r3, [r7, #4]
- 8001768:	691b      	ldr	r3, [r3, #16]
- 800176a:	00db      	lsls	r3, r3, #3
- 800176c:	490f      	ldr	r1, [pc, #60]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 800176e:	4313      	orrs	r3, r2
- 8001770:	608b      	str	r3, [r1, #8]
+ 800184a:	4b13      	ldr	r3, [pc, #76]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 800184c:	689b      	ldr	r3, [r3, #8]
+ 800184e:	f423 5260 	bic.w	r2, r3, #14336	@ 0x3800
+ 8001852:	687b      	ldr	r3, [r7, #4]
+ 8001854:	691b      	ldr	r3, [r3, #16]
+ 8001856:	00db      	lsls	r3, r3, #3
+ 8001858:	490f      	ldr	r1, [pc, #60]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 800185a:	4313      	orrs	r3, r2
+ 800185c:	608b      	str	r3, [r1, #8]
   }
 
   /* Update the SystemCoreClock global variable */
   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 8001772:	f000 f823 	bl	80017bc <HAL_RCC_GetSysClockFreq>
- 8001776:	4602      	mov	r2, r0
- 8001778:	4b0c      	ldr	r3, [pc, #48]	@ (80017ac <HAL_RCC_ClockConfig+0x258>)
- 800177a:	689b      	ldr	r3, [r3, #8]
- 800177c:	091b      	lsrs	r3, r3, #4
- 800177e:	f003 030f 	and.w	r3, r3, #15
- 8001782:	490b      	ldr	r1, [pc, #44]	@ (80017b0 <HAL_RCC_ClockConfig+0x25c>)
- 8001784:	5ccb      	ldrb	r3, [r1, r3]
- 8001786:	fa22 f303 	lsr.w	r3, r2, r3
- 800178a:	4a0a      	ldr	r2, [pc, #40]	@ (80017b4 <HAL_RCC_ClockConfig+0x260>)
- 800178c:	6013      	str	r3, [r2, #0]
+ 800185e:	f000 f823 	bl	80018a8 <HAL_RCC_GetSysClockFreq>
+ 8001862:	4602      	mov	r2, r0
+ 8001864:	4b0c      	ldr	r3, [pc, #48]	@ (8001898 <HAL_RCC_ClockConfig+0x258>)
+ 8001866:	689b      	ldr	r3, [r3, #8]
+ 8001868:	091b      	lsrs	r3, r3, #4
+ 800186a:	f003 030f 	and.w	r3, r3, #15
+ 800186e:	490b      	ldr	r1, [pc, #44]	@ (800189c <HAL_RCC_ClockConfig+0x25c>)
+ 8001870:	5ccb      	ldrb	r3, [r1, r3]
+ 8001872:	fa22 f303 	lsr.w	r3, r2, r3
+ 8001876:	4a0a      	ldr	r2, [pc, #40]	@ (80018a0 <HAL_RCC_ClockConfig+0x260>)
+ 8001878:	6013      	str	r3, [r2, #0]
 
   /* Configure the source of time base considering new system clocks settings*/
   status = HAL_InitTick(uwTickPrio);
- 800178e:	4b0a      	ldr	r3, [pc, #40]	@ (80017b8 <HAL_RCC_ClockConfig+0x264>)
- 8001790:	681b      	ldr	r3, [r3, #0]
- 8001792:	4618      	mov	r0, r3
- 8001794:	f7ff f88a 	bl	80008ac <HAL_InitTick>
- 8001798:	4603      	mov	r3, r0
- 800179a:	72fb      	strb	r3, [r7, #11]
+ 800187a:	4b0a      	ldr	r3, [pc, #40]	@ (80018a4 <HAL_RCC_ClockConfig+0x264>)
+ 800187c:	681b      	ldr	r3, [r3, #0]
+ 800187e:	4618      	mov	r0, r3
+ 8001880:	f7ff f88a 	bl	8000998 <HAL_InitTick>
+ 8001884:	4603      	mov	r3, r0
+ 8001886:	72fb      	strb	r3, [r7, #11]
 
   return status;
- 800179c:	7afb      	ldrb	r3, [r7, #11]
+ 8001888:	7afb      	ldrb	r3, [r7, #11]
 }
- 800179e:	4618      	mov	r0, r3
- 80017a0:	3710      	adds	r7, #16
- 80017a2:	46bd      	mov	sp, r7
- 80017a4:	bd80      	pop	{r7, pc}
- 80017a6:	bf00      	nop
- 80017a8:	40023c00 	.word	0x40023c00
- 80017ac:	40023800 	.word	0x40023800
- 80017b0:	08001dc4 	.word	0x08001dc4
- 80017b4:	20000000 	.word	0x20000000
- 80017b8:	20000004 	.word	0x20000004
+ 800188a:	4618      	mov	r0, r3
+ 800188c:	3710      	adds	r7, #16
+ 800188e:	46bd      	mov	sp, r7
+ 8001890:	bd80      	pop	{r7, pc}
+ 8001892:	bf00      	nop
+ 8001894:	40023c00 	.word	0x40023c00
+ 8001898:	40023800 	.word	0x40023800
+ 800189c:	080022c8 	.word	0x080022c8
+ 80018a0:	20000000 	.word	0x20000000
+ 80018a4:	20000004 	.word	0x20000004
 
-080017bc <HAL_RCC_GetSysClockFreq>:
+080018a8 <HAL_RCC_GetSysClockFreq>:
   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
   *
   * @retval SYSCLK frequency
   */
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
- 80017bc:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
- 80017c0:	b092      	sub	sp, #72	@ 0x48
- 80017c2:	af00      	add	r7, sp, #0
+ 80018a8:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 80018ac:	b092      	sub	sp, #72	@ 0x48
+ 80018ae:	af00      	add	r7, sp, #0
   uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
 
   tmpreg = RCC->CFGR;
- 80017c4:	4b79      	ldr	r3, [pc, #484]	@ (80019ac <HAL_RCC_GetSysClockFreq+0x1f0>)
- 80017c6:	689b      	ldr	r3, [r3, #8]
- 80017c8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 80018b0:	4b79      	ldr	r3, [pc, #484]	@ (8001a98 <HAL_RCC_GetSysClockFreq+0x1f0>)
+ 80018b2:	689b      	ldr	r3, [r3, #8]
+ 80018b4:	63fb      	str	r3, [r7, #60]	@ 0x3c
 
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (tmpreg & RCC_CFGR_SWS)
- 80017ca:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80017cc:	f003 030c 	and.w	r3, r3, #12
- 80017d0:	2b0c      	cmp	r3, #12
- 80017d2:	d00d      	beq.n	80017f0 <HAL_RCC_GetSysClockFreq+0x34>
- 80017d4:	2b0c      	cmp	r3, #12
- 80017d6:	f200 80d5 	bhi.w	8001984 <HAL_RCC_GetSysClockFreq+0x1c8>
- 80017da:	2b04      	cmp	r3, #4
- 80017dc:	d002      	beq.n	80017e4 <HAL_RCC_GetSysClockFreq+0x28>
- 80017de:	2b08      	cmp	r3, #8
- 80017e0:	d003      	beq.n	80017ea <HAL_RCC_GetSysClockFreq+0x2e>
- 80017e2:	e0cf      	b.n	8001984 <HAL_RCC_GetSysClockFreq+0x1c8>
+ 80018b6:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 80018b8:	f003 030c 	and.w	r3, r3, #12
+ 80018bc:	2b0c      	cmp	r3, #12
+ 80018be:	d00d      	beq.n	80018dc <HAL_RCC_GetSysClockFreq+0x34>
+ 80018c0:	2b0c      	cmp	r3, #12
+ 80018c2:	f200 80d5 	bhi.w	8001a70 <HAL_RCC_GetSysClockFreq+0x1c8>
+ 80018c6:	2b04      	cmp	r3, #4
+ 80018c8:	d002      	beq.n	80018d0 <HAL_RCC_GetSysClockFreq+0x28>
+ 80018ca:	2b08      	cmp	r3, #8
+ 80018cc:	d003      	beq.n	80018d6 <HAL_RCC_GetSysClockFreq+0x2e>
+ 80018ce:	e0cf      	b.n	8001a70 <HAL_RCC_GetSysClockFreq+0x1c8>
   {
     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
     {
       sysclockfreq = HSI_VALUE;
- 80017e4:	4b72      	ldr	r3, [pc, #456]	@ (80019b0 <HAL_RCC_GetSysClockFreq+0x1f4>)
- 80017e6:	643b      	str	r3, [r7, #64]	@ 0x40
+ 80018d0:	4b72      	ldr	r3, [pc, #456]	@ (8001a9c <HAL_RCC_GetSysClockFreq+0x1f4>)
+ 80018d2:	643b      	str	r3, [r7, #64]	@ 0x40
       break;
- 80017e8:	e0da      	b.n	80019a0 <HAL_RCC_GetSysClockFreq+0x1e4>
+ 80018d4:	e0da      	b.n	8001a8c <HAL_RCC_GetSysClockFreq+0x1e4>
     }
     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
     {
       sysclockfreq = HSE_VALUE;
- 80017ea:	4b72      	ldr	r3, [pc, #456]	@ (80019b4 <HAL_RCC_GetSysClockFreq+0x1f8>)
- 80017ec:	643b      	str	r3, [r7, #64]	@ 0x40
+ 80018d6:	4b72      	ldr	r3, [pc, #456]	@ (8001aa0 <HAL_RCC_GetSysClockFreq+0x1f8>)
+ 80018d8:	643b      	str	r3, [r7, #64]	@ 0x40
       break;
- 80017ee:	e0d7      	b.n	80019a0 <HAL_RCC_GetSysClockFreq+0x1e4>
+ 80018da:	e0d7      	b.n	8001a8c <HAL_RCC_GetSysClockFreq+0x1e4>
     }
     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
     {
       pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
- 80017f0:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80017f2:	0c9b      	lsrs	r3, r3, #18
- 80017f4:	f003 020f 	and.w	r2, r3, #15
- 80017f8:	4b6f      	ldr	r3, [pc, #444]	@ (80019b8 <HAL_RCC_GetSysClockFreq+0x1fc>)
- 80017fa:	5c9b      	ldrb	r3, [r3, r2]
- 80017fc:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 80018dc:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 80018de:	0c9b      	lsrs	r3, r3, #18
+ 80018e0:	f003 020f 	and.w	r2, r3, #15
+ 80018e4:	4b6f      	ldr	r3, [pc, #444]	@ (8001aa4 <HAL_RCC_GetSysClockFreq+0x1fc>)
+ 80018e6:	5c9b      	ldrb	r3, [r3, r2]
+ 80018e8:	63bb      	str	r3, [r7, #56]	@ 0x38
       plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
- 80017fe:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8001800:	0d9b      	lsrs	r3, r3, #22
- 8001802:	f003 0303 	and.w	r3, r3, #3
- 8001806:	3301      	adds	r3, #1
- 8001808:	637b      	str	r3, [r7, #52]	@ 0x34
+ 80018ea:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 80018ec:	0d9b      	lsrs	r3, r3, #22
+ 80018ee:	f003 0303 	and.w	r3, r3, #3
+ 80018f2:	3301      	adds	r3, #1
+ 80018f4:	637b      	str	r3, [r7, #52]	@ 0x34
       if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
- 800180a:	4b68      	ldr	r3, [pc, #416]	@ (80019ac <HAL_RCC_GetSysClockFreq+0x1f0>)
- 800180c:	689b      	ldr	r3, [r3, #8]
- 800180e:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
- 8001812:	2b00      	cmp	r3, #0
- 8001814:	d05d      	beq.n	80018d2 <HAL_RCC_GetSysClockFreq+0x116>
+ 80018f6:	4b68      	ldr	r3, [pc, #416]	@ (8001a98 <HAL_RCC_GetSysClockFreq+0x1f0>)
+ 80018f8:	689b      	ldr	r3, [r3, #8]
+ 80018fa:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 80018fe:	2b00      	cmp	r3, #0
+ 8001900:	d05d      	beq.n	80019be <HAL_RCC_GetSysClockFreq+0x116>
       {
         /* HSE used as PLL clock source */
         pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
- 8001816:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 8001818:	2200      	movs	r2, #0
- 800181a:	4618      	mov	r0, r3
- 800181c:	4611      	mov	r1, r2
- 800181e:	4604      	mov	r4, r0
- 8001820:	460d      	mov	r5, r1
- 8001822:	4622      	mov	r2, r4
- 8001824:	462b      	mov	r3, r5
- 8001826:	f04f 0000 	mov.w	r0, #0
- 800182a:	f04f 0100 	mov.w	r1, #0
- 800182e:	0159      	lsls	r1, r3, #5
- 8001830:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
- 8001834:	0150      	lsls	r0, r2, #5
- 8001836:	4602      	mov	r2, r0
- 8001838:	460b      	mov	r3, r1
- 800183a:	4621      	mov	r1, r4
- 800183c:	1a51      	subs	r1, r2, r1
- 800183e:	6139      	str	r1, [r7, #16]
- 8001840:	4629      	mov	r1, r5
- 8001842:	eb63 0301 	sbc.w	r3, r3, r1
- 8001846:	617b      	str	r3, [r7, #20]
- 8001848:	f04f 0200 	mov.w	r2, #0
- 800184c:	f04f 0300 	mov.w	r3, #0
- 8001850:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
- 8001854:	4659      	mov	r1, fp
- 8001856:	018b      	lsls	r3, r1, #6
- 8001858:	4651      	mov	r1, sl
- 800185a:	ea43 6391 	orr.w	r3, r3, r1, lsr #26
- 800185e:	4651      	mov	r1, sl
- 8001860:	018a      	lsls	r2, r1, #6
- 8001862:	46d4      	mov	ip, sl
- 8001864:	ebb2 080c 	subs.w	r8, r2, ip
- 8001868:	4659      	mov	r1, fp
- 800186a:	eb63 0901 	sbc.w	r9, r3, r1
- 800186e:	f04f 0200 	mov.w	r2, #0
- 8001872:	f04f 0300 	mov.w	r3, #0
- 8001876:	ea4f 03c9 	mov.w	r3, r9, lsl #3
- 800187a:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
- 800187e:	ea4f 02c8 	mov.w	r2, r8, lsl #3
- 8001882:	4690      	mov	r8, r2
- 8001884:	4699      	mov	r9, r3
- 8001886:	4623      	mov	r3, r4
- 8001888:	eb18 0303 	adds.w	r3, r8, r3
- 800188c:	60bb      	str	r3, [r7, #8]
- 800188e:	462b      	mov	r3, r5
- 8001890:	eb49 0303 	adc.w	r3, r9, r3
- 8001894:	60fb      	str	r3, [r7, #12]
- 8001896:	f04f 0200 	mov.w	r2, #0
- 800189a:	f04f 0300 	mov.w	r3, #0
- 800189e:	e9d7 4502 	ldrd	r4, r5, [r7, #8]
- 80018a2:	4629      	mov	r1, r5
- 80018a4:	024b      	lsls	r3, r1, #9
- 80018a6:	4620      	mov	r0, r4
- 80018a8:	4629      	mov	r1, r5
- 80018aa:	4604      	mov	r4, r0
- 80018ac:	ea43 53d4 	orr.w	r3, r3, r4, lsr #23
- 80018b0:	4601      	mov	r1, r0
- 80018b2:	024a      	lsls	r2, r1, #9
- 80018b4:	4610      	mov	r0, r2
- 80018b6:	4619      	mov	r1, r3
- 80018b8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 80018ba:	2200      	movs	r2, #0
- 80018bc:	62bb      	str	r3, [r7, #40]	@ 0x28
- 80018be:	62fa      	str	r2, [r7, #44]	@ 0x2c
- 80018c0:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	@ 0x28
- 80018c4:	f7fe fc5a 	bl	800017c <__aeabi_uldivmod>
- 80018c8:	4602      	mov	r2, r0
- 80018ca:	460b      	mov	r3, r1
- 80018cc:	4613      	mov	r3, r2
- 80018ce:	647b      	str	r3, [r7, #68]	@ 0x44
- 80018d0:	e055      	b.n	800197e <HAL_RCC_GetSysClockFreq+0x1c2>
+ 8001902:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8001904:	2200      	movs	r2, #0
+ 8001906:	4618      	mov	r0, r3
+ 8001908:	4611      	mov	r1, r2
+ 800190a:	4604      	mov	r4, r0
+ 800190c:	460d      	mov	r5, r1
+ 800190e:	4622      	mov	r2, r4
+ 8001910:	462b      	mov	r3, r5
+ 8001912:	f04f 0000 	mov.w	r0, #0
+ 8001916:	f04f 0100 	mov.w	r1, #0
+ 800191a:	0159      	lsls	r1, r3, #5
+ 800191c:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
+ 8001920:	0150      	lsls	r0, r2, #5
+ 8001922:	4602      	mov	r2, r0
+ 8001924:	460b      	mov	r3, r1
+ 8001926:	4621      	mov	r1, r4
+ 8001928:	1a51      	subs	r1, r2, r1
+ 800192a:	6139      	str	r1, [r7, #16]
+ 800192c:	4629      	mov	r1, r5
+ 800192e:	eb63 0301 	sbc.w	r3, r3, r1
+ 8001932:	617b      	str	r3, [r7, #20]
+ 8001934:	f04f 0200 	mov.w	r2, #0
+ 8001938:	f04f 0300 	mov.w	r3, #0
+ 800193c:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
+ 8001940:	4659      	mov	r1, fp
+ 8001942:	018b      	lsls	r3, r1, #6
+ 8001944:	4651      	mov	r1, sl
+ 8001946:	ea43 6391 	orr.w	r3, r3, r1, lsr #26
+ 800194a:	4651      	mov	r1, sl
+ 800194c:	018a      	lsls	r2, r1, #6
+ 800194e:	46d4      	mov	ip, sl
+ 8001950:	ebb2 080c 	subs.w	r8, r2, ip
+ 8001954:	4659      	mov	r1, fp
+ 8001956:	eb63 0901 	sbc.w	r9, r3, r1
+ 800195a:	f04f 0200 	mov.w	r2, #0
+ 800195e:	f04f 0300 	mov.w	r3, #0
+ 8001962:	ea4f 03c9 	mov.w	r3, r9, lsl #3
+ 8001966:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
+ 800196a:	ea4f 02c8 	mov.w	r2, r8, lsl #3
+ 800196e:	4690      	mov	r8, r2
+ 8001970:	4699      	mov	r9, r3
+ 8001972:	4623      	mov	r3, r4
+ 8001974:	eb18 0303 	adds.w	r3, r8, r3
+ 8001978:	60bb      	str	r3, [r7, #8]
+ 800197a:	462b      	mov	r3, r5
+ 800197c:	eb49 0303 	adc.w	r3, r9, r3
+ 8001980:	60fb      	str	r3, [r7, #12]
+ 8001982:	f04f 0200 	mov.w	r2, #0
+ 8001986:	f04f 0300 	mov.w	r3, #0
+ 800198a:	e9d7 4502 	ldrd	r4, r5, [r7, #8]
+ 800198e:	4629      	mov	r1, r5
+ 8001990:	024b      	lsls	r3, r1, #9
+ 8001992:	4620      	mov	r0, r4
+ 8001994:	4629      	mov	r1, r5
+ 8001996:	4604      	mov	r4, r0
+ 8001998:	ea43 53d4 	orr.w	r3, r3, r4, lsr #23
+ 800199c:	4601      	mov	r1, r0
+ 800199e:	024a      	lsls	r2, r1, #9
+ 80019a0:	4610      	mov	r0, r2
+ 80019a2:	4619      	mov	r1, r3
+ 80019a4:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 80019a6:	2200      	movs	r2, #0
+ 80019a8:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 80019aa:	62fa      	str	r2, [r7, #44]	@ 0x2c
+ 80019ac:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	@ 0x28
+ 80019b0:	f7fe fbe4 	bl	800017c <__aeabi_uldivmod>
+ 80019b4:	4602      	mov	r2, r0
+ 80019b6:	460b      	mov	r3, r1
+ 80019b8:	4613      	mov	r3, r2
+ 80019ba:	647b      	str	r3, [r7, #68]	@ 0x44
+ 80019bc:	e055      	b.n	8001a6a <HAL_RCC_GetSysClockFreq+0x1c2>
       }
       else
       {
         /* HSI used as PLL clock source */
         pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
- 80018d2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 80018d4:	2200      	movs	r2, #0
- 80018d6:	623b      	str	r3, [r7, #32]
- 80018d8:	627a      	str	r2, [r7, #36]	@ 0x24
- 80018da:	e9d7 8908 	ldrd	r8, r9, [r7, #32]
- 80018de:	4642      	mov	r2, r8
- 80018e0:	464b      	mov	r3, r9
- 80018e2:	f04f 0000 	mov.w	r0, #0
- 80018e6:	f04f 0100 	mov.w	r1, #0
- 80018ea:	0159      	lsls	r1, r3, #5
- 80018ec:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
- 80018f0:	0150      	lsls	r0, r2, #5
- 80018f2:	4602      	mov	r2, r0
- 80018f4:	460b      	mov	r3, r1
- 80018f6:	46c4      	mov	ip, r8
- 80018f8:	ebb2 0a0c 	subs.w	sl, r2, ip
- 80018fc:	4640      	mov	r0, r8
- 80018fe:	4649      	mov	r1, r9
- 8001900:	468c      	mov	ip, r1
- 8001902:	eb63 0b0c 	sbc.w	fp, r3, ip
- 8001906:	f04f 0200 	mov.w	r2, #0
- 800190a:	f04f 0300 	mov.w	r3, #0
- 800190e:	ea4f 138b 	mov.w	r3, fp, lsl #6
- 8001912:	ea43 639a 	orr.w	r3, r3, sl, lsr #26
- 8001916:	ea4f 128a 	mov.w	r2, sl, lsl #6
- 800191a:	ebb2 040a 	subs.w	r4, r2, sl
- 800191e:	eb63 050b 	sbc.w	r5, r3, fp
- 8001922:	f04f 0200 	mov.w	r2, #0
- 8001926:	f04f 0300 	mov.w	r3, #0
- 800192a:	00eb      	lsls	r3, r5, #3
- 800192c:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
- 8001930:	00e2      	lsls	r2, r4, #3
- 8001932:	4614      	mov	r4, r2
- 8001934:	461d      	mov	r5, r3
- 8001936:	4603      	mov	r3, r0
- 8001938:	18e3      	adds	r3, r4, r3
- 800193a:	603b      	str	r3, [r7, #0]
- 800193c:	460b      	mov	r3, r1
- 800193e:	eb45 0303 	adc.w	r3, r5, r3
- 8001942:	607b      	str	r3, [r7, #4]
- 8001944:	f04f 0200 	mov.w	r2, #0
- 8001948:	f04f 0300 	mov.w	r3, #0
- 800194c:	e9d7 4500 	ldrd	r4, r5, [r7]
- 8001950:	4629      	mov	r1, r5
- 8001952:	028b      	lsls	r3, r1, #10
- 8001954:	4620      	mov	r0, r4
- 8001956:	4629      	mov	r1, r5
- 8001958:	4604      	mov	r4, r0
- 800195a:	ea43 5394 	orr.w	r3, r3, r4, lsr #22
- 800195e:	4601      	mov	r1, r0
- 8001960:	028a      	lsls	r2, r1, #10
- 8001962:	4610      	mov	r0, r2
- 8001964:	4619      	mov	r1, r3
- 8001966:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 8001968:	2200      	movs	r2, #0
- 800196a:	61bb      	str	r3, [r7, #24]
- 800196c:	61fa      	str	r2, [r7, #28]
- 800196e:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
- 8001972:	f7fe fc03 	bl	800017c <__aeabi_uldivmod>
- 8001976:	4602      	mov	r2, r0
- 8001978:	460b      	mov	r3, r1
- 800197a:	4613      	mov	r3, r2
- 800197c:	647b      	str	r3, [r7, #68]	@ 0x44
+ 80019be:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 80019c0:	2200      	movs	r2, #0
+ 80019c2:	623b      	str	r3, [r7, #32]
+ 80019c4:	627a      	str	r2, [r7, #36]	@ 0x24
+ 80019c6:	e9d7 8908 	ldrd	r8, r9, [r7, #32]
+ 80019ca:	4642      	mov	r2, r8
+ 80019cc:	464b      	mov	r3, r9
+ 80019ce:	f04f 0000 	mov.w	r0, #0
+ 80019d2:	f04f 0100 	mov.w	r1, #0
+ 80019d6:	0159      	lsls	r1, r3, #5
+ 80019d8:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
+ 80019dc:	0150      	lsls	r0, r2, #5
+ 80019de:	4602      	mov	r2, r0
+ 80019e0:	460b      	mov	r3, r1
+ 80019e2:	46c4      	mov	ip, r8
+ 80019e4:	ebb2 0a0c 	subs.w	sl, r2, ip
+ 80019e8:	4640      	mov	r0, r8
+ 80019ea:	4649      	mov	r1, r9
+ 80019ec:	468c      	mov	ip, r1
+ 80019ee:	eb63 0b0c 	sbc.w	fp, r3, ip
+ 80019f2:	f04f 0200 	mov.w	r2, #0
+ 80019f6:	f04f 0300 	mov.w	r3, #0
+ 80019fa:	ea4f 138b 	mov.w	r3, fp, lsl #6
+ 80019fe:	ea43 639a 	orr.w	r3, r3, sl, lsr #26
+ 8001a02:	ea4f 128a 	mov.w	r2, sl, lsl #6
+ 8001a06:	ebb2 040a 	subs.w	r4, r2, sl
+ 8001a0a:	eb63 050b 	sbc.w	r5, r3, fp
+ 8001a0e:	f04f 0200 	mov.w	r2, #0
+ 8001a12:	f04f 0300 	mov.w	r3, #0
+ 8001a16:	00eb      	lsls	r3, r5, #3
+ 8001a18:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
+ 8001a1c:	00e2      	lsls	r2, r4, #3
+ 8001a1e:	4614      	mov	r4, r2
+ 8001a20:	461d      	mov	r5, r3
+ 8001a22:	4603      	mov	r3, r0
+ 8001a24:	18e3      	adds	r3, r4, r3
+ 8001a26:	603b      	str	r3, [r7, #0]
+ 8001a28:	460b      	mov	r3, r1
+ 8001a2a:	eb45 0303 	adc.w	r3, r5, r3
+ 8001a2e:	607b      	str	r3, [r7, #4]
+ 8001a30:	f04f 0200 	mov.w	r2, #0
+ 8001a34:	f04f 0300 	mov.w	r3, #0
+ 8001a38:	e9d7 4500 	ldrd	r4, r5, [r7]
+ 8001a3c:	4629      	mov	r1, r5
+ 8001a3e:	028b      	lsls	r3, r1, #10
+ 8001a40:	4620      	mov	r0, r4
+ 8001a42:	4629      	mov	r1, r5
+ 8001a44:	4604      	mov	r4, r0
+ 8001a46:	ea43 5394 	orr.w	r3, r3, r4, lsr #22
+ 8001a4a:	4601      	mov	r1, r0
+ 8001a4c:	028a      	lsls	r2, r1, #10
+ 8001a4e:	4610      	mov	r0, r2
+ 8001a50:	4619      	mov	r1, r3
+ 8001a52:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8001a54:	2200      	movs	r2, #0
+ 8001a56:	61bb      	str	r3, [r7, #24]
+ 8001a58:	61fa      	str	r2, [r7, #28]
+ 8001a5a:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
+ 8001a5e:	f7fe fb8d 	bl	800017c <__aeabi_uldivmod>
+ 8001a62:	4602      	mov	r2, r0
+ 8001a64:	460b      	mov	r3, r1
+ 8001a66:	4613      	mov	r3, r2
+ 8001a68:	647b      	str	r3, [r7, #68]	@ 0x44
       }
       sysclockfreq = pllvco;
- 800197e:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8001980:	643b      	str	r3, [r7, #64]	@ 0x40
+ 8001a6a:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8001a6c:	643b      	str	r3, [r7, #64]	@ 0x40
       break;
- 8001982:	e00d      	b.n	80019a0 <HAL_RCC_GetSysClockFreq+0x1e4>
+ 8001a6e:	e00d      	b.n	8001a8c <HAL_RCC_GetSysClockFreq+0x1e4>
     }
     case RCC_SYSCLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
     default: /* MSI used as system clock */
     {
       msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
- 8001984:	4b09      	ldr	r3, [pc, #36]	@ (80019ac <HAL_RCC_GetSysClockFreq+0x1f0>)
- 8001986:	685b      	ldr	r3, [r3, #4]
- 8001988:	0b5b      	lsrs	r3, r3, #13
- 800198a:	f003 0307 	and.w	r3, r3, #7
- 800198e:	633b      	str	r3, [r7, #48]	@ 0x30
+ 8001a70:	4b09      	ldr	r3, [pc, #36]	@ (8001a98 <HAL_RCC_GetSysClockFreq+0x1f0>)
+ 8001a72:	685b      	ldr	r3, [r3, #4]
+ 8001a74:	0b5b      	lsrs	r3, r3, #13
+ 8001a76:	f003 0307 	and.w	r3, r3, #7
+ 8001a7a:	633b      	str	r3, [r7, #48]	@ 0x30
       sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
- 8001990:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 8001992:	3301      	adds	r3, #1
- 8001994:	f44f 4200 	mov.w	r2, #32768	@ 0x8000
- 8001998:	fa02 f303 	lsl.w	r3, r2, r3
- 800199c:	643b      	str	r3, [r7, #64]	@ 0x40
+ 8001a7c:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 8001a7e:	3301      	adds	r3, #1
+ 8001a80:	f44f 4200 	mov.w	r2, #32768	@ 0x8000
+ 8001a84:	fa02 f303 	lsl.w	r3, r2, r3
+ 8001a88:	643b      	str	r3, [r7, #64]	@ 0x40
       break;
- 800199e:	bf00      	nop
+ 8001a8a:	bf00      	nop
     }
   }
   return sysclockfreq;
- 80019a0:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8001a8c:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
 }
- 80019a2:	4618      	mov	r0, r3
- 80019a4:	3748      	adds	r7, #72	@ 0x48
- 80019a6:	46bd      	mov	sp, r7
- 80019a8:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
- 80019ac:	40023800 	.word	0x40023800
- 80019b0:	00f42400 	.word	0x00f42400
- 80019b4:	007a1200 	.word	0x007a1200
- 80019b8:	08001db8 	.word	0x08001db8
+ 8001a8e:	4618      	mov	r0, r3
+ 8001a90:	3748      	adds	r7, #72	@ 0x48
+ 8001a92:	46bd      	mov	sp, r7
+ 8001a94:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 8001a98:	40023800 	.word	0x40023800
+ 8001a9c:	00f42400 	.word	0x00f42400
+ 8001aa0:	007a1200 	.word	0x007a1200
+ 8001aa4:	080022bc 	.word	0x080022bc
 
-080019bc <HAL_RCC_GetHCLKFreq>:
+08001aa8 <HAL_RCC_GetHCLKFreq>:
   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
   *         and updated within this function
   * @retval HCLK frequency
   */
 uint32_t HAL_RCC_GetHCLKFreq(void)
 {
- 80019bc:	b480      	push	{r7}
- 80019be:	af00      	add	r7, sp, #0
+ 8001aa8:	b480      	push	{r7}
+ 8001aaa:	af00      	add	r7, sp, #0
   return SystemCoreClock;
- 80019c0:	4b02      	ldr	r3, [pc, #8]	@ (80019cc <HAL_RCC_GetHCLKFreq+0x10>)
- 80019c2:	681b      	ldr	r3, [r3, #0]
+ 8001aac:	4b02      	ldr	r3, [pc, #8]	@ (8001ab8 <HAL_RCC_GetHCLKFreq+0x10>)
+ 8001aae:	681b      	ldr	r3, [r3, #0]
 }
- 80019c4:	4618      	mov	r0, r3
- 80019c6:	46bd      	mov	sp, r7
- 80019c8:	bc80      	pop	{r7}
- 80019ca:	4770      	bx	lr
- 80019cc:	20000000 	.word	0x20000000
+ 8001ab0:	4618      	mov	r0, r3
+ 8001ab2:	46bd      	mov	sp, r7
+ 8001ab4:	bc80      	pop	{r7}
+ 8001ab6:	4770      	bx	lr
+ 8001ab8:	20000000 	.word	0x20000000
 
-080019d0 <HAL_RCC_GetPCLK1Freq>:
+08001abc <HAL_RCC_GetPCLK1Freq>:
   * @note   Each time PCLK1 changes, this function must be called to update the
   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK1 frequency
   */
 uint32_t HAL_RCC_GetPCLK1Freq(void)
 {
- 80019d0:	b580      	push	{r7, lr}
- 80019d2:	af00      	add	r7, sp, #0
+ 8001abc:	b580      	push	{r7, lr}
+ 8001abe:	af00      	add	r7, sp, #0
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
- 80019d4:	f7ff fff2 	bl	80019bc <HAL_RCC_GetHCLKFreq>
- 80019d8:	4602      	mov	r2, r0
- 80019da:	4b05      	ldr	r3, [pc, #20]	@ (80019f0 <HAL_RCC_GetPCLK1Freq+0x20>)
- 80019dc:	689b      	ldr	r3, [r3, #8]
- 80019de:	0a1b      	lsrs	r3, r3, #8
- 80019e0:	f003 0307 	and.w	r3, r3, #7
- 80019e4:	4903      	ldr	r1, [pc, #12]	@ (80019f4 <HAL_RCC_GetPCLK1Freq+0x24>)
- 80019e6:	5ccb      	ldrb	r3, [r1, r3]
- 80019e8:	fa22 f303 	lsr.w	r3, r2, r3
+ 8001ac0:	f7ff fff2 	bl	8001aa8 <HAL_RCC_GetHCLKFreq>
+ 8001ac4:	4602      	mov	r2, r0
+ 8001ac6:	4b05      	ldr	r3, [pc, #20]	@ (8001adc <HAL_RCC_GetPCLK1Freq+0x20>)
+ 8001ac8:	689b      	ldr	r3, [r3, #8]
+ 8001aca:	0a1b      	lsrs	r3, r3, #8
+ 8001acc:	f003 0307 	and.w	r3, r3, #7
+ 8001ad0:	4903      	ldr	r1, [pc, #12]	@ (8001ae0 <HAL_RCC_GetPCLK1Freq+0x24>)
+ 8001ad2:	5ccb      	ldrb	r3, [r1, r3]
+ 8001ad4:	fa22 f303 	lsr.w	r3, r2, r3
 }
- 80019ec:	4618      	mov	r0, r3
- 80019ee:	bd80      	pop	{r7, pc}
- 80019f0:	40023800 	.word	0x40023800
- 80019f4:	08001dd4 	.word	0x08001dd4
+ 8001ad8:	4618      	mov	r0, r3
+ 8001ada:	bd80      	pop	{r7, pc}
+ 8001adc:	40023800 	.word	0x40023800
+ 8001ae0:	080022d8 	.word	0x080022d8
 
-080019f8 <HAL_RCC_GetPCLK2Freq>:
+08001ae4 <HAL_RCC_GetPCLK2Freq>:
   * @note   Each time PCLK2 changes, this function must be called to update the
   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK2 frequency
   */
 uint32_t HAL_RCC_GetPCLK2Freq(void)
 {
- 80019f8:	b580      	push	{r7, lr}
- 80019fa:	af00      	add	r7, sp, #0
+ 8001ae4:	b580      	push	{r7, lr}
+ 8001ae6:	af00      	add	r7, sp, #0
   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
- 80019fc:	f7ff ffde 	bl	80019bc <HAL_RCC_GetHCLKFreq>
- 8001a00:	4602      	mov	r2, r0
- 8001a02:	4b05      	ldr	r3, [pc, #20]	@ (8001a18 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8001a04:	689b      	ldr	r3, [r3, #8]
- 8001a06:	0adb      	lsrs	r3, r3, #11
- 8001a08:	f003 0307 	and.w	r3, r3, #7
- 8001a0c:	4903      	ldr	r1, [pc, #12]	@ (8001a1c <HAL_RCC_GetPCLK2Freq+0x24>)
- 8001a0e:	5ccb      	ldrb	r3, [r1, r3]
- 8001a10:	fa22 f303 	lsr.w	r3, r2, r3
+ 8001ae8:	f7ff ffde 	bl	8001aa8 <HAL_RCC_GetHCLKFreq>
+ 8001aec:	4602      	mov	r2, r0
+ 8001aee:	4b05      	ldr	r3, [pc, #20]	@ (8001b04 <HAL_RCC_GetPCLK2Freq+0x20>)
+ 8001af0:	689b      	ldr	r3, [r3, #8]
+ 8001af2:	0adb      	lsrs	r3, r3, #11
+ 8001af4:	f003 0307 	and.w	r3, r3, #7
+ 8001af8:	4903      	ldr	r1, [pc, #12]	@ (8001b08 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 8001afa:	5ccb      	ldrb	r3, [r1, r3]
+ 8001afc:	fa22 f303 	lsr.w	r3, r2, r3
 }
- 8001a14:	4618      	mov	r0, r3
- 8001a16:	bd80      	pop	{r7, pc}
- 8001a18:	40023800 	.word	0x40023800
- 8001a1c:	08001dd4 	.word	0x08001dd4
+ 8001b00:	4618      	mov	r0, r3
+ 8001b02:	bd80      	pop	{r7, pc}
+ 8001b04:	40023800 	.word	0x40023800
+ 8001b08:	080022d8 	.word	0x080022d8
 
-08001a20 <RCC_SetFlashLatencyFromMSIRange>:
+08001b0c <RCC_SetFlashLatencyFromMSIRange>:
             voltage range
   * @param  MSIrange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
   * @retval HAL status
   */
 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
 {
- 8001a20:	b480      	push	{r7}
- 8001a22:	b087      	sub	sp, #28
- 8001a24:	af00      	add	r7, sp, #0
- 8001a26:	6078      	str	r0, [r7, #4]
+ 8001b0c:	b480      	push	{r7}
+ 8001b0e:	b087      	sub	sp, #28
+ 8001b10:	af00      	add	r7, sp, #0
+ 8001b12:	6078      	str	r0, [r7, #4]
   uint32_t vos;
   uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
- 8001a28:	2300      	movs	r3, #0
- 8001a2a:	613b      	str	r3, [r7, #16]
+ 8001b14:	2300      	movs	r3, #0
+ 8001b16:	613b      	str	r3, [r7, #16]
 
   /* HCLK can reach 4 MHz only if AHB prescaler = 1 */
   if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
- 8001a2c:	4b29      	ldr	r3, [pc, #164]	@ (8001ad4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
- 8001a2e:	689b      	ldr	r3, [r3, #8]
- 8001a30:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
- 8001a34:	2b00      	cmp	r3, #0
- 8001a36:	d12c      	bne.n	8001a92 <RCC_SetFlashLatencyFromMSIRange+0x72>
+ 8001b18:	4b29      	ldr	r3, [pc, #164]	@ (8001bc0 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
+ 8001b1a:	689b      	ldr	r3, [r3, #8]
+ 8001b1c:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
+ 8001b20:	2b00      	cmp	r3, #0
+ 8001b22:	d12c      	bne.n	8001b7e <RCC_SetFlashLatencyFromMSIRange+0x72>
   {
     if(__HAL_RCC_PWR_IS_CLK_ENABLED())
- 8001a38:	4b26      	ldr	r3, [pc, #152]	@ (8001ad4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
- 8001a3a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8001a3c:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 8001a40:	2b00      	cmp	r3, #0
- 8001a42:	d005      	beq.n	8001a50 <RCC_SetFlashLatencyFromMSIRange+0x30>
+ 8001b24:	4b26      	ldr	r3, [pc, #152]	@ (8001bc0 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
+ 8001b26:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8001b28:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 8001b2c:	2b00      	cmp	r3, #0
+ 8001b2e:	d005      	beq.n	8001b3c <RCC_SetFlashLatencyFromMSIRange+0x30>
     {
       vos = READ_BIT(PWR->CR, PWR_CR_VOS);
- 8001a44:	4b24      	ldr	r3, [pc, #144]	@ (8001ad8 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
- 8001a46:	681b      	ldr	r3, [r3, #0]
- 8001a48:	f403 53c0 	and.w	r3, r3, #6144	@ 0x1800
- 8001a4c:	617b      	str	r3, [r7, #20]
- 8001a4e:	e016      	b.n	8001a7e <RCC_SetFlashLatencyFromMSIRange+0x5e>
+ 8001b30:	4b24      	ldr	r3, [pc, #144]	@ (8001bc4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
+ 8001b32:	681b      	ldr	r3, [r3, #0]
+ 8001b34:	f403 53c0 	and.w	r3, r3, #6144	@ 0x1800
+ 8001b38:	617b      	str	r3, [r7, #20]
+ 8001b3a:	e016      	b.n	8001b6a <RCC_SetFlashLatencyFromMSIRange+0x5e>
     }
     else
     {
       __HAL_RCC_PWR_CLK_ENABLE();
- 8001a50:	4b20      	ldr	r3, [pc, #128]	@ (8001ad4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
- 8001a52:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8001a54:	4a1f      	ldr	r2, [pc, #124]	@ (8001ad4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
- 8001a56:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
- 8001a5a:	6253      	str	r3, [r2, #36]	@ 0x24
- 8001a5c:	4b1d      	ldr	r3, [pc, #116]	@ (8001ad4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
- 8001a5e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8001a60:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
- 8001a64:	60fb      	str	r3, [r7, #12]
- 8001a66:	68fb      	ldr	r3, [r7, #12]
+ 8001b3c:	4b20      	ldr	r3, [pc, #128]	@ (8001bc0 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
+ 8001b3e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8001b40:	4a1f      	ldr	r2, [pc, #124]	@ (8001bc0 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
+ 8001b42:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 8001b46:	6253      	str	r3, [r2, #36]	@ 0x24
+ 8001b48:	4b1d      	ldr	r3, [pc, #116]	@ (8001bc0 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
+ 8001b4a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8001b4c:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 8001b50:	60fb      	str	r3, [r7, #12]
+ 8001b52:	68fb      	ldr	r3, [r7, #12]
       vos = READ_BIT(PWR->CR, PWR_CR_VOS);
- 8001a68:	4b1b      	ldr	r3, [pc, #108]	@ (8001ad8 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
- 8001a6a:	681b      	ldr	r3, [r3, #0]
- 8001a6c:	f403 53c0 	and.w	r3, r3, #6144	@ 0x1800
- 8001a70:	617b      	str	r3, [r7, #20]
+ 8001b54:	4b1b      	ldr	r3, [pc, #108]	@ (8001bc4 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
+ 8001b56:	681b      	ldr	r3, [r3, #0]
+ 8001b58:	f403 53c0 	and.w	r3, r3, #6144	@ 0x1800
+ 8001b5c:	617b      	str	r3, [r7, #20]
       __HAL_RCC_PWR_CLK_DISABLE();
- 8001a72:	4b18      	ldr	r3, [pc, #96]	@ (8001ad4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
- 8001a74:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8001a76:	4a17      	ldr	r2, [pc, #92]	@ (8001ad4 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
- 8001a78:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
- 8001a7c:	6253      	str	r3, [r2, #36]	@ 0x24
+ 8001b5e:	4b18      	ldr	r3, [pc, #96]	@ (8001bc0 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
+ 8001b60:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8001b62:	4a17      	ldr	r2, [pc, #92]	@ (8001bc0 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
+ 8001b64:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
+ 8001b68:	6253      	str	r3, [r2, #36]	@ 0x24
     }
 
     /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
     if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
- 8001a7e:	697b      	ldr	r3, [r7, #20]
- 8001a80:	f5b3 5fc0 	cmp.w	r3, #6144	@ 0x1800
- 8001a84:	d105      	bne.n	8001a92 <RCC_SetFlashLatencyFromMSIRange+0x72>
- 8001a86:	687b      	ldr	r3, [r7, #4]
- 8001a88:	f5b3 4f40 	cmp.w	r3, #49152	@ 0xc000
- 8001a8c:	d101      	bne.n	8001a92 <RCC_SetFlashLatencyFromMSIRange+0x72>
+ 8001b6a:	697b      	ldr	r3, [r7, #20]
+ 8001b6c:	f5b3 5fc0 	cmp.w	r3, #6144	@ 0x1800
+ 8001b70:	d105      	bne.n	8001b7e <RCC_SetFlashLatencyFromMSIRange+0x72>
+ 8001b72:	687b      	ldr	r3, [r7, #4]
+ 8001b74:	f5b3 4f40 	cmp.w	r3, #49152	@ 0xc000
+ 8001b78:	d101      	bne.n	8001b7e <RCC_SetFlashLatencyFromMSIRange+0x72>
     {
       latency = FLASH_LATENCY_1; /* 1WS */
- 8001a8e:	2301      	movs	r3, #1
- 8001a90:	613b      	str	r3, [r7, #16]
+ 8001b7a:	2301      	movs	r3, #1
+ 8001b7c:	613b      	str	r3, [r7, #16]
     }
   }
 
   __HAL_FLASH_SET_LATENCY(latency);
- 8001a92:	693b      	ldr	r3, [r7, #16]
- 8001a94:	2b01      	cmp	r3, #1
- 8001a96:	d105      	bne.n	8001aa4 <RCC_SetFlashLatencyFromMSIRange+0x84>
- 8001a98:	4b10      	ldr	r3, [pc, #64]	@ (8001adc <RCC_SetFlashLatencyFromMSIRange+0xbc>)
- 8001a9a:	681b      	ldr	r3, [r3, #0]
- 8001a9c:	4a0f      	ldr	r2, [pc, #60]	@ (8001adc <RCC_SetFlashLatencyFromMSIRange+0xbc>)
- 8001a9e:	f043 0304 	orr.w	r3, r3, #4
- 8001aa2:	6013      	str	r3, [r2, #0]
- 8001aa4:	4b0d      	ldr	r3, [pc, #52]	@ (8001adc <RCC_SetFlashLatencyFromMSIRange+0xbc>)
- 8001aa6:	681b      	ldr	r3, [r3, #0]
- 8001aa8:	f023 0201 	bic.w	r2, r3, #1
- 8001aac:	490b      	ldr	r1, [pc, #44]	@ (8001adc <RCC_SetFlashLatencyFromMSIRange+0xbc>)
- 8001aae:	693b      	ldr	r3, [r7, #16]
- 8001ab0:	4313      	orrs	r3, r2
- 8001ab2:	600b      	str	r3, [r1, #0]
+ 8001b7e:	693b      	ldr	r3, [r7, #16]
+ 8001b80:	2b01      	cmp	r3, #1
+ 8001b82:	d105      	bne.n	8001b90 <RCC_SetFlashLatencyFromMSIRange+0x84>
+ 8001b84:	4b10      	ldr	r3, [pc, #64]	@ (8001bc8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
+ 8001b86:	681b      	ldr	r3, [r3, #0]
+ 8001b88:	4a0f      	ldr	r2, [pc, #60]	@ (8001bc8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
+ 8001b8a:	f043 0304 	orr.w	r3, r3, #4
+ 8001b8e:	6013      	str	r3, [r2, #0]
+ 8001b90:	4b0d      	ldr	r3, [pc, #52]	@ (8001bc8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
+ 8001b92:	681b      	ldr	r3, [r3, #0]
+ 8001b94:	f023 0201 	bic.w	r2, r3, #1
+ 8001b98:	490b      	ldr	r1, [pc, #44]	@ (8001bc8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
+ 8001b9a:	693b      	ldr	r3, [r7, #16]
+ 8001b9c:	4313      	orrs	r3, r2
+ 8001b9e:	600b      	str	r3, [r1, #0]
 
   /* Check that the new number of wait states is taken into account to access the Flash
      memory by reading the FLASH_ACR register */
   if(__HAL_FLASH_GET_LATENCY() != latency)
- 8001ab4:	4b09      	ldr	r3, [pc, #36]	@ (8001adc <RCC_SetFlashLatencyFromMSIRange+0xbc>)
- 8001ab6:	681b      	ldr	r3, [r3, #0]
- 8001ab8:	f003 0301 	and.w	r3, r3, #1
- 8001abc:	693a      	ldr	r2, [r7, #16]
- 8001abe:	429a      	cmp	r2, r3
- 8001ac0:	d001      	beq.n	8001ac6 <RCC_SetFlashLatencyFromMSIRange+0xa6>
+ 8001ba0:	4b09      	ldr	r3, [pc, #36]	@ (8001bc8 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
+ 8001ba2:	681b      	ldr	r3, [r3, #0]
+ 8001ba4:	f003 0301 	and.w	r3, r3, #1
+ 8001ba8:	693a      	ldr	r2, [r7, #16]
+ 8001baa:	429a      	cmp	r2, r3
+ 8001bac:	d001      	beq.n	8001bb2 <RCC_SetFlashLatencyFromMSIRange+0xa6>
   {
     return HAL_ERROR;
- 8001ac2:	2301      	movs	r3, #1
- 8001ac4:	e000      	b.n	8001ac8 <RCC_SetFlashLatencyFromMSIRange+0xa8>
+ 8001bae:	2301      	movs	r3, #1
+ 8001bb0:	e000      	b.n	8001bb4 <RCC_SetFlashLatencyFromMSIRange+0xa8>
   }
 
   return HAL_OK;
- 8001ac6:	2300      	movs	r3, #0
+ 8001bb2:	2300      	movs	r3, #0
 }
- 8001ac8:	4618      	mov	r0, r3
- 8001aca:	371c      	adds	r7, #28
- 8001acc:	46bd      	mov	sp, r7
- 8001ace:	bc80      	pop	{r7}
- 8001ad0:	4770      	bx	lr
- 8001ad2:	bf00      	nop
- 8001ad4:	40023800 	.word	0x40023800
- 8001ad8:	40007000 	.word	0x40007000
- 8001adc:	40023c00 	.word	0x40023c00
+ 8001bb4:	4618      	mov	r0, r3
+ 8001bb6:	371c      	adds	r7, #28
+ 8001bb8:	46bd      	mov	sp, r7
+ 8001bba:	bc80      	pop	{r7}
+ 8001bbc:	4770      	bx	lr
+ 8001bbe:	bf00      	nop
+ 8001bc0:	40023800 	.word	0x40023800
+ 8001bc4:	40007000 	.word	0x40007000
+ 8001bc8:	40023c00 	.word	0x40023c00
 
-08001ae0 <HAL_UART_Init>:
+08001bcc <HAL_TIM_Base_Init>:
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ 8001bcc:	b580      	push	{r7, lr}
+ 8001bce:	b082      	sub	sp, #8
+ 8001bd0:	af00      	add	r7, sp, #0
+ 8001bd2:	6078      	str	r0, [r7, #4]
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 8001bd4:	687b      	ldr	r3, [r7, #4]
+ 8001bd6:	2b00      	cmp	r3, #0
+ 8001bd8:	d101      	bne.n	8001bde <HAL_TIM_Base_Init+0x12>
+  {
+    return HAL_ERROR;
+ 8001bda:	2301      	movs	r3, #1
+ 8001bdc:	e031      	b.n	8001c42 <HAL_TIM_Base_Init+0x76>
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 8001bde:	687b      	ldr	r3, [r7, #4]
+ 8001be0:	f893 3039 	ldrb.w	r3, [r3, #57]	@ 0x39
+ 8001be4:	b2db      	uxtb	r3, r3
+ 8001be6:	2b00      	cmp	r3, #0
+ 8001be8:	d106      	bne.n	8001bf8 <HAL_TIM_Base_Init+0x2c>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 8001bea:	687b      	ldr	r3, [r7, #4]
+ 8001bec:	2200      	movs	r2, #0
+ 8001bee:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+ 8001bf2:	6878      	ldr	r0, [r7, #4]
+ 8001bf4:	f7fe fddc 	bl	80007b0 <HAL_TIM_Base_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8001bf8:	687b      	ldr	r3, [r7, #4]
+ 8001bfa:	2202      	movs	r2, #2
+ 8001bfc:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8001c00:	687b      	ldr	r3, [r7, #4]
+ 8001c02:	681a      	ldr	r2, [r3, #0]
+ 8001c04:	687b      	ldr	r3, [r7, #4]
+ 8001c06:	3304      	adds	r3, #4
+ 8001c08:	4619      	mov	r1, r3
+ 8001c0a:	4610      	mov	r0, r2
+ 8001c0c:	f000 f916 	bl	8001e3c <TIM_Base_SetConfig>
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8001c10:	687b      	ldr	r3, [r7, #4]
+ 8001c12:	2201      	movs	r2, #1
+ 8001c14:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 8001c18:	687b      	ldr	r3, [r7, #4]
+ 8001c1a:	2201      	movs	r2, #1
+ 8001c1c:	f883 203a 	strb.w	r2, [r3, #58]	@ 0x3a
+ 8001c20:	687b      	ldr	r3, [r7, #4]
+ 8001c22:	2201      	movs	r2, #1
+ 8001c24:	f883 203b 	strb.w	r2, [r3, #59]	@ 0x3b
+ 8001c28:	687b      	ldr	r3, [r7, #4]
+ 8001c2a:	2201      	movs	r2, #1
+ 8001c2c:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+ 8001c30:	687b      	ldr	r3, [r7, #4]
+ 8001c32:	2201      	movs	r2, #1
+ 8001c34:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 8001c38:	687b      	ldr	r3, [r7, #4]
+ 8001c3a:	2201      	movs	r2, #1
+ 8001c3c:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
+
+  return HAL_OK;
+ 8001c40:	2300      	movs	r3, #0
+}
+ 8001c42:	4618      	mov	r0, r3
+ 8001c44:	3708      	adds	r7, #8
+ 8001c46:	46bd      	mov	sp, r7
+ 8001c48:	bd80      	pop	{r7, pc}
+
+08001c4a <HAL_TIM_IRQHandler>:
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ 8001c4a:	b580      	push	{r7, lr}
+ 8001c4c:	b084      	sub	sp, #16
+ 8001c4e:	af00      	add	r7, sp, #0
+ 8001c50:	6078      	str	r0, [r7, #4]
+  uint32_t itsource = htim->Instance->DIER;
+ 8001c52:	687b      	ldr	r3, [r7, #4]
+ 8001c54:	681b      	ldr	r3, [r3, #0]
+ 8001c56:	68db      	ldr	r3, [r3, #12]
+ 8001c58:	60fb      	str	r3, [r7, #12]
+  uint32_t itflag   = htim->Instance->SR;
+ 8001c5a:	687b      	ldr	r3, [r7, #4]
+ 8001c5c:	681b      	ldr	r3, [r3, #0]
+ 8001c5e:	691b      	ldr	r3, [r3, #16]
+ 8001c60:	60bb      	str	r3, [r7, #8]
+
+  /* Capture compare 1 event */
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+ 8001c62:	68bb      	ldr	r3, [r7, #8]
+ 8001c64:	f003 0302 	and.w	r3, r3, #2
+ 8001c68:	2b00      	cmp	r3, #0
+ 8001c6a:	d020      	beq.n	8001cae <HAL_TIM_IRQHandler+0x64>
+  {
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+ 8001c6c:	68fb      	ldr	r3, [r7, #12]
+ 8001c6e:	f003 0302 	and.w	r3, r3, #2
+ 8001c72:	2b00      	cmp	r3, #0
+ 8001c74:	d01b      	beq.n	8001cae <HAL_TIM_IRQHandler+0x64>
+    {
+      {
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+ 8001c76:	687b      	ldr	r3, [r7, #4]
+ 8001c78:	681b      	ldr	r3, [r3, #0]
+ 8001c7a:	f06f 0202 	mvn.w	r2, #2
+ 8001c7e:	611a      	str	r2, [r3, #16]
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ 8001c80:	687b      	ldr	r3, [r7, #4]
+ 8001c82:	2201      	movs	r2, #1
+ 8001c84:	761a      	strb	r2, [r3, #24]
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ 8001c86:	687b      	ldr	r3, [r7, #4]
+ 8001c88:	681b      	ldr	r3, [r3, #0]
+ 8001c8a:	699b      	ldr	r3, [r3, #24]
+ 8001c8c:	f003 0303 	and.w	r3, r3, #3
+ 8001c90:	2b00      	cmp	r3, #0
+ 8001c92:	d003      	beq.n	8001c9c <HAL_TIM_IRQHandler+0x52>
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+ 8001c94:	6878      	ldr	r0, [r7, #4]
+ 8001c96:	f000 f8b6 	bl	8001e06 <HAL_TIM_IC_CaptureCallback>
+ 8001c9a:	e005      	b.n	8001ca8 <HAL_TIM_IRQHandler+0x5e>
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8001c9c:	6878      	ldr	r0, [r7, #4]
+ 8001c9e:	f000 f8a9 	bl	8001df4 <HAL_TIM_OC_DelayElapsedCallback>
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8001ca2:	6878      	ldr	r0, [r7, #4]
+ 8001ca4:	f000 f8b8 	bl	8001e18 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8001ca8:	687b      	ldr	r3, [r7, #4]
+ 8001caa:	2200      	movs	r2, #0
+ 8001cac:	761a      	strb	r2, [r3, #24]
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+ 8001cae:	68bb      	ldr	r3, [r7, #8]
+ 8001cb0:	f003 0304 	and.w	r3, r3, #4
+ 8001cb4:	2b00      	cmp	r3, #0
+ 8001cb6:	d020      	beq.n	8001cfa <HAL_TIM_IRQHandler+0xb0>
+  {
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+ 8001cb8:	68fb      	ldr	r3, [r7, #12]
+ 8001cba:	f003 0304 	and.w	r3, r3, #4
+ 8001cbe:	2b00      	cmp	r3, #0
+ 8001cc0:	d01b      	beq.n	8001cfa <HAL_TIM_IRQHandler+0xb0>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+ 8001cc2:	687b      	ldr	r3, [r7, #4]
+ 8001cc4:	681b      	ldr	r3, [r3, #0]
+ 8001cc6:	f06f 0204 	mvn.w	r2, #4
+ 8001cca:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ 8001ccc:	687b      	ldr	r3, [r7, #4]
+ 8001cce:	2202      	movs	r2, #2
+ 8001cd0:	761a      	strb	r2, [r3, #24]
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ 8001cd2:	687b      	ldr	r3, [r7, #4]
+ 8001cd4:	681b      	ldr	r3, [r3, #0]
+ 8001cd6:	699b      	ldr	r3, [r3, #24]
+ 8001cd8:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 8001cdc:	2b00      	cmp	r3, #0
+ 8001cde:	d003      	beq.n	8001ce8 <HAL_TIM_IRQHandler+0x9e>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8001ce0:	6878      	ldr	r0, [r7, #4]
+ 8001ce2:	f000 f890 	bl	8001e06 <HAL_TIM_IC_CaptureCallback>
+ 8001ce6:	e005      	b.n	8001cf4 <HAL_TIM_IRQHandler+0xaa>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8001ce8:	6878      	ldr	r0, [r7, #4]
+ 8001cea:	f000 f883 	bl	8001df4 <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8001cee:	6878      	ldr	r0, [r7, #4]
+ 8001cf0:	f000 f892 	bl	8001e18 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8001cf4:	687b      	ldr	r3, [r7, #4]
+ 8001cf6:	2200      	movs	r2, #0
+ 8001cf8:	761a      	strb	r2, [r3, #24]
+    }
+  }
+  /* Capture compare 3 event */
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+ 8001cfa:	68bb      	ldr	r3, [r7, #8]
+ 8001cfc:	f003 0308 	and.w	r3, r3, #8
+ 8001d00:	2b00      	cmp	r3, #0
+ 8001d02:	d020      	beq.n	8001d46 <HAL_TIM_IRQHandler+0xfc>
+  {
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+ 8001d04:	68fb      	ldr	r3, [r7, #12]
+ 8001d06:	f003 0308 	and.w	r3, r3, #8
+ 8001d0a:	2b00      	cmp	r3, #0
+ 8001d0c:	d01b      	beq.n	8001d46 <HAL_TIM_IRQHandler+0xfc>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+ 8001d0e:	687b      	ldr	r3, [r7, #4]
+ 8001d10:	681b      	ldr	r3, [r3, #0]
+ 8001d12:	f06f 0208 	mvn.w	r2, #8
+ 8001d16:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ 8001d18:	687b      	ldr	r3, [r7, #4]
+ 8001d1a:	2204      	movs	r2, #4
+ 8001d1c:	761a      	strb	r2, [r3, #24]
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ 8001d1e:	687b      	ldr	r3, [r7, #4]
+ 8001d20:	681b      	ldr	r3, [r3, #0]
+ 8001d22:	69db      	ldr	r3, [r3, #28]
+ 8001d24:	f003 0303 	and.w	r3, r3, #3
+ 8001d28:	2b00      	cmp	r3, #0
+ 8001d2a:	d003      	beq.n	8001d34 <HAL_TIM_IRQHandler+0xea>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8001d2c:	6878      	ldr	r0, [r7, #4]
+ 8001d2e:	f000 f86a 	bl	8001e06 <HAL_TIM_IC_CaptureCallback>
+ 8001d32:	e005      	b.n	8001d40 <HAL_TIM_IRQHandler+0xf6>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8001d34:	6878      	ldr	r0, [r7, #4]
+ 8001d36:	f000 f85d 	bl	8001df4 <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8001d3a:	6878      	ldr	r0, [r7, #4]
+ 8001d3c:	f000 f86c 	bl	8001e18 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8001d40:	687b      	ldr	r3, [r7, #4]
+ 8001d42:	2200      	movs	r2, #0
+ 8001d44:	761a      	strb	r2, [r3, #24]
+    }
+  }
+  /* Capture compare 4 event */
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+ 8001d46:	68bb      	ldr	r3, [r7, #8]
+ 8001d48:	f003 0310 	and.w	r3, r3, #16
+ 8001d4c:	2b00      	cmp	r3, #0
+ 8001d4e:	d020      	beq.n	8001d92 <HAL_TIM_IRQHandler+0x148>
+  {
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+ 8001d50:	68fb      	ldr	r3, [r7, #12]
+ 8001d52:	f003 0310 	and.w	r3, r3, #16
+ 8001d56:	2b00      	cmp	r3, #0
+ 8001d58:	d01b      	beq.n	8001d92 <HAL_TIM_IRQHandler+0x148>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+ 8001d5a:	687b      	ldr	r3, [r7, #4]
+ 8001d5c:	681b      	ldr	r3, [r3, #0]
+ 8001d5e:	f06f 0210 	mvn.w	r2, #16
+ 8001d62:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ 8001d64:	687b      	ldr	r3, [r7, #4]
+ 8001d66:	2208      	movs	r2, #8
+ 8001d68:	761a      	strb	r2, [r3, #24]
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ 8001d6a:	687b      	ldr	r3, [r7, #4]
+ 8001d6c:	681b      	ldr	r3, [r3, #0]
+ 8001d6e:	69db      	ldr	r3, [r3, #28]
+ 8001d70:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 8001d74:	2b00      	cmp	r3, #0
+ 8001d76:	d003      	beq.n	8001d80 <HAL_TIM_IRQHandler+0x136>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8001d78:	6878      	ldr	r0, [r7, #4]
+ 8001d7a:	f000 f844 	bl	8001e06 <HAL_TIM_IC_CaptureCallback>
+ 8001d7e:	e005      	b.n	8001d8c <HAL_TIM_IRQHandler+0x142>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8001d80:	6878      	ldr	r0, [r7, #4]
+ 8001d82:	f000 f837 	bl	8001df4 <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8001d86:	6878      	ldr	r0, [r7, #4]
+ 8001d88:	f000 f846 	bl	8001e18 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8001d8c:	687b      	ldr	r3, [r7, #4]
+ 8001d8e:	2200      	movs	r2, #0
+ 8001d90:	761a      	strb	r2, [r3, #24]
+    }
+  }
+  /* TIM Update event */
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+ 8001d92:	68bb      	ldr	r3, [r7, #8]
+ 8001d94:	f003 0301 	and.w	r3, r3, #1
+ 8001d98:	2b00      	cmp	r3, #0
+ 8001d9a:	d00c      	beq.n	8001db6 <HAL_TIM_IRQHandler+0x16c>
+  {
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+ 8001d9c:	68fb      	ldr	r3, [r7, #12]
+ 8001d9e:	f003 0301 	and.w	r3, r3, #1
+ 8001da2:	2b00      	cmp	r3, #0
+ 8001da4:	d007      	beq.n	8001db6 <HAL_TIM_IRQHandler+0x16c>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+ 8001da6:	687b      	ldr	r3, [r7, #4]
+ 8001da8:	681b      	ldr	r3, [r3, #0]
+ 8001daa:	f06f 0201 	mvn.w	r2, #1
+ 8001dae:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+ 8001db0:	6878      	ldr	r0, [r7, #4]
+ 8001db2:	f000 f816 	bl	8001de2 <HAL_TIM_PeriodElapsedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+ 8001db6:	68bb      	ldr	r3, [r7, #8]
+ 8001db8:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8001dbc:	2b00      	cmp	r3, #0
+ 8001dbe:	d00c      	beq.n	8001dda <HAL_TIM_IRQHandler+0x190>
+  {
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+ 8001dc0:	68fb      	ldr	r3, [r7, #12]
+ 8001dc2:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8001dc6:	2b00      	cmp	r3, #0
+ 8001dc8:	d007      	beq.n	8001dda <HAL_TIM_IRQHandler+0x190>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+ 8001dca:	687b      	ldr	r3, [r7, #4]
+ 8001dcc:	681b      	ldr	r3, [r3, #0]
+ 8001dce:	f06f 0240 	mvn.w	r2, #64	@ 0x40
+ 8001dd2:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+ 8001dd4:	6878      	ldr	r0, [r7, #4]
+ 8001dd6:	f000 f828 	bl	8001e2a <HAL_TIM_TriggerCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+ 8001dda:	bf00      	nop
+ 8001ddc:	3710      	adds	r7, #16
+ 8001dde:	46bd      	mov	sp, r7
+ 8001de0:	bd80      	pop	{r7, pc}
+
+08001de2 <HAL_TIM_PeriodElapsedCallback>:
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ 8001de2:	b480      	push	{r7}
+ 8001de4:	b083      	sub	sp, #12
+ 8001de6:	af00      	add	r7, sp, #0
+ 8001de8:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+ 8001dea:	bf00      	nop
+ 8001dec:	370c      	adds	r7, #12
+ 8001dee:	46bd      	mov	sp, r7
+ 8001df0:	bc80      	pop	{r7}
+ 8001df2:	4770      	bx	lr
+
+08001df4 <HAL_TIM_OC_DelayElapsedCallback>:
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ 8001df4:	b480      	push	{r7}
+ 8001df6:	b083      	sub	sp, #12
+ 8001df8:	af00      	add	r7, sp, #0
+ 8001dfa:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+ 8001dfc:	bf00      	nop
+ 8001dfe:	370c      	adds	r7, #12
+ 8001e00:	46bd      	mov	sp, r7
+ 8001e02:	bc80      	pop	{r7}
+ 8001e04:	4770      	bx	lr
+
+08001e06 <HAL_TIM_IC_CaptureCallback>:
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ 8001e06:	b480      	push	{r7}
+ 8001e08:	b083      	sub	sp, #12
+ 8001e0a:	af00      	add	r7, sp, #0
+ 8001e0c:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+ 8001e0e:	bf00      	nop
+ 8001e10:	370c      	adds	r7, #12
+ 8001e12:	46bd      	mov	sp, r7
+ 8001e14:	bc80      	pop	{r7}
+ 8001e16:	4770      	bx	lr
+
+08001e18 <HAL_TIM_PWM_PulseFinishedCallback>:
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ 8001e18:	b480      	push	{r7}
+ 8001e1a:	b083      	sub	sp, #12
+ 8001e1c:	af00      	add	r7, sp, #0
+ 8001e1e:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+ 8001e20:	bf00      	nop
+ 8001e22:	370c      	adds	r7, #12
+ 8001e24:	46bd      	mov	sp, r7
+ 8001e26:	bc80      	pop	{r7}
+ 8001e28:	4770      	bx	lr
+
+08001e2a <HAL_TIM_TriggerCallback>:
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ 8001e2a:	b480      	push	{r7}
+ 8001e2c:	b083      	sub	sp, #12
+ 8001e2e:	af00      	add	r7, sp, #0
+ 8001e30:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+ 8001e32:	bf00      	nop
+ 8001e34:	370c      	adds	r7, #12
+ 8001e36:	46bd      	mov	sp, r7
+ 8001e38:	bc80      	pop	{r7}
+ 8001e3a:	4770      	bx	lr
+
+08001e3c <TIM_Base_SetConfig>:
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+ 8001e3c:	b480      	push	{r7}
+ 8001e3e:	b085      	sub	sp, #20
+ 8001e40:	af00      	add	r7, sp, #0
+ 8001e42:	6078      	str	r0, [r7, #4]
+ 8001e44:	6039      	str	r1, [r7, #0]
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+ 8001e46:	687b      	ldr	r3, [r7, #4]
+ 8001e48:	681b      	ldr	r3, [r3, #0]
+ 8001e4a:	60fb      	str	r3, [r7, #12]
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 8001e4c:	687b      	ldr	r3, [r7, #4]
+ 8001e4e:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 8001e52:	d00f      	beq.n	8001e74 <TIM_Base_SetConfig+0x38>
+ 8001e54:	687b      	ldr	r3, [r7, #4]
+ 8001e56:	4a2e      	ldr	r2, [pc, #184]	@ (8001f10 <TIM_Base_SetConfig+0xd4>)
+ 8001e58:	4293      	cmp	r3, r2
+ 8001e5a:	d00b      	beq.n	8001e74 <TIM_Base_SetConfig+0x38>
+ 8001e5c:	687b      	ldr	r3, [r7, #4]
+ 8001e5e:	4a2d      	ldr	r2, [pc, #180]	@ (8001f14 <TIM_Base_SetConfig+0xd8>)
+ 8001e60:	4293      	cmp	r3, r2
+ 8001e62:	d007      	beq.n	8001e74 <TIM_Base_SetConfig+0x38>
+ 8001e64:	687b      	ldr	r3, [r7, #4]
+ 8001e66:	4a2c      	ldr	r2, [pc, #176]	@ (8001f18 <TIM_Base_SetConfig+0xdc>)
+ 8001e68:	4293      	cmp	r3, r2
+ 8001e6a:	d003      	beq.n	8001e74 <TIM_Base_SetConfig+0x38>
+ 8001e6c:	687b      	ldr	r3, [r7, #4]
+ 8001e6e:	4a2b      	ldr	r2, [pc, #172]	@ (8001f1c <TIM_Base_SetConfig+0xe0>)
+ 8001e70:	4293      	cmp	r3, r2
+ 8001e72:	d108      	bne.n	8001e86 <TIM_Base_SetConfig+0x4a>
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 8001e74:	68fb      	ldr	r3, [r7, #12]
+ 8001e76:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
+ 8001e7a:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= Structure->CounterMode;
+ 8001e7c:	683b      	ldr	r3, [r7, #0]
+ 8001e7e:	685b      	ldr	r3, [r3, #4]
+ 8001e80:	68fa      	ldr	r2, [r7, #12]
+ 8001e82:	4313      	orrs	r3, r2
+ 8001e84:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 8001e86:	687b      	ldr	r3, [r7, #4]
+ 8001e88:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 8001e8c:	d017      	beq.n	8001ebe <TIM_Base_SetConfig+0x82>
+ 8001e8e:	687b      	ldr	r3, [r7, #4]
+ 8001e90:	4a1f      	ldr	r2, [pc, #124]	@ (8001f10 <TIM_Base_SetConfig+0xd4>)
+ 8001e92:	4293      	cmp	r3, r2
+ 8001e94:	d013      	beq.n	8001ebe <TIM_Base_SetConfig+0x82>
+ 8001e96:	687b      	ldr	r3, [r7, #4]
+ 8001e98:	4a1e      	ldr	r2, [pc, #120]	@ (8001f14 <TIM_Base_SetConfig+0xd8>)
+ 8001e9a:	4293      	cmp	r3, r2
+ 8001e9c:	d00f      	beq.n	8001ebe <TIM_Base_SetConfig+0x82>
+ 8001e9e:	687b      	ldr	r3, [r7, #4]
+ 8001ea0:	4a1d      	ldr	r2, [pc, #116]	@ (8001f18 <TIM_Base_SetConfig+0xdc>)
+ 8001ea2:	4293      	cmp	r3, r2
+ 8001ea4:	d00b      	beq.n	8001ebe <TIM_Base_SetConfig+0x82>
+ 8001ea6:	687b      	ldr	r3, [r7, #4]
+ 8001ea8:	4a1c      	ldr	r2, [pc, #112]	@ (8001f1c <TIM_Base_SetConfig+0xe0>)
+ 8001eaa:	4293      	cmp	r3, r2
+ 8001eac:	d007      	beq.n	8001ebe <TIM_Base_SetConfig+0x82>
+ 8001eae:	687b      	ldr	r3, [r7, #4]
+ 8001eb0:	4a1b      	ldr	r2, [pc, #108]	@ (8001f20 <TIM_Base_SetConfig+0xe4>)
+ 8001eb2:	4293      	cmp	r3, r2
+ 8001eb4:	d003      	beq.n	8001ebe <TIM_Base_SetConfig+0x82>
+ 8001eb6:	687b      	ldr	r3, [r7, #4]
+ 8001eb8:	4a1a      	ldr	r2, [pc, #104]	@ (8001f24 <TIM_Base_SetConfig+0xe8>)
+ 8001eba:	4293      	cmp	r3, r2
+ 8001ebc:	d108      	bne.n	8001ed0 <TIM_Base_SetConfig+0x94>
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+ 8001ebe:	68fb      	ldr	r3, [r7, #12]
+ 8001ec0:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
+ 8001ec4:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 8001ec6:	683b      	ldr	r3, [r7, #0]
+ 8001ec8:	68db      	ldr	r3, [r3, #12]
+ 8001eca:	68fa      	ldr	r2, [r7, #12]
+ 8001ecc:	4313      	orrs	r3, r2
+ 8001ece:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 8001ed0:	68fb      	ldr	r3, [r7, #12]
+ 8001ed2:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
+ 8001ed6:	683b      	ldr	r3, [r7, #0]
+ 8001ed8:	691b      	ldr	r3, [r3, #16]
+ 8001eda:	4313      	orrs	r3, r2
+ 8001edc:	60fb      	str	r3, [r7, #12]
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+ 8001ede:	683b      	ldr	r3, [r7, #0]
+ 8001ee0:	689a      	ldr	r2, [r3, #8]
+ 8001ee2:	687b      	ldr	r3, [r7, #4]
+ 8001ee4:	62da      	str	r2, [r3, #44]	@ 0x2c
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+ 8001ee6:	683b      	ldr	r3, [r7, #0]
+ 8001ee8:	681a      	ldr	r2, [r3, #0]
+ 8001eea:	687b      	ldr	r3, [r7, #4]
+ 8001eec:	629a      	str	r2, [r3, #40]	@ 0x28
+
+  /* Disable Update Event (UEV) with Update Generation (UG)
+     by changing Update Request Source (URS) to avoid Update flag (UIF) */
+  SET_BIT(TIMx->CR1, TIM_CR1_URS);
+ 8001eee:	687b      	ldr	r3, [r7, #4]
+ 8001ef0:	681b      	ldr	r3, [r3, #0]
+ 8001ef2:	f043 0204 	orr.w	r2, r3, #4
+ 8001ef6:	687b      	ldr	r3, [r7, #4]
+ 8001ef8:	601a      	str	r2, [r3, #0]
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+ 8001efa:	687b      	ldr	r3, [r7, #4]
+ 8001efc:	2201      	movs	r2, #1
+ 8001efe:	615a      	str	r2, [r3, #20]
+
+  TIMx->CR1 = tmpcr1;
+ 8001f00:	687b      	ldr	r3, [r7, #4]
+ 8001f02:	68fa      	ldr	r2, [r7, #12]
+ 8001f04:	601a      	str	r2, [r3, #0]
+}
+ 8001f06:	bf00      	nop
+ 8001f08:	3714      	adds	r7, #20
+ 8001f0a:	46bd      	mov	sp, r7
+ 8001f0c:	bc80      	pop	{r7}
+ 8001f0e:	4770      	bx	lr
+ 8001f10:	40000400 	.word	0x40000400
+ 8001f14:	40000800 	.word	0x40000800
+ 8001f18:	40000c00 	.word	0x40000c00
+ 8001f1c:	40010800 	.word	0x40010800
+ 8001f20:	40010c00 	.word	0x40010c00
+ 8001f24:	40011000 	.word	0x40011000
+
+08001f28 <HAL_TIMEx_MasterConfigSynchronization>:
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ 8001f28:	b480      	push	{r7}
+ 8001f2a:	b085      	sub	sp, #20
+ 8001f2c:	af00      	add	r7, sp, #0
+ 8001f2e:	6078      	str	r0, [r7, #4]
+ 8001f30:	6039      	str	r1, [r7, #0]
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+ 8001f32:	687b      	ldr	r3, [r7, #4]
+ 8001f34:	f893 3038 	ldrb.w	r3, [r3, #56]	@ 0x38
+ 8001f38:	2b01      	cmp	r3, #1
+ 8001f3a:	d101      	bne.n	8001f40 <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 8001f3c:	2302      	movs	r3, #2
+ 8001f3e:	e046      	b.n	8001fce <HAL_TIMEx_MasterConfigSynchronization+0xa6>
+ 8001f40:	687b      	ldr	r3, [r7, #4]
+ 8001f42:	2201      	movs	r2, #1
+ 8001f44:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8001f48:	687b      	ldr	r3, [r7, #4]
+ 8001f4a:	2202      	movs	r2, #2
+ 8001f4c:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+ 8001f50:	687b      	ldr	r3, [r7, #4]
+ 8001f52:	681b      	ldr	r3, [r3, #0]
+ 8001f54:	685b      	ldr	r3, [r3, #4]
+ 8001f56:	60fb      	str	r3, [r7, #12]
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+ 8001f58:	687b      	ldr	r3, [r7, #4]
+ 8001f5a:	681b      	ldr	r3, [r3, #0]
+ 8001f5c:	689b      	ldr	r3, [r3, #8]
+ 8001f5e:	60bb      	str	r3, [r7, #8]
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+ 8001f60:	68fb      	ldr	r3, [r7, #12]
+ 8001f62:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
+ 8001f66:	60fb      	str	r3, [r7, #12]
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+ 8001f68:	683b      	ldr	r3, [r7, #0]
+ 8001f6a:	681b      	ldr	r3, [r3, #0]
+ 8001f6c:	68fa      	ldr	r2, [r7, #12]
+ 8001f6e:	4313      	orrs	r3, r2
+ 8001f70:	60fb      	str	r3, [r7, #12]
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+ 8001f72:	687b      	ldr	r3, [r7, #4]
+ 8001f74:	681b      	ldr	r3, [r3, #0]
+ 8001f76:	68fa      	ldr	r2, [r7, #12]
+ 8001f78:	605a      	str	r2, [r3, #4]
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 8001f7a:	687b      	ldr	r3, [r7, #4]
+ 8001f7c:	681b      	ldr	r3, [r3, #0]
+ 8001f7e:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 8001f82:	d00e      	beq.n	8001fa2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
+ 8001f84:	687b      	ldr	r3, [r7, #4]
+ 8001f86:	681b      	ldr	r3, [r3, #0]
+ 8001f88:	4a13      	ldr	r2, [pc, #76]	@ (8001fd8 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
+ 8001f8a:	4293      	cmp	r3, r2
+ 8001f8c:	d009      	beq.n	8001fa2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
+ 8001f8e:	687b      	ldr	r3, [r7, #4]
+ 8001f90:	681b      	ldr	r3, [r3, #0]
+ 8001f92:	4a12      	ldr	r2, [pc, #72]	@ (8001fdc <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
+ 8001f94:	4293      	cmp	r3, r2
+ 8001f96:	d004      	beq.n	8001fa2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
+ 8001f98:	687b      	ldr	r3, [r7, #4]
+ 8001f9a:	681b      	ldr	r3, [r3, #0]
+ 8001f9c:	4a10      	ldr	r2, [pc, #64]	@ (8001fe0 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
+ 8001f9e:	4293      	cmp	r3, r2
+ 8001fa0:	d10c      	bne.n	8001fbc <HAL_TIMEx_MasterConfigSynchronization+0x94>
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+ 8001fa2:	68bb      	ldr	r3, [r7, #8]
+ 8001fa4:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
+ 8001fa8:	60bb      	str	r3, [r7, #8]
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+ 8001faa:	683b      	ldr	r3, [r7, #0]
+ 8001fac:	685b      	ldr	r3, [r3, #4]
+ 8001fae:	68ba      	ldr	r2, [r7, #8]
+ 8001fb0:	4313      	orrs	r3, r2
+ 8001fb2:	60bb      	str	r3, [r7, #8]
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+ 8001fb4:	687b      	ldr	r3, [r7, #4]
+ 8001fb6:	681b      	ldr	r3, [r3, #0]
+ 8001fb8:	68ba      	ldr	r2, [r7, #8]
+ 8001fba:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+ 8001fbc:	687b      	ldr	r3, [r7, #4]
+ 8001fbe:	2201      	movs	r2, #1
+ 8001fc0:	f883 2039 	strb.w	r2, [r3, #57]	@ 0x39
+
+  __HAL_UNLOCK(htim);
+ 8001fc4:	687b      	ldr	r3, [r7, #4]
+ 8001fc6:	2200      	movs	r2, #0
+ 8001fc8:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
+
+  return HAL_OK;
+ 8001fcc:	2300      	movs	r3, #0
+}
+ 8001fce:	4618      	mov	r0, r3
+ 8001fd0:	3714      	adds	r7, #20
+ 8001fd2:	46bd      	mov	sp, r7
+ 8001fd4:	bc80      	pop	{r7}
+ 8001fd6:	4770      	bx	lr
+ 8001fd8:	40000400 	.word	0x40000400
+ 8001fdc:	40000800 	.word	0x40000800
+ 8001fe0:	40010800 	.word	0x40010800
+
+08001fe4 <HAL_UART_Init>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
 {
- 8001ae0:	b580      	push	{r7, lr}
- 8001ae2:	b082      	sub	sp, #8
- 8001ae4:	af00      	add	r7, sp, #0
- 8001ae6:	6078      	str	r0, [r7, #4]
+ 8001fe4:	b580      	push	{r7, lr}
+ 8001fe6:	b082      	sub	sp, #8
+ 8001fe8:	af00      	add	r7, sp, #0
+ 8001fea:	6078      	str	r0, [r7, #4]
   /* Check the UART handle allocation */
   if (huart == NULL)
- 8001ae8:	687b      	ldr	r3, [r7, #4]
- 8001aea:	2b00      	cmp	r3, #0
- 8001aec:	d101      	bne.n	8001af2 <HAL_UART_Init+0x12>
+ 8001fec:	687b      	ldr	r3, [r7, #4]
+ 8001fee:	2b00      	cmp	r3, #0
+ 8001ff0:	d101      	bne.n	8001ff6 <HAL_UART_Init+0x12>
   {
     return HAL_ERROR;
- 8001aee:	2301      	movs	r3, #1
- 8001af0:	e042      	b.n	8001b78 <HAL_UART_Init+0x98>
+ 8001ff2:	2301      	movs	r3, #1
+ 8001ff4:	e042      	b.n	800207c <HAL_UART_Init+0x98>
     assert_param(IS_UART_INSTANCE(huart->Instance));
   }
   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
 
   if (huart->gState == HAL_UART_STATE_RESET)
- 8001af2:	687b      	ldr	r3, [r7, #4]
- 8001af4:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
- 8001af8:	b2db      	uxtb	r3, r3
- 8001afa:	2b00      	cmp	r3, #0
- 8001afc:	d106      	bne.n	8001b0c <HAL_UART_Init+0x2c>
+ 8001ff6:	687b      	ldr	r3, [r7, #4]
+ 8001ff8:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8001ffc:	b2db      	uxtb	r3, r3
+ 8001ffe:	2b00      	cmp	r3, #0
+ 8002000:	d106      	bne.n	8002010 <HAL_UART_Init+0x2c>
   {
     /* Allocate lock resource and initialize it */
     huart->Lock = HAL_UNLOCKED;
- 8001afe:	687b      	ldr	r3, [r7, #4]
- 8001b00:	2200      	movs	r2, #0
- 8001b02:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+ 8002002:	687b      	ldr	r3, [r7, #4]
+ 8002004:	2200      	movs	r2, #0
+ 8002006:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
 
     /* Init the low level hardware */
     huart->MspInitCallback(huart);
 #else
     /* Init the low level hardware : GPIO, CLOCK */
     HAL_UART_MspInit(huart);
- 8001b06:	6878      	ldr	r0, [r7, #4]
- 8001b08:	f7fe fe14 	bl	8000734 <HAL_UART_MspInit>
+ 800200a:	6878      	ldr	r0, [r7, #4]
+ 800200c:	f7fe fbf6 	bl	80007fc <HAL_UART_MspInit>
 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
   }
 
   huart->gState = HAL_UART_STATE_BUSY;
- 8001b0c:	687b      	ldr	r3, [r7, #4]
- 8001b0e:	2224      	movs	r2, #36	@ 0x24
- 8001b10:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8002010:	687b      	ldr	r3, [r7, #4]
+ 8002012:	2224      	movs	r2, #36	@ 0x24
+ 8002014:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
 
   /* Disable the peripheral */
   __HAL_UART_DISABLE(huart);
- 8001b14:	687b      	ldr	r3, [r7, #4]
- 8001b16:	681b      	ldr	r3, [r3, #0]
- 8001b18:	68da      	ldr	r2, [r3, #12]
- 8001b1a:	687b      	ldr	r3, [r7, #4]
- 8001b1c:	681b      	ldr	r3, [r3, #0]
- 8001b1e:	f422 5200 	bic.w	r2, r2, #8192	@ 0x2000
- 8001b22:	60da      	str	r2, [r3, #12]
+ 8002018:	687b      	ldr	r3, [r7, #4]
+ 800201a:	681b      	ldr	r3, [r3, #0]
+ 800201c:	68da      	ldr	r2, [r3, #12]
+ 800201e:	687b      	ldr	r3, [r7, #4]
+ 8002020:	681b      	ldr	r3, [r3, #0]
+ 8002022:	f422 5200 	bic.w	r2, r2, #8192	@ 0x2000
+ 8002026:	60da      	str	r2, [r3, #12]
 
   /* Set the UART Communication parameters */
   UART_SetConfig(huart);
- 8001b24:	6878      	ldr	r0, [r7, #4]
- 8001b26:	f000 f82b 	bl	8001b80 <UART_SetConfig>
+ 8002028:	6878      	ldr	r0, [r7, #4]
+ 800202a:	f000 f82b 	bl	8002084 <UART_SetConfig>
 
   /* In asynchronous mode, the following bits must be kept cleared:
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8001b2a:	687b      	ldr	r3, [r7, #4]
- 8001b2c:	681b      	ldr	r3, [r3, #0]
- 8001b2e:	691a      	ldr	r2, [r3, #16]
- 8001b30:	687b      	ldr	r3, [r7, #4]
- 8001b32:	681b      	ldr	r3, [r3, #0]
- 8001b34:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
- 8001b38:	611a      	str	r2, [r3, #16]
+ 800202e:	687b      	ldr	r3, [r7, #4]
+ 8002030:	681b      	ldr	r3, [r3, #0]
+ 8002032:	691a      	ldr	r2, [r3, #16]
+ 8002034:	687b      	ldr	r3, [r7, #4]
+ 8002036:	681b      	ldr	r3, [r3, #0]
+ 8002038:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
+ 800203c:	611a      	str	r2, [r3, #16]
   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8001b3a:	687b      	ldr	r3, [r7, #4]
- 8001b3c:	681b      	ldr	r3, [r3, #0]
- 8001b3e:	695a      	ldr	r2, [r3, #20]
- 8001b40:	687b      	ldr	r3, [r7, #4]
- 8001b42:	681b      	ldr	r3, [r3, #0]
- 8001b44:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
- 8001b48:	615a      	str	r2, [r3, #20]
+ 800203e:	687b      	ldr	r3, [r7, #4]
+ 8002040:	681b      	ldr	r3, [r3, #0]
+ 8002042:	695a      	ldr	r2, [r3, #20]
+ 8002044:	687b      	ldr	r3, [r7, #4]
+ 8002046:	681b      	ldr	r3, [r3, #0]
+ 8002048:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
+ 800204c:	615a      	str	r2, [r3, #20]
 
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
- 8001b4a:	687b      	ldr	r3, [r7, #4]
- 8001b4c:	681b      	ldr	r3, [r3, #0]
- 8001b4e:	68da      	ldr	r2, [r3, #12]
- 8001b50:	687b      	ldr	r3, [r7, #4]
- 8001b52:	681b      	ldr	r3, [r3, #0]
- 8001b54:	f442 5200 	orr.w	r2, r2, #8192	@ 0x2000
- 8001b58:	60da      	str	r2, [r3, #12]
+ 800204e:	687b      	ldr	r3, [r7, #4]
+ 8002050:	681b      	ldr	r3, [r3, #0]
+ 8002052:	68da      	ldr	r2, [r3, #12]
+ 8002054:	687b      	ldr	r3, [r7, #4]
+ 8002056:	681b      	ldr	r3, [r3, #0]
+ 8002058:	f442 5200 	orr.w	r2, r2, #8192	@ 0x2000
+ 800205c:	60da      	str	r2, [r3, #12]
 
   /* Initialize the UART state */
   huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8001b5a:	687b      	ldr	r3, [r7, #4]
- 8001b5c:	2200      	movs	r2, #0
- 8001b5e:	645a      	str	r2, [r3, #68]	@ 0x44
+ 800205e:	687b      	ldr	r3, [r7, #4]
+ 8002060:	2200      	movs	r2, #0
+ 8002062:	645a      	str	r2, [r3, #68]	@ 0x44
   huart->gState = HAL_UART_STATE_READY;
- 8001b60:	687b      	ldr	r3, [r7, #4]
- 8001b62:	2220      	movs	r2, #32
- 8001b64:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 8002064:	687b      	ldr	r3, [r7, #4]
+ 8002066:	2220      	movs	r2, #32
+ 8002068:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
   huart->RxState = HAL_UART_STATE_READY;
- 8001b68:	687b      	ldr	r3, [r7, #4]
- 8001b6a:	2220      	movs	r2, #32
- 8001b6c:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 800206c:	687b      	ldr	r3, [r7, #4]
+ 800206e:	2220      	movs	r2, #32
+ 8002070:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
   huart->RxEventType = HAL_UART_RXEVENT_TC;
- 8001b70:	687b      	ldr	r3, [r7, #4]
- 8001b72:	2200      	movs	r2, #0
- 8001b74:	635a      	str	r2, [r3, #52]	@ 0x34
+ 8002074:	687b      	ldr	r3, [r7, #4]
+ 8002076:	2200      	movs	r2, #0
+ 8002078:	635a      	str	r2, [r3, #52]	@ 0x34
 
   return HAL_OK;
- 8001b76:	2300      	movs	r3, #0
+ 800207a:	2300      	movs	r3, #0
 }
- 8001b78:	4618      	mov	r0, r3
- 8001b7a:	3708      	adds	r7, #8
- 8001b7c:	46bd      	mov	sp, r7
- 8001b7e:	bd80      	pop	{r7, pc}
+ 800207c:	4618      	mov	r0, r3
+ 800207e:	3708      	adds	r7, #8
+ 8002080:	46bd      	mov	sp, r7
+ 8002082:	bd80      	pop	{r7, pc}
 
-08001b80 <UART_SetConfig>:
+08002084 <UART_SetConfig>:
   * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 static void UART_SetConfig(UART_HandleTypeDef *huart)
 {
- 8001b80:	b580      	push	{r7, lr}
- 8001b82:	b084      	sub	sp, #16
- 8001b84:	af00      	add	r7, sp, #0
- 8001b86:	6078      	str	r0, [r7, #4]
+ 8002084:	b580      	push	{r7, lr}
+ 8002086:	b084      	sub	sp, #16
+ 8002088:	af00      	add	r7, sp, #0
+ 800208a:	6078      	str	r0, [r7, #4]
   assert_param(IS_UART_MODE(huart->Init.Mode));
 
   /*-------------------------- USART CR2 Configuration -----------------------*/
   /* Configure the UART Stop Bits: Set STOP[13:12] bits
      according to huart->Init.StopBits value */
   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8001b88:	687b      	ldr	r3, [r7, #4]
- 8001b8a:	681b      	ldr	r3, [r3, #0]
- 8001b8c:	691b      	ldr	r3, [r3, #16]
- 8001b8e:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
- 8001b92:	687b      	ldr	r3, [r7, #4]
- 8001b94:	68da      	ldr	r2, [r3, #12]
- 8001b96:	687b      	ldr	r3, [r7, #4]
- 8001b98:	681b      	ldr	r3, [r3, #0]
- 8001b9a:	430a      	orrs	r2, r1
- 8001b9c:	611a      	str	r2, [r3, #16]
+ 800208c:	687b      	ldr	r3, [r7, #4]
+ 800208e:	681b      	ldr	r3, [r3, #0]
+ 8002090:	691b      	ldr	r3, [r3, #16]
+ 8002092:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
+ 8002096:	687b      	ldr	r3, [r7, #4]
+ 8002098:	68da      	ldr	r2, [r3, #12]
+ 800209a:	687b      	ldr	r3, [r7, #4]
+ 800209c:	681b      	ldr	r3, [r3, #0]
+ 800209e:	430a      	orrs	r2, r1
+ 80020a0:	611a      	str	r2, [r3, #16]
      Set the M bits according to huart->Init.WordLength value
      Set PCE and PS bits according to huart->Init.Parity value
      Set TE and RE bits according to huart->Init.Mode value
      Set OVER8 bit according to huart->Init.OverSampling value */
 
   tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
- 8001b9e:	687b      	ldr	r3, [r7, #4]
- 8001ba0:	689a      	ldr	r2, [r3, #8]
- 8001ba2:	687b      	ldr	r3, [r7, #4]
- 8001ba4:	691b      	ldr	r3, [r3, #16]
- 8001ba6:	431a      	orrs	r2, r3
- 8001ba8:	687b      	ldr	r3, [r7, #4]
- 8001baa:	695b      	ldr	r3, [r3, #20]
- 8001bac:	431a      	orrs	r2, r3
- 8001bae:	687b      	ldr	r3, [r7, #4]
- 8001bb0:	69db      	ldr	r3, [r3, #28]
- 8001bb2:	4313      	orrs	r3, r2
- 8001bb4:	60bb      	str	r3, [r7, #8]
+ 80020a2:	687b      	ldr	r3, [r7, #4]
+ 80020a4:	689a      	ldr	r2, [r3, #8]
+ 80020a6:	687b      	ldr	r3, [r7, #4]
+ 80020a8:	691b      	ldr	r3, [r3, #16]
+ 80020aa:	431a      	orrs	r2, r3
+ 80020ac:	687b      	ldr	r3, [r7, #4]
+ 80020ae:	695b      	ldr	r3, [r3, #20]
+ 80020b0:	431a      	orrs	r2, r3
+ 80020b2:	687b      	ldr	r3, [r7, #4]
+ 80020b4:	69db      	ldr	r3, [r3, #28]
+ 80020b6:	4313      	orrs	r3, r2
+ 80020b8:	60bb      	str	r3, [r7, #8]
   MODIFY_REG(huart->Instance->CR1,
- 8001bb6:	687b      	ldr	r3, [r7, #4]
- 8001bb8:	681b      	ldr	r3, [r3, #0]
- 8001bba:	68db      	ldr	r3, [r3, #12]
- 8001bbc:	f423 4316 	bic.w	r3, r3, #38400	@ 0x9600
- 8001bc0:	f023 030c 	bic.w	r3, r3, #12
- 8001bc4:	687a      	ldr	r2, [r7, #4]
- 8001bc6:	6812      	ldr	r2, [r2, #0]
- 8001bc8:	68b9      	ldr	r1, [r7, #8]
- 8001bca:	430b      	orrs	r3, r1
- 8001bcc:	60d3      	str	r3, [r2, #12]
+ 80020ba:	687b      	ldr	r3, [r7, #4]
+ 80020bc:	681b      	ldr	r3, [r3, #0]
+ 80020be:	68db      	ldr	r3, [r3, #12]
+ 80020c0:	f423 4316 	bic.w	r3, r3, #38400	@ 0x9600
+ 80020c4:	f023 030c 	bic.w	r3, r3, #12
+ 80020c8:	687a      	ldr	r2, [r7, #4]
+ 80020ca:	6812      	ldr	r2, [r2, #0]
+ 80020cc:	68b9      	ldr	r1, [r7, #8]
+ 80020ce:	430b      	orrs	r3, r1
+ 80020d0:	60d3      	str	r3, [r2, #12]
              (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
              tmpreg);
 
   /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
- 8001bce:	687b      	ldr	r3, [r7, #4]
- 8001bd0:	681b      	ldr	r3, [r3, #0]
- 8001bd2:	695b      	ldr	r3, [r3, #20]
- 8001bd4:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
- 8001bd8:	687b      	ldr	r3, [r7, #4]
- 8001bda:	699a      	ldr	r2, [r3, #24]
- 8001bdc:	687b      	ldr	r3, [r7, #4]
- 8001bde:	681b      	ldr	r3, [r3, #0]
- 8001be0:	430a      	orrs	r2, r1
- 8001be2:	615a      	str	r2, [r3, #20]
+ 80020d2:	687b      	ldr	r3, [r7, #4]
+ 80020d4:	681b      	ldr	r3, [r3, #0]
+ 80020d6:	695b      	ldr	r3, [r3, #20]
+ 80020d8:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
+ 80020dc:	687b      	ldr	r3, [r7, #4]
+ 80020de:	699a      	ldr	r2, [r3, #24]
+ 80020e0:	687b      	ldr	r3, [r7, #4]
+ 80020e2:	681b      	ldr	r3, [r3, #0]
+ 80020e4:	430a      	orrs	r2, r1
+ 80020e6:	615a      	str	r2, [r3, #20]
 
 
   if((huart->Instance == USART1))
- 8001be4:	687b      	ldr	r3, [r7, #4]
- 8001be6:	681b      	ldr	r3, [r3, #0]
- 8001be8:	4a55      	ldr	r2, [pc, #340]	@ (8001d40 <UART_SetConfig+0x1c0>)
- 8001bea:	4293      	cmp	r3, r2
- 8001bec:	d103      	bne.n	8001bf6 <UART_SetConfig+0x76>
+ 80020e8:	687b      	ldr	r3, [r7, #4]
+ 80020ea:	681b      	ldr	r3, [r3, #0]
+ 80020ec:	4a55      	ldr	r2, [pc, #340]	@ (8002244 <UART_SetConfig+0x1c0>)
+ 80020ee:	4293      	cmp	r3, r2
+ 80020f0:	d103      	bne.n	80020fa <UART_SetConfig+0x76>
   {
     pclk = HAL_RCC_GetPCLK2Freq();
- 8001bee:	f7ff ff03 	bl	80019f8 <HAL_RCC_GetPCLK2Freq>
- 8001bf2:	60f8      	str	r0, [r7, #12]
- 8001bf4:	e002      	b.n	8001bfc <UART_SetConfig+0x7c>
+ 80020f2:	f7ff fcf7 	bl	8001ae4 <HAL_RCC_GetPCLK2Freq>
+ 80020f6:	60f8      	str	r0, [r7, #12]
+ 80020f8:	e002      	b.n	8002100 <UART_SetConfig+0x7c>
   }
   else
   {
     pclk = HAL_RCC_GetPCLK1Freq();
- 8001bf6:	f7ff feeb 	bl	80019d0 <HAL_RCC_GetPCLK1Freq>
- 8001bfa:	60f8      	str	r0, [r7, #12]
+ 80020fa:	f7ff fcdf 	bl	8001abc <HAL_RCC_GetPCLK1Freq>
+ 80020fe:	60f8      	str	r0, [r7, #12]
   }
 
   /*-------------------------- USART BRR Configuration ---------------------*/
   if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8001bfc:	687b      	ldr	r3, [r7, #4]
- 8001bfe:	69db      	ldr	r3, [r3, #28]
- 8001c00:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
- 8001c04:	d14c      	bne.n	8001ca0 <UART_SetConfig+0x120>
+ 8002100:	687b      	ldr	r3, [r7, #4]
+ 8002102:	69db      	ldr	r3, [r3, #28]
+ 8002104:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
+ 8002108:	d14c      	bne.n	80021a4 <UART_SetConfig+0x120>
   {
     huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
- 8001c06:	68fa      	ldr	r2, [r7, #12]
- 8001c08:	4613      	mov	r3, r2
- 8001c0a:	009b      	lsls	r3, r3, #2
- 8001c0c:	4413      	add	r3, r2
- 8001c0e:	009a      	lsls	r2, r3, #2
- 8001c10:	441a      	add	r2, r3
- 8001c12:	687b      	ldr	r3, [r7, #4]
- 8001c14:	685b      	ldr	r3, [r3, #4]
- 8001c16:	005b      	lsls	r3, r3, #1
- 8001c18:	fbb2 f3f3 	udiv	r3, r2, r3
- 8001c1c:	4a49      	ldr	r2, [pc, #292]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001c1e:	fba2 2303 	umull	r2, r3, r2, r3
- 8001c22:	095b      	lsrs	r3, r3, #5
- 8001c24:	0119      	lsls	r1, r3, #4
- 8001c26:	68fa      	ldr	r2, [r7, #12]
- 8001c28:	4613      	mov	r3, r2
- 8001c2a:	009b      	lsls	r3, r3, #2
- 8001c2c:	4413      	add	r3, r2
- 8001c2e:	009a      	lsls	r2, r3, #2
- 8001c30:	441a      	add	r2, r3
- 8001c32:	687b      	ldr	r3, [r7, #4]
- 8001c34:	685b      	ldr	r3, [r3, #4]
- 8001c36:	005b      	lsls	r3, r3, #1
- 8001c38:	fbb2 f2f3 	udiv	r2, r2, r3
- 8001c3c:	4b41      	ldr	r3, [pc, #260]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001c3e:	fba3 0302 	umull	r0, r3, r3, r2
- 8001c42:	095b      	lsrs	r3, r3, #5
- 8001c44:	2064      	movs	r0, #100	@ 0x64
- 8001c46:	fb00 f303 	mul.w	r3, r0, r3
- 8001c4a:	1ad3      	subs	r3, r2, r3
- 8001c4c:	00db      	lsls	r3, r3, #3
- 8001c4e:	3332      	adds	r3, #50	@ 0x32
- 8001c50:	4a3c      	ldr	r2, [pc, #240]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001c52:	fba2 2303 	umull	r2, r3, r2, r3
- 8001c56:	095b      	lsrs	r3, r3, #5
- 8001c58:	005b      	lsls	r3, r3, #1
- 8001c5a:	f403 73f8 	and.w	r3, r3, #496	@ 0x1f0
- 8001c5e:	4419      	add	r1, r3
- 8001c60:	68fa      	ldr	r2, [r7, #12]
- 8001c62:	4613      	mov	r3, r2
- 8001c64:	009b      	lsls	r3, r3, #2
- 8001c66:	4413      	add	r3, r2
- 8001c68:	009a      	lsls	r2, r3, #2
- 8001c6a:	441a      	add	r2, r3
- 8001c6c:	687b      	ldr	r3, [r7, #4]
- 8001c6e:	685b      	ldr	r3, [r3, #4]
- 8001c70:	005b      	lsls	r3, r3, #1
- 8001c72:	fbb2 f2f3 	udiv	r2, r2, r3
- 8001c76:	4b33      	ldr	r3, [pc, #204]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001c78:	fba3 0302 	umull	r0, r3, r3, r2
- 8001c7c:	095b      	lsrs	r3, r3, #5
- 8001c7e:	2064      	movs	r0, #100	@ 0x64
- 8001c80:	fb00 f303 	mul.w	r3, r0, r3
- 8001c84:	1ad3      	subs	r3, r2, r3
- 8001c86:	00db      	lsls	r3, r3, #3
- 8001c88:	3332      	adds	r3, #50	@ 0x32
- 8001c8a:	4a2e      	ldr	r2, [pc, #184]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001c8c:	fba2 2303 	umull	r2, r3, r2, r3
- 8001c90:	095b      	lsrs	r3, r3, #5
- 8001c92:	f003 0207 	and.w	r2, r3, #7
- 8001c96:	687b      	ldr	r3, [r7, #4]
- 8001c98:	681b      	ldr	r3, [r3, #0]
- 8001c9a:	440a      	add	r2, r1
- 8001c9c:	609a      	str	r2, [r3, #8]
+ 800210a:	68fa      	ldr	r2, [r7, #12]
+ 800210c:	4613      	mov	r3, r2
+ 800210e:	009b      	lsls	r3, r3, #2
+ 8002110:	4413      	add	r3, r2
+ 8002112:	009a      	lsls	r2, r3, #2
+ 8002114:	441a      	add	r2, r3
+ 8002116:	687b      	ldr	r3, [r7, #4]
+ 8002118:	685b      	ldr	r3, [r3, #4]
+ 800211a:	005b      	lsls	r3, r3, #1
+ 800211c:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8002120:	4a49      	ldr	r2, [pc, #292]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 8002122:	fba2 2303 	umull	r2, r3, r2, r3
+ 8002126:	095b      	lsrs	r3, r3, #5
+ 8002128:	0119      	lsls	r1, r3, #4
+ 800212a:	68fa      	ldr	r2, [r7, #12]
+ 800212c:	4613      	mov	r3, r2
+ 800212e:	009b      	lsls	r3, r3, #2
+ 8002130:	4413      	add	r3, r2
+ 8002132:	009a      	lsls	r2, r3, #2
+ 8002134:	441a      	add	r2, r3
+ 8002136:	687b      	ldr	r3, [r7, #4]
+ 8002138:	685b      	ldr	r3, [r3, #4]
+ 800213a:	005b      	lsls	r3, r3, #1
+ 800213c:	fbb2 f2f3 	udiv	r2, r2, r3
+ 8002140:	4b41      	ldr	r3, [pc, #260]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 8002142:	fba3 0302 	umull	r0, r3, r3, r2
+ 8002146:	095b      	lsrs	r3, r3, #5
+ 8002148:	2064      	movs	r0, #100	@ 0x64
+ 800214a:	fb00 f303 	mul.w	r3, r0, r3
+ 800214e:	1ad3      	subs	r3, r2, r3
+ 8002150:	00db      	lsls	r3, r3, #3
+ 8002152:	3332      	adds	r3, #50	@ 0x32
+ 8002154:	4a3c      	ldr	r2, [pc, #240]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 8002156:	fba2 2303 	umull	r2, r3, r2, r3
+ 800215a:	095b      	lsrs	r3, r3, #5
+ 800215c:	005b      	lsls	r3, r3, #1
+ 800215e:	f403 73f8 	and.w	r3, r3, #496	@ 0x1f0
+ 8002162:	4419      	add	r1, r3
+ 8002164:	68fa      	ldr	r2, [r7, #12]
+ 8002166:	4613      	mov	r3, r2
+ 8002168:	009b      	lsls	r3, r3, #2
+ 800216a:	4413      	add	r3, r2
+ 800216c:	009a      	lsls	r2, r3, #2
+ 800216e:	441a      	add	r2, r3
+ 8002170:	687b      	ldr	r3, [r7, #4]
+ 8002172:	685b      	ldr	r3, [r3, #4]
+ 8002174:	005b      	lsls	r3, r3, #1
+ 8002176:	fbb2 f2f3 	udiv	r2, r2, r3
+ 800217a:	4b33      	ldr	r3, [pc, #204]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 800217c:	fba3 0302 	umull	r0, r3, r3, r2
+ 8002180:	095b      	lsrs	r3, r3, #5
+ 8002182:	2064      	movs	r0, #100	@ 0x64
+ 8002184:	fb00 f303 	mul.w	r3, r0, r3
+ 8002188:	1ad3      	subs	r3, r2, r3
+ 800218a:	00db      	lsls	r3, r3, #3
+ 800218c:	3332      	adds	r3, #50	@ 0x32
+ 800218e:	4a2e      	ldr	r2, [pc, #184]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 8002190:	fba2 2303 	umull	r2, r3, r2, r3
+ 8002194:	095b      	lsrs	r3, r3, #5
+ 8002196:	f003 0207 	and.w	r2, r3, #7
+ 800219a:	687b      	ldr	r3, [r7, #4]
+ 800219c:	681b      	ldr	r3, [r3, #0]
+ 800219e:	440a      	add	r2, r1
+ 80021a0:	609a      	str	r2, [r3, #8]
   }
   else
   {
     huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
   }
 }
- 8001c9e:	e04a      	b.n	8001d36 <UART_SetConfig+0x1b6>
+ 80021a2:	e04a      	b.n	800223a <UART_SetConfig+0x1b6>
     huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
- 8001ca0:	68fa      	ldr	r2, [r7, #12]
- 8001ca2:	4613      	mov	r3, r2
- 8001ca4:	009b      	lsls	r3, r3, #2
- 8001ca6:	4413      	add	r3, r2
- 8001ca8:	009a      	lsls	r2, r3, #2
- 8001caa:	441a      	add	r2, r3
- 8001cac:	687b      	ldr	r3, [r7, #4]
- 8001cae:	685b      	ldr	r3, [r3, #4]
- 8001cb0:	009b      	lsls	r3, r3, #2
- 8001cb2:	fbb2 f3f3 	udiv	r3, r2, r3
- 8001cb6:	4a23      	ldr	r2, [pc, #140]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001cb8:	fba2 2303 	umull	r2, r3, r2, r3
- 8001cbc:	095b      	lsrs	r3, r3, #5
- 8001cbe:	0119      	lsls	r1, r3, #4
- 8001cc0:	68fa      	ldr	r2, [r7, #12]
- 8001cc2:	4613      	mov	r3, r2
- 8001cc4:	009b      	lsls	r3, r3, #2
- 8001cc6:	4413      	add	r3, r2
- 8001cc8:	009a      	lsls	r2, r3, #2
- 8001cca:	441a      	add	r2, r3
- 8001ccc:	687b      	ldr	r3, [r7, #4]
- 8001cce:	685b      	ldr	r3, [r3, #4]
- 8001cd0:	009b      	lsls	r3, r3, #2
- 8001cd2:	fbb2 f2f3 	udiv	r2, r2, r3
- 8001cd6:	4b1b      	ldr	r3, [pc, #108]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001cd8:	fba3 0302 	umull	r0, r3, r3, r2
- 8001cdc:	095b      	lsrs	r3, r3, #5
- 8001cde:	2064      	movs	r0, #100	@ 0x64
- 8001ce0:	fb00 f303 	mul.w	r3, r0, r3
- 8001ce4:	1ad3      	subs	r3, r2, r3
- 8001ce6:	011b      	lsls	r3, r3, #4
- 8001ce8:	3332      	adds	r3, #50	@ 0x32
- 8001cea:	4a16      	ldr	r2, [pc, #88]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001cec:	fba2 2303 	umull	r2, r3, r2, r3
- 8001cf0:	095b      	lsrs	r3, r3, #5
- 8001cf2:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
- 8001cf6:	4419      	add	r1, r3
- 8001cf8:	68fa      	ldr	r2, [r7, #12]
- 8001cfa:	4613      	mov	r3, r2
- 8001cfc:	009b      	lsls	r3, r3, #2
- 8001cfe:	4413      	add	r3, r2
- 8001d00:	009a      	lsls	r2, r3, #2
- 8001d02:	441a      	add	r2, r3
- 8001d04:	687b      	ldr	r3, [r7, #4]
- 8001d06:	685b      	ldr	r3, [r3, #4]
- 8001d08:	009b      	lsls	r3, r3, #2
- 8001d0a:	fbb2 f2f3 	udiv	r2, r2, r3
- 8001d0e:	4b0d      	ldr	r3, [pc, #52]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001d10:	fba3 0302 	umull	r0, r3, r3, r2
- 8001d14:	095b      	lsrs	r3, r3, #5
- 8001d16:	2064      	movs	r0, #100	@ 0x64
- 8001d18:	fb00 f303 	mul.w	r3, r0, r3
- 8001d1c:	1ad3      	subs	r3, r2, r3
- 8001d1e:	011b      	lsls	r3, r3, #4
- 8001d20:	3332      	adds	r3, #50	@ 0x32
- 8001d22:	4a08      	ldr	r2, [pc, #32]	@ (8001d44 <UART_SetConfig+0x1c4>)
- 8001d24:	fba2 2303 	umull	r2, r3, r2, r3
- 8001d28:	095b      	lsrs	r3, r3, #5
- 8001d2a:	f003 020f 	and.w	r2, r3, #15
- 8001d2e:	687b      	ldr	r3, [r7, #4]
- 8001d30:	681b      	ldr	r3, [r3, #0]
- 8001d32:	440a      	add	r2, r1
- 8001d34:	609a      	str	r2, [r3, #8]
+ 80021a4:	68fa      	ldr	r2, [r7, #12]
+ 80021a6:	4613      	mov	r3, r2
+ 80021a8:	009b      	lsls	r3, r3, #2
+ 80021aa:	4413      	add	r3, r2
+ 80021ac:	009a      	lsls	r2, r3, #2
+ 80021ae:	441a      	add	r2, r3
+ 80021b0:	687b      	ldr	r3, [r7, #4]
+ 80021b2:	685b      	ldr	r3, [r3, #4]
+ 80021b4:	009b      	lsls	r3, r3, #2
+ 80021b6:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80021ba:	4a23      	ldr	r2, [pc, #140]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 80021bc:	fba2 2303 	umull	r2, r3, r2, r3
+ 80021c0:	095b      	lsrs	r3, r3, #5
+ 80021c2:	0119      	lsls	r1, r3, #4
+ 80021c4:	68fa      	ldr	r2, [r7, #12]
+ 80021c6:	4613      	mov	r3, r2
+ 80021c8:	009b      	lsls	r3, r3, #2
+ 80021ca:	4413      	add	r3, r2
+ 80021cc:	009a      	lsls	r2, r3, #2
+ 80021ce:	441a      	add	r2, r3
+ 80021d0:	687b      	ldr	r3, [r7, #4]
+ 80021d2:	685b      	ldr	r3, [r3, #4]
+ 80021d4:	009b      	lsls	r3, r3, #2
+ 80021d6:	fbb2 f2f3 	udiv	r2, r2, r3
+ 80021da:	4b1b      	ldr	r3, [pc, #108]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 80021dc:	fba3 0302 	umull	r0, r3, r3, r2
+ 80021e0:	095b      	lsrs	r3, r3, #5
+ 80021e2:	2064      	movs	r0, #100	@ 0x64
+ 80021e4:	fb00 f303 	mul.w	r3, r0, r3
+ 80021e8:	1ad3      	subs	r3, r2, r3
+ 80021ea:	011b      	lsls	r3, r3, #4
+ 80021ec:	3332      	adds	r3, #50	@ 0x32
+ 80021ee:	4a16      	ldr	r2, [pc, #88]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 80021f0:	fba2 2303 	umull	r2, r3, r2, r3
+ 80021f4:	095b      	lsrs	r3, r3, #5
+ 80021f6:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
+ 80021fa:	4419      	add	r1, r3
+ 80021fc:	68fa      	ldr	r2, [r7, #12]
+ 80021fe:	4613      	mov	r3, r2
+ 8002200:	009b      	lsls	r3, r3, #2
+ 8002202:	4413      	add	r3, r2
+ 8002204:	009a      	lsls	r2, r3, #2
+ 8002206:	441a      	add	r2, r3
+ 8002208:	687b      	ldr	r3, [r7, #4]
+ 800220a:	685b      	ldr	r3, [r3, #4]
+ 800220c:	009b      	lsls	r3, r3, #2
+ 800220e:	fbb2 f2f3 	udiv	r2, r2, r3
+ 8002212:	4b0d      	ldr	r3, [pc, #52]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 8002214:	fba3 0302 	umull	r0, r3, r3, r2
+ 8002218:	095b      	lsrs	r3, r3, #5
+ 800221a:	2064      	movs	r0, #100	@ 0x64
+ 800221c:	fb00 f303 	mul.w	r3, r0, r3
+ 8002220:	1ad3      	subs	r3, r2, r3
+ 8002222:	011b      	lsls	r3, r3, #4
+ 8002224:	3332      	adds	r3, #50	@ 0x32
+ 8002226:	4a08      	ldr	r2, [pc, #32]	@ (8002248 <UART_SetConfig+0x1c4>)
+ 8002228:	fba2 2303 	umull	r2, r3, r2, r3
+ 800222c:	095b      	lsrs	r3, r3, #5
+ 800222e:	f003 020f 	and.w	r2, r3, #15
+ 8002232:	687b      	ldr	r3, [r7, #4]
+ 8002234:	681b      	ldr	r3, [r3, #0]
+ 8002236:	440a      	add	r2, r1
+ 8002238:	609a      	str	r2, [r3, #8]
 }
- 8001d36:	bf00      	nop
- 8001d38:	3710      	adds	r7, #16
- 8001d3a:	46bd      	mov	sp, r7
- 8001d3c:	bd80      	pop	{r7, pc}
- 8001d3e:	bf00      	nop
- 8001d40:	40013800 	.word	0x40013800
- 8001d44:	51eb851f 	.word	0x51eb851f
+ 800223a:	bf00      	nop
+ 800223c:	3710      	adds	r7, #16
+ 800223e:	46bd      	mov	sp, r7
+ 8002240:	bd80      	pop	{r7, pc}
+ 8002242:	bf00      	nop
+ 8002244:	40013800 	.word	0x40013800
+ 8002248:	51eb851f 	.word	0x51eb851f
 
-08001d48 <memset>:
- 8001d48:	4603      	mov	r3, r0
- 8001d4a:	4402      	add	r2, r0
- 8001d4c:	4293      	cmp	r3, r2
- 8001d4e:	d100      	bne.n	8001d52 <memset+0xa>
- 8001d50:	4770      	bx	lr
- 8001d52:	f803 1b01 	strb.w	r1, [r3], #1
- 8001d56:	e7f9      	b.n	8001d4c <memset+0x4>
+0800224c <memset>:
+ 800224c:	4603      	mov	r3, r0
+ 800224e:	4402      	add	r2, r0
+ 8002250:	4293      	cmp	r3, r2
+ 8002252:	d100      	bne.n	8002256 <memset+0xa>
+ 8002254:	4770      	bx	lr
+ 8002256:	f803 1b01 	strb.w	r1, [r3], #1
+ 800225a:	e7f9      	b.n	8002250 <memset+0x4>
 
-08001d58 <__libc_init_array>:
- 8001d58:	b570      	push	{r4, r5, r6, lr}
- 8001d5a:	2600      	movs	r6, #0
- 8001d5c:	4d0c      	ldr	r5, [pc, #48]	@ (8001d90 <__libc_init_array+0x38>)
- 8001d5e:	4c0d      	ldr	r4, [pc, #52]	@ (8001d94 <__libc_init_array+0x3c>)
- 8001d60:	1b64      	subs	r4, r4, r5
- 8001d62:	10a4      	asrs	r4, r4, #2
- 8001d64:	42a6      	cmp	r6, r4
- 8001d66:	d109      	bne.n	8001d7c <__libc_init_array+0x24>
- 8001d68:	f000 f81a 	bl	8001da0 <_init>
- 8001d6c:	2600      	movs	r6, #0
- 8001d6e:	4d0a      	ldr	r5, [pc, #40]	@ (8001d98 <__libc_init_array+0x40>)
- 8001d70:	4c0a      	ldr	r4, [pc, #40]	@ (8001d9c <__libc_init_array+0x44>)
- 8001d72:	1b64      	subs	r4, r4, r5
- 8001d74:	10a4      	asrs	r4, r4, #2
- 8001d76:	42a6      	cmp	r6, r4
- 8001d78:	d105      	bne.n	8001d86 <__libc_init_array+0x2e>
- 8001d7a:	bd70      	pop	{r4, r5, r6, pc}
- 8001d7c:	f855 3b04 	ldr.w	r3, [r5], #4
- 8001d80:	4798      	blx	r3
- 8001d82:	3601      	adds	r6, #1
- 8001d84:	e7ee      	b.n	8001d64 <__libc_init_array+0xc>
- 8001d86:	f855 3b04 	ldr.w	r3, [r5], #4
- 8001d8a:	4798      	blx	r3
- 8001d8c:	3601      	adds	r6, #1
- 8001d8e:	e7f2      	b.n	8001d76 <__libc_init_array+0x1e>
- 8001d90:	08001de4 	.word	0x08001de4
- 8001d94:	08001de4 	.word	0x08001de4
- 8001d98:	08001de4 	.word	0x08001de4
- 8001d9c:	08001de8 	.word	0x08001de8
+0800225c <__libc_init_array>:
+ 800225c:	b570      	push	{r4, r5, r6, lr}
+ 800225e:	2600      	movs	r6, #0
+ 8002260:	4d0c      	ldr	r5, [pc, #48]	@ (8002294 <__libc_init_array+0x38>)
+ 8002262:	4c0d      	ldr	r4, [pc, #52]	@ (8002298 <__libc_init_array+0x3c>)
+ 8002264:	1b64      	subs	r4, r4, r5
+ 8002266:	10a4      	asrs	r4, r4, #2
+ 8002268:	42a6      	cmp	r6, r4
+ 800226a:	d109      	bne.n	8002280 <__libc_init_array+0x24>
+ 800226c:	f000 f81a 	bl	80022a4 <_init>
+ 8002270:	2600      	movs	r6, #0
+ 8002272:	4d0a      	ldr	r5, [pc, #40]	@ (800229c <__libc_init_array+0x40>)
+ 8002274:	4c0a      	ldr	r4, [pc, #40]	@ (80022a0 <__libc_init_array+0x44>)
+ 8002276:	1b64      	subs	r4, r4, r5
+ 8002278:	10a4      	asrs	r4, r4, #2
+ 800227a:	42a6      	cmp	r6, r4
+ 800227c:	d105      	bne.n	800228a <__libc_init_array+0x2e>
+ 800227e:	bd70      	pop	{r4, r5, r6, pc}
+ 8002280:	f855 3b04 	ldr.w	r3, [r5], #4
+ 8002284:	4798      	blx	r3
+ 8002286:	3601      	adds	r6, #1
+ 8002288:	e7ee      	b.n	8002268 <__libc_init_array+0xc>
+ 800228a:	f855 3b04 	ldr.w	r3, [r5], #4
+ 800228e:	4798      	blx	r3
+ 8002290:	3601      	adds	r6, #1
+ 8002292:	e7f2      	b.n	800227a <__libc_init_array+0x1e>
+ 8002294:	080022e8 	.word	0x080022e8
+ 8002298:	080022e8 	.word	0x080022e8
+ 800229c:	080022e8 	.word	0x080022e8
+ 80022a0:	080022ec 	.word	0x080022ec
 
-08001da0 <_init>:
- 8001da0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8001da2:	bf00      	nop
- 8001da4:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8001da6:	bc08      	pop	{r3}
- 8001da8:	469e      	mov	lr, r3
- 8001daa:	4770      	bx	lr
+080022a4 <_init>:
+ 80022a4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80022a6:	bf00      	nop
+ 80022a8:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 80022aa:	bc08      	pop	{r3}
+ 80022ac:	469e      	mov	lr, r3
+ 80022ae:	4770      	bx	lr
 
-08001dac <_fini>:
- 8001dac:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8001dae:	bf00      	nop
- 8001db0:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8001db2:	bc08      	pop	{r3}
- 8001db4:	469e      	mov	lr, r3
- 8001db6:	4770      	bx	lr
+080022b0 <_fini>:
+ 80022b0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80022b2:	bf00      	nop
+ 80022b4:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 80022b6:	bc08      	pop	{r3}
+ 80022b8:	469e      	mov	lr, r3
+ 80022ba:	4770      	bx	lr
diff --git a/TD-1-test/Debug/TD-1-test.map b/TD-1-test/Debug/TD-1-test.map
index dcbb568..493f721 100644
--- a/TD-1-test/Debug/TD-1-test.map
+++ b/TD-1-test/Debug/TD-1-test.map
@@ -93,6 +93,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/main.o
  .group         0x00000000        0xc ./Core/Src/main.o
  .group         0x00000000        0xc ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/main.o
  .text          0x00000000        0x0 ./Core/Src/main.o
  .data          0x00000000        0x0 ./Core/Src/main.o
  .bss           0x00000000        0x0 ./Core/Src/main.o
@@ -130,13 +132,17 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/stm32l1xx_hal_msp.o
  .group         0x00000000        0xc ./Core/Src/stm32l1xx_hal_msp.o
  .group         0x00000000        0xc ./Core/Src/stm32l1xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32l1xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32l1xx_hal_msp.o
  .text          0x00000000        0x0 ./Core/Src/stm32l1xx_hal_msp.o
  .data          0x00000000        0x0 ./Core/Src/stm32l1xx_hal_msp.o
  .bss           0x00000000        0x0 ./Core/Src/stm32l1xx_hal_msp.o
+ .text.HAL_TIM_Base_MspDeInit
+                0x00000000       0x34 ./Core/Src/stm32l1xx_hal_msp.o
  .text.HAL_UART_MspDeInit
                 0x00000000       0x3c ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000      0xacc ./Core/Src/stm32l1xx_hal_msp.o
- .debug_macro   0x00000000      0x109 ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_macro   0x00000000      0x10f ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000       0x2e ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32l1xx_hal_msp.o
@@ -165,6 +171,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000      0x1e9 ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_macro   0x00000000      0x788 ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_macro   0x00000000       0xac ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000      0x2aa ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000      0x170 ./Core/Src/stm32l1xx_hal_msp.o
  .debug_macro   0x00000000      0x492 ./Core/Src/stm32l1xx_hal_msp.o
@@ -203,11 +211,13 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/stm32l1xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32l1xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32l1xx_it.o
+ .group         0x00000000        0xc ./Core/Src/stm32l1xx_it.o
+ .group         0x00000000        0xc ./Core/Src/stm32l1xx_it.o
  .text          0x00000000        0x0 ./Core/Src/stm32l1xx_it.o
  .data          0x00000000        0x0 ./Core/Src/stm32l1xx_it.o
  .bss           0x00000000        0x0 ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000      0xacc ./Core/Src/stm32l1xx_it.o
- .debug_macro   0x00000000      0x109 ./Core/Src/stm32l1xx_it.o
+ .debug_macro   0x00000000      0x10f ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000       0x2e ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32l1xx_it.o
@@ -236,6 +246,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000      0x1e9 ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32l1xx_it.o
+ .debug_macro   0x00000000      0x788 ./Core/Src/stm32l1xx_it.o
+ .debug_macro   0x00000000       0xac ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000      0x2aa ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000      0x170 ./Core/Src/stm32l1xx_it.o
  .debug_macro   0x00000000      0x492 ./Core/Src/stm32l1xx_it.o
@@ -473,6 +485,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/system_stm32l1xx.o
  .group         0x00000000        0xc ./Core/Src/system_stm32l1xx.o
  .group         0x00000000        0xc ./Core/Src/system_stm32l1xx.o
+ .group         0x00000000        0xc ./Core/Src/system_stm32l1xx.o
+ .group         0x00000000        0xc ./Core/Src/system_stm32l1xx.o
  .text          0x00000000        0x0 ./Core/Src/system_stm32l1xx.o
  .data          0x00000000        0x0 ./Core/Src/system_stm32l1xx.o
  .bss           0x00000000        0x0 ./Core/Src/system_stm32l1xx.o
@@ -494,7 +508,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x11f ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000     0xb7a1 ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000       0x6d ./Core/Src/system_stm32l1xx.o
- .debug_macro   0x00000000      0x109 ./Core/Src/system_stm32l1xx.o
+ .debug_macro   0x00000000      0x10f ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000     0x34e1 ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000      0x190 ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000       0x5b ./Core/Src/system_stm32l1xx.o
@@ -508,6 +522,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000      0x1e9 ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000       0x22 ./Core/Src/system_stm32l1xx.o
+ .debug_macro   0x00000000      0x788 ./Core/Src/system_stm32l1xx.o
+ .debug_macro   0x00000000       0xac ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000      0x2aa ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000      0x170 ./Core/Src/system_stm32l1xx.o
  .debug_macro   0x00000000      0x492 ./Core/Src/system_stm32l1xx.o
@@ -547,6 +563,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
@@ -593,7 +611,7 @@ Discarded input sections
  .text.HAL_DBGMCU_DisableDBGStandbyMode
                 0x00000000       0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
@@ -622,6 +640,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
@@ -658,6 +678,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
@@ -710,7 +732,7 @@ Discarded input sections
  .text.HAL_SYSTICK_Callback
                 0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
@@ -739,6 +761,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
@@ -775,6 +799,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
@@ -810,9 +836,9 @@ Discarded input sections
                 0x00000000       0x80 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_rnglists
                 0x00000000       0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
- .debug_macro   0x00000000      0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .debug_macro   0x00000000      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
@@ -841,11 +867,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
- .debug_line    0x00000000      0xbc2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
- .debug_str     0x00000000    0x80200 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .debug_line    0x00000000      0xbf3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
+ .debug_str     0x00000000    0x8650f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .debug_frame   0x00000000      0x204 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o
  .ARM.attributes
@@ -883,6 +911,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
@@ -910,9 +940,9 @@ Discarded input sections
                 0x00000000       0x60 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_rnglists
                 0x00000000       0x46 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
- .debug_macro   0x00000000      0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .debug_macro   0x00000000      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
@@ -941,11 +971,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
- .debug_line    0x00000000      0x98a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
- .debug_str     0x00000000    0x7ffb1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .debug_line    0x00000000      0x9bb ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
+ .debug_str     0x00000000    0x862c0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .debug_frame   0x00000000      0x174 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o
  .ARM.attributes
@@ -983,6 +1015,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
@@ -1019,9 +1053,9 @@ Discarded input sections
                 0x00000000       0x80 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_rnglists
                 0x00000000       0x5e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
- .debug_macro   0x00000000      0x19c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .debug_macro   0x00000000      0x1b0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
@@ -1050,11 +1084,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
- .debug_line    0x00000000      0x988 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
- .debug_str     0x00000000    0x8007a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .debug_line    0x00000000      0x9b9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
+ .debug_str     0x00000000    0x86389 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .debug_frame   0x00000000      0x1d8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o
  .ARM.attributes
@@ -1092,6 +1128,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
@@ -1163,9 +1201,9 @@ Discarded input sections
                 0x00000000      0x110 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_rnglists
                 0x00000000       0xd2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
- .debug_macro   0x00000000      0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
@@ -1194,11 +1232,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
- .debug_line    0x00000000      0xf2f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
- .debug_str     0x00000000    0x804d6 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .debug_line    0x00000000      0xf60 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
+ .debug_str     0x00000000    0x867e5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .debug_frame   0x00000000      0x470 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o
  .ARM.attributes
@@ -1236,6 +1276,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
@@ -1246,9 +1288,9 @@ Discarded input sections
                 0x00000000       0x68 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_rnglists
                 0x00000000       0x50 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
- .debug_macro   0x00000000      0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .debug_macro   0x00000000      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
@@ -1277,11 +1319,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
- .debug_line    0x00000000      0x946 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
- .debug_str     0x00000000    0x80103 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .debug_line    0x00000000      0x977 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
+ .debug_str     0x00000000    0x86412 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .debug_frame   0x00000000      0x178 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o
  .ARM.attributes
@@ -1319,6 +1363,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
@@ -1333,7 +1379,7 @@ Discarded input sections
  .text.HAL_GPIO_EXTI_Callback
                 0x00000000       0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
@@ -1362,6 +1408,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
@@ -1398,6 +1446,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
@@ -1441,9 +1491,9 @@ Discarded input sections
                 0x00000000       0xa0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_rnglists
                 0x00000000       0x74 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
- .debug_macro   0x00000000      0x1b3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .debug_macro   0x00000000      0x1c7 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
@@ -1472,11 +1522,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
- .debug_line    0x00000000      0x964 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
- .debug_str     0x00000000    0x8010f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .debug_line    0x00000000      0x995 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
+ .debug_str     0x00000000    0x8641e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .debug_frame   0x00000000      0x274 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
  .ARM.attributes
@@ -1514,6 +1566,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
@@ -1537,9 +1591,9 @@ Discarded input sections
                 0x00000000       0x50 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_rnglists
                 0x00000000       0x37 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
- .debug_macro   0x00000000      0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .debug_macro   0x00000000      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
@@ -1568,11 +1622,13 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
- .debug_line    0x00000000      0x895 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
- .debug_str     0x00000000    0x7feee ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .debug_line    0x00000000      0x8c6 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
+ .debug_str     0x00000000    0x861fd ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .debug_frame   0x00000000      0x120 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
  .ARM.attributes
@@ -1610,6 +1666,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
@@ -1630,7 +1688,7 @@ Discarded input sections
  .text.HAL_RCC_CSSCallback
                 0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
@@ -1659,6 +1717,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
@@ -1695,6 +1755,8 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
@@ -1720,9 +1782,9 @@ Discarded input sections
                 0x00000000       0x58 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_rnglists
                 0x00000000       0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
- .debug_macro   0x00000000      0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
@@ -1751,15 +1813,389 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
- .debug_line    0x00000000      0x8ef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
- .debug_str     0x00000000    0x8001e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .debug_line    0x00000000      0x920 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .debug_str     0x00000000    0x8632d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .comment       0x00000000       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .debug_frame   0x00000000      0x120 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
  .ARM.attributes
                 0x00000000       0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
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+ .debug_macro   0x00000000      0xe37 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x35b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x1b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000       0xc5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x21e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x236 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x115 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .text          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .data          0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .bss           0x00000000        0x0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .text.HAL_TIMEx_RemapConfig
+                0x00000000       0x3c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x8e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x51 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x103 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x6a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1df ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0xbd ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0xe49 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x11f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000     0xb7a1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000     0x34e1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x190 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x5b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0xe37 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x35b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0xc5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x21e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x236 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x115 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+ .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
@@ -1917,7 +2353,7 @@ Discarded input sections
  .text.UART_Receive_IT
                 0x00000000      0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000      0xacc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
- .debug_macro   0x00000000      0x109 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+ .debug_macro   0x00000000      0x10f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
@@ -1946,6 +2382,8 @@ Discarded input sections
  .debug_macro   0x00000000      0x567 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000      0x1e9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+ .debug_macro   0x00000000      0x788 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+ .debug_macro   0x00000000       0xac ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000      0x2aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000      0x170 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .debug_macro   0x00000000      0x492 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
@@ -2211,6 +2649,8 @@ LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o
 LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o
 LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
 LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o
+LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
 LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 START GROUP
 LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a
@@ -2243,7 +2683,7 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
                 0x08000000                g_pfnVectors
                 0x0800013c                        . = ALIGN (0x4)
 
-.text           0x0800013c     0x1c7c
+.text           0x0800013c     0x2180
                 0x0800013c                        . = ALIGN (0x4)
  *(.text)
  .text          0x0800013c       0x40 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
@@ -2255,283 +2695,315 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
                 0x080004ac                __aeabi_ldiv0
                 0x080004ac                __aeabi_idiv0
  *(.text*)
- .text.main     0x080004b0       0x26 ./Core/Src/main.o
+ .text.main     0x080004b0       0x48 ./Core/Src/main.o
                 0x080004b0                main
- *fill*         0x080004d6        0x2 
  .text.SystemClock_Config
-                0x080004d8       0x9c ./Core/Src/main.o
-                0x080004d8                SystemClock_Config
+                0x080004f8       0x8c ./Core/Src/main.o
+                0x080004f8                SystemClock_Config
+ .text.MX_TIM6_Init
+                0x08000584       0x6c ./Core/Src/main.o
  .text.MX_USART2_UART_Init
-                0x08000574       0x54 ./Core/Src/main.o
+                0x080005f0       0x54 ./Core/Src/main.o
  .text.MX_GPIO_Init
-                0x080005c8       0xdc ./Core/Src/main.o
+                0x08000644       0xdc ./Core/Src/main.o
  .text.HAL_GPIO_EXTI_Callback
-                0x080006a4       0x24 ./Core/Src/main.o
-                0x080006a4                HAL_GPIO_EXTI_Callback
+                0x08000720       0x24 ./Core/Src/main.o
+                0x08000720                HAL_GPIO_EXTI_Callback
  .text.Error_Handler
-                0x080006c8        0xc ./Core/Src/main.o
-                0x080006c8                Error_Handler
+                0x08000744        0xc ./Core/Src/main.o
+                0x08000744                Error_Handler
  .text.HAL_MspInit
-                0x080006d4       0x60 ./Core/Src/stm32l1xx_hal_msp.o
-                0x080006d4                HAL_MspInit
+                0x08000750       0x60 ./Core/Src/stm32l1xx_hal_msp.o
+                0x08000750                HAL_MspInit
+ .text.HAL_TIM_Base_MspInit
+                0x080007b0       0x4c ./Core/Src/stm32l1xx_hal_msp.o
+                0x080007b0                HAL_TIM_Base_MspInit
  .text.HAL_UART_MspInit
-                0x08000734       0x88 ./Core/Src/stm32l1xx_hal_msp.o
-                0x08000734                HAL_UART_MspInit
+                0x080007fc       0x88 ./Core/Src/stm32l1xx_hal_msp.o
+                0x080007fc                HAL_UART_MspInit
  .text.NMI_Handler
-                0x080007bc        0x8 ./Core/Src/stm32l1xx_it.o
-                0x080007bc                NMI_Handler
+                0x08000884        0x8 ./Core/Src/stm32l1xx_it.o
+                0x08000884                NMI_Handler
  .text.HardFault_Handler
-                0x080007c4        0x8 ./Core/Src/stm32l1xx_it.o
-                0x080007c4                HardFault_Handler
+                0x0800088c        0x8 ./Core/Src/stm32l1xx_it.o
+                0x0800088c                HardFault_Handler
  .text.MemManage_Handler
-                0x080007cc        0x8 ./Core/Src/stm32l1xx_it.o
-                0x080007cc                MemManage_Handler
+                0x08000894        0x8 ./Core/Src/stm32l1xx_it.o
+                0x08000894                MemManage_Handler
  .text.BusFault_Handler
-                0x080007d4        0x8 ./Core/Src/stm32l1xx_it.o
-                0x080007d4                BusFault_Handler
+                0x0800089c        0x8 ./Core/Src/stm32l1xx_it.o
+                0x0800089c                BusFault_Handler
  .text.UsageFault_Handler
-                0x080007dc        0x8 ./Core/Src/stm32l1xx_it.o
-                0x080007dc                UsageFault_Handler
+                0x080008a4        0x8 ./Core/Src/stm32l1xx_it.o
+                0x080008a4                UsageFault_Handler
  .text.SVC_Handler
-                0x080007e4        0xc ./Core/Src/stm32l1xx_it.o
-                0x080007e4                SVC_Handler
+                0x080008ac        0xc ./Core/Src/stm32l1xx_it.o
+                0x080008ac                SVC_Handler
  .text.DebugMon_Handler
-                0x080007f0        0xc ./Core/Src/stm32l1xx_it.o
-                0x080007f0                DebugMon_Handler
+                0x080008b8        0xc ./Core/Src/stm32l1xx_it.o
+                0x080008b8                DebugMon_Handler
  .text.PendSV_Handler
-                0x080007fc        0xc ./Core/Src/stm32l1xx_it.o
-                0x080007fc                PendSV_Handler
+                0x080008c4        0xc ./Core/Src/stm32l1xx_it.o
+                0x080008c4                PendSV_Handler
  .text.SysTick_Handler
-                0x08000808        0xc ./Core/Src/stm32l1xx_it.o
-                0x08000808                SysTick_Handler
+                0x080008d0        0xc ./Core/Src/stm32l1xx_it.o
+                0x080008d0                SysTick_Handler
  .text.EXTI15_10_IRQHandler
-                0x08000814       0x10 ./Core/Src/stm32l1xx_it.o
-                0x08000814                EXTI15_10_IRQHandler
+                0x080008dc       0x10 ./Core/Src/stm32l1xx_it.o
+                0x080008dc                EXTI15_10_IRQHandler
+ .text.TIM6_IRQHandler
+                0x080008ec       0x24 ./Core/Src/stm32l1xx_it.o
+                0x080008ec                TIM6_IRQHandler
  .text.SystemInit
-                0x08000824        0xc ./Core/Src/system_stm32l1xx.o
-                0x08000824                SystemInit
+                0x08000910        0xc ./Core/Src/system_stm32l1xx.o
+                0x08000910                SystemInit
  .text.Reset_Handler
-                0x08000830       0x48 ./Core/Startup/startup_stm32l152retx.o
-                0x08000830                Reset_Handler
+                0x0800091c       0x48 ./Core/Startup/startup_stm32l152retx.o
+                0x0800091c                Reset_Handler
  .text.Default_Handler
-                0x08000878        0x2 ./Core/Startup/startup_stm32l152retx.o
-                0x08000878                DMA2_Channel3_IRQHandler
-                0x08000878                EXTI2_IRQHandler
-                0x08000878                COMP_ACQ_IRQHandler
-                0x08000878                TIM10_IRQHandler
-                0x08000878                USB_HP_IRQHandler
-                0x08000878                TIM6_IRQHandler
-                0x08000878                PVD_IRQHandler
-                0x08000878                EXTI3_IRQHandler
-                0x08000878                EXTI0_IRQHandler
-                0x08000878                I2C2_EV_IRQHandler
-                0x08000878                SPI1_IRQHandler
-                0x08000878                USB_FS_WKUP_IRQHandler
-                0x08000878                DMA2_Channel2_IRQHandler
-                0x08000878                DMA1_Channel4_IRQHandler
-                0x08000878                ADC1_IRQHandler
-                0x08000878                USART3_IRQHandler
-                0x08000878                DMA1_Channel7_IRQHandler
-                0x08000878                LCD_IRQHandler
-                0x08000878                UART5_IRQHandler
-                0x08000878                TIM4_IRQHandler
-                0x08000878                DMA2_Channel1_IRQHandler
-                0x08000878                I2C1_EV_IRQHandler
-                0x08000878                DMA1_Channel6_IRQHandler
-                0x08000878                UART4_IRQHandler
-                0x08000878                DMA2_Channel4_IRQHandler
-                0x08000878                TIM3_IRQHandler
-                0x08000878                RCC_IRQHandler
-                0x08000878                DMA1_Channel1_IRQHandler
-                0x08000878                Default_Handler
-                0x08000878                TIM7_IRQHandler
-                0x08000878                TIM5_IRQHandler
-                0x08000878                EXTI9_5_IRQHandler
-                0x08000878                TIM9_IRQHandler
-                0x08000878                TAMPER_STAMP_IRQHandler
-                0x08000878                RTC_WKUP_IRQHandler
-                0x08000878                SPI2_IRQHandler
-                0x08000878                DMA2_Channel5_IRQHandler
-                0x08000878                DMA1_Channel5_IRQHandler
-                0x08000878                USB_LP_IRQHandler
-                0x08000878                EXTI4_IRQHandler
-                0x08000878                DMA1_Channel3_IRQHandler
-                0x08000878                COMP_IRQHandler
-                0x08000878                WWDG_IRQHandler
-                0x08000878                TIM2_IRQHandler
-                0x08000878                DAC_IRQHandler
-                0x08000878                EXTI1_IRQHandler
-                0x08000878                TIM11_IRQHandler
-                0x08000878                USART2_IRQHandler
-                0x08000878                I2C2_ER_IRQHandler
-                0x08000878                DMA1_Channel2_IRQHandler
-                0x08000878                FLASH_IRQHandler
-                0x08000878                USART1_IRQHandler
-                0x08000878                SPI3_IRQHandler
-                0x08000878                I2C1_ER_IRQHandler
-                0x08000878                RTC_Alarm_IRQHandler
+                0x08000964        0x2 ./Core/Startup/startup_stm32l152retx.o
+                0x08000964                DMA2_Channel3_IRQHandler
+                0x08000964                EXTI2_IRQHandler
+                0x08000964                COMP_ACQ_IRQHandler
+                0x08000964                TIM10_IRQHandler
+                0x08000964                USB_HP_IRQHandler
+                0x08000964                PVD_IRQHandler
+                0x08000964                EXTI3_IRQHandler
+                0x08000964                EXTI0_IRQHandler
+                0x08000964                I2C2_EV_IRQHandler
+                0x08000964                SPI1_IRQHandler
+                0x08000964                USB_FS_WKUP_IRQHandler
+                0x08000964                DMA2_Channel2_IRQHandler
+                0x08000964                DMA1_Channel4_IRQHandler
+                0x08000964                ADC1_IRQHandler
+                0x08000964                USART3_IRQHandler
+                0x08000964                DMA1_Channel7_IRQHandler
+                0x08000964                LCD_IRQHandler
+                0x08000964                UART5_IRQHandler
+                0x08000964                TIM4_IRQHandler
+                0x08000964                DMA2_Channel1_IRQHandler
+                0x08000964                I2C1_EV_IRQHandler
+                0x08000964                DMA1_Channel6_IRQHandler
+                0x08000964                UART4_IRQHandler
+                0x08000964                DMA2_Channel4_IRQHandler
+                0x08000964                TIM3_IRQHandler
+                0x08000964                RCC_IRQHandler
+                0x08000964                DMA1_Channel1_IRQHandler
+                0x08000964                Default_Handler
+                0x08000964                TIM7_IRQHandler
+                0x08000964                TIM5_IRQHandler
+                0x08000964                EXTI9_5_IRQHandler
+                0x08000964                TIM9_IRQHandler
+                0x08000964                TAMPER_STAMP_IRQHandler
+                0x08000964                RTC_WKUP_IRQHandler
+                0x08000964                SPI2_IRQHandler
+                0x08000964                DMA2_Channel5_IRQHandler
+                0x08000964                DMA1_Channel5_IRQHandler
+                0x08000964                USB_LP_IRQHandler
+                0x08000964                EXTI4_IRQHandler
+                0x08000964                DMA1_Channel3_IRQHandler
+                0x08000964                COMP_IRQHandler
+                0x08000964                WWDG_IRQHandler
+                0x08000964                TIM2_IRQHandler
+                0x08000964                DAC_IRQHandler
+                0x08000964                EXTI1_IRQHandler
+                0x08000964                TIM11_IRQHandler
+                0x08000964                USART2_IRQHandler
+                0x08000964                I2C2_ER_IRQHandler
+                0x08000964                DMA1_Channel2_IRQHandler
+                0x08000964                FLASH_IRQHandler
+                0x08000964                USART1_IRQHandler
+                0x08000964                SPI3_IRQHandler
+                0x08000964                I2C1_ER_IRQHandler
+                0x08000964                RTC_Alarm_IRQHandler
  .text.HAL_Init
-                0x0800087a       0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
-                0x0800087a                HAL_Init
- *fill*         0x080008aa        0x2 
+                0x08000966       0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+                0x08000966                HAL_Init
+ *fill*         0x08000996        0x2 
  .text.HAL_InitTick
-                0x080008ac       0x74 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
-                0x080008ac                HAL_InitTick
+                0x08000998       0x74 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+                0x08000998                HAL_InitTick
  .text.HAL_IncTick
-                0x08000920       0x24 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
-                0x08000920                HAL_IncTick
+                0x08000a0c       0x24 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+                0x08000a0c                HAL_IncTick
  .text.HAL_GetTick
-                0x08000944       0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
-                0x08000944                HAL_GetTick
+                0x08000a30       0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+                0x08000a30                HAL_GetTick
  .text.__NVIC_SetPriorityGrouping
-                0x08000958       0x48 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000a44       0x48 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .text.__NVIC_GetPriorityGrouping
-                0x080009a0       0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000a8c       0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .text.__NVIC_EnableIRQ
-                0x080009bc       0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000aa8       0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .text.__NVIC_SetPriority
-                0x080009f4       0x54 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000ae0       0x54 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .text.NVIC_EncodePriority
-                0x08000a48       0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000b34       0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .text.SysTick_Config
-                0x08000aac       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000b98       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .text.HAL_NVIC_SetPriorityGrouping
-                0x08000af0       0x16 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
-                0x08000af0                HAL_NVIC_SetPriorityGrouping
+                0x08000bdc       0x16 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000bdc                HAL_NVIC_SetPriorityGrouping
  .text.HAL_NVIC_SetPriority
-                0x08000b06       0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
-                0x08000b06                HAL_NVIC_SetPriority
+                0x08000bf2       0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000bf2                HAL_NVIC_SetPriority
  .text.HAL_NVIC_EnableIRQ
-                0x08000b3e       0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
-                0x08000b3e                HAL_NVIC_EnableIRQ
+                0x08000c2a       0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000c2a                HAL_NVIC_EnableIRQ
  .text.HAL_SYSTICK_Config
-                0x08000b5a       0x18 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
-                0x08000b5a                HAL_SYSTICK_Config
- *fill*         0x08000b72        0x2 
+                0x08000c46       0x18 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x08000c46                HAL_SYSTICK_Config
+ *fill*         0x08000c5e        0x2 
  .text.HAL_GPIO_Init
-                0x08000b74      0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
-                0x08000b74                HAL_GPIO_Init
+                0x08000c60      0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+                0x08000c60                HAL_GPIO_Init
  .text.HAL_GPIO_WritePin
-                0x08000e94       0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
-                0x08000e94                HAL_GPIO_WritePin
+                0x08000f80       0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+                0x08000f80                HAL_GPIO_WritePin
  .text.HAL_GPIO_EXTI_IRQHandler
-                0x08000ec4       0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
-                0x08000ec4                HAL_GPIO_EXTI_IRQHandler
+                0x08000fb0       0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+                0x08000fb0                HAL_GPIO_EXTI_IRQHandler
  .text.HAL_RCC_OscConfig
-                0x08000ef4      0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
-                0x08000ef4                HAL_RCC_OscConfig
+                0x08000fe0      0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x08000fe0                HAL_RCC_OscConfig
  .text.HAL_RCC_ClockConfig
-                0x08001554      0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
-                0x08001554                HAL_RCC_ClockConfig
+                0x08001640      0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x08001640                HAL_RCC_ClockConfig
  .text.HAL_RCC_GetSysClockFreq
-                0x080017bc      0x200 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
-                0x080017bc                HAL_RCC_GetSysClockFreq
+                0x080018a8      0x200 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x080018a8                HAL_RCC_GetSysClockFreq
  .text.HAL_RCC_GetHCLKFreq
-                0x080019bc       0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
-                0x080019bc                HAL_RCC_GetHCLKFreq
+                0x08001aa8       0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x08001aa8                HAL_RCC_GetHCLKFreq
  .text.HAL_RCC_GetPCLK1Freq
-                0x080019d0       0x28 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
-                0x080019d0                HAL_RCC_GetPCLK1Freq
+                0x08001abc       0x28 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x08001abc                HAL_RCC_GetPCLK1Freq
  .text.HAL_RCC_GetPCLK2Freq
-                0x080019f8       0x28 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
-                0x080019f8                HAL_RCC_GetPCLK2Freq
+                0x08001ae4       0x28 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x08001ae4                HAL_RCC_GetPCLK2Freq
  .text.RCC_SetFlashLatencyFromMSIRange
-                0x08001a20       0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x08001b0c       0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .text.HAL_TIM_Base_Init
+                0x08001bcc       0x7e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+                0x08001bcc                HAL_TIM_Base_Init
+ .text.HAL_TIM_IRQHandler
+                0x08001c4a      0x198 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+                0x08001c4a                HAL_TIM_IRQHandler
+ .text.HAL_TIM_PeriodElapsedCallback
+                0x08001de2       0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+                0x08001de2                HAL_TIM_PeriodElapsedCallback
+ .text.HAL_TIM_OC_DelayElapsedCallback
+                0x08001df4       0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+                0x08001df4                HAL_TIM_OC_DelayElapsedCallback
+ .text.HAL_TIM_IC_CaptureCallback
+                0x08001e06       0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+                0x08001e06                HAL_TIM_IC_CaptureCallback
+ .text.HAL_TIM_PWM_PulseFinishedCallback
+                0x08001e18       0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+                0x08001e18                HAL_TIM_PWM_PulseFinishedCallback
+ .text.HAL_TIM_TriggerCallback
+                0x08001e2a       0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+                0x08001e2a                HAL_TIM_TriggerCallback
+ .text.TIM_Base_SetConfig
+                0x08001e3c       0xec ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .text.HAL_TIMEx_MasterConfigSynchronization
+                0x08001f28       0xbc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+                0x08001f28                HAL_TIMEx_MasterConfigSynchronization
  .text.HAL_UART_Init
-                0x08001ae0       0xa0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
-                0x08001ae0                HAL_UART_Init
+                0x08001fe4       0xa0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+                0x08001fe4                HAL_UART_Init
  .text.UART_SetConfig
-                0x08001b80      0x1c8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
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-                0x08001d48                memset
+                0x08002084      0x1c8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
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+                0x0800224c                memset
  .text.__libc_init_array
-                0x08001d58       0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o)
-                0x08001d58                __libc_init_array
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+                0x0800225c                __libc_init_array
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  *(.glue_7t)
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-                0x08001db8                        . = ALIGN (0x4)
-                0x08001db8                        _etext = .
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+                0x080022bc                        . = ALIGN (0x4)
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  *(.rodata)
  *(.rodata*)
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-                0x08001db8        0x9 ./Core/Src/system_stm32l1xx.o
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  .rodata.AHBPrescTable
-                0x08001dc4       0x10 ./Core/Src/system_stm32l1xx.o
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+                0x080022e0                        . = ALIGN (0x4)
 
-.ARM            0x08001ddc        0x8
-                0x08001ddc                        . = ALIGN (0x4)
-                0x08001ddc                        __exidx_start = .
+.ARM            0x080022e0        0x8
+                0x080022e0                        . = ALIGN (0x4)
+                0x080022e0                        __exidx_start = .
  *(.ARM.exidx*)
- .ARM.exidx     0x08001ddc        0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o)
-                0x08001de4                        __exidx_end = .
-                0x08001de4                        . = ALIGN (0x4)
+ .ARM.exidx     0x080022e0        0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o)
+                0x080022e8                        __exidx_end = .
+                0x080022e8                        . = ALIGN (0x4)
 
-.preinit_array  0x08001de4        0x0
-                0x08001de4                        . = ALIGN (0x4)
-                0x08001de4                        PROVIDE (__preinit_array_start = .)
+.preinit_array  0x080022e8        0x0
+                0x080022e8                        . = ALIGN (0x4)
+                0x080022e8                        PROVIDE (__preinit_array_start = .)
  *(.preinit_array*)
-                0x08001de4                        PROVIDE (__preinit_array_end = .)
-                0x08001de4                        . = ALIGN (0x4)
+                0x080022e8                        PROVIDE (__preinit_array_end = .)
+                0x080022e8                        . = ALIGN (0x4)
 
-.init_array     0x08001de4        0x4
-                0x08001de4                        . = ALIGN (0x4)
-                0x08001de4                        PROVIDE (__init_array_start = .)
+.init_array     0x080022e8        0x4
+                0x080022e8                        . = ALIGN (0x4)
+                0x080022e8                        PROVIDE (__init_array_start = .)
  *(SORT_BY_NAME(.init_array.*))
  *(.init_array*)
- .init_array    0x08001de4        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
-                0x08001de8                        PROVIDE (__init_array_end = .)
-                0x08001de8                        . = ALIGN (0x4)
+ .init_array    0x080022e8        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
+                0x080022ec                        PROVIDE (__init_array_end = .)
+                0x080022ec                        . = ALIGN (0x4)
 
-.fini_array     0x08001de8        0x4
-                0x08001de8                        . = ALIGN (0x4)
+.fini_array     0x080022ec        0x4
+                0x080022ec                        . = ALIGN (0x4)
                 [!provide]                        PROVIDE (__fini_array_start = .)
  *(SORT_BY_NAME(.fini_array.*))
  *(.fini_array*)
- .fini_array    0x08001de8        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
+ .fini_array    0x080022ec        0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
                 [!provide]                        PROVIDE (__fini_array_end = .)
-                0x08001dec                        . = ALIGN (0x4)
-                0x08001dec                        _sidata = LOADADDR (.data)
+                0x080022f0                        . = ALIGN (0x4)
+                0x080022f0                        _sidata = LOADADDR (.data)
 
-.rel.dyn        0x08001dec        0x0
- .rel.iplt      0x08001dec        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
+.rel.dyn        0x080022f0        0x0
+ .rel.iplt      0x080022f0        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
 
-.data           0x20000000        0xc load address 0x08001dec
+.data           0x20000000        0xc load address 0x080022f0
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _sdata = .
  *(.data)
@@ -2550,36 +3022,38 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
                 0x2000000c                        . = ALIGN (0x4)
                 0x2000000c                        _edata = .
 
-.igot.plt       0x2000000c        0x0 load address 0x08001df8
+.igot.plt       0x2000000c        0x0 load address 0x080022fc
  .igot.plt      0x2000000c        0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
                 0x2000000c                        . = ALIGN (0x4)
 
-.bss            0x2000000c       0x68 load address 0x08001df8
+.bss            0x2000000c       0xa8 load address 0x080022fc
                 0x2000000c                        _sbss = .
                 0x2000000c                        __bss_start__ = _sbss
  *(.bss)
  .bss           0x2000000c       0x1c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o
  *(.bss*)
- .bss.huart2    0x20000028       0x48 ./Core/Src/main.o
-                0x20000028                huart2
- .bss.uwTick    0x20000070        0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
-                0x20000070                uwTick
+ .bss.htim6     0x20000028       0x40 ./Core/Src/main.o
+                0x20000028                htim6
+ .bss.huart2    0x20000068       0x48 ./Core/Src/main.o
+                0x20000068                huart2
+ .bss.uwTick    0x200000b0        0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+                0x200000b0                uwTick
  *(COMMON)
-                0x20000074                        . = ALIGN (0x4)
-                0x20000074                        _ebss = .
-                0x20000074                        __bss_end__ = _ebss
+                0x200000b4                        . = ALIGN (0x4)
+                0x200000b4                        _ebss = .
+                0x200000b4                        __bss_end__ = _ebss
 
 ._user_heap_stack
-                0x20000074      0x604 load address 0x08001df8
-                0x20000078                        . = ALIGN (0x8)
- *fill*         0x20000074        0x4 
+                0x200000b4      0x604 load address 0x080022fc
+                0x200000b8                        . = ALIGN (0x8)
+ *fill*         0x200000b4        0x4 
                 [!provide]                        PROVIDE (end = .)
-                0x20000078                        PROVIDE (_end = .)
-                0x20000278                        . = (. + _Min_Heap_Size)
- *fill*         0x20000078      0x200 
-                0x20000678                        . = (. + _Min_Stack_Size)
- *fill*         0x20000278      0x400 
-                0x20000678                        . = ALIGN (0x8)
+                0x200000b8                        PROVIDE (_end = .)
+                0x200002b8                        . = (. + _Min_Heap_Size)
+ *fill*         0x200000b8      0x200 
+                0x200006b8                        . = (. + _Min_Stack_Size)
+ *fill*         0x200002b8      0x400 
+                0x200006b8                        . = ALIGN (0x8)
 
 /DISCARD/
  libc.a(*)
@@ -2612,163 +3086,187 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
  .ARM.attributes
                 0x000001a6       0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .ARM.attributes
-                0x000001d3       0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+                0x000001d3       0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
  .ARM.attributes
-                0x00000200       0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o)
+                0x00000200       0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
  .ARM.attributes
-                0x0000022d       0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o)
+                0x0000022d       0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
  .ARM.attributes
-                0x0000025a       0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o)
+                0x0000025a       0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o)
  .ARM.attributes
-                0x00000277       0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o)
+                0x00000287       0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o)
  .ARM.attributes
-                0x000002a4       0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_dvmd_tls.o)
+                0x000002b4       0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o)
  .ARM.attributes
-                0x000002c1       0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o
+                0x000002d1       0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o)
+ .ARM.attributes
+                0x000002fe       0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_dvmd_tls.o)
+ .ARM.attributes
+                0x0000031b       0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o
 OUTPUT(TD-1-test.elf elf32-littlearm)
 LOAD linker stubs
 LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc.a
 LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libm.a
 LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a
 
-.debug_info     0x00000000     0x6afc
- .debug_info    0x00000000      0xce5 ./Core/Src/main.o
- .debug_info    0x00000ce5      0x80f ./Core/Src/stm32l1xx_hal_msp.o
- .debug_info    0x000014f4      0x14c ./Core/Src/stm32l1xx_it.o
- .debug_info    0x00001640      0x27c ./Core/Src/system_stm32l1xx.o
- .debug_info    0x000018bc       0x30 ./Core/Startup/startup_stm32l152retx.o
- .debug_info    0x000018ec      0x6ef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
- .debug_info    0x00001fdb      0xce5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
- .debug_info    0x00002cc0      0x5b2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
- .debug_info    0x00003272      0x99b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
- .debug_info    0x00003c0d     0x2eef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+.debug_info     0x00000000     0xa8cd
+ .debug_info    0x00000000     0x10a5 ./Core/Src/main.o
+ .debug_info    0x000010a5      0xd8a ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_info    0x00001e2f      0x76d ./Core/Src/stm32l1xx_it.o
+ .debug_info    0x0000259c      0x27c ./Core/Src/system_stm32l1xx.o
+ .debug_info    0x00002818       0x30 ./Core/Startup/startup_stm32l152retx.o
+ .debug_info    0x00002848      0x6ef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_info    0x00002f37      0xce5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_info    0x00003c1c      0x5b2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_info    0x000041ce      0x99b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_info    0x00004b69     0x27cd ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_info    0x00007336      0x6a8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_info    0x000079de     0x2eef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
-.debug_abbrev   0x00000000     0x130c
- .debug_abbrev  0x00000000      0x26e ./Core/Src/main.o
- .debug_abbrev  0x0000026e      0x1aa ./Core/Src/stm32l1xx_hal_msp.o
- .debug_abbrev  0x00000418       0xa0 ./Core/Src/stm32l1xx_it.o
- .debug_abbrev  0x000004b8      0x11c ./Core/Src/system_stm32l1xx.o
- .debug_abbrev  0x000005d4       0x24 ./Core/Startup/startup_stm32l152retx.o
- .debug_abbrev  0x000005f8      0x275 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
- .debug_abbrev  0x0000086d      0x31c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
- .debug_abbrev  0x00000b89      0x1d4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
- .debug_abbrev  0x00000d5d      0x2b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
- .debug_abbrev  0x00001015      0x2f7 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+.debug_abbrev   0x00000000     0x182d
+ .debug_abbrev  0x00000000      0x2c4 ./Core/Src/main.o
+ .debug_abbrev  0x000002c4      0x1c1 ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_abbrev  0x00000485      0x18e ./Core/Src/stm32l1xx_it.o
+ .debug_abbrev  0x00000613      0x11c ./Core/Src/system_stm32l1xx.o
+ .debug_abbrev  0x0000072f       0x24 ./Core/Startup/startup_stm32l152retx.o
+ .debug_abbrev  0x00000753      0x275 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_abbrev  0x000009c8      0x31c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_abbrev  0x00000ce4      0x1d4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_abbrev  0x00000eb8      0x2b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_abbrev  0x00001170      0x25e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_abbrev  0x000013ce      0x168 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_abbrev  0x00001536      0x2f7 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
-.debug_aranges  0x00000000      0x628
+.debug_aranges  0x00000000      0xa40
  .debug_aranges
-                0x00000000       0x48 ./Core/Src/main.o
+                0x00000000       0x50 ./Core/Src/main.o
  .debug_aranges
-                0x00000048       0x30 ./Core/Src/stm32l1xx_hal_msp.o
+                0x00000050       0x40 ./Core/Src/stm32l1xx_hal_msp.o
  .debug_aranges
-                0x00000078       0x68 ./Core/Src/stm32l1xx_it.o
+                0x00000090       0x70 ./Core/Src/stm32l1xx_it.o
  .debug_aranges
-                0x000000e0       0x28 ./Core/Src/system_stm32l1xx.o
+                0x00000100       0x28 ./Core/Src/system_stm32l1xx.o
  .debug_aranges
-                0x00000108       0x28 ./Core/Startup/startup_stm32l152retx.o
+                0x00000128       0x28 ./Core/Startup/startup_stm32l152retx.o
  .debug_aranges
-                0x00000130       0xe0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+                0x00000150       0xe0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_aranges
-                0x00000210      0x128 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x00000230      0x128 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_aranges
-                0x00000338       0x58 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+                0x00000358       0x58 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_aranges
-                0x00000390       0x90 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x000003b0       0x90 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_aranges
-                0x00000420      0x208 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+                0x00000440      0x3d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_aranges
+                0x00000810       0x28 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_aranges
+                0x00000838      0x208 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
 .debug_rnglists
-                0x00000000      0x4b3
+                0x00000000      0x7ec
  .debug_rnglists
-                0x00000000       0x33 ./Core/Src/main.o
+                0x00000000       0x39 ./Core/Src/main.o
  .debug_rnglists
-                0x00000033       0x20 ./Core/Src/stm32l1xx_hal_msp.o
+                0x00000039       0x2c ./Core/Src/stm32l1xx_hal_msp.o
  .debug_rnglists
-                0x00000053       0x49 ./Core/Src/stm32l1xx_it.o
+                0x00000065       0x4f ./Core/Src/stm32l1xx_it.o
  .debug_rnglists
-                0x0000009c       0x1a ./Core/Src/system_stm32l1xx.o
+                0x000000b4       0x1a ./Core/Src/system_stm32l1xx.o
  .debug_rnglists
-                0x000000b6       0x19 ./Core/Startup/startup_stm32l152retx.o
+                0x000000ce       0x19 ./Core/Startup/startup_stm32l152retx.o
  .debug_rnglists
-                0x000000cf       0xa3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+                0x000000e7       0xa3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
  .debug_rnglists
-                0x00000172       0xd9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+                0x0000018a       0xd9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .debug_rnglists
-                0x0000024b       0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+                0x00000263       0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .debug_rnglists
-                0x0000028a       0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+                0x000002a2       0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
  .debug_rnglists
-                0x000002f7      0x1bc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+                0x0000030f      0x307 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_rnglists
+                0x00000616       0x1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_rnglists
+                0x00000630      0x1bc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
-.debug_macro    0x00000000    0x14879
- .debug_macro   0x00000000      0x1aa ./Core/Src/main.o
- .debug_macro   0x000001aa      0xacc ./Core/Src/main.o
- .debug_macro   0x00000c76      0x109 ./Core/Src/main.o
- .debug_macro   0x00000d7f       0x2e ./Core/Src/main.o
- .debug_macro   0x00000dad       0x22 ./Core/Src/main.o
- .debug_macro   0x00000dcf       0x22 ./Core/Src/main.o
- .debug_macro   0x00000df1       0x8e ./Core/Src/main.o
- .debug_macro   0x00000e7f       0x51 ./Core/Src/main.o
- .debug_macro   0x00000ed0      0x103 ./Core/Src/main.o
- .debug_macro   0x00000fd3       0x6a ./Core/Src/main.o
- .debug_macro   0x0000103d      0x1df ./Core/Src/main.o
- .debug_macro   0x0000121c       0x1c ./Core/Src/main.o
- .debug_macro   0x00001238       0x22 ./Core/Src/main.o
- .debug_macro   0x0000125a       0xbd ./Core/Src/main.o
- .debug_macro   0x00001317      0xe49 ./Core/Src/main.o
- .debug_macro   0x00002160      0x11f ./Core/Src/main.o
- .debug_macro   0x0000227f     0xb7a1 ./Core/Src/main.o
- .debug_macro   0x0000da20       0x6d ./Core/Src/main.o
- .debug_macro   0x0000da8d     0x34e1 ./Core/Src/main.o
- .debug_macro   0x00010f6e      0x190 ./Core/Src/main.o
- .debug_macro   0x000110fe       0x5b ./Core/Src/main.o
- .debug_macro   0x00011159      0xe37 ./Core/Src/main.o
- .debug_macro   0x00011f90      0x35b ./Core/Src/main.o
- .debug_macro   0x000122eb      0x1b8 ./Core/Src/main.o
- .debug_macro   0x000124a3       0xc5 ./Core/Src/main.o
- .debug_macro   0x00012568      0x21e ./Core/Src/main.o
- .debug_macro   0x00012786      0x236 ./Core/Src/main.o
- .debug_macro   0x000129bc      0x115 ./Core/Src/main.o
- .debug_macro   0x00012ad1      0x567 ./Core/Src/main.o
- .debug_macro   0x00013038      0x1e9 ./Core/Src/main.o
- .debug_macro   0x00013221       0x22 ./Core/Src/main.o
- .debug_macro   0x00013243      0x2aa ./Core/Src/main.o
- .debug_macro   0x000134ed      0x170 ./Core/Src/main.o
- .debug_macro   0x0001365d      0x492 ./Core/Src/main.o
- .debug_macro   0x00013aef       0x4c ./Core/Src/main.o
- .debug_macro   0x00013b3b      0x1aa ./Core/Src/stm32l1xx_hal_msp.o
- .debug_macro   0x00013ce5      0x1b4 ./Core/Src/stm32l1xx_it.o
- .debug_macro   0x00013e99      0x19b ./Core/Src/system_stm32l1xx.o
- .debug_macro   0x00014034      0x1bf ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
- .debug_macro   0x000141f3      0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
- .debug_macro   0x0001438e      0x1a2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
- .debug_macro   0x00014530      0x1ad ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
- .debug_macro   0x000146dd      0x19c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+.debug_macro    0x00000000    0x154c6
+ .debug_macro   0x00000000      0x1be ./Core/Src/main.o
+ .debug_macro   0x000001be      0xacc ./Core/Src/main.o
+ .debug_macro   0x00000c8a      0x10f ./Core/Src/main.o
+ .debug_macro   0x00000d99       0x2e ./Core/Src/main.o
+ .debug_macro   0x00000dc7       0x22 ./Core/Src/main.o
+ .debug_macro   0x00000de9       0x22 ./Core/Src/main.o
+ .debug_macro   0x00000e0b       0x8e ./Core/Src/main.o
+ .debug_macro   0x00000e99       0x51 ./Core/Src/main.o
+ .debug_macro   0x00000eea      0x103 ./Core/Src/main.o
+ .debug_macro   0x00000fed       0x6a ./Core/Src/main.o
+ .debug_macro   0x00001057      0x1df ./Core/Src/main.o
+ .debug_macro   0x00001236       0x1c ./Core/Src/main.o
+ .debug_macro   0x00001252       0x22 ./Core/Src/main.o
+ .debug_macro   0x00001274       0xbd ./Core/Src/main.o
+ .debug_macro   0x00001331      0xe49 ./Core/Src/main.o
+ .debug_macro   0x0000217a      0x11f ./Core/Src/main.o
+ .debug_macro   0x00002299     0xb7a1 ./Core/Src/main.o
+ .debug_macro   0x0000da3a       0x6d ./Core/Src/main.o
+ .debug_macro   0x0000daa7     0x34e1 ./Core/Src/main.o
+ .debug_macro   0x00010f88      0x190 ./Core/Src/main.o
+ .debug_macro   0x00011118       0x5b ./Core/Src/main.o
+ .debug_macro   0x00011173      0xe37 ./Core/Src/main.o
+ .debug_macro   0x00011faa      0x35b ./Core/Src/main.o
+ .debug_macro   0x00012305      0x1b8 ./Core/Src/main.o
+ .debug_macro   0x000124bd       0xc5 ./Core/Src/main.o
+ .debug_macro   0x00012582      0x21e ./Core/Src/main.o
+ .debug_macro   0x000127a0      0x236 ./Core/Src/main.o
+ .debug_macro   0x000129d6      0x115 ./Core/Src/main.o
+ .debug_macro   0x00012aeb      0x567 ./Core/Src/main.o
+ .debug_macro   0x00013052      0x1e9 ./Core/Src/main.o
+ .debug_macro   0x0001323b       0x22 ./Core/Src/main.o
+ .debug_macro   0x0001325d      0x788 ./Core/Src/main.o
+ .debug_macro   0x000139e5       0xac ./Core/Src/main.o
+ .debug_macro   0x00013a91      0x2aa ./Core/Src/main.o
+ .debug_macro   0x00013d3b      0x170 ./Core/Src/main.o
+ .debug_macro   0x00013eab      0x492 ./Core/Src/main.o
+ .debug_macro   0x0001433d       0x4c ./Core/Src/main.o
+ .debug_macro   0x00014389      0x1be ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_macro   0x00014547      0x1c8 ./Core/Src/stm32l1xx_it.o
+ .debug_macro   0x0001470f      0x1af ./Core/Src/system_stm32l1xx.o
+ .debug_macro   0x000148be      0x1d3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_macro   0x00014a91      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_macro   0x00014c40      0x1b6 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_macro   0x00014df6      0x1c1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_macro   0x00014fb7      0x1b0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_macro   0x00015167      0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_macro   0x00015316      0x1b0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
-.debug_line     0x00000000     0x7071
- .debug_line    0x00000000      0x799 ./Core/Src/main.o
- .debug_line    0x00000799      0x6df ./Core/Src/stm32l1xx_hal_msp.o
- .debug_line    0x00000e78      0x757 ./Core/Src/stm32l1xx_it.o
- .debug_line    0x000015cf      0x731 ./Core/Src/system_stm32l1xx.o
- .debug_line    0x00001d00       0x79 ./Core/Startup/startup_stm32l152retx.o
- .debug_line    0x00001d79      0x95c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
- .debug_line    0x000026d5      0xc2b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
- .debug_line    0x00003300      0x9a0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
- .debug_line    0x00003ca0      0xf20 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
- .debug_line    0x00004bc0     0x24b1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+.debug_line     0x00000000     0xa9dc
+ .debug_line    0x00000000      0x817 ./Core/Src/main.o
+ .debug_line    0x00000817      0x74b ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_line    0x00000f62      0x7a6 ./Core/Src/stm32l1xx_it.o
+ .debug_line    0x00001708      0x762 ./Core/Src/system_stm32l1xx.o
+ .debug_line    0x00001e6a       0x79 ./Core/Startup/startup_stm32l152retx.o
+ .debug_line    0x00001ee3      0x98d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_line    0x00002870      0xc5c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_line    0x000034cc      0x9d1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_line    0x00003e9d      0xf51 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_line    0x00004dee     0x2fb2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_line    0x00007da0      0x75a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_line    0x000084fa     0x24e2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
-.debug_str      0x00000000    0x819bb
- .debug_str     0x00000000    0x819bb ./Core/Src/main.o
-                              0x8096e (size before relaxing)
- .debug_str     0x000819bb    0x803d4 ./Core/Src/stm32l1xx_hal_msp.o
- .debug_str     0x000819bb    0x7ff6c ./Core/Src/stm32l1xx_it.o
- .debug_str     0x000819bb    0x7fe7b ./Core/Src/system_stm32l1xx.o
- .debug_str     0x000819bb       0x85 ./Core/Startup/startup_stm32l152retx.o
- .debug_str     0x000819bb    0x805a3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
- .debug_str     0x000819bb    0x806af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
- .debug_str     0x000819bb    0x8000e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
- .debug_str     0x000819bb    0x80337 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
- .debug_str     0x000819bb    0x808e0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+.debug_str      0x00000000    0x88e84
+ .debug_str     0x00000000    0x88e84 ./Core/Src/main.o
+                              0x86fe0 (size before relaxing)
+ .debug_str     0x00088e84    0x86d8d ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_str     0x00088e84    0x8678f ./Core/Src/stm32l1xx_it.o
+ .debug_str     0x00088e84    0x8618a ./Core/Src/system_stm32l1xx.o
+ .debug_str     0x00088e84       0x85 ./Core/Startup/startup_stm32l152retx.o
+ .debug_str     0x00088e84    0x868b2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_str     0x00088e84    0x869be ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_str     0x00088e84    0x8631d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_str     0x00088e84    0x86646 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_str     0x00088e84    0x8748d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_str     0x00088e84    0x86632 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_str     0x00088e84    0x86bef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
 .comment        0x00000000       0x43
  .comment       0x00000000       0x43 ./Core/Src/main.o
@@ -2780,22 +3278,26 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id
  .comment       0x00000043       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
  .comment       0x00000043       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
  .comment       0x00000043       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .comment       0x00000043       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .comment       0x00000043       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
  .comment       0x00000043       0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
 
-.debug_frame    0x00000000     0x184c
- .debug_frame   0x00000000       0xd4 ./Core/Src/main.o
- .debug_frame   0x000000d4       0x7c ./Core/Src/stm32l1xx_hal_msp.o
- .debug_frame   0x00000150      0x120 ./Core/Src/stm32l1xx_it.o
- .debug_frame   0x00000270       0x58 ./Core/Src/system_stm32l1xx.o
- .debug_frame   0x000002c8      0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
- .debug_frame   0x00000604      0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
- .debug_frame   0x00000aec      0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
- .debug_frame   0x00000c38      0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
- .debug_frame   0x00000e5c      0x944 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
- .debug_frame   0x000017a0       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o)
- .debug_frame   0x000017c0       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o)
- .debug_frame   0x000017ec       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o)
- .debug_frame   0x00001818       0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o)
+.debug_frame    0x00000000     0x2ae8
+ .debug_frame   0x00000000       0xf8 ./Core/Src/main.o
+ .debug_frame   0x000000f8       0xc4 ./Core/Src/stm32l1xx_hal_msp.o
+ .debug_frame   0x000001bc      0x13c ./Core/Src/stm32l1xx_it.o
+ .debug_frame   0x000002f8       0x58 ./Core/Src/system_stm32l1xx.o
+ .debug_frame   0x00000350      0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
+ .debug_frame   0x0000068c      0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
+ .debug_frame   0x00000b74      0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o
+ .debug_frame   0x00000cc0      0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o
+ .debug_frame   0x00000ee4     0x11b4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o
+ .debug_frame   0x00002098       0x60 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o
+ .debug_frame   0x000020f8      0x944 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o
+ .debug_frame   0x00002a3c       0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o)
+ .debug_frame   0x00002a5c       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o)
+ .debug_frame   0x00002a88       0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o)
+ .debug_frame   0x00002ab4       0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o)
 
 .debug_line_str
                 0x00000000       0x69
diff --git a/TD-1-test/Debug/objects.list b/TD-1-test/Debug/objects.list
index 9bee5b4..4ca9df2 100644
--- a/TD-1-test/Debug/objects.list
+++ b/TD-1-test/Debug/objects.list
@@ -17,4 +17,6 @@
 "./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o"
 "./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o"
 "./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o"
+"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o"
+"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o"
 "./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o"
diff --git a/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h
new file mode 100644
index 0000000..cf4398e
--- /dev/null
+++ b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h
@@ -0,0 +1,1854 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_hal_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L1xx_HAL_TIM_H
+#define STM32L1xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_hal_def.h"
+
+/** @addtogroup STM32L1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_ClockDivision */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
+                               This parameter can be a value of @ref TIM_Output_Fast_State
+                               @note This parameter is valid only in PWM1 and PWM2 mode. */
+} TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the TIM mode.
+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;   /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t ICSelection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t ICFilter;     /*!< Specifies the input capture filter.
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+  * @brief  TIM Encoder Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Mode */
+
+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC1Selection;  /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
+
+  uint32_t IC2Selection;  /*!< Specifies the input.
+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
+                                 This parameter can be a value of @ref TIM_Clock_Polarity */
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
+typedef struct
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
+                                      ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  TIM Channel States definition
+  */
+typedef enum
+{
+  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
+  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
+  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
+} HAL_TIM_ChannelStateTypeDef;
+
+/**
+  * @brief  DMA Burst States definition
+  */
+typedef enum
+{
+  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
+  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
+  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
+typedef enum
+{
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+  TIM_TypeDef                        *Instance;         /*!< Register base address                             */
+  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
+  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
+  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
+                                                             This array is accessed by a @ref DMA_Handle_index */
+  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
+  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
+  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[4];   /*!< TIM channel operation state                       */
+  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                               */
+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                             */
+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                 */
+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                               */
+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                 */
+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                               */
+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                                */
+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                              */
+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                          */
+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                        */
+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                            */
+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                          */
+  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
+  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
+  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
+  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
+  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
+  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
+  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID                         */
+  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+  * @{
+  */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
+#define TIM_CLEARINPUTSOURCE_OCREFCLR       0x00000002U   /*!< OCREF_CLR is connected to OCREF_CLR_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+  * @{
+  */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
+#define TIM_DMABASE_OR                     0x00000014U
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+  * @{
+  */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+  * @{
+  */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+  * @{
+  */
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+  * @{
+  */
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+  * @{
+  */
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+  * @{
+  */
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+  * @{
+  */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+  * @{
+  */
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+  * @{
+  */
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+  * @{
+  */
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+  * @{
+  */
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+  * @{
+  */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+  * @{
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+  * @{
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+  * @{
+  */
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+  * @{
+  */
+#define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+  * @{
+  */
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Channel TIM Channel
+  * @{
+  */
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+  * @{
+  */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+  * @{
+  */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+  * @{
+  */
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+  * @{
+  */
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+  * @{
+  */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+  * @{
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+  * @{
+  */
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+  * @{
+  */
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+  * @{
+  */
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+  * @{
+  */
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+  * @{
+  */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+  * @{
+  */
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+  * @{
+  */
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+  * @{
+  */
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+  * @{
+  */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+  * @}
+  */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+  * @{
+  */
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
+                                                     } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
+                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
+                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
+                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
+                                                     } while(0)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+  * @brief  Disable the TIM peripheral.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+    } \
+  } while(0)
+
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  * @retval None
+  */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+  *       or Encoder mode.
+  */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+  * @brief  Set the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+  */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
+/**
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  * @retval None
+  */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+  */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+  *         function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__HANDLE__)->Instance->CCR4))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
+
+/**
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
+  *        overflow/underflow generates an update interrupt or DMA request (if
+  *        enabled)
+  * @retval None
+  */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
+  *        enabled):
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
+  * @retval None
+  */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __POLARITY__ Polarity for TIx source
+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+  * @retval None
+  */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/** @brief  Select the Capture/compare DMA request source.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __CCDMA__ specifies Capture/compare DMA request source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+  *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+  * @retval None
+  */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
+  MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)       || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_OR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+                                               (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) :        \
+                                               ((__PERIOD__) > 0U))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3)    || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1)  || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2)  || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
+   (__HANDLE__)->ChannelState[3])
+
+#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
+   ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
+
+#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__)\
+  do {\
+    (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);\
+    (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);\
+    (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);\
+    (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);\
+  } while(0)
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32l1xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
+  * @{
+  */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
+  * @{
+  */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
+  * @{
+  */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
+  * @{
+  */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
+  * @{
+  */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
+  * @{
+  */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
+  * @{
+  */
+/* Interrupt Handler functions  ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
+  * @{
+  */
+/* Control functions  *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer,
+                                              uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t BurstLength,  uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
+  * @{
+  */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
+
+/* Peripheral Channel state functions  ************************************************/
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L1xx_HAL_TIM_H */
diff --git a/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h
new file mode 100644
index 0000000..6e7a0a8
--- /dev/null
+++ b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h
@@ -0,0 +1,179 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L1xx_HAL_TIM_EX_H
+#define STM32L1xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_hal_def.h"
+
+/** @addtogroup STM32L1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+/* @note STM32L1XX devices are organized in 6 categories: Cat.1, Cat.2, Cat.3, Cat.4, Cat.5, Cat.6.
+         Remap capabilities depend on the device category. As the DMA2 controller is available only in
+         Cat.3, Cat.4,Cat.5 and Cat.6 devices it is used to discriminate Cat.1 and Cat.2 devices v.s.
+         Cat.3, Cat.4, Cat.5 and Cat.6 devices. */
+#if defined(DMA2)
+#define TIM_TIM2_ITR1_TIM10_OC        (0x00000000)       /*!< TIM2 ITR1 input is connected to TIM10 OC */
+#define TIM_TIM2_ITR1_TIM5_TGO        TIM2_OR_ITR1_RMP   /*!< TIM2 ITR1 input is connected to TIM5 TGO */
+#endif /* DMA2 */
+
+#if defined(DMA2)
+#define TIM_TIM3_ITR2_TIM11_OC        (0x00000000)       /*!< TIM3 ITR2 input is connected to TIM11 OC */
+#define TIM_TIM3_ITR2_TIM5_TGO        TIM2_OR_ITR1_RMP   /*!< TIM3 ITR2 input is connected to TIM5 TGO */
+#endif /* DMA2 */
+
+#if defined(DMA2)
+#define TIM_TIM9_ITR1_TIM3_TGO        (0x00000000)       /*!< TIM9 ITR1 input is connected to TIM3 TGO */
+#define TIM_TIM9_ITR1_TS              TIM9_OR_ITR1_RMP   /*!< TIM9 ITR1 input is connected to touch sensing I/O */
+#endif /* DMA2 */
+#define TIM_TIM9_GPIO                 (0x00000000)       /*!< TIM9 Channel1 is connected to GPIO */
+#define TIM_TIM9_LSE                  TIM_OR_TI1RMP_0    /*!< TIM9 Channel1 is connected to LSE internal clock */
+#define TIM_TIM9_GPIO1                TIM_OR_TI1RMP_1    /*!< TIM9 Channel1 is connected to GPIO */
+#define TIM_TIM9_GPIO2                TIM_OR_TI1RMP      /*!< TIM9 Channel1 is connected to GPIO */
+
+#if defined(DMA2)
+#define TIM_TIM10_TI1RMP              (0x00000000)       /*!< TIM10 Channel 1 depends on TI1_RMP */
+#define TIM_TIM10_RI                  TIM_OR_TI1_RMP_RI  /*!< TIM10 Channel 1 is connected to RI */
+#define TIM_TIM10_ETR_LSE             (0x00000000)       /*!< TIM10 ETR input is connected to LSE clock */
+#define TIM_TIM10_ETR_TIM9_TGO        TIM_OR_ETR_RMP     /*!< TIM10 ETR input is connected to TIM9 TGO */
+#endif /* DMA2 */
+#define TIM_TIM10_GPIO                (0x00000000)       /*!< TIM10 Channel1 is connected to GPIO */
+#define TIM_TIM10_LSI                 TIM_OR_TI1RMP_0    /*!< TIM10 Channel1 is connected to LSI internal clock */
+#define TIM_TIM10_LSE                 TIM_OR_TI1RMP_1    /*!< TIM10 Channel1 is connected to LSE internal clock */
+#define TIM_TIM10_RTC                 TIM_OR_TI1RMP      /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */
+
+#if defined(DMA2)
+#define TIM_TIM11_TI1RMP              (0x00000000)       /*!< TIM11 Channel 1 depends on TI1_RMP */
+#define TIM_TIM11_RI                  TIM_OR_TI1_RMP_RI  /*!< TIM11 Channel 1 is connected to RI */
+#define TIM_TIM11_ETR_LSE             (0x00000000)       /*!< TIM11 ETR input is connected to LSE clock */
+#define TIM_TIM11_ETR_TIM9_TGO        TIM_OR_ETR_RMP     /*!< TIM11 ETR input is connected to TIM9 TGO */
+#endif /* DMA2 */
+#define TIM_TIM11_GPIO                (0x00000000)       /*!< TIM11 Channel1 is connected to GPIO */
+#define TIM_TIM11_MSI                 TIM_OR_TI1RMP_0    /*!< TIM11 Channel1 is connected to MSI internal clock */
+#define TIM_TIM11_HSE_RTC             TIM_OR_TI1RMP_1    /*!< TIM11 Channel1 is connected to HSE_RTC clock */
+#define TIM_TIM11_GPIO1               TIM_OR_TI1RMP      /*!< TIM11 Channel1 is connected to GPIO */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#if defined(DMA2)
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)               \
+  ( (((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO)))  || \
+    (((INSTANCE) == TIM3)  && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO)))  || \
+    (((INSTANCE) == TIM9)  && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2)))                                  || \
+    (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC)))              || \
+    (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1)))               \
+  )
+#else
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)               \
+  ( (((INSTANCE) == TIM9)  && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2)))       || \
+    (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC)))       || \
+    (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1)))    \
+  )
+#endif /* DMA2 */
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32L1xx_HAL_TIM_EX_H */
diff --git a/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h
new file mode 100644
index 0000000..01662bc
--- /dev/null
+++ b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_tim.h
@@ -0,0 +1,3342 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_LL_TIM_H
+#define __STM32L1xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx.h"
+
+/** @addtogroup STM32L1xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: NA */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: NA */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x00U,   /* 5: NA */
+  0x04U    /* 6: TIMx_CH4  */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U             /* 6: OC4M, OC4FE, OC4PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U             /* 6: CC4S, IC4PSC, IC4F */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  0U,            /* 1: NA */
+  4U,            /* 2: CC2P */
+  0U,            /* 3: NA */
+  8U,            /* 4: CC3P */
+  0U,            /* 5: NA */
+  12U            /* 6: CC4P */
+};
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+
+#define TIMx_OR_RMP_SHIFT  16U
+#define TIMx_OR_RMP_MASK   0x0000FFFFU
+#define TIM_OR_RMP_MASK    ((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT)
+#define TIM9_OR_RMP_MASK   ((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
+#define TIM2_OR_RMP_MASK   (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM3_OR_RMP_MASK   (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT)
+
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+
+
+
+
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR            (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_OR register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM10_TI1_RMP  TIM10 input 1 remapping capability
+  * @{
+  */
+#define LL_TIM_TIM10_TI1_RMP_GPIO   TIM_OR_RMP_MASK                                         /*!< TIM10 channel1 is connected to GPIO */
+#define LL_TIM_TIM10_TI1_RMP_LSI    (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK)                     /*!< TIM10 channel1 is connected to LSI internal clock */
+#define LL_TIM_TIM10_TI1_RMP_LSE    (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)                     /*!< TIM10 channel1 is connected to LSE internal clock */
+#define LL_TIM_TIM10_TI1_RMP_RTC    (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)   /*!< TIM10 channel1 is connected to RTC wakeup interrupt signal */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM10_ETR_RMP  TIM10 ETR remap
+  * @{
+  */
+#define LL_TIM_TIM10_ETR_RMP_LSE      TIM_OR_RMP_MASK                                         /*!< TIM10 ETR input is connected to LSE */
+#define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK)                      /*!< TIM10 ETR input is connected to TIM9 TGO */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
+  * @{
+  */
+#define LL_TIM_TIM10_TI1_RMP          TIM_OR_RMP_MASK                                         /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */
+#define LL_TIM_TIM10_TI1_RMP_RI       (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK)                   /*!< TIM10 channel1 is connected to RI */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM11_TI1_RMP  TIM11 input 1 remapping capability
+  * @{
+  */
+#define LL_TIM_TIM11_TI1_RMP_GPIO       TIM_OR_RMP_MASK                                       /*!< TIM11 channel1 is connected to GPIO */
+#define LL_TIM_TIM11_TI1_RMP_MSI        (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to MSI internal clock */
+#define LL_TIM_TIM11_TI1_RMP_HSE_RTC    (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to HSE RTC clock */
+#define LL_TIM_TIM11_TI1_RMP_GPIO1      (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM11_ETR_RMP  TIM11 ETR remap
+  * @{
+  */
+#define LL_TIM_TIM11_ETR_RMP_LSE      TIM_OR_RMP_MASK                                         /*!< TIM11 ETR input is connected to LSE */
+#define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK)                      /*!< TIM11 ETR input is connected to TIM9 TGO clock */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
+  * @{
+  */
+#define LL_TIM_TIM11_TI1_RMP          TIM_OR_RMP_MASK                                         /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */
+#define LL_TIM_TIM11_TI1_RMP_RI       (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to RI */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
+  * @{
+  */
+#define LL_TIM_TIM9_TI1_RMP_GPIO     TIM9_OR_RMP_MASK                                          /*!< TIM9 channel1 is connected to GPIO */
+#define LL_TIM_TIM9_TI1_RMP_LSE      (TIM_OR_TI1RMP_0 | TIM9_OR_RMP_MASK)                      /*!< TIM9 channel1 is connected to LSE internal clock */
+#define LL_TIM_TIM9_TI1_RMP_GPIO1    (TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK)                      /*!< TIM9 channel1 is connected to GPIO */
+#define LL_TIM_TIM9_TI1_RMP_GPIO2    (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK)    /*!< TIM9 channel1 is connected to GPIO */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM9_ITR1_RMP  TIM9 ITR1 remap
+  * @{
+  */
+#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO   TIM9_OR_RMP_MASK                                     /*!< TIM9 channel1 is connected to TIM3 TGO signal */
+#define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO   (TIM9_OR_ITR1_RMP | TIM9_OR_RMP_MASK)                /*!< TIM9 channel1 is connected to touch sensing I/O */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP  TIM2 internal trigger 1 remap
+  * @{
+  */
+#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC    TIM9_OR_RMP_MASK                                     /*!< TIM2 ITR1 input is connected to TIM10 OC*/
+#define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO    (TIM2_OR_ITR1_RMP | TIM9_OR_RMP_MASK)                /*!< TIM2 ITR1 input is connected to TIM5 TGO */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_ITR2_RMP  TIM3 internal trigger 2 remap
+  * @{
+  */
+#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC    TIM9_OR_RMP_MASK                                     /*!< TIM3 ITR2 input is connected to TIM11 OC */
+#define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO    (TIM3_OR_ITR2_RMP | TIM9_OR_RMP_MASK)                /*!< TIM3 ITR2 input is connected to TIM5 TGO */
+/**
+  * @}
+  */
+
+
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+  * @{
+  */
+#define LL_TIM_OCREF_CLR_INT_OCREF_CLR     0x00000000U         /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
+#define LL_TIM_OCREF_CLR_INT_ETR           TIM_SMCR_OCCS       /*!< OCREF_CLR_INT is connected to ETRF */
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  * @rmtoll  TIM2_OR     ITR1_RMP      LL_TIM_SetRemap\n
+  *         TIM3_OR     ITR2_RMP      LL_TIM_SetRemap\n
+  *         TIM9_OR     TI1_RMP       LL_TIM_SetRemap\n
+  *         TIM9_OR     ITR1_RMP      LL_TIM_SetRemap\n
+  *         TIM10_OR    TI1_RMP       LL_TIM_SetRemap\n
+  *         TIM10_OR    ETR_RMP       LL_TIM_SetRemap\n
+  *         TIM10_OR    TI1_RMP_RI    LL_TIM_SetRemap\n
+  *         TIM11_OR    TI1_RMP       LL_TIM_SetRemap\n
+  *         TIM11_OR    ETR_RMP       LL_TIM_SetRemap\n
+  *         TIM11_OR    TI1_RMP_RI    LL_TIM_SetRemap
+  * @param  TIMx Timer instance
+  * @param  Remap Remap params depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of OR registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  *         TIM2: any combination of ITR1_RMP where
+  *
+  *            . . ITR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM10_OC  (**)
+  *            @arg @ref LL_TIM_TIM2_TIR1_RMP_TIM5_TGO  (**)
+  *
+  *         TIM3: any combination of ITR2_RMP where
+  *
+  *            . . ITR2_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM11_OC  (**)
+  *            @arg @ref LL_TIM_TIM3_TIR2_RMP_TIM5_TGO  (**)
+  *
+  *         TIM9: any combination of TI1_RMP, ITR1_RMP where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM9_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
+  *
+  *            . . ITR1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TGO  (*)
+  *            @arg @ref LL_TIM_TIM9_ITR1_RMP_TOUCH_IO  (*)
+  *
+  *
+  *         TIM10: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI   where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
+  *            @arg @ref LL_TIM_TIM10_TI1_RMP_LSI
+  *            @arg @ref LL_TIM_TIM10_TI1_RMP_LSE
+  *            @arg @ref LL_TIM_TIM10_TI1_RMP_RTC
+  *
+  *            . . ETR_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM10_ETR_RMP_TIM9_TGO  (*)
+  *
+  *            . . TI1_RMP_RI can be one of the following values
+  *            @arg @ref LL_TIM_TIM10_TI1_RMP_RI        (*)
+  *
+  *
+  *         TIM11: any combination of TI1_RMP, ETR_RMP, TI1_RMP_RI   where
+  *
+  *            . . TI1_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_MSI
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP
+  *
+  *            . . ETR_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM11_ETR_RMP_TIM9_TGO  (*)
+  *
+  *            . . TI1_RMP_RI can be one of the following values
+  *            @arg @ref LL_TIM_TIM11_TI1_RMP_RI        (*)
+  *
+  *           (*) value not available in all devices categories
+  *           (**) register not available in all devices categories
+  *
+  * @note Option registers are available only for cat.3, cat.4 and cat.5  devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+  * @{
+  */
+/**
+  * @brief  Set the OCREF clear input source
+  * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+  * @note This function can only be used in Output compare and PWM modes.
+  * @note the ETR signal can be connected to the output of a comparator to be used for current handling
+  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
+  * @param  TIMx Timer instance
+  * @param  OCRefClearInputSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_LL_TIM_H */
diff --git a/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c
new file mode 100644
index 0000000..19b9d7f
--- /dev/null
+++ b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c
@@ -0,0 +1,7188 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_hal_tim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer (TIM) peripheral:
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
+  *           + Commutation Event configuration with Interruption and DMA
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Generic features #####
+  ==============================================================================
+  [..] The Timer features include:
+       (#) 16-bit up, down, up/down auto-reload counter.
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+           counter clock frequency either by any factor between 1 and 65536.
+       (#) Up to 4 independent channels for:
+           (++) Input Capture
+           (++) Output Compare
+           (++) PWM generation (Edge and Center-aligned Mode)
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
+           (++) Input Capture : HAL_TIM_IC_MspInit()
+           (++) Output Compare : HAL_TIM_OC_MspInit()
+           (++) PWM generation : HAL_TIM_PWM_MspInit()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+     (#) Initialize the TIM low level resources :
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+        (##) TIM pins configuration
+            (+++) Enable the clock for the TIM GPIOs using the following function:
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+     (#) The external Clock can be configured, if needed (the default clock is the
+         internal clock from the APBx), using the following function:
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
+         any start function.
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+     (#) The DMA Burst is managed with the two following functions:
+         HAL_TIM_DMABurst_WriteStart()
+         HAL_TIM_DMABurst_ReadStart()
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function HAL_TIM_RegisterCallback() to register a callback.
+  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_hal.h"
+
+/** @addtogroup STM32L1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIM TIM
+  * @brief TIM HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+  * @{
+  */
+static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM base.
+    (+) De-initialize the TIM base.
+    (+) Start the Time Base.
+    (+) Stop the Time Base.
+    (+) Start the Time Base and enable interrupt.
+    (+) Stop the Time Base and disable interrupt.
+    (+) Start the Time Base and enable DMA transfer.
+    (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Time base Unit according to the specified
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Base MSP.
+  * @param  htim TIM Base handle
+  * @retval None
+  */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Base_MspDeInit could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Starts the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Set the TIM state */
+  if (htim->State == HAL_TIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->State == HAL_TIM_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->State = HAL_TIM_STATE_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA Period elapsed callbacks */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+  /* Set the DMA error callback */
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+                       Length) != HAL_OK)
+  {
+    /* Return error status */
+    return HAL_ERROR;
+  }
+
+  /* Enable the TIM Update DMA request */
+  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Base generation in DMA mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  /* Disable the TIM Update DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### TIM Output Compare functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Output Compare.
+    (+) De-initialize the TIM Output Compare.
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Output Compare according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Output Compare MSP.
+  * @param  htim TIM Output Compare handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Output compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM PWM functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM PWM.
+    (+) De-initialize the TIM PWM.
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM PWM Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM PWM MSP.
+  * @param  htim TIM PWM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the PWM signal generation.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the PWM signal generation.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the PWM signal generation in interrupt mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Set the TIM channel state */
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Output Capture/Compare 3 request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM PWM signal generation in DMA mode.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
+  ==============================================================================
+              ##### TIM Input Capture functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+   (+) Initialize and configure the TIM Input Capture.
+   (+) De-initialize the TIM Input Capture.
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Input Capture Time base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+  HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Change the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Input Capture MSP.
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpsmcr;
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  /* Check the TIM channel state */
+  if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Enable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Enable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Enable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Enable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4 interrupt */
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel state */
+  if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  if (channel_state == HAL_TIM_CHANNEL_STATE_READY)
+  {
+    if ((pData == NULL) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 2  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    {
+      __HAL_TIM_ENABLE(htim);
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Disable the TIM Capture/Compare 1 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Disable the TIM Capture/Compare 2 DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Disable the TIM Capture/Compare 3  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Disable the TIM Capture/Compare 4  DMA request */
+      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return status;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM One Pulse functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM One Pulse.
+    (+) De-initialize the TIM One Pulse.
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM One Pulse Time Base according to the specified
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @note   When the timer instance is initialized in One Pulse mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
+  *         This parameter can be one of the following values:
+  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Configure the Time base in the One Pulse Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Reset the OPM Bit */
+  htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  htim->Instance->CR1 |= OnePulseMode;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channel state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM One Pulse MSP.
+  * @param  htim TIM One Pulse handle
+  * @retval None
+  */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Check the TIM channels state */
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+
+  /* Enable the Capture compare and the Input Capture channels
+    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
+    (the counter starts in response to a stimulus and generate a pulse */
+
+  /* Enable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+  /* Enable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
+  * @note Though OutputChannel parameter is deprecated and ignored by the function
+  *        it has been kept to avoid HAL_TIM API compatibility break.
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel See note above
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the TIM Capture/Compare 1 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+  /* Disable the TIM Capture/Compare 2 interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+  /* Disable the Capture compare and the Input Capture channels
+  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
+  ==============================================================================
+                          ##### TIM Encoder functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize and configure the TIM Encoder.
+    (+) De-initialize the TIM Encoder.
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @note   When the timer instance is initialized in Encoder mode, timer
+  *         channels 1 and channel 2 are reserved and cannot be used for other
+  *         purpose.
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
+{
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+  /* Configure the Time base in the Encoder Mode */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = htim->Instance->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = htim->Instance->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr |= sConfig->EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  htim->Instance->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  htim->Instance->CCER = tmpccer;
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Disable the TIM Peripheral Clock */
+  __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
+  /* Set the TIM channels state */
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes TIM Encoder Interface MSP.
+  * @param  htim TIM Encoder Interface handle
+  * @retval None
+  */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
+    }
+  }
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
+    }
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+  else
+  {
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+    }
+  }
+
+  /* Enable the encoder interface channels */
+  /* Enable the capture compare Interrupts 1 and/or 2 */
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+
+    default :
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
+    }
+  }
+
+  /* Enable the Peripheral */
+  __HAL_TIM_ENABLE(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in interrupt mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare Interrupts 1 and 2 */
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Starts the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
+{
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Set the TIM channel(s) state */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+    {
+      return HAL_BUSY;
+    }
+    else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+    {
+      if ((pData1 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+    {
+      return HAL_BUSY;
+    }
+    else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+    {
+      if ((pData2 == NULL) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+    {
+      return HAL_BUSY;
+    }
+    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+    {
+      if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+      }
+    }
+    else
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+
+    default:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      /* Enable the TIM Input Capture  DMA request */
+      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
+      break;
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stops the TIM Encoder Interface in DMA mode.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+  else
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+    /* Disable the capture compare DMA Request 1 and 2 */
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
+
+  /* Disable the Peripheral */
+  __HAL_TIM_DISABLE(htim);
+
+  /* Set the TIM channel(s) state */
+  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
+  {
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
+  ==============================================================================
+                        ##### IRQ handler management #####
+  ==============================================================================
+  [..]
+    This section provides Timer IRQ handler function.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+  uint32_t itsource = htim->Instance->DIER;
+  uint32_t itflag   = htim->Instance->SR;
+
+  /* Capture compare 1 event */
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+  {
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+    {
+      {
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        /* Output compare event */
+        else
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+  {
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 3 event */
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+  {
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* Capture compare 4 event */
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+  {
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      /* Output compare event */
+      else
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+    }
+  }
+  /* TIM Update event */
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+  {
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+  {
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                   ##### Peripheral Control functions #####
+  ==============================================================================
+ [..]
+   This section provides functions allowing to:
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM Output Compare Channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 1 in Output Compare */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 2 in Output Compare */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 3 in Output Compare */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the TIM Channel 4 in Output Compare */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM Input Capture Channels according to the specified
+  *         parameters in the TIM_IC_InitTypeDef.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  if (Channel == TIM_CHANNEL_1)
+  {
+    /* TI1 Configuration */
+    TIM_TI1_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC1PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+    /* Set the IC1PSC value */
+    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    /* TI2 Configuration */
+    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+    TIM_TI2_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC2PSC Bits */
+    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+    /* Set the IC2PSC value */
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+  }
+  else if (Channel == TIM_CHANNEL_3)
+  {
+    /* TI3 Configuration */
+    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC3PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+    /* Set the IC3PSC value */
+    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+  }
+  else if (Channel == TIM_CHANNEL_4)
+  {
+    /* TI4 Configuration */
+    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
+    /* Reset the IC4PSC Bits */
+    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+    /* Set the IC4PSC value */
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM PWM  channels according to the specified
+  *         parameters in the TIM_OC_InitTypeDef.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 1 in PWM mode */
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel1 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 2 in PWM mode */
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel2 */
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 3 in PWM mode */
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel3 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Configure the Channel 4 in PWM mode */
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+      /* Set the Preload enable bit for channel4 */
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+      /* Configure the Output Fast mode */
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the TIM One Pulse Channels according to the specified
+  *         parameters in the TIM_OnePulse_InitTypeDef.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @param  InputChannel TIM input Channel to configure
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  TIM_OC_InitTypeDef temp1;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+  if (OutputChannel != InputChannel)
+  {
+    /* Process Locked */
+    __HAL_LOCK(htim);
+
+    htim->State = HAL_TIM_STATE_BUSY;
+
+    /* Extract the Output compare configuration from sConfig structure */
+    temp1.OCMode = sConfig->OCMode;
+    temp1.Pulse = sConfig->Pulse;
+    temp1.OCPolarity = sConfig->OCPolarity;
+
+    switch (OutputChannel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      case TIM_CHANNEL_2:
+      {
+        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+        TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
+      }
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+
+    if (status == HAL_OK)
+    {
+      switch (InputChannel)
+      {
+        case TIM_CHANNEL_1:
+        {
+          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC1PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        case TIM_CHANNEL_2:
+        {
+          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC2PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        default:
+          status = HAL_ERROR;
+          break;
+      }
+    }
+
+    htim->State = HAL_TIM_STATE_READY;
+
+    __HAL_UNLOCK(htim);
+
+    return status;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                              uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                            ((BurstLength) >> 8U) + 1U);
+
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t  BurstLength,  uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA compare callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
+{
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                           ((BurstLength) >> 8U) + 1U);
+
+
+  return status;
+}
+
+/**
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
+  *            @arg TIM_DMABASE_CR2
+  *            @arg TIM_DMABASE_SMCR
+  *            @arg TIM_DMABASE_DIER
+  *            @arg TIM_DMABASE_SR
+  *            @arg TIM_DMABASE_EGR
+  *            @arg TIM_DMABASE_CCMR1
+  *            @arg TIM_DMABASE_CCMR2
+  *            @arg TIM_DMABASE_CCER
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
+  *            @arg TIM_DMABASE_ARR
+  *            @arg TIM_DMABASE_CCR1
+  *            @arg TIM_DMABASE_CCR2
+  *            @arg TIM_DMABASE_CCR3
+  *            @arg TIM_DMABASE_CCR4
+  *            @arg TIM_DMABASE_OR
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  DataLength Data length. This parameter can be one value
+  *         between 1 and 0xFFFF.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
+  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
+  {
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      /* Set the DMA Period elapsed callbacks */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      /* Set the DMA capture callbacks */
+      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      /* Set the DMA trigger callbacks */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+      /* Set the DMA error callback */
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+                           DataLength) != HAL_OK)
+      {
+        /* Return error status */
+        return HAL_ERROR;
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+  /* Abort the DMA transfer (at least disable the DMA channel) */
+  switch (BurstRequestSrc)
+  {
+    case TIM_DMA_UPDATE:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
+    }
+    case TIM_DMA_CC1:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
+    }
+    case TIM_DMA_CC2:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
+    }
+    case TIM_DMA_CC3:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
+    }
+    case TIM_DMA_CC4:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
+    }
+    case TIM_DMA_TRIGGER:
+    {
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Generate a software event
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+  * @note   Basic timers can only generate an update event.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Set the event sources */
+  htim->Instance->EGR = EventSource;
+
+  /* Change the TIM state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the OCRef clear feature
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  switch (sClearInputConfig->ClearInputSource)
+  {
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+    case TIM_CLEARINPUTSOURCE_OCREFCLR:
+    {
+      /* Clear the OCREF clear selection bit */
+      CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+
+      /* Set the OCREF clear selection bit */
+      SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  if (status == HAL_OK)
+  {
+    switch (Channel)
+    {
+      case TIM_CHANNEL_1:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_2:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_3:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_4:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        break;
+      }
+      default:
+        break;
+    }
+  }
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief   Configures the clock source to be used
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+  htim->Instance->SMCR = tmpsmcr;
+
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INTERNAL:
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE1:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ETRMODE2:
+    {
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1ED:
+    {
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1:
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
+  *         or a XOR combination between CH1_input, CH2_input & CH3_input
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
+  *         output of a XOR gate.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+  *            pins are connected to the TI1 input (XOR combination)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+  uint32_t tmpcr2;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Reset the TI1 selection */
+  tmpcr2 &= ~TIM_CR2_TI1S;
+
+  /* Set the TI1 selection */
+  tmpcr2 |= TI1_Selection;
+
+  /* Write to TIMxCR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Disable Trigger Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIM in Slave mode in interrupt mode
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+  *         contains the selected trigger (internal trigger input, filtered
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+  __HAL_LOCK(htim);
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
+  /* Enable Trigger Interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+  /* Disable Trigger DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read the captured value from Capture Compare unit
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval Captured value
+  */
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t tmpreg = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+      /* Return the capture 1 value */
+      tmpreg =  htim->Instance->CCR1;
+
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+      /* Return the capture 2 value */
+      tmpreg =   htim->Instance->CCR2;
+
+      break;
+    }
+
+    case TIM_CHANNEL_3:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+      /* Return the capture 3 value */
+      tmpreg =   htim->Instance->CCR3;
+
+      break;
+    }
+
+    case TIM_CHANNEL_4:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+      /* Return the capture 4 value */
+      tmpreg =   htim->Instance->CCR4;
+
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### TIM Callbacks functions #####
+  ==============================================================================
+ [..]
+   This section provides TIM callback functions:
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        /* Legacy weak Period Elapsed Callback */
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        /* Legacy weak Period Elapsed half complete Callback */
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        /* Legacy weak Trigger Callback */
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        /* Legacy weak Trigger half complete Callback */
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        /* Legacy weak IC Capture Callback */
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        /* Legacy weak IC Capture half complete Callback */
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        /* Legacy weak OC Delay Elapsed Callback */
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        /* Legacy weak PWM Pulse Finished Callback */
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        /* Legacy weak PWM Pulse Finished half complete Callback */
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        /* Legacy weak Error Callback */
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM handle
+  * @retval Active channel
+  */
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
+{
+  return htim->Channel;
+}
+
+/**
+  * @brief  Return actual state of the TIM channel.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  *            @arg TIM_CHANNEL_5: TIM Channel 5
+  *            @arg TIM_CHANNEL_6: TIM Channel 6
+  * @retval TIM Channel state
+  */
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
+{
+  HAL_TIM_ChannelStateTypeDef channel_state;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
+
+  return channel_state;
+}
+
+/**
+  * @brief  Return actual state of a DMA burst operation.
+  * @param  htim TIM handle
+  * @retval DMA burst state
+  */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+  return htim->DMABurstState;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+  }
+  else
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
+    }
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+
+  /* Disable Update Event (UEV) with Update Generation (UG)
+     by changing Update Request Source (URS) to avoid Update flag (UIF) */
+  SET_BIT(TIMx->CR1, TIM_CR1_URS);
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+
+  TIMx->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Timer Output Compare 1 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC1M;
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= OC_Config->OCPolarity;
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 3 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC3M;
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= OC_Config->OCMode;
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 4 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The output configuration structure
+  * @retval None
+  */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR2_OC4M;
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = OC_Config->Pulse;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
+  * @retval None
+  */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the Trigger Selection Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source */
+  tmpsmcr |= sSlaveConfig->InputTrigger;
+
+  /* Reset the slave mode Bits */
+  tmpsmcr &= ~TIM_SMCR_SMS;
+  /* Set the slave mode */
+  tmpsmcr |= sSlaveConfig->SlaveMode;
+
+  /* Write to TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Configure the trigger prescaler, filter, and polarity */
+  switch (sSlaveConfig->InputTrigger)
+  {
+    case TIM_TS_ETRF:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+      /* Configure the ETR Trigger source */
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
+                        sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI1F_ED:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Disable the Channel 1: Reset the CC1E Bit */
+      tmpccer = htim->Instance->CCER;
+      htim->Instance->CCER &= ~TIM_CCER_CC1E;
+      tmpccmr1 = htim->Instance->CCMR1;
+
+      /* Set the filter */
+      tmpccmr1 &= ~TIM_CCMR1_IC1F;
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+      /* Write to TIMx CCMR1 and CCER registers */
+      htim->Instance->CCMR1 = tmpccmr1;
+      htim->Instance->CCER = tmpccer;
+      break;
+    }
+
+    case TIM_TS_TI1FP1:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI1 Filter and Polarity */
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_TI2FP2:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+      /* Configure TI2 Filter and Polarity */
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
+    }
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI1.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= TIM_ICPolarity;
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Select the Input */
+  tmpccmr1 &= ~TIM_CCMR1_CC2S;
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the Polarity and Filter for TI2.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |= (TIM_ICPolarity << 4U);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC3S;
+  tmpccmr2 |= TIM_ICSelection;
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC3F;
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
+  * @retval None
+  */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                              uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  tmpccer = TIMx->CCER;
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Select the Input */
+  tmpccmr2 &= ~TIM_CCMR2_CC4S;
+  tmpccmr2 |= (TIM_ICSelection << 8U);
+
+  /* Set the filter */
+  tmpccmr2 &= ~TIM_CCMR2_IC4F;
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx to select the TIM peripheral
+  * @param  InputTriggerSource The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx to select the TIM peripheral
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                              uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c
new file mode 100644
index 0000000..5e80f1f
--- /dev/null
+++ b/TD-1-test/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c
@@ -0,0 +1,226 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx_hal_tim_ex.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
+  *           + Time Master and Slave synchronization configuration
+  *           + Time OCRef clear configuration
+  *           + Timer remapping capabilities configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### TIMER Extended features #####
+  ==============================================================================
+  [..]
+    The Timer Extended features include:
+    (#) Synchronization circuit to control the timer with external signals and to
+        interconnect several timers together.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_hal.h"
+
+/** @addtogroup STM32L1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+                    ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM in master mode.
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *
+  *         For TIM2, the parameter can have the following values:(see note)
+  *            @arg TIM_TIM2_ITR1_TIM10_OC:      TIM2 ITR1 input is connected to TIM10 OC
+  *            @arg TIM_TIM2_ITR1_TIM5_TGO:      TIM2 ITR1 input is connected to TIM5 TGO
+  *
+  *         For TIM3, the parameter can have the following values:(see note)
+  *            @arg TIM_TIM3_ITR2_TIM11_OC:      TIM3 ITR2 input is connected to TIM11 OC
+  *            @arg TIM_TIM3_ITR2_TIM5_TGO:      TIM3 ITR2 input is connected to TIM5 TGO
+  *
+  *         For TIM9, the parameter is a combination of 2 fields (field1 | field2):
+  *
+  *                   field1 can have the following values:(see note)
+  *            @arg TIM_TIM9_ITR1_TIM3_TGO:      TIM9 ITR1 input is connected to TIM3 TGO
+  *            @arg TIM_TIM9_ITR1_TS:            TIM9 ITR1 input is connected to touch sensing I/O
+  *
+  *                   field2 can have the following values:
+  *            @arg TIM_TIM9_GPIO:               TIM9 Channel1 is connected to GPIO
+  *            @arg TIM_TIM9_LSE:                TIM9 Channel1 is connected to LSE internal clock
+  *            @arg TIM_TIM9_GPIO1:              TIM9 Channel1 is connected to GPIO
+  *            @arg TIM_TIM9_GPIO2:              TIM9 Channel1 is connected to GPIO
+  *
+  *         For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3):
+  *
+  *                   field1 can have the following values:(see note)
+  *            @arg TIM_TIM10_TI1RMP:            TIM10 Channel 1 depends on TI1_RMP
+  *            @arg TIM_TIM10_RI:                TIM10 Channel 1 is connected to RI
+  *
+  *                   field2 can have the following values:(see note)
+  *            @arg TIM_TIM10_ETR_LSE:           TIM10 ETR input is connected to LSE clock
+  *            @arg TIM_TIM10_ETR_TIM9_TGO:      TIM10 ETR input is connected to TIM9 TGO
+  *
+  *                   field3 can have the following values:
+  *            @arg TIM_TIM10_GPIO:              TIM10 Channel1 is connected to GPIO
+  *            @arg TIM_TIM10_LSI:               TIM10 Channel1 is connected to LSI internal clock
+  *            @arg TIM_TIM10_LSE:               TIM10 Channel1 is connected to LSE internal clock
+  *            @arg TIM_TIM10_RTC:               TIM10 Channel1 is connected to RTC wakeup interrupt
+  *
+  *         For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3):
+  *
+  *                   field1 can have the following values:(see note)
+  *            @arg TIM_TIM11_TI1RMP:            TIM11 Channel 1 depends on TI1_RMP
+  *            @arg TIM_TIM11_RI:                TIM11 Channel 1 is connected to RI
+  *
+  *                   field2 can have the following values:(see note)
+  *            @arg TIM_TIM11_ETR_LSE:           TIM11 ETR input is connected to LSE clock
+  *            @arg TIM_TIM11_ETR_TIM9_TGO:      TIM11 ETR input is connected to TIM9 TGO
+  *
+  *                   field3 can have the following values:
+  *            @arg TIM_TIM11_GPIO:     TIM11 Channel1 is connected to GPIO
+  *            @arg TIM_TIM11_MSI:      TIM11 Channel1 is connected to MSI internal clock
+  *            @arg TIM_TIM11_HSE_RTC:  TIM11 Channel1 is connected to HSE_RTC clock
+  *            @arg TIM_TIM11_GPIO1:    TIM11 Channel1 is connected to GPIO
+  *
+  * @note   Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+
+  /* Check parameters */
+  assert_param(IS_TIM_REMAP(htim->Instance, Remap));
+
+  __HAL_LOCK(htim);
+
+  /* Set the Timer remapping configuration */
+  WRITE_REG(htim->Instance->OR, Remap);
+
+  __HAL_UNLOCK(htim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/TD-1-test/TD-1-test.ioc b/TD-1-test/TD-1-test.ioc
index bc98acb..a4e21e6 100644
--- a/TD-1-test/TD-1-test.ioc
+++ b/TD-1-test/TD-1-test.ioc
@@ -9,14 +9,16 @@ Mcu.Family=STM32L1
 Mcu.IP0=NVIC
 Mcu.IP1=RCC
 Mcu.IP2=SYS
-Mcu.IP3=USART2
-Mcu.IPNb=4
+Mcu.IP3=TIM6
+Mcu.IP4=USART2
+Mcu.IPNb=5
 Mcu.Name=STM32L152RETx
 Mcu.Package=LQFP64
 Mcu.Pin0=PC13-WKUP2
 Mcu.Pin1=PC14-OSC32_IN
 Mcu.Pin10=PB3
 Mcu.Pin11=VP_SYS_VS_Systick
+Mcu.Pin12=VP_TIM6_VS_ClockSourceINT
 Mcu.Pin2=PC15-OSC32_OUT
 Mcu.Pin3=PH0-OSC_IN
 Mcu.Pin4=PH1-OSC_OUT
@@ -25,7 +27,7 @@ Mcu.Pin6=PA3
 Mcu.Pin7=PA5
 Mcu.Pin8=PA13
 Mcu.Pin9=PA14
-Mcu.PinsNb=12
+Mcu.PinsNb=13
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32L152RETx
@@ -42,6 +44,7 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0
 NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:true
 NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true\:true\:false
+NVIC.TIM6_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
 PA13.GPIOParameters=GPIO_Label
 PA13.GPIO_Label=TMS
@@ -120,40 +123,45 @@ ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=true
 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART2_UART_Init-USART2-false-HAL-true
 RCC.48MHZClocksFreq_Value=48000000
-RCC.AHBFreq_Value=32000000
-RCC.APB1Freq_Value=32000000
-RCC.APB1TimFreq_Value=32000000
-RCC.APB2Freq_Value=32000000
-RCC.APB2TimFreq_Value=32000000
-RCC.FCLKCortexFreq_Value=32000000
+RCC.AHBFreq_Value=16000000
+RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
+RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
 RCC.FamilyName=M
-RCC.HCLKFreq_Value=32000000
+RCC.HCLKFreq_Value=16000000
 RCC.HSE_VALUE=8000000
 RCC.HSI_VALUE=16000000
 RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,LCDFreq_Value,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLDIV,PLLMUL,PWRFreq_Value,RTCClockSelectionVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USBOutput,VCOOutputFreq_Value
 RCC.LCDFreq_Value=32768
 RCC.LSI_VALUE=37000
-RCC.MCOPinFreq_Value=32000000
+RCC.MCOPinFreq_Value=16000000
 RCC.MSI_VALUE=2097000
 RCC.PLLCLKFreq_Value=32000000
 RCC.PLLDIV=RCC_PLL_DIV3
 RCC.PLLMUL=RCC_PLL_MUL6
-RCC.PWRFreq_Value=32000000
+RCC.PWRFreq_Value=16000000
 RCC.RTCClockSelectionVirtual=RCC_RTCCLKSOURCE_LSE
 RCC.RTCFreq_Value=32768
 RCC.RTCHSEDivFreq_Value=4000000
-RCC.SYSCLKFreq_VALUE=32000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.TIMFreq_Value=32000000
-RCC.TimerFreq_Value=32000000
+RCC.SYSCLKFreq_VALUE=16000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI
+RCC.TIMFreq_Value=16000000
+RCC.TimerFreq_Value=16000000
 RCC.USBOutput=48000000
 RCC.VCOOutputFreq_Value=96000000
 SH.GPXTI13.0=GPIO_EXTI13
 SH.GPXTI13.ConfNb=1
+TIM6.IPParameters=Prescaler,Period
+TIM6.Period=1000-1
+TIM6.Prescaler=16000-1
 USART2.IPParameters=VirtualMode
 USART2.VirtualMode=VM_ASYNC
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM6_VS_ClockSourceINT.Mode=Enable_Timer
+VP_TIM6_VS_ClockSourceINT.Signal=TIM6_VS_ClockSourceINT
 board=NUCLEO-L152RE
 boardIOC=true
 isbadioc=false