From 3e595481b280fdc7aee54e028d183e261d99242f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?F=C3=A9lix=20MARQUET?=
<72651575+BreizhHardware@users.noreply.github.com>
Date: Thu, 26 Jun 2025 15:20:33 +0200
Subject: [PATCH] =?UTF-8?q?TP5=20Exo=203=20(Oscilloscope=20num=C3=A9rique)?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
TP5_OSCILLO_NUM/.cproject | 182 +
TP5_OSCILLO_NUM/.mxproject | 25 +
TP5_OSCILLO_NUM/.project | 32 +
.../com.st.stm32cube.ide.mcu.sfrview.prefs | 2 +
.../.settings/language.settings.xml | 25 +
.../.settings/org.eclipse.cdt.core.prefs | 6 +
.../org.eclipse.core.resources.prefs | 2 +
.../.settings/stm32cubeide.project.prefs | 5 +
TP5_OSCILLO_NUM/Core/Inc/main.h | 69 +
TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_hal_conf.h | 318 +
TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_it.h | 67 +
TP5_OSCILLO_NUM/Core/Src/main.c | 383 +
TP5_OSCILLO_NUM/Core/Src/stm32l1xx_hal_msp.c | 218 +
TP5_OSCILLO_NUM/Core/Src/stm32l1xx_it.c | 217 +
TP5_OSCILLO_NUM/Core/Src/syscalls.c | 176 +
TP5_OSCILLO_NUM/Core/Src/sysmem.c | 79 +
TP5_OSCILLO_NUM/Core/Src/system_stm32l1xx.c | 428 +
.../Core/Startup/startup_stm32l152retx.s | 413 +
TP5_OSCILLO_NUM/Debug/Core/Src/main.cyclo | 8 +
TP5_OSCILLO_NUM/Debug/Core/Src/main.d | 59 +
TP5_OSCILLO_NUM/Debug/Core/Src/main.o | Bin 0 -> 752340 bytes
TP5_OSCILLO_NUM/Debug/Core/Src/main.su | 8 +
.../Debug/Core/Src/stm32l1xx_hal_msp.cyclo | 5 +
.../Debug/Core/Src/stm32l1xx_hal_msp.d | 56 +
.../Debug/Core/Src/stm32l1xx_hal_msp.o | Bin 0 -> 747360 bytes
.../Debug/Core/Src/stm32l1xx_hal_msp.su | 5 +
.../Debug/Core/Src/stm32l1xx_it.cyclo | 10 +
TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_it.d | 58 +
TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_it.o | Bin 0 -> 743104 bytes
.../Debug/Core/Src/stm32l1xx_it.su | 10 +
TP5_OSCILLO_NUM/Debug/Core/Src/subdir.mk | 42 +
TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.cyclo | 18 +
TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.d | 1 +
TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.o | Bin 0 -> 83424 bytes
TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.su | 18 +
TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.cyclo | 1 +
TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.d | 1 +
TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.o | Bin 0 -> 55892 bytes
TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.su | 1 +
.../Debug/Core/Src/system_stm32l1xx.cyclo | 2 +
.../Debug/Core/Src/system_stm32l1xx.d | 55 +
.../Debug/Core/Src/system_stm32l1xx.o | Bin 0 -> 739608 bytes
.../Debug/Core/Src/system_stm32l1xx.su | 2 +
.../Core/Startup/startup_stm32l152retx.d | 2 +
.../Core/Startup/startup_stm32l152retx.o | Bin 0 -> 6044 bytes
TP5_OSCILLO_NUM/Debug/Core/Startup/subdir.mk | 27 +
.../Debug/Drivers/7Seg_MAX7219/max7219.cyclo | 12 +
.../Debug/Drivers/7Seg_MAX7219/max7219.d | 58 +
.../Debug/Drivers/7Seg_MAX7219/max7219.o | Bin 0 -> 746516 bytes
.../Debug/Drivers/7Seg_MAX7219/max7219.su | 12 +
.../Debug/Drivers/7Seg_MAX7219/subdir.mk | 27 +
.../Src/stm32l1xx_hal.cyclo | 25 +
.../STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d | 56 +
.../STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o | Bin 0 -> 750692 bytes
.../STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.su | 25 +
.../Src/stm32l1xx_hal_adc.cyclo | 27 +
.../Src/stm32l1xx_hal_adc.d | 56 +
.../Src/stm32l1xx_hal_adc.o | Bin 0 -> 759308 bytes
.../Src/stm32l1xx_hal_adc.su | 27 +
.../Src/stm32l1xx_hal_adc_ex.cyclo | 8 +
.../Src/stm32l1xx_hal_adc_ex.d | 56 +
.../Src/stm32l1xx_hal_adc_ex.o | Bin 0 -> 748484 bytes
.../Src/stm32l1xx_hal_adc_ex.su | 8 +
.../Src/stm32l1xx_hal_cortex.cyclo | 34 +
.../Src/stm32l1xx_hal_cortex.d | 56 +
.../Src/stm32l1xx_hal_cortex.o | Bin 0 -> 756788 bytes
.../Src/stm32l1xx_hal_cortex.su | 34 +
.../Src/stm32l1xx_hal_dma.cyclo | 13 +
.../Src/stm32l1xx_hal_dma.d | 56 +
.../Src/stm32l1xx_hal_dma.o | Bin 0 -> 747656 bytes
.../Src/stm32l1xx_hal_dma.su | 13 +
.../Src/stm32l1xx_hal_exti.cyclo | 9 +
.../Src/stm32l1xx_hal_exti.d | 56 +
.../Src/stm32l1xx_hal_exti.o | Bin 0 -> 743364 bytes
.../Src/stm32l1xx_hal_exti.su | 9 +
.../Src/stm32l1xx_hal_flash.cyclo | 13 +
.../Src/stm32l1xx_hal_flash.d | 56 +
.../Src/stm32l1xx_hal_flash.o | Bin 0 -> 745356 bytes
.../Src/stm32l1xx_hal_flash.su | 13 +
.../Src/stm32l1xx_hal_flash_ex.cyclo | 31 +
.../Src/stm32l1xx_hal_flash_ex.d | 56 +
.../Src/stm32l1xx_hal_flash_ex.o | Bin 0 -> 758624 bytes
.../Src/stm32l1xx_hal_flash_ex.su | 31 +
.../Src/stm32l1xx_hal_flash_ramfunc.cyclo | 10 +
.../Src/stm32l1xx_hal_flash_ramfunc.d | 56 +
.../Src/stm32l1xx_hal_flash_ramfunc.o | Bin 0 -> 744224 bytes
.../Src/stm32l1xx_hal_flash_ramfunc.su | 10 +
.../Src/stm32l1xx_hal_gpio.cyclo | 8 +
.../Src/stm32l1xx_hal_gpio.d | 56 +
.../Src/stm32l1xx_hal_gpio.o | Bin 0 -> 743996 bytes
.../Src/stm32l1xx_hal_gpio.su | 8 +
.../Src/stm32l1xx_hal_pwr.cyclo | 17 +
.../Src/stm32l1xx_hal_pwr.d | 56 +
.../Src/stm32l1xx_hal_pwr.o | Bin 0 -> 746236 bytes
.../Src/stm32l1xx_hal_pwr.su | 17 +
.../Src/stm32l1xx_hal_pwr_ex.cyclo | 7 +
.../Src/stm32l1xx_hal_pwr_ex.d | 56 +
.../Src/stm32l1xx_hal_pwr_ex.o | Bin 0 -> 740900 bytes
.../Src/stm32l1xx_hal_pwr_ex.su | 7 +
.../Src/stm32l1xx_hal_rcc.cyclo | 15 +
.../Src/stm32l1xx_hal_rcc.d | 56 +
.../Src/stm32l1xx_hal_rcc.o | Bin 0 -> 753140 bytes
.../Src/stm32l1xx_hal_rcc.su | 15 +
.../Src/stm32l1xx_hal_rcc_ex.cyclo | 8 +
.../Src/stm32l1xx_hal_rcc_ex.d | 56 +
.../Src/stm32l1xx_hal_rcc_ex.o | Bin 0 -> 742888 bytes
.../Src/stm32l1xx_hal_rcc_ex.su | 8 +
.../Src/stm32l1xx_hal_spi.cyclo | 55 +
.../Src/stm32l1xx_hal_spi.d | 56 +
.../Src/stm32l1xx_hal_spi.o | Bin 0 -> 778768 bytes
.../Src/stm32l1xx_hal_spi.su | 55 +
.../STM32L1xx_HAL_Driver/Src/subdir.mk | 69 +
.../Debug/Drivers/TFT_ST7735/fonc_tft.cyclo | 12 +
.../Debug/Drivers/TFT_ST7735/fonc_tft.d | 58 +
.../Debug/Drivers/TFT_ST7735/fonc_tft.o | Bin 0 -> 754320 bytes
.../Debug/Drivers/TFT_ST7735/fonc_tft.su | 12 +
.../Debug/Drivers/TFT_ST7735/subdir.mk | 27 +
TP5_OSCILLO_NUM/Debug/TP2_INIT_DISPLAY.list | 5454 +++++++++
TP5_OSCILLO_NUM/Debug/TP2_INIT_DISPLAY.map | 2896 +++++
TP5_OSCILLO_NUM/Debug/TP2_ISEN_DISPLAY.list | 5427 +++++++++
TP5_OSCILLO_NUM/Debug/TP2_ISEN_DISPLAY.map | 2895 +++++
.../Debug/TP3_M_A_TIMER_MODULO.list | 7251 ++++++++++++
.../Debug/TP3_M_A_TIMER_MODULO.map | 3420 ++++++
TP5_OSCILLO_NUM/Debug/TP3_PWM_GENERATOR.list | 8291 ++++++++++++++
TP5_OSCILLO_NUM/Debug/TP3_PWM_GENERATOR.map | 3419 ++++++
TP5_OSCILLO_NUM/Debug/TP3_PWM_LED.list | 8719 +++++++++++++++
TP5_OSCILLO_NUM/Debug/TP3_PWM_LED.map | 3436 ++++++
TP5_OSCILLO_NUM/Debug/TP3_PWM_MOTOR.list | 9179 ++++++++++++++++
TP5_OSCILLO_NUM/Debug/TP3_PWM_MOTOR.map | 3477 ++++++
TP5_OSCILLO_NUM/Debug/TP4_GAMME.list | 8029 ++++++++++++++
TP5_OSCILLO_NUM/Debug/TP4_GAMME.map | 3423 ++++++
TP5_OSCILLO_NUM/Debug/TP4_INIT_TFT.list | 6808 ++++++++++++
TP5_OSCILLO_NUM/Debug/TP4_INIT_TFT.map | 3104 ++++++
TP5_OSCILLO_NUM/Debug/TP4_MELODIE.list | 8000 ++++++++++++++
TP5_OSCILLO_NUM/Debug/TP4_MELODIE.map | 3415 ++++++
TP5_OSCILLO_NUM/Debug/TP4_TFT_CHAIN_CHAR.list | 6583 +++++++++++
TP5_OSCILLO_NUM/Debug/TP4_TFT_CHAIN_CHAR.map | 3030 +++++
TP5_OSCILLO_NUM/Debug/TP5_OSCILLO_NUM.elf | Bin 0 -> 776844 bytes
TP5_OSCILLO_NUM/Debug/TP5_OSCILLO_NUM.list | 9786 +++++++++++++++++
TP5_OSCILLO_NUM/Debug/TP5_OSCILLO_NUM.map | 3431 ++++++
.../Debug/TP5_VOLT.list | 0
.../Debug/TP5_VOLT.map | 0
TP5_OSCILLO_NUM/Debug/makefile | 96 +
TP5_OSCILLO_NUM/Debug/objects.list | 24 +
TP5_OSCILLO_NUM/Debug/objects.mk | 9 +
TP5_OSCILLO_NUM/Debug/sources.mk | 30 +
.../Drivers/7Seg_MAX7219/max7219.c | 269 +
.../Drivers/7Seg_MAX7219/max7219.h | 15 +
.../Device/ST/STM32L1xx/Include/stm32l152xe.h | 9022 +++++++++++++++
.../Device/ST/STM32L1xx/Include/stm32l1xx.h | 299 +
.../ST/STM32L1xx/Include/system_stm32l1xx.h | 107 +
.../CMSIS/Device/ST/STM32L1xx/LICENSE.txt | 6 +
.../CMSIS/Device/ST/STM32L1xx/License.md | 83 +
.../Drivers/CMSIS/Include/cmsis_armcc.h | 865 ++
.../Drivers/CMSIS/Include/cmsis_armclang.h | 1869 ++++
.../Drivers/CMSIS/Include/cmsis_compiler.h | 266 +
.../Drivers/CMSIS/Include/cmsis_gcc.h | 2085 ++++
.../Drivers/CMSIS/Include/cmsis_iccarm.h | 935 ++
.../Drivers/CMSIS/Include/cmsis_version.h | 39 +
.../Drivers/CMSIS/Include/core_armv8mbl.h | 1918 ++++
.../Drivers/CMSIS/Include/core_armv8mml.h | 2927 +++++
.../Drivers/CMSIS/Include/core_cm0.h | 949 ++
.../Drivers/CMSIS/Include/core_cm0plus.h | 1083 ++
.../Drivers/CMSIS/Include/core_cm1.h | 976 ++
.../Drivers/CMSIS/Include/core_cm23.h | 1993 ++++
.../Drivers/CMSIS/Include/core_cm3.h | 1941 ++++
.../Drivers/CMSIS/Include/core_cm33.h | 3002 +++++
.../Drivers/CMSIS/Include/core_cm4.h | 2129 ++++
.../Drivers/CMSIS/Include/core_cm7.h | 2671 +++++
.../Drivers/CMSIS/Include/core_sc000.h | 1022 ++
.../Drivers/CMSIS/Include/core_sc300.h | 1915 ++++
.../Drivers/CMSIS/Include/mpu_armv7.h | 270 +
.../Drivers/CMSIS/Include/mpu_armv8.h | 333 +
.../Drivers/CMSIS/Include/tz_context.h | 70 +
TP5_OSCILLO_NUM/Drivers/CMSIS/LICENSE.txt | 201 +
.../Inc/Legacy/stm32_hal_legacy.h | 4422 ++++++++
.../STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h | 995 ++
.../Inc/stm32l1xx_hal_adc.h | 1365 +++
.../Inc/stm32l1xx_hal_adc_ex.h | 568 +
.../Inc/stm32l1xx_hal_cortex.h | 437 +
.../Inc/stm32l1xx_hal_def.h | 199 +
.../Inc/stm32l1xx_hal_dma.h | 651 ++
.../Inc/stm32l1xx_hal_exti.h | 315 +
.../Inc/stm32l1xx_hal_flash.h | 411 +
.../Inc/stm32l1xx_hal_flash_ex.h | 965 ++
.../Inc/stm32l1xx_hal_flash_ramfunc.h | 116 +
.../Inc/stm32l1xx_hal_gpio.h | 333 +
.../Inc/stm32l1xx_hal_gpio_ex.h | 203 +
.../Inc/stm32l1xx_hal_pwr.h | 483 +
.../Inc/stm32l1xx_hal_pwr_ex.h | 115 +
.../Inc/stm32l1xx_hal_rcc.h | 1895 ++++
.../Inc/stm32l1xx_hal_rcc_ex.h | 1027 ++
.../Inc/stm32l1xx_hal_spi.h | 749 ++
.../Inc/stm32l1xx_ll_adc.h | 5205 +++++++++
.../Inc/stm32l1xx_ll_bus.h | 1100 ++
.../Inc/stm32l1xx_ll_cortex.h | 637 ++
.../Inc/stm32l1xx_ll_dma.h | 1996 ++++
.../Inc/stm32l1xx_ll_exti.h | 1015 ++
.../Inc/stm32l1xx_ll_gpio.h | 987 ++
.../Inc/stm32l1xx_ll_pwr.h | 718 ++
.../Inc/stm32l1xx_ll_rcc.h | 1796 +++
.../Inc/stm32l1xx_ll_spi.h | 2015 ++++
.../Inc/stm32l1xx_ll_system.h | 2007 ++++
.../Inc/stm32l1xx_ll_utils.h | 270 +
.../Drivers/STM32L1xx_HAL_Driver/LICENSE.txt | 6 +
.../Drivers/STM32L1xx_HAL_Driver/License.md | 3 +
.../STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c | 570 +
.../Src/stm32l1xx_hal_adc.c | 2403 ++++
.../Src/stm32l1xx_hal_adc_ex.c | 868 ++
.../Src/stm32l1xx_hal_cortex.c | 537 +
.../Src/stm32l1xx_hal_dma.c | 909 ++
.../Src/stm32l1xx_hal_exti.c | 547 +
.../Src/stm32l1xx_hal_flash.c | 723 ++
.../Src/stm32l1xx_hal_flash_ex.c | 1870 ++++
.../Src/stm32l1xx_hal_flash_ramfunc.c | 640 ++
.../Src/stm32l1xx_hal_gpio.c | 546 +
.../Src/stm32l1xx_hal_pwr.c | 650 ++
.../Src/stm32l1xx_hal_pwr_ex.c | 158 +
.../Src/stm32l1xx_hal_rcc.c | 1394 +++
.../Src/stm32l1xx_hal_rcc_ex.c | 447 +
.../Src/stm32l1xx_hal_spi.c | 3962 +++++++
TP5_OSCILLO_NUM/Drivers/TFT_ST7735/fonc_tft.c | 1065 ++
TP5_OSCILLO_NUM/Drivers/TFT_ST7735/fonc_tft.h | 65 +
TP5_OSCILLO_NUM/STM32L152RETX_FLASH.ld | 187 +
TP5_OSCILLO_NUM/STM32L152RETX_RAM.ld | 187 +
TP5_OSCILLO_NUM/TP5_OSCILLO_NUM Debug.launch | 85 +
TP5_OSCILLO_NUM/TP5_OSCILLO_NUM.ioc | 156 +
TP5_VOLT/Debug/Core/Src/syscalls.o | Bin 83424 -> 83420 bytes
TP5_VOLT/Debug/Core/Src/sysmem.o | Bin 55892 -> 55888 bytes
.../Core/Startup/startup_stm32l152retx.o | Bin 6044 -> 6028 bytes
TP5_VOLT/Debug/{TP5_VOLT.elf => TP5_TEMP.elf} | Bin 776484 -> 776404 bytes
TP5_VOLT/Debug/TP5_TEMP.list | 9758 ++++++++++++++++
TP5_VOLT/Debug/TP5_TEMP.map | 3425 ++++++
TP5_VOLT/Debug/makefile | 20 +-
234 files changed, 227781 insertions(+), 10 deletions(-)
create mode 100644 TP5_OSCILLO_NUM/.cproject
create mode 100644 TP5_OSCILLO_NUM/.mxproject
create mode 100644 TP5_OSCILLO_NUM/.project
create mode 100644 TP5_OSCILLO_NUM/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs
create mode 100644 TP5_OSCILLO_NUM/.settings/language.settings.xml
create mode 100644 TP5_OSCILLO_NUM/.settings/org.eclipse.cdt.core.prefs
create mode 100644 TP5_OSCILLO_NUM/.settings/org.eclipse.core.resources.prefs
create mode 100644 TP5_OSCILLO_NUM/.settings/stm32cubeide.project.prefs
create mode 100644 TP5_OSCILLO_NUM/Core/Inc/main.h
create mode 100644 TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_hal_conf.h
create mode 100644 TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_it.h
create mode 100644 TP5_OSCILLO_NUM/Core/Src/main.c
create mode 100644 TP5_OSCILLO_NUM/Core/Src/stm32l1xx_hal_msp.c
create mode 100644 TP5_OSCILLO_NUM/Core/Src/stm32l1xx_it.c
create mode 100644 TP5_OSCILLO_NUM/Core/Src/syscalls.c
create mode 100644 TP5_OSCILLO_NUM/Core/Src/sysmem.c
create mode 100644 TP5_OSCILLO_NUM/Core/Src/system_stm32l1xx.c
create mode 100644 TP5_OSCILLO_NUM/Core/Startup/startup_stm32l152retx.s
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/main.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/main.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/main.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/main.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_hal_msp.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_hal_msp.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_hal_msp.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_hal_msp.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_it.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_it.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_it.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/stm32l1xx_it.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/subdir.mk
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/syscalls.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/sysmem.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/system_stm32l1xx.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/system_stm32l1xx.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/system_stm32l1xx.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Src/system_stm32l1xx.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Startup/startup_stm32l152retx.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Startup/startup_stm32l152retx.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Core/Startup/subdir.mk
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/7Seg_MAX7219/max7219.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/7Seg_MAX7219/max7219.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/7Seg_MAX7219/max7219.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/7Seg_MAX7219/max7219.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/7Seg_MAX7219/subdir.mk
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o
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create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.cyclo
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create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/TFT_ST7735/fonc_tft.cyclo
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/TFT_ST7735/fonc_tft.d
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/TFT_ST7735/fonc_tft.o
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/TFT_ST7735/fonc_tft.su
create mode 100644 TP5_OSCILLO_NUM/Debug/Drivers/TFT_ST7735/subdir.mk
create mode 100644 TP5_OSCILLO_NUM/Debug/TP2_INIT_DISPLAY.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP2_INIT_DISPLAY.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP2_ISEN_DISPLAY.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP2_ISEN_DISPLAY.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP3_M_A_TIMER_MODULO.list
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create mode 100644 TP5_OSCILLO_NUM/Debug/TP3_PWM_GENERATOR.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP3_PWM_GENERATOR.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP3_PWM_LED.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP3_PWM_LED.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP3_PWM_MOTOR.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP3_PWM_MOTOR.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_GAMME.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_GAMME.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_INIT_TFT.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_INIT_TFT.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_MELODIE.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_MELODIE.map
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_TFT_CHAIN_CHAR.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP4_TFT_CHAIN_CHAR.map
create mode 100755 TP5_OSCILLO_NUM/Debug/TP5_OSCILLO_NUM.elf
create mode 100644 TP5_OSCILLO_NUM/Debug/TP5_OSCILLO_NUM.list
create mode 100644 TP5_OSCILLO_NUM/Debug/TP5_OSCILLO_NUM.map
rename {TP5_VOLT => TP5_OSCILLO_NUM}/Debug/TP5_VOLT.list (100%)
rename {TP5_VOLT => TP5_OSCILLO_NUM}/Debug/TP5_VOLT.map (100%)
create mode 100644 TP5_OSCILLO_NUM/Debug/makefile
create mode 100644 TP5_OSCILLO_NUM/Debug/objects.list
create mode 100644 TP5_OSCILLO_NUM/Debug/objects.mk
create mode 100644 TP5_OSCILLO_NUM/Debug/sources.mk
create mode 100644 TP5_OSCILLO_NUM/Drivers/7Seg_MAX7219/max7219.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/7Seg_MAX7219/max7219.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Device/ST/STM32L1xx/LICENSE.txt
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Device/ST/STM32L1xx/License.md
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/cmsis_armcc.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/cmsis_armclang.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/cmsis_compiler.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/cmsis_gcc.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/cmsis_iccarm.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/cmsis_version.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_armv8mbl.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_armv8mml.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm0.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm0plus.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm1.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm23.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm3.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm33.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm4.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_cm7.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_sc000.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/core_sc300.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/mpu_armv7.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/mpu_armv8.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/Include/tz_context.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/CMSIS/LICENSE.txt
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_adc.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/LICENSE.txt
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/License.md
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/TFT_ST7735/fonc_tft.c
create mode 100644 TP5_OSCILLO_NUM/Drivers/TFT_ST7735/fonc_tft.h
create mode 100644 TP5_OSCILLO_NUM/STM32L152RETX_FLASH.ld
create mode 100644 TP5_OSCILLO_NUM/STM32L152RETX_RAM.ld
create mode 100644 TP5_OSCILLO_NUM/TP5_OSCILLO_NUM Debug.launch
create mode 100644 TP5_OSCILLO_NUM/TP5_OSCILLO_NUM.ioc
rename TP5_VOLT/Debug/{TP5_VOLT.elf => TP5_TEMP.elf} (95%)
create mode 100644 TP5_VOLT/Debug/TP5_TEMP.list
create mode 100644 TP5_VOLT/Debug/TP5_TEMP.map
diff --git a/TP5_OSCILLO_NUM/.cproject b/TP5_OSCILLO_NUM/.cproject
new file mode 100644
index 0000000..eb1b19d
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.cproject
@@ -0,0 +1,182 @@
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diff --git a/TP5_OSCILLO_NUM/.mxproject b/TP5_OSCILLO_NUM/.mxproject
new file mode 100644
index 0000000..8076a40
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.mxproject
@@ -0,0 +1,25 @@
+[PreviousLibFiles]
+LibFiles=Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_adc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crs.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_adc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_crs.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core/Src/main.c;Core/Src/stm32l1xx_it.c;Core/Src/stm32l1xx_hal_msp.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Core/Src/system_stm32l1xx.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_adc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Core/Src/system_stm32l1xx.c;;;
+HeaderPath=Drivers/STM32L1xx_HAL_Driver/Inc;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L1xx/Include;Drivers/CMSIS/Include;Core/Inc;
+CDefines=USE_HAL_DRIVER;STM32L152xE;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=../Core/Inc/stm32l1xx_it.h
+HeaderFiles#1=../Core/Inc/stm32l1xx_hal_conf.h
+HeaderFiles#2=../Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=../Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=../Core/Src/stm32l1xx_it.c
+SourceFiles#1=../Core/Src/stm32l1xx_hal_msp.c
+SourceFiles#2=../Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=../Core/Src
+SourceFiles=;
+
diff --git a/TP5_OSCILLO_NUM/.project b/TP5_OSCILLO_NUM/.project
new file mode 100644
index 0000000..c4bdfb1
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.project
@@ -0,0 +1,32 @@
+
+
+ TP5_OSCILLO_NUM
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ com.st.stm32cube.ide.mcu.MCUProjectNature
+ com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+ org.eclipse.cdt.core.cnature
+ com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature
+ com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
+ com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+ com.st.stm32cube.ide.mcu.MCURootProjectNature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/TP5_OSCILLO_NUM/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/TP5_OSCILLO_NUM/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs
new file mode 100644
index 0000000..98a69fc
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}}
diff --git a/TP5_OSCILLO_NUM/.settings/language.settings.xml b/TP5_OSCILLO_NUM/.settings/language.settings.xml
new file mode 100644
index 0000000..fd737e1
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/TP5_OSCILLO_NUM/.settings/org.eclipse.cdt.core.prefs b/TP5_OSCILLO_NUM/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000..c8ec5df
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,6 @@
+doxygen/doxygen_new_line_after_brief=true
+doxygen/doxygen_use_brief_tag=false
+doxygen/doxygen_use_javadoc_tags=true
+doxygen/doxygen_use_pre_tag=false
+doxygen/doxygen_use_structural_commands=false
+eclipse.preferences.version=1
diff --git a/TP5_OSCILLO_NUM/.settings/org.eclipse.core.resources.prefs b/TP5_OSCILLO_NUM/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000..99f26c0
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding/=UTF-8
diff --git a/TP5_OSCILLO_NUM/.settings/stm32cubeide.project.prefs b/TP5_OSCILLO_NUM/.settings/stm32cubeide.project.prefs
new file mode 100644
index 0000000..a0b3b52
--- /dev/null
+++ b/TP5_OSCILLO_NUM/.settings/stm32cubeide.project.prefs
@@ -0,0 +1,5 @@
+635E684B79701B039C64EA45C3F84D30=20408E19A1D483CC68E7BF859CC595B4
+66BE74F758C12D739921AEA421D593D3=3
+8DF89ED150041C4CBC7CB9A9CAA90856=787343FA0477F66DEA4B2B86368887F5
+DC22A860405A8BF2F2C095E5B6529F12=787343FA0477F66DEA4B2B86368887F5
+eclipse.preferences.version=1
diff --git a/TP5_OSCILLO_NUM/Core/Inc/main.h b/TP5_OSCILLO_NUM/Core/Inc/main.h
new file mode 100644
index 0000000..f645caf
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Inc/main.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l1xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_hal_conf.h b/TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_hal_conf.h
new file mode 100644
index 0000000..25e9189
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_hal_conf.h
@@ -0,0 +1,318 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32l1xx_hal_conf.h
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_HAL_CONF_H
+#define __STM32L1xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_COMP_MODULE_ENABLED */
+/*#define HAL_CRC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_DAC_MODULE_ENABLED */
+/*#define HAL_I2C_MODULE_ENABLED */
+/*#define HAL_I2S_MODULE_ENABLED */
+/*#define HAL_IRDA_MODULE_ENABLED */
+/*#define HAL_IWDG_MODULE_ENABLED */
+/*#define HAL_LCD_MODULE_ENABLED */
+/*#define HAL_NOR_MODULE_ENABLED */
+/*#define HAL_OPAMP_MODULE_ENABLED */
+/*#define HAL_PCD_MODULE_ENABLED */
+/*#define HAL_RTC_MODULE_ENABLED */
+/*#define HAL_SD_MODULE_ENABLED */
+/*#define HAL_SMARTCARD_MODULE_ENABLED */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_SRAM_MODULE_ENABLED */
+/*#define HAL_TIM_MODULE_ENABLED */
+/*#define HAL_UART_MODULE_ENABLED */
+/*#define HAL_USART_MODULE_ENABLED */
+/*#define HAL_WWDG_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Multiple Speed oscillator (MSI) default value.
+ * This value is the default MSI range value after Reset.
+ */
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (37000U) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)15) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 0
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+ * @brief Set below the peripheral configuration to "1U" to add the support
+ * of HAL callback registration/deregistration feature for the HAL
+ * driver(s). This allows user application to provide specific callback
+ * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+ * the default weak callback functions (see each stm32l0xx_hal_ppp.h file
+ * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+ * for each PPP peripheral).
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
+#define USE_HAL_SDMMC_REGISTER_CALLBACKS 0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC 0U
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32l1xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32l1xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32l1xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32l1xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32l1xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32l1xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32l1xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32l1xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32l1xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32l1xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32l1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32l1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l1xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32l1xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l1xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+ #include "stm32l1xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l1xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l1xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32l1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l1xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l1xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l1xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l1xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l1xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l1xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l1xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32l1xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_HAL_CONF_H */
+
diff --git a/TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_it.h b/TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_it.h
new file mode 100644
index 0000000..a0c610b
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Inc/stm32l1xx_it.h
@@ -0,0 +1,67 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32l1xx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L1xx_IT_H
+#define __STM32L1xx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void ADC1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1xx_IT_H */
diff --git a/TP5_OSCILLO_NUM/Core/Src/main.c b/TP5_OSCILLO_NUM/Core/Src/main.c
new file mode 100644
index 0000000..fcdb057
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Src/main.c
@@ -0,0 +1,383 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "max7219.h"
+#include "fonc_tft.h"
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc;
+
+SPI_HandleTypeDef hspi1;
+
+/* USER CODE BEGIN PV */
+
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_SPI1_Init(void);
+static void MX_ADC_Init(void);
+/* USER CODE BEGIN PFP */
+void drawHLine_TFT(uint16_t x, uint16_t y, uint16_t length, uint16_t color);
+void drawAxes();
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+void drawHLine_TFT(uint16_t x, uint16_t y, uint16_t length, uint16_t color) {
+ for (uint16_t i = 0; i < length; i++) {
+ drawPixel_TFT(x + i, y, color);
+ }
+}
+
+void drawAxes() {
+ drawHLine_TFT(0, 127, 115, ST7735_WHITE);
+ drawHLine_TFT(0, 88, 115, ST7735_WHITE);
+ drawHLine_TFT(0, 50, 115, ST7735_WHITE);
+ drawHLine_TFT(0, 11, 115, ST7735_WHITE);
+
+ displayChar_TFT(120, 127, '0', ST7735_WHITE, ST7735_BLACK, 1);
+ displayChar_TFT(120, 88, '1', ST7735_WHITE, ST7735_BLACK, 1);
+ displayChar_TFT(120, 50, '2', ST7735_WHITE, ST7735_BLACK, 1);
+ displayChar_TFT(120, 11, '3', ST7735_WHITE, ST7735_BLACK, 1);
+}
+
+
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+
+ /* USER CODE BEGIN 1 */
+
+ /* USER CODE END 1 */
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_SPI1_Init();
+ MX_ADC_Init();
+ /* USER CODE BEGIN 2 */
+ MAX7219_Init();
+ init_TFT();
+ MAX7219_Clear();
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ drawAxes();
+ uint8_t x_pos = 0;
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ HAL_ADC_Start(&hadc);
+ HAL_ADC_PollForConversion(&hadc, 1000);
+ uint32_t value = HAL_ADC_GetValue(&hadc);
+ HAL_ADC_Stop(&hadc);
+ uint32_t milivolt = (value / 4096.0) * 3300;
+ uint8_t y_pos = 127 - (milivolt * 127) / 3300;
+ drawPixel_TFT(x_pos, y_pos, ST7735_YELLOW);
+ x_pos++;
+ if (x_pos >= 128) {
+ x_pos = 0;
+ fillScreen_TFT(ST7735_BLACK);
+ drawAxes();
+ }
+ HAL_Delay(100);
+ }
+
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/**
+ * @brief ADC Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_ADC_Init(void)
+{
+
+ /* USER CODE BEGIN ADC_Init 0 */
+
+ /* USER CODE END ADC_Init 0 */
+
+ ADC_ChannelConfTypeDef sConfig = {0};
+
+ /* USER CODE BEGIN ADC_Init 1 */
+
+ /* USER CODE END ADC_Init 1 */
+
+ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+ */
+ hadc.Instance = ADC1;
+ hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+ hadc.Init.Resolution = ADC_RESOLUTION_12B;
+ hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ hadc.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ hadc.Init.EOCSelection = ADC_EOC_SEQ_CONV;
+ hadc.Init.LowPowerAutoWait = ADC_AUTOWAIT_DISABLE;
+ hadc.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_DISABLE;
+ hadc.Init.ChannelsBank = ADC_CHANNELS_BANK_A;
+ hadc.Init.ContinuousConvMode = DISABLE;
+ hadc.Init.NbrOfConversion = 1;
+ hadc.Init.DiscontinuousConvMode = DISABLE;
+ hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ hadc.Init.DMAContinuousRequests = DISABLE;
+ if (HAL_ADC_Init(&hadc) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
+ */
+ sConfig.Channel = ADC_CHANNEL_0;
+ sConfig.Rank = ADC_REGULAR_RANK_1;
+ sConfig.SamplingTime = ADC_SAMPLETIME_4CYCLES;
+ if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN ADC_Init 2 */
+
+ /* USER CODE END ADC_Init 2 */
+
+}
+
+/**
+ * @brief SPI1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_SPI1_Init(void)
+{
+
+ /* USER CODE BEGIN SPI1_Init 0 */
+
+ /* USER CODE END SPI1_Init 0 */
+
+ /* USER CODE BEGIN SPI1_Init 1 */
+
+ /* USER CODE END SPI1_Init 1 */
+ /* SPI1 parameter configuration*/
+ hspi1.Instance = SPI1;
+ hspi1.Init.Mode = SPI_MODE_MASTER;
+ hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+ hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+ hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+ hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+ hspi1.Init.NSS = SPI_NSS_SOFT;
+ hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+ hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+ hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+ hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ hspi1.Init.CRCPolynomial = 10;
+ if (HAL_SPI_Init(&hspi1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN SPI1_Init 2 */
+
+ /* USER CODE END SPI1_Init 2 */
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ /* USER CODE BEGIN MX_GPIO_Init_1 */
+
+ /* USER CODE END MX_GPIO_Init_1 */
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_SET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET);
+
+ /*Configure GPIO pins : PC0 PC1 PC2 PC3 */
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : PB15 */
+ GPIO_InitStruct.Pin = GPIO_PIN_15;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF3_TIM11;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : PD2 */
+ GPIO_InitStruct.Pin = GPIO_PIN_2;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : PB7 */
+ GPIO_InitStruct.Pin = GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN MX_GPIO_Init_2 */
+
+ /* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/TP5_OSCILLO_NUM/Core/Src/stm32l1xx_hal_msp.c b/TP5_OSCILLO_NUM/Core/Src/stm32l1xx_hal_msp.c
new file mode 100644
index 0000000..70741cc
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Src/stm32l1xx_hal_msp.c
@@ -0,0 +1,218 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32l1xx_hal_msp.c
+ * @brief This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_COMP_CLK_ENABLE();
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/**
+ * @brief ADC MSP Initialization
+ * This function configures the hardware resources used in this example
+ * @param hadc: ADC handle pointer
+ * @retval None
+ */
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(hadc->Instance==ADC1)
+ {
+ /* USER CODE BEGIN ADC1_MspInit 0 */
+
+ /* USER CODE END ADC1_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_ADC1_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**ADC GPIO Configuration
+ PA0-WKUP1 ------> ADC_IN0
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_0;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* ADC1 interrupt Init */
+ HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(ADC1_IRQn);
+ /* USER CODE BEGIN ADC1_MspInit 1 */
+
+ /* USER CODE END ADC1_MspInit 1 */
+
+ }
+
+}
+
+/**
+ * @brief ADC MSP De-Initialization
+ * This function freeze the hardware resources used in this example
+ * @param hadc: ADC handle pointer
+ * @retval None
+ */
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ if(hadc->Instance==ADC1)
+ {
+ /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+ /* USER CODE END ADC1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_ADC1_CLK_DISABLE();
+
+ /**ADC GPIO Configuration
+ PA0-WKUP1 ------> ADC_IN0
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0);
+
+ /* ADC1 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(ADC1_IRQn);
+ /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+ /* USER CODE END ADC1_MspDeInit 1 */
+ }
+
+}
+
+/**
+ * @brief SPI MSP Initialization
+ * This function configures the hardware resources used in this example
+ * @param hspi: SPI handle pointer
+ * @retval None
+ */
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(hspi->Instance==SPI1)
+ {
+ /* USER CODE BEGIN SPI1_MspInit 0 */
+
+ /* USER CODE END SPI1_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_SPI1_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**SPI1 GPIO Configuration
+ PA5 ------> SPI1_SCK
+ PA6 ------> SPI1_MISO
+ PA7 ------> SPI1_MOSI
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN SPI1_MspInit 1 */
+
+ /* USER CODE END SPI1_MspInit 1 */
+
+ }
+
+}
+
+/**
+ * @brief SPI MSP De-Initialization
+ * This function freeze the hardware resources used in this example
+ * @param hspi: SPI handle pointer
+ * @retval None
+ */
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+ if(hspi->Instance==SPI1)
+ {
+ /* USER CODE BEGIN SPI1_MspDeInit 0 */
+
+ /* USER CODE END SPI1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_SPI1_CLK_DISABLE();
+
+ /**SPI1 GPIO Configuration
+ PA5 ------> SPI1_SCK
+ PA6 ------> SPI1_MISO
+ PA7 ------> SPI1_MOSI
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+
+ /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+ /* USER CODE END SPI1_MspDeInit 1 */
+ }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/TP5_OSCILLO_NUM/Core/Src/stm32l1xx_it.c b/TP5_OSCILLO_NUM/Core/Src/stm32l1xx_it.c
new file mode 100644
index 0000000..73b9c1f
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Src/stm32l1xx_it.c
@@ -0,0 +1,217 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32l1xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32l1xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern ADC_HandleTypeDef hadc;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex-M3 Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ /* USER CODE BEGIN SVC_IRQn 0 */
+
+ /* USER CODE END SVC_IRQn 0 */
+ /* USER CODE BEGIN SVC_IRQn 1 */
+
+ /* USER CODE END SVC_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ /* USER CODE BEGIN PendSV_IRQn 0 */
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32L1xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32l1xx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles ADC global interrupt.
+ */
+void ADC1_IRQHandler(void)
+{
+ /* USER CODE BEGIN ADC1_IRQn 0 */
+
+ /* USER CODE END ADC1_IRQn 0 */
+ HAL_ADC_IRQHandler(&hadc);
+ /* USER CODE BEGIN ADC1_IRQn 1 */
+
+ /* USER CODE END ADC1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/TP5_OSCILLO_NUM/Core/Src/syscalls.c b/TP5_OSCILLO_NUM/Core/Src/syscalls.c
new file mode 100644
index 0000000..8884b5a
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Src/syscalls.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file syscalls.c
+ * @author Auto-generated by STM32CubeIDE
+ * @brief STM32CubeIDE Minimal System calls file
+ *
+ * For more information about which c-functions
+ * need which of these lowlevel functions
+ * please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ (void)pid;
+ (void)sig;
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit (int status)
+{
+ _kill(status, -1);
+ while (1) {} /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ (void)file;
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ *ptr++ = __io_getchar();
+ }
+
+ return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+ (void)file;
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ __io_putchar(*ptr++);
+ }
+ return len;
+}
+
+int _close(int file)
+{
+ (void)file;
+ return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+ (void)file;
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _isatty(int file)
+{
+ (void)file;
+ return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+ (void)file;
+ (void)ptr;
+ (void)dir;
+ return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+ (void)path;
+ (void)flags;
+ /* Pretend like we always fail */
+ return -1;
+}
+
+int _wait(int *status)
+{
+ (void)status;
+ errno = ECHILD;
+ return -1;
+}
+
+int _unlink(char *name)
+{
+ (void)name;
+ errno = ENOENT;
+ return -1;
+}
+
+int _times(struct tms *buf)
+{
+ (void)buf;
+ return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+ (void)file;
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _link(char *old, char *new)
+{
+ (void)old;
+ (void)new;
+ errno = EMLINK;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+ (void)name;
+ (void)argv;
+ (void)env;
+ errno = ENOMEM;
+ return -1;
+}
diff --git a/TP5_OSCILLO_NUM/Core/Src/sysmem.c b/TP5_OSCILLO_NUM/Core/Src/sysmem.c
new file mode 100644
index 0000000..5d9f7e6
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Src/sysmem.c
@@ -0,0 +1,79 @@
+/**
+ ******************************************************************************
+ * @file sysmem.c
+ * @author Generated by STM32CubeIDE
+ * @brief STM32CubeIDE System Memory calls file
+ *
+ * For more information about which C functions
+ * need which of these lowlevel functions
+ * please consult the newlib libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2025 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include
+#include
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ * and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * # .data # .bss # newlib heap # MSP stack #
+ * # # # # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start ^-- _end _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+ extern uint8_t _end; /* Symbol defined in the linker script */
+ extern uint8_t _estack; /* Symbol defined in the linker script */
+ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+ const uint8_t *max_heap = (uint8_t *)stack_limit;
+ uint8_t *prev_heap_end;
+
+ /* Initialize heap end at first call */
+ if (NULL == __sbrk_heap_end)
+ {
+ __sbrk_heap_end = &_end;
+ }
+
+ /* Protect heap from growing into the reserved MSP stack */
+ if (__sbrk_heap_end + incr > max_heap)
+ {
+ errno = ENOMEM;
+ return (void *)-1;
+ }
+
+ prev_heap_end = __sbrk_heap_end;
+ __sbrk_heap_end += incr;
+
+ return (void *)prev_heap_end;
+}
diff --git a/TP5_OSCILLO_NUM/Core/Src/system_stm32l1xx.c b/TP5_OSCILLO_NUM/Core/Src/system_stm32l1xx.c
new file mode 100644
index 0000000..093a38b
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Src/system_stm32l1xx.c
@@ -0,0 +1,428 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l1xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32l1xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32l1xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000U) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM32L152D_EVAL board as data memory */
+/* #define DATA_IN_ExtSRAM */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_OFFSET */
+
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+uint32_t SystemCoreClock = 2097000U;
+const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock according to Clock Register Values
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+ * value as defined by the MSI range.
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));
+ break;
+ case 0x04: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+ pllmul = PLLMulTable[(pllmul >> 18)];
+ plldiv = (plldiv >> 22) + 1;
+
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock selected as PLL clock entry */
+ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+ }
+ break;
+ default: /* MSI used as system clock */
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in SystemInit() function before jump to main.
+ * This function configures the external SRAM mounted on STM32L152D_EVAL board
+ * This SRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Flash 1 wait state */
+ FLASH->ACR |= FLASH_ACR_LATENCY;
+
+ /* Power enable */
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
+
+ /* Select the Voltage Range 1 (1.8 V) */
+ PWR->CR = PWR_CR_VOS_0;
+
+ /* Wait Until the Voltage Regulator is ready */
+ while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+ {
+ }
+
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ + SRAM pins assignment +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
+ | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
+ | PD15 <-> FSMC_D1 |--------------------+
+ +-------------------+
+*/
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHBENR = 0x000080D8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
+
+ /* Connect PDx pins to FSMC Alternate function */
+ GPIOD->AFR[0] = 0x00CC00CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A0A;
+ /* Configure PDx pins speed to 40 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0F0F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FSMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 40 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC00F;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FSMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 40 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FSMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x00000C00;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00200AAA;
+ /* Configure PGx pins speed to 40 MHz */
+ GPIOG->OSPEEDR = 0x00300FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FSMC Configuration ------------------------------------------------------*/
+ /* Enable the FSMC interface clock */
+ RCC->AHBENR = 0x400080D8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+
+ (void)(tmpreg);
+
+ /* Configure and enable Bank1_SRAM3 */
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000300;
+ FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+ Bank1_SRAM3 is configured as follow:
+
+ p.FSMC_AddressSetupTime = 0;
+ p.FSMC_AddressHoldTime = 0;
+ p.FSMC_DataSetupTime = 3;
+ p.FSMC_BusTurnAroundDuration = 0;
+ p.FSMC_CLKDivision = 0;
+ p.FSMC_DataLatency = 0;
+ p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
diff --git a/TP5_OSCILLO_NUM/Core/Startup/startup_stm32l152retx.s b/TP5_OSCILLO_NUM/Core/Startup/startup_stm32l152retx.s
new file mode 100644
index 0000000..d3dd841
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Core/Startup/startup_stm32l152retx.s
@@ -0,0 +1,413 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32l152xe.s
+ * @author MCD Application Team
+ * @brief STM32L152XE Devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word USB_HP_IRQHandler
+ .word USB_LP_IRQHandler
+ .word DAC_IRQHandler
+ .word COMP_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word LCD_IRQHandler
+ .word TIM9_IRQHandler
+ .word TIM10_IRQHandler
+ .word TIM11_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word USB_FS_WKUP_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word 0
+ .word COMP_ACQ_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32L152XE devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak USB_HP_IRQHandler
+ .thumb_set USB_HP_IRQHandler,Default_Handler
+
+ .weak USB_LP_IRQHandler
+ .thumb_set USB_LP_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak TIM9_IRQHandler
+ .thumb_set TIM9_IRQHandler,Default_Handler
+
+ .weak TIM10_IRQHandler
+ .thumb_set TIM10_IRQHandler,Default_Handler
+
+ .weak TIM11_IRQHandler
+ .thumb_set TIM11_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USB_FS_WKUP_IRQHandler
+ .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak COMP_ACQ_IRQHandler
+ .thumb_set COMP_ACQ_IRQHandler,Default_Handler
+
+
+
diff --git a/TP5_OSCILLO_NUM/Debug/Core/Src/main.cyclo b/TP5_OSCILLO_NUM/Debug/Core/Src/main.cyclo
new file mode 100644
index 0000000..a9b4475
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Debug/Core/Src/main.cyclo
@@ -0,0 +1,8 @@
+../Core/Src/main.c:67:6:drawHLine_TFT 2
+../Core/Src/main.c:73:6:drawAxes 1
+../Core/Src/main.c:92:5:main 2
+../Core/Src/main.c:158:6:SystemClock_Config 3
+../Core/Src/main.c:199:13:MX_ADC_Init 3
+../Core/Src/main.c:254:13:MX_SPI1_Init 2
+../Core/Src/main.c:292:13:MX_GPIO_Init 1
+../Core/Src/main.c:357:6:Error_Handler 1
diff --git a/TP5_OSCILLO_NUM/Debug/Core/Src/main.d b/TP5_OSCILLO_NUM/Debug/Core/Src/main.d
new file mode 100644
index 0000000..4e4aa95
--- /dev/null
+++ b/TP5_OSCILLO_NUM/Debug/Core/Src/main.d
@@ -0,0 +1,59 @@
+Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \
+ ../Core/Inc/stm32l1xx_hal_conf.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \
+ ../Drivers/CMSIS/Include/core_cm3.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \
+ ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h \
+ ../Drivers/7Seg_MAX7219/max7219.h ../Drivers/TFT_ST7735/fonc_tft.h
+../Core/Inc/main.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h:
+../Core/Inc/stm32l1xx_hal_conf.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h:
+../Drivers/CMSIS/Include/core_cm3.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_adc_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h:
+../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h:
+../Drivers/7Seg_MAX7219/max7219.h:
+../Drivers/TFT_ST7735/fonc_tft.h:
diff --git a/TP5_OSCILLO_NUM/Debug/Core/Src/main.o b/TP5_OSCILLO_NUM/Debug/Core/Src/main.o
new file mode 100644
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