From 9ba9cbc6a6e95663c2f59f6f504d0c170899d0b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?F=C3=A9lix=20MARQUET?= <72651575+BreizhHardware@users.noreply.github.com> Date: Wed, 25 Jun 2025 16:19:43 +0200 Subject: [PATCH] =?UTF-8?q?TP4=20Exo=203=20(Affichage=20d'un=20nombre=20su?= =?UTF-8?q?r=20l=E2=80=99=C3=A9cran=20graphique=20TFT)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- TP4_INIT_TFT/.cproject | 182 + TP4_INIT_TFT/.mxproject | 25 + TP4_INIT_TFT/.project | 32 + .../com.st.stm32cube.ide.mcu.sfrview.prefs | 2 + TP4_INIT_TFT/.settings/language.settings.xml | 25 + .../.settings/org.eclipse.cdt.core.prefs | 6 + .../org.eclipse.core.resources.prefs | 2 + .../.settings/stm32cubeide.project.prefs | 5 + TP4_INIT_TFT/Core/Inc/main.h | 69 + TP4_INIT_TFT/Core/Inc/stm32l1xx_hal_conf.h | 318 + TP4_INIT_TFT/Core/Inc/stm32l1xx_it.h | 66 + TP4_INIT_TFT/Core/Src/main.c | 310 + TP4_INIT_TFT/Core/Src/stm32l1xx_hal_msp.c | 151 + TP4_INIT_TFT/Core/Src/stm32l1xx_it.c | 203 + TP4_INIT_TFT/Core/Src/syscalls.c | 176 + TP4_INIT_TFT/Core/Src/sysmem.c | 79 + TP4_INIT_TFT/Core/Src/system_stm32l1xx.c | 428 + .../Core/Startup/startup_stm32l152retx.s | 413 + TP4_INIT_TFT/Debug/Core/Src/main.cyclo | 6 + TP4_INIT_TFT/Debug/Core/Src/main.d | 55 + TP4_INIT_TFT/Debug/Core/Src/main.o | Bin 0 -> 739848 bytes TP4_INIT_TFT/Debug/Core/Src/main.su | 6 + .../Debug/Core/Src/stm32l1xx_hal_msp.cyclo | 3 + .../Debug/Core/Src/stm32l1xx_hal_msp.d | 52 + .../Debug/Core/Src/stm32l1xx_hal_msp.o | Bin 0 -> 712016 bytes .../Debug/Core/Src/stm32l1xx_hal_msp.su | 3 + .../Debug/Core/Src/stm32l1xx_it.cyclo | 9 + TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.d | 54 + TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.o | Bin 0 -> 708860 bytes TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.su | 9 + TP4_INIT_TFT/Debug/Core/Src/subdir.mk | 42 + TP4_INIT_TFT/Debug/Core/Src/syscalls.cyclo | 18 + TP4_INIT_TFT/Debug/Core/Src/syscalls.d | 1 + TP4_INIT_TFT/Debug/Core/Src/syscalls.o | Bin 0 -> 83424 bytes TP4_INIT_TFT/Debug/Core/Src/syscalls.su | 18 + TP4_INIT_TFT/Debug/Core/Src/sysmem.cyclo | 1 + TP4_INIT_TFT/Debug/Core/Src/sysmem.d | 1 + TP4_INIT_TFT/Debug/Core/Src/sysmem.o | Bin 0 -> 55892 bytes TP4_INIT_TFT/Debug/Core/Src/sysmem.su | 1 + .../Debug/Core/Src/system_stm32l1xx.cyclo | 2 + .../Debug/Core/Src/system_stm32l1xx.d | 51 + .../Debug/Core/Src/system_stm32l1xx.o | Bin 0 -> 709044 bytes .../Debug/Core/Src/system_stm32l1xx.su | 2 + .../Core/Startup/startup_stm32l152retx.d | 2 + .../Core/Startup/startup_stm32l152retx.o | Bin 0 -> 6044 bytes TP4_INIT_TFT/Debug/Core/Startup/subdir.mk | 27 + .../Debug/Drivers/7Seg_MAX7219/max7219.cyclo | 12 + .../Debug/Drivers/7Seg_MAX7219/max7219.d | 54 + .../Debug/Drivers/7Seg_MAX7219/max7219.o | Bin 0 -> 715952 bytes .../Debug/Drivers/7Seg_MAX7219/max7219.su | 12 + .../Debug/Drivers/7Seg_MAX7219/subdir.mk | 27 + .../Src/stm32l1xx_hal.cyclo | 25 + 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.../Src/stm32l1xx_hal_flash_ex.su | 31 + .../Src/stm32l1xx_hal_flash_ramfunc.cyclo | 10 + .../Src/stm32l1xx_hal_flash_ramfunc.d | 52 + .../Src/stm32l1xx_hal_flash_ramfunc.o | Bin 0 -> 713660 bytes .../Src/stm32l1xx_hal_flash_ramfunc.su | 10 + .../Src/stm32l1xx_hal_gpio.cyclo | 8 + .../Src/stm32l1xx_hal_gpio.d | 52 + .../Src/stm32l1xx_hal_gpio.o | Bin 0 -> 713432 bytes .../Src/stm32l1xx_hal_gpio.su | 8 + .../Src/stm32l1xx_hal_pwr.cyclo | 17 + .../Src/stm32l1xx_hal_pwr.d | 52 + .../Src/stm32l1xx_hal_pwr.o | Bin 0 -> 715676 bytes .../Src/stm32l1xx_hal_pwr.su | 17 + .../Src/stm32l1xx_hal_pwr_ex.cyclo | 7 + .../Src/stm32l1xx_hal_pwr_ex.d | 52 + .../Src/stm32l1xx_hal_pwr_ex.o | Bin 0 -> 710336 bytes .../Src/stm32l1xx_hal_pwr_ex.su | 7 + .../Src/stm32l1xx_hal_rcc.cyclo | 15 + .../Src/stm32l1xx_hal_rcc.d | 52 + .../Src/stm32l1xx_hal_rcc.o | Bin 0 -> 722576 bytes .../Src/stm32l1xx_hal_rcc.su | 15 + .../Src/stm32l1xx_hal_rcc_ex.cyclo | 8 + .../Src/stm32l1xx_hal_rcc_ex.d | 52 + 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TP4_INIT_TFT/Debug/TP3_PWM_GENERATOR.map | 3419 ++++++ TP4_INIT_TFT/Debug/TP3_PWM_LED.list | 8719 ++++++++++++++++ TP4_INIT_TFT/Debug/TP3_PWM_LED.map | 3436 ++++++ TP4_INIT_TFT/Debug/TP3_PWM_MOTOR.list | 9179 +++++++++++++++++ TP4_INIT_TFT/Debug/TP3_PWM_MOTOR.map | 3477 +++++++ TP4_INIT_TFT/Debug/TP4_GAMME.list | 8029 ++++++++++++++ TP4_INIT_TFT/Debug/TP4_GAMME.map | 3423 ++++++ TP4_INIT_TFT/Debug/TP4_INIT_TFT.elf | Bin 0 -> 735008 bytes TP4_INIT_TFT/Debug/TP4_INIT_TFT.list | 6808 ++++++++++++ TP4_INIT_TFT/Debug/TP4_INIT_TFT.map | 3104 ++++++ TP4_INIT_TFT/Debug/TP4_MELODIE.list | 8000 ++++++++++++++ TP4_INIT_TFT/Debug/TP4_MELODIE.map | 3415 ++++++ TP4_INIT_TFT/Debug/makefile | 96 + TP4_INIT_TFT/Debug/objects.list | 22 + TP4_INIT_TFT/Debug/objects.mk | 9 + TP4_INIT_TFT/Debug/sources.mk | 30 + TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.c | 269 + TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.h | 15 + .../Device/ST/STM32L1xx/Include/stm32l152xe.h | 9022 ++++++++++++++++ .../Device/ST/STM32L1xx/Include/stm32l1xx.h | 299 + .../ST/STM32L1xx/Include/system_stm32l1xx.h | 107 + .../CMSIS/Device/ST/STM32L1xx/LICENSE.txt | 6 + .../CMSIS/Device/ST/STM32L1xx/License.md | 83 + .../Drivers/CMSIS/Include/cmsis_armcc.h | 865 ++ .../Drivers/CMSIS/Include/cmsis_armclang.h | 1869 ++++ .../Drivers/CMSIS/Include/cmsis_compiler.h | 266 + .../Drivers/CMSIS/Include/cmsis_gcc.h | 2085 ++++ .../Drivers/CMSIS/Include/cmsis_iccarm.h | 935 ++ .../Drivers/CMSIS/Include/cmsis_version.h | 39 + .../Drivers/CMSIS/Include/core_armv8mbl.h | 1918 ++++ .../Drivers/CMSIS/Include/core_armv8mml.h | 2927 ++++++ TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm0.h | 949 ++ .../Drivers/CMSIS/Include/core_cm0plus.h | 1083 ++ TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm1.h | 976 ++ .../Drivers/CMSIS/Include/core_cm23.h | 1993 ++++ TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm3.h | 1941 ++++ .../Drivers/CMSIS/Include/core_cm33.h | 3002 ++++++ TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm4.h | 2129 ++++ TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm7.h | 2671 +++++ .../Drivers/CMSIS/Include/core_sc000.h | 1022 ++ .../Drivers/CMSIS/Include/core_sc300.h | 1915 ++++ .../Drivers/CMSIS/Include/mpu_armv7.h | 270 + .../Drivers/CMSIS/Include/mpu_armv8.h | 333 + .../Drivers/CMSIS/Include/tz_context.h | 70 + TP4_INIT_TFT/Drivers/CMSIS/LICENSE.txt | 201 + .../Inc/Legacy/stm32_hal_legacy.h | 4422 ++++++++ .../STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h | 995 ++ .../Inc/stm32l1xx_hal_cortex.h | 437 + .../Inc/stm32l1xx_hal_def.h | 199 + .../Inc/stm32l1xx_hal_dma.h | 651 ++ .../Inc/stm32l1xx_hal_exti.h | 315 + .../Inc/stm32l1xx_hal_flash.h | 411 + .../Inc/stm32l1xx_hal_flash_ex.h | 965 ++ .../Inc/stm32l1xx_hal_flash_ramfunc.h | 116 + .../Inc/stm32l1xx_hal_gpio.h | 333 + .../Inc/stm32l1xx_hal_gpio_ex.h | 203 + .../Inc/stm32l1xx_hal_pwr.h | 483 + .../Inc/stm32l1xx_hal_pwr_ex.h | 115 + .../Inc/stm32l1xx_hal_rcc.h | 1895 ++++ .../Inc/stm32l1xx_hal_rcc_ex.h | 1027 ++ .../Inc/stm32l1xx_hal_spi.h | 749 ++ .../Inc/stm32l1xx_ll_bus.h | 1100 ++ .../Inc/stm32l1xx_ll_cortex.h | 637 ++ .../Inc/stm32l1xx_ll_dma.h | 1996 ++++ .../Inc/stm32l1xx_ll_exti.h | 1015 ++ .../Inc/stm32l1xx_ll_gpio.h | 987 ++ .../Inc/stm32l1xx_ll_pwr.h | 718 ++ .../Inc/stm32l1xx_ll_rcc.h | 1796 ++++ .../Inc/stm32l1xx_ll_spi.h | 2015 ++++ .../Inc/stm32l1xx_ll_system.h | 2007 ++++ .../Inc/stm32l1xx_ll_utils.h | 270 + .../Drivers/STM32L1xx_HAL_Driver/LICENSE.txt | 6 + .../Drivers/STM32L1xx_HAL_Driver/License.md | 3 + .../STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c | 570 + .../Src/stm32l1xx_hal_cortex.c | 537 + .../Src/stm32l1xx_hal_dma.c | 909 ++ .../Src/stm32l1xx_hal_exti.c | 547 + .../Src/stm32l1xx_hal_flash.c | 723 ++ .../Src/stm32l1xx_hal_flash_ex.c | 1870 ++++ .../Src/stm32l1xx_hal_flash_ramfunc.c | 640 ++ .../Src/stm32l1xx_hal_gpio.c | 546 + .../Src/stm32l1xx_hal_pwr.c | 650 ++ .../Src/stm32l1xx_hal_pwr_ex.c | 158 + .../Src/stm32l1xx_hal_rcc.c | 1394 +++ .../Src/stm32l1xx_hal_rcc_ex.c | 447 + .../Src/stm32l1xx_hal_spi.c | 3962 +++++++ TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.c | 1065 ++ TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.h | 65 + TP4_INIT_TFT/STM32L152RETX_FLASH.ld | 187 + TP4_INIT_TFT/STM32L152RETX_RAM.ld | 187 + TP4_INIT_TFT/TP4_INIT_TFT Debug.launch | 85 + TP4_INIT_TFT/TP4_INIT_TFT.ioc | 145 + 208 files changed, 180907 insertions(+) create mode 100644 TP4_INIT_TFT/.cproject create mode 100644 TP4_INIT_TFT/.mxproject create mode 100644 TP4_INIT_TFT/.project create mode 100644 TP4_INIT_TFT/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs create mode 100644 TP4_INIT_TFT/.settings/language.settings.xml create mode 100644 TP4_INIT_TFT/.settings/org.eclipse.cdt.core.prefs create mode 100644 TP4_INIT_TFT/.settings/org.eclipse.core.resources.prefs create mode 100644 TP4_INIT_TFT/.settings/stm32cubeide.project.prefs create mode 100644 TP4_INIT_TFT/Core/Inc/main.h create mode 100644 TP4_INIT_TFT/Core/Inc/stm32l1xx_hal_conf.h create mode 100644 TP4_INIT_TFT/Core/Inc/stm32l1xx_it.h create mode 100644 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+ +[PreviousUsedCubeIDEFiles] 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+HeaderPath=Drivers/STM32L1xx_HAL_Driver/Inc;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L1xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_HAL_DRIVER;STM32L152xE;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=../Core/Inc/stm32l1xx_it.h +HeaderFiles#1=../Core/Inc/stm32l1xx_hal_conf.h +HeaderFiles#2=../Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=../Core/Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=../Core/Src/stm32l1xx_it.c +SourceFiles#1=../Core/Src/stm32l1xx_hal_msp.c +SourceFiles#2=../Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=../Core/Src +SourceFiles=; + diff --git a/TP4_INIT_TFT/.project b/TP4_INIT_TFT/.project new file mode 100644 index 0000000..1815b41 --- /dev/null +++ b/TP4_INIT_TFT/.project @@ -0,0 +1,32 @@ + + + TP4_INIT_TFT + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/TP4_INIT_TFT/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/TP4_INIT_TFT/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 0000000..98a69fc --- /dev/null +++ b/TP4_INIT_TFT/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/TP4_INIT_TFT/.settings/language.settings.xml b/TP4_INIT_TFT/.settings/language.settings.xml new file mode 100644 index 0000000..fd737e1 --- /dev/null +++ b/TP4_INIT_TFT/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/TP4_INIT_TFT/.settings/org.eclipse.cdt.core.prefs b/TP4_INIT_TFT/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000..c8ec5df --- /dev/null +++ b/TP4_INIT_TFT/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,6 @@ +doxygen/doxygen_new_line_after_brief=true +doxygen/doxygen_use_brief_tag=false +doxygen/doxygen_use_javadoc_tags=true +doxygen/doxygen_use_pre_tag=false +doxygen/doxygen_use_structural_commands=false +eclipse.preferences.version=1 diff --git a/TP4_INIT_TFT/.settings/org.eclipse.core.resources.prefs b/TP4_INIT_TFT/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..99f26c0 --- /dev/null +++ b/TP4_INIT_TFT/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/TP4_INIT_TFT/.settings/stm32cubeide.project.prefs b/TP4_INIT_TFT/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..a0b3b52 --- /dev/null +++ b/TP4_INIT_TFT/.settings/stm32cubeide.project.prefs @@ -0,0 +1,5 @@ +635E684B79701B039C64EA45C3F84D30=20408E19A1D483CC68E7BF859CC595B4 +66BE74F758C12D739921AEA421D593D3=3 +8DF89ED150041C4CBC7CB9A9CAA90856=787343FA0477F66DEA4B2B86368887F5 +DC22A860405A8BF2F2C095E5B6529F12=787343FA0477F66DEA4B2B86368887F5 +eclipse.preferences.version=1 diff --git a/TP4_INIT_TFT/Core/Inc/main.h b/TP4_INIT_TFT/Core/Inc/main.h new file mode 100644 index 0000000..f645caf --- /dev/null +++ b/TP4_INIT_TFT/Core/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/TP4_INIT_TFT/Core/Inc/stm32l1xx_hal_conf.h b/TP4_INIT_TFT/Core/Inc/stm32l1xx_hal_conf.h new file mode 100644 index 0000000..7ce33fa --- /dev/null +++ b/TP4_INIT_TFT/Core/Inc/stm32l1xx_hal_conf.h @@ -0,0 +1,318 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l1xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CONF_H +#define __STM32L1xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE (37000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 0 +#define INSTRUCTION_CACHE_ENABLE 1 +#define DATA_CACHE_ENABLE 1 + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/deregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32l0xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SDMMC_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ + +#define USE_SPI_CRC 0U +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32l1xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32l1xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32l1xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32l1xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32l1xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32l1xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32l1xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32l1xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32l1xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32l1xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32l1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32l1xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32l1xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32l1xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32l1xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LCD_MODULE_ENABLED + #include "stm32l1xx_hal_lcd.h" +#endif /* HAL_LCD_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32l1xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32l1xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32l1xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32l1xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32l1xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32l1xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32l1xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32l1xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32l1xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32l1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32l1xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32l1xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32l1xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CONF_H */ + diff --git a/TP4_INIT_TFT/Core/Inc/stm32l1xx_it.h b/TP4_INIT_TFT/Core/Inc/stm32l1xx_it.h new file mode 100644 index 0000000..2c5eb24 --- /dev/null +++ b/TP4_INIT_TFT/Core/Inc/stm32l1xx_it.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l1xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_IT_H +#define __STM32L1xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_IT_H */ diff --git a/TP4_INIT_TFT/Core/Src/main.c b/TP4_INIT_TFT/Core/Src/main.c new file mode 100644 index 0000000..670ef32 --- /dev/null +++ b/TP4_INIT_TFT/Core/Src/main.c @@ -0,0 +1,310 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "max7219.h" +#include "fonc_tft.h" +#include + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +SPI_HandleTypeDef hspi1; + +/* USER CODE BEGIN PV */ + + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_SPI1_Init(void); +/* USER CODE BEGIN PFP */ +void affiche_nombre(char nombre[], uint8_t col, uint8_t ligne); + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void affiche_nombre(char nombre[], uint8_t col, uint8_t ligne) { + int nombre_int = atoi(nombre); + + if (nombre_int < 0 || nombre_int > 9999) { + return; + } + + uint8_t mil = nombre_int / 1000; + uint8_t cen = (nombre_int / 100) % 10; + uint8_t diz = (nombre_int / 10) % 10; + uint8_t uni = nombre_int % 10; + + displayChar_TFT(col, ligne, mil + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); + displayChar_TFT(col + 12, ligne, cen + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); + displayChar_TFT(col + 24, ligne, diz + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); + displayChar_TFT(col + 36, ligne, uni + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); +} + + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_SPI1_Init(); + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + init_TFT(); + MAX7219_Clear(); + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + char nombre[] = "4090"; + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + affiche_nombre(nombre, 10, 80); + } + + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET); + + /*Configure GPIO pins : PC0 PC1 PC2 PC3 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PB15 */ + GPIO_InitStruct.Pin = GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/TP4_INIT_TFT/Core/Src/stm32l1xx_hal_msp.c b/TP4_INIT_TFT/Core/Src/stm32l1xx_hal_msp.c new file mode 100644 index 0000000..7b71e54 --- /dev/null +++ b/TP4_INIT_TFT/Core/Src/stm32l1xx_hal_msp.c @@ -0,0 +1,151 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l1xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** + * @brief SPI MSP Initialization + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + +/** + * @brief SPI MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/TP4_INIT_TFT/Core/Src/stm32l1xx_it.c b/TP4_INIT_TFT/Core/Src/stm32l1xx_it.c new file mode 100644 index 0000000..afd5dcc --- /dev/null +++ b/TP4_INIT_TFT/Core/Src/stm32l1xx_it.c @@ -0,0 +1,203 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32l1xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32l1xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M3 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32L1xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32l1xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/TP4_INIT_TFT/Core/Src/syscalls.c b/TP4_INIT_TFT/Core/Src/syscalls.c new file mode 100644 index 0000000..8884b5a --- /dev/null +++ b/TP4_INIT_TFT/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/TP4_INIT_TFT/Core/Src/sysmem.c b/TP4_INIT_TFT/Core/Src/sysmem.c new file mode 100644 index 0000000..5d9f7e6 --- /dev/null +++ b/TP4_INIT_TFT/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/TP4_INIT_TFT/Core/Src/system_stm32l1xx.c b/TP4_INIT_TFT/Core/Src/system_stm32l1xx.c new file mode 100644 index 0000000..093a38b --- /dev/null +++ b/TP4_INIT_TFT/Core/Src/system_stm32l1xx.c @@ -0,0 +1,428 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l1xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** @addtogroup STM32L1xx_System_Private_Includes + * @{ + */ + +#include "stm32l1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM32L152D_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ + +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 2097000U; +const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in SystemInit() function before jump to main. + * This function configures the external SRAM mounted on STM32L152D_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmpreg = 0; + + /* Flash 1 wait state */ + FLASH->ACR |= FLASH_ACR_LATENCY; + + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ + | PD15 <-> FSMC_D1 |--------------------+ + +-------------------+ +*/ + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHBENR = 0x000080D8; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00CC00CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A0A; + /* Configure PDx pins speed to 40 MHz */ + GPIOD->OSPEEDR = 0xFFFF0F0F; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 40 MHz */ + GPIOE->OSPEEDR = 0xFFFFC00F; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 40 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x00000C00; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00200AAA; + /* Configure PGx pins speed to 40 MHz */ + GPIOG->OSPEEDR = 0x00300FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHBENR = 0x400080D8; + + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); + + (void)(tmpreg); + + /* Configure and enable Bank1_SRAM3 */ + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000300; + FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; +/* + Bank1_SRAM3 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 3; + p.FSMC_BusTurnAroundDuration = 0; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; + + FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); + + FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); +*/ + +} +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/TP4_INIT_TFT/Core/Startup/startup_stm32l152retx.s b/TP4_INIT_TFT/Core/Startup/startup_stm32l152retx.s new file mode 100644 index 0000000..d3dd841 --- /dev/null +++ b/TP4_INIT_TFT/Core/Startup/startup_stm32l152retx.s @@ -0,0 +1,413 @@ +/** + ****************************************************************************** + * @file startup_stm32l152xe.s + * @author MCD Application Team + * @brief STM32L152XE Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word COMP_ACQ_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L152XE devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_ACQ_IRQHandler + .thumb_set COMP_ACQ_IRQHandler,Default_Handler + + + diff --git a/TP4_INIT_TFT/Debug/Core/Src/main.cyclo b/TP4_INIT_TFT/Debug/Core/Src/main.cyclo new file mode 100644 index 0000000..a9dfdb6 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Core/Src/main.cyclo @@ -0,0 +1,6 @@ +../Core/Src/main.c:64:6:affiche_nombre 3 +../Core/Src/main.c:89:5:main 1 +../Core/Src/main.c:140:6:SystemClock_Config 3 +../Core/Src/main.c:181:13:MX_SPI1_Init 2 +../Core/Src/main.c:219:13:MX_GPIO_Init 1 +../Core/Src/main.c:284:6:Error_Handler 1 diff --git a/TP4_INIT_TFT/Debug/Core/Src/main.d b/TP4_INIT_TFT/Debug/Core/Src/main.d new file mode 100644 index 0000000..7ffea36 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Core/Src/main.d @@ -0,0 +1,55 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h \ + ../Drivers/7Seg_MAX7219/max7219.h ../Drivers/TFT_ST7735/fonc_tft.h +../Core/Inc/main.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: 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+../Core/Src/stm32l1xx_hal_msp.c:125:6:HAL_SPI_MspDeInit 16 static diff --git a/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.cyclo b/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.cyclo new file mode 100644 index 0000000..79351de --- /dev/null +++ b/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.cyclo @@ -0,0 +1,9 @@ +../Core/Src/stm32l1xx_it.c:69:6:NMI_Handler 1 +../Core/Src/stm32l1xx_it.c:84:6:HardFault_Handler 1 +../Core/Src/stm32l1xx_it.c:99:6:MemManage_Handler 1 +../Core/Src/stm32l1xx_it.c:114:6:BusFault_Handler 1 +../Core/Src/stm32l1xx_it.c:129:6:UsageFault_Handler 1 +../Core/Src/stm32l1xx_it.c:144:6:SVC_Handler 1 +../Core/Src/stm32l1xx_it.c:157:6:DebugMon_Handler 1 +../Core/Src/stm32l1xx_it.c:170:6:PendSV_Handler 1 +../Core/Src/stm32l1xx_it.c:183:6:SysTick_Handler 1 diff --git a/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.d b/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.d new file mode 100644 index 0000000..9cdcc59 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.d @@ -0,0 +1,54 @@ +Core/Src/stm32l1xx_it.o: ../Core/Src/stm32l1xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h \ + ../Core/Inc/stm32l1xx_it.h +../Core/Inc/main.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h: 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a/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.su b/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.su new file mode 100644 index 0000000..affde81 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Core/Src/stm32l1xx_it.su @@ -0,0 +1,9 @@ +../Core/Src/stm32l1xx_it.c:69:6:NMI_Handler 4 static +../Core/Src/stm32l1xx_it.c:84:6:HardFault_Handler 4 static +../Core/Src/stm32l1xx_it.c:99:6:MemManage_Handler 4 static +../Core/Src/stm32l1xx_it.c:114:6:BusFault_Handler 4 static +../Core/Src/stm32l1xx_it.c:129:6:UsageFault_Handler 4 static +../Core/Src/stm32l1xx_it.c:144:6:SVC_Handler 4 static +../Core/Src/stm32l1xx_it.c:157:6:DebugMon_Handler 4 static +../Core/Src/stm32l1xx_it.c:170:6:PendSV_Handler 4 static +../Core/Src/stm32l1xx_it.c:183:6:SysTick_Handler 8 static diff --git a/TP4_INIT_TFT/Debug/Core/Src/subdir.mk b/TP4_INIT_TFT/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..9a450e8 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Core/Src/subdir.mk @@ -0,0 +1,42 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/main.c \ +../Core/Src/stm32l1xx_hal_msp.c \ +../Core/Src/stm32l1xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32l1xx.c + +OBJS += \ +./Core/Src/main.o \ +./Core/Src/stm32l1xx_hal_msp.o \ +./Core/Src/stm32l1xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32l1xx.o + +C_DEPS += \ +./Core/Src/main.d \ +./Core/Src/stm32l1xx_hal_msp.d \ +./Core/Src/stm32l1xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32l1xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L152xE -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -I../Drivers/7Seg_MAX7219 -I../Drivers/TFT_ST7735 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32l1xx_hal_msp.cyclo ./Core/Src/stm32l1xx_hal_msp.d ./Core/Src/stm32l1xx_hal_msp.o ./Core/Src/stm32l1xx_hal_msp.su ./Core/Src/stm32l1xx_it.cyclo ./Core/Src/stm32l1xx_it.d ./Core/Src/stm32l1xx_it.o ./Core/Src/stm32l1xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32l1xx.cyclo ./Core/Src/system_stm32l1xx.d ./Core/Src/system_stm32l1xx.o ./Core/Src/system_stm32l1xx.su + +.PHONY: clean-Core-2f-Src + diff --git a/TP4_INIT_TFT/Debug/Core/Src/syscalls.cyclo b/TP4_INIT_TFT/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 0000000..6cbfdd0 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 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b/TP4_INIT_TFT/Debug/Core/Src/system_stm32l1xx.d @@ -0,0 +1,51 @@ +Core/Src/system_stm32l1xx.o: ../Core/Src/system_stm32l1xx.c \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: 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Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32l152retx.s + +OBJS += \ +./Core/Startup/startup_stm32l152retx.o + +S_DEPS += \ +./Core/Startup/startup_stm32l152retx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m3 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32l152retx.d ./Core/Startup/startup_stm32l152retx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/TP4_INIT_TFT/Debug/Drivers/7Seg_MAX7219/max7219.cyclo b/TP4_INIT_TFT/Debug/Drivers/7Seg_MAX7219/max7219.cyclo new file mode 100644 index 0000000..2eb1da7 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/7Seg_MAX7219/max7219.cyclo @@ -0,0 +1,12 @@ +../Drivers/7Seg_MAX7219/max7219.c:100:6:MAX7219_Init 1 +../Drivers/7Seg_MAX7219/max7219.c:121:6:MAX7219_ShutdownStart 1 +../Drivers/7Seg_MAX7219/max7219.c:136:6:MAX7219_ShutdownStop 1 +../Drivers/7Seg_MAX7219/max7219.c:149:6:MAX7219_DisplayTestStart 1 +../Drivers/7Seg_MAX7219/max7219.c:165:6:MAX7219_DisplayTestStop 1 +../Drivers/7Seg_MAX7219/max7219.c:180:6:MAX7219_SetBrightness 1 +../Drivers/7Seg_MAX7219/max7219.c:196:6:MAX7219_Clear 2 +../Drivers/7Seg_MAX7219/max7219.c:214:6:MAX7219_DisplayChar 1 +../Drivers/7Seg_MAX7219/max7219.c:220:6:MAX7219_DisplayCharPointOff 1 +../Drivers/7Seg_MAX7219/max7219.c:225:6:MAX7219_DisplayCharPointOn 1 +../Drivers/7Seg_MAX7219/max7219.c:243:6:MAX7219_Write 1 +../Drivers/7Seg_MAX7219/max7219.c:262:13:MAX7219_SendByte 1 diff --git a/TP4_INIT_TFT/Debug/Drivers/7Seg_MAX7219/max7219.d b/TP4_INIT_TFT/Debug/Drivers/7Seg_MAX7219/max7219.d new file mode 100644 index 0000000..102bf96 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/7Seg_MAX7219/max7219.d @@ -0,0 +1,54 @@ +Drivers/7Seg_MAX7219/max7219.o: ../Drivers/7Seg_MAX7219/max7219.c \ + ../Core/Inc/main.h ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h \ + ../Drivers/7Seg_MAX7219/max7219.h +../Core/Inc/main.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: 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+../Drivers/CMSIS/Include/core_cm3.h:1547:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm3.h:1566:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm3.h:1585:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm3.h:1600:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm3.h:1617:26:__NVIC_GetActive 16 static +../Drivers/CMSIS/Include/core_cm3.h:1639:22:__NVIC_SetPriority 16 static +../Drivers/CMSIS/Include/core_cm3.h:1661:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm3.h:1686:26:NVIC_EncodePriority 40 static +../Drivers/CMSIS/Include/core_cm3.h:1713:22:NVIC_DecodePriority 40 static +../Drivers/CMSIS/Include/core_cm3.h:1762:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm3.h:1834:26:SysTick_Config 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:168:6:HAL_NVIC_SetPriorityGrouping 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:190:6:HAL_NVIC_SetPriority 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:212:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:228:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:241:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:254:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:290:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:304:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:317:6:HAL_MPU_EnableRegion 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:333:6:HAL_MPU_DisableRegion 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:351:6:HAL_MPU_ConfigRegion 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:389:10:HAL_NVIC_GetPriorityGrouping 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:416:6:HAL_NVIC_GetPriority 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:431:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:446:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:459:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:473:10:HAL_NVIC_GetActive 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:487:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:505:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c:514:13:HAL_SYSTICK_Callback 4 static diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.cyclo b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.cyclo new file mode 100644 index 0000000..7a3ffe2 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.cyclo @@ -0,0 +1,13 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:144:19:HAL_DMA_Init 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:223:19:HAL_DMA_DeInit 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:315:19:HAL_DMA_Start 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:358:19:HAL_DMA_Start_IT 4 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:413:19:HAL_DMA_Abort 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:454:19:HAL_DMA_Abort_IT 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:499:19:HAL_DMA_PollForTransfer 10 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:600:6:HAL_DMA_IRQHandler 12 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:697:19:HAL_DMA_RegisterCallback 7 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:748:19:HAL_DMA_UnRegisterCallback 8 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:826:22:HAL_DMA_GetState 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:838:10:HAL_DMA_GetError 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c:864:13:DMA_SetConfig 2 diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d new file mode 100644 index 0000000..a4a60dd --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d @@ -0,0 +1,52 @@ +Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o: \ + ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + 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b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:142:19:HAL_EXTI_SetConfigLine 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:237:19:HAL_EXTI_GetConfigLine 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:316:19:HAL_EXTI_ClearConfigLine 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:369:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:394:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:434:6:HAL_EXTI_IRQHandler 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:466:10:HAL_EXTI_GetPending 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:495:6:HAL_EXTI_ClearPending 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c:516:6:HAL_EXTI_GenerateSWI 24 static diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.cyclo b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.cyclo new file mode 100644 index 0000000..f6e8b03 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.cyclo @@ -0,0 +1,13 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:229:19:HAL_FLASH_Program 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:271:19:HAL_FLASH_Program_IT 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:302:6:HAL_FLASH_IRQHandler 12 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:417:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:434:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:467:19:HAL_FLASH_Unlock 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:502:19:HAL_FLASH_Lock 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:514:19:HAL_FLASH_OB_Unlock 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:550:19:HAL_FLASH_OB_Lock 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:563:19:HAL_FLASH_OB_Launch 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:595:10:HAL_FLASH_GetError 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:617:19:FLASH_WaitForLastOperation 11 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:668:13:FLASH_SetErrorCode 6 diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d new file mode 100644 index 0000000..ff081a7 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d @@ -0,0 +1,52 @@ +Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o: \ + ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: 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+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:417:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:434:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:467:19:HAL_FLASH_Unlock 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:502:19:HAL_FLASH_Lock 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:514:19:HAL_FLASH_OB_Unlock 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:550:19:HAL_FLASH_OB_Lock 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:563:19:HAL_FLASH_OB_Launch 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:595:10:HAL_FLASH_GetError 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:617:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c:668:13:FLASH_SetErrorCode 16 static diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.cyclo b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.cyclo new file mode 100644 index 0000000..8ebac3a --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.cyclo @@ -0,0 +1,31 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:185:19:HAL_FLASHEx_Erase 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:281:19:HAL_FLASHEx_Erase_IT 4 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:404:19:HAL_FLASHEx_OBProgram 11 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:486:6:HAL_FLASHEx_OBGetConfig 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:540:19:HAL_FLASHEx_AdvOBProgram 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:597:6:HAL_FLASHEx_AdvOBGetConfig 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:749:19:HAL_FLASHEx_DATAEEPROM_Unlock 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:768:19:HAL_FLASHEx_DATAEEPROM_Lock 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:788:19:HAL_FLASHEx_DATAEEPROM_Erase 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:846:21:HAL_FLASHEx_DATAEEPROM_Program 9 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:911:6:HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:920:6:HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:956:26:FLASH_OB_RDPConfig 4 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1020:26:FLASH_OB_BORConfig 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1058:16:FLASH_OB_GetUser 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1072:16:FLASH_OB_GetRDP 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1090:16:FLASH_OB_GetBOR 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1104:26:FLASH_OB_WRPConfig 6 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1235:13:FLASH_OB_WRPConfigWRP1OrPCROP1 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1281:13:FLASH_OB_WRPConfigWRP2OrPCROP2 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1327:13:FLASH_OB_WRPConfigWRP3 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1372:13:FLASH_OB_WRPConfigWRP4 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1422:26:FLASH_OB_UserConfig 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1475:26:FLASH_OB_BootConfig 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1524:26:FLASH_DATAEEPROM_FastProgramByte 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1584:26:FLASH_DATAEEPROM_FastProgramHalfWord 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1652:26:FLASH_DATAEEPROM_FastProgramWord 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1683:26:FLASH_DATAEEPROM_ProgramByte 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1737:26:FLASH_DATAEEPROM_ProgramHalfWord 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1798:26:FLASH_DATAEEPROM_ProgramWord 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1843:6:FLASH_PageErase 1 diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d new file mode 100644 index 0000000..a16b882 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d @@ -0,0 +1,52 @@ +Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o: \ + ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o new file mode 100644 index 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a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su new file mode 100644 index 0000000..2d287b1 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su @@ -0,0 +1,31 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:185:19:HAL_FLASHEx_Erase 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:281:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:404:19:HAL_FLASHEx_OBProgram 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:486:6:HAL_FLASHEx_OBGetConfig 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:540:19:HAL_FLASHEx_AdvOBProgram 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:597:6:HAL_FLASHEx_AdvOBGetConfig 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:749:19:HAL_FLASHEx_DATAEEPROM_Unlock 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:768:19:HAL_FLASHEx_DATAEEPROM_Lock 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:788:19:HAL_FLASHEx_DATAEEPROM_Erase 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:846:21:HAL_FLASHEx_DATAEEPROM_Program 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:911:6:HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:920:6:HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:956:26:FLASH_OB_RDPConfig 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1020:26:FLASH_OB_BORConfig 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1058:16:FLASH_OB_GetUser 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1072:16:FLASH_OB_GetRDP 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1090:16:FLASH_OB_GetBOR 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1104:26:FLASH_OB_WRPConfig 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1235:13:FLASH_OB_WRPConfigWRP1OrPCROP1 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1281:13:FLASH_OB_WRPConfigWRP2OrPCROP2 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1327:13:FLASH_OB_WRPConfigWRP3 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1372:13:FLASH_OB_WRPConfigWRP4 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1422:26:FLASH_OB_UserConfig 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1475:26:FLASH_OB_BootConfig 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1524:26:FLASH_DATAEEPROM_FastProgramByte 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1584:26:FLASH_DATAEEPROM_FastProgramHalfWord 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1652:26:FLASH_DATAEEPROM_FastProgramWord 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1683:26:FLASH_DATAEEPROM_ProgramByte 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1737:26:FLASH_DATAEEPROM_ProgramHalfWord 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1798:26:FLASH_DATAEEPROM_ProgramWord 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c:1843:6:FLASH_PageErase 16 static diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.cyclo b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.cyclo new file mode 100644 index 0000000..569838d --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.cyclo @@ -0,0 +1,10 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:113:30:HAL_FLASHEx_EnableRunPowerDown 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:126:30:HAL_FLASHEx_DisableRunPowerDown 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:163:30:HAL_FLASHEx_EraseParallelPage 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:224:30:HAL_FLASHEx_ProgramParallelHalfPage 4 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:302:30:HAL_FLASHEx_HalfPageProgram 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:394:30:HAL_FLASHEx_GetError 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:426:30:HAL_FLASHEx_DATAEEPROM_EraseDoubleWord 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:486:30:HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:586:37:FLASHRAM_WaitForLastOperation 9 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c:540:37:FLASHRAM_SetErrorCode 5 diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d new file mode 100644 index 0000000..49ae568 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d @@ -0,0 +1,52 @@ +Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o: \ + ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: 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static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:390:6:HAL_PWR_DisablePVD 16 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:405:6:HAL_PWR_EnableWakeUpPin 24 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:422:6:HAL_PWR_DisableWakeUpPin 24 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:445:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:494:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:534:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:559:6:HAL_PWR_EnableSleepOnExit 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:572:6:HAL_PWR_DisableSleepOnExit 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:585:6:HAL_PWR_EnableSEVOnPend 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:598:6:HAL_PWR_DisableSEVOnPend 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:611:6:HAL_PWR_PVD_IRQHandler 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c:628:13:HAL_PWR_PVDCallback 4 static diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.cyclo b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.cyclo new file mode 100644 index 0000000..67dc12f --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.cyclo @@ -0,0 +1,7 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c:65:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c:78:6:HAL_PWREx_EnableFastWakeUp 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c:88:6:HAL_PWREx_DisableFastWakeUp 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c:98:6:HAL_PWREx_EnableUltraLowPower 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c:108:6:HAL_PWREx_DisableUltraLowPower 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c:124:6:HAL_PWREx_EnableLowPowerRunMode 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c:135:19:HAL_PWREx_DisableLowPowerRunMode 1 diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d new file mode 100644 index 0000000..2a439c2 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d @@ -0,0 +1,52 @@ +Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o: \ + ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o new file mode 100644 index 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+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:797:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1003:6:HAL_RCC_MCOConfig 48 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1040:6:HAL_RCC_EnableCSS 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1049:6:HAL_RCC_DisableCSS 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1084:10:HAL_RCC_GetSysClockFreq 88 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1140:10:HAL_RCC_GetHCLKFreq 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1151:10:HAL_RCC_GetPCLK1Freq 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1163:10:HAL_RCC_GetPCLK2Freq 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1176:6:HAL_RCC_GetOscConfig 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1272:6:HAL_RCC_GetClockConfig 16 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1302:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1319:13:HAL_RCC_CSSCallback 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c:1344:26:RCC_SetFlashLatencyFromMSIRange 32 static diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.cyclo b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.cyclo new file mode 100644 index 0000000..e67d81f --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:90:19:HAL_RCCEx_PeriphCLKConfig 24 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:229:6:HAL_RCCEx_GetPeriphCLKConfig 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:266:10:HAL_RCCEx_GetPeriphCLKFreq 12 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:358:6:HAL_RCCEx_EnableLSECSS 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:371:6:HAL_RCCEx_DisableLSECSS 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:385:6:HAL_RCCEx_EnableLSECSS_IT 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:402:6:HAL_RCCEx_LSECSS_IRQHandler 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:419:13:HAL_RCCEx_LSECSS_Callback 1 diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d new file mode 100644 index 0000000..562e0f7 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d @@ -0,0 +1,52 @@ +Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o: \ + ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o new file mode 100644 index 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+../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:90:19:HAL_RCCEx_PeriphCLKConfig 32 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:229:6:HAL_RCCEx_GetPeriphCLKConfig 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:266:10:HAL_RCCEx_GetPeriphCLKFreq 24 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:358:6:HAL_RCCEx_EnableLSECSS 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:371:6:HAL_RCCEx_DisableLSECSS 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:385:6:HAL_RCCEx_EnableLSECSS_IT 4 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:402:6:HAL_RCCEx_LSECSS_IRQHandler 8 static +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c:419:13:HAL_RCCEx_LSECSS_Callback 4 static diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.cyclo b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.cyclo new file mode 100644 index 0000000..e52466e --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.cyclo @@ -0,0 +1,55 @@ +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:313:19:HAL_SPI_Init 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:446:19:HAL_SPI_DeInit 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:490:13:HAL_SPI_MspInit 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:506:13:HAL_SPI_MspDeInit 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:778:19:HAL_SPI_Transmit 25 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:947:19:HAL_SPI_Receive 22 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:1147:19:HAL_SPI_TransmitReceive 38 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:1398:19:HAL_SPI_Transmit_IT 8 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:1480:19:HAL_SPI_Receive_IT 10 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:1571:19:HAL_SPI_TransmitReceive_IT 12 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:1658:19:HAL_SPI_Transmit_DMA 8 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:1762:19:HAL_SPI_Receive_DMA 10 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:1872:19:HAL_SPI_TransmitReceive_DMA 14 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2015:19:HAL_SPI_Abort 16 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2162:19:HAL_SPI_Abort_IT 19 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2325:19:HAL_SPI_DMAPause 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2345:19:HAL_SPI_DMAResume 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2365:19:HAL_SPI_DMAStop 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2407:6:HAL_SPI_IRQHandler 21 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2521:13:HAL_SPI_TxCpltCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2537:13:HAL_SPI_RxCpltCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2553:13:HAL_SPI_TxRxCpltCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2569:13:HAL_SPI_TxHalfCpltCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2585:13:HAL_SPI_RxHalfCpltCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2601:13:HAL_SPI_TxRxHalfCpltCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2617:13:HAL_SPI_ErrorCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2635:13:HAL_SPI_AbortCpltCallback 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2670:22:HAL_SPI_GetState 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2682:10:HAL_SPI_GetError 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2707:13:SPI_DMATransmitCplt 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2764:13:SPI_DMAReceiveCplt 6 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2853:13:SPI_DMATransmitReceiveCplt 4 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2933:13:SPI_DMAHalfTransmitCplt 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2951:13:SPI_DMAHalfReceiveCplt 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2969:13:SPI_DMAHalfTransmitReceiveCplt 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:2987:13:SPI_DMAError 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3010:13:SPI_DMAAbortOnError 1 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3032:13:SPI_DMATxAbortCallback 6 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3099:13:SPI_DMARxAbortCallback 5 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3160:13:SPI_2linesRxISR_8BIT 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3223:13:SPI_2linesTxISR_8BIT 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3259:13:SPI_2linesRxISR_16BIT 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3315:13:SPI_2linesTxISR_16BIT 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3375:13:SPI_RxISR_8BIT 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3431:13:SPI_RxISR_16BIT 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3464:13:SPI_TxISR_8BIT 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3489:13:SPI_TxISR_16BIT 2 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3519:26:SPI_WaitFlagStateUntilTimeout 10 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3586:26:SPI_EndRxTransaction 9 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3636:26:SPI_EndRxTxTransaction 6 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3683:13:SPI_CloseRxTx_ISR 7 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3778:13:SPI_CloseRx_ISR 4 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3841:13:SPI_CloseTx_ISR 6 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3902:13:SPI_AbortRx_ISR 3 +../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c:3938:13:SPI_AbortTx_ISR 1 diff --git a/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.d b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.d new file mode 100644 index 0000000..67fa3ac --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.d @@ -0,0 +1,52 @@ +Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o: \ + ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ + ../Core/Inc/stm32l1xx_hal_conf.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ + ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h \ + ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Core/Inc/stm32l1xx_hal_conf.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: 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: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000510: b580 push {r7, lr} + 8000512: b082 sub sp, #8 + 8000514: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000516: f000 fa39 bl 800098c + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 800051a: f000 f81b bl 8000554 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 800051e: f000 f895 bl 800064c + MX_SPI1_Init(); + 8000522: f000 f85d bl 80005e0 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 8000526: f000 f99e bl 8000866 + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 800052a: f000 f9d3 bl 80008d4 + uint8_t compteur = 0; + 800052e: 2300 movs r3, #0 + 8000530: 71fb strb r3, [r7, #7] +#ifdef V1 + MAX7219_DisplayChar(1, 3); + MAX7219_DisplayChar(2, 5); +#endif +#ifdef V2 + affiche(compteur); + 8000532: 79fb ldrb r3, [r7, #7] + 8000534: 4618 mov r0, r3 + 8000536: f7ff ffbb bl 80004b0 + compteur++; + 800053a: 79fb ldrb r3, [r7, #7] + 800053c: 3301 adds r3, #1 + 800053e: 71fb strb r3, [r7, #7] + if (compteur >= 100) { + 8000540: 79fb ldrb r3, [r7, #7] + 8000542: 2b63 cmp r3, #99 @ 0x63 + 8000544: d901 bls.n 800054a + compteur = 0; + 8000546: 2300 movs r3, #0 + 8000548: 71fb strb r3, [r7, #7] + } + HAL_Delay(500); + 800054a: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800054e: f000 fa8b bl 8000a68 + affiche(compteur); + 8000552: e7ee b.n 8000532 + +08000554 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000554: b580 push {r7, lr} + 8000556: b092 sub sp, #72 @ 0x48 + 8000558: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 800055a: f107 0314 add.w r3, r7, #20 + 800055e: 2234 movs r2, #52 @ 0x34 + 8000560: 2100 movs r1, #0 + 8000562: 4618 mov r0, r3 + 8000564: f001 fd5a bl 800201c + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000568: 463b mov r3, r7 + 800056a: 2200 movs r2, #0 + 800056c: 601a str r2, [r3, #0] + 800056e: 605a str r2, [r3, #4] + 8000570: 609a str r2, [r3, #8] + 8000572: 60da str r2, [r3, #12] + 8000574: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000576: 4b19 ldr r3, [pc, #100] @ (80005dc ) + 8000578: 681b ldr r3, [r3, #0] + 800057a: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 800057e: 4a17 ldr r2, [pc, #92] @ (80005dc ) + 8000580: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000584: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000586: 2302 movs r3, #2 + 8000588: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 800058a: 2301 movs r3, #1 + 800058c: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 800058e: 2310 movs r3, #16 + 8000590: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000592: 2300 movs r3, #0 + 8000594: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000596: f107 0314 add.w r3, r7, #20 + 800059a: 4618 mov r0, r3 + 800059c: f000 fd12 bl 8000fc4 + 80005a0: 4603 mov r3, r0 + 80005a2: 2b00 cmp r3, #0 + 80005a4: d001 beq.n 80005aa + { + Error_Handler(); + 80005a6: f000 f88f bl 80006c8 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80005aa: 230f movs r3, #15 + 80005ac: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 80005ae: 2301 movs r3, #1 + 80005b0: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80005b2: 2300 movs r3, #0 + 80005b4: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80005b6: 2300 movs r3, #0 + 80005b8: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80005ba: 2300 movs r3, #0 + 80005bc: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 80005be: 463b mov r3, r7 + 80005c0: 2100 movs r1, #0 + 80005c2: 4618 mov r0, r3 + 80005c4: f001 f82e bl 8001624 + 80005c8: 4603 mov r3, r0 + 80005ca: 2b00 cmp r3, #0 + 80005cc: d001 beq.n 80005d2 + { + Error_Handler(); + 80005ce: f000 f87b bl 80006c8 + } +} + 80005d2: bf00 nop + 80005d4: 3748 adds r7, #72 @ 0x48 + 80005d6: 46bd mov sp, r7 + 80005d8: bd80 pop {r7, pc} + 80005da: bf00 nop + 80005dc: 40007000 .word 0x40007000 + +080005e0 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 80005e0: b580 push {r7, lr} + 80005e2: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 80005e4: 4b17 ldr r3, [pc, #92] @ (8000644 ) + 80005e6: 4a18 ldr r2, [pc, #96] @ (8000648 ) + 80005e8: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 80005ea: 4b16 ldr r3, [pc, #88] @ (8000644 ) + 80005ec: f44f 7282 mov.w r2, #260 @ 0x104 + 80005f0: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 80005f2: 4b14 ldr r3, [pc, #80] @ (8000644 ) + 80005f4: 2200 movs r2, #0 + 80005f6: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 80005f8: 4b12 ldr r3, [pc, #72] @ (8000644 ) + 80005fa: 2200 movs r2, #0 + 80005fc: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 80005fe: 4b11 ldr r3, [pc, #68] @ (8000644 ) + 8000600: 2200 movs r2, #0 + 8000602: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 8000604: 4b0f ldr r3, [pc, #60] @ (8000644 ) + 8000606: 2200 movs r2, #0 + 8000608: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 800060a: 4b0e ldr r3, [pc, #56] @ (8000644 ) + 800060c: f44f 7200 mov.w r2, #512 @ 0x200 + 8000610: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8000612: 4b0c ldr r3, [pc, #48] @ (8000644 ) + 8000614: 2200 movs r2, #0 + 8000616: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 8000618: 4b0a ldr r3, [pc, #40] @ (8000644 ) + 800061a: 2200 movs r2, #0 + 800061c: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 800061e: 4b09 ldr r3, [pc, #36] @ (8000644 ) + 8000620: 2200 movs r2, #0 + 8000622: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8000624: 4b07 ldr r3, [pc, #28] @ (8000644 ) + 8000626: 2200 movs r2, #0 + 8000628: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 800062a: 4b06 ldr r3, [pc, #24] @ (8000644 ) + 800062c: 220a movs r2, #10 + 800062e: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8000630: 4804 ldr r0, [pc, #16] @ (8000644 ) + 8000632: f001 fa49 bl 8001ac8 + 8000636: 4603 mov r3, r0 + 8000638: 2b00 cmp r3, #0 + 800063a: d001 beq.n 8000640 + { + Error_Handler(); + 800063c: f000 f844 bl 80006c8 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 8000640: bf00 nop + 8000642: bd80 pop {r7, pc} + 8000644: 20000028 .word 0x20000028 + 8000648: 40013000 .word 0x40013000 + +0800064c : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 800064c: b580 push {r7, lr} + 800064e: b088 sub sp, #32 + 8000650: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000652: f107 030c add.w r3, r7, #12 + 8000656: 2200 movs r2, #0 + 8000658: 601a str r2, [r3, #0] + 800065a: 605a str r2, [r3, #4] + 800065c: 609a str r2, [r3, #8] + 800065e: 60da str r2, [r3, #12] + 8000660: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000662: 4b17 ldr r3, [pc, #92] @ (80006c0 ) + 8000664: 69db ldr r3, [r3, #28] + 8000666: 4a16 ldr r2, [pc, #88] @ (80006c0 ) + 8000668: f043 0304 orr.w r3, r3, #4 + 800066c: 61d3 str r3, [r2, #28] + 800066e: 4b14 ldr r3, [pc, #80] @ (80006c0 ) + 8000670: 69db ldr r3, [r3, #28] + 8000672: f003 0304 and.w r3, r3, #4 + 8000676: 60bb str r3, [r7, #8] + 8000678: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800067a: 4b11 ldr r3, [pc, #68] @ (80006c0 ) + 800067c: 69db ldr r3, [r3, #28] + 800067e: 4a10 ldr r2, [pc, #64] @ (80006c0 ) + 8000680: f043 0301 orr.w r3, r3, #1 + 8000684: 61d3 str r3, [r2, #28] + 8000686: 4b0e ldr r3, [pc, #56] @ (80006c0 ) + 8000688: 69db ldr r3, [r3, #28] + 800068a: f003 0301 and.w r3, r3, #1 + 800068e: 607b str r3, [r7, #4] + 8000690: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 8000692: 2200 movs r2, #0 + 8000694: 2101 movs r1, #1 + 8000696: 480b ldr r0, [pc, #44] @ (80006c4 ) + 8000698: f000 fc7c bl 8000f94 + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 800069c: 2301 movs r3, #1 + 800069e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80006a0: 2301 movs r3, #1 + 80006a2: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80006a4: 2300 movs r3, #0 + 80006a6: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80006a8: 2300 movs r3, #0 + 80006aa: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80006ac: f107 030c add.w r3, r7, #12 + 80006b0: 4619 mov r1, r3 + 80006b2: 4804 ldr r0, [pc, #16] @ (80006c4 ) + 80006b4: f000 fade bl 8000c74 + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 80006b8: bf00 nop + 80006ba: 3720 adds r7, #32 + 80006bc: 46bd mov sp, r7 + 80006be: bd80 pop {r7, pc} + 80006c0: 40023800 .word 0x40023800 + 80006c4: 40020800 .word 0x40020800 + +080006c8 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 80006c8: b480 push {r7} + 80006ca: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 80006cc: b672 cpsid i +} + 80006ce: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 80006d0: bf00 nop + 80006d2: e7fd b.n 80006d0 + +080006d4 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80006d4: b480 push {r7} + 80006d6: b085 sub sp, #20 + 80006d8: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 80006da: 4b14 ldr r3, [pc, #80] @ (800072c ) + 80006dc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80006de: 4a13 ldr r2, [pc, #76] @ (800072c ) + 80006e0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 80006e4: 6253 str r3, [r2, #36] @ 0x24 + 80006e6: 4b11 ldr r3, [pc, #68] @ (800072c ) + 80006e8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80006ea: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 80006ee: 60fb str r3, [r7, #12] + 80006f0: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80006f2: 4b0e ldr r3, [pc, #56] @ (800072c ) + 80006f4: 6a1b ldr r3, [r3, #32] + 80006f6: 4a0d ldr r2, [pc, #52] @ (800072c ) + 80006f8: f043 0301 orr.w r3, r3, #1 + 80006fc: 6213 str r3, [r2, #32] + 80006fe: 4b0b ldr r3, [pc, #44] @ (800072c ) + 8000700: 6a1b ldr r3, [r3, #32] + 8000702: f003 0301 and.w r3, r3, #1 + 8000706: 60bb str r3, [r7, #8] + 8000708: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800070a: 4b08 ldr r3, [pc, #32] @ (800072c ) + 800070c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800070e: 4a07 ldr r2, [pc, #28] @ (800072c ) + 8000710: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000714: 6253 str r3, [r2, #36] @ 0x24 + 8000716: 4b05 ldr r3, [pc, #20] @ (800072c ) + 8000718: 6a5b ldr r3, [r3, #36] @ 0x24 + 800071a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800071e: 607b str r3, [r7, #4] + 8000720: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000722: bf00 nop + 8000724: 3714 adds r7, #20 + 8000726: 46bd mov sp, r7 + 8000728: bc80 pop {r7} + 800072a: 4770 bx lr + 800072c: 40023800 .word 0x40023800 + +08000730 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8000730: b580 push {r7, lr} + 8000732: b08a sub sp, #40 @ 0x28 + 8000734: af00 add r7, sp, #0 + 8000736: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000738: f107 0314 add.w r3, r7, #20 + 800073c: 2200 movs r2, #0 + 800073e: 601a str r2, [r3, #0] + 8000740: 605a str r2, [r3, #4] + 8000742: 609a str r2, [r3, #8] + 8000744: 60da str r2, [r3, #12] + 8000746: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 8000748: 687b ldr r3, [r7, #4] + 800074a: 681b ldr r3, [r3, #0] + 800074c: 4a17 ldr r2, [pc, #92] @ (80007ac ) + 800074e: 4293 cmp r3, r2 + 8000750: d127 bne.n 80007a2 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 8000752: 4b17 ldr r3, [pc, #92] @ (80007b0 ) + 8000754: 6a1b ldr r3, [r3, #32] + 8000756: 4a16 ldr r2, [pc, #88] @ (80007b0 ) + 8000758: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 800075c: 6213 str r3, [r2, #32] + 800075e: 4b14 ldr r3, [pc, #80] @ (80007b0 ) + 8000760: 6a1b ldr r3, [r3, #32] + 8000762: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8000766: 613b str r3, [r7, #16] + 8000768: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800076a: 4b11 ldr r3, [pc, #68] @ (80007b0 ) + 800076c: 69db ldr r3, [r3, #28] + 800076e: 4a10 ldr r2, [pc, #64] @ (80007b0 ) + 8000770: f043 0301 orr.w r3, r3, #1 + 8000774: 61d3 str r3, [r2, #28] + 8000776: 4b0e ldr r3, [pc, #56] @ (80007b0 ) + 8000778: 69db ldr r3, [r3, #28] + 800077a: f003 0301 and.w r3, r3, #1 + 800077e: 60fb str r3, [r7, #12] + 8000780: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 8000782: 23e0 movs r3, #224 @ 0xe0 + 8000784: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000786: 2302 movs r3, #2 + 8000788: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800078a: 2300 movs r3, #0 + 800078c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800078e: 2303 movs r3, #3 + 8000790: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8000792: 2305 movs r3, #5 + 8000794: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000796: f107 0314 add.w r3, r7, #20 + 800079a: 4619 mov r1, r3 + 800079c: 4805 ldr r0, [pc, #20] @ (80007b4 ) + 800079e: f000 fa69 bl 8000c74 + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 80007a2: bf00 nop + 80007a4: 3728 adds r7, #40 @ 0x28 + 80007a6: 46bd mov sp, r7 + 80007a8: bd80 pop {r7, pc} + 80007aa: bf00 nop + 80007ac: 40013000 .word 0x40013000 + 80007b0: 40023800 .word 0x40023800 + 80007b4: 40020000 .word 0x40020000 + +080007b8 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 80007b8: b480 push {r7} + 80007ba: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 80007bc: bf00 nop + 80007be: e7fd b.n 80007bc + +080007c0 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 80007c0: b480 push {r7} + 80007c2: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 80007c4: bf00 nop + 80007c6: e7fd b.n 80007c4 + +080007c8 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 80007c8: b480 push {r7} + 80007ca: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 80007cc: bf00 nop + 80007ce: e7fd b.n 80007cc + +080007d0 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 80007d0: b480 push {r7} + 80007d2: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 80007d4: bf00 nop + 80007d6: e7fd b.n 80007d4 + +080007d8 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 80007d8: b480 push {r7} + 80007da: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 80007dc: bf00 nop + 80007de: e7fd b.n 80007dc + +080007e0 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 80007e0: b480 push {r7} + 80007e2: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 80007e4: bf00 nop + 80007e6: 46bd mov sp, r7 + 80007e8: bc80 pop {r7} + 80007ea: 4770 bx lr + +080007ec : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 80007ec: b480 push {r7} + 80007ee: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 80007f0: bf00 nop + 80007f2: 46bd mov sp, r7 + 80007f4: bc80 pop {r7} + 80007f6: 4770 bx lr + +080007f8 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 80007f8: b480 push {r7} + 80007fa: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 80007fc: bf00 nop + 80007fe: 46bd mov sp, r7 + 8000800: bc80 pop {r7} + 8000802: 4770 bx lr + +08000804 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000804: b580 push {r7, lr} + 8000806: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000808: f000 f912 bl 8000a30 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 800080c: bf00 nop + 800080e: bd80 pop {r7, pc} + +08000810 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000810: b480 push {r7} + 8000812: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000814: bf00 nop + 8000816: 46bd mov sp, r7 + 8000818: bc80 pop {r7} + 800081a: 4770 bx lr + +0800081c : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 800081c: f7ff fff8 bl 8000810 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000820: 480b ldr r0, [pc, #44] @ (8000850 ) + ldr r1, =_edata + 8000822: 490c ldr r1, [pc, #48] @ (8000854 ) + ldr r2, =_sidata + 8000824: 4a0c ldr r2, [pc, #48] @ (8000858 ) + movs r3, #0 + 8000826: 2300 movs r3, #0 + b LoopCopyDataInit + 8000828: e002 b.n 8000830 + +0800082a : + +CopyDataInit: + ldr r4, [r2, r3] + 800082a: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 800082c: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 800082e: 3304 adds r3, #4 + +08000830 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000830: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000832: 428c cmp r4, r1 + bcc CopyDataInit + 8000834: d3f9 bcc.n 800082a + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000836: 4a09 ldr r2, [pc, #36] @ (800085c ) + ldr r4, =_ebss + 8000838: 4c09 ldr r4, [pc, #36] @ (8000860 ) + movs r3, #0 + 800083a: 2300 movs r3, #0 + b LoopFillZerobss + 800083c: e001 b.n 8000842 + +0800083e : + +FillZerobss: + str r3, [r2] + 800083e: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000840: 3204 adds r2, #4 + +08000842 : + +LoopFillZerobss: + cmp r2, r4 + 8000842: 42a2 cmp r2, r4 + bcc FillZerobss + 8000844: d3fb bcc.n 800083e + +/* Call static constructors */ + bl __libc_init_array + 8000846: f001 fbf1 bl 800202c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800084a: f7ff fe61 bl 8000510
+ bx lr + 800084e: 4770 bx lr + ldr r0, =_sdata + 8000850: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000854: 2000000c .word 0x2000000c + ldr r2, =_sidata + 8000858: 080020c8 .word 0x080020c8 + ldr r2, =_sbss + 800085c: 2000000c .word 0x2000000c + ldr r4, =_ebss + 8000860: 20000084 .word 0x20000084 + +08000864 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000864: e7fe b.n 8000864 + +08000866 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 8000866: b580 push {r7, lr} + 8000868: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 800086a: 2107 movs r1, #7 + 800086c: 200b movs r0, #11 + 800086e: f000 f85d bl 800092c + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 8000872: 2100 movs r1, #0 + 8000874: 2009 movs r0, #9 + 8000876: f000 f859 bl 800092c + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 800087a: f000 f809 bl 8000890 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 800087e: f000 f80f bl 80008a0 + MAX7219_Clear(); // clear all digits + 8000882: f000 f827 bl 80008d4 + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 8000886: 200f movs r0, #15 + 8000888: f000 f812 bl 80008b0 +} + 800088c: bf00 nop + 800088e: bd80 pop {r7, pc} + +08000890 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000890: b580 push {r7, lr} + 8000892: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000894: 2101 movs r1, #1 + 8000896: 200c movs r0, #12 + 8000898: f000 f848 bl 800092c +} + 800089c: bf00 nop + 800089e: bd80 pop {r7, pc} + +080008a0 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 80008a0: b580 push {r7, lr} + 80008a2: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 80008a4: 2100 movs r1, #0 + 80008a6: 200f movs r0, #15 + 80008a8: f000 f840 bl 800092c +} + 80008ac: bf00 nop + 80008ae: bd80 pop {r7, pc} + +080008b0 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 80008b0: b580 push {r7, lr} + 80008b2: b082 sub sp, #8 + 80008b4: af00 add r7, sp, #0 + 80008b6: 4603 mov r3, r0 + 80008b8: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 80008ba: 79fb ldrb r3, [r7, #7] + 80008bc: f003 030f and.w r3, r3, #15 + 80008c0: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 80008c2: 79fb ldrb r3, [r7, #7] + 80008c4: 4619 mov r1, r3 + 80008c6: 200a movs r0, #10 + 80008c8: f000 f830 bl 800092c +} + 80008cc: bf00 nop + 80008ce: 3708 adds r7, #8 + 80008d0: 46bd mov sp, r7 + 80008d2: bd80 pop {r7, pc} + +080008d4 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 80008d4: b580 push {r7, lr} + 80008d6: b082 sub sp, #8 + 80008d8: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 80008da: 2300 movs r3, #0 + 80008dc: 71fb strb r3, [r7, #7] + 80008de: e007 b.n 80008f0 + MAX7219_Write(i, 0x00); // turn all segments off + 80008e0: 79fb ldrb r3, [r7, #7] + 80008e2: 2100 movs r1, #0 + 80008e4: 4618 mov r0, r3 + 80008e6: f000 f821 bl 800092c + for (i=0; i < 8; i++) + 80008ea: 79fb ldrb r3, [r7, #7] + 80008ec: 3301 adds r3, #1 + 80008ee: 71fb strb r3, [r7, #7] + 80008f0: 79fb ldrb r3, [r7, #7] + 80008f2: 2b07 cmp r3, #7 + 80008f4: d9f4 bls.n 80008e0 +} + 80008f6: bf00 nop + 80008f8: bf00 nop + 80008fa: 3708 adds r7, #8 + 80008fc: 46bd mov sp, r7 + 80008fe: bd80 pop {r7, pc} + +08000900 : +* character = character to display (0-9, A-Z) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayChar(char digit, char character) +{ + 8000900: b580 push {r7, lr} + 8000902: b082 sub sp, #8 + 8000904: af00 add r7, sp, #0 + 8000906: 4603 mov r3, r0 + 8000908: 460a mov r2, r1 + 800090a: 71fb strb r3, [r7, #7] + 800090c: 4613 mov r3, r2 + 800090e: 71bb strb r3, [r7, #6] + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]); + 8000910: 79bb ldrb r3, [r7, #6] + 8000912: 4a05 ldr r2, [pc, #20] @ (8000928 ) + 8000914: 5cd2 ldrb r2, [r2, r3] + 8000916: 79fb ldrb r3, [r7, #7] + 8000918: 4611 mov r1, r2 + 800091a: 4618 mov r0, r3 + 800091c: f000 f806 bl 800092c +} + 8000920: bf00 nop + 8000922: 3708 adds r7, #8 + 8000924: 46bd mov sp, r7 + 8000926: bd80 pop {r7, pc} + 8000928: 080020a8 .word 0x080020a8 + +0800092c : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 800092c: b580 push {r7, lr} + 800092e: b082 sub sp, #8 + 8000930: af00 add r7, sp, #0 + 8000932: 4603 mov r3, r0 + 8000934: 460a mov r2, r1 + 8000936: 71fb strb r3, [r7, #7] + 8000938: 4613 mov r3, r2 + 800093a: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 800093c: 4b09 ldr r3, [pc, #36] @ (8000964 ) + 800093e: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000942: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8000944: 79fb ldrb r3, [r7, #7] + 8000946: 4618 mov r0, r3 + 8000948: f000 f80e bl 8000968 + MAX7219_SendByte(dataout); // write data to MAX7219 + 800094c: 79bb ldrb r3, [r7, #6] + 800094e: 4618 mov r0, r3 + 8000950: f000 f80a bl 8000968 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 8000954: 4b03 ldr r3, [pc, #12] @ (8000964 ) + 8000956: 2201 movs r2, #1 + 8000958: 619a str r2, [r3, #24] + } + 800095a: bf00 nop + 800095c: 3708 adds r7, #8 + 800095e: 46bd mov sp, r7 + 8000960: bd80 pop {r7, pc} + 8000962: bf00 nop + 8000964: 40020800 .word 0x40020800 + +08000968 : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000968: b580 push {r7, lr} + 800096a: b082 sub sp, #8 + 800096c: af00 add r7, sp, #0 + 800096e: 4603 mov r3, r0 + 8000970: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 8000972: 1df9 adds r1, r7, #7 + 8000974: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000978: 2201 movs r2, #1 + 800097a: 4803 ldr r0, [pc, #12] @ (8000988 ) + 800097c: f001 f92d bl 8001bda + +} + 8000980: bf00 nop + 8000982: 3708 adds r7, #8 + 8000984: 46bd mov sp, r7 + 8000986: bd80 pop {r7, pc} + 8000988: 20000028 .word 0x20000028 + +0800098c : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 800098c: b580 push {r7, lr} + 800098e: b082 sub sp, #8 + 8000990: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000992: 2300 movs r3, #0 + 8000994: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000996: 2003 movs r0, #3 + 8000998: f000 f938 bl 8000c0c + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 800099c: 200f movs r0, #15 + 800099e: f000 f80d bl 80009bc + 80009a2: 4603 mov r3, r0 + 80009a4: 2b00 cmp r3, #0 + 80009a6: d002 beq.n 80009ae + { + status = HAL_ERROR; + 80009a8: 2301 movs r3, #1 + 80009aa: 71fb strb r3, [r7, #7] + 80009ac: e001 b.n 80009b2 + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 80009ae: f7ff fe91 bl 80006d4 + } + + /* Return function status */ + return status; + 80009b2: 79fb ldrb r3, [r7, #7] +} + 80009b4: 4618 mov r0, r3 + 80009b6: 3708 adds r7, #8 + 80009b8: 46bd mov sp, r7 + 80009ba: bd80 pop {r7, pc} + +080009bc : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 80009bc: b580 push {r7, lr} + 80009be: b084 sub sp, #16 + 80009c0: af00 add r7, sp, #0 + 80009c2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80009c4: 2300 movs r3, #0 + 80009c6: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 80009c8: 4b16 ldr r3, [pc, #88] @ (8000a24 ) + 80009ca: 681b ldr r3, [r3, #0] + 80009cc: 2b00 cmp r3, #0 + 80009ce: d022 beq.n 8000a16 + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 80009d0: 4b15 ldr r3, [pc, #84] @ (8000a28 ) + 80009d2: 681a ldr r2, [r3, #0] + 80009d4: 4b13 ldr r3, [pc, #76] @ (8000a24 ) + 80009d6: 681b ldr r3, [r3, #0] + 80009d8: f44f 717a mov.w r1, #1000 @ 0x3e8 + 80009dc: fbb1 f3f3 udiv r3, r1, r3 + 80009e0: fbb2 f3f3 udiv r3, r2, r3 + 80009e4: 4618 mov r0, r3 + 80009e6: f000 f938 bl 8000c5a + 80009ea: 4603 mov r3, r0 + 80009ec: 2b00 cmp r3, #0 + 80009ee: d10f bne.n 8000a10 + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 80009f0: 687b ldr r3, [r7, #4] + 80009f2: 2b0f cmp r3, #15 + 80009f4: d809 bhi.n 8000a0a + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 80009f6: 2200 movs r2, #0 + 80009f8: 6879 ldr r1, [r7, #4] + 80009fa: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80009fe: f000 f910 bl 8000c22 + uwTickPrio = TickPriority; + 8000a02: 4a0a ldr r2, [pc, #40] @ (8000a2c ) + 8000a04: 687b ldr r3, [r7, #4] + 8000a06: 6013 str r3, [r2, #0] + 8000a08: e007 b.n 8000a1a + } + else + { + status = HAL_ERROR; + 8000a0a: 2301 movs r3, #1 + 8000a0c: 73fb strb r3, [r7, #15] + 8000a0e: e004 b.n 8000a1a + } + } + else + { + status = HAL_ERROR; + 8000a10: 2301 movs r3, #1 + 8000a12: 73fb strb r3, [r7, #15] + 8000a14: e001 b.n 8000a1a + } + } + else + { + status = HAL_ERROR; + 8000a16: 2301 movs r3, #1 + 8000a18: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8000a1a: 7bfb ldrb r3, [r7, #15] +} + 8000a1c: 4618 mov r0, r3 + 8000a1e: 3710 adds r7, #16 + 8000a20: 46bd mov sp, r7 + 8000a22: bd80 pop {r7, pc} + 8000a24: 20000008 .word 0x20000008 + 8000a28: 20000000 .word 0x20000000 + 8000a2c: 20000004 .word 0x20000004 + +08000a30 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000a30: b480 push {r7} + 8000a32: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000a34: 4b05 ldr r3, [pc, #20] @ (8000a4c ) + 8000a36: 681a ldr r2, [r3, #0] + 8000a38: 4b05 ldr r3, [pc, #20] @ (8000a50 ) + 8000a3a: 681b ldr r3, [r3, #0] + 8000a3c: 4413 add r3, r2 + 8000a3e: 4a03 ldr r2, [pc, #12] @ (8000a4c ) + 8000a40: 6013 str r3, [r2, #0] +} + 8000a42: bf00 nop + 8000a44: 46bd mov sp, r7 + 8000a46: bc80 pop {r7} + 8000a48: 4770 bx lr + 8000a4a: bf00 nop + 8000a4c: 20000080 .word 0x20000080 + 8000a50: 20000008 .word 0x20000008 + +08000a54 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000a54: b480 push {r7} + 8000a56: af00 add r7, sp, #0 + return uwTick; + 8000a58: 4b02 ldr r3, [pc, #8] @ (8000a64 ) + 8000a5a: 681b ldr r3, [r3, #0] +} + 8000a5c: 4618 mov r0, r3 + 8000a5e: 46bd mov sp, r7 + 8000a60: bc80 pop {r7} + 8000a62: 4770 bx lr + 8000a64: 20000080 .word 0x20000080 + +08000a68 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000a68: b580 push {r7, lr} + 8000a6a: b084 sub sp, #16 + 8000a6c: af00 add r7, sp, #0 + 8000a6e: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8000a70: f7ff fff0 bl 8000a54 + 8000a74: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8000a76: 687b ldr r3, [r7, #4] + 8000a78: 60fb str r3, [r7, #12] + + /* Add a period to guaranty minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000a7a: 68fb ldr r3, [r7, #12] + 8000a7c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8000a80: d004 beq.n 8000a8c + { + wait += (uint32_t)(uwTickFreq); + 8000a82: 4b09 ldr r3, [pc, #36] @ (8000aa8 ) + 8000a84: 681b ldr r3, [r3, #0] + 8000a86: 68fa ldr r2, [r7, #12] + 8000a88: 4413 add r3, r2 + 8000a8a: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 8000a8c: bf00 nop + 8000a8e: f7ff ffe1 bl 8000a54 + 8000a92: 4602 mov r2, r0 + 8000a94: 68bb ldr r3, [r7, #8] + 8000a96: 1ad3 subs r3, r2, r3 + 8000a98: 68fa ldr r2, [r7, #12] + 8000a9a: 429a cmp r2, r3 + 8000a9c: d8f7 bhi.n 8000a8e + { + } +} + 8000a9e: bf00 nop + 8000aa0: bf00 nop + 8000aa2: 3710 adds r7, #16 + 8000aa4: 46bd mov sp, r7 + 8000aa6: bd80 pop {r7, pc} + 8000aa8: 20000008 .word 0x20000008 + +08000aac <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000aac: b480 push {r7} + 8000aae: b085 sub sp, #20 + 8000ab0: af00 add r7, sp, #0 + 8000ab2: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000ab4: 687b ldr r3, [r7, #4] + 8000ab6: f003 0307 and.w r3, r3, #7 + 8000aba: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000abc: 4b0c ldr r3, [pc, #48] @ (8000af0 <__NVIC_SetPriorityGrouping+0x44>) + 8000abe: 68db ldr r3, [r3, #12] + 8000ac0: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000ac2: 68ba ldr r2, [r7, #8] + 8000ac4: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000ac8: 4013 ands r3, r2 + 8000aca: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000acc: 68fb ldr r3, [r7, #12] + 8000ace: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000ad0: 68bb ldr r3, [r7, #8] + 8000ad2: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000ad4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000ad8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000adc: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000ade: 4a04 ldr r2, [pc, #16] @ (8000af0 <__NVIC_SetPriorityGrouping+0x44>) + 8000ae0: 68bb ldr r3, [r7, #8] + 8000ae2: 60d3 str r3, [r2, #12] +} + 8000ae4: bf00 nop + 8000ae6: 3714 adds r7, #20 + 8000ae8: 46bd mov sp, r7 + 8000aea: bc80 pop {r7} + 8000aec: 4770 bx lr + 8000aee: bf00 nop + 8000af0: e000ed00 .word 0xe000ed00 + +08000af4 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000af4: b480 push {r7} + 8000af6: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000af8: 4b04 ldr r3, [pc, #16] @ (8000b0c <__NVIC_GetPriorityGrouping+0x18>) + 8000afa: 68db ldr r3, [r3, #12] + 8000afc: 0a1b lsrs r3, r3, #8 + 8000afe: f003 0307 and.w r3, r3, #7 +} + 8000b02: 4618 mov r0, r3 + 8000b04: 46bd mov sp, r7 + 8000b06: bc80 pop {r7} + 8000b08: 4770 bx lr + 8000b0a: bf00 nop + 8000b0c: e000ed00 .word 0xe000ed00 + +08000b10 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000b10: b480 push {r7} + 8000b12: b083 sub sp, #12 + 8000b14: af00 add r7, sp, #0 + 8000b16: 4603 mov r3, r0 + 8000b18: 6039 str r1, [r7, #0] + 8000b1a: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000b1c: f997 3007 ldrsb.w r3, [r7, #7] + 8000b20: 2b00 cmp r3, #0 + 8000b22: db0a blt.n 8000b3a <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000b24: 683b ldr r3, [r7, #0] + 8000b26: b2da uxtb r2, r3 + 8000b28: 490c ldr r1, [pc, #48] @ (8000b5c <__NVIC_SetPriority+0x4c>) + 8000b2a: f997 3007 ldrsb.w r3, [r7, #7] + 8000b2e: 0112 lsls r2, r2, #4 + 8000b30: b2d2 uxtb r2, r2 + 8000b32: 440b add r3, r1 + 8000b34: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000b38: e00a b.n 8000b50 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000b3a: 683b ldr r3, [r7, #0] + 8000b3c: b2da uxtb r2, r3 + 8000b3e: 4908 ldr r1, [pc, #32] @ (8000b60 <__NVIC_SetPriority+0x50>) + 8000b40: 79fb ldrb r3, [r7, #7] + 8000b42: f003 030f and.w r3, r3, #15 + 8000b46: 3b04 subs r3, #4 + 8000b48: 0112 lsls r2, r2, #4 + 8000b4a: b2d2 uxtb r2, r2 + 8000b4c: 440b add r3, r1 + 8000b4e: 761a strb r2, [r3, #24] +} + 8000b50: bf00 nop + 8000b52: 370c adds r7, #12 + 8000b54: 46bd mov sp, r7 + 8000b56: bc80 pop {r7} + 8000b58: 4770 bx lr + 8000b5a: bf00 nop + 8000b5c: e000e100 .word 0xe000e100 + 8000b60: e000ed00 .word 0xe000ed00 + +08000b64 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000b64: b480 push {r7} + 8000b66: b089 sub sp, #36 @ 0x24 + 8000b68: af00 add r7, sp, #0 + 8000b6a: 60f8 str r0, [r7, #12] + 8000b6c: 60b9 str r1, [r7, #8] + 8000b6e: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000b70: 68fb ldr r3, [r7, #12] + 8000b72: f003 0307 and.w r3, r3, #7 + 8000b76: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000b78: 69fb ldr r3, [r7, #28] + 8000b7a: f1c3 0307 rsb r3, r3, #7 + 8000b7e: 2b04 cmp r3, #4 + 8000b80: bf28 it cs + 8000b82: 2304 movcs r3, #4 + 8000b84: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000b86: 69fb ldr r3, [r7, #28] + 8000b88: 3304 adds r3, #4 + 8000b8a: 2b06 cmp r3, #6 + 8000b8c: d902 bls.n 8000b94 + 8000b8e: 69fb ldr r3, [r7, #28] + 8000b90: 3b03 subs r3, #3 + 8000b92: e000 b.n 8000b96 + 8000b94: 2300 movs r3, #0 + 8000b96: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000b98: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000b9c: 69bb ldr r3, [r7, #24] + 8000b9e: fa02 f303 lsl.w r3, r2, r3 + 8000ba2: 43da mvns r2, r3 + 8000ba4: 68bb ldr r3, [r7, #8] + 8000ba6: 401a ands r2, r3 + 8000ba8: 697b ldr r3, [r7, #20] + 8000baa: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000bac: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000bb0: 697b ldr r3, [r7, #20] + 8000bb2: fa01 f303 lsl.w r3, r1, r3 + 8000bb6: 43d9 mvns r1, r3 + 8000bb8: 687b ldr r3, [r7, #4] + 8000bba: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000bbc: 4313 orrs r3, r2 + ); +} + 8000bbe: 4618 mov r0, r3 + 8000bc0: 3724 adds r7, #36 @ 0x24 + 8000bc2: 46bd mov sp, r7 + 8000bc4: bc80 pop {r7} + 8000bc6: 4770 bx lr + +08000bc8 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000bc8: b580 push {r7, lr} + 8000bca: b082 sub sp, #8 + 8000bcc: af00 add r7, sp, #0 + 8000bce: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000bd0: 687b ldr r3, [r7, #4] + 8000bd2: 3b01 subs r3, #1 + 8000bd4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000bd8: d301 bcc.n 8000bde + { + return (1UL); /* Reload value impossible */ + 8000bda: 2301 movs r3, #1 + 8000bdc: e00f b.n 8000bfe + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000bde: 4a0a ldr r2, [pc, #40] @ (8000c08 ) + 8000be0: 687b ldr r3, [r7, #4] + 8000be2: 3b01 subs r3, #1 + 8000be4: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000be6: 210f movs r1, #15 + 8000be8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000bec: f7ff ff90 bl 8000b10 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000bf0: 4b05 ldr r3, [pc, #20] @ (8000c08 ) + 8000bf2: 2200 movs r2, #0 + 8000bf4: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000bf6: 4b04 ldr r3, [pc, #16] @ (8000c08 ) + 8000bf8: 2207 movs r2, #7 + 8000bfa: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000bfc: 2300 movs r3, #0 +} + 8000bfe: 4618 mov r0, r3 + 8000c00: 3708 adds r7, #8 + 8000c02: 46bd mov sp, r7 + 8000c04: bd80 pop {r7, pc} + 8000c06: bf00 nop + 8000c08: e000e010 .word 0xe000e010 + +08000c0c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000c0c: b580 push {r7, lr} + 8000c0e: b082 sub sp, #8 + 8000c10: af00 add r7, sp, #0 + 8000c12: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8000c14: 6878 ldr r0, [r7, #4] + 8000c16: f7ff ff49 bl 8000aac <__NVIC_SetPriorityGrouping> +} + 8000c1a: bf00 nop + 8000c1c: 3708 adds r7, #8 + 8000c1e: 46bd mov sp, r7 + 8000c20: bd80 pop {r7, pc} + +08000c22 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000c22: b580 push {r7, lr} + 8000c24: b086 sub sp, #24 + 8000c26: af00 add r7, sp, #0 + 8000c28: 4603 mov r3, r0 + 8000c2a: 60b9 str r1, [r7, #8] + 8000c2c: 607a str r2, [r7, #4] + 8000c2e: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8000c30: 2300 movs r3, #0 + 8000c32: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8000c34: f7ff ff5e bl 8000af4 <__NVIC_GetPriorityGrouping> + 8000c38: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8000c3a: 687a ldr r2, [r7, #4] + 8000c3c: 68b9 ldr r1, [r7, #8] + 8000c3e: 6978 ldr r0, [r7, #20] + 8000c40: f7ff ff90 bl 8000b64 + 8000c44: 4602 mov r2, r0 + 8000c46: f997 300f ldrsb.w r3, [r7, #15] + 8000c4a: 4611 mov r1, r2 + 8000c4c: 4618 mov r0, r3 + 8000c4e: f7ff ff5f bl 8000b10 <__NVIC_SetPriority> +} + 8000c52: bf00 nop + 8000c54: 3718 adds r7, #24 + 8000c56: 46bd mov sp, r7 + 8000c58: bd80 pop {r7, pc} + +08000c5a : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000c5a: b580 push {r7, lr} + 8000c5c: b082 sub sp, #8 + 8000c5e: af00 add r7, sp, #0 + 8000c60: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000c62: 6878 ldr r0, [r7, #4] + 8000c64: f7ff ffb0 bl 8000bc8 + 8000c68: 4603 mov r3, r0 +} + 8000c6a: 4618 mov r0, r3 + 8000c6c: 3708 adds r7, #8 + 8000c6e: 46bd mov sp, r7 + 8000c70: bd80 pop {r7, pc} + ... + +08000c74 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000c74: b480 push {r7} + 8000c76: b087 sub sp, #28 + 8000c78: af00 add r7, sp, #0 + 8000c7a: 6078 str r0, [r7, #4] + 8000c7c: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8000c7e: 2300 movs r3, #0 + 8000c80: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8000c82: 2300 movs r3, #0 + 8000c84: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 8000c86: 2300 movs r3, #0 + 8000c88: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8000c8a: e160 b.n 8000f4e + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8000c8c: 683b ldr r3, [r7, #0] + 8000c8e: 681a ldr r2, [r3, #0] + 8000c90: 2101 movs r1, #1 + 8000c92: 697b ldr r3, [r7, #20] + 8000c94: fa01 f303 lsl.w r3, r1, r3 + 8000c98: 4013 ands r3, r2 + 8000c9a: 60fb str r3, [r7, #12] + + if (iocurrent) + 8000c9c: 68fb ldr r3, [r7, #12] + 8000c9e: 2b00 cmp r3, #0 + 8000ca0: f000 8152 beq.w 8000f48 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000ca4: 683b ldr r3, [r7, #0] + 8000ca6: 685b ldr r3, [r3, #4] + 8000ca8: f003 0303 and.w r3, r3, #3 + 8000cac: 2b01 cmp r3, #1 + 8000cae: d005 beq.n 8000cbc + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8000cb0: 683b ldr r3, [r7, #0] + 8000cb2: 685b ldr r3, [r3, #4] + 8000cb4: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000cb8: 2b02 cmp r3, #2 + 8000cba: d130 bne.n 8000d1e + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8000cbc: 687b ldr r3, [r7, #4] + 8000cbe: 689b ldr r3, [r3, #8] + 8000cc0: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8000cc2: 697b ldr r3, [r7, #20] + 8000cc4: 005b lsls r3, r3, #1 + 8000cc6: 2203 movs r2, #3 + 8000cc8: fa02 f303 lsl.w r3, r2, r3 + 8000ccc: 43db mvns r3, r3 + 8000cce: 693a ldr r2, [r7, #16] + 8000cd0: 4013 ands r3, r2 + 8000cd2: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8000cd4: 683b ldr r3, [r7, #0] + 8000cd6: 68da ldr r2, [r3, #12] + 8000cd8: 697b ldr r3, [r7, #20] + 8000cda: 005b lsls r3, r3, #1 + 8000cdc: fa02 f303 lsl.w r3, r2, r3 + 8000ce0: 693a ldr r2, [r7, #16] + 8000ce2: 4313 orrs r3, r2 + 8000ce4: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8000ce6: 687b ldr r3, [r7, #4] + 8000ce8: 693a ldr r2, [r7, #16] + 8000cea: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8000cec: 687b ldr r3, [r7, #4] + 8000cee: 685b ldr r3, [r3, #4] + 8000cf0: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 8000cf2: 2201 movs r2, #1 + 8000cf4: 697b ldr r3, [r7, #20] + 8000cf6: fa02 f303 lsl.w r3, r2, r3 + 8000cfa: 43db mvns r3, r3 + 8000cfc: 693a ldr r2, [r7, #16] + 8000cfe: 4013 ands r3, r2 + 8000d00: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8000d02: 683b ldr r3, [r7, #0] + 8000d04: 685b ldr r3, [r3, #4] + 8000d06: 091b lsrs r3, r3, #4 + 8000d08: f003 0201 and.w r2, r3, #1 + 8000d0c: 697b ldr r3, [r7, #20] + 8000d0e: fa02 f303 lsl.w r3, r2, r3 + 8000d12: 693a ldr r2, [r7, #16] + 8000d14: 4313 orrs r3, r2 + 8000d16: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8000d18: 687b ldr r3, [r7, #4] + 8000d1a: 693a ldr r2, [r7, #16] + 8000d1c: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8000d1e: 683b ldr r3, [r7, #0] + 8000d20: 685b ldr r3, [r3, #4] + 8000d22: f003 0303 and.w r3, r3, #3 + 8000d26: 2b03 cmp r3, #3 + 8000d28: d017 beq.n 8000d5a + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8000d2a: 687b ldr r3, [r7, #4] + 8000d2c: 68db ldr r3, [r3, #12] + 8000d2e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 8000d30: 697b ldr r3, [r7, #20] + 8000d32: 005b lsls r3, r3, #1 + 8000d34: 2203 movs r2, #3 + 8000d36: fa02 f303 lsl.w r3, r2, r3 + 8000d3a: 43db mvns r3, r3 + 8000d3c: 693a ldr r2, [r7, #16] + 8000d3e: 4013 ands r3, r2 + 8000d40: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 8000d42: 683b ldr r3, [r7, #0] + 8000d44: 689a ldr r2, [r3, #8] + 8000d46: 697b ldr r3, [r7, #20] + 8000d48: 005b lsls r3, r3, #1 + 8000d4a: fa02 f303 lsl.w r3, r2, r3 + 8000d4e: 693a ldr r2, [r7, #16] + 8000d50: 4313 orrs r3, r2 + 8000d52: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8000d54: 687b ldr r3, [r7, #4] + 8000d56: 693a ldr r2, [r7, #16] + 8000d58: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8000d5a: 683b ldr r3, [r7, #0] + 8000d5c: 685b ldr r3, [r3, #4] + 8000d5e: f003 0303 and.w r3, r3, #3 + 8000d62: 2b02 cmp r3, #2 + 8000d64: d123 bne.n 8000dae + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 8000d66: 697b ldr r3, [r7, #20] + 8000d68: 08da lsrs r2, r3, #3 + 8000d6a: 687b ldr r3, [r7, #4] + 8000d6c: 3208 adds r2, #8 + 8000d6e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8000d72: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 8000d74: 697b ldr r3, [r7, #20] + 8000d76: f003 0307 and.w r3, r3, #7 + 8000d7a: 009b lsls r3, r3, #2 + 8000d7c: 220f movs r2, #15 + 8000d7e: fa02 f303 lsl.w r3, r2, r3 + 8000d82: 43db mvns r3, r3 + 8000d84: 693a ldr r2, [r7, #16] + 8000d86: 4013 ands r3, r2 + 8000d88: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8000d8a: 683b ldr r3, [r7, #0] + 8000d8c: 691a ldr r2, [r3, #16] + 8000d8e: 697b ldr r3, [r7, #20] + 8000d90: f003 0307 and.w r3, r3, #7 + 8000d94: 009b lsls r3, r3, #2 + 8000d96: fa02 f303 lsl.w r3, r2, r3 + 8000d9a: 693a ldr r2, [r7, #16] + 8000d9c: 4313 orrs r3, r2 + 8000d9e: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 8000da0: 697b ldr r3, [r7, #20] + 8000da2: 08da lsrs r2, r3, #3 + 8000da4: 687b ldr r3, [r7, #4] + 8000da6: 3208 adds r2, #8 + 8000da8: 6939 ldr r1, [r7, #16] + 8000daa: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8000dae: 687b ldr r3, [r7, #4] + 8000db0: 681b ldr r3, [r3, #0] + 8000db2: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8000db4: 697b ldr r3, [r7, #20] + 8000db6: 005b lsls r3, r3, #1 + 8000db8: 2203 movs r2, #3 + 8000dba: fa02 f303 lsl.w r3, r2, r3 + 8000dbe: 43db mvns r3, r3 + 8000dc0: 693a ldr r2, [r7, #16] + 8000dc2: 4013 ands r3, r2 + 8000dc4: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8000dc6: 683b ldr r3, [r7, #0] + 8000dc8: 685b ldr r3, [r3, #4] + 8000dca: f003 0203 and.w r2, r3, #3 + 8000dce: 697b ldr r3, [r7, #20] + 8000dd0: 005b lsls r3, r3, #1 + 8000dd2: fa02 f303 lsl.w r3, r2, r3 + 8000dd6: 693a ldr r2, [r7, #16] + 8000dd8: 4313 orrs r3, r2 + 8000dda: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8000ddc: 687b ldr r3, [r7, #4] + 8000dde: 693a ldr r2, [r7, #16] + 8000de0: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8000de2: 683b ldr r3, [r7, #0] + 8000de4: 685b ldr r3, [r3, #4] + 8000de6: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8000dea: 2b00 cmp r3, #0 + 8000dec: f000 80ac beq.w 8000f48 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000df0: 4b5e ldr r3, [pc, #376] @ (8000f6c ) + 8000df2: 6a1b ldr r3, [r3, #32] + 8000df4: 4a5d ldr r2, [pc, #372] @ (8000f6c ) + 8000df6: f043 0301 orr.w r3, r3, #1 + 8000dfa: 6213 str r3, [r2, #32] + 8000dfc: 4b5b ldr r3, [pc, #364] @ (8000f6c ) + 8000dfe: 6a1b ldr r3, [r3, #32] + 8000e00: f003 0301 and.w r3, r3, #1 + 8000e04: 60bb str r3, [r7, #8] + 8000e06: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8000e08: 4a59 ldr r2, [pc, #356] @ (8000f70 ) + 8000e0a: 697b ldr r3, [r7, #20] + 8000e0c: 089b lsrs r3, r3, #2 + 8000e0e: 3302 adds r3, #2 + 8000e10: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8000e14: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 8000e16: 697b ldr r3, [r7, #20] + 8000e18: f003 0303 and.w r3, r3, #3 + 8000e1c: 009b lsls r3, r3, #2 + 8000e1e: 220f movs r2, #15 + 8000e20: fa02 f303 lsl.w r3, r2, r3 + 8000e24: 43db mvns r3, r3 + 8000e26: 693a ldr r2, [r7, #16] + 8000e28: 4013 ands r3, r2 + 8000e2a: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 8000e2c: 687b ldr r3, [r7, #4] + 8000e2e: 4a51 ldr r2, [pc, #324] @ (8000f74 ) + 8000e30: 4293 cmp r3, r2 + 8000e32: d025 beq.n 8000e80 + 8000e34: 687b ldr r3, [r7, #4] + 8000e36: 4a50 ldr r2, [pc, #320] @ (8000f78 ) + 8000e38: 4293 cmp r3, r2 + 8000e3a: d01f beq.n 8000e7c + 8000e3c: 687b ldr r3, [r7, #4] + 8000e3e: 4a4f ldr r2, [pc, #316] @ (8000f7c ) + 8000e40: 4293 cmp r3, r2 + 8000e42: d019 beq.n 8000e78 + 8000e44: 687b ldr r3, [r7, #4] + 8000e46: 4a4e ldr r2, [pc, #312] @ (8000f80 ) + 8000e48: 4293 cmp r3, r2 + 8000e4a: d013 beq.n 8000e74 + 8000e4c: 687b ldr r3, [r7, #4] + 8000e4e: 4a4d ldr r2, [pc, #308] @ (8000f84 ) + 8000e50: 4293 cmp r3, r2 + 8000e52: d00d beq.n 8000e70 + 8000e54: 687b ldr r3, [r7, #4] + 8000e56: 4a4c ldr r2, [pc, #304] @ (8000f88 ) + 8000e58: 4293 cmp r3, r2 + 8000e5a: d007 beq.n 8000e6c + 8000e5c: 687b ldr r3, [r7, #4] + 8000e5e: 4a4b ldr r2, [pc, #300] @ (8000f8c ) + 8000e60: 4293 cmp r3, r2 + 8000e62: d101 bne.n 8000e68 + 8000e64: 2306 movs r3, #6 + 8000e66: e00c b.n 8000e82 + 8000e68: 2307 movs r3, #7 + 8000e6a: e00a b.n 8000e82 + 8000e6c: 2305 movs r3, #5 + 8000e6e: e008 b.n 8000e82 + 8000e70: 2304 movs r3, #4 + 8000e72: e006 b.n 8000e82 + 8000e74: 2303 movs r3, #3 + 8000e76: e004 b.n 8000e82 + 8000e78: 2302 movs r3, #2 + 8000e7a: e002 b.n 8000e82 + 8000e7c: 2301 movs r3, #1 + 8000e7e: e000 b.n 8000e82 + 8000e80: 2300 movs r3, #0 + 8000e82: 697a ldr r2, [r7, #20] + 8000e84: f002 0203 and.w r2, r2, #3 + 8000e88: 0092 lsls r2, r2, #2 + 8000e8a: 4093 lsls r3, r2 + 8000e8c: 693a ldr r2, [r7, #16] + 8000e8e: 4313 orrs r3, r2 + 8000e90: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 8000e92: 4937 ldr r1, [pc, #220] @ (8000f70 ) + 8000e94: 697b ldr r3, [r7, #20] + 8000e96: 089b lsrs r3, r3, #2 + 8000e98: 3302 adds r3, #2 + 8000e9a: 693a ldr r2, [r7, #16] + 8000e9c: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8000ea0: 4b3b ldr r3, [pc, #236] @ (8000f90 ) + 8000ea2: 689b ldr r3, [r3, #8] + 8000ea4: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000ea6: 68fb ldr r3, [r7, #12] + 8000ea8: 43db mvns r3, r3 + 8000eaa: 693a ldr r2, [r7, #16] + 8000eac: 4013 ands r3, r2 + 8000eae: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8000eb0: 683b ldr r3, [r7, #0] + 8000eb2: 685b ldr r3, [r3, #4] + 8000eb4: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8000eb8: 2b00 cmp r3, #0 + 8000eba: d003 beq.n 8000ec4 + { + SET_BIT(temp, iocurrent); + 8000ebc: 693a ldr r2, [r7, #16] + 8000ebe: 68fb ldr r3, [r7, #12] + 8000ec0: 4313 orrs r3, r2 + 8000ec2: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 8000ec4: 4a32 ldr r2, [pc, #200] @ (8000f90 ) + 8000ec6: 693b ldr r3, [r7, #16] + 8000ec8: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8000eca: 4b31 ldr r3, [pc, #196] @ (8000f90 ) + 8000ecc: 68db ldr r3, [r3, #12] + 8000ece: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000ed0: 68fb ldr r3, [r7, #12] + 8000ed2: 43db mvns r3, r3 + 8000ed4: 693a ldr r2, [r7, #16] + 8000ed6: 4013 ands r3, r2 + 8000ed8: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8000eda: 683b ldr r3, [r7, #0] + 8000edc: 685b ldr r3, [r3, #4] + 8000ede: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8000ee2: 2b00 cmp r3, #0 + 8000ee4: d003 beq.n 8000eee + { + SET_BIT(temp, iocurrent); + 8000ee6: 693a ldr r2, [r7, #16] + 8000ee8: 68fb ldr r3, [r7, #12] + 8000eea: 4313 orrs r3, r2 + 8000eec: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 8000eee: 4a28 ldr r2, [pc, #160] @ (8000f90 ) + 8000ef0: 693b ldr r3, [r7, #16] + 8000ef2: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8000ef4: 4b26 ldr r3, [pc, #152] @ (8000f90 ) + 8000ef6: 685b ldr r3, [r3, #4] + 8000ef8: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000efa: 68fb ldr r3, [r7, #12] + 8000efc: 43db mvns r3, r3 + 8000efe: 693a ldr r2, [r7, #16] + 8000f00: 4013 ands r3, r2 + 8000f02: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8000f04: 683b ldr r3, [r7, #0] + 8000f06: 685b ldr r3, [r3, #4] + 8000f08: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8000f0c: 2b00 cmp r3, #0 + 8000f0e: d003 beq.n 8000f18 + { + SET_BIT(temp, iocurrent); + 8000f10: 693a ldr r2, [r7, #16] + 8000f12: 68fb ldr r3, [r7, #12] + 8000f14: 4313 orrs r3, r2 + 8000f16: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8000f18: 4a1d ldr r2, [pc, #116] @ (8000f90 ) + 8000f1a: 693b ldr r3, [r7, #16] + 8000f1c: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8000f1e: 4b1c ldr r3, [pc, #112] @ (8000f90 ) + 8000f20: 681b ldr r3, [r3, #0] + 8000f22: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000f24: 68fb ldr r3, [r7, #12] + 8000f26: 43db mvns r3, r3 + 8000f28: 693a ldr r2, [r7, #16] + 8000f2a: 4013 ands r3, r2 + 8000f2c: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 8000f2e: 683b ldr r3, [r7, #0] + 8000f30: 685b ldr r3, [r3, #4] + 8000f32: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8000f36: 2b00 cmp r3, #0 + 8000f38: d003 beq.n 8000f42 + { + SET_BIT(temp, iocurrent); + 8000f3a: 693a ldr r2, [r7, #16] + 8000f3c: 68fb ldr r3, [r7, #12] + 8000f3e: 4313 orrs r3, r2 + 8000f40: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 8000f42: 4a13 ldr r2, [pc, #76] @ (8000f90 ) + 8000f44: 693b ldr r3, [r7, #16] + 8000f46: 6013 str r3, [r2, #0] + } + } + + position++; + 8000f48: 697b ldr r3, [r7, #20] + 8000f4a: 3301 adds r3, #1 + 8000f4c: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 8000f4e: 683b ldr r3, [r7, #0] + 8000f50: 681a ldr r2, [r3, #0] + 8000f52: 697b ldr r3, [r7, #20] + 8000f54: fa22 f303 lsr.w r3, r2, r3 + 8000f58: 2b00 cmp r3, #0 + 8000f5a: f47f ae97 bne.w 8000c8c + } +} + 8000f5e: bf00 nop + 8000f60: bf00 nop + 8000f62: 371c adds r7, #28 + 8000f64: 46bd mov sp, r7 + 8000f66: bc80 pop {r7} + 8000f68: 4770 bx lr + 8000f6a: bf00 nop + 8000f6c: 40023800 .word 0x40023800 + 8000f70: 40010000 .word 0x40010000 + 8000f74: 40020000 .word 0x40020000 + 8000f78: 40020400 .word 0x40020400 + 8000f7c: 40020800 .word 0x40020800 + 8000f80: 40020c00 .word 0x40020c00 + 8000f84: 40021000 .word 0x40021000 + 8000f88: 40021400 .word 0x40021400 + 8000f8c: 40021800 .word 0x40021800 + 8000f90: 40010400 .word 0x40010400 + +08000f94 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8000f94: b480 push {r7} + 8000f96: b083 sub sp, #12 + 8000f98: af00 add r7, sp, #0 + 8000f9a: 6078 str r0, [r7, #4] + 8000f9c: 460b mov r3, r1 + 8000f9e: 807b strh r3, [r7, #2] + 8000fa0: 4613 mov r3, r2 + 8000fa2: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8000fa4: 787b ldrb r3, [r7, #1] + 8000fa6: 2b00 cmp r3, #0 + 8000fa8: d003 beq.n 8000fb2 + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8000faa: 887a ldrh r2, [r7, #2] + 8000fac: 687b ldr r3, [r7, #4] + 8000fae: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 8000fb0: e003 b.n 8000fba + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 8000fb2: 887b ldrh r3, [r7, #2] + 8000fb4: 041a lsls r2, r3, #16 + 8000fb6: 687b ldr r3, [r7, #4] + 8000fb8: 619a str r2, [r3, #24] +} + 8000fba: bf00 nop + 8000fbc: 370c adds r7, #12 + 8000fbe: 46bd mov sp, r7 + 8000fc0: bc80 pop {r7} + 8000fc2: 4770 bx lr + +08000fc4 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8000fc4: b580 push {r7, lr} + 8000fc6: b088 sub sp, #32 + 8000fc8: af00 add r7, sp, #0 + 8000fca: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 8000fcc: 687b ldr r3, [r7, #4] + 8000fce: 2b00 cmp r3, #0 + 8000fd0: d101 bne.n 8000fd6 + { + return HAL_ERROR; + 8000fd2: 2301 movs r3, #1 + 8000fd4: e31d b.n 8001612 + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8000fd6: 4b94 ldr r3, [pc, #592] @ (8001228 ) + 8000fd8: 689b ldr r3, [r3, #8] + 8000fda: f003 030c and.w r3, r3, #12 + 8000fde: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8000fe0: 4b91 ldr r3, [pc, #580] @ (8001228 ) + 8000fe2: 689b ldr r3, [r3, #8] + 8000fe4: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8000fe8: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8000fea: 687b ldr r3, [r7, #4] + 8000fec: 681b ldr r3, [r3, #0] + 8000fee: f003 0301 and.w r3, r3, #1 + 8000ff2: 2b00 cmp r3, #0 + 8000ff4: d07b beq.n 80010ee + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 8000ff6: 69bb ldr r3, [r7, #24] + 8000ff8: 2b08 cmp r3, #8 + 8000ffa: d006 beq.n 800100a + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8000ffc: 69bb ldr r3, [r7, #24] + 8000ffe: 2b0c cmp r3, #12 + 8001000: d10f bne.n 8001022 + 8001002: 697b ldr r3, [r7, #20] + 8001004: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001008: d10b bne.n 8001022 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 800100a: 4b87 ldr r3, [pc, #540] @ (8001228 ) + 800100c: 681b ldr r3, [r3, #0] + 800100e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001012: 2b00 cmp r3, #0 + 8001014: d06a beq.n 80010ec + 8001016: 687b ldr r3, [r7, #4] + 8001018: 685b ldr r3, [r3, #4] + 800101a: 2b00 cmp r3, #0 + 800101c: d166 bne.n 80010ec + { + return HAL_ERROR; + 800101e: 2301 movs r3, #1 + 8001020: e2f7 b.n 8001612 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8001022: 687b ldr r3, [r7, #4] + 8001024: 685b ldr r3, [r3, #4] + 8001026: 2b01 cmp r3, #1 + 8001028: d106 bne.n 8001038 + 800102a: 4b7f ldr r3, [pc, #508] @ (8001228 ) + 800102c: 681b ldr r3, [r3, #0] + 800102e: 4a7e ldr r2, [pc, #504] @ (8001228 ) + 8001030: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001034: 6013 str r3, [r2, #0] + 8001036: e02d b.n 8001094 + 8001038: 687b ldr r3, [r7, #4] + 800103a: 685b ldr r3, [r3, #4] + 800103c: 2b00 cmp r3, #0 + 800103e: d10c bne.n 800105a + 8001040: 4b79 ldr r3, [pc, #484] @ (8001228 ) + 8001042: 681b ldr r3, [r3, #0] + 8001044: 4a78 ldr r2, [pc, #480] @ (8001228 ) + 8001046: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800104a: 6013 str r3, [r2, #0] + 800104c: 4b76 ldr r3, [pc, #472] @ (8001228 ) + 800104e: 681b ldr r3, [r3, #0] + 8001050: 4a75 ldr r2, [pc, #468] @ (8001228 ) + 8001052: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001056: 6013 str r3, [r2, #0] + 8001058: e01c b.n 8001094 + 800105a: 687b ldr r3, [r7, #4] + 800105c: 685b ldr r3, [r3, #4] + 800105e: 2b05 cmp r3, #5 + 8001060: d10c bne.n 800107c + 8001062: 4b71 ldr r3, [pc, #452] @ (8001228 ) + 8001064: 681b ldr r3, [r3, #0] + 8001066: 4a70 ldr r2, [pc, #448] @ (8001228 ) + 8001068: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 800106c: 6013 str r3, [r2, #0] + 800106e: 4b6e ldr r3, [pc, #440] @ (8001228 ) + 8001070: 681b ldr r3, [r3, #0] + 8001072: 4a6d ldr r2, [pc, #436] @ (8001228 ) + 8001074: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001078: 6013 str r3, [r2, #0] + 800107a: e00b b.n 8001094 + 800107c: 4b6a ldr r3, [pc, #424] @ (8001228 ) + 800107e: 681b ldr r3, [r3, #0] + 8001080: 4a69 ldr r2, [pc, #420] @ (8001228 ) + 8001082: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001086: 6013 str r3, [r2, #0] + 8001088: 4b67 ldr r3, [pc, #412] @ (8001228 ) + 800108a: 681b ldr r3, [r3, #0] + 800108c: 4a66 ldr r2, [pc, #408] @ (8001228 ) + 800108e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001092: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8001094: 687b ldr r3, [r7, #4] + 8001096: 685b ldr r3, [r3, #4] + 8001098: 2b00 cmp r3, #0 + 800109a: d013 beq.n 80010c4 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800109c: f7ff fcda bl 8000a54 + 80010a0: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 80010a2: e008 b.n 80010b6 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80010a4: f7ff fcd6 bl 8000a54 + 80010a8: 4602 mov r2, r0 + 80010aa: 693b ldr r3, [r7, #16] + 80010ac: 1ad3 subs r3, r2, r3 + 80010ae: 2b64 cmp r3, #100 @ 0x64 + 80010b0: d901 bls.n 80010b6 + { + return HAL_TIMEOUT; + 80010b2: 2303 movs r3, #3 + 80010b4: e2ad b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 80010b6: 4b5c ldr r3, [pc, #368] @ (8001228 ) + 80010b8: 681b ldr r3, [r3, #0] + 80010ba: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80010be: 2b00 cmp r3, #0 + 80010c0: d0f0 beq.n 80010a4 + 80010c2: e014 b.n 80010ee + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80010c4: f7ff fcc6 bl 8000a54 + 80010c8: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80010ca: e008 b.n 80010de + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80010cc: f7ff fcc2 bl 8000a54 + 80010d0: 4602 mov r2, r0 + 80010d2: 693b ldr r3, [r7, #16] + 80010d4: 1ad3 subs r3, r2, r3 + 80010d6: 2b64 cmp r3, #100 @ 0x64 + 80010d8: d901 bls.n 80010de + { + return HAL_TIMEOUT; + 80010da: 2303 movs r3, #3 + 80010dc: e299 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80010de: 4b52 ldr r3, [pc, #328] @ (8001228 ) + 80010e0: 681b ldr r3, [r3, #0] + 80010e2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80010e6: 2b00 cmp r3, #0 + 80010e8: d1f0 bne.n 80010cc + 80010ea: e000 b.n 80010ee + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80010ec: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80010ee: 687b ldr r3, [r7, #4] + 80010f0: 681b ldr r3, [r3, #0] + 80010f2: f003 0302 and.w r3, r3, #2 + 80010f6: 2b00 cmp r3, #0 + 80010f8: d05a beq.n 80011b0 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 80010fa: 69bb ldr r3, [r7, #24] + 80010fc: 2b04 cmp r3, #4 + 80010fe: d005 beq.n 800110c + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8001100: 69bb ldr r3, [r7, #24] + 8001102: 2b0c cmp r3, #12 + 8001104: d119 bne.n 800113a + 8001106: 697b ldr r3, [r7, #20] + 8001108: 2b00 cmp r3, #0 + 800110a: d116 bne.n 800113a + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800110c: 4b46 ldr r3, [pc, #280] @ (8001228 ) + 800110e: 681b ldr r3, [r3, #0] + 8001110: f003 0302 and.w r3, r3, #2 + 8001114: 2b00 cmp r3, #0 + 8001116: d005 beq.n 8001124 + 8001118: 687b ldr r3, [r7, #4] + 800111a: 68db ldr r3, [r3, #12] + 800111c: 2b01 cmp r3, #1 + 800111e: d001 beq.n 8001124 + { + return HAL_ERROR; + 8001120: 2301 movs r3, #1 + 8001122: e276 b.n 8001612 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001124: 4b40 ldr r3, [pc, #256] @ (8001228 ) + 8001126: 685b ldr r3, [r3, #4] + 8001128: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 800112c: 687b ldr r3, [r7, #4] + 800112e: 691b ldr r3, [r3, #16] + 8001130: 021b lsls r3, r3, #8 + 8001132: 493d ldr r1, [pc, #244] @ (8001228 ) + 8001134: 4313 orrs r3, r2 + 8001136: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001138: e03a b.n 80011b0 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 800113a: 687b ldr r3, [r7, #4] + 800113c: 68db ldr r3, [r3, #12] + 800113e: 2b00 cmp r3, #0 + 8001140: d020 beq.n 8001184 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8001142: 4b3a ldr r3, [pc, #232] @ (800122c ) + 8001144: 2201 movs r2, #1 + 8001146: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001148: f7ff fc84 bl 8000a54 + 800114c: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800114e: e008 b.n 8001162 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001150: f7ff fc80 bl 8000a54 + 8001154: 4602 mov r2, r0 + 8001156: 693b ldr r3, [r7, #16] + 8001158: 1ad3 subs r3, r2, r3 + 800115a: 2b02 cmp r3, #2 + 800115c: d901 bls.n 8001162 + { + return HAL_TIMEOUT; + 800115e: 2303 movs r3, #3 + 8001160: e257 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001162: 4b31 ldr r3, [pc, #196] @ (8001228 ) + 8001164: 681b ldr r3, [r3, #0] + 8001166: f003 0302 and.w r3, r3, #2 + 800116a: 2b00 cmp r3, #0 + 800116c: d0f0 beq.n 8001150 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800116e: 4b2e ldr r3, [pc, #184] @ (8001228 ) + 8001170: 685b ldr r3, [r3, #4] + 8001172: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001176: 687b ldr r3, [r7, #4] + 8001178: 691b ldr r3, [r3, #16] + 800117a: 021b lsls r3, r3, #8 + 800117c: 492a ldr r1, [pc, #168] @ (8001228 ) + 800117e: 4313 orrs r3, r2 + 8001180: 604b str r3, [r1, #4] + 8001182: e015 b.n 80011b0 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8001184: 4b29 ldr r3, [pc, #164] @ (800122c ) + 8001186: 2200 movs r2, #0 + 8001188: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800118a: f7ff fc63 bl 8000a54 + 800118e: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001190: e008 b.n 80011a4 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001192: f7ff fc5f bl 8000a54 + 8001196: 4602 mov r2, r0 + 8001198: 693b ldr r3, [r7, #16] + 800119a: 1ad3 subs r3, r2, r3 + 800119c: 2b02 cmp r3, #2 + 800119e: d901 bls.n 80011a4 + { + return HAL_TIMEOUT; + 80011a0: 2303 movs r3, #3 + 80011a2: e236 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 80011a4: 4b20 ldr r3, [pc, #128] @ (8001228 ) + 80011a6: 681b ldr r3, [r3, #0] + 80011a8: f003 0302 and.w r3, r3, #2 + 80011ac: 2b00 cmp r3, #0 + 80011ae: d1f0 bne.n 8001192 + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 80011b0: 687b ldr r3, [r7, #4] + 80011b2: 681b ldr r3, [r3, #0] + 80011b4: f003 0310 and.w r3, r3, #16 + 80011b8: 2b00 cmp r3, #0 + 80011ba: f000 80b8 beq.w 800132e + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 80011be: 69bb ldr r3, [r7, #24] + 80011c0: 2b00 cmp r3, #0 + 80011c2: d170 bne.n 80012a6 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 80011c4: 4b18 ldr r3, [pc, #96] @ (8001228 ) + 80011c6: 681b ldr r3, [r3, #0] + 80011c8: f403 7300 and.w r3, r3, #512 @ 0x200 + 80011cc: 2b00 cmp r3, #0 + 80011ce: d005 beq.n 80011dc + 80011d0: 687b ldr r3, [r7, #4] + 80011d2: 699b ldr r3, [r3, #24] + 80011d4: 2b00 cmp r3, #0 + 80011d6: d101 bne.n 80011dc + { + return HAL_ERROR; + 80011d8: 2301 movs r3, #1 + 80011da: e21a b.n 8001612 + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 80011dc: 687b ldr r3, [r7, #4] + 80011de: 6a1a ldr r2, [r3, #32] + 80011e0: 4b11 ldr r3, [pc, #68] @ (8001228 ) + 80011e2: 685b ldr r3, [r3, #4] + 80011e4: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 80011e8: 429a cmp r2, r3 + 80011ea: d921 bls.n 8001230 + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80011ec: 687b ldr r3, [r7, #4] + 80011ee: 6a1b ldr r3, [r3, #32] + 80011f0: 4618 mov r0, r3 + 80011f2: f000 fc09 bl 8001a08 + 80011f6: 4603 mov r3, r0 + 80011f8: 2b00 cmp r3, #0 + 80011fa: d001 beq.n 8001200 + { + return HAL_ERROR; + 80011fc: 2301 movs r3, #1 + 80011fe: e208 b.n 8001612 + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001200: 4b09 ldr r3, [pc, #36] @ (8001228 ) + 8001202: 685b ldr r3, [r3, #4] + 8001204: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001208: 687b ldr r3, [r7, #4] + 800120a: 6a1b ldr r3, [r3, #32] + 800120c: 4906 ldr r1, [pc, #24] @ (8001228 ) + 800120e: 4313 orrs r3, r2 + 8001210: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001212: 4b05 ldr r3, [pc, #20] @ (8001228 ) + 8001214: 685b ldr r3, [r3, #4] + 8001216: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 800121a: 687b ldr r3, [r7, #4] + 800121c: 69db ldr r3, [r3, #28] + 800121e: 061b lsls r3, r3, #24 + 8001220: 4901 ldr r1, [pc, #4] @ (8001228 ) + 8001222: 4313 orrs r3, r2 + 8001224: 604b str r3, [r1, #4] + 8001226: e020 b.n 800126a + 8001228: 40023800 .word 0x40023800 + 800122c: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001230: 4b99 ldr r3, [pc, #612] @ (8001498 ) + 8001232: 685b ldr r3, [r3, #4] + 8001234: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001238: 687b ldr r3, [r7, #4] + 800123a: 6a1b ldr r3, [r3, #32] + 800123c: 4996 ldr r1, [pc, #600] @ (8001498 ) + 800123e: 4313 orrs r3, r2 + 8001240: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001242: 4b95 ldr r3, [pc, #596] @ (8001498 ) + 8001244: 685b ldr r3, [r3, #4] + 8001246: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 800124a: 687b ldr r3, [r7, #4] + 800124c: 69db ldr r3, [r3, #28] + 800124e: 061b lsls r3, r3, #24 + 8001250: 4991 ldr r1, [pc, #580] @ (8001498 ) + 8001252: 4313 orrs r3, r2 + 8001254: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001256: 687b ldr r3, [r7, #4] + 8001258: 6a1b ldr r3, [r3, #32] + 800125a: 4618 mov r0, r3 + 800125c: f000 fbd4 bl 8001a08 + 8001260: 4603 mov r3, r0 + 8001262: 2b00 cmp r3, #0 + 8001264: d001 beq.n 800126a + { + return HAL_ERROR; + 8001266: 2301 movs r3, #1 + 8001268: e1d3 b.n 8001612 + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 800126a: 687b ldr r3, [r7, #4] + 800126c: 6a1b ldr r3, [r3, #32] + 800126e: 0b5b lsrs r3, r3, #13 + 8001270: 3301 adds r3, #1 + 8001272: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001276: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 800127a: 4a87 ldr r2, [pc, #540] @ (8001498 ) + 800127c: 6892 ldr r2, [r2, #8] + 800127e: 0912 lsrs r2, r2, #4 + 8001280: f002 020f and.w r2, r2, #15 + 8001284: 4985 ldr r1, [pc, #532] @ (800149c ) + 8001286: 5c8a ldrb r2, [r1, r2] + 8001288: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 800128a: 4a85 ldr r2, [pc, #532] @ (80014a0 ) + 800128c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 800128e: 4b85 ldr r3, [pc, #532] @ (80014a4 ) + 8001290: 681b ldr r3, [r3, #0] + 8001292: 4618 mov r0, r3 + 8001294: f7ff fb92 bl 80009bc + 8001298: 4603 mov r3, r0 + 800129a: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 800129c: 7bfb ldrb r3, [r7, #15] + 800129e: 2b00 cmp r3, #0 + 80012a0: d045 beq.n 800132e + { + return status; + 80012a2: 7bfb ldrb r3, [r7, #15] + 80012a4: e1b5 b.n 8001612 + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 80012a6: 687b ldr r3, [r7, #4] + 80012a8: 699b ldr r3, [r3, #24] + 80012aa: 2b00 cmp r3, #0 + 80012ac: d029 beq.n 8001302 + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 80012ae: 4b7e ldr r3, [pc, #504] @ (80014a8 ) + 80012b0: 2201 movs r2, #1 + 80012b2: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80012b4: f7ff fbce bl 8000a54 + 80012b8: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80012ba: e008 b.n 80012ce + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80012bc: f7ff fbca bl 8000a54 + 80012c0: 4602 mov r2, r0 + 80012c2: 693b ldr r3, [r7, #16] + 80012c4: 1ad3 subs r3, r2, r3 + 80012c6: 2b02 cmp r3, #2 + 80012c8: d901 bls.n 80012ce + { + return HAL_TIMEOUT; + 80012ca: 2303 movs r3, #3 + 80012cc: e1a1 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80012ce: 4b72 ldr r3, [pc, #456] @ (8001498 ) + 80012d0: 681b ldr r3, [r3, #0] + 80012d2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80012d6: 2b00 cmp r3, #0 + 80012d8: d0f0 beq.n 80012bc + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80012da: 4b6f ldr r3, [pc, #444] @ (8001498 ) + 80012dc: 685b ldr r3, [r3, #4] + 80012de: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80012e2: 687b ldr r3, [r7, #4] + 80012e4: 6a1b ldr r3, [r3, #32] + 80012e6: 496c ldr r1, [pc, #432] @ (8001498 ) + 80012e8: 4313 orrs r3, r2 + 80012ea: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80012ec: 4b6a ldr r3, [pc, #424] @ (8001498 ) + 80012ee: 685b ldr r3, [r3, #4] + 80012f0: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80012f4: 687b ldr r3, [r7, #4] + 80012f6: 69db ldr r3, [r3, #28] + 80012f8: 061b lsls r3, r3, #24 + 80012fa: 4967 ldr r1, [pc, #412] @ (8001498 ) + 80012fc: 4313 orrs r3, r2 + 80012fe: 604b str r3, [r1, #4] + 8001300: e015 b.n 800132e + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8001302: 4b69 ldr r3, [pc, #420] @ (80014a8 ) + 8001304: 2200 movs r2, #0 + 8001306: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001308: f7ff fba4 bl 8000a54 + 800130c: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 800130e: e008 b.n 8001322 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001310: f7ff fba0 bl 8000a54 + 8001314: 4602 mov r2, r0 + 8001316: 693b ldr r3, [r7, #16] + 8001318: 1ad3 subs r3, r2, r3 + 800131a: 2b02 cmp r3, #2 + 800131c: d901 bls.n 8001322 + { + return HAL_TIMEOUT; + 800131e: 2303 movs r3, #3 + 8001320: e177 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 8001322: 4b5d ldr r3, [pc, #372] @ (8001498 ) + 8001324: 681b ldr r3, [r3, #0] + 8001326: f403 7300 and.w r3, r3, #512 @ 0x200 + 800132a: 2b00 cmp r3, #0 + 800132c: d1f0 bne.n 8001310 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 800132e: 687b ldr r3, [r7, #4] + 8001330: 681b ldr r3, [r3, #0] + 8001332: f003 0308 and.w r3, r3, #8 + 8001336: 2b00 cmp r3, #0 + 8001338: d030 beq.n 800139c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 800133a: 687b ldr r3, [r7, #4] + 800133c: 695b ldr r3, [r3, #20] + 800133e: 2b00 cmp r3, #0 + 8001340: d016 beq.n 8001370 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8001342: 4b5a ldr r3, [pc, #360] @ (80014ac ) + 8001344: 2201 movs r2, #1 + 8001346: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001348: f7ff fb84 bl 8000a54 + 800134c: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800134e: e008 b.n 8001362 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001350: f7ff fb80 bl 8000a54 + 8001354: 4602 mov r2, r0 + 8001356: 693b ldr r3, [r7, #16] + 8001358: 1ad3 subs r3, r2, r3 + 800135a: 2b02 cmp r3, #2 + 800135c: d901 bls.n 8001362 + { + return HAL_TIMEOUT; + 800135e: 2303 movs r3, #3 + 8001360: e157 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8001362: 4b4d ldr r3, [pc, #308] @ (8001498 ) + 8001364: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001366: f003 0302 and.w r3, r3, #2 + 800136a: 2b00 cmp r3, #0 + 800136c: d0f0 beq.n 8001350 + 800136e: e015 b.n 800139c + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001370: 4b4e ldr r3, [pc, #312] @ (80014ac ) + 8001372: 2200 movs r2, #0 + 8001374: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001376: f7ff fb6d bl 8000a54 + 800137a: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 800137c: e008 b.n 8001390 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800137e: f7ff fb69 bl 8000a54 + 8001382: 4602 mov r2, r0 + 8001384: 693b ldr r3, [r7, #16] + 8001386: 1ad3 subs r3, r2, r3 + 8001388: 2b02 cmp r3, #2 + 800138a: d901 bls.n 8001390 + { + return HAL_TIMEOUT; + 800138c: 2303 movs r3, #3 + 800138e: e140 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001390: 4b41 ldr r3, [pc, #260] @ (8001498 ) + 8001392: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001394: f003 0302 and.w r3, r3, #2 + 8001398: 2b00 cmp r3, #0 + 800139a: d1f0 bne.n 800137e + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800139c: 687b ldr r3, [r7, #4] + 800139e: 681b ldr r3, [r3, #0] + 80013a0: f003 0304 and.w r3, r3, #4 + 80013a4: 2b00 cmp r3, #0 + 80013a6: f000 80b5 beq.w 8001514 + { + FlagStatus pwrclkchanged = RESET; + 80013aa: 2300 movs r3, #0 + 80013ac: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 80013ae: 4b3a ldr r3, [pc, #232] @ (8001498 ) + 80013b0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80013b2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80013b6: 2b00 cmp r3, #0 + 80013b8: d10d bne.n 80013d6 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 80013ba: 4b37 ldr r3, [pc, #220] @ (8001498 ) + 80013bc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80013be: 4a36 ldr r2, [pc, #216] @ (8001498 ) + 80013c0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80013c4: 6253 str r3, [r2, #36] @ 0x24 + 80013c6: 4b34 ldr r3, [pc, #208] @ (8001498 ) + 80013c8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80013ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80013ce: 60bb str r3, [r7, #8] + 80013d0: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 80013d2: 2301 movs r3, #1 + 80013d4: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80013d6: 4b36 ldr r3, [pc, #216] @ (80014b0 ) + 80013d8: 681b ldr r3, [r3, #0] + 80013da: f403 7380 and.w r3, r3, #256 @ 0x100 + 80013de: 2b00 cmp r3, #0 + 80013e0: d118 bne.n 8001414 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80013e2: 4b33 ldr r3, [pc, #204] @ (80014b0 ) + 80013e4: 681b ldr r3, [r3, #0] + 80013e6: 4a32 ldr r2, [pc, #200] @ (80014b0 ) + 80013e8: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80013ec: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80013ee: f7ff fb31 bl 8000a54 + 80013f2: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80013f4: e008 b.n 8001408 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80013f6: f7ff fb2d bl 8000a54 + 80013fa: 4602 mov r2, r0 + 80013fc: 693b ldr r3, [r7, #16] + 80013fe: 1ad3 subs r3, r2, r3 + 8001400: 2b64 cmp r3, #100 @ 0x64 + 8001402: d901 bls.n 8001408 + { + return HAL_TIMEOUT; + 8001404: 2303 movs r3, #3 + 8001406: e104 b.n 8001612 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001408: 4b29 ldr r3, [pc, #164] @ (80014b0 ) + 800140a: 681b ldr r3, [r3, #0] + 800140c: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001410: 2b00 cmp r3, #0 + 8001412: d0f0 beq.n 80013f6 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8001414: 687b ldr r3, [r7, #4] + 8001416: 689b ldr r3, [r3, #8] + 8001418: 2b01 cmp r3, #1 + 800141a: d106 bne.n 800142a + 800141c: 4b1e ldr r3, [pc, #120] @ (8001498 ) + 800141e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001420: 4a1d ldr r2, [pc, #116] @ (8001498 ) + 8001422: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001426: 6353 str r3, [r2, #52] @ 0x34 + 8001428: e02d b.n 8001486 + 800142a: 687b ldr r3, [r7, #4] + 800142c: 689b ldr r3, [r3, #8] + 800142e: 2b00 cmp r3, #0 + 8001430: d10c bne.n 800144c + 8001432: 4b19 ldr r3, [pc, #100] @ (8001498 ) + 8001434: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001436: 4a18 ldr r2, [pc, #96] @ (8001498 ) + 8001438: f423 7380 bic.w r3, r3, #256 @ 0x100 + 800143c: 6353 str r3, [r2, #52] @ 0x34 + 800143e: 4b16 ldr r3, [pc, #88] @ (8001498 ) + 8001440: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001442: 4a15 ldr r2, [pc, #84] @ (8001498 ) + 8001444: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001448: 6353 str r3, [r2, #52] @ 0x34 + 800144a: e01c b.n 8001486 + 800144c: 687b ldr r3, [r7, #4] + 800144e: 689b ldr r3, [r3, #8] + 8001450: 2b05 cmp r3, #5 + 8001452: d10c bne.n 800146e + 8001454: 4b10 ldr r3, [pc, #64] @ (8001498 ) + 8001456: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001458: 4a0f ldr r2, [pc, #60] @ (8001498 ) + 800145a: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 800145e: 6353 str r3, [r2, #52] @ 0x34 + 8001460: 4b0d ldr r3, [pc, #52] @ (8001498 ) + 8001462: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001464: 4a0c ldr r2, [pc, #48] @ (8001498 ) + 8001466: f443 7380 orr.w r3, r3, #256 @ 0x100 + 800146a: 6353 str r3, [r2, #52] @ 0x34 + 800146c: e00b b.n 8001486 + 800146e: 4b0a ldr r3, [pc, #40] @ (8001498 ) + 8001470: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001472: 4a09 ldr r2, [pc, #36] @ (8001498 ) + 8001474: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001478: 6353 str r3, [r2, #52] @ 0x34 + 800147a: 4b07 ldr r3, [pc, #28] @ (8001498 ) + 800147c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800147e: 4a06 ldr r2, [pc, #24] @ (8001498 ) + 8001480: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001484: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8001486: 687b ldr r3, [r7, #4] + 8001488: 689b ldr r3, [r3, #8] + 800148a: 2b00 cmp r3, #0 + 800148c: d024 beq.n 80014d8 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800148e: f7ff fae1 bl 8000a54 + 8001492: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001494: e019 b.n 80014ca + 8001496: bf00 nop + 8001498: 40023800 .word 0x40023800 + 800149c: 08002098 .word 0x08002098 + 80014a0: 20000000 .word 0x20000000 + 80014a4: 20000004 .word 0x20000004 + 80014a8: 42470020 .word 0x42470020 + 80014ac: 42470680 .word 0x42470680 + 80014b0: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80014b4: f7ff face bl 8000a54 + 80014b8: 4602 mov r2, r0 + 80014ba: 693b ldr r3, [r7, #16] + 80014bc: 1ad3 subs r3, r2, r3 + 80014be: f241 3288 movw r2, #5000 @ 0x1388 + 80014c2: 4293 cmp r3, r2 + 80014c4: d901 bls.n 80014ca + { + return HAL_TIMEOUT; + 80014c6: 2303 movs r3, #3 + 80014c8: e0a3 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 80014ca: 4b54 ldr r3, [pc, #336] @ (800161c ) + 80014cc: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014ce: f403 7300 and.w r3, r3, #512 @ 0x200 + 80014d2: 2b00 cmp r3, #0 + 80014d4: d0ee beq.n 80014b4 + 80014d6: e014 b.n 8001502 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80014d8: f7ff fabc bl 8000a54 + 80014dc: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80014de: e00a b.n 80014f6 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80014e0: f7ff fab8 bl 8000a54 + 80014e4: 4602 mov r2, r0 + 80014e6: 693b ldr r3, [r7, #16] + 80014e8: 1ad3 subs r3, r2, r3 + 80014ea: f241 3288 movw r2, #5000 @ 0x1388 + 80014ee: 4293 cmp r3, r2 + 80014f0: d901 bls.n 80014f6 + { + return HAL_TIMEOUT; + 80014f2: 2303 movs r3, #3 + 80014f4: e08d b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80014f6: 4b49 ldr r3, [pc, #292] @ (800161c ) + 80014f8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014fa: f403 7300 and.w r3, r3, #512 @ 0x200 + 80014fe: 2b00 cmp r3, #0 + 8001500: d1ee bne.n 80014e0 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 8001502: 7ffb ldrb r3, [r7, #31] + 8001504: 2b01 cmp r3, #1 + 8001506: d105 bne.n 8001514 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8001508: 4b44 ldr r3, [pc, #272] @ (800161c ) + 800150a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800150c: 4a43 ldr r2, [pc, #268] @ (800161c ) + 800150e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001512: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8001514: 687b ldr r3, [r7, #4] + 8001516: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001518: 2b00 cmp r3, #0 + 800151a: d079 beq.n 8001610 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 800151c: 69bb ldr r3, [r7, #24] + 800151e: 2b0c cmp r3, #12 + 8001520: d056 beq.n 80015d0 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8001522: 687b ldr r3, [r7, #4] + 8001524: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001526: 2b02 cmp r3, #2 + 8001528: d13b bne.n 80015a2 + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 800152a: 4b3d ldr r3, [pc, #244] @ (8001620 ) + 800152c: 2200 movs r2, #0 + 800152e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001530: f7ff fa90 bl 8000a54 + 8001534: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001536: e008 b.n 800154a + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001538: f7ff fa8c bl 8000a54 + 800153c: 4602 mov r2, r0 + 800153e: 693b ldr r3, [r7, #16] + 8001540: 1ad3 subs r3, r2, r3 + 8001542: 2b02 cmp r3, #2 + 8001544: d901 bls.n 800154a + { + return HAL_TIMEOUT; + 8001546: 2303 movs r3, #3 + 8001548: e063 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800154a: 4b34 ldr r3, [pc, #208] @ (800161c ) + 800154c: 681b ldr r3, [r3, #0] + 800154e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001552: 2b00 cmp r3, #0 + 8001554: d1f0 bne.n 8001538 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8001556: 4b31 ldr r3, [pc, #196] @ (800161c ) + 8001558: 689b ldr r3, [r3, #8] + 800155a: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 800155e: 687b ldr r3, [r7, #4] + 8001560: 6a99 ldr r1, [r3, #40] @ 0x28 + 8001562: 687b ldr r3, [r7, #4] + 8001564: 6adb ldr r3, [r3, #44] @ 0x2c + 8001566: 4319 orrs r1, r3 + 8001568: 687b ldr r3, [r7, #4] + 800156a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800156c: 430b orrs r3, r1 + 800156e: 492b ldr r1, [pc, #172] @ (800161c ) + 8001570: 4313 orrs r3, r2 + 8001572: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8001574: 4b2a ldr r3, [pc, #168] @ (8001620 ) + 8001576: 2201 movs r2, #1 + 8001578: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800157a: f7ff fa6b bl 8000a54 + 800157e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001580: e008 b.n 8001594 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001582: f7ff fa67 bl 8000a54 + 8001586: 4602 mov r2, r0 + 8001588: 693b ldr r3, [r7, #16] + 800158a: 1ad3 subs r3, r2, r3 + 800158c: 2b02 cmp r3, #2 + 800158e: d901 bls.n 8001594 + { + return HAL_TIMEOUT; + 8001590: 2303 movs r3, #3 + 8001592: e03e b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001594: 4b21 ldr r3, [pc, #132] @ (800161c ) + 8001596: 681b ldr r3, [r3, #0] + 8001598: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800159c: 2b00 cmp r3, #0 + 800159e: d0f0 beq.n 8001582 + 80015a0: e036 b.n 8001610 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80015a2: 4b1f ldr r3, [pc, #124] @ (8001620 ) + 80015a4: 2200 movs r2, #0 + 80015a6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80015a8: f7ff fa54 bl 8000a54 + 80015ac: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80015ae: e008 b.n 80015c2 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80015b0: f7ff fa50 bl 8000a54 + 80015b4: 4602 mov r2, r0 + 80015b6: 693b ldr r3, [r7, #16] + 80015b8: 1ad3 subs r3, r2, r3 + 80015ba: 2b02 cmp r3, #2 + 80015bc: d901 bls.n 80015c2 + { + return HAL_TIMEOUT; + 80015be: 2303 movs r3, #3 + 80015c0: e027 b.n 8001612 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80015c2: 4b16 ldr r3, [pc, #88] @ (800161c ) + 80015c4: 681b ldr r3, [r3, #0] + 80015c6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80015ca: 2b00 cmp r3, #0 + 80015cc: d1f0 bne.n 80015b0 + 80015ce: e01f b.n 8001610 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 80015d0: 687b ldr r3, [r7, #4] + 80015d2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80015d4: 2b01 cmp r3, #1 + 80015d6: d101 bne.n 80015dc + { + return HAL_ERROR; + 80015d8: 2301 movs r3, #1 + 80015da: e01a b.n 8001612 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 80015dc: 4b0f ldr r3, [pc, #60] @ (800161c ) + 80015de: 689b ldr r3, [r3, #8] + 80015e0: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80015e2: 697b ldr r3, [r7, #20] + 80015e4: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 80015e8: 687b ldr r3, [r7, #4] + 80015ea: 6a9b ldr r3, [r3, #40] @ 0x28 + 80015ec: 429a cmp r2, r3 + 80015ee: d10d bne.n 800160c + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80015f0: 697b ldr r3, [r7, #20] + 80015f2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 80015f6: 687b ldr r3, [r7, #4] + 80015f8: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80015fa: 429a cmp r2, r3 + 80015fc: d106 bne.n 800160c + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 80015fe: 697b ldr r3, [r7, #20] + 8001600: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 8001604: 687b ldr r3, [r7, #4] + 8001606: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8001608: 429a cmp r2, r3 + 800160a: d001 beq.n 8001610 + { + return HAL_ERROR; + 800160c: 2301 movs r3, #1 + 800160e: e000 b.n 8001612 + } + } + } + } + + return HAL_OK; + 8001610: 2300 movs r3, #0 +} + 8001612: 4618 mov r0, r3 + 8001614: 3720 adds r7, #32 + 8001616: 46bd mov sp, r7 + 8001618: bd80 pop {r7, pc} + 800161a: bf00 nop + 800161c: 40023800 .word 0x40023800 + 8001620: 42470060 .word 0x42470060 + +08001624 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8001624: b580 push {r7, lr} + 8001626: b084 sub sp, #16 + 8001628: af00 add r7, sp, #0 + 800162a: 6078 str r0, [r7, #4] + 800162c: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 800162e: 687b ldr r3, [r7, #4] + 8001630: 2b00 cmp r3, #0 + 8001632: d101 bne.n 8001638 + { + return HAL_ERROR; + 8001634: 2301 movs r3, #1 + 8001636: e11a b.n 800186e + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8001638: 4b8f ldr r3, [pc, #572] @ (8001878 ) + 800163a: 681b ldr r3, [r3, #0] + 800163c: f003 0301 and.w r3, r3, #1 + 8001640: 683a ldr r2, [r7, #0] + 8001642: 429a cmp r2, r3 + 8001644: d919 bls.n 800167a + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001646: 683b ldr r3, [r7, #0] + 8001648: 2b01 cmp r3, #1 + 800164a: d105 bne.n 8001658 + 800164c: 4b8a ldr r3, [pc, #552] @ (8001878 ) + 800164e: 681b ldr r3, [r3, #0] + 8001650: 4a89 ldr r2, [pc, #548] @ (8001878 ) + 8001652: f043 0304 orr.w r3, r3, #4 + 8001656: 6013 str r3, [r2, #0] + 8001658: 4b87 ldr r3, [pc, #540] @ (8001878 ) + 800165a: 681b ldr r3, [r3, #0] + 800165c: f023 0201 bic.w r2, r3, #1 + 8001660: 4985 ldr r1, [pc, #532] @ (8001878 ) + 8001662: 683b ldr r3, [r7, #0] + 8001664: 4313 orrs r3, r2 + 8001666: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001668: 4b83 ldr r3, [pc, #524] @ (8001878 ) + 800166a: 681b ldr r3, [r3, #0] + 800166c: f003 0301 and.w r3, r3, #1 + 8001670: 683a ldr r2, [r7, #0] + 8001672: 429a cmp r2, r3 + 8001674: d001 beq.n 800167a + { + return HAL_ERROR; + 8001676: 2301 movs r3, #1 + 8001678: e0f9 b.n 800186e + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800167a: 687b ldr r3, [r7, #4] + 800167c: 681b ldr r3, [r3, #0] + 800167e: f003 0302 and.w r3, r3, #2 + 8001682: 2b00 cmp r3, #0 + 8001684: d008 beq.n 8001698 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8001686: 4b7d ldr r3, [pc, #500] @ (800187c ) + 8001688: 689b ldr r3, [r3, #8] + 800168a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800168e: 687b ldr r3, [r7, #4] + 8001690: 689b ldr r3, [r3, #8] + 8001692: 497a ldr r1, [pc, #488] @ (800187c ) + 8001694: 4313 orrs r3, r2 + 8001696: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8001698: 687b ldr r3, [r7, #4] + 800169a: 681b ldr r3, [r3, #0] + 800169c: f003 0301 and.w r3, r3, #1 + 80016a0: 2b00 cmp r3, #0 + 80016a2: f000 808e beq.w 80017c2 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80016a6: 687b ldr r3, [r7, #4] + 80016a8: 685b ldr r3, [r3, #4] + 80016aa: 2b02 cmp r3, #2 + 80016ac: d107 bne.n 80016be + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 80016ae: 4b73 ldr r3, [pc, #460] @ (800187c ) + 80016b0: 681b ldr r3, [r3, #0] + 80016b2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80016b6: 2b00 cmp r3, #0 + 80016b8: d121 bne.n 80016fe + { + return HAL_ERROR; + 80016ba: 2301 movs r3, #1 + 80016bc: e0d7 b.n 800186e + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80016be: 687b ldr r3, [r7, #4] + 80016c0: 685b ldr r3, [r3, #4] + 80016c2: 2b03 cmp r3, #3 + 80016c4: d107 bne.n 80016d6 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 80016c6: 4b6d ldr r3, [pc, #436] @ (800187c ) + 80016c8: 681b ldr r3, [r3, #0] + 80016ca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80016ce: 2b00 cmp r3, #0 + 80016d0: d115 bne.n 80016fe + { + return HAL_ERROR; + 80016d2: 2301 movs r3, #1 + 80016d4: e0cb b.n 800186e + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 80016d6: 687b ldr r3, [r7, #4] + 80016d8: 685b ldr r3, [r3, #4] + 80016da: 2b01 cmp r3, #1 + 80016dc: d107 bne.n 80016ee + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80016de: 4b67 ldr r3, [pc, #412] @ (800187c ) + 80016e0: 681b ldr r3, [r3, #0] + 80016e2: f003 0302 and.w r3, r3, #2 + 80016e6: 2b00 cmp r3, #0 + 80016e8: d109 bne.n 80016fe + { + return HAL_ERROR; + 80016ea: 2301 movs r3, #1 + 80016ec: e0bf b.n 800186e + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80016ee: 4b63 ldr r3, [pc, #396] @ (800187c ) + 80016f0: 681b ldr r3, [r3, #0] + 80016f2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80016f6: 2b00 cmp r3, #0 + 80016f8: d101 bne.n 80016fe + { + return HAL_ERROR; + 80016fa: 2301 movs r3, #1 + 80016fc: e0b7 b.n 800186e + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 80016fe: 4b5f ldr r3, [pc, #380] @ (800187c ) + 8001700: 689b ldr r3, [r3, #8] + 8001702: f023 0203 bic.w r2, r3, #3 + 8001706: 687b ldr r3, [r7, #4] + 8001708: 685b ldr r3, [r3, #4] + 800170a: 495c ldr r1, [pc, #368] @ (800187c ) + 800170c: 4313 orrs r3, r2 + 800170e: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001710: f7ff f9a0 bl 8000a54 + 8001714: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001716: 687b ldr r3, [r7, #4] + 8001718: 685b ldr r3, [r3, #4] + 800171a: 2b02 cmp r3, #2 + 800171c: d112 bne.n 8001744 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 800171e: e00a b.n 8001736 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001720: f7ff f998 bl 8000a54 + 8001724: 4602 mov r2, r0 + 8001726: 68fb ldr r3, [r7, #12] + 8001728: 1ad3 subs r3, r2, r3 + 800172a: f241 3288 movw r2, #5000 @ 0x1388 + 800172e: 4293 cmp r3, r2 + 8001730: d901 bls.n 8001736 + { + return HAL_TIMEOUT; + 8001732: 2303 movs r3, #3 + 8001734: e09b b.n 800186e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001736: 4b51 ldr r3, [pc, #324] @ (800187c ) + 8001738: 689b ldr r3, [r3, #8] + 800173a: f003 030c and.w r3, r3, #12 + 800173e: 2b08 cmp r3, #8 + 8001740: d1ee bne.n 8001720 + 8001742: e03e b.n 80017c2 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001744: 687b ldr r3, [r7, #4] + 8001746: 685b ldr r3, [r3, #4] + 8001748: 2b03 cmp r3, #3 + 800174a: d112 bne.n 8001772 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 800174c: e00a b.n 8001764 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 800174e: f7ff f981 bl 8000a54 + 8001752: 4602 mov r2, r0 + 8001754: 68fb ldr r3, [r7, #12] + 8001756: 1ad3 subs r3, r2, r3 + 8001758: f241 3288 movw r2, #5000 @ 0x1388 + 800175c: 4293 cmp r3, r2 + 800175e: d901 bls.n 8001764 + { + return HAL_TIMEOUT; + 8001760: 2303 movs r3, #3 + 8001762: e084 b.n 800186e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001764: 4b45 ldr r3, [pc, #276] @ (800187c ) + 8001766: 689b ldr r3, [r3, #8] + 8001768: f003 030c and.w r3, r3, #12 + 800176c: 2b0c cmp r3, #12 + 800176e: d1ee bne.n 800174e + 8001770: e027 b.n 80017c2 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001772: 687b ldr r3, [r7, #4] + 8001774: 685b ldr r3, [r3, #4] + 8001776: 2b01 cmp r3, #1 + 8001778: d11d bne.n 80017b6 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 800177a: e00a b.n 8001792 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 800177c: f7ff f96a bl 8000a54 + 8001780: 4602 mov r2, r0 + 8001782: 68fb ldr r3, [r7, #12] + 8001784: 1ad3 subs r3, r2, r3 + 8001786: f241 3288 movw r2, #5000 @ 0x1388 + 800178a: 4293 cmp r3, r2 + 800178c: d901 bls.n 8001792 + { + return HAL_TIMEOUT; + 800178e: 2303 movs r3, #3 + 8001790: e06d b.n 800186e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001792: 4b3a ldr r3, [pc, #232] @ (800187c ) + 8001794: 689b ldr r3, [r3, #8] + 8001796: f003 030c and.w r3, r3, #12 + 800179a: 2b04 cmp r3, #4 + 800179c: d1ee bne.n 800177c + 800179e: e010 b.n 80017c2 + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80017a0: f7ff f958 bl 8000a54 + 80017a4: 4602 mov r2, r0 + 80017a6: 68fb ldr r3, [r7, #12] + 80017a8: 1ad3 subs r3, r2, r3 + 80017aa: f241 3288 movw r2, #5000 @ 0x1388 + 80017ae: 4293 cmp r3, r2 + 80017b0: d901 bls.n 80017b6 + { + return HAL_TIMEOUT; + 80017b2: 2303 movs r3, #3 + 80017b4: e05b b.n 800186e + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 80017b6: 4b31 ldr r3, [pc, #196] @ (800187c ) + 80017b8: 689b ldr r3, [r3, #8] + 80017ba: f003 030c and.w r3, r3, #12 + 80017be: 2b00 cmp r3, #0 + 80017c0: d1ee bne.n 80017a0 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 80017c2: 4b2d ldr r3, [pc, #180] @ (8001878 ) + 80017c4: 681b ldr r3, [r3, #0] + 80017c6: f003 0301 and.w r3, r3, #1 + 80017ca: 683a ldr r2, [r7, #0] + 80017cc: 429a cmp r2, r3 + 80017ce: d219 bcs.n 8001804 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80017d0: 683b ldr r3, [r7, #0] + 80017d2: 2b01 cmp r3, #1 + 80017d4: d105 bne.n 80017e2 + 80017d6: 4b28 ldr r3, [pc, #160] @ (8001878 ) + 80017d8: 681b ldr r3, [r3, #0] + 80017da: 4a27 ldr r2, [pc, #156] @ (8001878 ) + 80017dc: f043 0304 orr.w r3, r3, #4 + 80017e0: 6013 str r3, [r2, #0] + 80017e2: 4b25 ldr r3, [pc, #148] @ (8001878 ) + 80017e4: 681b ldr r3, [r3, #0] + 80017e6: f023 0201 bic.w r2, r3, #1 + 80017ea: 4923 ldr r1, [pc, #140] @ (8001878 ) + 80017ec: 683b ldr r3, [r7, #0] + 80017ee: 4313 orrs r3, r2 + 80017f0: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 80017f2: 4b21 ldr r3, [pc, #132] @ (8001878 ) + 80017f4: 681b ldr r3, [r3, #0] + 80017f6: f003 0301 and.w r3, r3, #1 + 80017fa: 683a ldr r2, [r7, #0] + 80017fc: 429a cmp r2, r3 + 80017fe: d001 beq.n 8001804 + { + return HAL_ERROR; + 8001800: 2301 movs r3, #1 + 8001802: e034 b.n 800186e + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001804: 687b ldr r3, [r7, #4] + 8001806: 681b ldr r3, [r3, #0] + 8001808: f003 0304 and.w r3, r3, #4 + 800180c: 2b00 cmp r3, #0 + 800180e: d008 beq.n 8001822 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8001810: 4b1a ldr r3, [pc, #104] @ (800187c ) + 8001812: 689b ldr r3, [r3, #8] + 8001814: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001818: 687b ldr r3, [r7, #4] + 800181a: 68db ldr r3, [r3, #12] + 800181c: 4917 ldr r1, [pc, #92] @ (800187c ) + 800181e: 4313 orrs r3, r2 + 8001820: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001822: 687b ldr r3, [r7, #4] + 8001824: 681b ldr r3, [r3, #0] + 8001826: f003 0308 and.w r3, r3, #8 + 800182a: 2b00 cmp r3, #0 + 800182c: d009 beq.n 8001842 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 800182e: 4b13 ldr r3, [pc, #76] @ (800187c ) + 8001830: 689b ldr r3, [r3, #8] + 8001832: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001836: 687b ldr r3, [r7, #4] + 8001838: 691b ldr r3, [r3, #16] + 800183a: 00db lsls r3, r3, #3 + 800183c: 490f ldr r1, [pc, #60] @ (800187c ) + 800183e: 4313 orrs r3, r2 + 8001840: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8001842: f000 f823 bl 800188c + 8001846: 4602 mov r2, r0 + 8001848: 4b0c ldr r3, [pc, #48] @ (800187c ) + 800184a: 689b ldr r3, [r3, #8] + 800184c: 091b lsrs r3, r3, #4 + 800184e: f003 030f and.w r3, r3, #15 + 8001852: 490b ldr r1, [pc, #44] @ (8001880 ) + 8001854: 5ccb ldrb r3, [r1, r3] + 8001856: fa22 f303 lsr.w r3, r2, r3 + 800185a: 4a0a ldr r2, [pc, #40] @ (8001884 ) + 800185c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 800185e: 4b0a ldr r3, [pc, #40] @ (8001888 ) + 8001860: 681b ldr r3, [r3, #0] + 8001862: 4618 mov r0, r3 + 8001864: f7ff f8aa bl 80009bc + 8001868: 4603 mov r3, r0 + 800186a: 72fb strb r3, [r7, #11] + + return status; + 800186c: 7afb ldrb r3, [r7, #11] +} + 800186e: 4618 mov r0, r3 + 8001870: 3710 adds r7, #16 + 8001872: 46bd mov sp, r7 + 8001874: bd80 pop {r7, pc} + 8001876: bf00 nop + 8001878: 40023c00 .word 0x40023c00 + 800187c: 40023800 .word 0x40023800 + 8001880: 08002098 .word 0x08002098 + 8001884: 20000000 .word 0x20000000 + 8001888: 20000004 .word 0x20000004 + +0800188c : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 800188c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001890: b08e sub sp, #56 @ 0x38 + 8001892: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 8001894: 4b58 ldr r3, [pc, #352] @ (80019f8 ) + 8001896: 689b ldr r3, [r3, #8] + 8001898: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 800189a: 6afb ldr r3, [r7, #44] @ 0x2c + 800189c: f003 030c and.w r3, r3, #12 + 80018a0: 2b0c cmp r3, #12 + 80018a2: d00d beq.n 80018c0 + 80018a4: 2b0c cmp r3, #12 + 80018a6: f200 8092 bhi.w 80019ce + 80018aa: 2b04 cmp r3, #4 + 80018ac: d002 beq.n 80018b4 + 80018ae: 2b08 cmp r3, #8 + 80018b0: d003 beq.n 80018ba + 80018b2: e08c b.n 80019ce + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 80018b4: 4b51 ldr r3, [pc, #324] @ (80019fc ) + 80018b6: 633b str r3, [r7, #48] @ 0x30 + break; + 80018b8: e097 b.n 80019ea + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 80018ba: 4b51 ldr r3, [pc, #324] @ (8001a00 ) + 80018bc: 633b str r3, [r7, #48] @ 0x30 + break; + 80018be: e094 b.n 80019ea + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 80018c0: 6afb ldr r3, [r7, #44] @ 0x2c + 80018c2: 0c9b lsrs r3, r3, #18 + 80018c4: f003 020f and.w r2, r3, #15 + 80018c8: 4b4e ldr r3, [pc, #312] @ (8001a04 ) + 80018ca: 5c9b ldrb r3, [r3, r2] + 80018cc: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 80018ce: 6afb ldr r3, [r7, #44] @ 0x2c + 80018d0: 0d9b lsrs r3, r3, #22 + 80018d2: f003 0303 and.w r3, r3, #3 + 80018d6: 3301 adds r3, #1 + 80018d8: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 80018da: 4b47 ldr r3, [pc, #284] @ (80019f8 ) + 80018dc: 689b ldr r3, [r3, #8] + 80018de: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80018e2: 2b00 cmp r3, #0 + 80018e4: d021 beq.n 800192a + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 80018e6: 6abb ldr r3, [r7, #40] @ 0x28 + 80018e8: 2200 movs r2, #0 + 80018ea: 61bb str r3, [r7, #24] + 80018ec: 61fa str r2, [r7, #28] + 80018ee: 4b44 ldr r3, [pc, #272] @ (8001a00 ) + 80018f0: e9d7 8906 ldrd r8, r9, [r7, #24] + 80018f4: 464a mov r2, r9 + 80018f6: fb03 f202 mul.w r2, r3, r2 + 80018fa: 2300 movs r3, #0 + 80018fc: 4644 mov r4, r8 + 80018fe: fb04 f303 mul.w r3, r4, r3 + 8001902: 4413 add r3, r2 + 8001904: 4a3e ldr r2, [pc, #248] @ (8001a00 ) + 8001906: 4644 mov r4, r8 + 8001908: fba4 0102 umull r0, r1, r4, r2 + 800190c: 440b add r3, r1 + 800190e: 4619 mov r1, r3 + 8001910: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001912: 2200 movs r2, #0 + 8001914: 613b str r3, [r7, #16] + 8001916: 617a str r2, [r7, #20] + 8001918: e9d7 2304 ldrd r2, r3, [r7, #16] + 800191c: f7fe fc2e bl 800017c <__aeabi_uldivmod> + 8001920: 4602 mov r2, r0 + 8001922: 460b mov r3, r1 + 8001924: 4613 mov r3, r2 + 8001926: 637b str r3, [r7, #52] @ 0x34 + 8001928: e04e b.n 80019c8 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 800192a: 6abb ldr r3, [r7, #40] @ 0x28 + 800192c: 2200 movs r2, #0 + 800192e: 469a mov sl, r3 + 8001930: 4693 mov fp, r2 + 8001932: 4652 mov r2, sl + 8001934: 465b mov r3, fp + 8001936: f04f 0000 mov.w r0, #0 + 800193a: f04f 0100 mov.w r1, #0 + 800193e: 0159 lsls r1, r3, #5 + 8001940: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001944: 0150 lsls r0, r2, #5 + 8001946: 4602 mov r2, r0 + 8001948: 460b mov r3, r1 + 800194a: ebb2 080a subs.w r8, r2, sl + 800194e: eb63 090b sbc.w r9, r3, fp + 8001952: f04f 0200 mov.w r2, #0 + 8001956: f04f 0300 mov.w r3, #0 + 800195a: ea4f 1389 mov.w r3, r9, lsl #6 + 800195e: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001962: ea4f 1288 mov.w r2, r8, lsl #6 + 8001966: ebb2 0408 subs.w r4, r2, r8 + 800196a: eb63 0509 sbc.w r5, r3, r9 + 800196e: f04f 0200 mov.w r2, #0 + 8001972: f04f 0300 mov.w r3, #0 + 8001976: 00eb lsls r3, r5, #3 + 8001978: ea43 7354 orr.w r3, r3, r4, lsr #29 + 800197c: 00e2 lsls r2, r4, #3 + 800197e: 4614 mov r4, r2 + 8001980: 461d mov r5, r3 + 8001982: eb14 030a adds.w r3, r4, sl + 8001986: 603b str r3, [r7, #0] + 8001988: eb45 030b adc.w r3, r5, fp + 800198c: 607b str r3, [r7, #4] + 800198e: f04f 0200 mov.w r2, #0 + 8001992: f04f 0300 mov.w r3, #0 + 8001996: e9d7 4500 ldrd r4, r5, [r7] + 800199a: 4629 mov r1, r5 + 800199c: 028b lsls r3, r1, #10 + 800199e: 4620 mov r0, r4 + 80019a0: 4629 mov r1, r5 + 80019a2: 4604 mov r4, r0 + 80019a4: ea43 5394 orr.w r3, r3, r4, lsr #22 + 80019a8: 4601 mov r1, r0 + 80019aa: 028a lsls r2, r1, #10 + 80019ac: 4610 mov r0, r2 + 80019ae: 4619 mov r1, r3 + 80019b0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80019b2: 2200 movs r2, #0 + 80019b4: 60bb str r3, [r7, #8] + 80019b6: 60fa str r2, [r7, #12] + 80019b8: e9d7 2302 ldrd r2, r3, [r7, #8] + 80019bc: f7fe fbde bl 800017c <__aeabi_uldivmod> + 80019c0: 4602 mov r2, r0 + 80019c2: 460b mov r3, r1 + 80019c4: 4613 mov r3, r2 + 80019c6: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 80019c8: 6b7b ldr r3, [r7, #52] @ 0x34 + 80019ca: 633b str r3, [r7, #48] @ 0x30 + break; + 80019cc: e00d b.n 80019ea + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 80019ce: 4b0a ldr r3, [pc, #40] @ (80019f8 ) + 80019d0: 685b ldr r3, [r3, #4] + 80019d2: 0b5b lsrs r3, r3, #13 + 80019d4: f003 0307 and.w r3, r3, #7 + 80019d8: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 80019da: 6a3b ldr r3, [r7, #32] + 80019dc: 3301 adds r3, #1 + 80019de: f44f 4200 mov.w r2, #32768 @ 0x8000 + 80019e2: fa02 f303 lsl.w r3, r2, r3 + 80019e6: 633b str r3, [r7, #48] @ 0x30 + break; + 80019e8: bf00 nop + } + } + return sysclockfreq; + 80019ea: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 80019ec: 4618 mov r0, r3 + 80019ee: 3738 adds r7, #56 @ 0x38 + 80019f0: 46bd mov sp, r7 + 80019f2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80019f6: bf00 nop + 80019f8: 40023800 .word 0x40023800 + 80019fc: 00f42400 .word 0x00f42400 + 8001a00: 016e3600 .word 0x016e3600 + 8001a04: 0800208c .word 0x0800208c + +08001a08 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 8001a08: b480 push {r7} + 8001a0a: b087 sub sp, #28 + 8001a0c: af00 add r7, sp, #0 + 8001a0e: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8001a10: 2300 movs r3, #0 + 8001a12: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 8001a14: 4b29 ldr r3, [pc, #164] @ (8001abc ) + 8001a16: 689b ldr r3, [r3, #8] + 8001a18: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001a1c: 2b00 cmp r3, #0 + 8001a1e: d12c bne.n 8001a7a + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 8001a20: 4b26 ldr r3, [pc, #152] @ (8001abc ) + 8001a22: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a24: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001a28: 2b00 cmp r3, #0 + 8001a2a: d005 beq.n 8001a38 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001a2c: 4b24 ldr r3, [pc, #144] @ (8001ac0 ) + 8001a2e: 681b ldr r3, [r3, #0] + 8001a30: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001a34: 617b str r3, [r7, #20] + 8001a36: e016 b.n 8001a66 + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001a38: 4b20 ldr r3, [pc, #128] @ (8001abc ) + 8001a3a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a3c: 4a1f ldr r2, [pc, #124] @ (8001abc ) + 8001a3e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001a42: 6253 str r3, [r2, #36] @ 0x24 + 8001a44: 4b1d ldr r3, [pc, #116] @ (8001abc ) + 8001a46: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a48: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001a4c: 60fb str r3, [r7, #12] + 8001a4e: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001a50: 4b1b ldr r3, [pc, #108] @ (8001ac0 ) + 8001a52: 681b ldr r3, [r3, #0] + 8001a54: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001a58: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001a5a: 4b18 ldr r3, [pc, #96] @ (8001abc ) + 8001a5c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a5e: 4a17 ldr r2, [pc, #92] @ (8001abc ) + 8001a60: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001a64: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001a66: 697b ldr r3, [r7, #20] + 8001a68: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001a6c: d105 bne.n 8001a7a + 8001a6e: 687b ldr r3, [r7, #4] + 8001a70: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001a74: d101 bne.n 8001a7a + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001a76: 2301 movs r3, #1 + 8001a78: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001a7a: 693b ldr r3, [r7, #16] + 8001a7c: 2b01 cmp r3, #1 + 8001a7e: d105 bne.n 8001a8c + 8001a80: 4b10 ldr r3, [pc, #64] @ (8001ac4 ) + 8001a82: 681b ldr r3, [r3, #0] + 8001a84: 4a0f ldr r2, [pc, #60] @ (8001ac4 ) + 8001a86: f043 0304 orr.w r3, r3, #4 + 8001a8a: 6013 str r3, [r2, #0] + 8001a8c: 4b0d ldr r3, [pc, #52] @ (8001ac4 ) + 8001a8e: 681b ldr r3, [r3, #0] + 8001a90: f023 0201 bic.w r2, r3, #1 + 8001a94: 490b ldr r1, [pc, #44] @ (8001ac4 ) + 8001a96: 693b ldr r3, [r7, #16] + 8001a98: 4313 orrs r3, r2 + 8001a9a: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001a9c: 4b09 ldr r3, [pc, #36] @ (8001ac4 ) + 8001a9e: 681b ldr r3, [r3, #0] + 8001aa0: f003 0301 and.w r3, r3, #1 + 8001aa4: 693a ldr r2, [r7, #16] + 8001aa6: 429a cmp r2, r3 + 8001aa8: d001 beq.n 8001aae + { + return HAL_ERROR; + 8001aaa: 2301 movs r3, #1 + 8001aac: e000 b.n 8001ab0 + } + + return HAL_OK; + 8001aae: 2300 movs r3, #0 +} + 8001ab0: 4618 mov r0, r3 + 8001ab2: 371c adds r7, #28 + 8001ab4: 46bd mov sp, r7 + 8001ab6: bc80 pop {r7} + 8001ab8: 4770 bx lr + 8001aba: bf00 nop + 8001abc: 40023800 .word 0x40023800 + 8001ac0: 40007000 .word 0x40007000 + 8001ac4: 40023c00 .word 0x40023c00 + +08001ac8 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001ac8: b580 push {r7, lr} + 8001aca: b082 sub sp, #8 + 8001acc: af00 add r7, sp, #0 + 8001ace: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001ad0: 687b ldr r3, [r7, #4] + 8001ad2: 2b00 cmp r3, #0 + 8001ad4: d101 bne.n 8001ada + { + return HAL_ERROR; + 8001ad6: 2301 movs r3, #1 + 8001ad8: e07b b.n 8001bd2 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001ada: 687b ldr r3, [r7, #4] + 8001adc: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ade: 2b00 cmp r3, #0 + 8001ae0: d108 bne.n 8001af4 + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001ae2: 687b ldr r3, [r7, #4] + 8001ae4: 685b ldr r3, [r3, #4] + 8001ae6: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001aea: d009 beq.n 8001b00 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001aec: 687b ldr r3, [r7, #4] + 8001aee: 2200 movs r2, #0 + 8001af0: 61da str r2, [r3, #28] + 8001af2: e005 b.n 8001b00 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001af4: 687b ldr r3, [r7, #4] + 8001af6: 2200 movs r2, #0 + 8001af8: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001afa: 687b ldr r3, [r7, #4] + 8001afc: 2200 movs r2, #0 + 8001afe: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001b00: 687b ldr r3, [r7, #4] + 8001b02: 2200 movs r2, #0 + 8001b04: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001b06: 687b ldr r3, [r7, #4] + 8001b08: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001b0c: b2db uxtb r3, r3 + 8001b0e: 2b00 cmp r3, #0 + 8001b10: d106 bne.n 8001b20 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001b12: 687b ldr r3, [r7, #4] + 8001b14: 2200 movs r2, #0 + 8001b16: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001b1a: 6878 ldr r0, [r7, #4] + 8001b1c: f7fe fe08 bl 8000730 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001b20: 687b ldr r3, [r7, #4] + 8001b22: 2202 movs r2, #2 + 8001b24: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001b28: 687b ldr r3, [r7, #4] + 8001b2a: 681b ldr r3, [r3, #0] + 8001b2c: 681a ldr r2, [r3, #0] + 8001b2e: 687b ldr r3, [r7, #4] + 8001b30: 681b ldr r3, [r3, #0] + 8001b32: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001b36: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001b38: 687b ldr r3, [r7, #4] + 8001b3a: 685b ldr r3, [r3, #4] + 8001b3c: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001b40: 687b ldr r3, [r7, #4] + 8001b42: 689b ldr r3, [r3, #8] + 8001b44: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001b48: 431a orrs r2, r3 + 8001b4a: 687b ldr r3, [r7, #4] + 8001b4c: 68db ldr r3, [r3, #12] + 8001b4e: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001b52: 431a orrs r2, r3 + 8001b54: 687b ldr r3, [r7, #4] + 8001b56: 691b ldr r3, [r3, #16] + 8001b58: f003 0302 and.w r3, r3, #2 + 8001b5c: 431a orrs r2, r3 + 8001b5e: 687b ldr r3, [r7, #4] + 8001b60: 695b ldr r3, [r3, #20] + 8001b62: f003 0301 and.w r3, r3, #1 + 8001b66: 431a orrs r2, r3 + 8001b68: 687b ldr r3, [r7, #4] + 8001b6a: 699b ldr r3, [r3, #24] + 8001b6c: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001b70: 431a orrs r2, r3 + 8001b72: 687b ldr r3, [r7, #4] + 8001b74: 69db ldr r3, [r3, #28] + 8001b76: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001b7a: 431a orrs r2, r3 + 8001b7c: 687b ldr r3, [r7, #4] + 8001b7e: 6a1b ldr r3, [r3, #32] + 8001b80: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001b84: ea42 0103 orr.w r1, r2, r3 + 8001b88: 687b ldr r3, [r7, #4] + 8001b8a: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001b8c: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001b90: 687b ldr r3, [r7, #4] + 8001b92: 681b ldr r3, [r3, #0] + 8001b94: 430a orrs r2, r1 + 8001b96: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8001b98: 687b ldr r3, [r7, #4] + 8001b9a: 699b ldr r3, [r3, #24] + 8001b9c: 0c1b lsrs r3, r3, #16 + 8001b9e: f003 0104 and.w r1, r3, #4 + 8001ba2: 687b ldr r3, [r7, #4] + 8001ba4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ba6: f003 0210 and.w r2, r3, #16 + 8001baa: 687b ldr r3, [r7, #4] + 8001bac: 681b ldr r3, [r3, #0] + 8001bae: 430a orrs r2, r1 + 8001bb0: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8001bb2: 687b ldr r3, [r7, #4] + 8001bb4: 681b ldr r3, [r3, #0] + 8001bb6: 69da ldr r2, [r3, #28] + 8001bb8: 687b ldr r3, [r7, #4] + 8001bba: 681b ldr r3, [r3, #0] + 8001bbc: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001bc0: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001bc2: 687b ldr r3, [r7, #4] + 8001bc4: 2200 movs r2, #0 + 8001bc6: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8001bc8: 687b ldr r3, [r7, #4] + 8001bca: 2201 movs r2, #1 + 8001bcc: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8001bd0: 2300 movs r3, #0 +} + 8001bd2: 4618 mov r0, r3 + 8001bd4: 3708 adds r7, #8 + 8001bd6: 46bd mov sp, r7 + 8001bd8: bd80 pop {r7, pc} + +08001bda : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8001bda: b580 push {r7, lr} + 8001bdc: b088 sub sp, #32 + 8001bde: af00 add r7, sp, #0 + 8001be0: 60f8 str r0, [r7, #12] + 8001be2: 60b9 str r1, [r7, #8] + 8001be4: 603b str r3, [r7, #0] + 8001be6: 4613 mov r3, r2 + 8001be8: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001bea: f7fe ff33 bl 8000a54 + 8001bee: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8001bf0: 88fb ldrh r3, [r7, #6] + 8001bf2: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8001bf4: 68fb ldr r3, [r7, #12] + 8001bf6: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001bfa: b2db uxtb r3, r3 + 8001bfc: 2b01 cmp r3, #1 + 8001bfe: d001 beq.n 8001c04 + { + return HAL_BUSY; + 8001c00: 2302 movs r3, #2 + 8001c02: e12a b.n 8001e5a + } + + if ((pData == NULL) || (Size == 0U)) + 8001c04: 68bb ldr r3, [r7, #8] + 8001c06: 2b00 cmp r3, #0 + 8001c08: d002 beq.n 8001c10 + 8001c0a: 88fb ldrh r3, [r7, #6] + 8001c0c: 2b00 cmp r3, #0 + 8001c0e: d101 bne.n 8001c14 + { + return HAL_ERROR; + 8001c10: 2301 movs r3, #1 + 8001c12: e122 b.n 8001e5a + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 8001c14: 68fb ldr r3, [r7, #12] + 8001c16: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001c1a: 2b01 cmp r3, #1 + 8001c1c: d101 bne.n 8001c22 + 8001c1e: 2302 movs r3, #2 + 8001c20: e11b b.n 8001e5a + 8001c22: 68fb ldr r3, [r7, #12] + 8001c24: 2201 movs r2, #1 + 8001c26: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8001c2a: 68fb ldr r3, [r7, #12] + 8001c2c: 2203 movs r2, #3 + 8001c2e: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001c32: 68fb ldr r3, [r7, #12] + 8001c34: 2200 movs r2, #0 + 8001c36: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8001c38: 68fb ldr r3, [r7, #12] + 8001c3a: 68ba ldr r2, [r7, #8] + 8001c3c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 8001c3e: 68fb ldr r3, [r7, #12] + 8001c40: 88fa ldrh r2, [r7, #6] + 8001c42: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8001c44: 68fb ldr r3, [r7, #12] + 8001c46: 88fa ldrh r2, [r7, #6] + 8001c48: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8001c4a: 68fb ldr r3, [r7, #12] + 8001c4c: 2200 movs r2, #0 + 8001c4e: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 8001c50: 68fb ldr r3, [r7, #12] + 8001c52: 2200 movs r2, #0 + 8001c54: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8001c56: 68fb ldr r3, [r7, #12] + 8001c58: 2200 movs r2, #0 + 8001c5a: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 8001c5c: 68fb ldr r3, [r7, #12] + 8001c5e: 2200 movs r2, #0 + 8001c60: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8001c62: 68fb ldr r3, [r7, #12] + 8001c64: 2200 movs r2, #0 + 8001c66: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8001c68: 68fb ldr r3, [r7, #12] + 8001c6a: 689b ldr r3, [r3, #8] + 8001c6c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001c70: d10f bne.n 8001c92 + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8001c72: 68fb ldr r3, [r7, #12] + 8001c74: 681b ldr r3, [r3, #0] + 8001c76: 681a ldr r2, [r3, #0] + 8001c78: 68fb ldr r3, [r7, #12] + 8001c7a: 681b ldr r3, [r3, #0] + 8001c7c: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001c80: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8001c82: 68fb ldr r3, [r7, #12] + 8001c84: 681b ldr r3, [r3, #0] + 8001c86: 681a ldr r2, [r3, #0] + 8001c88: 68fb ldr r3, [r7, #12] + 8001c8a: 681b ldr r3, [r3, #0] + 8001c8c: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8001c90: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8001c92: 68fb ldr r3, [r7, #12] + 8001c94: 681b ldr r3, [r3, #0] + 8001c96: 681b ldr r3, [r3, #0] + 8001c98: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001c9c: 2b40 cmp r3, #64 @ 0x40 + 8001c9e: d007 beq.n 8001cb0 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8001ca0: 68fb ldr r3, [r7, #12] + 8001ca2: 681b ldr r3, [r3, #0] + 8001ca4: 681a ldr r2, [r3, #0] + 8001ca6: 68fb ldr r3, [r7, #12] + 8001ca8: 681b ldr r3, [r3, #0] + 8001caa: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8001cae: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8001cb0: 68fb ldr r3, [r7, #12] + 8001cb2: 68db ldr r3, [r3, #12] + 8001cb4: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8001cb8: d152 bne.n 8001d60 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001cba: 68fb ldr r3, [r7, #12] + 8001cbc: 685b ldr r3, [r3, #4] + 8001cbe: 2b00 cmp r3, #0 + 8001cc0: d002 beq.n 8001cc8 + 8001cc2: 8b7b ldrh r3, [r7, #26] + 8001cc4: 2b01 cmp r3, #1 + 8001cc6: d145 bne.n 8001d54 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001cc8: 68fb ldr r3, [r7, #12] + 8001cca: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ccc: 881a ldrh r2, [r3, #0] + 8001cce: 68fb ldr r3, [r7, #12] + 8001cd0: 681b ldr r3, [r3, #0] + 8001cd2: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001cd4: 68fb ldr r3, [r7, #12] + 8001cd6: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001cd8: 1c9a adds r2, r3, #2 + 8001cda: 68fb ldr r3, [r7, #12] + 8001cdc: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001cde: 68fb ldr r3, [r7, #12] + 8001ce0: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001ce2: b29b uxth r3, r3 + 8001ce4: 3b01 subs r3, #1 + 8001ce6: b29a uxth r2, r3 + 8001ce8: 68fb ldr r3, [r7, #12] + 8001cea: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 8001cec: e032 b.n 8001d54 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001cee: 68fb ldr r3, [r7, #12] + 8001cf0: 681b ldr r3, [r3, #0] + 8001cf2: 689b ldr r3, [r3, #8] + 8001cf4: f003 0302 and.w r3, r3, #2 + 8001cf8: 2b02 cmp r3, #2 + 8001cfa: d112 bne.n 8001d22 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001cfc: 68fb ldr r3, [r7, #12] + 8001cfe: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d00: 881a ldrh r2, [r3, #0] + 8001d02: 68fb ldr r3, [r7, #12] + 8001d04: 681b ldr r3, [r3, #0] + 8001d06: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001d08: 68fb ldr r3, [r7, #12] + 8001d0a: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d0c: 1c9a adds r2, r3, #2 + 8001d0e: 68fb ldr r3, [r7, #12] + 8001d10: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001d12: 68fb ldr r3, [r7, #12] + 8001d14: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d16: b29b uxth r3, r3 + 8001d18: 3b01 subs r3, #1 + 8001d1a: b29a uxth r2, r3 + 8001d1c: 68fb ldr r3, [r7, #12] + 8001d1e: 86da strh r2, [r3, #54] @ 0x36 + 8001d20: e018 b.n 8001d54 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001d22: f7fe fe97 bl 8000a54 + 8001d26: 4602 mov r2, r0 + 8001d28: 69fb ldr r3, [r7, #28] + 8001d2a: 1ad3 subs r3, r2, r3 + 8001d2c: 683a ldr r2, [r7, #0] + 8001d2e: 429a cmp r2, r3 + 8001d30: d803 bhi.n 8001d3a + 8001d32: 683b ldr r3, [r7, #0] + 8001d34: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001d38: d102 bne.n 8001d40 + 8001d3a: 683b ldr r3, [r7, #0] + 8001d3c: 2b00 cmp r3, #0 + 8001d3e: d109 bne.n 8001d54 + { + hspi->State = HAL_SPI_STATE_READY; + 8001d40: 68fb ldr r3, [r7, #12] + 8001d42: 2201 movs r2, #1 + 8001d44: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001d48: 68fb ldr r3, [r7, #12] + 8001d4a: 2200 movs r2, #0 + 8001d4c: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001d50: 2303 movs r3, #3 + 8001d52: e082 b.n 8001e5a + while (hspi->TxXferCount > 0U) + 8001d54: 68fb ldr r3, [r7, #12] + 8001d56: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d58: b29b uxth r3, r3 + 8001d5a: 2b00 cmp r3, #0 + 8001d5c: d1c7 bne.n 8001cee + 8001d5e: e053 b.n 8001e08 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001d60: 68fb ldr r3, [r7, #12] + 8001d62: 685b ldr r3, [r3, #4] + 8001d64: 2b00 cmp r3, #0 + 8001d66: d002 beq.n 8001d6e + 8001d68: 8b7b ldrh r3, [r7, #26] + 8001d6a: 2b01 cmp r3, #1 + 8001d6c: d147 bne.n 8001dfe + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001d6e: 68fb ldr r3, [r7, #12] + 8001d70: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001d72: 68fb ldr r3, [r7, #12] + 8001d74: 681b ldr r3, [r3, #0] + 8001d76: 330c adds r3, #12 + 8001d78: 7812 ldrb r2, [r2, #0] + 8001d7a: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001d7c: 68fb ldr r3, [r7, #12] + 8001d7e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d80: 1c5a adds r2, r3, #1 + 8001d82: 68fb ldr r3, [r7, #12] + 8001d84: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001d86: 68fb ldr r3, [r7, #12] + 8001d88: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d8a: b29b uxth r3, r3 + 8001d8c: 3b01 subs r3, #1 + 8001d8e: b29a uxth r2, r3 + 8001d90: 68fb ldr r3, [r7, #12] + 8001d92: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8001d94: e033 b.n 8001dfe + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001d96: 68fb ldr r3, [r7, #12] + 8001d98: 681b ldr r3, [r3, #0] + 8001d9a: 689b ldr r3, [r3, #8] + 8001d9c: f003 0302 and.w r3, r3, #2 + 8001da0: 2b02 cmp r3, #2 + 8001da2: d113 bne.n 8001dcc + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001da4: 68fb ldr r3, [r7, #12] + 8001da6: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001da8: 68fb ldr r3, [r7, #12] + 8001daa: 681b ldr r3, [r3, #0] + 8001dac: 330c adds r3, #12 + 8001dae: 7812 ldrb r2, [r2, #0] + 8001db0: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001db2: 68fb ldr r3, [r7, #12] + 8001db4: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001db6: 1c5a adds r2, r3, #1 + 8001db8: 68fb ldr r3, [r7, #12] + 8001dba: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001dbc: 68fb ldr r3, [r7, #12] + 8001dbe: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001dc0: b29b uxth r3, r3 + 8001dc2: 3b01 subs r3, #1 + 8001dc4: b29a uxth r2, r3 + 8001dc6: 68fb ldr r3, [r7, #12] + 8001dc8: 86da strh r2, [r3, #54] @ 0x36 + 8001dca: e018 b.n 8001dfe + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001dcc: f7fe fe42 bl 8000a54 + 8001dd0: 4602 mov r2, r0 + 8001dd2: 69fb ldr r3, [r7, #28] + 8001dd4: 1ad3 subs r3, r2, r3 + 8001dd6: 683a ldr r2, [r7, #0] + 8001dd8: 429a cmp r2, r3 + 8001dda: d803 bhi.n 8001de4 + 8001ddc: 683b ldr r3, [r7, #0] + 8001dde: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001de2: d102 bne.n 8001dea + 8001de4: 683b ldr r3, [r7, #0] + 8001de6: 2b00 cmp r3, #0 + 8001de8: d109 bne.n 8001dfe + { + hspi->State = HAL_SPI_STATE_READY; + 8001dea: 68fb ldr r3, [r7, #12] + 8001dec: 2201 movs r2, #1 + 8001dee: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001df2: 68fb ldr r3, [r7, #12] + 8001df4: 2200 movs r2, #0 + 8001df6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001dfa: 2303 movs r3, #3 + 8001dfc: e02d b.n 8001e5a + while (hspi->TxXferCount > 0U) + 8001dfe: 68fb ldr r3, [r7, #12] + 8001e00: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001e02: b29b uxth r3, r3 + 8001e04: 2b00 cmp r3, #0 + 8001e06: d1c6 bne.n 8001d96 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 8001e08: 69fa ldr r2, [r7, #28] + 8001e0a: 6839 ldr r1, [r7, #0] + 8001e0c: 68f8 ldr r0, [r7, #12] + 8001e0e: f000 f8b1 bl 8001f74 + 8001e12: 4603 mov r3, r0 + 8001e14: 2b00 cmp r3, #0 + 8001e16: d002 beq.n 8001e1e + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 8001e18: 68fb ldr r3, [r7, #12] + 8001e1a: 2220 movs r2, #32 + 8001e1c: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 8001e1e: 68fb ldr r3, [r7, #12] + 8001e20: 689b ldr r3, [r3, #8] + 8001e22: 2b00 cmp r3, #0 + 8001e24: d10a bne.n 8001e3c + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 8001e26: 2300 movs r3, #0 + 8001e28: 617b str r3, [r7, #20] + 8001e2a: 68fb ldr r3, [r7, #12] + 8001e2c: 681b ldr r3, [r3, #0] + 8001e2e: 68db ldr r3, [r3, #12] + 8001e30: 617b str r3, [r7, #20] + 8001e32: 68fb ldr r3, [r7, #12] + 8001e34: 681b ldr r3, [r3, #0] + 8001e36: 689b ldr r3, [r3, #8] + 8001e38: 617b str r3, [r7, #20] + 8001e3a: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 8001e3c: 68fb ldr r3, [r7, #12] + 8001e3e: 2201 movs r2, #1 + 8001e40: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8001e44: 68fb ldr r3, [r7, #12] + 8001e46: 2200 movs r2, #0 + 8001e48: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 8001e4c: 68fb ldr r3, [r7, #12] + 8001e4e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001e50: 2b00 cmp r3, #0 + 8001e52: d001 beq.n 8001e58 + { + return HAL_ERROR; + 8001e54: 2301 movs r3, #1 + 8001e56: e000 b.n 8001e5a + } + else + { + return HAL_OK; + 8001e58: 2300 movs r3, #0 + } +} + 8001e5a: 4618 mov r0, r3 + 8001e5c: 3720 adds r7, #32 + 8001e5e: 46bd mov sp, r7 + 8001e60: bd80 pop {r7, pc} + ... + +08001e64 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8001e64: b580 push {r7, lr} + 8001e66: b088 sub sp, #32 + 8001e68: af00 add r7, sp, #0 + 8001e6a: 60f8 str r0, [r7, #12] + 8001e6c: 60b9 str r1, [r7, #8] + 8001e6e: 603b str r3, [r7, #0] + 8001e70: 4613 mov r3, r2 + 8001e72: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 8001e74: f7fe fdee bl 8000a54 + 8001e78: 4602 mov r2, r0 + 8001e7a: 6abb ldr r3, [r7, #40] @ 0x28 + 8001e7c: 1a9b subs r3, r3, r2 + 8001e7e: 683a ldr r2, [r7, #0] + 8001e80: 4413 add r3, r2 + 8001e82: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 8001e84: f7fe fde6 bl 8000a54 + 8001e88: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 8001e8a: 4b39 ldr r3, [pc, #228] @ (8001f70 ) + 8001e8c: 681b ldr r3, [r3, #0] + 8001e8e: 015b lsls r3, r3, #5 + 8001e90: 0d1b lsrs r3, r3, #20 + 8001e92: 69fa ldr r2, [r7, #28] + 8001e94: fb02 f303 mul.w r3, r2, r3 + 8001e98: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8001e9a: e054 b.n 8001f46 + { + if (Timeout != HAL_MAX_DELAY) + 8001e9c: 683b ldr r3, [r7, #0] + 8001e9e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001ea2: d050 beq.n 8001f46 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8001ea4: f7fe fdd6 bl 8000a54 + 8001ea8: 4602 mov r2, r0 + 8001eaa: 69bb ldr r3, [r7, #24] + 8001eac: 1ad3 subs r3, r2, r3 + 8001eae: 69fa ldr r2, [r7, #28] + 8001eb0: 429a cmp r2, r3 + 8001eb2: d902 bls.n 8001eba + 8001eb4: 69fb ldr r3, [r7, #28] + 8001eb6: 2b00 cmp r3, #0 + 8001eb8: d13d bne.n 8001f36 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8001eba: 68fb ldr r3, [r7, #12] + 8001ebc: 681b ldr r3, [r3, #0] + 8001ebe: 685a ldr r2, [r3, #4] + 8001ec0: 68fb ldr r3, [r7, #12] + 8001ec2: 681b ldr r3, [r3, #0] + 8001ec4: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8001ec8: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8001eca: 68fb ldr r3, [r7, #12] + 8001ecc: 685b ldr r3, [r3, #4] + 8001ece: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001ed2: d111 bne.n 8001ef8 + 8001ed4: 68fb ldr r3, [r7, #12] + 8001ed6: 689b ldr r3, [r3, #8] + 8001ed8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001edc: d004 beq.n 8001ee8 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 8001ede: 68fb ldr r3, [r7, #12] + 8001ee0: 689b ldr r3, [r3, #8] + 8001ee2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8001ee6: d107 bne.n 8001ef8 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001ee8: 68fb ldr r3, [r7, #12] + 8001eea: 681b ldr r3, [r3, #0] + 8001eec: 681a ldr r2, [r3, #0] + 8001eee: 68fb ldr r3, [r7, #12] + 8001ef0: 681b ldr r3, [r3, #0] + 8001ef2: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001ef6: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8001ef8: 68fb ldr r3, [r7, #12] + 8001efa: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001efc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8001f00: d10f bne.n 8001f22 + { + SPI_RESET_CRC(hspi); + 8001f02: 68fb ldr r3, [r7, #12] + 8001f04: 681b ldr r3, [r3, #0] + 8001f06: 681a ldr r2, [r3, #0] + 8001f08: 68fb ldr r3, [r7, #12] + 8001f0a: 681b ldr r3, [r3, #0] + 8001f0c: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 8001f10: 601a str r2, [r3, #0] + 8001f12: 68fb ldr r3, [r7, #12] + 8001f14: 681b ldr r3, [r3, #0] + 8001f16: 681a ldr r2, [r3, #0] + 8001f18: 68fb ldr r3, [r7, #12] + 8001f1a: 681b ldr r3, [r3, #0] + 8001f1c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 8001f20: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 8001f22: 68fb ldr r3, [r7, #12] + 8001f24: 2201 movs r2, #1 + 8001f26: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8001f2a: 68fb ldr r3, [r7, #12] + 8001f2c: 2200 movs r2, #0 + 8001f2e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 8001f32: 2303 movs r3, #3 + 8001f34: e017 b.n 8001f66 + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 8001f36: 697b ldr r3, [r7, #20] + 8001f38: 2b00 cmp r3, #0 + 8001f3a: d101 bne.n 8001f40 + { + tmp_timeout = 0U; + 8001f3c: 2300 movs r3, #0 + 8001f3e: 61fb str r3, [r7, #28] + } + count--; + 8001f40: 697b ldr r3, [r7, #20] + 8001f42: 3b01 subs r3, #1 + 8001f44: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8001f46: 68fb ldr r3, [r7, #12] + 8001f48: 681b ldr r3, [r3, #0] + 8001f4a: 689a ldr r2, [r3, #8] + 8001f4c: 68bb ldr r3, [r7, #8] + 8001f4e: 4013 ands r3, r2 + 8001f50: 68ba ldr r2, [r7, #8] + 8001f52: 429a cmp r2, r3 + 8001f54: bf0c ite eq + 8001f56: 2301 moveq r3, #1 + 8001f58: 2300 movne r3, #0 + 8001f5a: b2db uxtb r3, r3 + 8001f5c: 461a mov r2, r3 + 8001f5e: 79fb ldrb r3, [r7, #7] + 8001f60: 429a cmp r2, r3 + 8001f62: d19b bne.n 8001e9c + } + } + + return HAL_OK; + 8001f64: 2300 movs r3, #0 +} + 8001f66: 4618 mov r0, r3 + 8001f68: 3720 adds r7, #32 + 8001f6a: 46bd mov sp, r7 + 8001f6c: bd80 pop {r7, pc} + 8001f6e: bf00 nop + 8001f70: 20000000 .word 0x20000000 + +08001f74 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 8001f74: b580 push {r7, lr} + 8001f76: b088 sub sp, #32 + 8001f78: af02 add r7, sp, #8 + 8001f7a: 60f8 str r0, [r7, #12] + 8001f7c: 60b9 str r1, [r7, #8] + 8001f7e: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 8001f80: 687b ldr r3, [r7, #4] + 8001f82: 9300 str r3, [sp, #0] + 8001f84: 68bb ldr r3, [r7, #8] + 8001f86: 2201 movs r2, #1 + 8001f88: 2102 movs r1, #2 + 8001f8a: 68f8 ldr r0, [r7, #12] + 8001f8c: f7ff ff6a bl 8001e64 + 8001f90: 4603 mov r3, r0 + 8001f92: 2b00 cmp r3, #0 + 8001f94: d007 beq.n 8001fa6 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8001f96: 68fb ldr r3, [r7, #12] + 8001f98: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f9a: f043 0220 orr.w r2, r3, #32 + 8001f9e: 68fb ldr r3, [r7, #12] + 8001fa0: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8001fa2: 2303 movs r3, #3 + 8001fa4: e032 b.n 800200c + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 8001fa6: 4b1b ldr r3, [pc, #108] @ (8002014 ) + 8001fa8: 681b ldr r3, [r3, #0] + 8001faa: 4a1b ldr r2, [pc, #108] @ (8002018 ) + 8001fac: fba2 2303 umull r2, r3, r2, r3 + 8001fb0: 0d5b lsrs r3, r3, #21 + 8001fb2: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8001fb6: fb02 f303 mul.w r3, r2, r3 + 8001fba: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001fbc: 68fb ldr r3, [r7, #12] + 8001fbe: 685b ldr r3, [r3, #4] + 8001fc0: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001fc4: d112 bne.n 8001fec + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8001fc6: 687b ldr r3, [r7, #4] + 8001fc8: 9300 str r3, [sp, #0] + 8001fca: 68bb ldr r3, [r7, #8] + 8001fcc: 2200 movs r2, #0 + 8001fce: 2180 movs r1, #128 @ 0x80 + 8001fd0: 68f8 ldr r0, [r7, #12] + 8001fd2: f7ff ff47 bl 8001e64 + 8001fd6: 4603 mov r3, r0 + 8001fd8: 2b00 cmp r3, #0 + 8001fda: d016 beq.n 800200a + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8001fdc: 68fb ldr r3, [r7, #12] + 8001fde: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001fe0: f043 0220 orr.w r2, r3, #32 + 8001fe4: 68fb ldr r3, [r7, #12] + 8001fe6: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8001fe8: 2303 movs r3, #3 + 8001fea: e00f b.n 800200c + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 8001fec: 697b ldr r3, [r7, #20] + 8001fee: 2b00 cmp r3, #0 + 8001ff0: d00a beq.n 8002008 + { + break; + } + count--; + 8001ff2: 697b ldr r3, [r7, #20] + 8001ff4: 3b01 subs r3, #1 + 8001ff6: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 8001ff8: 68fb ldr r3, [r7, #12] + 8001ffa: 681b ldr r3, [r3, #0] + 8001ffc: 689b ldr r3, [r3, #8] + 8001ffe: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002002: 2b80 cmp r3, #128 @ 0x80 + 8002004: d0f2 beq.n 8001fec + 8002006: e000 b.n 800200a + break; + 8002008: bf00 nop + } + + return HAL_OK; + 800200a: 2300 movs r3, #0 +} + 800200c: 4618 mov r0, r3 + 800200e: 3718 adds r7, #24 + 8002010: 46bd mov sp, r7 + 8002012: bd80 pop {r7, pc} + 8002014: 20000000 .word 0x20000000 + 8002018: 165e9f81 .word 0x165e9f81 + +0800201c : + 800201c: 4603 mov r3, r0 + 800201e: 4402 add r2, r0 + 8002020: 4293 cmp r3, r2 + 8002022: d100 bne.n 8002026 + 8002024: 4770 bx lr + 8002026: f803 1b01 strb.w r1, [r3], #1 + 800202a: e7f9 b.n 8002020 + +0800202c <__libc_init_array>: + 800202c: b570 push {r4, r5, r6, lr} + 800202e: 2600 movs r6, #0 + 8002030: 4d0c ldr r5, [pc, #48] @ (8002064 <__libc_init_array+0x38>) + 8002032: 4c0d ldr r4, [pc, #52] @ (8002068 <__libc_init_array+0x3c>) + 8002034: 1b64 subs r4, r4, r5 + 8002036: 10a4 asrs r4, r4, #2 + 8002038: 42a6 cmp r6, r4 + 800203a: d109 bne.n 8002050 <__libc_init_array+0x24> + 800203c: f000 f81a bl 8002074 <_init> + 8002040: 2600 movs r6, #0 + 8002042: 4d0a ldr r5, [pc, #40] @ (800206c <__libc_init_array+0x40>) + 8002044: 4c0a ldr r4, [pc, #40] @ (8002070 <__libc_init_array+0x44>) + 8002046: 1b64 subs r4, r4, r5 + 8002048: 10a4 asrs r4, r4, #2 + 800204a: 42a6 cmp r6, r4 + 800204c: d105 bne.n 800205a <__libc_init_array+0x2e> + 800204e: bd70 pop {r4, r5, r6, pc} + 8002050: f855 3b04 ldr.w r3, [r5], #4 + 8002054: 4798 blx r3 + 8002056: 3601 adds r6, #1 + 8002058: e7ee b.n 8002038 <__libc_init_array+0xc> + 800205a: f855 3b04 ldr.w r3, [r5], #4 + 800205e: 4798 blx r3 + 8002060: 3601 adds r6, #1 + 8002062: e7f2 b.n 800204a <__libc_init_array+0x1e> + 8002064: 080020c0 .word 0x080020c0 + 8002068: 080020c0 .word 0x080020c0 + 800206c: 080020c0 .word 0x080020c0 + 8002070: 080020c4 .word 0x080020c4 + +08002074 <_init>: + 8002074: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002076: bf00 nop + 8002078: bcf8 pop {r3, r4, r5, r6, r7} + 800207a: bc08 pop {r3} + 800207c: 469e mov lr, r3 + 800207e: 4770 bx lr + +08002080 <_fini>: + 8002080: b5f8 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +START GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libm.a +END GROUP +START GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a +END GROUP +START GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libnosys.a +END GROUP +START GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libnosys.a +END GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtend.o +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + 0x20014000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0x13c + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x13c ./Core/Startup/startup_stm32l152retx.o + 0x08000000 g_pfnVectors + 0x0800013c . = ALIGN (0x4) + +.text 0x0800013c 0x1f50 + 0x0800013c . = ALIGN (0x4) + *(.text) + .text 0x0800013c 0x40 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + .text 0x0800017c 0x30 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x0800017c __aeabi_uldivmod + .text 0x080001ac 0x300 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + 0x080001ac __udivmoddi4 + .text 0x080004ac 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_dvmd_tls.o) + 0x080004ac __aeabi_ldiv0 + 0x080004ac __aeabi_idiv0 + *(.text*) + .text.affiche 0x080004b0 0x60 ./Core/Src/main.o + 0x080004b0 affiche + .text.main 0x08000510 0x44 ./Core/Src/main.o + 0x08000510 main + .text.SystemClock_Config + 0x08000554 0x8c ./Core/Src/main.o + 0x08000554 SystemClock_Config + .text.MX_SPI1_Init + 0x080005e0 0x6c ./Core/Src/main.o + .text.MX_GPIO_Init + 0x0800064c 0x7c ./Core/Src/main.o + .text.Error_Handler + 0x080006c8 0xc ./Core/Src/main.o + 0x080006c8 Error_Handler + .text.HAL_MspInit + 0x080006d4 0x5c ./Core/Src/stm32l1xx_hal_msp.o + 0x080006d4 HAL_MspInit + .text.HAL_SPI_MspInit + 0x08000730 0x88 ./Core/Src/stm32l1xx_hal_msp.o + 0x08000730 HAL_SPI_MspInit + .text.NMI_Handler + 0x080007b8 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007b8 NMI_Handler + .text.HardFault_Handler + 0x080007c0 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007c0 HardFault_Handler + .text.MemManage_Handler + 0x080007c8 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007c8 MemManage_Handler + .text.BusFault_Handler + 0x080007d0 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007d0 BusFault_Handler + .text.UsageFault_Handler + 0x080007d8 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007d8 UsageFault_Handler + .text.SVC_Handler + 0x080007e0 0xc ./Core/Src/stm32l1xx_it.o + 0x080007e0 SVC_Handler + .text.DebugMon_Handler + 0x080007ec 0xc ./Core/Src/stm32l1xx_it.o + 0x080007ec DebugMon_Handler + .text.PendSV_Handler + 0x080007f8 0xc ./Core/Src/stm32l1xx_it.o + 0x080007f8 PendSV_Handler + .text.SysTick_Handler + 0x08000804 0xc ./Core/Src/stm32l1xx_it.o + 0x08000804 SysTick_Handler + .text.SystemInit + 0x08000810 0xc ./Core/Src/system_stm32l1xx.o + 0x08000810 SystemInit + .text.Reset_Handler + 0x0800081c 0x48 ./Core/Startup/startup_stm32l152retx.o + 0x0800081c Reset_Handler + .text.Default_Handler + 0x08000864 0x2 ./Core/Startup/startup_stm32l152retx.o + 0x08000864 DMA2_Channel3_IRQHandler + 0x08000864 EXTI2_IRQHandler + 0x08000864 COMP_ACQ_IRQHandler + 0x08000864 TIM10_IRQHandler + 0x08000864 USB_HP_IRQHandler + 0x08000864 TIM6_IRQHandler + 0x08000864 PVD_IRQHandler + 0x08000864 EXTI3_IRQHandler + 0x08000864 EXTI0_IRQHandler + 0x08000864 I2C2_EV_IRQHandler + 0x08000864 SPI1_IRQHandler + 0x08000864 USB_FS_WKUP_IRQHandler + 0x08000864 DMA2_Channel2_IRQHandler + 0x08000864 DMA1_Channel4_IRQHandler + 0x08000864 ADC1_IRQHandler + 0x08000864 USART3_IRQHandler + 0x08000864 DMA1_Channel7_IRQHandler + 0x08000864 LCD_IRQHandler + 0x08000864 UART5_IRQHandler + 0x08000864 TIM4_IRQHandler + 0x08000864 DMA2_Channel1_IRQHandler + 0x08000864 I2C1_EV_IRQHandler + 0x08000864 DMA1_Channel6_IRQHandler + 0x08000864 UART4_IRQHandler + 0x08000864 DMA2_Channel4_IRQHandler + 0x08000864 TIM3_IRQHandler + 0x08000864 RCC_IRQHandler + 0x08000864 DMA1_Channel1_IRQHandler + 0x08000864 Default_Handler + 0x08000864 EXTI15_10_IRQHandler + 0x08000864 TIM7_IRQHandler + 0x08000864 TIM5_IRQHandler + 0x08000864 EXTI9_5_IRQHandler + 0x08000864 TIM9_IRQHandler + 0x08000864 TAMPER_STAMP_IRQHandler + 0x08000864 RTC_WKUP_IRQHandler + 0x08000864 SPI2_IRQHandler + 0x08000864 DMA2_Channel5_IRQHandler + 0x08000864 DMA1_Channel5_IRQHandler + 0x08000864 USB_LP_IRQHandler + 0x08000864 EXTI4_IRQHandler + 0x08000864 DMA1_Channel3_IRQHandler + 0x08000864 COMP_IRQHandler + 0x08000864 WWDG_IRQHandler + 0x08000864 TIM2_IRQHandler + 0x08000864 DAC_IRQHandler + 0x08000864 EXTI1_IRQHandler + 0x08000864 TIM11_IRQHandler + 0x08000864 USART2_IRQHandler + 0x08000864 I2C2_ER_IRQHandler + 0x08000864 DMA1_Channel2_IRQHandler + 0x08000864 FLASH_IRQHandler + 0x08000864 USART1_IRQHandler + 0x08000864 SPI3_IRQHandler + 0x08000864 I2C1_ER_IRQHandler + 0x08000864 RTC_Alarm_IRQHandler + .text.MAX7219_Init + 0x08000866 0x2a ./Drivers/7Seg_MAX7219/max7219.o + 0x08000866 MAX7219_Init + .text.MAX7219_ShutdownStop + 0x08000890 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x08000890 MAX7219_ShutdownStop + .text.MAX7219_DisplayTestStop + 0x080008a0 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x080008a0 MAX7219_DisplayTestStop + .text.MAX7219_SetBrightness + 0x080008b0 0x24 ./Drivers/7Seg_MAX7219/max7219.o + 0x080008b0 MAX7219_SetBrightness + .text.MAX7219_Clear + 0x080008d4 0x2c ./Drivers/7Seg_MAX7219/max7219.o + 0x080008d4 MAX7219_Clear + .text.MAX7219_DisplayChar + 0x08000900 0x2c ./Drivers/7Seg_MAX7219/max7219.o + 0x08000900 MAX7219_DisplayChar + .text.MAX7219_Write + 0x0800092c 0x3c ./Drivers/7Seg_MAX7219/max7219.o + 0x0800092c MAX7219_Write + .text.MAX7219_SendByte + 0x08000968 0x24 ./Drivers/7Seg_MAX7219/max7219.o + .text.HAL_Init + 0x0800098c 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0800098c HAL_Init + .text.HAL_InitTick + 0x080009bc 0x74 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x080009bc HAL_InitTick + .text.HAL_IncTick + 0x08000a30 0x24 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a30 HAL_IncTick + .text.HAL_GetTick + 0x08000a54 0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a54 HAL_GetTick + .text.HAL_Delay + 0x08000a68 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a68 HAL_Delay + .text.__NVIC_SetPriorityGrouping + 0x08000aac 0x48 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.__NVIC_GetPriorityGrouping + 0x08000af4 0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.__NVIC_SetPriority + 0x08000b10 0x54 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.NVIC_EncodePriority + 0x08000b64 0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.SysTick_Config + 0x08000bc8 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x08000c0c 0x16 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000c0c HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x08000c22 0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000c22 HAL_NVIC_SetPriority + .text.HAL_SYSTICK_Config + 0x08000c5a 0x18 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000c5a HAL_SYSTICK_Config + *fill* 0x08000c72 0x2 + .text.HAL_GPIO_Init + 0x08000c74 0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000c74 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x08000f94 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000f94 HAL_GPIO_WritePin + .text.HAL_RCC_OscConfig + 0x08000fc4 0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08000fc4 HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x08001624 0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08001624 HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x0800188c 0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0800188c HAL_RCC_GetSysClockFreq + .text.RCC_SetFlashLatencyFromMSIRange + 0x08001a08 0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .text.HAL_SPI_Init + 0x08001ac8 0x112 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001ac8 HAL_SPI_Init + .text.HAL_SPI_Transmit + 0x08001bda 0x288 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001bda HAL_SPI_Transmit + *fill* 0x08001e62 0x2 + .text.SPI_WaitFlagStateUntilTimeout + 0x08001e64 0x110 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .text.SPI_EndRxTxTransaction + 0x08001f74 0xa8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .text.memset 0x0800201c 0x10 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + 0x0800201c memset + .text.__libc_init_array + 0x0800202c 0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + 0x0800202c __libc_init_array + *(.glue_7) + .glue_7 0x08002074 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x08002074 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x08002074 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + *(.init) + .init 0x08002074 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x08002074 _init + .init 0x08002078 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + *(.fini) + .fini 0x08002080 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x08002080 _fini + .fini 0x08002084 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + 0x0800208c . = ALIGN (0x4) + 0x0800208c _etext = . + +.vfp11_veneer 0x0800208c 0x0 + .vfp11_veneer 0x0800208c 0x0 linker stubs + +.v4_bx 0x0800208c 0x0 + .v4_bx 0x0800208c 0x0 linker stubs + +.iplt 0x0800208c 0x0 + .iplt 0x0800208c 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + +.rodata 0x0800208c 0x2c + 0x0800208c . = ALIGN (0x4) + *(.rodata) + *(.rodata*) + .rodata.PLLMulTable + 0x0800208c 0x9 ./Core/Src/system_stm32l1xx.o + 0x0800208c PLLMulTable + *fill* 0x08002095 0x3 + .rodata.AHBPrescTable + 0x08002098 0x10 ./Core/Src/system_stm32l1xx.o + 0x08002098 AHBPrescTable + .rodata.conv_7seg + 0x080020a8 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x080020a8 conv_7seg + 0x080020b8 . = ALIGN (0x4) + +.ARM.extab 0x080020b8 0x0 + 0x080020b8 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x080020b8 . = ALIGN (0x4) + +.ARM 0x080020b8 0x8 + 0x080020b8 . = ALIGN (0x4) + 0x080020b8 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x080020b8 0x8 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0x1ad ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_macro 0x000147f4 0x1aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + +.debug_line 0x00000000 0x6fc2 + .debug_line 0x00000000 0x7c4 ./Core/Src/main.o + .debug_line 0x000007c4 0x6dd ./Core/Src/stm32l1xx_hal_msp.o + .debug_line 0x00000ea1 0x73e ./Core/Src/stm32l1xx_it.o + .debug_line 0x000015df 0x730 ./Core/Src/system_stm32l1xx.o + .debug_line 0x00001d0f 0x79 ./Core/Startup/startup_stm32l152retx.o + .debug_line 0x00001d88 0x7de ./Drivers/7Seg_MAX7219/max7219.o + .debug_line 0x00002566 0x95b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_line 0x00002ec1 0xc2a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_line 0x00003aeb 0x99f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_line 0x0000448a 0xf1e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_line 0x000053a8 0x1c1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + +.debug_str 0x00000000 0x81143 + .debug_str 0x00000000 0x81143 ./Core/Src/main.o + 0x7fc9a (size before relaxing) + .debug_str 0x00081143 0x7fa10 ./Core/Src/stm32l1xx_hal_msp.o + .debug_str 0x00081143 0x7f5a7 ./Core/Src/stm32l1xx_it.o + .debug_str 0x00081143 0x7f5f8 ./Core/Src/system_stm32l1xx.o + .debug_str 0x00081143 0x8c ./Core/Startup/startup_stm32l152retx.o + .debug_str 0x00081143 0x7fb54 ./Drivers/7Seg_MAX7219/max7219.o + .debug_str 0x00081143 0x7fd20 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_str 0x00081143 0x7fe2c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_str 0x00081143 0x7f78b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_str 0x00081143 0x7fab4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_str 0x00081143 0x7ff1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Core/Src/main.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_hal_msp.o + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_it.o + .comment 0x00000043 0x44 ./Core/Src/system_stm32l1xx.o + .comment 0x00000043 0x44 ./Drivers/7Seg_MAX7219/max7219.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + +.debug_frame 0x00000000 0x18ac + .debug_frame 0x00000000 0xd0 ./Core/Src/main.o + .debug_frame 0x000000d0 0x80 ./Core/Src/stm32l1xx_hal_msp.o + .debug_frame 0x00000150 0x104 ./Core/Src/stm32l1xx_it.o + .debug_frame 0x00000254 0x58 ./Core/Src/system_stm32l1xx.o + .debug_frame 0x000002ac 0x198 ./Drivers/7Seg_MAX7219/max7219.o + .debug_frame 0x00000444 0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_frame 0x00000780 0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_frame 0x00000c68 0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_frame 0x00000db4 0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_frame 0x00000fd8 0x828 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_frame 0x00001800 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00001820 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .debug_frame 0x0000184c 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00001878 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x70 + .debug_line_str + 0x00000000 0x70 ./Core/Startup/startup_stm32l152retx.o diff --git a/TP4_INIT_TFT/Debug/TP2_ISEN_DISPLAY.list b/TP4_INIT_TFT/Debug/TP2_ISEN_DISPLAY.list new file mode 100644 index 0000000..e9f61c3 --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP2_ISEN_DISPLAY.list @@ -0,0 +1,5427 @@ + +TP2_ISEN_DISPLAY.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00001f28 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000001c 08002064 08002064 00003064 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08002080 08002080 0000400c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08002080 08002080 00003080 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08002088 08002088 0000400c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08002088 08002088 00003088 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 0800208c 0800208c 0000308c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000000c 20000000 08002090 00004000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000078 2000000c 0800209c 0000400c 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20000084 0800209c 00004084 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0 + CONTENTS, READONLY + 12 .debug_info 000057a5 00000000 00000000 00004035 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 0000148d 00000000 00000000 000097da 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000660 00000000 00000000 0000ac68 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 000004b5 00000000 00000000 0000b2c8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 00014998 00000000 00000000 0000b77d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 00006fed 00000000 00000000 00020115 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 0008118d 00000000 00000000 00027102 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000a828f 2**0 + CONTENTS, READONLY + 20 .debug_frame 000018a4 00000000 00000000 000a82d4 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000a9b78 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 2000000c .word 0x2000000c + 8000158: 00000000 .word 0x00000000 + 800015c: 0800204c .word 0x0800204c + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000010 .word 0x20000010 + 8000178: 0800204c .word 0x0800204c + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0 : + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void displayScrollingText() { + 80004b0: b580 push {r7, lr} + 80004b2: b086 sub sp, #24 + 80004b4: af00 add r7, sp, #0 + const uint8_t I = 0b00110000; // I + 80004b6: 2330 movs r3, #48 @ 0x30 + 80004b8: 73fb strb r3, [r7, #15] + const uint8_t S = 0b01011011; // S + 80004ba: 235b movs r3, #91 @ 0x5b + 80004bc: 73bb strb r3, [r7, #14] + const uint8_t E = 0b01001111; // E + 80004be: 234f movs r3, #79 @ 0x4f + 80004c0: 737b strb r3, [r7, #13] + const uint8_t N = 0b00110110; // N + 80004c2: 2336 movs r3, #54 @ 0x36 + 80004c4: 733b strb r3, [r7, #12] + const uint8_t SPACE = 0b00000000; // Espace + 80004c6: 2300 movs r3, #0 + 80004c8: 72fb strb r3, [r7, #11] + + const uint8_t symbols[] = {I, S, E, N, SPACE}; + 80004ca: 7bfb ldrb r3, [r7, #15] + 80004cc: 713b strb r3, [r7, #4] + 80004ce: 7bbb ldrb r3, [r7, #14] + 80004d0: 717b strb r3, [r7, #5] + 80004d2: 7b7b ldrb r3, [r7, #13] + 80004d4: 71bb strb r3, [r7, #6] + 80004d6: 7b3b ldrb r3, [r7, #12] + 80004d8: 71fb strb r3, [r7, #7] + 80004da: 7afb ldrb r3, [r7, #11] + 80004dc: 723b strb r3, [r7, #8] + const uint8_t numSymbols = sizeof(symbols) / sizeof(symbols[0]); + 80004de: 2305 movs r3, #5 + 80004e0: 72bb strb r3, [r7, #10] + + while (1) { + for (int i = 0; i < numSymbols; i++) { + 80004e2: 2300 movs r3, #0 + 80004e4: 617b str r3, [r7, #20] + 80004e6: e021 b.n 800052c + for (int j = 0; j < 4; j++) { + 80004e8: 2300 movs r3, #0 + 80004ea: 613b str r3, [r7, #16] + 80004ec: e014 b.n 8000518 + MAX7219_Write(j + 1, symbols[(i + j) % numSymbols]); + 80004ee: 693b ldr r3, [r7, #16] + 80004f0: 1c58 adds r0, r3, #1 + 80004f2: 697a ldr r2, [r7, #20] + 80004f4: 693b ldr r3, [r7, #16] + 80004f6: 4413 add r3, r2 + 80004f8: 7aba ldrb r2, [r7, #10] + 80004fa: fb93 f1f2 sdiv r1, r3, r2 + 80004fe: fb01 f202 mul.w r2, r1, r2 + 8000502: 1a9b subs r3, r3, r2 + 8000504: 3318 adds r3, #24 + 8000506: 443b add r3, r7 + 8000508: f813 3c14 ldrb.w r3, [r3, #-20] + 800050c: 4619 mov r1, r3 + 800050e: f000 f9f9 bl 8000904 + for (int j = 0; j < 4; j++) { + 8000512: 693b ldr r3, [r7, #16] + 8000514: 3301 adds r3, #1 + 8000516: 613b str r3, [r7, #16] + 8000518: 693b ldr r3, [r7, #16] + 800051a: 2b03 cmp r3, #3 + 800051c: dde7 ble.n 80004ee + } + HAL_Delay(500); + 800051e: f44f 70fa mov.w r0, #500 @ 0x1f4 + 8000522: f000 fa8d bl 8000a40 + for (int i = 0; i < numSymbols; i++) { + 8000526: 697b ldr r3, [r7, #20] + 8000528: 3301 adds r3, #1 + 800052a: 617b str r3, [r7, #20] + 800052c: 7abb ldrb r3, [r7, #10] + 800052e: 697a ldr r2, [r7, #20] + 8000530: 429a cmp r2, r3 + 8000532: dbd9 blt.n 80004e8 + 8000534: e7d5 b.n 80004e2 + +08000536
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000536: b580 push {r7, lr} + 8000538: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 800053a: f000 fa13 bl 8000964 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 800053e: f000 f80b bl 8000558 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000542: f000 f885 bl 8000650 + MX_SPI1_Init(); + 8000546: f000 f84d bl 80005e4 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 800054a: f000 f98e bl 800086a + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 800054e: f000 f9c3 bl 80008d8 + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + displayScrollingText(); + 8000552: f7ff ffad bl 80004b0 + 8000556: e7fc b.n 8000552 + +08000558 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000558: b580 push {r7, lr} + 800055a: b092 sub sp, #72 @ 0x48 + 800055c: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 800055e: f107 0314 add.w r3, r7, #20 + 8000562: 2234 movs r2, #52 @ 0x34 + 8000564: 2100 movs r1, #0 + 8000566: 4618 mov r0, r3 + 8000568: f001 fd44 bl 8001ff4 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 800056c: 463b mov r3, r7 + 800056e: 2200 movs r2, #0 + 8000570: 601a str r2, [r3, #0] + 8000572: 605a str r2, [r3, #4] + 8000574: 609a str r2, [r3, #8] + 8000576: 60da str r2, [r3, #12] + 8000578: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 800057a: 4b19 ldr r3, [pc, #100] @ (80005e0 ) + 800057c: 681b ldr r3, [r3, #0] + 800057e: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 8000582: 4a17 ldr r2, [pc, #92] @ (80005e0 ) + 8000584: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000588: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 800058a: 2302 movs r3, #2 + 800058c: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 800058e: 2301 movs r3, #1 + 8000590: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000592: 2310 movs r3, #16 + 8000594: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000596: 2300 movs r3, #0 + 8000598: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 800059a: f107 0314 add.w r3, r7, #20 + 800059e: 4618 mov r0, r3 + 80005a0: f000 fcfc bl 8000f9c + 80005a4: 4603 mov r3, r0 + 80005a6: 2b00 cmp r3, #0 + 80005a8: d001 beq.n 80005ae + { + Error_Handler(); + 80005aa: f000 f88f bl 80006cc + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80005ae: 230f movs r3, #15 + 80005b0: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 80005b2: 2301 movs r3, #1 + 80005b4: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80005b6: 2300 movs r3, #0 + 80005b8: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80005ba: 2300 movs r3, #0 + 80005bc: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80005be: 2300 movs r3, #0 + 80005c0: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 80005c2: 463b mov r3, r7 + 80005c4: 2100 movs r1, #0 + 80005c6: 4618 mov r0, r3 + 80005c8: f001 f818 bl 80015fc + 80005cc: 4603 mov r3, r0 + 80005ce: 2b00 cmp r3, #0 + 80005d0: d001 beq.n 80005d6 + { + Error_Handler(); + 80005d2: f000 f87b bl 80006cc + } +} + 80005d6: bf00 nop + 80005d8: 3748 adds r7, #72 @ 0x48 + 80005da: 46bd mov sp, r7 + 80005dc: bd80 pop {r7, pc} + 80005de: bf00 nop + 80005e0: 40007000 .word 0x40007000 + +080005e4 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 80005e4: b580 push {r7, lr} + 80005e6: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 80005e8: 4b17 ldr r3, [pc, #92] @ (8000648 ) + 80005ea: 4a18 ldr r2, [pc, #96] @ (800064c ) + 80005ec: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 80005ee: 4b16 ldr r3, [pc, #88] @ (8000648 ) + 80005f0: f44f 7282 mov.w r2, #260 @ 0x104 + 80005f4: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 80005f6: 4b14 ldr r3, [pc, #80] @ (8000648 ) + 80005f8: 2200 movs r2, #0 + 80005fa: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 80005fc: 4b12 ldr r3, [pc, #72] @ (8000648 ) + 80005fe: 2200 movs r2, #0 + 8000600: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 8000602: 4b11 ldr r3, [pc, #68] @ (8000648 ) + 8000604: 2200 movs r2, #0 + 8000606: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 8000608: 4b0f ldr r3, [pc, #60] @ (8000648 ) + 800060a: 2200 movs r2, #0 + 800060c: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 800060e: 4b0e ldr r3, [pc, #56] @ (8000648 ) + 8000610: f44f 7200 mov.w r2, #512 @ 0x200 + 8000614: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8000616: 4b0c ldr r3, [pc, #48] @ (8000648 ) + 8000618: 2200 movs r2, #0 + 800061a: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 800061c: 4b0a ldr r3, [pc, #40] @ (8000648 ) + 800061e: 2200 movs r2, #0 + 8000620: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 8000622: 4b09 ldr r3, [pc, #36] @ (8000648 ) + 8000624: 2200 movs r2, #0 + 8000626: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8000628: 4b07 ldr r3, [pc, #28] @ (8000648 ) + 800062a: 2200 movs r2, #0 + 800062c: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 800062e: 4b06 ldr r3, [pc, #24] @ (8000648 ) + 8000630: 220a movs r2, #10 + 8000632: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8000634: 4804 ldr r0, [pc, #16] @ (8000648 ) + 8000636: f001 fa33 bl 8001aa0 + 800063a: 4603 mov r3, r0 + 800063c: 2b00 cmp r3, #0 + 800063e: d001 beq.n 8000644 + { + Error_Handler(); + 8000640: f000 f844 bl 80006cc + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 8000644: bf00 nop + 8000646: bd80 pop {r7, pc} + 8000648: 20000028 .word 0x20000028 + 800064c: 40013000 .word 0x40013000 + +08000650 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000650: b580 push {r7, lr} + 8000652: b088 sub sp, #32 + 8000654: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000656: f107 030c add.w r3, r7, #12 + 800065a: 2200 movs r2, #0 + 800065c: 601a str r2, [r3, #0] + 800065e: 605a str r2, [r3, #4] + 8000660: 609a str r2, [r3, #8] + 8000662: 60da str r2, [r3, #12] + 8000664: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000666: 4b17 ldr r3, [pc, #92] @ (80006c4 ) + 8000668: 69db ldr r3, [r3, #28] + 800066a: 4a16 ldr r2, [pc, #88] @ (80006c4 ) + 800066c: f043 0304 orr.w r3, r3, #4 + 8000670: 61d3 str r3, [r2, #28] + 8000672: 4b14 ldr r3, [pc, #80] @ (80006c4 ) + 8000674: 69db ldr r3, [r3, #28] + 8000676: f003 0304 and.w r3, r3, #4 + 800067a: 60bb str r3, [r7, #8] + 800067c: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800067e: 4b11 ldr r3, [pc, #68] @ (80006c4 ) + 8000680: 69db ldr r3, [r3, #28] + 8000682: 4a10 ldr r2, [pc, #64] @ (80006c4 ) + 8000684: f043 0301 orr.w r3, r3, #1 + 8000688: 61d3 str r3, [r2, #28] + 800068a: 4b0e ldr r3, [pc, #56] @ (80006c4 ) + 800068c: 69db ldr r3, [r3, #28] + 800068e: f003 0301 and.w r3, r3, #1 + 8000692: 607b str r3, [r7, #4] + 8000694: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 8000696: 2200 movs r2, #0 + 8000698: 2101 movs r1, #1 + 800069a: 480b ldr r0, [pc, #44] @ (80006c8 ) + 800069c: f000 fc66 bl 8000f6c + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 80006a0: 2301 movs r3, #1 + 80006a2: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80006a4: 2301 movs r3, #1 + 80006a6: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80006a8: 2300 movs r3, #0 + 80006aa: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80006ac: 2300 movs r3, #0 + 80006ae: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80006b0: f107 030c add.w r3, r7, #12 + 80006b4: 4619 mov r1, r3 + 80006b6: 4804 ldr r0, [pc, #16] @ (80006c8 ) + 80006b8: f000 fac8 bl 8000c4c + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 80006bc: bf00 nop + 80006be: 3720 adds r7, #32 + 80006c0: 46bd mov sp, r7 + 80006c2: bd80 pop {r7, pc} + 80006c4: 40023800 .word 0x40023800 + 80006c8: 40020800 .word 0x40020800 + +080006cc : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 80006cc: b480 push {r7} + 80006ce: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 80006d0: b672 cpsid i +} + 80006d2: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 80006d4: bf00 nop + 80006d6: e7fd b.n 80006d4 + +080006d8 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80006d8: b480 push {r7} + 80006da: b085 sub sp, #20 + 80006dc: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 80006de: 4b14 ldr r3, [pc, #80] @ (8000730 ) + 80006e0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80006e2: 4a13 ldr r2, [pc, #76] @ (8000730 ) + 80006e4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 80006e8: 6253 str r3, [r2, #36] @ 0x24 + 80006ea: 4b11 ldr r3, [pc, #68] @ (8000730 ) + 80006ec: 6a5b ldr r3, [r3, #36] @ 0x24 + 80006ee: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 80006f2: 60fb str r3, [r7, #12] + 80006f4: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80006f6: 4b0e ldr r3, [pc, #56] @ (8000730 ) + 80006f8: 6a1b ldr r3, [r3, #32] + 80006fa: 4a0d ldr r2, [pc, #52] @ (8000730 ) + 80006fc: f043 0301 orr.w r3, r3, #1 + 8000700: 6213 str r3, [r2, #32] + 8000702: 4b0b ldr r3, [pc, #44] @ (8000730 ) + 8000704: 6a1b ldr r3, [r3, #32] + 8000706: f003 0301 and.w r3, r3, #1 + 800070a: 60bb str r3, [r7, #8] + 800070c: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800070e: 4b08 ldr r3, [pc, #32] @ (8000730 ) + 8000710: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000712: 4a07 ldr r2, [pc, #28] @ (8000730 ) + 8000714: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000718: 6253 str r3, [r2, #36] @ 0x24 + 800071a: 4b05 ldr r3, [pc, #20] @ (8000730 ) + 800071c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800071e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000722: 607b str r3, [r7, #4] + 8000724: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000726: bf00 nop + 8000728: 3714 adds r7, #20 + 800072a: 46bd mov sp, r7 + 800072c: bc80 pop {r7} + 800072e: 4770 bx lr + 8000730: 40023800 .word 0x40023800 + +08000734 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8000734: b580 push {r7, lr} + 8000736: b08a sub sp, #40 @ 0x28 + 8000738: af00 add r7, sp, #0 + 800073a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800073c: f107 0314 add.w r3, r7, #20 + 8000740: 2200 movs r2, #0 + 8000742: 601a str r2, [r3, #0] + 8000744: 605a str r2, [r3, #4] + 8000746: 609a str r2, [r3, #8] + 8000748: 60da str r2, [r3, #12] + 800074a: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 800074c: 687b ldr r3, [r7, #4] + 800074e: 681b ldr r3, [r3, #0] + 8000750: 4a17 ldr r2, [pc, #92] @ (80007b0 ) + 8000752: 4293 cmp r3, r2 + 8000754: d127 bne.n 80007a6 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 8000756: 4b17 ldr r3, [pc, #92] @ (80007b4 ) + 8000758: 6a1b ldr r3, [r3, #32] + 800075a: 4a16 ldr r2, [pc, #88] @ (80007b4 ) + 800075c: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 8000760: 6213 str r3, [r2, #32] + 8000762: 4b14 ldr r3, [pc, #80] @ (80007b4 ) + 8000764: 6a1b ldr r3, [r3, #32] + 8000766: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 800076a: 613b str r3, [r7, #16] + 800076c: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800076e: 4b11 ldr r3, [pc, #68] @ (80007b4 ) + 8000770: 69db ldr r3, [r3, #28] + 8000772: 4a10 ldr r2, [pc, #64] @ (80007b4 ) + 8000774: f043 0301 orr.w r3, r3, #1 + 8000778: 61d3 str r3, [r2, #28] + 800077a: 4b0e ldr r3, [pc, #56] @ (80007b4 ) + 800077c: 69db ldr r3, [r3, #28] + 800077e: f003 0301 and.w r3, r3, #1 + 8000782: 60fb str r3, [r7, #12] + 8000784: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 8000786: 23e0 movs r3, #224 @ 0xe0 + 8000788: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800078a: 2302 movs r3, #2 + 800078c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800078e: 2300 movs r3, #0 + 8000790: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000792: 2303 movs r3, #3 + 8000794: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8000796: 2305 movs r3, #5 + 8000798: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800079a: f107 0314 add.w r3, r7, #20 + 800079e: 4619 mov r1, r3 + 80007a0: 4805 ldr r0, [pc, #20] @ (80007b8 ) + 80007a2: f000 fa53 bl 8000c4c + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 80007a6: bf00 nop + 80007a8: 3728 adds r7, #40 @ 0x28 + 80007aa: 46bd mov sp, r7 + 80007ac: bd80 pop {r7, pc} + 80007ae: bf00 nop + 80007b0: 40013000 .word 0x40013000 + 80007b4: 40023800 .word 0x40023800 + 80007b8: 40020000 .word 0x40020000 + +080007bc : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 80007bc: b480 push {r7} + 80007be: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 80007c0: bf00 nop + 80007c2: e7fd b.n 80007c0 + +080007c4 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 80007c4: b480 push {r7} + 80007c6: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 80007c8: bf00 nop + 80007ca: e7fd b.n 80007c8 + +080007cc : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 80007cc: b480 push {r7} + 80007ce: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 80007d0: bf00 nop + 80007d2: e7fd b.n 80007d0 + +080007d4 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 80007d4: b480 push {r7} + 80007d6: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 80007d8: bf00 nop + 80007da: e7fd b.n 80007d8 + +080007dc : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 80007dc: b480 push {r7} + 80007de: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 80007e0: bf00 nop + 80007e2: e7fd b.n 80007e0 + +080007e4 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 80007e4: b480 push {r7} + 80007e6: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 80007e8: bf00 nop + 80007ea: 46bd mov sp, r7 + 80007ec: bc80 pop {r7} + 80007ee: 4770 bx lr + +080007f0 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 80007f0: b480 push {r7} + 80007f2: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 80007f4: bf00 nop + 80007f6: 46bd mov sp, r7 + 80007f8: bc80 pop {r7} + 80007fa: 4770 bx lr + +080007fc : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 80007fc: b480 push {r7} + 80007fe: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000800: bf00 nop + 8000802: 46bd mov sp, r7 + 8000804: bc80 pop {r7} + 8000806: 4770 bx lr + +08000808 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000808: b580 push {r7, lr} + 800080a: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 800080c: f000 f8fc bl 8000a08 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000810: bf00 nop + 8000812: bd80 pop {r7, pc} + +08000814 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000814: b480 push {r7} + 8000816: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000818: bf00 nop + 800081a: 46bd mov sp, r7 + 800081c: bc80 pop {r7} + 800081e: 4770 bx lr + +08000820 : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000820: f7ff fff8 bl 8000814 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000824: 480b ldr r0, [pc, #44] @ (8000854 ) + ldr r1, =_edata + 8000826: 490c ldr r1, [pc, #48] @ (8000858 ) + ldr r2, =_sidata + 8000828: 4a0c ldr r2, [pc, #48] @ (800085c ) + movs r3, #0 + 800082a: 2300 movs r3, #0 + b LoopCopyDataInit + 800082c: e002 b.n 8000834 + +0800082e : + +CopyDataInit: + ldr r4, [r2, r3] + 800082e: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000830: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000832: 3304 adds r3, #4 + +08000834 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000834: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000836: 428c cmp r4, r1 + bcc CopyDataInit + 8000838: d3f9 bcc.n 800082e + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 800083a: 4a09 ldr r2, [pc, #36] @ (8000860 ) + ldr r4, =_ebss + 800083c: 4c09 ldr r4, [pc, #36] @ (8000864 ) + movs r3, #0 + 800083e: 2300 movs r3, #0 + b LoopFillZerobss + 8000840: e001 b.n 8000846 + +08000842 : + +FillZerobss: + str r3, [r2] + 8000842: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000844: 3204 adds r2, #4 + +08000846 : + +LoopFillZerobss: + cmp r2, r4 + 8000846: 42a2 cmp r2, r4 + bcc FillZerobss + 8000848: d3fb bcc.n 8000842 + +/* Call static constructors */ + bl __libc_init_array + 800084a: f001 fbdb bl 8002004 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800084e: f7ff fe72 bl 8000536
+ bx lr + 8000852: 4770 bx lr + ldr r0, =_sdata + 8000854: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000858: 2000000c .word 0x2000000c + ldr r2, =_sidata + 800085c: 08002090 .word 0x08002090 + ldr r2, =_sbss + 8000860: 2000000c .word 0x2000000c + ldr r4, =_ebss + 8000864: 20000084 .word 0x20000084 + +08000868 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000868: e7fe b.n 8000868 + +0800086a : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 800086a: b580 push {r7, lr} + 800086c: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 800086e: 2107 movs r1, #7 + 8000870: 200b movs r0, #11 + 8000872: f000 f847 bl 8000904 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 8000876: 2100 movs r1, #0 + 8000878: 2009 movs r0, #9 + 800087a: f000 f843 bl 8000904 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 800087e: f000 f809 bl 8000894 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 8000882: f000 f80f bl 80008a4 + MAX7219_Clear(); // clear all digits + 8000886: f000 f827 bl 80008d8 + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 800088a: 200f movs r0, #15 + 800088c: f000 f812 bl 80008b4 +} + 8000890: bf00 nop + 8000892: bd80 pop {r7, pc} + +08000894 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000894: b580 push {r7, lr} + 8000896: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000898: 2101 movs r1, #1 + 800089a: 200c movs r0, #12 + 800089c: f000 f832 bl 8000904 +} + 80008a0: bf00 nop + 80008a2: bd80 pop {r7, pc} + +080008a4 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 80008a4: b580 push {r7, lr} + 80008a6: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 80008a8: 2100 movs r1, #0 + 80008aa: 200f movs r0, #15 + 80008ac: f000 f82a bl 8000904 +} + 80008b0: bf00 nop + 80008b2: bd80 pop {r7, pc} + +080008b4 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 80008b4: b580 push {r7, lr} + 80008b6: b082 sub sp, #8 + 80008b8: af00 add r7, sp, #0 + 80008ba: 4603 mov r3, r0 + 80008bc: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 80008be: 79fb ldrb r3, [r7, #7] + 80008c0: f003 030f and.w r3, r3, #15 + 80008c4: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 80008c6: 79fb ldrb r3, [r7, #7] + 80008c8: 4619 mov r1, r3 + 80008ca: 200a movs r0, #10 + 80008cc: f000 f81a bl 8000904 +} + 80008d0: bf00 nop + 80008d2: 3708 adds r7, #8 + 80008d4: 46bd mov sp, r7 + 80008d6: bd80 pop {r7, pc} + +080008d8 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 80008d8: b580 push {r7, lr} + 80008da: b082 sub sp, #8 + 80008dc: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 80008de: 2300 movs r3, #0 + 80008e0: 71fb strb r3, [r7, #7] + 80008e2: e007 b.n 80008f4 + MAX7219_Write(i, 0x00); // turn all segments off + 80008e4: 79fb ldrb r3, [r7, #7] + 80008e6: 2100 movs r1, #0 + 80008e8: 4618 mov r0, r3 + 80008ea: f000 f80b bl 8000904 + for (i=0; i < 8; i++) + 80008ee: 79fb ldrb r3, [r7, #7] + 80008f0: 3301 adds r3, #1 + 80008f2: 71fb strb r3, [r7, #7] + 80008f4: 79fb ldrb r3, [r7, #7] + 80008f6: 2b07 cmp r3, #7 + 80008f8: d9f4 bls.n 80008e4 +} + 80008fa: bf00 nop + 80008fc: bf00 nop + 80008fe: 3708 adds r7, #8 + 8000900: 46bd mov sp, r7 + 8000902: bd80 pop {r7, pc} + +08000904 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8000904: b580 push {r7, lr} + 8000906: b082 sub sp, #8 + 8000908: af00 add r7, sp, #0 + 800090a: 4603 mov r3, r0 + 800090c: 460a mov r2, r1 + 800090e: 71fb strb r3, [r7, #7] + 8000910: 4613 mov r3, r2 + 8000912: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8000914: 4b09 ldr r3, [pc, #36] @ (800093c ) + 8000916: f44f 3280 mov.w r2, #65536 @ 0x10000 + 800091a: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 800091c: 79fb ldrb r3, [r7, #7] + 800091e: 4618 mov r0, r3 + 8000920: f000 f80e bl 8000940 + MAX7219_SendByte(dataout); // write data to MAX7219 + 8000924: 79bb ldrb r3, [r7, #6] + 8000926: 4618 mov r0, r3 + 8000928: f000 f80a bl 8000940 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 800092c: 4b03 ldr r3, [pc, #12] @ (800093c ) + 800092e: 2201 movs r2, #1 + 8000930: 619a str r2, [r3, #24] + } + 8000932: bf00 nop + 8000934: 3708 adds r7, #8 + 8000936: 46bd mov sp, r7 + 8000938: bd80 pop {r7, pc} + 800093a: bf00 nop + 800093c: 40020800 .word 0x40020800 + +08000940 : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000940: b580 push {r7, lr} + 8000942: b082 sub sp, #8 + 8000944: af00 add r7, sp, #0 + 8000946: 4603 mov r3, r0 + 8000948: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 800094a: 1df9 adds r1, r7, #7 + 800094c: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000950: 2201 movs r2, #1 + 8000952: 4803 ldr r0, [pc, #12] @ (8000960 ) + 8000954: f001 f92d bl 8001bb2 + +} + 8000958: bf00 nop + 800095a: 3708 adds r7, #8 + 800095c: 46bd mov sp, r7 + 800095e: bd80 pop {r7, pc} + 8000960: 20000028 .word 0x20000028 + +08000964 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000964: b580 push {r7, lr} + 8000966: b082 sub sp, #8 + 8000968: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 800096a: 2300 movs r3, #0 + 800096c: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 800096e: 2003 movs r0, #3 + 8000970: f000 f938 bl 8000be4 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000974: 200f movs r0, #15 + 8000976: f000 f80d bl 8000994 + 800097a: 4603 mov r3, r0 + 800097c: 2b00 cmp r3, #0 + 800097e: d002 beq.n 8000986 + { + status = HAL_ERROR; + 8000980: 2301 movs r3, #1 + 8000982: 71fb strb r3, [r7, #7] + 8000984: e001 b.n 800098a + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000986: f7ff fea7 bl 80006d8 + } + + /* Return function status */ + return status; + 800098a: 79fb ldrb r3, [r7, #7] +} + 800098c: 4618 mov r0, r3 + 800098e: 3708 adds r7, #8 + 8000990: 46bd mov sp, r7 + 8000992: bd80 pop {r7, pc} + +08000994 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000994: b580 push {r7, lr} + 8000996: b084 sub sp, #16 + 8000998: af00 add r7, sp, #0 + 800099a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 800099c: 2300 movs r3, #0 + 800099e: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 80009a0: 4b16 ldr r3, [pc, #88] @ (80009fc ) + 80009a2: 681b ldr r3, [r3, #0] + 80009a4: 2b00 cmp r3, #0 + 80009a6: d022 beq.n 80009ee + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 80009a8: 4b15 ldr r3, [pc, #84] @ (8000a00 ) + 80009aa: 681a ldr r2, [r3, #0] + 80009ac: 4b13 ldr r3, [pc, #76] @ (80009fc ) + 80009ae: 681b ldr r3, [r3, #0] + 80009b0: f44f 717a mov.w r1, #1000 @ 0x3e8 + 80009b4: fbb1 f3f3 udiv r3, r1, r3 + 80009b8: fbb2 f3f3 udiv r3, r2, r3 + 80009bc: 4618 mov r0, r3 + 80009be: f000 f938 bl 8000c32 + 80009c2: 4603 mov r3, r0 + 80009c4: 2b00 cmp r3, #0 + 80009c6: d10f bne.n 80009e8 + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 80009c8: 687b ldr r3, [r7, #4] + 80009ca: 2b0f cmp r3, #15 + 80009cc: d809 bhi.n 80009e2 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 80009ce: 2200 movs r2, #0 + 80009d0: 6879 ldr r1, [r7, #4] + 80009d2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80009d6: f000 f910 bl 8000bfa + uwTickPrio = TickPriority; + 80009da: 4a0a ldr r2, [pc, #40] @ (8000a04 ) + 80009dc: 687b ldr r3, [r7, #4] + 80009de: 6013 str r3, [r2, #0] + 80009e0: e007 b.n 80009f2 + } + else + { + status = HAL_ERROR; + 80009e2: 2301 movs r3, #1 + 80009e4: 73fb strb r3, [r7, #15] + 80009e6: e004 b.n 80009f2 + } + } + else + { + status = HAL_ERROR; + 80009e8: 2301 movs r3, #1 + 80009ea: 73fb strb r3, [r7, #15] + 80009ec: e001 b.n 80009f2 + } + } + else + { + status = HAL_ERROR; + 80009ee: 2301 movs r3, #1 + 80009f0: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 80009f2: 7bfb ldrb r3, [r7, #15] +} + 80009f4: 4618 mov r0, r3 + 80009f6: 3710 adds r7, #16 + 80009f8: 46bd mov sp, r7 + 80009fa: bd80 pop {r7, pc} + 80009fc: 20000008 .word 0x20000008 + 8000a00: 20000000 .word 0x20000000 + 8000a04: 20000004 .word 0x20000004 + +08000a08 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000a08: b480 push {r7} + 8000a0a: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000a0c: 4b05 ldr r3, [pc, #20] @ (8000a24 ) + 8000a0e: 681a ldr r2, [r3, #0] + 8000a10: 4b05 ldr r3, [pc, #20] @ (8000a28 ) + 8000a12: 681b ldr r3, [r3, #0] + 8000a14: 4413 add r3, r2 + 8000a16: 4a03 ldr r2, [pc, #12] @ (8000a24 ) + 8000a18: 6013 str r3, [r2, #0] +} + 8000a1a: bf00 nop + 8000a1c: 46bd mov sp, r7 + 8000a1e: bc80 pop {r7} + 8000a20: 4770 bx lr + 8000a22: bf00 nop + 8000a24: 20000080 .word 0x20000080 + 8000a28: 20000008 .word 0x20000008 + +08000a2c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000a2c: b480 push {r7} + 8000a2e: af00 add r7, sp, #0 + return uwTick; + 8000a30: 4b02 ldr r3, [pc, #8] @ (8000a3c ) + 8000a32: 681b ldr r3, [r3, #0] +} + 8000a34: 4618 mov r0, r3 + 8000a36: 46bd mov sp, r7 + 8000a38: bc80 pop {r7} + 8000a3a: 4770 bx lr + 8000a3c: 20000080 .word 0x20000080 + +08000a40 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000a40: b580 push {r7, lr} + 8000a42: b084 sub sp, #16 + 8000a44: af00 add r7, sp, #0 + 8000a46: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8000a48: f7ff fff0 bl 8000a2c + 8000a4c: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8000a4e: 687b ldr r3, [r7, #4] + 8000a50: 60fb str r3, [r7, #12] + + /* Add a period to guaranty minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000a52: 68fb ldr r3, [r7, #12] + 8000a54: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8000a58: d004 beq.n 8000a64 + { + wait += (uint32_t)(uwTickFreq); + 8000a5a: 4b09 ldr r3, [pc, #36] @ (8000a80 ) + 8000a5c: 681b ldr r3, [r3, #0] + 8000a5e: 68fa ldr r2, [r7, #12] + 8000a60: 4413 add r3, r2 + 8000a62: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 8000a64: bf00 nop + 8000a66: f7ff ffe1 bl 8000a2c + 8000a6a: 4602 mov r2, r0 + 8000a6c: 68bb ldr r3, [r7, #8] + 8000a6e: 1ad3 subs r3, r2, r3 + 8000a70: 68fa ldr r2, [r7, #12] + 8000a72: 429a cmp r2, r3 + 8000a74: d8f7 bhi.n 8000a66 + { + } +} + 8000a76: bf00 nop + 8000a78: bf00 nop + 8000a7a: 3710 adds r7, #16 + 8000a7c: 46bd mov sp, r7 + 8000a7e: bd80 pop {r7, pc} + 8000a80: 20000008 .word 0x20000008 + +08000a84 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000a84: b480 push {r7} + 8000a86: b085 sub sp, #20 + 8000a88: af00 add r7, sp, #0 + 8000a8a: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000a8c: 687b ldr r3, [r7, #4] + 8000a8e: f003 0307 and.w r3, r3, #7 + 8000a92: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000a94: 4b0c ldr r3, [pc, #48] @ (8000ac8 <__NVIC_SetPriorityGrouping+0x44>) + 8000a96: 68db ldr r3, [r3, #12] + 8000a98: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000a9a: 68ba ldr r2, [r7, #8] + 8000a9c: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000aa0: 4013 ands r3, r2 + 8000aa2: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000aa4: 68fb ldr r3, [r7, #12] + 8000aa6: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000aa8: 68bb ldr r3, [r7, #8] + 8000aaa: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000aac: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000ab0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000ab4: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000ab6: 4a04 ldr r2, [pc, #16] @ (8000ac8 <__NVIC_SetPriorityGrouping+0x44>) + 8000ab8: 68bb ldr r3, [r7, #8] + 8000aba: 60d3 str r3, [r2, #12] +} + 8000abc: bf00 nop + 8000abe: 3714 adds r7, #20 + 8000ac0: 46bd mov sp, r7 + 8000ac2: bc80 pop {r7} + 8000ac4: 4770 bx lr + 8000ac6: bf00 nop + 8000ac8: e000ed00 .word 0xe000ed00 + +08000acc <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000acc: b480 push {r7} + 8000ace: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000ad0: 4b04 ldr r3, [pc, #16] @ (8000ae4 <__NVIC_GetPriorityGrouping+0x18>) + 8000ad2: 68db ldr r3, [r3, #12] + 8000ad4: 0a1b lsrs r3, r3, #8 + 8000ad6: f003 0307 and.w r3, r3, #7 +} + 8000ada: 4618 mov r0, r3 + 8000adc: 46bd mov sp, r7 + 8000ade: bc80 pop {r7} + 8000ae0: 4770 bx lr + 8000ae2: bf00 nop + 8000ae4: e000ed00 .word 0xe000ed00 + +08000ae8 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000ae8: b480 push {r7} + 8000aea: b083 sub sp, #12 + 8000aec: af00 add r7, sp, #0 + 8000aee: 4603 mov r3, r0 + 8000af0: 6039 str r1, [r7, #0] + 8000af2: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000af4: f997 3007 ldrsb.w r3, [r7, #7] + 8000af8: 2b00 cmp r3, #0 + 8000afa: db0a blt.n 8000b12 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000afc: 683b ldr r3, [r7, #0] + 8000afe: b2da uxtb r2, r3 + 8000b00: 490c ldr r1, [pc, #48] @ (8000b34 <__NVIC_SetPriority+0x4c>) + 8000b02: f997 3007 ldrsb.w r3, [r7, #7] + 8000b06: 0112 lsls r2, r2, #4 + 8000b08: b2d2 uxtb r2, r2 + 8000b0a: 440b add r3, r1 + 8000b0c: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000b10: e00a b.n 8000b28 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000b12: 683b ldr r3, [r7, #0] + 8000b14: b2da uxtb r2, r3 + 8000b16: 4908 ldr r1, [pc, #32] @ (8000b38 <__NVIC_SetPriority+0x50>) + 8000b18: 79fb ldrb r3, [r7, #7] + 8000b1a: f003 030f and.w r3, r3, #15 + 8000b1e: 3b04 subs r3, #4 + 8000b20: 0112 lsls r2, r2, #4 + 8000b22: b2d2 uxtb r2, r2 + 8000b24: 440b add r3, r1 + 8000b26: 761a strb r2, [r3, #24] +} + 8000b28: bf00 nop + 8000b2a: 370c adds r7, #12 + 8000b2c: 46bd mov sp, r7 + 8000b2e: bc80 pop {r7} + 8000b30: 4770 bx lr + 8000b32: bf00 nop + 8000b34: e000e100 .word 0xe000e100 + 8000b38: e000ed00 .word 0xe000ed00 + +08000b3c : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000b3c: b480 push {r7} + 8000b3e: b089 sub sp, #36 @ 0x24 + 8000b40: af00 add r7, sp, #0 + 8000b42: 60f8 str r0, [r7, #12] + 8000b44: 60b9 str r1, [r7, #8] + 8000b46: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000b48: 68fb ldr r3, [r7, #12] + 8000b4a: f003 0307 and.w r3, r3, #7 + 8000b4e: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000b50: 69fb ldr r3, [r7, #28] + 8000b52: f1c3 0307 rsb r3, r3, #7 + 8000b56: 2b04 cmp r3, #4 + 8000b58: bf28 it cs + 8000b5a: 2304 movcs r3, #4 + 8000b5c: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000b5e: 69fb ldr r3, [r7, #28] + 8000b60: 3304 adds r3, #4 + 8000b62: 2b06 cmp r3, #6 + 8000b64: d902 bls.n 8000b6c + 8000b66: 69fb ldr r3, [r7, #28] + 8000b68: 3b03 subs r3, #3 + 8000b6a: e000 b.n 8000b6e + 8000b6c: 2300 movs r3, #0 + 8000b6e: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000b70: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000b74: 69bb ldr r3, [r7, #24] + 8000b76: fa02 f303 lsl.w r3, r2, r3 + 8000b7a: 43da mvns r2, r3 + 8000b7c: 68bb ldr r3, [r7, #8] + 8000b7e: 401a ands r2, r3 + 8000b80: 697b ldr r3, [r7, #20] + 8000b82: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000b84: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000b88: 697b ldr r3, [r7, #20] + 8000b8a: fa01 f303 lsl.w r3, r1, r3 + 8000b8e: 43d9 mvns r1, r3 + 8000b90: 687b ldr r3, [r7, #4] + 8000b92: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000b94: 4313 orrs r3, r2 + ); +} + 8000b96: 4618 mov r0, r3 + 8000b98: 3724 adds r7, #36 @ 0x24 + 8000b9a: 46bd mov sp, r7 + 8000b9c: bc80 pop {r7} + 8000b9e: 4770 bx lr + +08000ba0 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000ba0: b580 push {r7, lr} + 8000ba2: b082 sub sp, #8 + 8000ba4: af00 add r7, sp, #0 + 8000ba6: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000ba8: 687b ldr r3, [r7, #4] + 8000baa: 3b01 subs r3, #1 + 8000bac: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000bb0: d301 bcc.n 8000bb6 + { + return (1UL); /* Reload value impossible */ + 8000bb2: 2301 movs r3, #1 + 8000bb4: e00f b.n 8000bd6 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000bb6: 4a0a ldr r2, [pc, #40] @ (8000be0 ) + 8000bb8: 687b ldr r3, [r7, #4] + 8000bba: 3b01 subs r3, #1 + 8000bbc: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000bbe: 210f movs r1, #15 + 8000bc0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000bc4: f7ff ff90 bl 8000ae8 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000bc8: 4b05 ldr r3, [pc, #20] @ (8000be0 ) + 8000bca: 2200 movs r2, #0 + 8000bcc: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000bce: 4b04 ldr r3, [pc, #16] @ (8000be0 ) + 8000bd0: 2207 movs r2, #7 + 8000bd2: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000bd4: 2300 movs r3, #0 +} + 8000bd6: 4618 mov r0, r3 + 8000bd8: 3708 adds r7, #8 + 8000bda: 46bd mov sp, r7 + 8000bdc: bd80 pop {r7, pc} + 8000bde: bf00 nop + 8000be0: e000e010 .word 0xe000e010 + +08000be4 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000be4: b580 push {r7, lr} + 8000be6: b082 sub sp, #8 + 8000be8: af00 add r7, sp, #0 + 8000bea: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8000bec: 6878 ldr r0, [r7, #4] + 8000bee: f7ff ff49 bl 8000a84 <__NVIC_SetPriorityGrouping> +} + 8000bf2: bf00 nop + 8000bf4: 3708 adds r7, #8 + 8000bf6: 46bd mov sp, r7 + 8000bf8: bd80 pop {r7, pc} + +08000bfa : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000bfa: b580 push {r7, lr} + 8000bfc: b086 sub sp, #24 + 8000bfe: af00 add r7, sp, #0 + 8000c00: 4603 mov r3, r0 + 8000c02: 60b9 str r1, [r7, #8] + 8000c04: 607a str r2, [r7, #4] + 8000c06: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8000c08: 2300 movs r3, #0 + 8000c0a: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8000c0c: f7ff ff5e bl 8000acc <__NVIC_GetPriorityGrouping> + 8000c10: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8000c12: 687a ldr r2, [r7, #4] + 8000c14: 68b9 ldr r1, [r7, #8] + 8000c16: 6978 ldr r0, [r7, #20] + 8000c18: f7ff ff90 bl 8000b3c + 8000c1c: 4602 mov r2, r0 + 8000c1e: f997 300f ldrsb.w r3, [r7, #15] + 8000c22: 4611 mov r1, r2 + 8000c24: 4618 mov r0, r3 + 8000c26: f7ff ff5f bl 8000ae8 <__NVIC_SetPriority> +} + 8000c2a: bf00 nop + 8000c2c: 3718 adds r7, #24 + 8000c2e: 46bd mov sp, r7 + 8000c30: bd80 pop {r7, pc} + +08000c32 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000c32: b580 push {r7, lr} + 8000c34: b082 sub sp, #8 + 8000c36: af00 add r7, sp, #0 + 8000c38: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000c3a: 6878 ldr r0, [r7, #4] + 8000c3c: f7ff ffb0 bl 8000ba0 + 8000c40: 4603 mov r3, r0 +} + 8000c42: 4618 mov r0, r3 + 8000c44: 3708 adds r7, #8 + 8000c46: 46bd mov sp, r7 + 8000c48: bd80 pop {r7, pc} + ... + +08000c4c : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000c4c: b480 push {r7} + 8000c4e: b087 sub sp, #28 + 8000c50: af00 add r7, sp, #0 + 8000c52: 6078 str r0, [r7, #4] + 8000c54: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8000c56: 2300 movs r3, #0 + 8000c58: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8000c5a: 2300 movs r3, #0 + 8000c5c: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 8000c5e: 2300 movs r3, #0 + 8000c60: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8000c62: e160 b.n 8000f26 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8000c64: 683b ldr r3, [r7, #0] + 8000c66: 681a ldr r2, [r3, #0] + 8000c68: 2101 movs r1, #1 + 8000c6a: 697b ldr r3, [r7, #20] + 8000c6c: fa01 f303 lsl.w r3, r1, r3 + 8000c70: 4013 ands r3, r2 + 8000c72: 60fb str r3, [r7, #12] + + if (iocurrent) + 8000c74: 68fb ldr r3, [r7, #12] + 8000c76: 2b00 cmp r3, #0 + 8000c78: f000 8152 beq.w 8000f20 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000c7c: 683b ldr r3, [r7, #0] + 8000c7e: 685b ldr r3, [r3, #4] + 8000c80: f003 0303 and.w r3, r3, #3 + 8000c84: 2b01 cmp r3, #1 + 8000c86: d005 beq.n 8000c94 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8000c88: 683b ldr r3, [r7, #0] + 8000c8a: 685b ldr r3, [r3, #4] + 8000c8c: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000c90: 2b02 cmp r3, #2 + 8000c92: d130 bne.n 8000cf6 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8000c94: 687b ldr r3, [r7, #4] + 8000c96: 689b ldr r3, [r3, #8] + 8000c98: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8000c9a: 697b ldr r3, [r7, #20] + 8000c9c: 005b lsls r3, r3, #1 + 8000c9e: 2203 movs r2, #3 + 8000ca0: fa02 f303 lsl.w r3, r2, r3 + 8000ca4: 43db mvns r3, r3 + 8000ca6: 693a ldr r2, [r7, #16] + 8000ca8: 4013 ands r3, r2 + 8000caa: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8000cac: 683b ldr r3, [r7, #0] + 8000cae: 68da ldr r2, [r3, #12] + 8000cb0: 697b ldr r3, [r7, #20] + 8000cb2: 005b lsls r3, r3, #1 + 8000cb4: fa02 f303 lsl.w r3, r2, r3 + 8000cb8: 693a ldr r2, [r7, #16] + 8000cba: 4313 orrs r3, r2 + 8000cbc: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8000cbe: 687b ldr r3, [r7, #4] + 8000cc0: 693a ldr r2, [r7, #16] + 8000cc2: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8000cc4: 687b ldr r3, [r7, #4] + 8000cc6: 685b ldr r3, [r3, #4] + 8000cc8: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 8000cca: 2201 movs r2, #1 + 8000ccc: 697b ldr r3, [r7, #20] + 8000cce: fa02 f303 lsl.w r3, r2, r3 + 8000cd2: 43db mvns r3, r3 + 8000cd4: 693a ldr r2, [r7, #16] + 8000cd6: 4013 ands r3, r2 + 8000cd8: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8000cda: 683b ldr r3, [r7, #0] + 8000cdc: 685b ldr r3, [r3, #4] + 8000cde: 091b lsrs r3, r3, #4 + 8000ce0: f003 0201 and.w r2, r3, #1 + 8000ce4: 697b ldr r3, [r7, #20] + 8000ce6: fa02 f303 lsl.w r3, r2, r3 + 8000cea: 693a ldr r2, [r7, #16] + 8000cec: 4313 orrs r3, r2 + 8000cee: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8000cf0: 687b ldr r3, [r7, #4] + 8000cf2: 693a ldr r2, [r7, #16] + 8000cf4: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8000cf6: 683b ldr r3, [r7, #0] + 8000cf8: 685b ldr r3, [r3, #4] + 8000cfa: f003 0303 and.w r3, r3, #3 + 8000cfe: 2b03 cmp r3, #3 + 8000d00: d017 beq.n 8000d32 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8000d02: 687b ldr r3, [r7, #4] + 8000d04: 68db ldr r3, [r3, #12] + 8000d06: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 8000d08: 697b ldr r3, [r7, #20] + 8000d0a: 005b lsls r3, r3, #1 + 8000d0c: 2203 movs r2, #3 + 8000d0e: fa02 f303 lsl.w r3, r2, r3 + 8000d12: 43db mvns r3, r3 + 8000d14: 693a ldr r2, [r7, #16] + 8000d16: 4013 ands r3, r2 + 8000d18: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 8000d1a: 683b ldr r3, [r7, #0] + 8000d1c: 689a ldr r2, [r3, #8] + 8000d1e: 697b ldr r3, [r7, #20] + 8000d20: 005b lsls r3, r3, #1 + 8000d22: fa02 f303 lsl.w r3, r2, r3 + 8000d26: 693a ldr r2, [r7, #16] + 8000d28: 4313 orrs r3, r2 + 8000d2a: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8000d2c: 687b ldr r3, [r7, #4] + 8000d2e: 693a ldr r2, [r7, #16] + 8000d30: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8000d32: 683b ldr r3, [r7, #0] + 8000d34: 685b ldr r3, [r3, #4] + 8000d36: f003 0303 and.w r3, r3, #3 + 8000d3a: 2b02 cmp r3, #2 + 8000d3c: d123 bne.n 8000d86 + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 8000d3e: 697b ldr r3, [r7, #20] + 8000d40: 08da lsrs r2, r3, #3 + 8000d42: 687b ldr r3, [r7, #4] + 8000d44: 3208 adds r2, #8 + 8000d46: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8000d4a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 8000d4c: 697b ldr r3, [r7, #20] + 8000d4e: f003 0307 and.w r3, r3, #7 + 8000d52: 009b lsls r3, r3, #2 + 8000d54: 220f movs r2, #15 + 8000d56: fa02 f303 lsl.w r3, r2, r3 + 8000d5a: 43db mvns r3, r3 + 8000d5c: 693a ldr r2, [r7, #16] + 8000d5e: 4013 ands r3, r2 + 8000d60: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8000d62: 683b ldr r3, [r7, #0] + 8000d64: 691a ldr r2, [r3, #16] + 8000d66: 697b ldr r3, [r7, #20] + 8000d68: f003 0307 and.w r3, r3, #7 + 8000d6c: 009b lsls r3, r3, #2 + 8000d6e: fa02 f303 lsl.w r3, r2, r3 + 8000d72: 693a ldr r2, [r7, #16] + 8000d74: 4313 orrs r3, r2 + 8000d76: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 8000d78: 697b ldr r3, [r7, #20] + 8000d7a: 08da lsrs r2, r3, #3 + 8000d7c: 687b ldr r3, [r7, #4] + 8000d7e: 3208 adds r2, #8 + 8000d80: 6939 ldr r1, [r7, #16] + 8000d82: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8000d86: 687b ldr r3, [r7, #4] + 8000d88: 681b ldr r3, [r3, #0] + 8000d8a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8000d8c: 697b ldr r3, [r7, #20] + 8000d8e: 005b lsls r3, r3, #1 + 8000d90: 2203 movs r2, #3 + 8000d92: fa02 f303 lsl.w r3, r2, r3 + 8000d96: 43db mvns r3, r3 + 8000d98: 693a ldr r2, [r7, #16] + 8000d9a: 4013 ands r3, r2 + 8000d9c: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8000d9e: 683b ldr r3, [r7, #0] + 8000da0: 685b ldr r3, [r3, #4] + 8000da2: f003 0203 and.w r2, r3, #3 + 8000da6: 697b ldr r3, [r7, #20] + 8000da8: 005b lsls r3, r3, #1 + 8000daa: fa02 f303 lsl.w r3, r2, r3 + 8000dae: 693a ldr r2, [r7, #16] + 8000db0: 4313 orrs r3, r2 + 8000db2: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8000db4: 687b ldr r3, [r7, #4] + 8000db6: 693a ldr r2, [r7, #16] + 8000db8: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8000dba: 683b ldr r3, [r7, #0] + 8000dbc: 685b ldr r3, [r3, #4] + 8000dbe: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8000dc2: 2b00 cmp r3, #0 + 8000dc4: f000 80ac beq.w 8000f20 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000dc8: 4b5e ldr r3, [pc, #376] @ (8000f44 ) + 8000dca: 6a1b ldr r3, [r3, #32] + 8000dcc: 4a5d ldr r2, [pc, #372] @ (8000f44 ) + 8000dce: f043 0301 orr.w r3, r3, #1 + 8000dd2: 6213 str r3, [r2, #32] + 8000dd4: 4b5b ldr r3, [pc, #364] @ (8000f44 ) + 8000dd6: 6a1b ldr r3, [r3, #32] + 8000dd8: f003 0301 and.w r3, r3, #1 + 8000ddc: 60bb str r3, [r7, #8] + 8000dde: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8000de0: 4a59 ldr r2, [pc, #356] @ (8000f48 ) + 8000de2: 697b ldr r3, [r7, #20] + 8000de4: 089b lsrs r3, r3, #2 + 8000de6: 3302 adds r3, #2 + 8000de8: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8000dec: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 8000dee: 697b ldr r3, [r7, #20] + 8000df0: f003 0303 and.w r3, r3, #3 + 8000df4: 009b lsls r3, r3, #2 + 8000df6: 220f movs r2, #15 + 8000df8: fa02 f303 lsl.w r3, r2, r3 + 8000dfc: 43db mvns r3, r3 + 8000dfe: 693a ldr r2, [r7, #16] + 8000e00: 4013 ands r3, r2 + 8000e02: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 8000e04: 687b ldr r3, [r7, #4] + 8000e06: 4a51 ldr r2, [pc, #324] @ (8000f4c ) + 8000e08: 4293 cmp r3, r2 + 8000e0a: d025 beq.n 8000e58 + 8000e0c: 687b ldr r3, [r7, #4] + 8000e0e: 4a50 ldr r2, [pc, #320] @ (8000f50 ) + 8000e10: 4293 cmp r3, r2 + 8000e12: d01f beq.n 8000e54 + 8000e14: 687b ldr r3, [r7, #4] + 8000e16: 4a4f ldr r2, [pc, #316] @ (8000f54 ) + 8000e18: 4293 cmp r3, r2 + 8000e1a: d019 beq.n 8000e50 + 8000e1c: 687b ldr r3, [r7, #4] + 8000e1e: 4a4e ldr r2, [pc, #312] @ (8000f58 ) + 8000e20: 4293 cmp r3, r2 + 8000e22: d013 beq.n 8000e4c + 8000e24: 687b ldr r3, [r7, #4] + 8000e26: 4a4d ldr r2, [pc, #308] @ (8000f5c ) + 8000e28: 4293 cmp r3, r2 + 8000e2a: d00d beq.n 8000e48 + 8000e2c: 687b ldr r3, [r7, #4] + 8000e2e: 4a4c ldr r2, [pc, #304] @ (8000f60 ) + 8000e30: 4293 cmp r3, r2 + 8000e32: d007 beq.n 8000e44 + 8000e34: 687b ldr r3, [r7, #4] + 8000e36: 4a4b ldr r2, [pc, #300] @ (8000f64 ) + 8000e38: 4293 cmp r3, r2 + 8000e3a: d101 bne.n 8000e40 + 8000e3c: 2306 movs r3, #6 + 8000e3e: e00c b.n 8000e5a + 8000e40: 2307 movs r3, #7 + 8000e42: e00a b.n 8000e5a + 8000e44: 2305 movs r3, #5 + 8000e46: e008 b.n 8000e5a + 8000e48: 2304 movs r3, #4 + 8000e4a: e006 b.n 8000e5a + 8000e4c: 2303 movs r3, #3 + 8000e4e: e004 b.n 8000e5a + 8000e50: 2302 movs r3, #2 + 8000e52: e002 b.n 8000e5a + 8000e54: 2301 movs r3, #1 + 8000e56: e000 b.n 8000e5a + 8000e58: 2300 movs r3, #0 + 8000e5a: 697a ldr r2, [r7, #20] + 8000e5c: f002 0203 and.w r2, r2, #3 + 8000e60: 0092 lsls r2, r2, #2 + 8000e62: 4093 lsls r3, r2 + 8000e64: 693a ldr r2, [r7, #16] + 8000e66: 4313 orrs r3, r2 + 8000e68: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 8000e6a: 4937 ldr r1, [pc, #220] @ (8000f48 ) + 8000e6c: 697b ldr r3, [r7, #20] + 8000e6e: 089b lsrs r3, r3, #2 + 8000e70: 3302 adds r3, #2 + 8000e72: 693a ldr r2, [r7, #16] + 8000e74: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8000e78: 4b3b ldr r3, [pc, #236] @ (8000f68 ) + 8000e7a: 689b ldr r3, [r3, #8] + 8000e7c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000e7e: 68fb ldr r3, [r7, #12] + 8000e80: 43db mvns r3, r3 + 8000e82: 693a ldr r2, [r7, #16] + 8000e84: 4013 ands r3, r2 + 8000e86: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8000e88: 683b ldr r3, [r7, #0] + 8000e8a: 685b ldr r3, [r3, #4] + 8000e8c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8000e90: 2b00 cmp r3, #0 + 8000e92: d003 beq.n 8000e9c + { + SET_BIT(temp, iocurrent); + 8000e94: 693a ldr r2, [r7, #16] + 8000e96: 68fb ldr r3, [r7, #12] + 8000e98: 4313 orrs r3, r2 + 8000e9a: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 8000e9c: 4a32 ldr r2, [pc, #200] @ (8000f68 ) + 8000e9e: 693b ldr r3, [r7, #16] + 8000ea0: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8000ea2: 4b31 ldr r3, [pc, #196] @ (8000f68 ) + 8000ea4: 68db ldr r3, [r3, #12] + 8000ea6: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000ea8: 68fb ldr r3, [r7, #12] + 8000eaa: 43db mvns r3, r3 + 8000eac: 693a ldr r2, [r7, #16] + 8000eae: 4013 ands r3, r2 + 8000eb0: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8000eb2: 683b ldr r3, [r7, #0] + 8000eb4: 685b ldr r3, [r3, #4] + 8000eb6: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8000eba: 2b00 cmp r3, #0 + 8000ebc: d003 beq.n 8000ec6 + { + SET_BIT(temp, iocurrent); + 8000ebe: 693a ldr r2, [r7, #16] + 8000ec0: 68fb ldr r3, [r7, #12] + 8000ec2: 4313 orrs r3, r2 + 8000ec4: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 8000ec6: 4a28 ldr r2, [pc, #160] @ (8000f68 ) + 8000ec8: 693b ldr r3, [r7, #16] + 8000eca: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8000ecc: 4b26 ldr r3, [pc, #152] @ (8000f68 ) + 8000ece: 685b ldr r3, [r3, #4] + 8000ed0: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000ed2: 68fb ldr r3, [r7, #12] + 8000ed4: 43db mvns r3, r3 + 8000ed6: 693a ldr r2, [r7, #16] + 8000ed8: 4013 ands r3, r2 + 8000eda: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8000edc: 683b ldr r3, [r7, #0] + 8000ede: 685b ldr r3, [r3, #4] + 8000ee0: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8000ee4: 2b00 cmp r3, #0 + 8000ee6: d003 beq.n 8000ef0 + { + SET_BIT(temp, iocurrent); + 8000ee8: 693a ldr r2, [r7, #16] + 8000eea: 68fb ldr r3, [r7, #12] + 8000eec: 4313 orrs r3, r2 + 8000eee: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8000ef0: 4a1d ldr r2, [pc, #116] @ (8000f68 ) + 8000ef2: 693b ldr r3, [r7, #16] + 8000ef4: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8000ef6: 4b1c ldr r3, [pc, #112] @ (8000f68 ) + 8000ef8: 681b ldr r3, [r3, #0] + 8000efa: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8000efc: 68fb ldr r3, [r7, #12] + 8000efe: 43db mvns r3, r3 + 8000f00: 693a ldr r2, [r7, #16] + 8000f02: 4013 ands r3, r2 + 8000f04: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 8000f06: 683b ldr r3, [r7, #0] + 8000f08: 685b ldr r3, [r3, #4] + 8000f0a: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8000f0e: 2b00 cmp r3, #0 + 8000f10: d003 beq.n 8000f1a + { + SET_BIT(temp, iocurrent); + 8000f12: 693a ldr r2, [r7, #16] + 8000f14: 68fb ldr r3, [r7, #12] + 8000f16: 4313 orrs r3, r2 + 8000f18: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 8000f1a: 4a13 ldr r2, [pc, #76] @ (8000f68 ) + 8000f1c: 693b ldr r3, [r7, #16] + 8000f1e: 6013 str r3, [r2, #0] + } + } + + position++; + 8000f20: 697b ldr r3, [r7, #20] + 8000f22: 3301 adds r3, #1 + 8000f24: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 8000f26: 683b ldr r3, [r7, #0] + 8000f28: 681a ldr r2, [r3, #0] + 8000f2a: 697b ldr r3, [r7, #20] + 8000f2c: fa22 f303 lsr.w r3, r2, r3 + 8000f30: 2b00 cmp r3, #0 + 8000f32: f47f ae97 bne.w 8000c64 + } +} + 8000f36: bf00 nop + 8000f38: bf00 nop + 8000f3a: 371c adds r7, #28 + 8000f3c: 46bd mov sp, r7 + 8000f3e: bc80 pop {r7} + 8000f40: 4770 bx lr + 8000f42: bf00 nop + 8000f44: 40023800 .word 0x40023800 + 8000f48: 40010000 .word 0x40010000 + 8000f4c: 40020000 .word 0x40020000 + 8000f50: 40020400 .word 0x40020400 + 8000f54: 40020800 .word 0x40020800 + 8000f58: 40020c00 .word 0x40020c00 + 8000f5c: 40021000 .word 0x40021000 + 8000f60: 40021400 .word 0x40021400 + 8000f64: 40021800 .word 0x40021800 + 8000f68: 40010400 .word 0x40010400 + +08000f6c : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8000f6c: b480 push {r7} + 8000f6e: b083 sub sp, #12 + 8000f70: af00 add r7, sp, #0 + 8000f72: 6078 str r0, [r7, #4] + 8000f74: 460b mov r3, r1 + 8000f76: 807b strh r3, [r7, #2] + 8000f78: 4613 mov r3, r2 + 8000f7a: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8000f7c: 787b ldrb r3, [r7, #1] + 8000f7e: 2b00 cmp r3, #0 + 8000f80: d003 beq.n 8000f8a + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8000f82: 887a ldrh r2, [r7, #2] + 8000f84: 687b ldr r3, [r7, #4] + 8000f86: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 8000f88: e003 b.n 8000f92 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 8000f8a: 887b ldrh r3, [r7, #2] + 8000f8c: 041a lsls r2, r3, #16 + 8000f8e: 687b ldr r3, [r7, #4] + 8000f90: 619a str r2, [r3, #24] +} + 8000f92: bf00 nop + 8000f94: 370c adds r7, #12 + 8000f96: 46bd mov sp, r7 + 8000f98: bc80 pop {r7} + 8000f9a: 4770 bx lr + +08000f9c : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8000f9c: b580 push {r7, lr} + 8000f9e: b088 sub sp, #32 + 8000fa0: af00 add r7, sp, #0 + 8000fa2: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 8000fa4: 687b ldr r3, [r7, #4] + 8000fa6: 2b00 cmp r3, #0 + 8000fa8: d101 bne.n 8000fae + { + return HAL_ERROR; + 8000faa: 2301 movs r3, #1 + 8000fac: e31d b.n 80015ea + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8000fae: 4b94 ldr r3, [pc, #592] @ (8001200 ) + 8000fb0: 689b ldr r3, [r3, #8] + 8000fb2: f003 030c and.w r3, r3, #12 + 8000fb6: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8000fb8: 4b91 ldr r3, [pc, #580] @ (8001200 ) + 8000fba: 689b ldr r3, [r3, #8] + 8000fbc: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8000fc0: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8000fc2: 687b ldr r3, [r7, #4] + 8000fc4: 681b ldr r3, [r3, #0] + 8000fc6: f003 0301 and.w r3, r3, #1 + 8000fca: 2b00 cmp r3, #0 + 8000fcc: d07b beq.n 80010c6 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 8000fce: 69bb ldr r3, [r7, #24] + 8000fd0: 2b08 cmp r3, #8 + 8000fd2: d006 beq.n 8000fe2 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8000fd4: 69bb ldr r3, [r7, #24] + 8000fd6: 2b0c cmp r3, #12 + 8000fd8: d10f bne.n 8000ffa + 8000fda: 697b ldr r3, [r7, #20] + 8000fdc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8000fe0: d10b bne.n 8000ffa + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8000fe2: 4b87 ldr r3, [pc, #540] @ (8001200 ) + 8000fe4: 681b ldr r3, [r3, #0] + 8000fe6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8000fea: 2b00 cmp r3, #0 + 8000fec: d06a beq.n 80010c4 + 8000fee: 687b ldr r3, [r7, #4] + 8000ff0: 685b ldr r3, [r3, #4] + 8000ff2: 2b00 cmp r3, #0 + 8000ff4: d166 bne.n 80010c4 + { + return HAL_ERROR; + 8000ff6: 2301 movs r3, #1 + 8000ff8: e2f7 b.n 80015ea + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8000ffa: 687b ldr r3, [r7, #4] + 8000ffc: 685b ldr r3, [r3, #4] + 8000ffe: 2b01 cmp r3, #1 + 8001000: d106 bne.n 8001010 + 8001002: 4b7f ldr r3, [pc, #508] @ (8001200 ) + 8001004: 681b ldr r3, [r3, #0] + 8001006: 4a7e ldr r2, [pc, #504] @ (8001200 ) + 8001008: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 800100c: 6013 str r3, [r2, #0] + 800100e: e02d b.n 800106c + 8001010: 687b ldr r3, [r7, #4] + 8001012: 685b ldr r3, [r3, #4] + 8001014: 2b00 cmp r3, #0 + 8001016: d10c bne.n 8001032 + 8001018: 4b79 ldr r3, [pc, #484] @ (8001200 ) + 800101a: 681b ldr r3, [r3, #0] + 800101c: 4a78 ldr r2, [pc, #480] @ (8001200 ) + 800101e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001022: 6013 str r3, [r2, #0] + 8001024: 4b76 ldr r3, [pc, #472] @ (8001200 ) + 8001026: 681b ldr r3, [r3, #0] + 8001028: 4a75 ldr r2, [pc, #468] @ (8001200 ) + 800102a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 800102e: 6013 str r3, [r2, #0] + 8001030: e01c b.n 800106c + 8001032: 687b ldr r3, [r7, #4] + 8001034: 685b ldr r3, [r3, #4] + 8001036: 2b05 cmp r3, #5 + 8001038: d10c bne.n 8001054 + 800103a: 4b71 ldr r3, [pc, #452] @ (8001200 ) + 800103c: 681b ldr r3, [r3, #0] + 800103e: 4a70 ldr r2, [pc, #448] @ (8001200 ) + 8001040: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001044: 6013 str r3, [r2, #0] + 8001046: 4b6e ldr r3, [pc, #440] @ (8001200 ) + 8001048: 681b ldr r3, [r3, #0] + 800104a: 4a6d ldr r2, [pc, #436] @ (8001200 ) + 800104c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001050: 6013 str r3, [r2, #0] + 8001052: e00b b.n 800106c + 8001054: 4b6a ldr r3, [pc, #424] @ (8001200 ) + 8001056: 681b ldr r3, [r3, #0] + 8001058: 4a69 ldr r2, [pc, #420] @ (8001200 ) + 800105a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800105e: 6013 str r3, [r2, #0] + 8001060: 4b67 ldr r3, [pc, #412] @ (8001200 ) + 8001062: 681b ldr r3, [r3, #0] + 8001064: 4a66 ldr r2, [pc, #408] @ (8001200 ) + 8001066: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 800106a: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 800106c: 687b ldr r3, [r7, #4] + 800106e: 685b ldr r3, [r3, #4] + 8001070: 2b00 cmp r3, #0 + 8001072: d013 beq.n 800109c + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001074: f7ff fcda bl 8000a2c + 8001078: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800107a: e008 b.n 800108e + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 800107c: f7ff fcd6 bl 8000a2c + 8001080: 4602 mov r2, r0 + 8001082: 693b ldr r3, [r7, #16] + 8001084: 1ad3 subs r3, r2, r3 + 8001086: 2b64 cmp r3, #100 @ 0x64 + 8001088: d901 bls.n 800108e + { + return HAL_TIMEOUT; + 800108a: 2303 movs r3, #3 + 800108c: e2ad b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800108e: 4b5c ldr r3, [pc, #368] @ (8001200 ) + 8001090: 681b ldr r3, [r3, #0] + 8001092: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001096: 2b00 cmp r3, #0 + 8001098: d0f0 beq.n 800107c + 800109a: e014 b.n 80010c6 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800109c: f7ff fcc6 bl 8000a2c + 80010a0: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80010a2: e008 b.n 80010b6 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80010a4: f7ff fcc2 bl 8000a2c + 80010a8: 4602 mov r2, r0 + 80010aa: 693b ldr r3, [r7, #16] + 80010ac: 1ad3 subs r3, r2, r3 + 80010ae: 2b64 cmp r3, #100 @ 0x64 + 80010b0: d901 bls.n 80010b6 + { + return HAL_TIMEOUT; + 80010b2: 2303 movs r3, #3 + 80010b4: e299 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80010b6: 4b52 ldr r3, [pc, #328] @ (8001200 ) + 80010b8: 681b ldr r3, [r3, #0] + 80010ba: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80010be: 2b00 cmp r3, #0 + 80010c0: d1f0 bne.n 80010a4 + 80010c2: e000 b.n 80010c6 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80010c4: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80010c6: 687b ldr r3, [r7, #4] + 80010c8: 681b ldr r3, [r3, #0] + 80010ca: f003 0302 and.w r3, r3, #2 + 80010ce: 2b00 cmp r3, #0 + 80010d0: d05a beq.n 8001188 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 80010d2: 69bb ldr r3, [r7, #24] + 80010d4: 2b04 cmp r3, #4 + 80010d6: d005 beq.n 80010e4 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 80010d8: 69bb ldr r3, [r7, #24] + 80010da: 2b0c cmp r3, #12 + 80010dc: d119 bne.n 8001112 + 80010de: 697b ldr r3, [r7, #20] + 80010e0: 2b00 cmp r3, #0 + 80010e2: d116 bne.n 8001112 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80010e4: 4b46 ldr r3, [pc, #280] @ (8001200 ) + 80010e6: 681b ldr r3, [r3, #0] + 80010e8: f003 0302 and.w r3, r3, #2 + 80010ec: 2b00 cmp r3, #0 + 80010ee: d005 beq.n 80010fc + 80010f0: 687b ldr r3, [r7, #4] + 80010f2: 68db ldr r3, [r3, #12] + 80010f4: 2b01 cmp r3, #1 + 80010f6: d001 beq.n 80010fc + { + return HAL_ERROR; + 80010f8: 2301 movs r3, #1 + 80010fa: e276 b.n 80015ea + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80010fc: 4b40 ldr r3, [pc, #256] @ (8001200 ) + 80010fe: 685b ldr r3, [r3, #4] + 8001100: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001104: 687b ldr r3, [r7, #4] + 8001106: 691b ldr r3, [r3, #16] + 8001108: 021b lsls r3, r3, #8 + 800110a: 493d ldr r1, [pc, #244] @ (8001200 ) + 800110c: 4313 orrs r3, r2 + 800110e: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001110: e03a b.n 8001188 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8001112: 687b ldr r3, [r7, #4] + 8001114: 68db ldr r3, [r3, #12] + 8001116: 2b00 cmp r3, #0 + 8001118: d020 beq.n 800115c + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800111a: 4b3a ldr r3, [pc, #232] @ (8001204 ) + 800111c: 2201 movs r2, #1 + 800111e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001120: f7ff fc84 bl 8000a2c + 8001124: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001126: e008 b.n 800113a + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001128: f7ff fc80 bl 8000a2c + 800112c: 4602 mov r2, r0 + 800112e: 693b ldr r3, [r7, #16] + 8001130: 1ad3 subs r3, r2, r3 + 8001132: 2b02 cmp r3, #2 + 8001134: d901 bls.n 800113a + { + return HAL_TIMEOUT; + 8001136: 2303 movs r3, #3 + 8001138: e257 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800113a: 4b31 ldr r3, [pc, #196] @ (8001200 ) + 800113c: 681b ldr r3, [r3, #0] + 800113e: f003 0302 and.w r3, r3, #2 + 8001142: 2b00 cmp r3, #0 + 8001144: d0f0 beq.n 8001128 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001146: 4b2e ldr r3, [pc, #184] @ (8001200 ) + 8001148: 685b ldr r3, [r3, #4] + 800114a: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 800114e: 687b ldr r3, [r7, #4] + 8001150: 691b ldr r3, [r3, #16] + 8001152: 021b lsls r3, r3, #8 + 8001154: 492a ldr r1, [pc, #168] @ (8001200 ) + 8001156: 4313 orrs r3, r2 + 8001158: 604b str r3, [r1, #4] + 800115a: e015 b.n 8001188 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 800115c: 4b29 ldr r3, [pc, #164] @ (8001204 ) + 800115e: 2200 movs r2, #0 + 8001160: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001162: f7ff fc63 bl 8000a2c + 8001166: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001168: e008 b.n 800117c + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 800116a: f7ff fc5f bl 8000a2c + 800116e: 4602 mov r2, r0 + 8001170: 693b ldr r3, [r7, #16] + 8001172: 1ad3 subs r3, r2, r3 + 8001174: 2b02 cmp r3, #2 + 8001176: d901 bls.n 800117c + { + return HAL_TIMEOUT; + 8001178: 2303 movs r3, #3 + 800117a: e236 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 800117c: 4b20 ldr r3, [pc, #128] @ (8001200 ) + 800117e: 681b ldr r3, [r3, #0] + 8001180: f003 0302 and.w r3, r3, #2 + 8001184: 2b00 cmp r3, #0 + 8001186: d1f0 bne.n 800116a + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8001188: 687b ldr r3, [r7, #4] + 800118a: 681b ldr r3, [r3, #0] + 800118c: f003 0310 and.w r3, r3, #16 + 8001190: 2b00 cmp r3, #0 + 8001192: f000 80b8 beq.w 8001306 + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 8001196: 69bb ldr r3, [r7, #24] + 8001198: 2b00 cmp r3, #0 + 800119a: d170 bne.n 800127e + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 800119c: 4b18 ldr r3, [pc, #96] @ (8001200 ) + 800119e: 681b ldr r3, [r3, #0] + 80011a0: f403 7300 and.w r3, r3, #512 @ 0x200 + 80011a4: 2b00 cmp r3, #0 + 80011a6: d005 beq.n 80011b4 + 80011a8: 687b ldr r3, [r7, #4] + 80011aa: 699b ldr r3, [r3, #24] + 80011ac: 2b00 cmp r3, #0 + 80011ae: d101 bne.n 80011b4 + { + return HAL_ERROR; + 80011b0: 2301 movs r3, #1 + 80011b2: e21a b.n 80015ea + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 80011b4: 687b ldr r3, [r7, #4] + 80011b6: 6a1a ldr r2, [r3, #32] + 80011b8: 4b11 ldr r3, [pc, #68] @ (8001200 ) + 80011ba: 685b ldr r3, [r3, #4] + 80011bc: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 80011c0: 429a cmp r2, r3 + 80011c2: d921 bls.n 8001208 + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80011c4: 687b ldr r3, [r7, #4] + 80011c6: 6a1b ldr r3, [r3, #32] + 80011c8: 4618 mov r0, r3 + 80011ca: f000 fc09 bl 80019e0 + 80011ce: 4603 mov r3, r0 + 80011d0: 2b00 cmp r3, #0 + 80011d2: d001 beq.n 80011d8 + { + return HAL_ERROR; + 80011d4: 2301 movs r3, #1 + 80011d6: e208 b.n 80015ea + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80011d8: 4b09 ldr r3, [pc, #36] @ (8001200 ) + 80011da: 685b ldr r3, [r3, #4] + 80011dc: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80011e0: 687b ldr r3, [r7, #4] + 80011e2: 6a1b ldr r3, [r3, #32] + 80011e4: 4906 ldr r1, [pc, #24] @ (8001200 ) + 80011e6: 4313 orrs r3, r2 + 80011e8: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80011ea: 4b05 ldr r3, [pc, #20] @ (8001200 ) + 80011ec: 685b ldr r3, [r3, #4] + 80011ee: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80011f2: 687b ldr r3, [r7, #4] + 80011f4: 69db ldr r3, [r3, #28] + 80011f6: 061b lsls r3, r3, #24 + 80011f8: 4901 ldr r1, [pc, #4] @ (8001200 ) + 80011fa: 4313 orrs r3, r2 + 80011fc: 604b str r3, [r1, #4] + 80011fe: e020 b.n 8001242 + 8001200: 40023800 .word 0x40023800 + 8001204: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001208: 4b99 ldr r3, [pc, #612] @ (8001470 ) + 800120a: 685b ldr r3, [r3, #4] + 800120c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001210: 687b ldr r3, [r7, #4] + 8001212: 6a1b ldr r3, [r3, #32] + 8001214: 4996 ldr r1, [pc, #600] @ (8001470 ) + 8001216: 4313 orrs r3, r2 + 8001218: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800121a: 4b95 ldr r3, [pc, #596] @ (8001470 ) + 800121c: 685b ldr r3, [r3, #4] + 800121e: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001222: 687b ldr r3, [r7, #4] + 8001224: 69db ldr r3, [r3, #28] + 8001226: 061b lsls r3, r3, #24 + 8001228: 4991 ldr r1, [pc, #580] @ (8001470 ) + 800122a: 4313 orrs r3, r2 + 800122c: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 800122e: 687b ldr r3, [r7, #4] + 8001230: 6a1b ldr r3, [r3, #32] + 8001232: 4618 mov r0, r3 + 8001234: f000 fbd4 bl 80019e0 + 8001238: 4603 mov r3, r0 + 800123a: 2b00 cmp r3, #0 + 800123c: d001 beq.n 8001242 + { + return HAL_ERROR; + 800123e: 2301 movs r3, #1 + 8001240: e1d3 b.n 80015ea + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001242: 687b ldr r3, [r7, #4] + 8001244: 6a1b ldr r3, [r3, #32] + 8001246: 0b5b lsrs r3, r3, #13 + 8001248: 3301 adds r3, #1 + 800124a: f44f 4200 mov.w r2, #32768 @ 0x8000 + 800124e: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 8001252: 4a87 ldr r2, [pc, #540] @ (8001470 ) + 8001254: 6892 ldr r2, [r2, #8] + 8001256: 0912 lsrs r2, r2, #4 + 8001258: f002 020f and.w r2, r2, #15 + 800125c: 4985 ldr r1, [pc, #532] @ (8001474 ) + 800125e: 5c8a ldrb r2, [r1, r2] + 8001260: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001262: 4a85 ldr r2, [pc, #532] @ (8001478 ) + 8001264: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001266: 4b85 ldr r3, [pc, #532] @ (800147c ) + 8001268: 681b ldr r3, [r3, #0] + 800126a: 4618 mov r0, r3 + 800126c: f7ff fb92 bl 8000994 + 8001270: 4603 mov r3, r0 + 8001272: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 8001274: 7bfb ldrb r3, [r7, #15] + 8001276: 2b00 cmp r3, #0 + 8001278: d045 beq.n 8001306 + { + return status; + 800127a: 7bfb ldrb r3, [r7, #15] + 800127c: e1b5 b.n 80015ea + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 800127e: 687b ldr r3, [r7, #4] + 8001280: 699b ldr r3, [r3, #24] + 8001282: 2b00 cmp r3, #0 + 8001284: d029 beq.n 80012da + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 8001286: 4b7e ldr r3, [pc, #504] @ (8001480 ) + 8001288: 2201 movs r2, #1 + 800128a: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800128c: f7ff fbce bl 8000a2c + 8001290: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001292: e008 b.n 80012a6 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001294: f7ff fbca bl 8000a2c + 8001298: 4602 mov r2, r0 + 800129a: 693b ldr r3, [r7, #16] + 800129c: 1ad3 subs r3, r2, r3 + 800129e: 2b02 cmp r3, #2 + 80012a0: d901 bls.n 80012a6 + { + return HAL_TIMEOUT; + 80012a2: 2303 movs r3, #3 + 80012a4: e1a1 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80012a6: 4b72 ldr r3, [pc, #456] @ (8001470 ) + 80012a8: 681b ldr r3, [r3, #0] + 80012aa: f403 7300 and.w r3, r3, #512 @ 0x200 + 80012ae: 2b00 cmp r3, #0 + 80012b0: d0f0 beq.n 8001294 + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80012b2: 4b6f ldr r3, [pc, #444] @ (8001470 ) + 80012b4: 685b ldr r3, [r3, #4] + 80012b6: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80012ba: 687b ldr r3, [r7, #4] + 80012bc: 6a1b ldr r3, [r3, #32] + 80012be: 496c ldr r1, [pc, #432] @ (8001470 ) + 80012c0: 4313 orrs r3, r2 + 80012c2: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80012c4: 4b6a ldr r3, [pc, #424] @ (8001470 ) + 80012c6: 685b ldr r3, [r3, #4] + 80012c8: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80012cc: 687b ldr r3, [r7, #4] + 80012ce: 69db ldr r3, [r3, #28] + 80012d0: 061b lsls r3, r3, #24 + 80012d2: 4967 ldr r1, [pc, #412] @ (8001470 ) + 80012d4: 4313 orrs r3, r2 + 80012d6: 604b str r3, [r1, #4] + 80012d8: e015 b.n 8001306 + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 80012da: 4b69 ldr r3, [pc, #420] @ (8001480 ) + 80012dc: 2200 movs r2, #0 + 80012de: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80012e0: f7ff fba4 bl 8000a2c + 80012e4: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80012e6: e008 b.n 80012fa + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80012e8: f7ff fba0 bl 8000a2c + 80012ec: 4602 mov r2, r0 + 80012ee: 693b ldr r3, [r7, #16] + 80012f0: 1ad3 subs r3, r2, r3 + 80012f2: 2b02 cmp r3, #2 + 80012f4: d901 bls.n 80012fa + { + return HAL_TIMEOUT; + 80012f6: 2303 movs r3, #3 + 80012f8: e177 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80012fa: 4b5d ldr r3, [pc, #372] @ (8001470 ) + 80012fc: 681b ldr r3, [r3, #0] + 80012fe: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001302: 2b00 cmp r3, #0 + 8001304: d1f0 bne.n 80012e8 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8001306: 687b ldr r3, [r7, #4] + 8001308: 681b ldr r3, [r3, #0] + 800130a: f003 0308 and.w r3, r3, #8 + 800130e: 2b00 cmp r3, #0 + 8001310: d030 beq.n 8001374 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8001312: 687b ldr r3, [r7, #4] + 8001314: 695b ldr r3, [r3, #20] + 8001316: 2b00 cmp r3, #0 + 8001318: d016 beq.n 8001348 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800131a: 4b5a ldr r3, [pc, #360] @ (8001484 ) + 800131c: 2201 movs r2, #1 + 800131e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001320: f7ff fb84 bl 8000a2c + 8001324: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8001326: e008 b.n 800133a + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001328: f7ff fb80 bl 8000a2c + 800132c: 4602 mov r2, r0 + 800132e: 693b ldr r3, [r7, #16] + 8001330: 1ad3 subs r3, r2, r3 + 8001332: 2b02 cmp r3, #2 + 8001334: d901 bls.n 800133a + { + return HAL_TIMEOUT; + 8001336: 2303 movs r3, #3 + 8001338: e157 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800133a: 4b4d ldr r3, [pc, #308] @ (8001470 ) + 800133c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800133e: f003 0302 and.w r3, r3, #2 + 8001342: 2b00 cmp r3, #0 + 8001344: d0f0 beq.n 8001328 + 8001346: e015 b.n 8001374 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001348: 4b4e ldr r3, [pc, #312] @ (8001484 ) + 800134a: 2200 movs r2, #0 + 800134c: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800134e: f7ff fb6d bl 8000a2c + 8001352: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001354: e008 b.n 8001368 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001356: f7ff fb69 bl 8000a2c + 800135a: 4602 mov r2, r0 + 800135c: 693b ldr r3, [r7, #16] + 800135e: 1ad3 subs r3, r2, r3 + 8001360: 2b02 cmp r3, #2 + 8001362: d901 bls.n 8001368 + { + return HAL_TIMEOUT; + 8001364: 2303 movs r3, #3 + 8001366: e140 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001368: 4b41 ldr r3, [pc, #260] @ (8001470 ) + 800136a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800136c: f003 0302 and.w r3, r3, #2 + 8001370: 2b00 cmp r3, #0 + 8001372: d1f0 bne.n 8001356 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8001374: 687b ldr r3, [r7, #4] + 8001376: 681b ldr r3, [r3, #0] + 8001378: f003 0304 and.w r3, r3, #4 + 800137c: 2b00 cmp r3, #0 + 800137e: f000 80b5 beq.w 80014ec + { + FlagStatus pwrclkchanged = RESET; + 8001382: 2300 movs r3, #0 + 8001384: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8001386: 4b3a ldr r3, [pc, #232] @ (8001470 ) + 8001388: 6a5b ldr r3, [r3, #36] @ 0x24 + 800138a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800138e: 2b00 cmp r3, #0 + 8001390: d10d bne.n 80013ae + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001392: 4b37 ldr r3, [pc, #220] @ (8001470 ) + 8001394: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001396: 4a36 ldr r2, [pc, #216] @ (8001470 ) + 8001398: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800139c: 6253 str r3, [r2, #36] @ 0x24 + 800139e: 4b34 ldr r3, [pc, #208] @ (8001470 ) + 80013a0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80013a2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80013a6: 60bb str r3, [r7, #8] + 80013a8: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 80013aa: 2301 movs r3, #1 + 80013ac: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80013ae: 4b36 ldr r3, [pc, #216] @ (8001488 ) + 80013b0: 681b ldr r3, [r3, #0] + 80013b2: f403 7380 and.w r3, r3, #256 @ 0x100 + 80013b6: 2b00 cmp r3, #0 + 80013b8: d118 bne.n 80013ec + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80013ba: 4b33 ldr r3, [pc, #204] @ (8001488 ) + 80013bc: 681b ldr r3, [r3, #0] + 80013be: 4a32 ldr r2, [pc, #200] @ (8001488 ) + 80013c0: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80013c4: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80013c6: f7ff fb31 bl 8000a2c + 80013ca: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80013cc: e008 b.n 80013e0 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80013ce: f7ff fb2d bl 8000a2c + 80013d2: 4602 mov r2, r0 + 80013d4: 693b ldr r3, [r7, #16] + 80013d6: 1ad3 subs r3, r2, r3 + 80013d8: 2b64 cmp r3, #100 @ 0x64 + 80013da: d901 bls.n 80013e0 + { + return HAL_TIMEOUT; + 80013dc: 2303 movs r3, #3 + 80013de: e104 b.n 80015ea + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80013e0: 4b29 ldr r3, [pc, #164] @ (8001488 ) + 80013e2: 681b ldr r3, [r3, #0] + 80013e4: f403 7380 and.w r3, r3, #256 @ 0x100 + 80013e8: 2b00 cmp r3, #0 + 80013ea: d0f0 beq.n 80013ce + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80013ec: 687b ldr r3, [r7, #4] + 80013ee: 689b ldr r3, [r3, #8] + 80013f0: 2b01 cmp r3, #1 + 80013f2: d106 bne.n 8001402 + 80013f4: 4b1e ldr r3, [pc, #120] @ (8001470 ) + 80013f6: 6b5b ldr r3, [r3, #52] @ 0x34 + 80013f8: 4a1d ldr r2, [pc, #116] @ (8001470 ) + 80013fa: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80013fe: 6353 str r3, [r2, #52] @ 0x34 + 8001400: e02d b.n 800145e + 8001402: 687b ldr r3, [r7, #4] + 8001404: 689b ldr r3, [r3, #8] + 8001406: 2b00 cmp r3, #0 + 8001408: d10c bne.n 8001424 + 800140a: 4b19 ldr r3, [pc, #100] @ (8001470 ) + 800140c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800140e: 4a18 ldr r2, [pc, #96] @ (8001470 ) + 8001410: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001414: 6353 str r3, [r2, #52] @ 0x34 + 8001416: 4b16 ldr r3, [pc, #88] @ (8001470 ) + 8001418: 6b5b ldr r3, [r3, #52] @ 0x34 + 800141a: 4a15 ldr r2, [pc, #84] @ (8001470 ) + 800141c: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001420: 6353 str r3, [r2, #52] @ 0x34 + 8001422: e01c b.n 800145e + 8001424: 687b ldr r3, [r7, #4] + 8001426: 689b ldr r3, [r3, #8] + 8001428: 2b05 cmp r3, #5 + 800142a: d10c bne.n 8001446 + 800142c: 4b10 ldr r3, [pc, #64] @ (8001470 ) + 800142e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001430: 4a0f ldr r2, [pc, #60] @ (8001470 ) + 8001432: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8001436: 6353 str r3, [r2, #52] @ 0x34 + 8001438: 4b0d ldr r3, [pc, #52] @ (8001470 ) + 800143a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800143c: 4a0c ldr r2, [pc, #48] @ (8001470 ) + 800143e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001442: 6353 str r3, [r2, #52] @ 0x34 + 8001444: e00b b.n 800145e + 8001446: 4b0a ldr r3, [pc, #40] @ (8001470 ) + 8001448: 6b5b ldr r3, [r3, #52] @ 0x34 + 800144a: 4a09 ldr r2, [pc, #36] @ (8001470 ) + 800144c: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001450: 6353 str r3, [r2, #52] @ 0x34 + 8001452: 4b07 ldr r3, [pc, #28] @ (8001470 ) + 8001454: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001456: 4a06 ldr r2, [pc, #24] @ (8001470 ) + 8001458: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 800145c: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 800145e: 687b ldr r3, [r7, #4] + 8001460: 689b ldr r3, [r3, #8] + 8001462: 2b00 cmp r3, #0 + 8001464: d024 beq.n 80014b0 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001466: f7ff fae1 bl 8000a2c + 800146a: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800146c: e019 b.n 80014a2 + 800146e: bf00 nop + 8001470: 40023800 .word 0x40023800 + 8001474: 08002070 .word 0x08002070 + 8001478: 20000000 .word 0x20000000 + 800147c: 20000004 .word 0x20000004 + 8001480: 42470020 .word 0x42470020 + 8001484: 42470680 .word 0x42470680 + 8001488: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800148c: f7ff face bl 8000a2c + 8001490: 4602 mov r2, r0 + 8001492: 693b ldr r3, [r7, #16] + 8001494: 1ad3 subs r3, r2, r3 + 8001496: f241 3288 movw r2, #5000 @ 0x1388 + 800149a: 4293 cmp r3, r2 + 800149c: d901 bls.n 80014a2 + { + return HAL_TIMEOUT; + 800149e: 2303 movs r3, #3 + 80014a0: e0a3 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 80014a2: 4b54 ldr r3, [pc, #336] @ (80015f4 ) + 80014a4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014a6: f403 7300 and.w r3, r3, #512 @ 0x200 + 80014aa: 2b00 cmp r3, #0 + 80014ac: d0ee beq.n 800148c + 80014ae: e014 b.n 80014da + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80014b0: f7ff fabc bl 8000a2c + 80014b4: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80014b6: e00a b.n 80014ce + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80014b8: f7ff fab8 bl 8000a2c + 80014bc: 4602 mov r2, r0 + 80014be: 693b ldr r3, [r7, #16] + 80014c0: 1ad3 subs r3, r2, r3 + 80014c2: f241 3288 movw r2, #5000 @ 0x1388 + 80014c6: 4293 cmp r3, r2 + 80014c8: d901 bls.n 80014ce + { + return HAL_TIMEOUT; + 80014ca: 2303 movs r3, #3 + 80014cc: e08d b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80014ce: 4b49 ldr r3, [pc, #292] @ (80015f4 ) + 80014d0: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014d2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80014d6: 2b00 cmp r3, #0 + 80014d8: d1ee bne.n 80014b8 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 80014da: 7ffb ldrb r3, [r7, #31] + 80014dc: 2b01 cmp r3, #1 + 80014de: d105 bne.n 80014ec + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80014e0: 4b44 ldr r3, [pc, #272] @ (80015f4 ) + 80014e2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80014e4: 4a43 ldr r2, [pc, #268] @ (80015f4 ) + 80014e6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80014ea: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80014ec: 687b ldr r3, [r7, #4] + 80014ee: 6a5b ldr r3, [r3, #36] @ 0x24 + 80014f0: 2b00 cmp r3, #0 + 80014f2: d079 beq.n 80015e8 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80014f4: 69bb ldr r3, [r7, #24] + 80014f6: 2b0c cmp r3, #12 + 80014f8: d056 beq.n 80015a8 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80014fa: 687b ldr r3, [r7, #4] + 80014fc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80014fe: 2b02 cmp r3, #2 + 8001500: d13b bne.n 800157a + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001502: 4b3d ldr r3, [pc, #244] @ (80015f8 ) + 8001504: 2200 movs r2, #0 + 8001506: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001508: f7ff fa90 bl 8000a2c + 800150c: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800150e: e008 b.n 8001522 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001510: f7ff fa8c bl 8000a2c + 8001514: 4602 mov r2, r0 + 8001516: 693b ldr r3, [r7, #16] + 8001518: 1ad3 subs r3, r2, r3 + 800151a: 2b02 cmp r3, #2 + 800151c: d901 bls.n 8001522 + { + return HAL_TIMEOUT; + 800151e: 2303 movs r3, #3 + 8001520: e063 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001522: 4b34 ldr r3, [pc, #208] @ (80015f4 ) + 8001524: 681b ldr r3, [r3, #0] + 8001526: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800152a: 2b00 cmp r3, #0 + 800152c: d1f0 bne.n 8001510 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 800152e: 4b31 ldr r3, [pc, #196] @ (80015f4 ) + 8001530: 689b ldr r3, [r3, #8] + 8001532: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 8001536: 687b ldr r3, [r7, #4] + 8001538: 6a99 ldr r1, [r3, #40] @ 0x28 + 800153a: 687b ldr r3, [r7, #4] + 800153c: 6adb ldr r3, [r3, #44] @ 0x2c + 800153e: 4319 orrs r1, r3 + 8001540: 687b ldr r3, [r7, #4] + 8001542: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001544: 430b orrs r3, r1 + 8001546: 492b ldr r1, [pc, #172] @ (80015f4 ) + 8001548: 4313 orrs r3, r2 + 800154a: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 800154c: 4b2a ldr r3, [pc, #168] @ (80015f8 ) + 800154e: 2201 movs r2, #1 + 8001550: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001552: f7ff fa6b bl 8000a2c + 8001556: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001558: e008 b.n 800156c + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800155a: f7ff fa67 bl 8000a2c + 800155e: 4602 mov r2, r0 + 8001560: 693b ldr r3, [r7, #16] + 8001562: 1ad3 subs r3, r2, r3 + 8001564: 2b02 cmp r3, #2 + 8001566: d901 bls.n 800156c + { + return HAL_TIMEOUT; + 8001568: 2303 movs r3, #3 + 800156a: e03e b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 800156c: 4b21 ldr r3, [pc, #132] @ (80015f4 ) + 800156e: 681b ldr r3, [r3, #0] + 8001570: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001574: 2b00 cmp r3, #0 + 8001576: d0f0 beq.n 800155a + 8001578: e036 b.n 80015e8 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 800157a: 4b1f ldr r3, [pc, #124] @ (80015f8 ) + 800157c: 2200 movs r2, #0 + 800157e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001580: f7ff fa54 bl 8000a2c + 8001584: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001586: e008 b.n 800159a + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001588: f7ff fa50 bl 8000a2c + 800158c: 4602 mov r2, r0 + 800158e: 693b ldr r3, [r7, #16] + 8001590: 1ad3 subs r3, r2, r3 + 8001592: 2b02 cmp r3, #2 + 8001594: d901 bls.n 800159a + { + return HAL_TIMEOUT; + 8001596: 2303 movs r3, #3 + 8001598: e027 b.n 80015ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800159a: 4b16 ldr r3, [pc, #88] @ (80015f4 ) + 800159c: 681b ldr r3, [r3, #0] + 800159e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80015a2: 2b00 cmp r3, #0 + 80015a4: d1f0 bne.n 8001588 + 80015a6: e01f b.n 80015e8 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 80015a8: 687b ldr r3, [r7, #4] + 80015aa: 6a5b ldr r3, [r3, #36] @ 0x24 + 80015ac: 2b01 cmp r3, #1 + 80015ae: d101 bne.n 80015b4 + { + return HAL_ERROR; + 80015b0: 2301 movs r3, #1 + 80015b2: e01a b.n 80015ea + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 80015b4: 4b0f ldr r3, [pc, #60] @ (80015f4 ) + 80015b6: 689b ldr r3, [r3, #8] + 80015b8: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80015ba: 697b ldr r3, [r7, #20] + 80015bc: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 80015c0: 687b ldr r3, [r7, #4] + 80015c2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80015c4: 429a cmp r2, r3 + 80015c6: d10d bne.n 80015e4 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80015c8: 697b ldr r3, [r7, #20] + 80015ca: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 80015ce: 687b ldr r3, [r7, #4] + 80015d0: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80015d2: 429a cmp r2, r3 + 80015d4: d106 bne.n 80015e4 + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 80015d6: 697b ldr r3, [r7, #20] + 80015d8: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 80015dc: 687b ldr r3, [r7, #4] + 80015de: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80015e0: 429a cmp r2, r3 + 80015e2: d001 beq.n 80015e8 + { + return HAL_ERROR; + 80015e4: 2301 movs r3, #1 + 80015e6: e000 b.n 80015ea + } + } + } + } + + return HAL_OK; + 80015e8: 2300 movs r3, #0 +} + 80015ea: 4618 mov r0, r3 + 80015ec: 3720 adds r7, #32 + 80015ee: 46bd mov sp, r7 + 80015f0: bd80 pop {r7, pc} + 80015f2: bf00 nop + 80015f4: 40023800 .word 0x40023800 + 80015f8: 42470060 .word 0x42470060 + +080015fc : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80015fc: b580 push {r7, lr} + 80015fe: b084 sub sp, #16 + 8001600: af00 add r7, sp, #0 + 8001602: 6078 str r0, [r7, #4] + 8001604: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 8001606: 687b ldr r3, [r7, #4] + 8001608: 2b00 cmp r3, #0 + 800160a: d101 bne.n 8001610 + { + return HAL_ERROR; + 800160c: 2301 movs r3, #1 + 800160e: e11a b.n 8001846 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8001610: 4b8f ldr r3, [pc, #572] @ (8001850 ) + 8001612: 681b ldr r3, [r3, #0] + 8001614: f003 0301 and.w r3, r3, #1 + 8001618: 683a ldr r2, [r7, #0] + 800161a: 429a cmp r2, r3 + 800161c: d919 bls.n 8001652 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800161e: 683b ldr r3, [r7, #0] + 8001620: 2b01 cmp r3, #1 + 8001622: d105 bne.n 8001630 + 8001624: 4b8a ldr r3, [pc, #552] @ (8001850 ) + 8001626: 681b ldr r3, [r3, #0] + 8001628: 4a89 ldr r2, [pc, #548] @ (8001850 ) + 800162a: f043 0304 orr.w r3, r3, #4 + 800162e: 6013 str r3, [r2, #0] + 8001630: 4b87 ldr r3, [pc, #540] @ (8001850 ) + 8001632: 681b ldr r3, [r3, #0] + 8001634: f023 0201 bic.w r2, r3, #1 + 8001638: 4985 ldr r1, [pc, #532] @ (8001850 ) + 800163a: 683b ldr r3, [r7, #0] + 800163c: 4313 orrs r3, r2 + 800163e: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001640: 4b83 ldr r3, [pc, #524] @ (8001850 ) + 8001642: 681b ldr r3, [r3, #0] + 8001644: f003 0301 and.w r3, r3, #1 + 8001648: 683a ldr r2, [r7, #0] + 800164a: 429a cmp r2, r3 + 800164c: d001 beq.n 8001652 + { + return HAL_ERROR; + 800164e: 2301 movs r3, #1 + 8001650: e0f9 b.n 8001846 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8001652: 687b ldr r3, [r7, #4] + 8001654: 681b ldr r3, [r3, #0] + 8001656: f003 0302 and.w r3, r3, #2 + 800165a: 2b00 cmp r3, #0 + 800165c: d008 beq.n 8001670 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 800165e: 4b7d ldr r3, [pc, #500] @ (8001854 ) + 8001660: 689b ldr r3, [r3, #8] + 8001662: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8001666: 687b ldr r3, [r7, #4] + 8001668: 689b ldr r3, [r3, #8] + 800166a: 497a ldr r1, [pc, #488] @ (8001854 ) + 800166c: 4313 orrs r3, r2 + 800166e: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8001670: 687b ldr r3, [r7, #4] + 8001672: 681b ldr r3, [r3, #0] + 8001674: f003 0301 and.w r3, r3, #1 + 8001678: 2b00 cmp r3, #0 + 800167a: f000 808e beq.w 800179a + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800167e: 687b ldr r3, [r7, #4] + 8001680: 685b ldr r3, [r3, #4] + 8001682: 2b02 cmp r3, #2 + 8001684: d107 bne.n 8001696 + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001686: 4b73 ldr r3, [pc, #460] @ (8001854 ) + 8001688: 681b ldr r3, [r3, #0] + 800168a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800168e: 2b00 cmp r3, #0 + 8001690: d121 bne.n 80016d6 + { + return HAL_ERROR; + 8001692: 2301 movs r3, #1 + 8001694: e0d7 b.n 8001846 + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001696: 687b ldr r3, [r7, #4] + 8001698: 685b ldr r3, [r3, #4] + 800169a: 2b03 cmp r3, #3 + 800169c: d107 bne.n 80016ae + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 800169e: 4b6d ldr r3, [pc, #436] @ (8001854 ) + 80016a0: 681b ldr r3, [r3, #0] + 80016a2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80016a6: 2b00 cmp r3, #0 + 80016a8: d115 bne.n 80016d6 + { + return HAL_ERROR; + 80016aa: 2301 movs r3, #1 + 80016ac: e0cb b.n 8001846 + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 80016ae: 687b ldr r3, [r7, #4] + 80016b0: 685b ldr r3, [r3, #4] + 80016b2: 2b01 cmp r3, #1 + 80016b4: d107 bne.n 80016c6 + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80016b6: 4b67 ldr r3, [pc, #412] @ (8001854 ) + 80016b8: 681b ldr r3, [r3, #0] + 80016ba: f003 0302 and.w r3, r3, #2 + 80016be: 2b00 cmp r3, #0 + 80016c0: d109 bne.n 80016d6 + { + return HAL_ERROR; + 80016c2: 2301 movs r3, #1 + 80016c4: e0bf b.n 8001846 + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80016c6: 4b63 ldr r3, [pc, #396] @ (8001854 ) + 80016c8: 681b ldr r3, [r3, #0] + 80016ca: f403 7300 and.w r3, r3, #512 @ 0x200 + 80016ce: 2b00 cmp r3, #0 + 80016d0: d101 bne.n 80016d6 + { + return HAL_ERROR; + 80016d2: 2301 movs r3, #1 + 80016d4: e0b7 b.n 8001846 + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 80016d6: 4b5f ldr r3, [pc, #380] @ (8001854 ) + 80016d8: 689b ldr r3, [r3, #8] + 80016da: f023 0203 bic.w r2, r3, #3 + 80016de: 687b ldr r3, [r7, #4] + 80016e0: 685b ldr r3, [r3, #4] + 80016e2: 495c ldr r1, [pc, #368] @ (8001854 ) + 80016e4: 4313 orrs r3, r2 + 80016e6: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80016e8: f7ff f9a0 bl 8000a2c + 80016ec: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80016ee: 687b ldr r3, [r7, #4] + 80016f0: 685b ldr r3, [r3, #4] + 80016f2: 2b02 cmp r3, #2 + 80016f4: d112 bne.n 800171c + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 80016f6: e00a b.n 800170e + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80016f8: f7ff f998 bl 8000a2c + 80016fc: 4602 mov r2, r0 + 80016fe: 68fb ldr r3, [r7, #12] + 8001700: 1ad3 subs r3, r2, r3 + 8001702: f241 3288 movw r2, #5000 @ 0x1388 + 8001706: 4293 cmp r3, r2 + 8001708: d901 bls.n 800170e + { + return HAL_TIMEOUT; + 800170a: 2303 movs r3, #3 + 800170c: e09b b.n 8001846 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 800170e: 4b51 ldr r3, [pc, #324] @ (8001854 ) + 8001710: 689b ldr r3, [r3, #8] + 8001712: f003 030c and.w r3, r3, #12 + 8001716: 2b08 cmp r3, #8 + 8001718: d1ee bne.n 80016f8 + 800171a: e03e b.n 800179a + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800171c: 687b ldr r3, [r7, #4] + 800171e: 685b ldr r3, [r3, #4] + 8001720: 2b03 cmp r3, #3 + 8001722: d112 bne.n 800174a + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001724: e00a b.n 800173c + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001726: f7ff f981 bl 8000a2c + 800172a: 4602 mov r2, r0 + 800172c: 68fb ldr r3, [r7, #12] + 800172e: 1ad3 subs r3, r2, r3 + 8001730: f241 3288 movw r2, #5000 @ 0x1388 + 8001734: 4293 cmp r3, r2 + 8001736: d901 bls.n 800173c + { + return HAL_TIMEOUT; + 8001738: 2303 movs r3, #3 + 800173a: e084 b.n 8001846 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 800173c: 4b45 ldr r3, [pc, #276] @ (8001854 ) + 800173e: 689b ldr r3, [r3, #8] + 8001740: f003 030c and.w r3, r3, #12 + 8001744: 2b0c cmp r3, #12 + 8001746: d1ee bne.n 8001726 + 8001748: e027 b.n 800179a + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 800174a: 687b ldr r3, [r7, #4] + 800174c: 685b ldr r3, [r3, #4] + 800174e: 2b01 cmp r3, #1 + 8001750: d11d bne.n 800178e + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001752: e00a b.n 800176a + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001754: f7ff f96a bl 8000a2c + 8001758: 4602 mov r2, r0 + 800175a: 68fb ldr r3, [r7, #12] + 800175c: 1ad3 subs r3, r2, r3 + 800175e: f241 3288 movw r2, #5000 @ 0x1388 + 8001762: 4293 cmp r3, r2 + 8001764: d901 bls.n 800176a + { + return HAL_TIMEOUT; + 8001766: 2303 movs r3, #3 + 8001768: e06d b.n 8001846 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 800176a: 4b3a ldr r3, [pc, #232] @ (8001854 ) + 800176c: 689b ldr r3, [r3, #8] + 800176e: f003 030c and.w r3, r3, #12 + 8001772: 2b04 cmp r3, #4 + 8001774: d1ee bne.n 8001754 + 8001776: e010 b.n 800179a + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001778: f7ff f958 bl 8000a2c + 800177c: 4602 mov r2, r0 + 800177e: 68fb ldr r3, [r7, #12] + 8001780: 1ad3 subs r3, r2, r3 + 8001782: f241 3288 movw r2, #5000 @ 0x1388 + 8001786: 4293 cmp r3, r2 + 8001788: d901 bls.n 800178e + { + return HAL_TIMEOUT; + 800178a: 2303 movs r3, #3 + 800178c: e05b b.n 8001846 + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 800178e: 4b31 ldr r3, [pc, #196] @ (8001854 ) + 8001790: 689b ldr r3, [r3, #8] + 8001792: f003 030c and.w r3, r3, #12 + 8001796: 2b00 cmp r3, #0 + 8001798: d1ee bne.n 8001778 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 800179a: 4b2d ldr r3, [pc, #180] @ (8001850 ) + 800179c: 681b ldr r3, [r3, #0] + 800179e: f003 0301 and.w r3, r3, #1 + 80017a2: 683a ldr r2, [r7, #0] + 80017a4: 429a cmp r2, r3 + 80017a6: d219 bcs.n 80017dc + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80017a8: 683b ldr r3, [r7, #0] + 80017aa: 2b01 cmp r3, #1 + 80017ac: d105 bne.n 80017ba + 80017ae: 4b28 ldr r3, [pc, #160] @ (8001850 ) + 80017b0: 681b ldr r3, [r3, #0] + 80017b2: 4a27 ldr r2, [pc, #156] @ (8001850 ) + 80017b4: f043 0304 orr.w r3, r3, #4 + 80017b8: 6013 str r3, [r2, #0] + 80017ba: 4b25 ldr r3, [pc, #148] @ (8001850 ) + 80017bc: 681b ldr r3, [r3, #0] + 80017be: f023 0201 bic.w r2, r3, #1 + 80017c2: 4923 ldr r1, [pc, #140] @ (8001850 ) + 80017c4: 683b ldr r3, [r7, #0] + 80017c6: 4313 orrs r3, r2 + 80017c8: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 80017ca: 4b21 ldr r3, [pc, #132] @ (8001850 ) + 80017cc: 681b ldr r3, [r3, #0] + 80017ce: f003 0301 and.w r3, r3, #1 + 80017d2: 683a ldr r2, [r7, #0] + 80017d4: 429a cmp r2, r3 + 80017d6: d001 beq.n 80017dc + { + return HAL_ERROR; + 80017d8: 2301 movs r3, #1 + 80017da: e034 b.n 8001846 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 80017dc: 687b ldr r3, [r7, #4] + 80017de: 681b ldr r3, [r3, #0] + 80017e0: f003 0304 and.w r3, r3, #4 + 80017e4: 2b00 cmp r3, #0 + 80017e6: d008 beq.n 80017fa + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 80017e8: 4b1a ldr r3, [pc, #104] @ (8001854 ) + 80017ea: 689b ldr r3, [r3, #8] + 80017ec: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 80017f0: 687b ldr r3, [r7, #4] + 80017f2: 68db ldr r3, [r3, #12] + 80017f4: 4917 ldr r1, [pc, #92] @ (8001854 ) + 80017f6: 4313 orrs r3, r2 + 80017f8: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80017fa: 687b ldr r3, [r7, #4] + 80017fc: 681b ldr r3, [r3, #0] + 80017fe: f003 0308 and.w r3, r3, #8 + 8001802: 2b00 cmp r3, #0 + 8001804: d009 beq.n 800181a + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8001806: 4b13 ldr r3, [pc, #76] @ (8001854 ) + 8001808: 689b ldr r3, [r3, #8] + 800180a: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 800180e: 687b ldr r3, [r7, #4] + 8001810: 691b ldr r3, [r3, #16] + 8001812: 00db lsls r3, r3, #3 + 8001814: 490f ldr r1, [pc, #60] @ (8001854 ) + 8001816: 4313 orrs r3, r2 + 8001818: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 800181a: f000 f823 bl 8001864 + 800181e: 4602 mov r2, r0 + 8001820: 4b0c ldr r3, [pc, #48] @ (8001854 ) + 8001822: 689b ldr r3, [r3, #8] + 8001824: 091b lsrs r3, r3, #4 + 8001826: f003 030f and.w r3, r3, #15 + 800182a: 490b ldr r1, [pc, #44] @ (8001858 ) + 800182c: 5ccb ldrb r3, [r1, r3] + 800182e: fa22 f303 lsr.w r3, r2, r3 + 8001832: 4a0a ldr r2, [pc, #40] @ (800185c ) + 8001834: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001836: 4b0a ldr r3, [pc, #40] @ (8001860 ) + 8001838: 681b ldr r3, [r3, #0] + 800183a: 4618 mov r0, r3 + 800183c: f7ff f8aa bl 8000994 + 8001840: 4603 mov r3, r0 + 8001842: 72fb strb r3, [r7, #11] + + return status; + 8001844: 7afb ldrb r3, [r7, #11] +} + 8001846: 4618 mov r0, r3 + 8001848: 3710 adds r7, #16 + 800184a: 46bd mov sp, r7 + 800184c: bd80 pop {r7, pc} + 800184e: bf00 nop + 8001850: 40023c00 .word 0x40023c00 + 8001854: 40023800 .word 0x40023800 + 8001858: 08002070 .word 0x08002070 + 800185c: 20000000 .word 0x20000000 + 8001860: 20000004 .word 0x20000004 + +08001864 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8001864: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001868: b08e sub sp, #56 @ 0x38 + 800186a: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 800186c: 4b58 ldr r3, [pc, #352] @ (80019d0 ) + 800186e: 689b ldr r3, [r3, #8] + 8001870: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8001872: 6afb ldr r3, [r7, #44] @ 0x2c + 8001874: f003 030c and.w r3, r3, #12 + 8001878: 2b0c cmp r3, #12 + 800187a: d00d beq.n 8001898 + 800187c: 2b0c cmp r3, #12 + 800187e: f200 8092 bhi.w 80019a6 + 8001882: 2b04 cmp r3, #4 + 8001884: d002 beq.n 800188c + 8001886: 2b08 cmp r3, #8 + 8001888: d003 beq.n 8001892 + 800188a: e08c b.n 80019a6 + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 800188c: 4b51 ldr r3, [pc, #324] @ (80019d4 ) + 800188e: 633b str r3, [r7, #48] @ 0x30 + break; + 8001890: e097 b.n 80019c2 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001892: 4b51 ldr r3, [pc, #324] @ (80019d8 ) + 8001894: 633b str r3, [r7, #48] @ 0x30 + break; + 8001896: e094 b.n 80019c2 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8001898: 6afb ldr r3, [r7, #44] @ 0x2c + 800189a: 0c9b lsrs r3, r3, #18 + 800189c: f003 020f and.w r2, r3, #15 + 80018a0: 4b4e ldr r3, [pc, #312] @ (80019dc ) + 80018a2: 5c9b ldrb r3, [r3, r2] + 80018a4: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 80018a6: 6afb ldr r3, [r7, #44] @ 0x2c + 80018a8: 0d9b lsrs r3, r3, #22 + 80018aa: f003 0303 and.w r3, r3, #3 + 80018ae: 3301 adds r3, #1 + 80018b0: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 80018b2: 4b47 ldr r3, [pc, #284] @ (80019d0 ) + 80018b4: 689b ldr r3, [r3, #8] + 80018b6: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80018ba: 2b00 cmp r3, #0 + 80018bc: d021 beq.n 8001902 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 80018be: 6abb ldr r3, [r7, #40] @ 0x28 + 80018c0: 2200 movs r2, #0 + 80018c2: 61bb str r3, [r7, #24] + 80018c4: 61fa str r2, [r7, #28] + 80018c6: 4b44 ldr r3, [pc, #272] @ (80019d8 ) + 80018c8: e9d7 8906 ldrd r8, r9, [r7, #24] + 80018cc: 464a mov r2, r9 + 80018ce: fb03 f202 mul.w r2, r3, r2 + 80018d2: 2300 movs r3, #0 + 80018d4: 4644 mov r4, r8 + 80018d6: fb04 f303 mul.w r3, r4, r3 + 80018da: 4413 add r3, r2 + 80018dc: 4a3e ldr r2, [pc, #248] @ (80019d8 ) + 80018de: 4644 mov r4, r8 + 80018e0: fba4 0102 umull r0, r1, r4, r2 + 80018e4: 440b add r3, r1 + 80018e6: 4619 mov r1, r3 + 80018e8: 6a7b ldr r3, [r7, #36] @ 0x24 + 80018ea: 2200 movs r2, #0 + 80018ec: 613b str r3, [r7, #16] + 80018ee: 617a str r2, [r7, #20] + 80018f0: e9d7 2304 ldrd r2, r3, [r7, #16] + 80018f4: f7fe fc42 bl 800017c <__aeabi_uldivmod> + 80018f8: 4602 mov r2, r0 + 80018fa: 460b mov r3, r1 + 80018fc: 4613 mov r3, r2 + 80018fe: 637b str r3, [r7, #52] @ 0x34 + 8001900: e04e b.n 80019a0 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001902: 6abb ldr r3, [r7, #40] @ 0x28 + 8001904: 2200 movs r2, #0 + 8001906: 469a mov sl, r3 + 8001908: 4693 mov fp, r2 + 800190a: 4652 mov r2, sl + 800190c: 465b mov r3, fp + 800190e: f04f 0000 mov.w r0, #0 + 8001912: f04f 0100 mov.w r1, #0 + 8001916: 0159 lsls r1, r3, #5 + 8001918: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 800191c: 0150 lsls r0, r2, #5 + 800191e: 4602 mov r2, r0 + 8001920: 460b mov r3, r1 + 8001922: ebb2 080a subs.w r8, r2, sl + 8001926: eb63 090b sbc.w r9, r3, fp + 800192a: f04f 0200 mov.w r2, #0 + 800192e: f04f 0300 mov.w r3, #0 + 8001932: ea4f 1389 mov.w r3, r9, lsl #6 + 8001936: ea43 6398 orr.w r3, r3, r8, lsr #26 + 800193a: ea4f 1288 mov.w r2, r8, lsl #6 + 800193e: ebb2 0408 subs.w r4, r2, r8 + 8001942: eb63 0509 sbc.w r5, r3, r9 + 8001946: f04f 0200 mov.w r2, #0 + 800194a: f04f 0300 mov.w r3, #0 + 800194e: 00eb lsls r3, r5, #3 + 8001950: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8001954: 00e2 lsls r2, r4, #3 + 8001956: 4614 mov r4, r2 + 8001958: 461d mov r5, r3 + 800195a: eb14 030a adds.w r3, r4, sl + 800195e: 603b str r3, [r7, #0] + 8001960: eb45 030b adc.w r3, r5, fp + 8001964: 607b str r3, [r7, #4] + 8001966: f04f 0200 mov.w r2, #0 + 800196a: f04f 0300 mov.w r3, #0 + 800196e: e9d7 4500 ldrd r4, r5, [r7] + 8001972: 4629 mov r1, r5 + 8001974: 028b lsls r3, r1, #10 + 8001976: 4620 mov r0, r4 + 8001978: 4629 mov r1, r5 + 800197a: 4604 mov r4, r0 + 800197c: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8001980: 4601 mov r1, r0 + 8001982: 028a lsls r2, r1, #10 + 8001984: 4610 mov r0, r2 + 8001986: 4619 mov r1, r3 + 8001988: 6a7b ldr r3, [r7, #36] @ 0x24 + 800198a: 2200 movs r2, #0 + 800198c: 60bb str r3, [r7, #8] + 800198e: 60fa str r2, [r7, #12] + 8001990: e9d7 2302 ldrd r2, r3, [r7, #8] + 8001994: f7fe fbf2 bl 800017c <__aeabi_uldivmod> + 8001998: 4602 mov r2, r0 + 800199a: 460b mov r3, r1 + 800199c: 4613 mov r3, r2 + 800199e: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 80019a0: 6b7b ldr r3, [r7, #52] @ 0x34 + 80019a2: 633b str r3, [r7, #48] @ 0x30 + break; + 80019a4: e00d b.n 80019c2 + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 80019a6: 4b0a ldr r3, [pc, #40] @ (80019d0 ) + 80019a8: 685b ldr r3, [r3, #4] + 80019aa: 0b5b lsrs r3, r3, #13 + 80019ac: f003 0307 and.w r3, r3, #7 + 80019b0: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 80019b2: 6a3b ldr r3, [r7, #32] + 80019b4: 3301 adds r3, #1 + 80019b6: f44f 4200 mov.w r2, #32768 @ 0x8000 + 80019ba: fa02 f303 lsl.w r3, r2, r3 + 80019be: 633b str r3, [r7, #48] @ 0x30 + break; + 80019c0: bf00 nop + } + } + return sysclockfreq; + 80019c2: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 80019c4: 4618 mov r0, r3 + 80019c6: 3738 adds r7, #56 @ 0x38 + 80019c8: 46bd mov sp, r7 + 80019ca: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80019ce: bf00 nop + 80019d0: 40023800 .word 0x40023800 + 80019d4: 00f42400 .word 0x00f42400 + 80019d8: 016e3600 .word 0x016e3600 + 80019dc: 08002064 .word 0x08002064 + +080019e0 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 80019e0: b480 push {r7} + 80019e2: b087 sub sp, #28 + 80019e4: af00 add r7, sp, #0 + 80019e6: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 80019e8: 2300 movs r3, #0 + 80019ea: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 80019ec: 4b29 ldr r3, [pc, #164] @ (8001a94 ) + 80019ee: 689b ldr r3, [r3, #8] + 80019f0: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 80019f4: 2b00 cmp r3, #0 + 80019f6: d12c bne.n 8001a52 + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 80019f8: 4b26 ldr r3, [pc, #152] @ (8001a94 ) + 80019fa: 6a5b ldr r3, [r3, #36] @ 0x24 + 80019fc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001a00: 2b00 cmp r3, #0 + 8001a02: d005 beq.n 8001a10 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001a04: 4b24 ldr r3, [pc, #144] @ (8001a98 ) + 8001a06: 681b ldr r3, [r3, #0] + 8001a08: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001a0c: 617b str r3, [r7, #20] + 8001a0e: e016 b.n 8001a3e + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001a10: 4b20 ldr r3, [pc, #128] @ (8001a94 ) + 8001a12: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a14: 4a1f ldr r2, [pc, #124] @ (8001a94 ) + 8001a16: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001a1a: 6253 str r3, [r2, #36] @ 0x24 + 8001a1c: 4b1d ldr r3, [pc, #116] @ (8001a94 ) + 8001a1e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a20: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001a24: 60fb str r3, [r7, #12] + 8001a26: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001a28: 4b1b ldr r3, [pc, #108] @ (8001a98 ) + 8001a2a: 681b ldr r3, [r3, #0] + 8001a2c: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001a30: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001a32: 4b18 ldr r3, [pc, #96] @ (8001a94 ) + 8001a34: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a36: 4a17 ldr r2, [pc, #92] @ (8001a94 ) + 8001a38: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001a3c: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001a3e: 697b ldr r3, [r7, #20] + 8001a40: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001a44: d105 bne.n 8001a52 + 8001a46: 687b ldr r3, [r7, #4] + 8001a48: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001a4c: d101 bne.n 8001a52 + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001a4e: 2301 movs r3, #1 + 8001a50: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001a52: 693b ldr r3, [r7, #16] + 8001a54: 2b01 cmp r3, #1 + 8001a56: d105 bne.n 8001a64 + 8001a58: 4b10 ldr r3, [pc, #64] @ (8001a9c ) + 8001a5a: 681b ldr r3, [r3, #0] + 8001a5c: 4a0f ldr r2, [pc, #60] @ (8001a9c ) + 8001a5e: f043 0304 orr.w r3, r3, #4 + 8001a62: 6013 str r3, [r2, #0] + 8001a64: 4b0d ldr r3, [pc, #52] @ (8001a9c ) + 8001a66: 681b ldr r3, [r3, #0] + 8001a68: f023 0201 bic.w r2, r3, #1 + 8001a6c: 490b ldr r1, [pc, #44] @ (8001a9c ) + 8001a6e: 693b ldr r3, [r7, #16] + 8001a70: 4313 orrs r3, r2 + 8001a72: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001a74: 4b09 ldr r3, [pc, #36] @ (8001a9c ) + 8001a76: 681b ldr r3, [r3, #0] + 8001a78: f003 0301 and.w r3, r3, #1 + 8001a7c: 693a ldr r2, [r7, #16] + 8001a7e: 429a cmp r2, r3 + 8001a80: d001 beq.n 8001a86 + { + return HAL_ERROR; + 8001a82: 2301 movs r3, #1 + 8001a84: e000 b.n 8001a88 + } + + return HAL_OK; + 8001a86: 2300 movs r3, #0 +} + 8001a88: 4618 mov r0, r3 + 8001a8a: 371c adds r7, #28 + 8001a8c: 46bd mov sp, r7 + 8001a8e: bc80 pop {r7} + 8001a90: 4770 bx lr + 8001a92: bf00 nop + 8001a94: 40023800 .word 0x40023800 + 8001a98: 40007000 .word 0x40007000 + 8001a9c: 40023c00 .word 0x40023c00 + +08001aa0 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001aa0: b580 push {r7, lr} + 8001aa2: b082 sub sp, #8 + 8001aa4: af00 add r7, sp, #0 + 8001aa6: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001aa8: 687b ldr r3, [r7, #4] + 8001aaa: 2b00 cmp r3, #0 + 8001aac: d101 bne.n 8001ab2 + { + return HAL_ERROR; + 8001aae: 2301 movs r3, #1 + 8001ab0: e07b b.n 8001baa + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001ab2: 687b ldr r3, [r7, #4] + 8001ab4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ab6: 2b00 cmp r3, #0 + 8001ab8: d108 bne.n 8001acc + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001aba: 687b ldr r3, [r7, #4] + 8001abc: 685b ldr r3, [r3, #4] + 8001abe: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001ac2: d009 beq.n 8001ad8 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001ac4: 687b ldr r3, [r7, #4] + 8001ac6: 2200 movs r2, #0 + 8001ac8: 61da str r2, [r3, #28] + 8001aca: e005 b.n 8001ad8 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001acc: 687b ldr r3, [r7, #4] + 8001ace: 2200 movs r2, #0 + 8001ad0: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001ad2: 687b ldr r3, [r7, #4] + 8001ad4: 2200 movs r2, #0 + 8001ad6: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001ad8: 687b ldr r3, [r7, #4] + 8001ada: 2200 movs r2, #0 + 8001adc: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001ade: 687b ldr r3, [r7, #4] + 8001ae0: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001ae4: b2db uxtb r3, r3 + 8001ae6: 2b00 cmp r3, #0 + 8001ae8: d106 bne.n 8001af8 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001aea: 687b ldr r3, [r7, #4] + 8001aec: 2200 movs r2, #0 + 8001aee: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001af2: 6878 ldr r0, [r7, #4] + 8001af4: f7fe fe1e bl 8000734 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001af8: 687b ldr r3, [r7, #4] + 8001afa: 2202 movs r2, #2 + 8001afc: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001b00: 687b ldr r3, [r7, #4] + 8001b02: 681b ldr r3, [r3, #0] + 8001b04: 681a ldr r2, [r3, #0] + 8001b06: 687b ldr r3, [r7, #4] + 8001b08: 681b ldr r3, [r3, #0] + 8001b0a: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001b0e: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001b10: 687b ldr r3, [r7, #4] + 8001b12: 685b ldr r3, [r3, #4] + 8001b14: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001b18: 687b ldr r3, [r7, #4] + 8001b1a: 689b ldr r3, [r3, #8] + 8001b1c: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001b20: 431a orrs r2, r3 + 8001b22: 687b ldr r3, [r7, #4] + 8001b24: 68db ldr r3, [r3, #12] + 8001b26: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001b2a: 431a orrs r2, r3 + 8001b2c: 687b ldr r3, [r7, #4] + 8001b2e: 691b ldr r3, [r3, #16] + 8001b30: f003 0302 and.w r3, r3, #2 + 8001b34: 431a orrs r2, r3 + 8001b36: 687b ldr r3, [r7, #4] + 8001b38: 695b ldr r3, [r3, #20] + 8001b3a: f003 0301 and.w r3, r3, #1 + 8001b3e: 431a orrs r2, r3 + 8001b40: 687b ldr r3, [r7, #4] + 8001b42: 699b ldr r3, [r3, #24] + 8001b44: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001b48: 431a orrs r2, r3 + 8001b4a: 687b ldr r3, [r7, #4] + 8001b4c: 69db ldr r3, [r3, #28] + 8001b4e: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001b52: 431a orrs r2, r3 + 8001b54: 687b ldr r3, [r7, #4] + 8001b56: 6a1b ldr r3, [r3, #32] + 8001b58: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001b5c: ea42 0103 orr.w r1, r2, r3 + 8001b60: 687b ldr r3, [r7, #4] + 8001b62: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001b64: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001b68: 687b ldr r3, [r7, #4] + 8001b6a: 681b ldr r3, [r3, #0] + 8001b6c: 430a orrs r2, r1 + 8001b6e: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8001b70: 687b ldr r3, [r7, #4] + 8001b72: 699b ldr r3, [r3, #24] + 8001b74: 0c1b lsrs r3, r3, #16 + 8001b76: f003 0104 and.w r1, r3, #4 + 8001b7a: 687b ldr r3, [r7, #4] + 8001b7c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001b7e: f003 0210 and.w r2, r3, #16 + 8001b82: 687b ldr r3, [r7, #4] + 8001b84: 681b ldr r3, [r3, #0] + 8001b86: 430a orrs r2, r1 + 8001b88: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8001b8a: 687b ldr r3, [r7, #4] + 8001b8c: 681b ldr r3, [r3, #0] + 8001b8e: 69da ldr r2, [r3, #28] + 8001b90: 687b ldr r3, [r7, #4] + 8001b92: 681b ldr r3, [r3, #0] + 8001b94: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001b98: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001b9a: 687b ldr r3, [r7, #4] + 8001b9c: 2200 movs r2, #0 + 8001b9e: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8001ba0: 687b ldr r3, [r7, #4] + 8001ba2: 2201 movs r2, #1 + 8001ba4: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8001ba8: 2300 movs r3, #0 +} + 8001baa: 4618 mov r0, r3 + 8001bac: 3708 adds r7, #8 + 8001bae: 46bd mov sp, r7 + 8001bb0: bd80 pop {r7, pc} + +08001bb2 : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8001bb2: b580 push {r7, lr} + 8001bb4: b088 sub sp, #32 + 8001bb6: af00 add r7, sp, #0 + 8001bb8: 60f8 str r0, [r7, #12] + 8001bba: 60b9 str r1, [r7, #8] + 8001bbc: 603b str r3, [r7, #0] + 8001bbe: 4613 mov r3, r2 + 8001bc0: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001bc2: f7fe ff33 bl 8000a2c + 8001bc6: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8001bc8: 88fb ldrh r3, [r7, #6] + 8001bca: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8001bcc: 68fb ldr r3, [r7, #12] + 8001bce: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001bd2: b2db uxtb r3, r3 + 8001bd4: 2b01 cmp r3, #1 + 8001bd6: d001 beq.n 8001bdc + { + return HAL_BUSY; + 8001bd8: 2302 movs r3, #2 + 8001bda: e12a b.n 8001e32 + } + + if ((pData == NULL) || (Size == 0U)) + 8001bdc: 68bb ldr r3, [r7, #8] + 8001bde: 2b00 cmp r3, #0 + 8001be0: d002 beq.n 8001be8 + 8001be2: 88fb ldrh r3, [r7, #6] + 8001be4: 2b00 cmp r3, #0 + 8001be6: d101 bne.n 8001bec + { + return HAL_ERROR; + 8001be8: 2301 movs r3, #1 + 8001bea: e122 b.n 8001e32 + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 8001bec: 68fb ldr r3, [r7, #12] + 8001bee: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001bf2: 2b01 cmp r3, #1 + 8001bf4: d101 bne.n 8001bfa + 8001bf6: 2302 movs r3, #2 + 8001bf8: e11b b.n 8001e32 + 8001bfa: 68fb ldr r3, [r7, #12] + 8001bfc: 2201 movs r2, #1 + 8001bfe: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8001c02: 68fb ldr r3, [r7, #12] + 8001c04: 2203 movs r2, #3 + 8001c06: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001c0a: 68fb ldr r3, [r7, #12] + 8001c0c: 2200 movs r2, #0 + 8001c0e: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8001c10: 68fb ldr r3, [r7, #12] + 8001c12: 68ba ldr r2, [r7, #8] + 8001c14: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 8001c16: 68fb ldr r3, [r7, #12] + 8001c18: 88fa ldrh r2, [r7, #6] + 8001c1a: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8001c1c: 68fb ldr r3, [r7, #12] + 8001c1e: 88fa ldrh r2, [r7, #6] + 8001c20: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8001c22: 68fb ldr r3, [r7, #12] + 8001c24: 2200 movs r2, #0 + 8001c26: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 8001c28: 68fb ldr r3, [r7, #12] + 8001c2a: 2200 movs r2, #0 + 8001c2c: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8001c2e: 68fb ldr r3, [r7, #12] + 8001c30: 2200 movs r2, #0 + 8001c32: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 8001c34: 68fb ldr r3, [r7, #12] + 8001c36: 2200 movs r2, #0 + 8001c38: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8001c3a: 68fb ldr r3, [r7, #12] + 8001c3c: 2200 movs r2, #0 + 8001c3e: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8001c40: 68fb ldr r3, [r7, #12] + 8001c42: 689b ldr r3, [r3, #8] + 8001c44: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001c48: d10f bne.n 8001c6a + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8001c4a: 68fb ldr r3, [r7, #12] + 8001c4c: 681b ldr r3, [r3, #0] + 8001c4e: 681a ldr r2, [r3, #0] + 8001c50: 68fb ldr r3, [r7, #12] + 8001c52: 681b ldr r3, [r3, #0] + 8001c54: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001c58: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8001c5a: 68fb ldr r3, [r7, #12] + 8001c5c: 681b ldr r3, [r3, #0] + 8001c5e: 681a ldr r2, [r3, #0] + 8001c60: 68fb ldr r3, [r7, #12] + 8001c62: 681b ldr r3, [r3, #0] + 8001c64: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8001c68: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8001c6a: 68fb ldr r3, [r7, #12] + 8001c6c: 681b ldr r3, [r3, #0] + 8001c6e: 681b ldr r3, [r3, #0] + 8001c70: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001c74: 2b40 cmp r3, #64 @ 0x40 + 8001c76: d007 beq.n 8001c88 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8001c78: 68fb ldr r3, [r7, #12] + 8001c7a: 681b ldr r3, [r3, #0] + 8001c7c: 681a ldr r2, [r3, #0] + 8001c7e: 68fb ldr r3, [r7, #12] + 8001c80: 681b ldr r3, [r3, #0] + 8001c82: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8001c86: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8001c88: 68fb ldr r3, [r7, #12] + 8001c8a: 68db ldr r3, [r3, #12] + 8001c8c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8001c90: d152 bne.n 8001d38 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001c92: 68fb ldr r3, [r7, #12] + 8001c94: 685b ldr r3, [r3, #4] + 8001c96: 2b00 cmp r3, #0 + 8001c98: d002 beq.n 8001ca0 + 8001c9a: 8b7b ldrh r3, [r7, #26] + 8001c9c: 2b01 cmp r3, #1 + 8001c9e: d145 bne.n 8001d2c + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001ca0: 68fb ldr r3, [r7, #12] + 8001ca2: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ca4: 881a ldrh r2, [r3, #0] + 8001ca6: 68fb ldr r3, [r7, #12] + 8001ca8: 681b ldr r3, [r3, #0] + 8001caa: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001cac: 68fb ldr r3, [r7, #12] + 8001cae: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001cb0: 1c9a adds r2, r3, #2 + 8001cb2: 68fb ldr r3, [r7, #12] + 8001cb4: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001cb6: 68fb ldr r3, [r7, #12] + 8001cb8: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001cba: b29b uxth r3, r3 + 8001cbc: 3b01 subs r3, #1 + 8001cbe: b29a uxth r2, r3 + 8001cc0: 68fb ldr r3, [r7, #12] + 8001cc2: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 8001cc4: e032 b.n 8001d2c + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001cc6: 68fb ldr r3, [r7, #12] + 8001cc8: 681b ldr r3, [r3, #0] + 8001cca: 689b ldr r3, [r3, #8] + 8001ccc: f003 0302 and.w r3, r3, #2 + 8001cd0: 2b02 cmp r3, #2 + 8001cd2: d112 bne.n 8001cfa + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001cd4: 68fb ldr r3, [r7, #12] + 8001cd6: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001cd8: 881a ldrh r2, [r3, #0] + 8001cda: 68fb ldr r3, [r7, #12] + 8001cdc: 681b ldr r3, [r3, #0] + 8001cde: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001ce0: 68fb ldr r3, [r7, #12] + 8001ce2: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ce4: 1c9a adds r2, r3, #2 + 8001ce6: 68fb ldr r3, [r7, #12] + 8001ce8: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001cea: 68fb ldr r3, [r7, #12] + 8001cec: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001cee: b29b uxth r3, r3 + 8001cf0: 3b01 subs r3, #1 + 8001cf2: b29a uxth r2, r3 + 8001cf4: 68fb ldr r3, [r7, #12] + 8001cf6: 86da strh r2, [r3, #54] @ 0x36 + 8001cf8: e018 b.n 8001d2c + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001cfa: f7fe fe97 bl 8000a2c + 8001cfe: 4602 mov r2, r0 + 8001d00: 69fb ldr r3, [r7, #28] + 8001d02: 1ad3 subs r3, r2, r3 + 8001d04: 683a ldr r2, [r7, #0] + 8001d06: 429a cmp r2, r3 + 8001d08: d803 bhi.n 8001d12 + 8001d0a: 683b ldr r3, [r7, #0] + 8001d0c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001d10: d102 bne.n 8001d18 + 8001d12: 683b ldr r3, [r7, #0] + 8001d14: 2b00 cmp r3, #0 + 8001d16: d109 bne.n 8001d2c + { + hspi->State = HAL_SPI_STATE_READY; + 8001d18: 68fb ldr r3, [r7, #12] + 8001d1a: 2201 movs r2, #1 + 8001d1c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001d20: 68fb ldr r3, [r7, #12] + 8001d22: 2200 movs r2, #0 + 8001d24: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001d28: 2303 movs r3, #3 + 8001d2a: e082 b.n 8001e32 + while (hspi->TxXferCount > 0U) + 8001d2c: 68fb ldr r3, [r7, #12] + 8001d2e: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d30: b29b uxth r3, r3 + 8001d32: 2b00 cmp r3, #0 + 8001d34: d1c7 bne.n 8001cc6 + 8001d36: e053 b.n 8001de0 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001d38: 68fb ldr r3, [r7, #12] + 8001d3a: 685b ldr r3, [r3, #4] + 8001d3c: 2b00 cmp r3, #0 + 8001d3e: d002 beq.n 8001d46 + 8001d40: 8b7b ldrh r3, [r7, #26] + 8001d42: 2b01 cmp r3, #1 + 8001d44: d147 bne.n 8001dd6 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001d46: 68fb ldr r3, [r7, #12] + 8001d48: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001d4a: 68fb ldr r3, [r7, #12] + 8001d4c: 681b ldr r3, [r3, #0] + 8001d4e: 330c adds r3, #12 + 8001d50: 7812 ldrb r2, [r2, #0] + 8001d52: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001d54: 68fb ldr r3, [r7, #12] + 8001d56: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d58: 1c5a adds r2, r3, #1 + 8001d5a: 68fb ldr r3, [r7, #12] + 8001d5c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001d5e: 68fb ldr r3, [r7, #12] + 8001d60: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d62: b29b uxth r3, r3 + 8001d64: 3b01 subs r3, #1 + 8001d66: b29a uxth r2, r3 + 8001d68: 68fb ldr r3, [r7, #12] + 8001d6a: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8001d6c: e033 b.n 8001dd6 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001d6e: 68fb ldr r3, [r7, #12] + 8001d70: 681b ldr r3, [r3, #0] + 8001d72: 689b ldr r3, [r3, #8] + 8001d74: f003 0302 and.w r3, r3, #2 + 8001d78: 2b02 cmp r3, #2 + 8001d7a: d113 bne.n 8001da4 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001d7c: 68fb ldr r3, [r7, #12] + 8001d7e: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001d80: 68fb ldr r3, [r7, #12] + 8001d82: 681b ldr r3, [r3, #0] + 8001d84: 330c adds r3, #12 + 8001d86: 7812 ldrb r2, [r2, #0] + 8001d88: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001d8a: 68fb ldr r3, [r7, #12] + 8001d8c: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d8e: 1c5a adds r2, r3, #1 + 8001d90: 68fb ldr r3, [r7, #12] + 8001d92: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001d94: 68fb ldr r3, [r7, #12] + 8001d96: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d98: b29b uxth r3, r3 + 8001d9a: 3b01 subs r3, #1 + 8001d9c: b29a uxth r2, r3 + 8001d9e: 68fb ldr r3, [r7, #12] + 8001da0: 86da strh r2, [r3, #54] @ 0x36 + 8001da2: e018 b.n 8001dd6 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001da4: f7fe fe42 bl 8000a2c + 8001da8: 4602 mov r2, r0 + 8001daa: 69fb ldr r3, [r7, #28] + 8001dac: 1ad3 subs r3, r2, r3 + 8001dae: 683a ldr r2, [r7, #0] + 8001db0: 429a cmp r2, r3 + 8001db2: d803 bhi.n 8001dbc + 8001db4: 683b ldr r3, [r7, #0] + 8001db6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001dba: d102 bne.n 8001dc2 + 8001dbc: 683b ldr r3, [r7, #0] + 8001dbe: 2b00 cmp r3, #0 + 8001dc0: d109 bne.n 8001dd6 + { + hspi->State = HAL_SPI_STATE_READY; + 8001dc2: 68fb ldr r3, [r7, #12] + 8001dc4: 2201 movs r2, #1 + 8001dc6: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001dca: 68fb ldr r3, [r7, #12] + 8001dcc: 2200 movs r2, #0 + 8001dce: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001dd2: 2303 movs r3, #3 + 8001dd4: e02d b.n 8001e32 + while (hspi->TxXferCount > 0U) + 8001dd6: 68fb ldr r3, [r7, #12] + 8001dd8: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001dda: b29b uxth r3, r3 + 8001ddc: 2b00 cmp r3, #0 + 8001dde: d1c6 bne.n 8001d6e + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 8001de0: 69fa ldr r2, [r7, #28] + 8001de2: 6839 ldr r1, [r7, #0] + 8001de4: 68f8 ldr r0, [r7, #12] + 8001de6: f000 f8b1 bl 8001f4c + 8001dea: 4603 mov r3, r0 + 8001dec: 2b00 cmp r3, #0 + 8001dee: d002 beq.n 8001df6 + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 8001df0: 68fb ldr r3, [r7, #12] + 8001df2: 2220 movs r2, #32 + 8001df4: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 8001df6: 68fb ldr r3, [r7, #12] + 8001df8: 689b ldr r3, [r3, #8] + 8001dfa: 2b00 cmp r3, #0 + 8001dfc: d10a bne.n 8001e14 + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 8001dfe: 2300 movs r3, #0 + 8001e00: 617b str r3, [r7, #20] + 8001e02: 68fb ldr r3, [r7, #12] + 8001e04: 681b ldr r3, [r3, #0] + 8001e06: 68db ldr r3, [r3, #12] + 8001e08: 617b str r3, [r7, #20] + 8001e0a: 68fb ldr r3, [r7, #12] + 8001e0c: 681b ldr r3, [r3, #0] + 8001e0e: 689b ldr r3, [r3, #8] + 8001e10: 617b str r3, [r7, #20] + 8001e12: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 8001e14: 68fb ldr r3, [r7, #12] + 8001e16: 2201 movs r2, #1 + 8001e18: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8001e1c: 68fb ldr r3, [r7, #12] + 8001e1e: 2200 movs r2, #0 + 8001e20: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 8001e24: 68fb ldr r3, [r7, #12] + 8001e26: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001e28: 2b00 cmp r3, #0 + 8001e2a: d001 beq.n 8001e30 + { + return HAL_ERROR; + 8001e2c: 2301 movs r3, #1 + 8001e2e: e000 b.n 8001e32 + } + else + { + return HAL_OK; + 8001e30: 2300 movs r3, #0 + } +} + 8001e32: 4618 mov r0, r3 + 8001e34: 3720 adds r7, #32 + 8001e36: 46bd mov sp, r7 + 8001e38: bd80 pop {r7, pc} + ... + +08001e3c : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8001e3c: b580 push {r7, lr} + 8001e3e: b088 sub sp, #32 + 8001e40: af00 add r7, sp, #0 + 8001e42: 60f8 str r0, [r7, #12] + 8001e44: 60b9 str r1, [r7, #8] + 8001e46: 603b str r3, [r7, #0] + 8001e48: 4613 mov r3, r2 + 8001e4a: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 8001e4c: f7fe fdee bl 8000a2c + 8001e50: 4602 mov r2, r0 + 8001e52: 6abb ldr r3, [r7, #40] @ 0x28 + 8001e54: 1a9b subs r3, r3, r2 + 8001e56: 683a ldr r2, [r7, #0] + 8001e58: 4413 add r3, r2 + 8001e5a: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 8001e5c: f7fe fde6 bl 8000a2c + 8001e60: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 8001e62: 4b39 ldr r3, [pc, #228] @ (8001f48 ) + 8001e64: 681b ldr r3, [r3, #0] + 8001e66: 015b lsls r3, r3, #5 + 8001e68: 0d1b lsrs r3, r3, #20 + 8001e6a: 69fa ldr r2, [r7, #28] + 8001e6c: fb02 f303 mul.w r3, r2, r3 + 8001e70: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8001e72: e054 b.n 8001f1e + { + if (Timeout != HAL_MAX_DELAY) + 8001e74: 683b ldr r3, [r7, #0] + 8001e76: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001e7a: d050 beq.n 8001f1e + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8001e7c: f7fe fdd6 bl 8000a2c + 8001e80: 4602 mov r2, r0 + 8001e82: 69bb ldr r3, [r7, #24] + 8001e84: 1ad3 subs r3, r2, r3 + 8001e86: 69fa ldr r2, [r7, #28] + 8001e88: 429a cmp r2, r3 + 8001e8a: d902 bls.n 8001e92 + 8001e8c: 69fb ldr r3, [r7, #28] + 8001e8e: 2b00 cmp r3, #0 + 8001e90: d13d bne.n 8001f0e + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8001e92: 68fb ldr r3, [r7, #12] + 8001e94: 681b ldr r3, [r3, #0] + 8001e96: 685a ldr r2, [r3, #4] + 8001e98: 68fb ldr r3, [r7, #12] + 8001e9a: 681b ldr r3, [r3, #0] + 8001e9c: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8001ea0: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8001ea2: 68fb ldr r3, [r7, #12] + 8001ea4: 685b ldr r3, [r3, #4] + 8001ea6: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001eaa: d111 bne.n 8001ed0 + 8001eac: 68fb ldr r3, [r7, #12] + 8001eae: 689b ldr r3, [r3, #8] + 8001eb0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001eb4: d004 beq.n 8001ec0 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 8001eb6: 68fb ldr r3, [r7, #12] + 8001eb8: 689b ldr r3, [r3, #8] + 8001eba: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8001ebe: d107 bne.n 8001ed0 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001ec0: 68fb ldr r3, [r7, #12] + 8001ec2: 681b ldr r3, [r3, #0] + 8001ec4: 681a ldr r2, [r3, #0] + 8001ec6: 68fb ldr r3, [r7, #12] + 8001ec8: 681b ldr r3, [r3, #0] + 8001eca: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001ece: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8001ed0: 68fb ldr r3, [r7, #12] + 8001ed2: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001ed4: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8001ed8: d10f bne.n 8001efa + { + SPI_RESET_CRC(hspi); + 8001eda: 68fb ldr r3, [r7, #12] + 8001edc: 681b ldr r3, [r3, #0] + 8001ede: 681a ldr r2, [r3, #0] + 8001ee0: 68fb ldr r3, [r7, #12] + 8001ee2: 681b ldr r3, [r3, #0] + 8001ee4: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 8001ee8: 601a str r2, [r3, #0] + 8001eea: 68fb ldr r3, [r7, #12] + 8001eec: 681b ldr r3, [r3, #0] + 8001eee: 681a ldr r2, [r3, #0] + 8001ef0: 68fb ldr r3, [r7, #12] + 8001ef2: 681b ldr r3, [r3, #0] + 8001ef4: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 8001ef8: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 8001efa: 68fb ldr r3, [r7, #12] + 8001efc: 2201 movs r2, #1 + 8001efe: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8001f02: 68fb ldr r3, [r7, #12] + 8001f04: 2200 movs r2, #0 + 8001f06: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 8001f0a: 2303 movs r3, #3 + 8001f0c: e017 b.n 8001f3e + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 8001f0e: 697b ldr r3, [r7, #20] + 8001f10: 2b00 cmp r3, #0 + 8001f12: d101 bne.n 8001f18 + { + tmp_timeout = 0U; + 8001f14: 2300 movs r3, #0 + 8001f16: 61fb str r3, [r7, #28] + } + count--; + 8001f18: 697b ldr r3, [r7, #20] + 8001f1a: 3b01 subs r3, #1 + 8001f1c: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8001f1e: 68fb ldr r3, [r7, #12] + 8001f20: 681b ldr r3, [r3, #0] + 8001f22: 689a ldr r2, [r3, #8] + 8001f24: 68bb ldr r3, [r7, #8] + 8001f26: 4013 ands r3, r2 + 8001f28: 68ba ldr r2, [r7, #8] + 8001f2a: 429a cmp r2, r3 + 8001f2c: bf0c ite eq + 8001f2e: 2301 moveq r3, #1 + 8001f30: 2300 movne r3, #0 + 8001f32: b2db uxtb r3, r3 + 8001f34: 461a mov r2, r3 + 8001f36: 79fb ldrb r3, [r7, #7] + 8001f38: 429a cmp r2, r3 + 8001f3a: d19b bne.n 8001e74 + } + } + + return HAL_OK; + 8001f3c: 2300 movs r3, #0 +} + 8001f3e: 4618 mov r0, r3 + 8001f40: 3720 adds r7, #32 + 8001f42: 46bd mov sp, r7 + 8001f44: bd80 pop {r7, pc} + 8001f46: bf00 nop + 8001f48: 20000000 .word 0x20000000 + +08001f4c : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 8001f4c: b580 push {r7, lr} + 8001f4e: b088 sub sp, #32 + 8001f50: af02 add r7, sp, #8 + 8001f52: 60f8 str r0, [r7, #12] + 8001f54: 60b9 str r1, [r7, #8] + 8001f56: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 8001f58: 687b ldr r3, [r7, #4] + 8001f5a: 9300 str r3, [sp, #0] + 8001f5c: 68bb ldr r3, [r7, #8] + 8001f5e: 2201 movs r2, #1 + 8001f60: 2102 movs r1, #2 + 8001f62: 68f8 ldr r0, [r7, #12] + 8001f64: f7ff ff6a bl 8001e3c + 8001f68: 4603 mov r3, r0 + 8001f6a: 2b00 cmp r3, #0 + 8001f6c: d007 beq.n 8001f7e + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8001f6e: 68fb ldr r3, [r7, #12] + 8001f70: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f72: f043 0220 orr.w r2, r3, #32 + 8001f76: 68fb ldr r3, [r7, #12] + 8001f78: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8001f7a: 2303 movs r3, #3 + 8001f7c: e032 b.n 8001fe4 + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 8001f7e: 4b1b ldr r3, [pc, #108] @ (8001fec ) + 8001f80: 681b ldr r3, [r3, #0] + 8001f82: 4a1b ldr r2, [pc, #108] @ (8001ff0 ) + 8001f84: fba2 2303 umull r2, r3, r2, r3 + 8001f88: 0d5b lsrs r3, r3, #21 + 8001f8a: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8001f8e: fb02 f303 mul.w r3, r2, r3 + 8001f92: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001f94: 68fb ldr r3, [r7, #12] + 8001f96: 685b ldr r3, [r3, #4] + 8001f98: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001f9c: d112 bne.n 8001fc4 + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8001f9e: 687b ldr r3, [r7, #4] + 8001fa0: 9300 str r3, [sp, #0] + 8001fa2: 68bb ldr r3, [r7, #8] + 8001fa4: 2200 movs r2, #0 + 8001fa6: 2180 movs r1, #128 @ 0x80 + 8001fa8: 68f8 ldr r0, [r7, #12] + 8001faa: f7ff ff47 bl 8001e3c + 8001fae: 4603 mov r3, r0 + 8001fb0: 2b00 cmp r3, #0 + 8001fb2: d016 beq.n 8001fe2 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8001fb4: 68fb ldr r3, [r7, #12] + 8001fb6: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001fb8: f043 0220 orr.w r2, r3, #32 + 8001fbc: 68fb ldr r3, [r7, #12] + 8001fbe: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8001fc0: 2303 movs r3, #3 + 8001fc2: e00f b.n 8001fe4 + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 8001fc4: 697b ldr r3, [r7, #20] + 8001fc6: 2b00 cmp r3, #0 + 8001fc8: d00a beq.n 8001fe0 + { + break; + } + count--; + 8001fca: 697b ldr r3, [r7, #20] + 8001fcc: 3b01 subs r3, #1 + 8001fce: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 8001fd0: 68fb ldr r3, [r7, #12] + 8001fd2: 681b ldr r3, [r3, #0] + 8001fd4: 689b ldr r3, [r3, #8] + 8001fd6: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001fda: 2b80 cmp r3, #128 @ 0x80 + 8001fdc: d0f2 beq.n 8001fc4 + 8001fde: e000 b.n 8001fe2 + break; + 8001fe0: bf00 nop + } + + return HAL_OK; + 8001fe2: 2300 movs r3, #0 +} + 8001fe4: 4618 mov r0, r3 + 8001fe6: 3718 adds r7, #24 + 8001fe8: 46bd mov sp, r7 + 8001fea: bd80 pop {r7, pc} + 8001fec: 20000000 .word 0x20000000 + 8001ff0: 165e9f81 .word 0x165e9f81 + +08001ff4 : + 8001ff4: 4603 mov r3, r0 + 8001ff6: 4402 add r2, r0 + 8001ff8: 4293 cmp r3, r2 + 8001ffa: d100 bne.n 8001ffe + 8001ffc: 4770 bx lr + 8001ffe: f803 1b01 strb.w r1, [r3], #1 + 8002002: e7f9 b.n 8001ff8 + +08002004 <__libc_init_array>: + 8002004: b570 push {r4, r5, r6, lr} + 8002006: 2600 movs r6, #0 + 8002008: 4d0c ldr r5, [pc, #48] @ (800203c <__libc_init_array+0x38>) + 800200a: 4c0d ldr r4, [pc, #52] @ (8002040 <__libc_init_array+0x3c>) + 800200c: 1b64 subs r4, r4, r5 + 800200e: 10a4 asrs r4, r4, #2 + 8002010: 42a6 cmp r6, r4 + 8002012: d109 bne.n 8002028 <__libc_init_array+0x24> + 8002014: f000 f81a bl 800204c <_init> + 8002018: 2600 movs r6, #0 + 800201a: 4d0a ldr r5, [pc, #40] @ (8002044 <__libc_init_array+0x40>) + 800201c: 4c0a ldr r4, [pc, #40] @ (8002048 <__libc_init_array+0x44>) + 800201e: 1b64 subs r4, r4, r5 + 8002020: 10a4 asrs r4, r4, #2 + 8002022: 42a6 cmp r6, r4 + 8002024: d105 bne.n 8002032 <__libc_init_array+0x2e> + 8002026: bd70 pop {r4, r5, r6, pc} + 8002028: f855 3b04 ldr.w r3, [r5], #4 + 800202c: 4798 blx r3 + 800202e: 3601 adds r6, #1 + 8002030: e7ee b.n 8002010 <__libc_init_array+0xc> + 8002032: f855 3b04 ldr.w r3, [r5], #4 + 8002036: 4798 blx r3 + 8002038: 3601 adds r6, #1 + 800203a: e7f2 b.n 8002022 <__libc_init_array+0x1e> + 800203c: 08002088 .word 0x08002088 + 8002040: 08002088 .word 0x08002088 + 8002044: 08002088 .word 0x08002088 + 8002048: 0800208c .word 0x0800208c + +0800204c <_init>: + 800204c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800204e: bf00 nop + 8002050: bcf8 pop {r3, r4, r5, r6, r7} + 8002052: bc08 pop {r3} + 8002054: 469e mov lr, r3 + 8002056: 4770 bx lr + +08002058 <_fini>: + 8002058: b5f8 push {r3, r4, r5, r6, r7, lr} + 800205a: bf00 nop + 800205c: bcf8 pop {r3, r4, r5, r6, r7} + 800205e: bc08 pop {r3} + 8002060: 469e mov lr, r3 + 8002062: 4770 bx lr diff --git a/TP4_INIT_TFT/Debug/TP2_ISEN_DISPLAY.map b/TP4_INIT_TFT/Debug/TP2_ISEN_DISPLAY.map new file mode 100644 index 0000000..d61fceb --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP2_ISEN_DISPLAY.map @@ -0,0 +1,2895 @@ +Archive member included to satisfy reference by file (symbol) + +/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-exit.o) + /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o (exit) 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +START GROUP +LOAD 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g_pfnVectors + 0x0800013c . = ALIGN (0x4) + +.text 0x0800013c 0x1f28 + 0x0800013c . = ALIGN (0x4) + *(.text) + .text 0x0800013c 0x40 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + .text 0x0800017c 0x30 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x0800017c __aeabi_uldivmod + .text 0x080001ac 0x300 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + 0x080001ac __udivmoddi4 + .text 0x080004ac 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_dvmd_tls.o) + 0x080004ac __aeabi_ldiv0 + 0x080004ac __aeabi_idiv0 + *(.text*) + .text.displayScrollingText + 0x080004b0 0x86 ./Core/Src/main.o + 0x080004b0 displayScrollingText + .text.main 0x08000536 0x22 ./Core/Src/main.o + 0x08000536 main + .text.SystemClock_Config + 0x08000558 0x8c ./Core/Src/main.o + 0x08000558 SystemClock_Config + .text.MX_SPI1_Init + 0x080005e4 0x6c ./Core/Src/main.o + .text.MX_GPIO_Init + 0x08000650 0x7c ./Core/Src/main.o + .text.Error_Handler + 0x080006cc 0xc ./Core/Src/main.o + 0x080006cc Error_Handler + .text.HAL_MspInit + 0x080006d8 0x5c ./Core/Src/stm32l1xx_hal_msp.o + 0x080006d8 HAL_MspInit + .text.HAL_SPI_MspInit + 0x08000734 0x88 ./Core/Src/stm32l1xx_hal_msp.o + 0x08000734 HAL_SPI_MspInit + .text.NMI_Handler + 0x080007bc 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007bc NMI_Handler + .text.HardFault_Handler + 0x080007c4 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007c4 HardFault_Handler + .text.MemManage_Handler + 0x080007cc 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007cc MemManage_Handler + .text.BusFault_Handler + 0x080007d4 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007d4 BusFault_Handler + .text.UsageFault_Handler + 0x080007dc 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007dc UsageFault_Handler + .text.SVC_Handler + 0x080007e4 0xc ./Core/Src/stm32l1xx_it.o + 0x080007e4 SVC_Handler + .text.DebugMon_Handler + 0x080007f0 0xc ./Core/Src/stm32l1xx_it.o + 0x080007f0 DebugMon_Handler + .text.PendSV_Handler + 0x080007fc 0xc ./Core/Src/stm32l1xx_it.o + 0x080007fc PendSV_Handler + .text.SysTick_Handler + 0x08000808 0xc ./Core/Src/stm32l1xx_it.o + 0x08000808 SysTick_Handler + .text.SystemInit + 0x08000814 0xc ./Core/Src/system_stm32l1xx.o + 0x08000814 SystemInit + .text.Reset_Handler + 0x08000820 0x48 ./Core/Startup/startup_stm32l152retx.o + 0x08000820 Reset_Handler + .text.Default_Handler + 0x08000868 0x2 ./Core/Startup/startup_stm32l152retx.o + 0x08000868 DMA2_Channel3_IRQHandler + 0x08000868 EXTI2_IRQHandler + 0x08000868 COMP_ACQ_IRQHandler + 0x08000868 TIM10_IRQHandler + 0x08000868 USB_HP_IRQHandler + 0x08000868 TIM6_IRQHandler + 0x08000868 PVD_IRQHandler + 0x08000868 EXTI3_IRQHandler + 0x08000868 EXTI0_IRQHandler + 0x08000868 I2C2_EV_IRQHandler + 0x08000868 SPI1_IRQHandler + 0x08000868 USB_FS_WKUP_IRQHandler + 0x08000868 DMA2_Channel2_IRQHandler + 0x08000868 DMA1_Channel4_IRQHandler + 0x08000868 ADC1_IRQHandler + 0x08000868 USART3_IRQHandler + 0x08000868 DMA1_Channel7_IRQHandler + 0x08000868 LCD_IRQHandler + 0x08000868 UART5_IRQHandler + 0x08000868 TIM4_IRQHandler + 0x08000868 DMA2_Channel1_IRQHandler + 0x08000868 I2C1_EV_IRQHandler + 0x08000868 DMA1_Channel6_IRQHandler + 0x08000868 UART4_IRQHandler + 0x08000868 DMA2_Channel4_IRQHandler + 0x08000868 TIM3_IRQHandler + 0x08000868 RCC_IRQHandler + 0x08000868 DMA1_Channel1_IRQHandler + 0x08000868 Default_Handler + 0x08000868 EXTI15_10_IRQHandler + 0x08000868 TIM7_IRQHandler + 0x08000868 TIM5_IRQHandler + 0x08000868 EXTI9_5_IRQHandler + 0x08000868 TIM9_IRQHandler + 0x08000868 TAMPER_STAMP_IRQHandler + 0x08000868 RTC_WKUP_IRQHandler + 0x08000868 SPI2_IRQHandler + 0x08000868 DMA2_Channel5_IRQHandler + 0x08000868 DMA1_Channel5_IRQHandler + 0x08000868 USB_LP_IRQHandler + 0x08000868 EXTI4_IRQHandler + 0x08000868 DMA1_Channel3_IRQHandler + 0x08000868 COMP_IRQHandler + 0x08000868 WWDG_IRQHandler + 0x08000868 TIM2_IRQHandler + 0x08000868 DAC_IRQHandler + 0x08000868 EXTI1_IRQHandler + 0x08000868 TIM11_IRQHandler + 0x08000868 USART2_IRQHandler + 0x08000868 I2C2_ER_IRQHandler + 0x08000868 DMA1_Channel2_IRQHandler + 0x08000868 FLASH_IRQHandler + 0x08000868 USART1_IRQHandler + 0x08000868 SPI3_IRQHandler + 0x08000868 I2C1_ER_IRQHandler + 0x08000868 RTC_Alarm_IRQHandler + .text.MAX7219_Init + 0x0800086a 0x2a ./Drivers/7Seg_MAX7219/max7219.o + 0x0800086a MAX7219_Init + .text.MAX7219_ShutdownStop + 0x08000894 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x08000894 MAX7219_ShutdownStop + .text.MAX7219_DisplayTestStop + 0x080008a4 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x080008a4 MAX7219_DisplayTestStop + .text.MAX7219_SetBrightness + 0x080008b4 0x24 ./Drivers/7Seg_MAX7219/max7219.o + 0x080008b4 MAX7219_SetBrightness + .text.MAX7219_Clear + 0x080008d8 0x2c ./Drivers/7Seg_MAX7219/max7219.o + 0x080008d8 MAX7219_Clear + .text.MAX7219_Write + 0x08000904 0x3c ./Drivers/7Seg_MAX7219/max7219.o + 0x08000904 MAX7219_Write + .text.MAX7219_SendByte + 0x08000940 0x24 ./Drivers/7Seg_MAX7219/max7219.o + .text.HAL_Init + 0x08000964 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000964 HAL_Init + .text.HAL_InitTick + 0x08000994 0x74 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000994 HAL_InitTick + .text.HAL_IncTick + 0x08000a08 0x24 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a08 HAL_IncTick + .text.HAL_GetTick + 0x08000a2c 0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a2c HAL_GetTick + .text.HAL_Delay + 0x08000a40 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a40 HAL_Delay + .text.__NVIC_SetPriorityGrouping + 0x08000a84 0x48 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.__NVIC_GetPriorityGrouping + 0x08000acc 0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.__NVIC_SetPriority + 0x08000ae8 0x54 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.NVIC_EncodePriority + 0x08000b3c 0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.SysTick_Config + 0x08000ba0 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x08000be4 0x16 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000be4 HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x08000bfa 0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000bfa HAL_NVIC_SetPriority + .text.HAL_SYSTICK_Config + 0x08000c32 0x18 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000c32 HAL_SYSTICK_Config + *fill* 0x08000c4a 0x2 + .text.HAL_GPIO_Init + 0x08000c4c 0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000c4c HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x08000f6c 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000f6c HAL_GPIO_WritePin + .text.HAL_RCC_OscConfig + 0x08000f9c 0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08000f9c HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x080015fc 0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x080015fc HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x08001864 0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08001864 HAL_RCC_GetSysClockFreq + .text.RCC_SetFlashLatencyFromMSIRange + 0x080019e0 0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .text.HAL_SPI_Init + 0x08001aa0 0x112 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001aa0 HAL_SPI_Init + .text.HAL_SPI_Transmit + 0x08001bb2 0x288 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001bb2 HAL_SPI_Transmit + *fill* 0x08001e3a 0x2 + .text.SPI_WaitFlagStateUntilTimeout + 0x08001e3c 0x110 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .text.SPI_EndRxTxTransaction + 0x08001f4c 0xa8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .text.memset 0x08001ff4 0x10 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + 0x08001ff4 memset + .text.__libc_init_array + 0x08002004 0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + 0x08002004 __libc_init_array + *(.glue_7) + .glue_7 0x0800204c 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x0800204c 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x0800204c 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + *(.init) + .init 0x0800204c 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x0800204c _init + .init 0x08002050 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + *(.fini) + .fini 0x08002058 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x08002058 _fini + .fini 0x0800205c 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + 0x08002064 . = ALIGN (0x4) + 0x08002064 _etext = . + +.vfp11_veneer 0x08002064 0x0 + .vfp11_veneer 0x08002064 0x0 linker stubs + +.v4_bx 0x08002064 0x0 + .v4_bx 0x08002064 0x0 linker stubs + +.iplt 0x08002064 0x0 + .iplt 0x08002064 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + +.rodata 0x08002064 0x1c + 0x08002064 . = ALIGN (0x4) + *(.rodata) + *(.rodata*) + .rodata.PLLMulTable + 0x08002064 0x9 ./Core/Src/system_stm32l1xx.o + 0x08002064 PLLMulTable + *fill* 0x0800206d 0x3 + .rodata.AHBPrescTable + 0x08002070 0x10 ./Core/Src/system_stm32l1xx.o + 0x08002070 AHBPrescTable + 0x08002080 . = ALIGN (0x4) + +.ARM.extab 0x08002080 0x0 + 0x08002080 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x08002080 . = ALIGN (0x4) + +.ARM 0x08002080 0x8 + 0x08002080 . = ALIGN (0x4) + 0x08002080 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x08002080 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + 0x08002088 __exidx_end = . + 0x08002088 . = ALIGN (0x4) + +.preinit_array 0x08002088 0x0 + 0x08002088 . = ALIGN (0x4) + 0x08002088 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x08002088 PROVIDE (__preinit_array_end = .) + 0x08002088 . = ALIGN (0x4) + +.init_array 0x08002088 0x4 + 0x08002088 . = ALIGN (0x4) + 0x08002088 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x08002088 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + 0x0800208c PROVIDE (__init_array_end = .) + 0x0800208c . = ALIGN (0x4) + +.fini_array 0x0800208c 0x4 + 0x0800208c . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0800208c 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08002090 . = ALIGN (0x4) + 0x08002090 _sidata = LOADADDR (.data) + +.rel.dyn 0x08002090 0x0 + .rel.iplt 0x08002090 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + +.data 0x20000000 0xc load address 0x08002090 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x20000000 0x4 ./Core/Src/system_stm32l1xx.o + 0x20000000 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + +.debug_abbrev 0x00000000 0x148d + .debug_abbrev 0x00000000 0x2ad ./Core/Src/main.o + .debug_abbrev 0x000002ad 0x1ad ./Core/Src/stm32l1xx_hal_msp.o + .debug_abbrev 0x0000045a 0x73 ./Core/Src/stm32l1xx_it.o + .debug_abbrev 0x000004cd 0x11c ./Core/Src/system_stm32l1xx.o + .debug_abbrev 0x000005e9 0x24 ./Core/Startup/startup_stm32l152retx.o + .debug_abbrev 0x0000060d 0x1e9 ./Drivers/7Seg_MAX7219/max7219.o + .debug_abbrev 0x000007f6 0x275 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_abbrev 0x00000a6b 0x31c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_abbrev 0x00000d87 0x1d4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_abbrev 0x00000f5b 0x2b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_abbrev 0x00001213 0x27a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + +.debug_aranges 0x00000000 0x660 + .debug_aranges + 0x00000000 0x48 ./Core/Src/main.o + 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+ .debug_frame 0x00001844 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00001870 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x70 + .debug_line_str + 0x00000000 0x70 ./Core/Startup/startup_stm32l152retx.o diff --git a/TP4_INIT_TFT/Debug/TP3_M_A_TIMER_MODULO.list b/TP4_INIT_TFT/Debug/TP3_M_A_TIMER_MODULO.list new file mode 100644 index 0000000..2a01f3c --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP3_M_A_TIMER_MODULO.list @@ -0,0 +1,7251 @@ + +TP3_M_A_TIMER_MODULO.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000028c0 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000002c 080029fc 080029fc 000039fc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08002a28 08002a28 0000400c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08002a28 08002a28 00003a28 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08002a30 08002a30 0000400c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08002a30 08002a30 00003a30 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 08002a34 08002a34 00003a34 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000000c 20000000 08002a38 00004000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000000bc 2000000c 08002a44 0000400c 2**2 + ALLOC + 10 ._user_heap_stack 00000600 200000c8 08002a44 000040c8 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0 + CONTENTS, READONLY + 12 .debug_info 00009760 00000000 00000000 00004035 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 000019c7 00000000 00000000 0000d795 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000a90 00000000 00000000 0000f160 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 00000801 00000000 00000000 0000fbf0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000155f9 00000000 00000000 000103f1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0000a9e1 00000000 00000000 000259ea 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 00088678 00000000 00000000 000303cb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000b8a43 2**0 + CONTENTS, READONLY + 20 .debug_frame 00002bb4 00000000 00000000 000b8a88 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000bb63c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 2000000c .word 0x2000000c + 8000158: 00000000 .word 0x00000000 + 800015c: 080029e4 .word 0x080029e4 + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000010 .word 0x20000010 + 8000178: 080029e4 .word 0x080029e4 + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0 : +/* USER CODE BEGIN 0 */ + +volatile uint8_t marche = 0; +volatile uint8_t tempo_500ms_ok = 0; + +void affiche(uint8_t nombre) { + 80004b0: b580 push {r7, lr} + 80004b2: b084 sub sp, #16 + 80004b4: af00 add r7, sp, #0 + 80004b6: 4603 mov r3, r0 + 80004b8: 71fb strb r3, [r7, #7] + uint8_t compt_uni; + uint8_t compt_diz; + + compt_uni = nombre % 10; + 80004ba: 79fa ldrb r2, [r7, #7] + 80004bc: 4b13 ldr r3, [pc, #76] @ (800050c ) + 80004be: fba3 1302 umull r1, r3, r3, r2 + 80004c2: 08d9 lsrs r1, r3, #3 + 80004c4: 460b mov r3, r1 + 80004c6: 009b lsls r3, r3, #2 + 80004c8: 440b add r3, r1 + 80004ca: 005b lsls r3, r3, #1 + 80004cc: 1ad3 subs r3, r2, r3 + 80004ce: 73fb strb r3, [r7, #15] + compt_diz = nombre / 10; + 80004d0: 79fb ldrb r3, [r7, #7] + 80004d2: 4a0e ldr r2, [pc, #56] @ (800050c ) + 80004d4: fba2 2303 umull r2, r3, r2, r3 + 80004d8: 08db lsrs r3, r3, #3 + 80004da: 73bb strb r3, [r7, #14] + + MAX7219_DisplayChar(1, compt_diz); + 80004dc: 7bbb ldrb r3, [r7, #14] + 80004de: 4619 mov r1, r3 + 80004e0: 2001 movs r0, #1 + 80004e2: f000 faf1 bl 8000ac8 + MAX7219_DisplayChar(2, compt_uni); + 80004e6: 7bfb ldrb r3, [r7, #15] + 80004e8: 4619 mov r1, r3 + 80004ea: 2002 movs r0, #2 + 80004ec: f000 faec bl 8000ac8 + MAX7219_DisplayChar(3, compt_diz); + 80004f0: 7bbb ldrb r3, [r7, #14] + 80004f2: 4619 mov r1, r3 + 80004f4: 2003 movs r0, #3 + 80004f6: f000 fae7 bl 8000ac8 + MAX7219_DisplayChar(4, compt_uni); + 80004fa: 7bfb ldrb r3, [r7, #15] + 80004fc: 4619 mov r1, r3 + 80004fe: 2004 movs r0, #4 + 8000500: f000 fae2 bl 8000ac8 +} + 8000504: bf00 nop + 8000506: 3710 adds r7, #16 + 8000508: 46bd mov sp, r7 + 800050a: bd80 pop {r7, pc} + 800050c: cccccccd .word 0xcccccccd + +08000510
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000510: b580 push {r7, lr} + 8000512: b082 sub sp, #8 + 8000514: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000516: f000 fb1d bl 8000b54 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 800051a: f000 f82f bl 800057c + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 800051e: f000 f8f7 bl 8000710 + MX_SPI1_Init(); + 8000522: f000 f871 bl 8000608 + MX_TIM2_Init(); + 8000526: f000 f8a5 bl 8000674 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 800052a: f000 fa80 bl 8000a2e + HAL_TIM_Base_Start_IT(&htim2); + 800052e: 4810 ldr r0, [pc, #64] @ (8000570 ) + 8000530: f001 feb8 bl 80022a4 + uint8_t counter = 0; + 8000534: 2300 movs r3, #0 + 8000536: 71fb strb r3, [r7, #7] + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 8000538: f000 fab0 bl 8000a9c + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + if (marche && tempo_500ms_ok) { + 800053c: 4b0d ldr r3, [pc, #52] @ (8000574 ) + 800053e: 781b ldrb r3, [r3, #0] + 8000540: b2db uxtb r3, r3 + 8000542: 2b00 cmp r3, #0 + 8000544: d0fa beq.n 800053c + 8000546: 4b0c ldr r3, [pc, #48] @ (8000578 ) + 8000548: 781b ldrb r3, [r3, #0] + 800054a: b2db uxtb r3, r3 + 800054c: 2b00 cmp r3, #0 + 800054e: d0f5 beq.n 800053c + counter ++; + 8000550: 79fb ldrb r3, [r7, #7] + 8000552: 3301 adds r3, #1 + 8000554: 71fb strb r3, [r7, #7] + if (counter >= 100) { + 8000556: 79fb ldrb r3, [r7, #7] + 8000558: 2b63 cmp r3, #99 @ 0x63 + 800055a: d901 bls.n 8000560 + counter = 0; + 800055c: 2300 movs r3, #0 + 800055e: 71fb strb r3, [r7, #7] + } + affiche(counter); + 8000560: 79fb ldrb r3, [r7, #7] + 8000562: 4618 mov r0, r3 + 8000564: f7ff ffa4 bl 80004b0 + tempo_500ms_ok = 0; + 8000568: 4b03 ldr r3, [pc, #12] @ (8000578 ) + 800056a: 2200 movs r2, #0 + 800056c: 701a strb r2, [r3, #0] + if (marche && tempo_500ms_ok) { + 800056e: e7e5 b.n 800053c + 8000570: 20000080 .word 0x20000080 + 8000574: 200000c0 .word 0x200000c0 + 8000578: 200000c1 .word 0x200000c1 + +0800057c : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 800057c: b580 push {r7, lr} + 800057e: b092 sub sp, #72 @ 0x48 + 8000580: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000582: f107 0314 add.w r3, r7, #20 + 8000586: 2234 movs r2, #52 @ 0x34 + 8000588: 2100 movs r1, #0 + 800058a: 4618 mov r0, r3 + 800058c: f002 f9fe bl 800298c + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000590: 463b mov r3, r7 + 8000592: 2200 movs r2, #0 + 8000594: 601a str r2, [r3, #0] + 8000596: 605a str r2, [r3, #4] + 8000598: 609a str r2, [r3, #8] + 800059a: 60da str r2, [r3, #12] + 800059c: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 800059e: 4b19 ldr r3, [pc, #100] @ (8000604 ) + 80005a0: 681b ldr r3, [r3, #0] + 80005a2: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 80005a6: 4a17 ldr r2, [pc, #92] @ (8000604 ) + 80005a8: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 80005ac: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 80005ae: 2302 movs r3, #2 + 80005b0: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 80005b2: 2301 movs r3, #1 + 80005b4: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 80005b6: 2310 movs r3, #16 + 80005b8: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 80005ba: 2300 movs r3, #0 + 80005bc: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 80005be: f107 0314 add.w r3, r7, #20 + 80005c2: 4618 mov r0, r3 + 80005c4: f000 fe02 bl 80011cc + 80005c8: 4603 mov r3, r0 + 80005ca: 2b00 cmp r3, #0 + 80005cc: d001 beq.n 80005d2 + { + Error_Handler(); + 80005ce: f000 f925 bl 800081c + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80005d2: 230f movs r3, #15 + 80005d4: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 80005d6: 2301 movs r3, #1 + 80005d8: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80005da: 2300 movs r3, #0 + 80005dc: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80005de: 2300 movs r3, #0 + 80005e0: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80005e2: 2300 movs r3, #0 + 80005e4: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 80005e6: 463b mov r3, r7 + 80005e8: 2100 movs r1, #0 + 80005ea: 4618 mov r0, r3 + 80005ec: f001 f91e bl 800182c + 80005f0: 4603 mov r3, r0 + 80005f2: 2b00 cmp r3, #0 + 80005f4: d001 beq.n 80005fa + { + Error_Handler(); + 80005f6: f000 f911 bl 800081c + } +} + 80005fa: bf00 nop + 80005fc: 3748 adds r7, #72 @ 0x48 + 80005fe: 46bd mov sp, r7 + 8000600: bd80 pop {r7, pc} + 8000602: bf00 nop + 8000604: 40007000 .word 0x40007000 + +08000608 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 8000608: b580 push {r7, lr} + 800060a: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 800060c: 4b17 ldr r3, [pc, #92] @ (800066c ) + 800060e: 4a18 ldr r2, [pc, #96] @ (8000670 ) + 8000610: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 8000612: 4b16 ldr r3, [pc, #88] @ (800066c ) + 8000614: f44f 7282 mov.w r2, #260 @ 0x104 + 8000618: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 800061a: 4b14 ldr r3, [pc, #80] @ (800066c ) + 800061c: 2200 movs r2, #0 + 800061e: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 8000620: 4b12 ldr r3, [pc, #72] @ (800066c ) + 8000622: 2200 movs r2, #0 + 8000624: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 8000626: 4b11 ldr r3, [pc, #68] @ (800066c ) + 8000628: 2200 movs r2, #0 + 800062a: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 800062c: 4b0f ldr r3, [pc, #60] @ (800066c ) + 800062e: 2200 movs r2, #0 + 8000630: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 8000632: 4b0e ldr r3, [pc, #56] @ (800066c ) + 8000634: f44f 7200 mov.w r2, #512 @ 0x200 + 8000638: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 800063a: 4b0c ldr r3, [pc, #48] @ (800066c ) + 800063c: 2200 movs r2, #0 + 800063e: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 8000640: 4b0a ldr r3, [pc, #40] @ (800066c ) + 8000642: 2200 movs r2, #0 + 8000644: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 8000646: 4b09 ldr r3, [pc, #36] @ (800066c ) + 8000648: 2200 movs r2, #0 + 800064a: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 800064c: 4b07 ldr r3, [pc, #28] @ (800066c ) + 800064e: 2200 movs r2, #0 + 8000650: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 8000652: 4b06 ldr r3, [pc, #24] @ (800066c ) + 8000654: 220a movs r2, #10 + 8000656: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8000658: 4804 ldr r0, [pc, #16] @ (800066c ) + 800065a: f001 fb39 bl 8001cd0 + 800065e: 4603 mov r3, r0 + 8000660: 2b00 cmp r3, #0 + 8000662: d001 beq.n 8000668 + { + Error_Handler(); + 8000664: f000 f8da bl 800081c + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 8000668: bf00 nop + 800066a: bd80 pop {r7, pc} + 800066c: 20000028 .word 0x20000028 + 8000670: 40013000 .word 0x40013000 + +08000674 : + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 8000674: b580 push {r7, lr} + 8000676: b086 sub sp, #24 + 8000678: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800067a: f107 0308 add.w r3, r7, #8 + 800067e: 2200 movs r2, #0 + 8000680: 601a str r2, [r3, #0] + 8000682: 605a str r2, [r3, #4] + 8000684: 609a str r2, [r3, #8] + 8000686: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000688: 463b mov r3, r7 + 800068a: 2200 movs r2, #0 + 800068c: 601a str r2, [r3, #0] + 800068e: 605a str r2, [r3, #4] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8000690: 4b1e ldr r3, [pc, #120] @ (800070c ) + 8000692: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 + 8000696: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 1000-1; + 8000698: 4b1c ldr r3, [pc, #112] @ (800070c ) + 800069a: f240 32e7 movw r2, #999 @ 0x3e7 + 800069e: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 80006a0: 4b1a ldr r3, [pc, #104] @ (800070c ) + 80006a2: 2200 movs r2, #0 + 80006a4: 609a str r2, [r3, #8] + htim2.Init.Period = 16000-1; + 80006a6: 4b19 ldr r3, [pc, #100] @ (800070c ) + 80006a8: f643 627f movw r2, #15999 @ 0x3e7f + 80006ac: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80006ae: 4b17 ldr r3, [pc, #92] @ (800070c ) + 80006b0: 2200 movs r2, #0 + 80006b2: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 80006b4: 4b15 ldr r3, [pc, #84] @ (800070c ) + 80006b6: 2280 movs r2, #128 @ 0x80 + 80006b8: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + 80006ba: 4814 ldr r0, [pc, #80] @ (800070c ) + 80006bc: f001 fdb2 bl 8002224 + 80006c0: 4603 mov r3, r0 + 80006c2: 2b00 cmp r3, #0 + 80006c4: d001 beq.n 80006ca + { + Error_Handler(); + 80006c6: f000 f8a9 bl 800081c + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 80006ca: f44f 5380 mov.w r3, #4096 @ 0x1000 + 80006ce: 60bb str r3, [r7, #8] + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + 80006d0: f107 0308 add.w r3, r7, #8 + 80006d4: 4619 mov r1, r3 + 80006d6: 480d ldr r0, [pc, #52] @ (800070c ) + 80006d8: f001 ff02 bl 80024e0 + 80006dc: 4603 mov r3, r0 + 80006de: 2b00 cmp r3, #0 + 80006e0: d001 beq.n 80006e6 + { + Error_Handler(); + 80006e2: f000 f89b bl 800081c + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80006e6: 2300 movs r3, #0 + 80006e8: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80006ea: 2300 movs r3, #0 + 80006ec: 607b str r3, [r7, #4] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 80006ee: 463b mov r3, r7 + 80006f0: 4619 mov r1, r3 + 80006f2: 4806 ldr r0, [pc, #24] @ (800070c ) + 80006f4: f002 f8ec bl 80028d0 + 80006f8: 4603 mov r3, r0 + 80006fa: 2b00 cmp r3, #0 + 80006fc: d001 beq.n 8000702 + { + Error_Handler(); + 80006fe: f000 f88d bl 800081c + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 8000702: bf00 nop + 8000704: 3718 adds r7, #24 + 8000706: 46bd mov sp, r7 + 8000708: bd80 pop {r7, pc} + 800070a: bf00 nop + 800070c: 20000080 .word 0x20000080 + +08000710 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000710: b580 push {r7, lr} + 8000712: b088 sub sp, #32 + 8000714: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000716: f107 030c add.w r3, r7, #12 + 800071a: 2200 movs r2, #0 + 800071c: 601a str r2, [r3, #0] + 800071e: 605a str r2, [r3, #4] + 8000720: 609a str r2, [r3, #8] + 8000722: 60da str r2, [r3, #12] + 8000724: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000726: 4b22 ldr r3, [pc, #136] @ (80007b0 ) + 8000728: 69db ldr r3, [r3, #28] + 800072a: 4a21 ldr r2, [pc, #132] @ (80007b0 ) + 800072c: f043 0304 orr.w r3, r3, #4 + 8000730: 61d3 str r3, [r2, #28] + 8000732: 4b1f ldr r3, [pc, #124] @ (80007b0 ) + 8000734: 69db ldr r3, [r3, #28] + 8000736: f003 0304 and.w r3, r3, #4 + 800073a: 60bb str r3, [r7, #8] + 800073c: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800073e: 4b1c ldr r3, [pc, #112] @ (80007b0 ) + 8000740: 69db ldr r3, [r3, #28] + 8000742: 4a1b ldr r2, [pc, #108] @ (80007b0 ) + 8000744: f043 0301 orr.w r3, r3, #1 + 8000748: 61d3 str r3, [r2, #28] + 800074a: 4b19 ldr r3, [pc, #100] @ (80007b0 ) + 800074c: 69db ldr r3, [r3, #28] + 800074e: f003 0301 and.w r3, r3, #1 + 8000752: 607b str r3, [r7, #4] + 8000754: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 8000756: 2200 movs r2, #0 + 8000758: 2101 movs r1, #1 + 800075a: 4816 ldr r0, [pc, #88] @ (80007b4 ) + 800075c: f000 fd06 bl 800116c + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 8000760: 2301 movs r3, #1 + 8000762: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000764: 2301 movs r3, #1 + 8000766: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000768: 2300 movs r3, #0 + 800076a: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800076c: 2300 movs r3, #0 + 800076e: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8000770: f107 030c add.w r3, r7, #12 + 8000774: 4619 mov r1, r3 + 8000776: 480f ldr r0, [pc, #60] @ (80007b4 ) + 8000778: f000 fb68 bl 8000e4c + + /*Configure GPIO pins : PA11 PA12 */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 800077c: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 8000780: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 8000782: f44f 1388 mov.w r3, #1114112 @ 0x110000 + 8000786: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000788: 2300 movs r3, #0 + 800078a: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800078c: f107 030c add.w r3, r7, #12 + 8000790: 4619 mov r1, r3 + 8000792: 4809 ldr r0, [pc, #36] @ (80007b8 ) + 8000794: f000 fb5a bl 8000e4c + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 8000798: 2200 movs r2, #0 + 800079a: 2100 movs r1, #0 + 800079c: 2028 movs r0, #40 @ 0x28 + 800079e: f000 fb1e bl 8000dde + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 80007a2: 2028 movs r0, #40 @ 0x28 + 80007a4: f000 fb37 bl 8000e16 + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 80007a8: bf00 nop + 80007aa: 3720 adds r7, #32 + 80007ac: 46bd mov sp, r7 + 80007ae: bd80 pop {r7, pc} + 80007b0: 40023800 .word 0x40023800 + 80007b4: 40020800 .word 0x40020800 + 80007b8: 40020000 .word 0x40020000 + +080007bc : + +/* USER CODE BEGIN 4 */ +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { + 80007bc: b480 push {r7} + 80007be: b083 sub sp, #12 + 80007c0: af00 add r7, sp, #0 + 80007c2: 4603 mov r3, r0 + 80007c4: 80fb strh r3, [r7, #6] + if (GPIO_Pin == (1<<11)){ + 80007c6: 88fb ldrh r3, [r7, #6] + 80007c8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 80007cc: d103 bne.n 80007d6 + marche = 1; + 80007ce: 4b08 ldr r3, [pc, #32] @ (80007f0 ) + 80007d0: 2201 movs r2, #1 + 80007d2: 701a strb r2, [r3, #0] + } else if (GPIO_Pin == (1<<12)) { + marche = 0; + } +} + 80007d4: e006 b.n 80007e4 + } else if (GPIO_Pin == (1<<12)) { + 80007d6: 88fb ldrh r3, [r7, #6] + 80007d8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80007dc: d102 bne.n 80007e4 + marche = 0; + 80007de: 4b04 ldr r3, [pc, #16] @ (80007f0 ) + 80007e0: 2200 movs r2, #0 + 80007e2: 701a strb r2, [r3, #0] +} + 80007e4: bf00 nop + 80007e6: 370c adds r7, #12 + 80007e8: 46bd mov sp, r7 + 80007ea: bc80 pop {r7} + 80007ec: 4770 bx lr + 80007ee: bf00 nop + 80007f0: 200000c0 .word 0x200000c0 + +080007f4 : + +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef* htim) { + 80007f4: b480 push {r7} + 80007f6: b083 sub sp, #12 + 80007f8: af00 add r7, sp, #0 + 80007fa: 6078 str r0, [r7, #4] + if (htim->Instance == TIM2) { + 80007fc: 687b ldr r3, [r7, #4] + 80007fe: 681b ldr r3, [r3, #0] + 8000800: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8000804: d102 bne.n 800080c + tempo_500ms_ok = 1; + 8000806: 4b04 ldr r3, [pc, #16] @ (8000818 ) + 8000808: 2201 movs r2, #1 + 800080a: 701a strb r2, [r3, #0] + } +} + 800080c: bf00 nop + 800080e: 370c adds r7, #12 + 8000810: 46bd mov sp, r7 + 8000812: bc80 pop {r7} + 8000814: 4770 bx lr + 8000816: bf00 nop + 8000818: 200000c1 .word 0x200000c1 + +0800081c : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 800081c: b480 push {r7} + 800081e: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000820: b672 cpsid i +} + 8000822: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000824: bf00 nop + 8000826: e7fd b.n 8000824 + +08000828 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000828: b480 push {r7} + 800082a: b085 sub sp, #20 + 800082c: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 800082e: 4b14 ldr r3, [pc, #80] @ (8000880 ) + 8000830: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000832: 4a13 ldr r2, [pc, #76] @ (8000880 ) + 8000834: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 8000838: 6253 str r3, [r2, #36] @ 0x24 + 800083a: 4b11 ldr r3, [pc, #68] @ (8000880 ) + 800083c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800083e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8000842: 60fb str r3, [r7, #12] + 8000844: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000846: 4b0e ldr r3, [pc, #56] @ (8000880 ) + 8000848: 6a1b ldr r3, [r3, #32] + 800084a: 4a0d ldr r2, [pc, #52] @ (8000880 ) + 800084c: f043 0301 orr.w r3, r3, #1 + 8000850: 6213 str r3, [r2, #32] + 8000852: 4b0b ldr r3, [pc, #44] @ (8000880 ) + 8000854: 6a1b ldr r3, [r3, #32] + 8000856: f003 0301 and.w r3, r3, #1 + 800085a: 60bb str r3, [r7, #8] + 800085c: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800085e: 4b08 ldr r3, [pc, #32] @ (8000880 ) + 8000860: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000862: 4a07 ldr r2, [pc, #28] @ (8000880 ) + 8000864: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000868: 6253 str r3, [r2, #36] @ 0x24 + 800086a: 4b05 ldr r3, [pc, #20] @ (8000880 ) + 800086c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800086e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000872: 607b str r3, [r7, #4] + 8000874: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000876: bf00 nop + 8000878: 3714 adds r7, #20 + 800087a: 46bd mov sp, r7 + 800087c: bc80 pop {r7} + 800087e: 4770 bx lr + 8000880: 40023800 .word 0x40023800 + +08000884 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8000884: b580 push {r7, lr} + 8000886: b08a sub sp, #40 @ 0x28 + 8000888: af00 add r7, sp, #0 + 800088a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800088c: f107 0314 add.w r3, r7, #20 + 8000890: 2200 movs r2, #0 + 8000892: 601a str r2, [r3, #0] + 8000894: 605a str r2, [r3, #4] + 8000896: 609a str r2, [r3, #8] + 8000898: 60da str r2, [r3, #12] + 800089a: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 800089c: 687b ldr r3, [r7, #4] + 800089e: 681b ldr r3, [r3, #0] + 80008a0: 4a17 ldr r2, [pc, #92] @ (8000900 ) + 80008a2: 4293 cmp r3, r2 + 80008a4: d127 bne.n 80008f6 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 80008a6: 4b17 ldr r3, [pc, #92] @ (8000904 ) + 80008a8: 6a1b ldr r3, [r3, #32] + 80008aa: 4a16 ldr r2, [pc, #88] @ (8000904 ) + 80008ac: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 80008b0: 6213 str r3, [r2, #32] + 80008b2: 4b14 ldr r3, [pc, #80] @ (8000904 ) + 80008b4: 6a1b ldr r3, [r3, #32] + 80008b6: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80008ba: 613b str r3, [r7, #16] + 80008bc: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80008be: 4b11 ldr r3, [pc, #68] @ (8000904 ) + 80008c0: 69db ldr r3, [r3, #28] + 80008c2: 4a10 ldr r2, [pc, #64] @ (8000904 ) + 80008c4: f043 0301 orr.w r3, r3, #1 + 80008c8: 61d3 str r3, [r2, #28] + 80008ca: 4b0e ldr r3, [pc, #56] @ (8000904 ) + 80008cc: 69db ldr r3, [r3, #28] + 80008ce: f003 0301 and.w r3, r3, #1 + 80008d2: 60fb str r3, [r7, #12] + 80008d4: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 80008d6: 23e0 movs r3, #224 @ 0xe0 + 80008d8: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80008da: 2302 movs r3, #2 + 80008dc: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008de: 2300 movs r3, #0 + 80008e0: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80008e2: 2303 movs r3, #3 + 80008e4: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 80008e6: 2305 movs r3, #5 + 80008e8: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80008ea: f107 0314 add.w r3, r7, #20 + 80008ee: 4619 mov r1, r3 + 80008f0: 4805 ldr r0, [pc, #20] @ (8000908 ) + 80008f2: f000 faab bl 8000e4c + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 80008f6: bf00 nop + 80008f8: 3728 adds r7, #40 @ 0x28 + 80008fa: 46bd mov sp, r7 + 80008fc: bd80 pop {r7, pc} + 80008fe: bf00 nop + 8000900: 40013000 .word 0x40013000 + 8000904: 40023800 .word 0x40023800 + 8000908: 40020000 .word 0x40020000 + +0800090c : + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 800090c: b580 push {r7, lr} + 800090e: b084 sub sp, #16 + 8000910: af00 add r7, sp, #0 + 8000912: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM2) + 8000914: 687b ldr r3, [r7, #4] + 8000916: 681b ldr r3, [r3, #0] + 8000918: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 800091c: d113 bne.n 8000946 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 800091e: 4b0c ldr r3, [pc, #48] @ (8000950 ) + 8000920: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000922: 4a0b ldr r2, [pc, #44] @ (8000950 ) + 8000924: f043 0301 orr.w r3, r3, #1 + 8000928: 6253 str r3, [r2, #36] @ 0x24 + 800092a: 4b09 ldr r3, [pc, #36] @ (8000950 ) + 800092c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800092e: f003 0301 and.w r3, r3, #1 + 8000932: 60fb str r3, [r7, #12] + 8000934: 68fb ldr r3, [r7, #12] + /* TIM2 interrupt Init */ + HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); + 8000936: 2200 movs r2, #0 + 8000938: 2100 movs r1, #0 + 800093a: 201c movs r0, #28 + 800093c: f000 fa4f bl 8000dde + HAL_NVIC_EnableIRQ(TIM2_IRQn); + 8000940: 201c movs r0, #28 + 8000942: f000 fa68 bl 8000e16 + + /* USER CODE END TIM2_MspInit 1 */ + + } + +} + 8000946: bf00 nop + 8000948: 3710 adds r7, #16 + 800094a: 46bd mov sp, r7 + 800094c: bd80 pop {r7, pc} + 800094e: bf00 nop + 8000950: 40023800 .word 0x40023800 + +08000954 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000954: b480 push {r7} + 8000956: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000958: bf00 nop + 800095a: e7fd b.n 8000958 + +0800095c : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 800095c: b480 push {r7} + 800095e: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000960: bf00 nop + 8000962: e7fd b.n 8000960 + +08000964 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000964: b480 push {r7} + 8000966: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000968: bf00 nop + 800096a: e7fd b.n 8000968 + +0800096c : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 800096c: b480 push {r7} + 800096e: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000970: bf00 nop + 8000972: e7fd b.n 8000970 + +08000974 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000974: b480 push {r7} + 8000976: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000978: bf00 nop + 800097a: e7fd b.n 8000978 + +0800097c : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 800097c: b480 push {r7} + 800097e: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000980: bf00 nop + 8000982: 46bd mov sp, r7 + 8000984: bc80 pop {r7} + 8000986: 4770 bx lr + +08000988 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000988: b480 push {r7} + 800098a: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 800098c: bf00 nop + 800098e: 46bd mov sp, r7 + 8000990: bc80 pop {r7} + 8000992: 4770 bx lr + +08000994 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000994: b480 push {r7} + 8000996: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000998: bf00 nop + 800099a: 46bd mov sp, r7 + 800099c: bc80 pop {r7} + 800099e: 4770 bx lr + +080009a0 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 80009a0: b580 push {r7, lr} + 80009a2: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 80009a4: f000 f928 bl 8000bf8 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 80009a8: bf00 nop + 80009aa: bd80 pop {r7, pc} + +080009ac : + +/** + * @brief This function handles TIM2 global interrupt. + */ +void TIM2_IRQHandler(void) +{ + 80009ac: b580 push {r7, lr} + 80009ae: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM2_IRQn 0 */ + + /* USER CODE END TIM2_IRQn 0 */ + HAL_TIM_IRQHandler(&htim2); + 80009b0: 4802 ldr r0, [pc, #8] @ (80009bc ) + 80009b2: f001 fcc9 bl 8002348 + /* USER CODE BEGIN TIM2_IRQn 1 */ + + /* USER CODE END TIM2_IRQn 1 */ +} + 80009b6: bf00 nop + 80009b8: bd80 pop {r7, pc} + 80009ba: bf00 nop + 80009bc: 20000080 .word 0x20000080 + +080009c0 : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 80009c0: b580 push {r7, lr} + 80009c2: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + 80009c4: f44f 6000 mov.w r0, #2048 @ 0x800 + 80009c8: f000 fbe8 bl 800119c + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + 80009cc: f44f 5080 mov.w r0, #4096 @ 0x1000 + 80009d0: f000 fbe4 bl 800119c + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 80009d4: bf00 nop + 80009d6: bd80 pop {r7, pc} + +080009d8 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 80009d8: b480 push {r7} + 80009da: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 80009dc: bf00 nop + 80009de: 46bd mov sp, r7 + 80009e0: bc80 pop {r7} + 80009e2: 4770 bx lr + +080009e4 : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 80009e4: f7ff fff8 bl 80009d8 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 80009e8: 480b ldr r0, [pc, #44] @ (8000a18 ) + ldr r1, =_edata + 80009ea: 490c ldr r1, [pc, #48] @ (8000a1c ) + ldr r2, =_sidata + 80009ec: 4a0c ldr r2, [pc, #48] @ (8000a20 ) + movs r3, #0 + 80009ee: 2300 movs r3, #0 + b LoopCopyDataInit + 80009f0: e002 b.n 80009f8 + +080009f2 : + +CopyDataInit: + ldr r4, [r2, r3] + 80009f2: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 80009f4: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 80009f6: 3304 adds r3, #4 + +080009f8 : + +LoopCopyDataInit: + adds r4, r0, r3 + 80009f8: 18c4 adds r4, r0, r3 + cmp r4, r1 + 80009fa: 428c cmp r4, r1 + bcc CopyDataInit + 80009fc: d3f9 bcc.n 80009f2 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 80009fe: 4a09 ldr r2, [pc, #36] @ (8000a24 ) + ldr r4, =_ebss + 8000a00: 4c09 ldr r4, [pc, #36] @ (8000a28 ) + movs r3, #0 + 8000a02: 2300 movs r3, #0 + b LoopFillZerobss + 8000a04: e001 b.n 8000a0a + +08000a06 : + +FillZerobss: + str r3, [r2] + 8000a06: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000a08: 3204 adds r2, #4 + +08000a0a : + +LoopFillZerobss: + cmp r2, r4 + 8000a0a: 42a2 cmp r2, r4 + bcc FillZerobss + 8000a0c: d3fb bcc.n 8000a06 + +/* Call static constructors */ + bl __libc_init_array + 8000a0e: f001 ffc5 bl 800299c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8000a12: f7ff fd7d bl 8000510
+ bx lr + 8000a16: 4770 bx lr + ldr r0, =_sdata + 8000a18: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000a1c: 2000000c .word 0x2000000c + ldr r2, =_sidata + 8000a20: 08002a38 .word 0x08002a38 + ldr r2, =_sbss + 8000a24: 2000000c .word 0x2000000c + ldr r4, =_ebss + 8000a28: 200000c8 .word 0x200000c8 + +08000a2c : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000a2c: e7fe b.n 8000a2c + +08000a2e : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 8000a2e: b580 push {r7, lr} + 8000a30: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 8000a32: 2107 movs r1, #7 + 8000a34: 200b movs r0, #11 + 8000a36: f000 f85d bl 8000af4 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 8000a3a: 2100 movs r1, #0 + 8000a3c: 2009 movs r0, #9 + 8000a3e: f000 f859 bl 8000af4 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 8000a42: f000 f809 bl 8000a58 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 8000a46: f000 f80f bl 8000a68 + MAX7219_Clear(); // clear all digits + 8000a4a: f000 f827 bl 8000a9c + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 8000a4e: 200f movs r0, #15 + 8000a50: f000 f812 bl 8000a78 +} + 8000a54: bf00 nop + 8000a56: bd80 pop {r7, pc} + +08000a58 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000a58: b580 push {r7, lr} + 8000a5a: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000a5c: 2101 movs r1, #1 + 8000a5e: 200c movs r0, #12 + 8000a60: f000 f848 bl 8000af4 +} + 8000a64: bf00 nop + 8000a66: bd80 pop {r7, pc} + +08000a68 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 8000a68: b580 push {r7, lr} + 8000a6a: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 8000a6c: 2100 movs r1, #0 + 8000a6e: 200f movs r0, #15 + 8000a70: f000 f840 bl 8000af4 +} + 8000a74: bf00 nop + 8000a76: bd80 pop {r7, pc} + +08000a78 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 8000a78: b580 push {r7, lr} + 8000a7a: b082 sub sp, #8 + 8000a7c: af00 add r7, sp, #0 + 8000a7e: 4603 mov r3, r0 + 8000a80: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 8000a82: 79fb ldrb r3, [r7, #7] + 8000a84: f003 030f and.w r3, r3, #15 + 8000a88: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 8000a8a: 79fb ldrb r3, [r7, #7] + 8000a8c: 4619 mov r1, r3 + 8000a8e: 200a movs r0, #10 + 8000a90: f000 f830 bl 8000af4 +} + 8000a94: bf00 nop + 8000a96: 3708 adds r7, #8 + 8000a98: 46bd mov sp, r7 + 8000a9a: bd80 pop {r7, pc} + +08000a9c : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 8000a9c: b580 push {r7, lr} + 8000a9e: b082 sub sp, #8 + 8000aa0: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 8000aa2: 2300 movs r3, #0 + 8000aa4: 71fb strb r3, [r7, #7] + 8000aa6: e007 b.n 8000ab8 + MAX7219_Write(i, 0x00); // turn all segments off + 8000aa8: 79fb ldrb r3, [r7, #7] + 8000aaa: 2100 movs r1, #0 + 8000aac: 4618 mov r0, r3 + 8000aae: f000 f821 bl 8000af4 + for (i=0; i < 8; i++) + 8000ab2: 79fb ldrb r3, [r7, #7] + 8000ab4: 3301 adds r3, #1 + 8000ab6: 71fb strb r3, [r7, #7] + 8000ab8: 79fb ldrb r3, [r7, #7] + 8000aba: 2b07 cmp r3, #7 + 8000abc: d9f4 bls.n 8000aa8 +} + 8000abe: bf00 nop + 8000ac0: bf00 nop + 8000ac2: 3708 adds r7, #8 + 8000ac4: 46bd mov sp, r7 + 8000ac6: bd80 pop {r7, pc} + +08000ac8 : +* character = character to display (0-9, A-Z) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayChar(char digit, char character) +{ + 8000ac8: b580 push {r7, lr} + 8000aca: b082 sub sp, #8 + 8000acc: af00 add r7, sp, #0 + 8000ace: 4603 mov r3, r0 + 8000ad0: 460a mov r2, r1 + 8000ad2: 71fb strb r3, [r7, #7] + 8000ad4: 4613 mov r3, r2 + 8000ad6: 71bb strb r3, [r7, #6] + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]); + 8000ad8: 79bb ldrb r3, [r7, #6] + 8000ada: 4a05 ldr r2, [pc, #20] @ (8000af0 ) + 8000adc: 5cd2 ldrb r2, [r2, r3] + 8000ade: 79fb ldrb r3, [r7, #7] + 8000ae0: 4611 mov r1, r2 + 8000ae2: 4618 mov r0, r3 + 8000ae4: f000 f806 bl 8000af4 +} + 8000ae8: bf00 nop + 8000aea: 3708 adds r7, #8 + 8000aec: 46bd mov sp, r7 + 8000aee: bd80 pop {r7, pc} + 8000af0: 08002a18 .word 0x08002a18 + +08000af4 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8000af4: b580 push {r7, lr} + 8000af6: b082 sub sp, #8 + 8000af8: af00 add r7, sp, #0 + 8000afa: 4603 mov r3, r0 + 8000afc: 460a mov r2, r1 + 8000afe: 71fb strb r3, [r7, #7] + 8000b00: 4613 mov r3, r2 + 8000b02: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8000b04: 4b09 ldr r3, [pc, #36] @ (8000b2c ) + 8000b06: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000b0a: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8000b0c: 79fb ldrb r3, [r7, #7] + 8000b0e: 4618 mov r0, r3 + 8000b10: f000 f80e bl 8000b30 + MAX7219_SendByte(dataout); // write data to MAX7219 + 8000b14: 79bb ldrb r3, [r7, #6] + 8000b16: 4618 mov r0, r3 + 8000b18: f000 f80a bl 8000b30 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 8000b1c: 4b03 ldr r3, [pc, #12] @ (8000b2c ) + 8000b1e: 2201 movs r2, #1 + 8000b20: 619a str r2, [r3, #24] + } + 8000b22: bf00 nop + 8000b24: 3708 adds r7, #8 + 8000b26: 46bd mov sp, r7 + 8000b28: bd80 pop {r7, pc} + 8000b2a: bf00 nop + 8000b2c: 40020800 .word 0x40020800 + +08000b30 : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000b30: b580 push {r7, lr} + 8000b32: b082 sub sp, #8 + 8000b34: af00 add r7, sp, #0 + 8000b36: 4603 mov r3, r0 + 8000b38: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 8000b3a: 1df9 adds r1, r7, #7 + 8000b3c: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000b40: 2201 movs r2, #1 + 8000b42: 4803 ldr r0, [pc, #12] @ (8000b50 ) + 8000b44: f001 f94d bl 8001de2 + +} + 8000b48: bf00 nop + 8000b4a: 3708 adds r7, #8 + 8000b4c: 46bd mov sp, r7 + 8000b4e: bd80 pop {r7, pc} + 8000b50: 20000028 .word 0x20000028 + +08000b54 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000b54: b580 push {r7, lr} + 8000b56: b082 sub sp, #8 + 8000b58: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000b5a: 2300 movs r3, #0 + 8000b5c: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000b5e: 2003 movs r0, #3 + 8000b60: f000 f932 bl 8000dc8 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000b64: 200f movs r0, #15 + 8000b66: f000 f80d bl 8000b84 + 8000b6a: 4603 mov r3, r0 + 8000b6c: 2b00 cmp r3, #0 + 8000b6e: d002 beq.n 8000b76 + { + status = HAL_ERROR; + 8000b70: 2301 movs r3, #1 + 8000b72: 71fb strb r3, [r7, #7] + 8000b74: e001 b.n 8000b7a + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000b76: f7ff fe57 bl 8000828 + } + + /* Return function status */ + return status; + 8000b7a: 79fb ldrb r3, [r7, #7] +} + 8000b7c: 4618 mov r0, r3 + 8000b7e: 3708 adds r7, #8 + 8000b80: 46bd mov sp, r7 + 8000b82: bd80 pop {r7, pc} + +08000b84 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000b84: b580 push {r7, lr} + 8000b86: b084 sub sp, #16 + 8000b88: af00 add r7, sp, #0 + 8000b8a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000b8c: 2300 movs r3, #0 + 8000b8e: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 8000b90: 4b16 ldr r3, [pc, #88] @ (8000bec ) + 8000b92: 681b ldr r3, [r3, #0] + 8000b94: 2b00 cmp r3, #0 + 8000b96: d022 beq.n 8000bde + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 8000b98: 4b15 ldr r3, [pc, #84] @ (8000bf0 ) + 8000b9a: 681a ldr r2, [r3, #0] + 8000b9c: 4b13 ldr r3, [pc, #76] @ (8000bec ) + 8000b9e: 681b ldr r3, [r3, #0] + 8000ba0: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8000ba4: fbb1 f3f3 udiv r3, r1, r3 + 8000ba8: fbb2 f3f3 udiv r3, r2, r3 + 8000bac: 4618 mov r0, r3 + 8000bae: f000 f940 bl 8000e32 + 8000bb2: 4603 mov r3, r0 + 8000bb4: 2b00 cmp r3, #0 + 8000bb6: d10f bne.n 8000bd8 + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000bb8: 687b ldr r3, [r7, #4] + 8000bba: 2b0f cmp r3, #15 + 8000bbc: d809 bhi.n 8000bd2 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000bbe: 2200 movs r2, #0 + 8000bc0: 6879 ldr r1, [r7, #4] + 8000bc2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000bc6: f000 f90a bl 8000dde + uwTickPrio = TickPriority; + 8000bca: 4a0a ldr r2, [pc, #40] @ (8000bf4 ) + 8000bcc: 687b ldr r3, [r7, #4] + 8000bce: 6013 str r3, [r2, #0] + 8000bd0: e007 b.n 8000be2 + } + else + { + status = HAL_ERROR; + 8000bd2: 2301 movs r3, #1 + 8000bd4: 73fb strb r3, [r7, #15] + 8000bd6: e004 b.n 8000be2 + } + } + else + { + status = HAL_ERROR; + 8000bd8: 2301 movs r3, #1 + 8000bda: 73fb strb r3, [r7, #15] + 8000bdc: e001 b.n 8000be2 + } + } + else + { + status = HAL_ERROR; + 8000bde: 2301 movs r3, #1 + 8000be0: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8000be2: 7bfb ldrb r3, [r7, #15] +} + 8000be4: 4618 mov r0, r3 + 8000be6: 3710 adds r7, #16 + 8000be8: 46bd mov sp, r7 + 8000bea: bd80 pop {r7, pc} + 8000bec: 20000008 .word 0x20000008 + 8000bf0: 20000000 .word 0x20000000 + 8000bf4: 20000004 .word 0x20000004 + +08000bf8 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000bf8: b480 push {r7} + 8000bfa: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000bfc: 4b05 ldr r3, [pc, #20] @ (8000c14 ) + 8000bfe: 681a ldr r2, [r3, #0] + 8000c00: 4b05 ldr r3, [pc, #20] @ (8000c18 ) + 8000c02: 681b ldr r3, [r3, #0] + 8000c04: 4413 add r3, r2 + 8000c06: 4a03 ldr r2, [pc, #12] @ (8000c14 ) + 8000c08: 6013 str r3, [r2, #0] +} + 8000c0a: bf00 nop + 8000c0c: 46bd mov sp, r7 + 8000c0e: bc80 pop {r7} + 8000c10: 4770 bx lr + 8000c12: bf00 nop + 8000c14: 200000c4 .word 0x200000c4 + 8000c18: 20000008 .word 0x20000008 + +08000c1c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000c1c: b480 push {r7} + 8000c1e: af00 add r7, sp, #0 + return uwTick; + 8000c20: 4b02 ldr r3, [pc, #8] @ (8000c2c ) + 8000c22: 681b ldr r3, [r3, #0] +} + 8000c24: 4618 mov r0, r3 + 8000c26: 46bd mov sp, r7 + 8000c28: bc80 pop {r7} + 8000c2a: 4770 bx lr + 8000c2c: 200000c4 .word 0x200000c4 + +08000c30 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000c30: b480 push {r7} + 8000c32: b085 sub sp, #20 + 8000c34: af00 add r7, sp, #0 + 8000c36: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000c38: 687b ldr r3, [r7, #4] + 8000c3a: f003 0307 and.w r3, r3, #7 + 8000c3e: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000c40: 4b0c ldr r3, [pc, #48] @ (8000c74 <__NVIC_SetPriorityGrouping+0x44>) + 8000c42: 68db ldr r3, [r3, #12] + 8000c44: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000c46: 68ba ldr r2, [r7, #8] + 8000c48: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000c4c: 4013 ands r3, r2 + 8000c4e: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000c50: 68fb ldr r3, [r7, #12] + 8000c52: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000c54: 68bb ldr r3, [r7, #8] + 8000c56: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000c58: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000c5c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000c60: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000c62: 4a04 ldr r2, [pc, #16] @ (8000c74 <__NVIC_SetPriorityGrouping+0x44>) + 8000c64: 68bb ldr r3, [r7, #8] + 8000c66: 60d3 str r3, [r2, #12] +} + 8000c68: bf00 nop + 8000c6a: 3714 adds r7, #20 + 8000c6c: 46bd mov sp, r7 + 8000c6e: bc80 pop {r7} + 8000c70: 4770 bx lr + 8000c72: bf00 nop + 8000c74: e000ed00 .word 0xe000ed00 + +08000c78 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000c78: b480 push {r7} + 8000c7a: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000c7c: 4b04 ldr r3, [pc, #16] @ (8000c90 <__NVIC_GetPriorityGrouping+0x18>) + 8000c7e: 68db ldr r3, [r3, #12] + 8000c80: 0a1b lsrs r3, r3, #8 + 8000c82: f003 0307 and.w r3, r3, #7 +} + 8000c86: 4618 mov r0, r3 + 8000c88: 46bd mov sp, r7 + 8000c8a: bc80 pop {r7} + 8000c8c: 4770 bx lr + 8000c8e: bf00 nop + 8000c90: e000ed00 .word 0xe000ed00 + +08000c94 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000c94: b480 push {r7} + 8000c96: b083 sub sp, #12 + 8000c98: af00 add r7, sp, #0 + 8000c9a: 4603 mov r3, r0 + 8000c9c: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000c9e: f997 3007 ldrsb.w r3, [r7, #7] + 8000ca2: 2b00 cmp r3, #0 + 8000ca4: db0b blt.n 8000cbe <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8000ca6: 79fb ldrb r3, [r7, #7] + 8000ca8: f003 021f and.w r2, r3, #31 + 8000cac: 4906 ldr r1, [pc, #24] @ (8000cc8 <__NVIC_EnableIRQ+0x34>) + 8000cae: f997 3007 ldrsb.w r3, [r7, #7] + 8000cb2: 095b lsrs r3, r3, #5 + 8000cb4: 2001 movs r0, #1 + 8000cb6: fa00 f202 lsl.w r2, r0, r2 + 8000cba: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8000cbe: bf00 nop + 8000cc0: 370c adds r7, #12 + 8000cc2: 46bd mov sp, r7 + 8000cc4: bc80 pop {r7} + 8000cc6: 4770 bx lr + 8000cc8: e000e100 .word 0xe000e100 + +08000ccc <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000ccc: b480 push {r7} + 8000cce: b083 sub sp, #12 + 8000cd0: af00 add r7, sp, #0 + 8000cd2: 4603 mov r3, r0 + 8000cd4: 6039 str r1, [r7, #0] + 8000cd6: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000cd8: f997 3007 ldrsb.w r3, [r7, #7] + 8000cdc: 2b00 cmp r3, #0 + 8000cde: db0a blt.n 8000cf6 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000ce0: 683b ldr r3, [r7, #0] + 8000ce2: b2da uxtb r2, r3 + 8000ce4: 490c ldr r1, [pc, #48] @ (8000d18 <__NVIC_SetPriority+0x4c>) + 8000ce6: f997 3007 ldrsb.w r3, [r7, #7] + 8000cea: 0112 lsls r2, r2, #4 + 8000cec: b2d2 uxtb r2, r2 + 8000cee: 440b add r3, r1 + 8000cf0: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000cf4: e00a b.n 8000d0c <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000cf6: 683b ldr r3, [r7, #0] + 8000cf8: b2da uxtb r2, r3 + 8000cfa: 4908 ldr r1, [pc, #32] @ (8000d1c <__NVIC_SetPriority+0x50>) + 8000cfc: 79fb ldrb r3, [r7, #7] + 8000cfe: f003 030f and.w r3, r3, #15 + 8000d02: 3b04 subs r3, #4 + 8000d04: 0112 lsls r2, r2, #4 + 8000d06: b2d2 uxtb r2, r2 + 8000d08: 440b add r3, r1 + 8000d0a: 761a strb r2, [r3, #24] +} + 8000d0c: bf00 nop + 8000d0e: 370c adds r7, #12 + 8000d10: 46bd mov sp, r7 + 8000d12: bc80 pop {r7} + 8000d14: 4770 bx lr + 8000d16: bf00 nop + 8000d18: e000e100 .word 0xe000e100 + 8000d1c: e000ed00 .word 0xe000ed00 + +08000d20 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000d20: b480 push {r7} + 8000d22: b089 sub sp, #36 @ 0x24 + 8000d24: af00 add r7, sp, #0 + 8000d26: 60f8 str r0, [r7, #12] + 8000d28: 60b9 str r1, [r7, #8] + 8000d2a: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000d2c: 68fb ldr r3, [r7, #12] + 8000d2e: f003 0307 and.w r3, r3, #7 + 8000d32: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000d34: 69fb ldr r3, [r7, #28] + 8000d36: f1c3 0307 rsb r3, r3, #7 + 8000d3a: 2b04 cmp r3, #4 + 8000d3c: bf28 it cs + 8000d3e: 2304 movcs r3, #4 + 8000d40: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000d42: 69fb ldr r3, [r7, #28] + 8000d44: 3304 adds r3, #4 + 8000d46: 2b06 cmp r3, #6 + 8000d48: d902 bls.n 8000d50 + 8000d4a: 69fb ldr r3, [r7, #28] + 8000d4c: 3b03 subs r3, #3 + 8000d4e: e000 b.n 8000d52 + 8000d50: 2300 movs r3, #0 + 8000d52: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000d54: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000d58: 69bb ldr r3, [r7, #24] + 8000d5a: fa02 f303 lsl.w r3, r2, r3 + 8000d5e: 43da mvns r2, r3 + 8000d60: 68bb ldr r3, [r7, #8] + 8000d62: 401a ands r2, r3 + 8000d64: 697b ldr r3, [r7, #20] + 8000d66: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000d68: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000d6c: 697b ldr r3, [r7, #20] + 8000d6e: fa01 f303 lsl.w r3, r1, r3 + 8000d72: 43d9 mvns r1, r3 + 8000d74: 687b ldr r3, [r7, #4] + 8000d76: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000d78: 4313 orrs r3, r2 + ); +} + 8000d7a: 4618 mov r0, r3 + 8000d7c: 3724 adds r7, #36 @ 0x24 + 8000d7e: 46bd mov sp, r7 + 8000d80: bc80 pop {r7} + 8000d82: 4770 bx lr + +08000d84 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000d84: b580 push {r7, lr} + 8000d86: b082 sub sp, #8 + 8000d88: af00 add r7, sp, #0 + 8000d8a: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000d8c: 687b ldr r3, [r7, #4] + 8000d8e: 3b01 subs r3, #1 + 8000d90: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000d94: d301 bcc.n 8000d9a + { + return (1UL); /* Reload value impossible */ + 8000d96: 2301 movs r3, #1 + 8000d98: e00f b.n 8000dba + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000d9a: 4a0a ldr r2, [pc, #40] @ (8000dc4 ) + 8000d9c: 687b ldr r3, [r7, #4] + 8000d9e: 3b01 subs r3, #1 + 8000da0: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000da2: 210f movs r1, #15 + 8000da4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000da8: f7ff ff90 bl 8000ccc <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000dac: 4b05 ldr r3, [pc, #20] @ (8000dc4 ) + 8000dae: 2200 movs r2, #0 + 8000db0: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000db2: 4b04 ldr r3, [pc, #16] @ (8000dc4 ) + 8000db4: 2207 movs r2, #7 + 8000db6: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000db8: 2300 movs r3, #0 +} + 8000dba: 4618 mov r0, r3 + 8000dbc: 3708 adds r7, #8 + 8000dbe: 46bd mov sp, r7 + 8000dc0: bd80 pop {r7, pc} + 8000dc2: bf00 nop + 8000dc4: e000e010 .word 0xe000e010 + +08000dc8 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000dc8: b580 push {r7, lr} + 8000dca: b082 sub sp, #8 + 8000dcc: af00 add r7, sp, #0 + 8000dce: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8000dd0: 6878 ldr r0, [r7, #4] + 8000dd2: f7ff ff2d bl 8000c30 <__NVIC_SetPriorityGrouping> +} + 8000dd6: bf00 nop + 8000dd8: 3708 adds r7, #8 + 8000dda: 46bd mov sp, r7 + 8000ddc: bd80 pop {r7, pc} + +08000dde : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000dde: b580 push {r7, lr} + 8000de0: b086 sub sp, #24 + 8000de2: af00 add r7, sp, #0 + 8000de4: 4603 mov r3, r0 + 8000de6: 60b9 str r1, [r7, #8] + 8000de8: 607a str r2, [r7, #4] + 8000dea: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8000dec: 2300 movs r3, #0 + 8000dee: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8000df0: f7ff ff42 bl 8000c78 <__NVIC_GetPriorityGrouping> + 8000df4: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8000df6: 687a ldr r2, [r7, #4] + 8000df8: 68b9 ldr r1, [r7, #8] + 8000dfa: 6978 ldr r0, [r7, #20] + 8000dfc: f7ff ff90 bl 8000d20 + 8000e00: 4602 mov r2, r0 + 8000e02: f997 300f ldrsb.w r3, [r7, #15] + 8000e06: 4611 mov r1, r2 + 8000e08: 4618 mov r0, r3 + 8000e0a: f7ff ff5f bl 8000ccc <__NVIC_SetPriority> +} + 8000e0e: bf00 nop + 8000e10: 3718 adds r7, #24 + 8000e12: 46bd mov sp, r7 + 8000e14: bd80 pop {r7, pc} + +08000e16 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000e16: b580 push {r7, lr} + 8000e18: b082 sub sp, #8 + 8000e1a: af00 add r7, sp, #0 + 8000e1c: 4603 mov r3, r0 + 8000e1e: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8000e20: f997 3007 ldrsb.w r3, [r7, #7] + 8000e24: 4618 mov r0, r3 + 8000e26: f7ff ff35 bl 8000c94 <__NVIC_EnableIRQ> +} + 8000e2a: bf00 nop + 8000e2c: 3708 adds r7, #8 + 8000e2e: 46bd mov sp, r7 + 8000e30: bd80 pop {r7, pc} + +08000e32 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000e32: b580 push {r7, lr} + 8000e34: b082 sub sp, #8 + 8000e36: af00 add r7, sp, #0 + 8000e38: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000e3a: 6878 ldr r0, [r7, #4] + 8000e3c: f7ff ffa2 bl 8000d84 + 8000e40: 4603 mov r3, r0 +} + 8000e42: 4618 mov r0, r3 + 8000e44: 3708 adds r7, #8 + 8000e46: 46bd mov sp, r7 + 8000e48: bd80 pop {r7, pc} + ... + +08000e4c : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000e4c: b480 push {r7} + 8000e4e: b087 sub sp, #28 + 8000e50: af00 add r7, sp, #0 + 8000e52: 6078 str r0, [r7, #4] + 8000e54: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8000e56: 2300 movs r3, #0 + 8000e58: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8000e5a: 2300 movs r3, #0 + 8000e5c: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 8000e5e: 2300 movs r3, #0 + 8000e60: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8000e62: e160 b.n 8001126 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8000e64: 683b ldr r3, [r7, #0] + 8000e66: 681a ldr r2, [r3, #0] + 8000e68: 2101 movs r1, #1 + 8000e6a: 697b ldr r3, [r7, #20] + 8000e6c: fa01 f303 lsl.w r3, r1, r3 + 8000e70: 4013 ands r3, r2 + 8000e72: 60fb str r3, [r7, #12] + + if (iocurrent) + 8000e74: 68fb ldr r3, [r7, #12] + 8000e76: 2b00 cmp r3, #0 + 8000e78: f000 8152 beq.w 8001120 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000e7c: 683b ldr r3, [r7, #0] + 8000e7e: 685b ldr r3, [r3, #4] + 8000e80: f003 0303 and.w r3, r3, #3 + 8000e84: 2b01 cmp r3, #1 + 8000e86: d005 beq.n 8000e94 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8000e88: 683b ldr r3, [r7, #0] + 8000e8a: 685b ldr r3, [r3, #4] + 8000e8c: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000e90: 2b02 cmp r3, #2 + 8000e92: d130 bne.n 8000ef6 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8000e94: 687b ldr r3, [r7, #4] + 8000e96: 689b ldr r3, [r3, #8] + 8000e98: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8000e9a: 697b ldr r3, [r7, #20] + 8000e9c: 005b lsls r3, r3, #1 + 8000e9e: 2203 movs r2, #3 + 8000ea0: fa02 f303 lsl.w r3, r2, r3 + 8000ea4: 43db mvns r3, r3 + 8000ea6: 693a ldr r2, [r7, #16] + 8000ea8: 4013 ands r3, r2 + 8000eaa: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8000eac: 683b ldr r3, [r7, #0] + 8000eae: 68da ldr r2, [r3, #12] + 8000eb0: 697b ldr r3, [r7, #20] + 8000eb2: 005b lsls r3, r3, #1 + 8000eb4: fa02 f303 lsl.w r3, r2, r3 + 8000eb8: 693a ldr r2, [r7, #16] + 8000eba: 4313 orrs r3, r2 + 8000ebc: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8000ebe: 687b ldr r3, [r7, #4] + 8000ec0: 693a ldr r2, [r7, #16] + 8000ec2: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8000ec4: 687b ldr r3, [r7, #4] + 8000ec6: 685b ldr r3, [r3, #4] + 8000ec8: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 8000eca: 2201 movs r2, #1 + 8000ecc: 697b ldr r3, [r7, #20] + 8000ece: fa02 f303 lsl.w r3, r2, r3 + 8000ed2: 43db mvns r3, r3 + 8000ed4: 693a ldr r2, [r7, #16] + 8000ed6: 4013 ands r3, r2 + 8000ed8: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8000eda: 683b ldr r3, [r7, #0] + 8000edc: 685b ldr r3, [r3, #4] + 8000ede: 091b lsrs r3, r3, #4 + 8000ee0: f003 0201 and.w r2, r3, #1 + 8000ee4: 697b ldr r3, [r7, #20] + 8000ee6: fa02 f303 lsl.w r3, r2, r3 + 8000eea: 693a ldr r2, [r7, #16] + 8000eec: 4313 orrs r3, r2 + 8000eee: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8000ef0: 687b ldr r3, [r7, #4] + 8000ef2: 693a ldr r2, [r7, #16] + 8000ef4: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8000ef6: 683b ldr r3, [r7, #0] + 8000ef8: 685b ldr r3, [r3, #4] + 8000efa: f003 0303 and.w r3, r3, #3 + 8000efe: 2b03 cmp r3, #3 + 8000f00: d017 beq.n 8000f32 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8000f02: 687b ldr r3, [r7, #4] + 8000f04: 68db ldr r3, [r3, #12] + 8000f06: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 8000f08: 697b ldr r3, [r7, #20] + 8000f0a: 005b lsls r3, r3, #1 + 8000f0c: 2203 movs r2, #3 + 8000f0e: fa02 f303 lsl.w r3, r2, r3 + 8000f12: 43db mvns r3, r3 + 8000f14: 693a ldr r2, [r7, #16] + 8000f16: 4013 ands r3, r2 + 8000f18: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 8000f1a: 683b ldr r3, [r7, #0] + 8000f1c: 689a ldr r2, [r3, #8] + 8000f1e: 697b ldr r3, [r7, #20] + 8000f20: 005b lsls r3, r3, #1 + 8000f22: fa02 f303 lsl.w r3, r2, r3 + 8000f26: 693a ldr r2, [r7, #16] + 8000f28: 4313 orrs r3, r2 + 8000f2a: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8000f2c: 687b ldr r3, [r7, #4] + 8000f2e: 693a ldr r2, [r7, #16] + 8000f30: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8000f32: 683b ldr r3, [r7, #0] + 8000f34: 685b ldr r3, [r3, #4] + 8000f36: f003 0303 and.w r3, r3, #3 + 8000f3a: 2b02 cmp r3, #2 + 8000f3c: d123 bne.n 8000f86 + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 8000f3e: 697b ldr r3, [r7, #20] + 8000f40: 08da lsrs r2, r3, #3 + 8000f42: 687b ldr r3, [r7, #4] + 8000f44: 3208 adds r2, #8 + 8000f46: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8000f4a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 8000f4c: 697b ldr r3, [r7, #20] + 8000f4e: f003 0307 and.w r3, r3, #7 + 8000f52: 009b lsls r3, r3, #2 + 8000f54: 220f movs r2, #15 + 8000f56: fa02 f303 lsl.w r3, r2, r3 + 8000f5a: 43db mvns r3, r3 + 8000f5c: 693a ldr r2, [r7, #16] + 8000f5e: 4013 ands r3, r2 + 8000f60: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8000f62: 683b ldr r3, [r7, #0] + 8000f64: 691a ldr r2, [r3, #16] + 8000f66: 697b ldr r3, [r7, #20] + 8000f68: f003 0307 and.w r3, r3, #7 + 8000f6c: 009b lsls r3, r3, #2 + 8000f6e: fa02 f303 lsl.w r3, r2, r3 + 8000f72: 693a ldr r2, [r7, #16] + 8000f74: 4313 orrs r3, r2 + 8000f76: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 8000f78: 697b ldr r3, [r7, #20] + 8000f7a: 08da lsrs r2, r3, #3 + 8000f7c: 687b ldr r3, [r7, #4] + 8000f7e: 3208 adds r2, #8 + 8000f80: 6939 ldr r1, [r7, #16] + 8000f82: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8000f86: 687b ldr r3, [r7, #4] + 8000f88: 681b ldr r3, [r3, #0] + 8000f8a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8000f8c: 697b ldr r3, [r7, #20] + 8000f8e: 005b lsls r3, r3, #1 + 8000f90: 2203 movs r2, #3 + 8000f92: fa02 f303 lsl.w r3, r2, r3 + 8000f96: 43db mvns r3, r3 + 8000f98: 693a ldr r2, [r7, #16] + 8000f9a: 4013 ands r3, r2 + 8000f9c: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8000f9e: 683b ldr r3, [r7, #0] + 8000fa0: 685b ldr r3, [r3, #4] + 8000fa2: f003 0203 and.w r2, r3, #3 + 8000fa6: 697b ldr r3, [r7, #20] + 8000fa8: 005b lsls r3, r3, #1 + 8000faa: fa02 f303 lsl.w r3, r2, r3 + 8000fae: 693a ldr r2, [r7, #16] + 8000fb0: 4313 orrs r3, r2 + 8000fb2: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8000fb4: 687b ldr r3, [r7, #4] + 8000fb6: 693a ldr r2, [r7, #16] + 8000fb8: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8000fba: 683b ldr r3, [r7, #0] + 8000fbc: 685b ldr r3, [r3, #4] + 8000fbe: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8000fc2: 2b00 cmp r3, #0 + 8000fc4: f000 80ac beq.w 8001120 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000fc8: 4b5e ldr r3, [pc, #376] @ (8001144 ) + 8000fca: 6a1b ldr r3, [r3, #32] + 8000fcc: 4a5d ldr r2, [pc, #372] @ (8001144 ) + 8000fce: f043 0301 orr.w r3, r3, #1 + 8000fd2: 6213 str r3, [r2, #32] + 8000fd4: 4b5b ldr r3, [pc, #364] @ (8001144 ) + 8000fd6: 6a1b ldr r3, [r3, #32] + 8000fd8: f003 0301 and.w r3, r3, #1 + 8000fdc: 60bb str r3, [r7, #8] + 8000fde: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8000fe0: 4a59 ldr r2, [pc, #356] @ (8001148 ) + 8000fe2: 697b ldr r3, [r7, #20] + 8000fe4: 089b lsrs r3, r3, #2 + 8000fe6: 3302 adds r3, #2 + 8000fe8: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8000fec: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 8000fee: 697b ldr r3, [r7, #20] + 8000ff0: f003 0303 and.w r3, r3, #3 + 8000ff4: 009b lsls r3, r3, #2 + 8000ff6: 220f movs r2, #15 + 8000ff8: fa02 f303 lsl.w r3, r2, r3 + 8000ffc: 43db mvns r3, r3 + 8000ffe: 693a ldr r2, [r7, #16] + 8001000: 4013 ands r3, r2 + 8001002: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 8001004: 687b ldr r3, [r7, #4] + 8001006: 4a51 ldr r2, [pc, #324] @ (800114c ) + 8001008: 4293 cmp r3, r2 + 800100a: d025 beq.n 8001058 + 800100c: 687b ldr r3, [r7, #4] + 800100e: 4a50 ldr r2, [pc, #320] @ (8001150 ) + 8001010: 4293 cmp r3, r2 + 8001012: d01f beq.n 8001054 + 8001014: 687b ldr r3, [r7, #4] + 8001016: 4a4f ldr r2, [pc, #316] @ (8001154 ) + 8001018: 4293 cmp r3, r2 + 800101a: d019 beq.n 8001050 + 800101c: 687b ldr r3, [r7, #4] + 800101e: 4a4e ldr r2, [pc, #312] @ (8001158 ) + 8001020: 4293 cmp r3, r2 + 8001022: d013 beq.n 800104c + 8001024: 687b ldr r3, [r7, #4] + 8001026: 4a4d ldr r2, [pc, #308] @ (800115c ) + 8001028: 4293 cmp r3, r2 + 800102a: d00d beq.n 8001048 + 800102c: 687b ldr r3, [r7, #4] + 800102e: 4a4c ldr r2, [pc, #304] @ (8001160 ) + 8001030: 4293 cmp r3, r2 + 8001032: d007 beq.n 8001044 + 8001034: 687b ldr r3, [r7, #4] + 8001036: 4a4b ldr r2, [pc, #300] @ (8001164 ) + 8001038: 4293 cmp r3, r2 + 800103a: d101 bne.n 8001040 + 800103c: 2306 movs r3, #6 + 800103e: e00c b.n 800105a + 8001040: 2307 movs r3, #7 + 8001042: e00a b.n 800105a + 8001044: 2305 movs r3, #5 + 8001046: e008 b.n 800105a + 8001048: 2304 movs r3, #4 + 800104a: e006 b.n 800105a + 800104c: 2303 movs r3, #3 + 800104e: e004 b.n 800105a + 8001050: 2302 movs r3, #2 + 8001052: e002 b.n 800105a + 8001054: 2301 movs r3, #1 + 8001056: e000 b.n 800105a + 8001058: 2300 movs r3, #0 + 800105a: 697a ldr r2, [r7, #20] + 800105c: f002 0203 and.w r2, r2, #3 + 8001060: 0092 lsls r2, r2, #2 + 8001062: 4093 lsls r3, r2 + 8001064: 693a ldr r2, [r7, #16] + 8001066: 4313 orrs r3, r2 + 8001068: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 800106a: 4937 ldr r1, [pc, #220] @ (8001148 ) + 800106c: 697b ldr r3, [r7, #20] + 800106e: 089b lsrs r3, r3, #2 + 8001070: 3302 adds r3, #2 + 8001072: 693a ldr r2, [r7, #16] + 8001074: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8001078: 4b3b ldr r3, [pc, #236] @ (8001168 ) + 800107a: 689b ldr r3, [r3, #8] + 800107c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 800107e: 68fb ldr r3, [r7, #12] + 8001080: 43db mvns r3, r3 + 8001082: 693a ldr r2, [r7, #16] + 8001084: 4013 ands r3, r2 + 8001086: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8001088: 683b ldr r3, [r7, #0] + 800108a: 685b ldr r3, [r3, #4] + 800108c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001090: 2b00 cmp r3, #0 + 8001092: d003 beq.n 800109c + { + SET_BIT(temp, iocurrent); + 8001094: 693a ldr r2, [r7, #16] + 8001096: 68fb ldr r3, [r7, #12] + 8001098: 4313 orrs r3, r2 + 800109a: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 800109c: 4a32 ldr r2, [pc, #200] @ (8001168 ) + 800109e: 693b ldr r3, [r7, #16] + 80010a0: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 80010a2: 4b31 ldr r3, [pc, #196] @ (8001168 ) + 80010a4: 68db ldr r3, [r3, #12] + 80010a6: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 80010a8: 68fb ldr r3, [r7, #12] + 80010aa: 43db mvns r3, r3 + 80010ac: 693a ldr r2, [r7, #16] + 80010ae: 4013 ands r3, r2 + 80010b0: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 80010b2: 683b ldr r3, [r7, #0] + 80010b4: 685b ldr r3, [r3, #4] + 80010b6: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 80010ba: 2b00 cmp r3, #0 + 80010bc: d003 beq.n 80010c6 + { + SET_BIT(temp, iocurrent); + 80010be: 693a ldr r2, [r7, #16] + 80010c0: 68fb ldr r3, [r7, #12] + 80010c2: 4313 orrs r3, r2 + 80010c4: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 80010c6: 4a28 ldr r2, [pc, #160] @ (8001168 ) + 80010c8: 693b ldr r3, [r7, #16] + 80010ca: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 80010cc: 4b26 ldr r3, [pc, #152] @ (8001168 ) + 80010ce: 685b ldr r3, [r3, #4] + 80010d0: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 80010d2: 68fb ldr r3, [r7, #12] + 80010d4: 43db mvns r3, r3 + 80010d6: 693a ldr r2, [r7, #16] + 80010d8: 4013 ands r3, r2 + 80010da: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 80010dc: 683b ldr r3, [r7, #0] + 80010de: 685b ldr r3, [r3, #4] + 80010e0: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80010e4: 2b00 cmp r3, #0 + 80010e6: d003 beq.n 80010f0 + { + SET_BIT(temp, iocurrent); + 80010e8: 693a ldr r2, [r7, #16] + 80010ea: 68fb ldr r3, [r7, #12] + 80010ec: 4313 orrs r3, r2 + 80010ee: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 80010f0: 4a1d ldr r2, [pc, #116] @ (8001168 ) + 80010f2: 693b ldr r3, [r7, #16] + 80010f4: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 80010f6: 4b1c ldr r3, [pc, #112] @ (8001168 ) + 80010f8: 681b ldr r3, [r3, #0] + 80010fa: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 80010fc: 68fb ldr r3, [r7, #12] + 80010fe: 43db mvns r3, r3 + 8001100: 693a ldr r2, [r7, #16] + 8001102: 4013 ands r3, r2 + 8001104: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 8001106: 683b ldr r3, [r7, #0] + 8001108: 685b ldr r3, [r3, #4] + 800110a: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 800110e: 2b00 cmp r3, #0 + 8001110: d003 beq.n 800111a + { + SET_BIT(temp, iocurrent); + 8001112: 693a ldr r2, [r7, #16] + 8001114: 68fb ldr r3, [r7, #12] + 8001116: 4313 orrs r3, r2 + 8001118: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 800111a: 4a13 ldr r2, [pc, #76] @ (8001168 ) + 800111c: 693b ldr r3, [r7, #16] + 800111e: 6013 str r3, [r2, #0] + } + } + + position++; + 8001120: 697b ldr r3, [r7, #20] + 8001122: 3301 adds r3, #1 + 8001124: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 8001126: 683b ldr r3, [r7, #0] + 8001128: 681a ldr r2, [r3, #0] + 800112a: 697b ldr r3, [r7, #20] + 800112c: fa22 f303 lsr.w r3, r2, r3 + 8001130: 2b00 cmp r3, #0 + 8001132: f47f ae97 bne.w 8000e64 + } +} + 8001136: bf00 nop + 8001138: bf00 nop + 800113a: 371c adds r7, #28 + 800113c: 46bd mov sp, r7 + 800113e: bc80 pop {r7} + 8001140: 4770 bx lr + 8001142: bf00 nop + 8001144: 40023800 .word 0x40023800 + 8001148: 40010000 .word 0x40010000 + 800114c: 40020000 .word 0x40020000 + 8001150: 40020400 .word 0x40020400 + 8001154: 40020800 .word 0x40020800 + 8001158: 40020c00 .word 0x40020c00 + 800115c: 40021000 .word 0x40021000 + 8001160: 40021400 .word 0x40021400 + 8001164: 40021800 .word 0x40021800 + 8001168: 40010400 .word 0x40010400 + +0800116c : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 800116c: b480 push {r7} + 800116e: b083 sub sp, #12 + 8001170: af00 add r7, sp, #0 + 8001172: 6078 str r0, [r7, #4] + 8001174: 460b mov r3, r1 + 8001176: 807b strh r3, [r7, #2] + 8001178: 4613 mov r3, r2 + 800117a: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 800117c: 787b ldrb r3, [r7, #1] + 800117e: 2b00 cmp r3, #0 + 8001180: d003 beq.n 800118a + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8001182: 887a ldrh r2, [r7, #2] + 8001184: 687b ldr r3, [r7, #4] + 8001186: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 8001188: e003 b.n 8001192 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 800118a: 887b ldrh r3, [r7, #2] + 800118c: 041a lsls r2, r3, #16 + 800118e: 687b ldr r3, [r7, #4] + 8001190: 619a str r2, [r3, #24] +} + 8001192: bf00 nop + 8001194: 370c adds r7, #12 + 8001196: 46bd mov sp, r7 + 8001198: bc80 pop {r7} + 800119a: 4770 bx lr + +0800119c : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 800119c: b580 push {r7, lr} + 800119e: b082 sub sp, #8 + 80011a0: af00 add r7, sp, #0 + 80011a2: 4603 mov r3, r0 + 80011a4: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 80011a6: 4b08 ldr r3, [pc, #32] @ (80011c8 ) + 80011a8: 695a ldr r2, [r3, #20] + 80011aa: 88fb ldrh r3, [r7, #6] + 80011ac: 4013 ands r3, r2 + 80011ae: 2b00 cmp r3, #0 + 80011b0: d006 beq.n 80011c0 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 80011b2: 4a05 ldr r2, [pc, #20] @ (80011c8 ) + 80011b4: 88fb ldrh r3, [r7, #6] + 80011b6: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 80011b8: 88fb ldrh r3, [r7, #6] + 80011ba: 4618 mov r0, r3 + 80011bc: f7ff fafe bl 80007bc + } +} + 80011c0: bf00 nop + 80011c2: 3708 adds r7, #8 + 80011c4: 46bd mov sp, r7 + 80011c6: bd80 pop {r7, pc} + 80011c8: 40010400 .word 0x40010400 + +080011cc : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80011cc: b580 push {r7, lr} + 80011ce: b088 sub sp, #32 + 80011d0: af00 add r7, sp, #0 + 80011d2: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 80011d4: 687b ldr r3, [r7, #4] + 80011d6: 2b00 cmp r3, #0 + 80011d8: d101 bne.n 80011de + { + return HAL_ERROR; + 80011da: 2301 movs r3, #1 + 80011dc: e31d b.n 800181a + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80011de: 4b94 ldr r3, [pc, #592] @ (8001430 ) + 80011e0: 689b ldr r3, [r3, #8] + 80011e2: f003 030c and.w r3, r3, #12 + 80011e6: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80011e8: 4b91 ldr r3, [pc, #580] @ (8001430 ) + 80011ea: 689b ldr r3, [r3, #8] + 80011ec: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80011f0: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80011f2: 687b ldr r3, [r7, #4] + 80011f4: 681b ldr r3, [r3, #0] + 80011f6: f003 0301 and.w r3, r3, #1 + 80011fa: 2b00 cmp r3, #0 + 80011fc: d07b beq.n 80012f6 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 80011fe: 69bb ldr r3, [r7, #24] + 8001200: 2b08 cmp r3, #8 + 8001202: d006 beq.n 8001212 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8001204: 69bb ldr r3, [r7, #24] + 8001206: 2b0c cmp r3, #12 + 8001208: d10f bne.n 800122a + 800120a: 697b ldr r3, [r7, #20] + 800120c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001210: d10b bne.n 800122a + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001212: 4b87 ldr r3, [pc, #540] @ (8001430 ) + 8001214: 681b ldr r3, [r3, #0] + 8001216: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800121a: 2b00 cmp r3, #0 + 800121c: d06a beq.n 80012f4 + 800121e: 687b ldr r3, [r7, #4] + 8001220: 685b ldr r3, [r3, #4] + 8001222: 2b00 cmp r3, #0 + 8001224: d166 bne.n 80012f4 + { + return HAL_ERROR; + 8001226: 2301 movs r3, #1 + 8001228: e2f7 b.n 800181a + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800122a: 687b ldr r3, [r7, #4] + 800122c: 685b ldr r3, [r3, #4] + 800122e: 2b01 cmp r3, #1 + 8001230: d106 bne.n 8001240 + 8001232: 4b7f ldr r3, [pc, #508] @ (8001430 ) + 8001234: 681b ldr r3, [r3, #0] + 8001236: 4a7e ldr r2, [pc, #504] @ (8001430 ) + 8001238: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 800123c: 6013 str r3, [r2, #0] + 800123e: e02d b.n 800129c + 8001240: 687b ldr r3, [r7, #4] + 8001242: 685b ldr r3, [r3, #4] + 8001244: 2b00 cmp r3, #0 + 8001246: d10c bne.n 8001262 + 8001248: 4b79 ldr r3, [pc, #484] @ (8001430 ) + 800124a: 681b ldr r3, [r3, #0] + 800124c: 4a78 ldr r2, [pc, #480] @ (8001430 ) + 800124e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001252: 6013 str r3, [r2, #0] + 8001254: 4b76 ldr r3, [pc, #472] @ (8001430 ) + 8001256: 681b ldr r3, [r3, #0] + 8001258: 4a75 ldr r2, [pc, #468] @ (8001430 ) + 800125a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 800125e: 6013 str r3, [r2, #0] + 8001260: e01c b.n 800129c + 8001262: 687b ldr r3, [r7, #4] + 8001264: 685b ldr r3, [r3, #4] + 8001266: 2b05 cmp r3, #5 + 8001268: d10c bne.n 8001284 + 800126a: 4b71 ldr r3, [pc, #452] @ (8001430 ) + 800126c: 681b ldr r3, [r3, #0] + 800126e: 4a70 ldr r2, [pc, #448] @ (8001430 ) + 8001270: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001274: 6013 str r3, [r2, #0] + 8001276: 4b6e ldr r3, [pc, #440] @ (8001430 ) + 8001278: 681b ldr r3, [r3, #0] + 800127a: 4a6d ldr r2, [pc, #436] @ (8001430 ) + 800127c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001280: 6013 str r3, [r2, #0] + 8001282: e00b b.n 800129c + 8001284: 4b6a ldr r3, [pc, #424] @ (8001430 ) + 8001286: 681b ldr r3, [r3, #0] + 8001288: 4a69 ldr r2, [pc, #420] @ (8001430 ) + 800128a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800128e: 6013 str r3, [r2, #0] + 8001290: 4b67 ldr r3, [pc, #412] @ (8001430 ) + 8001292: 681b ldr r3, [r3, #0] + 8001294: 4a66 ldr r2, [pc, #408] @ (8001430 ) + 8001296: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 800129a: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 800129c: 687b ldr r3, [r7, #4] + 800129e: 685b ldr r3, [r3, #4] + 80012a0: 2b00 cmp r3, #0 + 80012a2: d013 beq.n 80012cc + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80012a4: f7ff fcba bl 8000c1c + 80012a8: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 80012aa: e008 b.n 80012be + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80012ac: f7ff fcb6 bl 8000c1c + 80012b0: 4602 mov r2, r0 + 80012b2: 693b ldr r3, [r7, #16] + 80012b4: 1ad3 subs r3, r2, r3 + 80012b6: 2b64 cmp r3, #100 @ 0x64 + 80012b8: d901 bls.n 80012be + { + return HAL_TIMEOUT; + 80012ba: 2303 movs r3, #3 + 80012bc: e2ad b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 80012be: 4b5c ldr r3, [pc, #368] @ (8001430 ) + 80012c0: 681b ldr r3, [r3, #0] + 80012c2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80012c6: 2b00 cmp r3, #0 + 80012c8: d0f0 beq.n 80012ac + 80012ca: e014 b.n 80012f6 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80012cc: f7ff fca6 bl 8000c1c + 80012d0: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80012d2: e008 b.n 80012e6 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80012d4: f7ff fca2 bl 8000c1c + 80012d8: 4602 mov r2, r0 + 80012da: 693b ldr r3, [r7, #16] + 80012dc: 1ad3 subs r3, r2, r3 + 80012de: 2b64 cmp r3, #100 @ 0x64 + 80012e0: d901 bls.n 80012e6 + { + return HAL_TIMEOUT; + 80012e2: 2303 movs r3, #3 + 80012e4: e299 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80012e6: 4b52 ldr r3, [pc, #328] @ (8001430 ) + 80012e8: 681b ldr r3, [r3, #0] + 80012ea: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80012ee: 2b00 cmp r3, #0 + 80012f0: d1f0 bne.n 80012d4 + 80012f2: e000 b.n 80012f6 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80012f4: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80012f6: 687b ldr r3, [r7, #4] + 80012f8: 681b ldr r3, [r3, #0] + 80012fa: f003 0302 and.w r3, r3, #2 + 80012fe: 2b00 cmp r3, #0 + 8001300: d05a beq.n 80013b8 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 8001302: 69bb ldr r3, [r7, #24] + 8001304: 2b04 cmp r3, #4 + 8001306: d005 beq.n 8001314 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8001308: 69bb ldr r3, [r7, #24] + 800130a: 2b0c cmp r3, #12 + 800130c: d119 bne.n 8001342 + 800130e: 697b ldr r3, [r7, #20] + 8001310: 2b00 cmp r3, #0 + 8001312: d116 bne.n 8001342 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001314: 4b46 ldr r3, [pc, #280] @ (8001430 ) + 8001316: 681b ldr r3, [r3, #0] + 8001318: f003 0302 and.w r3, r3, #2 + 800131c: 2b00 cmp r3, #0 + 800131e: d005 beq.n 800132c + 8001320: 687b ldr r3, [r7, #4] + 8001322: 68db ldr r3, [r3, #12] + 8001324: 2b01 cmp r3, #1 + 8001326: d001 beq.n 800132c + { + return HAL_ERROR; + 8001328: 2301 movs r3, #1 + 800132a: e276 b.n 800181a + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800132c: 4b40 ldr r3, [pc, #256] @ (8001430 ) + 800132e: 685b ldr r3, [r3, #4] + 8001330: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001334: 687b ldr r3, [r7, #4] + 8001336: 691b ldr r3, [r3, #16] + 8001338: 021b lsls r3, r3, #8 + 800133a: 493d ldr r1, [pc, #244] @ (8001430 ) + 800133c: 4313 orrs r3, r2 + 800133e: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001340: e03a b.n 80013b8 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8001342: 687b ldr r3, [r7, #4] + 8001344: 68db ldr r3, [r3, #12] + 8001346: 2b00 cmp r3, #0 + 8001348: d020 beq.n 800138c + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800134a: 4b3a ldr r3, [pc, #232] @ (8001434 ) + 800134c: 2201 movs r2, #1 + 800134e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001350: f7ff fc64 bl 8000c1c + 8001354: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001356: e008 b.n 800136a + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001358: f7ff fc60 bl 8000c1c + 800135c: 4602 mov r2, r0 + 800135e: 693b ldr r3, [r7, #16] + 8001360: 1ad3 subs r3, r2, r3 + 8001362: 2b02 cmp r3, #2 + 8001364: d901 bls.n 800136a + { + return HAL_TIMEOUT; + 8001366: 2303 movs r3, #3 + 8001368: e257 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800136a: 4b31 ldr r3, [pc, #196] @ (8001430 ) + 800136c: 681b ldr r3, [r3, #0] + 800136e: f003 0302 and.w r3, r3, #2 + 8001372: 2b00 cmp r3, #0 + 8001374: d0f0 beq.n 8001358 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001376: 4b2e ldr r3, [pc, #184] @ (8001430 ) + 8001378: 685b ldr r3, [r3, #4] + 800137a: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 800137e: 687b ldr r3, [r7, #4] + 8001380: 691b ldr r3, [r3, #16] + 8001382: 021b lsls r3, r3, #8 + 8001384: 492a ldr r1, [pc, #168] @ (8001430 ) + 8001386: 4313 orrs r3, r2 + 8001388: 604b str r3, [r1, #4] + 800138a: e015 b.n 80013b8 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 800138c: 4b29 ldr r3, [pc, #164] @ (8001434 ) + 800138e: 2200 movs r2, #0 + 8001390: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001392: f7ff fc43 bl 8000c1c + 8001396: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001398: e008 b.n 80013ac + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 800139a: f7ff fc3f bl 8000c1c + 800139e: 4602 mov r2, r0 + 80013a0: 693b ldr r3, [r7, #16] + 80013a2: 1ad3 subs r3, r2, r3 + 80013a4: 2b02 cmp r3, #2 + 80013a6: d901 bls.n 80013ac + { + return HAL_TIMEOUT; + 80013a8: 2303 movs r3, #3 + 80013aa: e236 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 80013ac: 4b20 ldr r3, [pc, #128] @ (8001430 ) + 80013ae: 681b ldr r3, [r3, #0] + 80013b0: f003 0302 and.w r3, r3, #2 + 80013b4: 2b00 cmp r3, #0 + 80013b6: d1f0 bne.n 800139a + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 80013b8: 687b ldr r3, [r7, #4] + 80013ba: 681b ldr r3, [r3, #0] + 80013bc: f003 0310 and.w r3, r3, #16 + 80013c0: 2b00 cmp r3, #0 + 80013c2: f000 80b8 beq.w 8001536 + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 80013c6: 69bb ldr r3, [r7, #24] + 80013c8: 2b00 cmp r3, #0 + 80013ca: d170 bne.n 80014ae + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 80013cc: 4b18 ldr r3, [pc, #96] @ (8001430 ) + 80013ce: 681b ldr r3, [r3, #0] + 80013d0: f403 7300 and.w r3, r3, #512 @ 0x200 + 80013d4: 2b00 cmp r3, #0 + 80013d6: d005 beq.n 80013e4 + 80013d8: 687b ldr r3, [r7, #4] + 80013da: 699b ldr r3, [r3, #24] + 80013dc: 2b00 cmp r3, #0 + 80013de: d101 bne.n 80013e4 + { + return HAL_ERROR; + 80013e0: 2301 movs r3, #1 + 80013e2: e21a b.n 800181a + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 80013e4: 687b ldr r3, [r7, #4] + 80013e6: 6a1a ldr r2, [r3, #32] + 80013e8: 4b11 ldr r3, [pc, #68] @ (8001430 ) + 80013ea: 685b ldr r3, [r3, #4] + 80013ec: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 80013f0: 429a cmp r2, r3 + 80013f2: d921 bls.n 8001438 + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80013f4: 687b ldr r3, [r7, #4] + 80013f6: 6a1b ldr r3, [r3, #32] + 80013f8: 4618 mov r0, r3 + 80013fa: f000 fc09 bl 8001c10 + 80013fe: 4603 mov r3, r0 + 8001400: 2b00 cmp r3, #0 + 8001402: d001 beq.n 8001408 + { + return HAL_ERROR; + 8001404: 2301 movs r3, #1 + 8001406: e208 b.n 800181a + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001408: 4b09 ldr r3, [pc, #36] @ (8001430 ) + 800140a: 685b ldr r3, [r3, #4] + 800140c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001410: 687b ldr r3, [r7, #4] + 8001412: 6a1b ldr r3, [r3, #32] + 8001414: 4906 ldr r1, [pc, #24] @ (8001430 ) + 8001416: 4313 orrs r3, r2 + 8001418: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800141a: 4b05 ldr r3, [pc, #20] @ (8001430 ) + 800141c: 685b ldr r3, [r3, #4] + 800141e: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001422: 687b ldr r3, [r7, #4] + 8001424: 69db ldr r3, [r3, #28] + 8001426: 061b lsls r3, r3, #24 + 8001428: 4901 ldr r1, [pc, #4] @ (8001430 ) + 800142a: 4313 orrs r3, r2 + 800142c: 604b str r3, [r1, #4] + 800142e: e020 b.n 8001472 + 8001430: 40023800 .word 0x40023800 + 8001434: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001438: 4b99 ldr r3, [pc, #612] @ (80016a0 ) + 800143a: 685b ldr r3, [r3, #4] + 800143c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001440: 687b ldr r3, [r7, #4] + 8001442: 6a1b ldr r3, [r3, #32] + 8001444: 4996 ldr r1, [pc, #600] @ (80016a0 ) + 8001446: 4313 orrs r3, r2 + 8001448: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800144a: 4b95 ldr r3, [pc, #596] @ (80016a0 ) + 800144c: 685b ldr r3, [r3, #4] + 800144e: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001452: 687b ldr r3, [r7, #4] + 8001454: 69db ldr r3, [r3, #28] + 8001456: 061b lsls r3, r3, #24 + 8001458: 4991 ldr r1, [pc, #580] @ (80016a0 ) + 800145a: 4313 orrs r3, r2 + 800145c: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 800145e: 687b ldr r3, [r7, #4] + 8001460: 6a1b ldr r3, [r3, #32] + 8001462: 4618 mov r0, r3 + 8001464: f000 fbd4 bl 8001c10 + 8001468: 4603 mov r3, r0 + 800146a: 2b00 cmp r3, #0 + 800146c: d001 beq.n 8001472 + { + return HAL_ERROR; + 800146e: 2301 movs r3, #1 + 8001470: e1d3 b.n 800181a + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001472: 687b ldr r3, [r7, #4] + 8001474: 6a1b ldr r3, [r3, #32] + 8001476: 0b5b lsrs r3, r3, #13 + 8001478: 3301 adds r3, #1 + 800147a: f44f 4200 mov.w r2, #32768 @ 0x8000 + 800147e: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 8001482: 4a87 ldr r2, [pc, #540] @ (80016a0 ) + 8001484: 6892 ldr r2, [r2, #8] + 8001486: 0912 lsrs r2, r2, #4 + 8001488: f002 020f and.w r2, r2, #15 + 800148c: 4985 ldr r1, [pc, #532] @ (80016a4 ) + 800148e: 5c8a ldrb r2, [r1, r2] + 8001490: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001492: 4a85 ldr r2, [pc, #532] @ (80016a8 ) + 8001494: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001496: 4b85 ldr r3, [pc, #532] @ (80016ac ) + 8001498: 681b ldr r3, [r3, #0] + 800149a: 4618 mov r0, r3 + 800149c: f7ff fb72 bl 8000b84 + 80014a0: 4603 mov r3, r0 + 80014a2: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 80014a4: 7bfb ldrb r3, [r7, #15] + 80014a6: 2b00 cmp r3, #0 + 80014a8: d045 beq.n 8001536 + { + return status; + 80014aa: 7bfb ldrb r3, [r7, #15] + 80014ac: e1b5 b.n 800181a + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 80014ae: 687b ldr r3, [r7, #4] + 80014b0: 699b ldr r3, [r3, #24] + 80014b2: 2b00 cmp r3, #0 + 80014b4: d029 beq.n 800150a + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 80014b6: 4b7e ldr r3, [pc, #504] @ (80016b0 ) + 80014b8: 2201 movs r2, #1 + 80014ba: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80014bc: f7ff fbae bl 8000c1c + 80014c0: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80014c2: e008 b.n 80014d6 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80014c4: f7ff fbaa bl 8000c1c + 80014c8: 4602 mov r2, r0 + 80014ca: 693b ldr r3, [r7, #16] + 80014cc: 1ad3 subs r3, r2, r3 + 80014ce: 2b02 cmp r3, #2 + 80014d0: d901 bls.n 80014d6 + { + return HAL_TIMEOUT; + 80014d2: 2303 movs r3, #3 + 80014d4: e1a1 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80014d6: 4b72 ldr r3, [pc, #456] @ (80016a0 ) + 80014d8: 681b ldr r3, [r3, #0] + 80014da: f403 7300 and.w r3, r3, #512 @ 0x200 + 80014de: 2b00 cmp r3, #0 + 80014e0: d0f0 beq.n 80014c4 + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80014e2: 4b6f ldr r3, [pc, #444] @ (80016a0 ) + 80014e4: 685b ldr r3, [r3, #4] + 80014e6: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80014ea: 687b ldr r3, [r7, #4] + 80014ec: 6a1b ldr r3, [r3, #32] + 80014ee: 496c ldr r1, [pc, #432] @ (80016a0 ) + 80014f0: 4313 orrs r3, r2 + 80014f2: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80014f4: 4b6a ldr r3, [pc, #424] @ (80016a0 ) + 80014f6: 685b ldr r3, [r3, #4] + 80014f8: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80014fc: 687b ldr r3, [r7, #4] + 80014fe: 69db ldr r3, [r3, #28] + 8001500: 061b lsls r3, r3, #24 + 8001502: 4967 ldr r1, [pc, #412] @ (80016a0 ) + 8001504: 4313 orrs r3, r2 + 8001506: 604b str r3, [r1, #4] + 8001508: e015 b.n 8001536 + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 800150a: 4b69 ldr r3, [pc, #420] @ (80016b0 ) + 800150c: 2200 movs r2, #0 + 800150e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001510: f7ff fb84 bl 8000c1c + 8001514: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 8001516: e008 b.n 800152a + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001518: f7ff fb80 bl 8000c1c + 800151c: 4602 mov r2, r0 + 800151e: 693b ldr r3, [r7, #16] + 8001520: 1ad3 subs r3, r2, r3 + 8001522: 2b02 cmp r3, #2 + 8001524: d901 bls.n 800152a + { + return HAL_TIMEOUT; + 8001526: 2303 movs r3, #3 + 8001528: e177 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 800152a: 4b5d ldr r3, [pc, #372] @ (80016a0 ) + 800152c: 681b ldr r3, [r3, #0] + 800152e: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001532: 2b00 cmp r3, #0 + 8001534: d1f0 bne.n 8001518 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8001536: 687b ldr r3, [r7, #4] + 8001538: 681b ldr r3, [r3, #0] + 800153a: f003 0308 and.w r3, r3, #8 + 800153e: 2b00 cmp r3, #0 + 8001540: d030 beq.n 80015a4 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8001542: 687b ldr r3, [r7, #4] + 8001544: 695b ldr r3, [r3, #20] + 8001546: 2b00 cmp r3, #0 + 8001548: d016 beq.n 8001578 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800154a: 4b5a ldr r3, [pc, #360] @ (80016b4 ) + 800154c: 2201 movs r2, #1 + 800154e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001550: f7ff fb64 bl 8000c1c + 8001554: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8001556: e008 b.n 800156a + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001558: f7ff fb60 bl 8000c1c + 800155c: 4602 mov r2, r0 + 800155e: 693b ldr r3, [r7, #16] + 8001560: 1ad3 subs r3, r2, r3 + 8001562: 2b02 cmp r3, #2 + 8001564: d901 bls.n 800156a + { + return HAL_TIMEOUT; + 8001566: 2303 movs r3, #3 + 8001568: e157 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800156a: 4b4d ldr r3, [pc, #308] @ (80016a0 ) + 800156c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800156e: f003 0302 and.w r3, r3, #2 + 8001572: 2b00 cmp r3, #0 + 8001574: d0f0 beq.n 8001558 + 8001576: e015 b.n 80015a4 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001578: 4b4e ldr r3, [pc, #312] @ (80016b4 ) + 800157a: 2200 movs r2, #0 + 800157c: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800157e: f7ff fb4d bl 8000c1c + 8001582: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001584: e008 b.n 8001598 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001586: f7ff fb49 bl 8000c1c + 800158a: 4602 mov r2, r0 + 800158c: 693b ldr r3, [r7, #16] + 800158e: 1ad3 subs r3, r2, r3 + 8001590: 2b02 cmp r3, #2 + 8001592: d901 bls.n 8001598 + { + return HAL_TIMEOUT; + 8001594: 2303 movs r3, #3 + 8001596: e140 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001598: 4b41 ldr r3, [pc, #260] @ (80016a0 ) + 800159a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800159c: f003 0302 and.w r3, r3, #2 + 80015a0: 2b00 cmp r3, #0 + 80015a2: d1f0 bne.n 8001586 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 80015a4: 687b ldr r3, [r7, #4] + 80015a6: 681b ldr r3, [r3, #0] + 80015a8: f003 0304 and.w r3, r3, #4 + 80015ac: 2b00 cmp r3, #0 + 80015ae: f000 80b5 beq.w 800171c + { + FlagStatus pwrclkchanged = RESET; + 80015b2: 2300 movs r3, #0 + 80015b4: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 80015b6: 4b3a ldr r3, [pc, #232] @ (80016a0 ) + 80015b8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80015ba: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80015be: 2b00 cmp r3, #0 + 80015c0: d10d bne.n 80015de + { + __HAL_RCC_PWR_CLK_ENABLE(); + 80015c2: 4b37 ldr r3, [pc, #220] @ (80016a0 ) + 80015c4: 6a5b ldr r3, [r3, #36] @ 0x24 + 80015c6: 4a36 ldr r2, [pc, #216] @ (80016a0 ) + 80015c8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80015cc: 6253 str r3, [r2, #36] @ 0x24 + 80015ce: 4b34 ldr r3, [pc, #208] @ (80016a0 ) + 80015d0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80015d2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80015d6: 60bb str r3, [r7, #8] + 80015d8: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 80015da: 2301 movs r3, #1 + 80015dc: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80015de: 4b36 ldr r3, [pc, #216] @ (80016b8 ) + 80015e0: 681b ldr r3, [r3, #0] + 80015e2: f403 7380 and.w r3, r3, #256 @ 0x100 + 80015e6: 2b00 cmp r3, #0 + 80015e8: d118 bne.n 800161c + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80015ea: 4b33 ldr r3, [pc, #204] @ (80016b8 ) + 80015ec: 681b ldr r3, [r3, #0] + 80015ee: 4a32 ldr r2, [pc, #200] @ (80016b8 ) + 80015f0: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80015f4: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80015f6: f7ff fb11 bl 8000c1c + 80015fa: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80015fc: e008 b.n 8001610 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80015fe: f7ff fb0d bl 8000c1c + 8001602: 4602 mov r2, r0 + 8001604: 693b ldr r3, [r7, #16] + 8001606: 1ad3 subs r3, r2, r3 + 8001608: 2b64 cmp r3, #100 @ 0x64 + 800160a: d901 bls.n 8001610 + { + return HAL_TIMEOUT; + 800160c: 2303 movs r3, #3 + 800160e: e104 b.n 800181a + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001610: 4b29 ldr r3, [pc, #164] @ (80016b8 ) + 8001612: 681b ldr r3, [r3, #0] + 8001614: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001618: 2b00 cmp r3, #0 + 800161a: d0f0 beq.n 80015fe + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 800161c: 687b ldr r3, [r7, #4] + 800161e: 689b ldr r3, [r3, #8] + 8001620: 2b01 cmp r3, #1 + 8001622: d106 bne.n 8001632 + 8001624: 4b1e ldr r3, [pc, #120] @ (80016a0 ) + 8001626: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001628: 4a1d ldr r2, [pc, #116] @ (80016a0 ) + 800162a: f443 7380 orr.w r3, r3, #256 @ 0x100 + 800162e: 6353 str r3, [r2, #52] @ 0x34 + 8001630: e02d b.n 800168e + 8001632: 687b ldr r3, [r7, #4] + 8001634: 689b ldr r3, [r3, #8] + 8001636: 2b00 cmp r3, #0 + 8001638: d10c bne.n 8001654 + 800163a: 4b19 ldr r3, [pc, #100] @ (80016a0 ) + 800163c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800163e: 4a18 ldr r2, [pc, #96] @ (80016a0 ) + 8001640: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001644: 6353 str r3, [r2, #52] @ 0x34 + 8001646: 4b16 ldr r3, [pc, #88] @ (80016a0 ) + 8001648: 6b5b ldr r3, [r3, #52] @ 0x34 + 800164a: 4a15 ldr r2, [pc, #84] @ (80016a0 ) + 800164c: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001650: 6353 str r3, [r2, #52] @ 0x34 + 8001652: e01c b.n 800168e + 8001654: 687b ldr r3, [r7, #4] + 8001656: 689b ldr r3, [r3, #8] + 8001658: 2b05 cmp r3, #5 + 800165a: d10c bne.n 8001676 + 800165c: 4b10 ldr r3, [pc, #64] @ (80016a0 ) + 800165e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001660: 4a0f ldr r2, [pc, #60] @ (80016a0 ) + 8001662: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8001666: 6353 str r3, [r2, #52] @ 0x34 + 8001668: 4b0d ldr r3, [pc, #52] @ (80016a0 ) + 800166a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800166c: 4a0c ldr r2, [pc, #48] @ (80016a0 ) + 800166e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001672: 6353 str r3, [r2, #52] @ 0x34 + 8001674: e00b b.n 800168e + 8001676: 4b0a ldr r3, [pc, #40] @ (80016a0 ) + 8001678: 6b5b ldr r3, [r3, #52] @ 0x34 + 800167a: 4a09 ldr r2, [pc, #36] @ (80016a0 ) + 800167c: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001680: 6353 str r3, [r2, #52] @ 0x34 + 8001682: 4b07 ldr r3, [pc, #28] @ (80016a0 ) + 8001684: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001686: 4a06 ldr r2, [pc, #24] @ (80016a0 ) + 8001688: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 800168c: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 800168e: 687b ldr r3, [r7, #4] + 8001690: 689b ldr r3, [r3, #8] + 8001692: 2b00 cmp r3, #0 + 8001694: d024 beq.n 80016e0 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001696: f7ff fac1 bl 8000c1c + 800169a: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800169c: e019 b.n 80016d2 + 800169e: bf00 nop + 80016a0: 40023800 .word 0x40023800 + 80016a4: 08002a08 .word 0x08002a08 + 80016a8: 20000000 .word 0x20000000 + 80016ac: 20000004 .word 0x20000004 + 80016b0: 42470020 .word 0x42470020 + 80016b4: 42470680 .word 0x42470680 + 80016b8: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80016bc: f7ff faae bl 8000c1c + 80016c0: 4602 mov r2, r0 + 80016c2: 693b ldr r3, [r7, #16] + 80016c4: 1ad3 subs r3, r2, r3 + 80016c6: f241 3288 movw r2, #5000 @ 0x1388 + 80016ca: 4293 cmp r3, r2 + 80016cc: d901 bls.n 80016d2 + { + return HAL_TIMEOUT; + 80016ce: 2303 movs r3, #3 + 80016d0: e0a3 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 80016d2: 4b54 ldr r3, [pc, #336] @ (8001824 ) + 80016d4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80016d6: f403 7300 and.w r3, r3, #512 @ 0x200 + 80016da: 2b00 cmp r3, #0 + 80016dc: d0ee beq.n 80016bc + 80016de: e014 b.n 800170a + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80016e0: f7ff fa9c bl 8000c1c + 80016e4: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80016e6: e00a b.n 80016fe + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80016e8: f7ff fa98 bl 8000c1c + 80016ec: 4602 mov r2, r0 + 80016ee: 693b ldr r3, [r7, #16] + 80016f0: 1ad3 subs r3, r2, r3 + 80016f2: f241 3288 movw r2, #5000 @ 0x1388 + 80016f6: 4293 cmp r3, r2 + 80016f8: d901 bls.n 80016fe + { + return HAL_TIMEOUT; + 80016fa: 2303 movs r3, #3 + 80016fc: e08d b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80016fe: 4b49 ldr r3, [pc, #292] @ (8001824 ) + 8001700: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001702: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001706: 2b00 cmp r3, #0 + 8001708: d1ee bne.n 80016e8 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 800170a: 7ffb ldrb r3, [r7, #31] + 800170c: 2b01 cmp r3, #1 + 800170e: d105 bne.n 800171c + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8001710: 4b44 ldr r3, [pc, #272] @ (8001824 ) + 8001712: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001714: 4a43 ldr r2, [pc, #268] @ (8001824 ) + 8001716: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 800171a: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 800171c: 687b ldr r3, [r7, #4] + 800171e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001720: 2b00 cmp r3, #0 + 8001722: d079 beq.n 8001818 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001724: 69bb ldr r3, [r7, #24] + 8001726: 2b0c cmp r3, #12 + 8001728: d056 beq.n 80017d8 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 800172a: 687b ldr r3, [r7, #4] + 800172c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800172e: 2b02 cmp r3, #2 + 8001730: d13b bne.n 80017aa + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001732: 4b3d ldr r3, [pc, #244] @ (8001828 ) + 8001734: 2200 movs r2, #0 + 8001736: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001738: f7ff fa70 bl 8000c1c + 800173c: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800173e: e008 b.n 8001752 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001740: f7ff fa6c bl 8000c1c + 8001744: 4602 mov r2, r0 + 8001746: 693b ldr r3, [r7, #16] + 8001748: 1ad3 subs r3, r2, r3 + 800174a: 2b02 cmp r3, #2 + 800174c: d901 bls.n 8001752 + { + return HAL_TIMEOUT; + 800174e: 2303 movs r3, #3 + 8001750: e063 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001752: 4b34 ldr r3, [pc, #208] @ (8001824 ) + 8001754: 681b ldr r3, [r3, #0] + 8001756: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800175a: 2b00 cmp r3, #0 + 800175c: d1f0 bne.n 8001740 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 800175e: 4b31 ldr r3, [pc, #196] @ (8001824 ) + 8001760: 689b ldr r3, [r3, #8] + 8001762: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 8001766: 687b ldr r3, [r7, #4] + 8001768: 6a99 ldr r1, [r3, #40] @ 0x28 + 800176a: 687b ldr r3, [r7, #4] + 800176c: 6adb ldr r3, [r3, #44] @ 0x2c + 800176e: 4319 orrs r1, r3 + 8001770: 687b ldr r3, [r7, #4] + 8001772: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001774: 430b orrs r3, r1 + 8001776: 492b ldr r1, [pc, #172] @ (8001824 ) + 8001778: 4313 orrs r3, r2 + 800177a: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 800177c: 4b2a ldr r3, [pc, #168] @ (8001828 ) + 800177e: 2201 movs r2, #1 + 8001780: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001782: f7ff fa4b bl 8000c1c + 8001786: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001788: e008 b.n 800179c + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800178a: f7ff fa47 bl 8000c1c + 800178e: 4602 mov r2, r0 + 8001790: 693b ldr r3, [r7, #16] + 8001792: 1ad3 subs r3, r2, r3 + 8001794: 2b02 cmp r3, #2 + 8001796: d901 bls.n 800179c + { + return HAL_TIMEOUT; + 8001798: 2303 movs r3, #3 + 800179a: e03e b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 800179c: 4b21 ldr r3, [pc, #132] @ (8001824 ) + 800179e: 681b ldr r3, [r3, #0] + 80017a0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80017a4: 2b00 cmp r3, #0 + 80017a6: d0f0 beq.n 800178a + 80017a8: e036 b.n 8001818 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80017aa: 4b1f ldr r3, [pc, #124] @ (8001828 ) + 80017ac: 2200 movs r2, #0 + 80017ae: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80017b0: f7ff fa34 bl 8000c1c + 80017b4: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80017b6: e008 b.n 80017ca + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80017b8: f7ff fa30 bl 8000c1c + 80017bc: 4602 mov r2, r0 + 80017be: 693b ldr r3, [r7, #16] + 80017c0: 1ad3 subs r3, r2, r3 + 80017c2: 2b02 cmp r3, #2 + 80017c4: d901 bls.n 80017ca + { + return HAL_TIMEOUT; + 80017c6: 2303 movs r3, #3 + 80017c8: e027 b.n 800181a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80017ca: 4b16 ldr r3, [pc, #88] @ (8001824 ) + 80017cc: 681b ldr r3, [r3, #0] + 80017ce: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80017d2: 2b00 cmp r3, #0 + 80017d4: d1f0 bne.n 80017b8 + 80017d6: e01f b.n 8001818 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 80017d8: 687b ldr r3, [r7, #4] + 80017da: 6a5b ldr r3, [r3, #36] @ 0x24 + 80017dc: 2b01 cmp r3, #1 + 80017de: d101 bne.n 80017e4 + { + return HAL_ERROR; + 80017e0: 2301 movs r3, #1 + 80017e2: e01a b.n 800181a + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 80017e4: 4b0f ldr r3, [pc, #60] @ (8001824 ) + 80017e6: 689b ldr r3, [r3, #8] + 80017e8: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80017ea: 697b ldr r3, [r7, #20] + 80017ec: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 80017f0: 687b ldr r3, [r7, #4] + 80017f2: 6a9b ldr r3, [r3, #40] @ 0x28 + 80017f4: 429a cmp r2, r3 + 80017f6: d10d bne.n 8001814 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80017f8: 697b ldr r3, [r7, #20] + 80017fa: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 80017fe: 687b ldr r3, [r7, #4] + 8001800: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8001802: 429a cmp r2, r3 + 8001804: d106 bne.n 8001814 + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 8001806: 697b ldr r3, [r7, #20] + 8001808: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 800180c: 687b ldr r3, [r7, #4] + 800180e: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8001810: 429a cmp r2, r3 + 8001812: d001 beq.n 8001818 + { + return HAL_ERROR; + 8001814: 2301 movs r3, #1 + 8001816: e000 b.n 800181a + } + } + } + } + + return HAL_OK; + 8001818: 2300 movs r3, #0 +} + 800181a: 4618 mov r0, r3 + 800181c: 3720 adds r7, #32 + 800181e: 46bd mov sp, r7 + 8001820: bd80 pop {r7, pc} + 8001822: bf00 nop + 8001824: 40023800 .word 0x40023800 + 8001828: 42470060 .word 0x42470060 + +0800182c : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 800182c: b580 push {r7, lr} + 800182e: b084 sub sp, #16 + 8001830: af00 add r7, sp, #0 + 8001832: 6078 str r0, [r7, #4] + 8001834: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 8001836: 687b ldr r3, [r7, #4] + 8001838: 2b00 cmp r3, #0 + 800183a: d101 bne.n 8001840 + { + return HAL_ERROR; + 800183c: 2301 movs r3, #1 + 800183e: e11a b.n 8001a76 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8001840: 4b8f ldr r3, [pc, #572] @ (8001a80 ) + 8001842: 681b ldr r3, [r3, #0] + 8001844: f003 0301 and.w r3, r3, #1 + 8001848: 683a ldr r2, [r7, #0] + 800184a: 429a cmp r2, r3 + 800184c: d919 bls.n 8001882 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800184e: 683b ldr r3, [r7, #0] + 8001850: 2b01 cmp r3, #1 + 8001852: d105 bne.n 8001860 + 8001854: 4b8a ldr r3, [pc, #552] @ (8001a80 ) + 8001856: 681b ldr r3, [r3, #0] + 8001858: 4a89 ldr r2, [pc, #548] @ (8001a80 ) + 800185a: f043 0304 orr.w r3, r3, #4 + 800185e: 6013 str r3, [r2, #0] + 8001860: 4b87 ldr r3, [pc, #540] @ (8001a80 ) + 8001862: 681b ldr r3, [r3, #0] + 8001864: f023 0201 bic.w r2, r3, #1 + 8001868: 4985 ldr r1, [pc, #532] @ (8001a80 ) + 800186a: 683b ldr r3, [r7, #0] + 800186c: 4313 orrs r3, r2 + 800186e: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001870: 4b83 ldr r3, [pc, #524] @ (8001a80 ) + 8001872: 681b ldr r3, [r3, #0] + 8001874: f003 0301 and.w r3, r3, #1 + 8001878: 683a ldr r2, [r7, #0] + 800187a: 429a cmp r2, r3 + 800187c: d001 beq.n 8001882 + { + return HAL_ERROR; + 800187e: 2301 movs r3, #1 + 8001880: e0f9 b.n 8001a76 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8001882: 687b ldr r3, [r7, #4] + 8001884: 681b ldr r3, [r3, #0] + 8001886: f003 0302 and.w r3, r3, #2 + 800188a: 2b00 cmp r3, #0 + 800188c: d008 beq.n 80018a0 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 800188e: 4b7d ldr r3, [pc, #500] @ (8001a84 ) + 8001890: 689b ldr r3, [r3, #8] + 8001892: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8001896: 687b ldr r3, [r7, #4] + 8001898: 689b ldr r3, [r3, #8] + 800189a: 497a ldr r1, [pc, #488] @ (8001a84 ) + 800189c: 4313 orrs r3, r2 + 800189e: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 80018a0: 687b ldr r3, [r7, #4] + 80018a2: 681b ldr r3, [r3, #0] + 80018a4: f003 0301 and.w r3, r3, #1 + 80018a8: 2b00 cmp r3, #0 + 80018aa: f000 808e beq.w 80019ca + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80018ae: 687b ldr r3, [r7, #4] + 80018b0: 685b ldr r3, [r3, #4] + 80018b2: 2b02 cmp r3, #2 + 80018b4: d107 bne.n 80018c6 + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 80018b6: 4b73 ldr r3, [pc, #460] @ (8001a84 ) + 80018b8: 681b ldr r3, [r3, #0] + 80018ba: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80018be: 2b00 cmp r3, #0 + 80018c0: d121 bne.n 8001906 + { + return HAL_ERROR; + 80018c2: 2301 movs r3, #1 + 80018c4: e0d7 b.n 8001a76 + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80018c6: 687b ldr r3, [r7, #4] + 80018c8: 685b ldr r3, [r3, #4] + 80018ca: 2b03 cmp r3, #3 + 80018cc: d107 bne.n 80018de + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 80018ce: 4b6d ldr r3, [pc, #436] @ (8001a84 ) + 80018d0: 681b ldr r3, [r3, #0] + 80018d2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80018d6: 2b00 cmp r3, #0 + 80018d8: d115 bne.n 8001906 + { + return HAL_ERROR; + 80018da: 2301 movs r3, #1 + 80018dc: e0cb b.n 8001a76 + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 80018de: 687b ldr r3, [r7, #4] + 80018e0: 685b ldr r3, [r3, #4] + 80018e2: 2b01 cmp r3, #1 + 80018e4: d107 bne.n 80018f6 + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80018e6: 4b67 ldr r3, [pc, #412] @ (8001a84 ) + 80018e8: 681b ldr r3, [r3, #0] + 80018ea: f003 0302 and.w r3, r3, #2 + 80018ee: 2b00 cmp r3, #0 + 80018f0: d109 bne.n 8001906 + { + return HAL_ERROR; + 80018f2: 2301 movs r3, #1 + 80018f4: e0bf b.n 8001a76 + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 80018f6: 4b63 ldr r3, [pc, #396] @ (8001a84 ) + 80018f8: 681b ldr r3, [r3, #0] + 80018fa: f403 7300 and.w r3, r3, #512 @ 0x200 + 80018fe: 2b00 cmp r3, #0 + 8001900: d101 bne.n 8001906 + { + return HAL_ERROR; + 8001902: 2301 movs r3, #1 + 8001904: e0b7 b.n 8001a76 + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8001906: 4b5f ldr r3, [pc, #380] @ (8001a84 ) + 8001908: 689b ldr r3, [r3, #8] + 800190a: f023 0203 bic.w r2, r3, #3 + 800190e: 687b ldr r3, [r7, #4] + 8001910: 685b ldr r3, [r3, #4] + 8001912: 495c ldr r1, [pc, #368] @ (8001a84 ) + 8001914: 4313 orrs r3, r2 + 8001916: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001918: f7ff f980 bl 8000c1c + 800191c: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800191e: 687b ldr r3, [r7, #4] + 8001920: 685b ldr r3, [r3, #4] + 8001922: 2b02 cmp r3, #2 + 8001924: d112 bne.n 800194c + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001926: e00a b.n 800193e + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001928: f7ff f978 bl 8000c1c + 800192c: 4602 mov r2, r0 + 800192e: 68fb ldr r3, [r7, #12] + 8001930: 1ad3 subs r3, r2, r3 + 8001932: f241 3288 movw r2, #5000 @ 0x1388 + 8001936: 4293 cmp r3, r2 + 8001938: d901 bls.n 800193e + { + return HAL_TIMEOUT; + 800193a: 2303 movs r3, #3 + 800193c: e09b b.n 8001a76 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 800193e: 4b51 ldr r3, [pc, #324] @ (8001a84 ) + 8001940: 689b ldr r3, [r3, #8] + 8001942: f003 030c and.w r3, r3, #12 + 8001946: 2b08 cmp r3, #8 + 8001948: d1ee bne.n 8001928 + 800194a: e03e b.n 80019ca + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800194c: 687b ldr r3, [r7, #4] + 800194e: 685b ldr r3, [r3, #4] + 8001950: 2b03 cmp r3, #3 + 8001952: d112 bne.n 800197a + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001954: e00a b.n 800196c + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001956: f7ff f961 bl 8000c1c + 800195a: 4602 mov r2, r0 + 800195c: 68fb ldr r3, [r7, #12] + 800195e: 1ad3 subs r3, r2, r3 + 8001960: f241 3288 movw r2, #5000 @ 0x1388 + 8001964: 4293 cmp r3, r2 + 8001966: d901 bls.n 800196c + { + return HAL_TIMEOUT; + 8001968: 2303 movs r3, #3 + 800196a: e084 b.n 8001a76 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 800196c: 4b45 ldr r3, [pc, #276] @ (8001a84 ) + 800196e: 689b ldr r3, [r3, #8] + 8001970: f003 030c and.w r3, r3, #12 + 8001974: 2b0c cmp r3, #12 + 8001976: d1ee bne.n 8001956 + 8001978: e027 b.n 80019ca + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 800197a: 687b ldr r3, [r7, #4] + 800197c: 685b ldr r3, [r3, #4] + 800197e: 2b01 cmp r3, #1 + 8001980: d11d bne.n 80019be + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001982: e00a b.n 800199a + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001984: f7ff f94a bl 8000c1c + 8001988: 4602 mov r2, r0 + 800198a: 68fb ldr r3, [r7, #12] + 800198c: 1ad3 subs r3, r2, r3 + 800198e: f241 3288 movw r2, #5000 @ 0x1388 + 8001992: 4293 cmp r3, r2 + 8001994: d901 bls.n 800199a + { + return HAL_TIMEOUT; + 8001996: 2303 movs r3, #3 + 8001998: e06d b.n 8001a76 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 800199a: 4b3a ldr r3, [pc, #232] @ (8001a84 ) + 800199c: 689b ldr r3, [r3, #8] + 800199e: f003 030c and.w r3, r3, #12 + 80019a2: 2b04 cmp r3, #4 + 80019a4: d1ee bne.n 8001984 + 80019a6: e010 b.n 80019ca + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80019a8: f7ff f938 bl 8000c1c + 80019ac: 4602 mov r2, r0 + 80019ae: 68fb ldr r3, [r7, #12] + 80019b0: 1ad3 subs r3, r2, r3 + 80019b2: f241 3288 movw r2, #5000 @ 0x1388 + 80019b6: 4293 cmp r3, r2 + 80019b8: d901 bls.n 80019be + { + return HAL_TIMEOUT; + 80019ba: 2303 movs r3, #3 + 80019bc: e05b b.n 8001a76 + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 80019be: 4b31 ldr r3, [pc, #196] @ (8001a84 ) + 80019c0: 689b ldr r3, [r3, #8] + 80019c2: f003 030c and.w r3, r3, #12 + 80019c6: 2b00 cmp r3, #0 + 80019c8: d1ee bne.n 80019a8 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 80019ca: 4b2d ldr r3, [pc, #180] @ (8001a80 ) + 80019cc: 681b ldr r3, [r3, #0] + 80019ce: f003 0301 and.w r3, r3, #1 + 80019d2: 683a ldr r2, [r7, #0] + 80019d4: 429a cmp r2, r3 + 80019d6: d219 bcs.n 8001a0c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80019d8: 683b ldr r3, [r7, #0] + 80019da: 2b01 cmp r3, #1 + 80019dc: d105 bne.n 80019ea + 80019de: 4b28 ldr r3, [pc, #160] @ (8001a80 ) + 80019e0: 681b ldr r3, [r3, #0] + 80019e2: 4a27 ldr r2, [pc, #156] @ (8001a80 ) + 80019e4: f043 0304 orr.w r3, r3, #4 + 80019e8: 6013 str r3, [r2, #0] + 80019ea: 4b25 ldr r3, [pc, #148] @ (8001a80 ) + 80019ec: 681b ldr r3, [r3, #0] + 80019ee: f023 0201 bic.w r2, r3, #1 + 80019f2: 4923 ldr r1, [pc, #140] @ (8001a80 ) + 80019f4: 683b ldr r3, [r7, #0] + 80019f6: 4313 orrs r3, r2 + 80019f8: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 80019fa: 4b21 ldr r3, [pc, #132] @ (8001a80 ) + 80019fc: 681b ldr r3, [r3, #0] + 80019fe: f003 0301 and.w r3, r3, #1 + 8001a02: 683a ldr r2, [r7, #0] + 8001a04: 429a cmp r2, r3 + 8001a06: d001 beq.n 8001a0c + { + return HAL_ERROR; + 8001a08: 2301 movs r3, #1 + 8001a0a: e034 b.n 8001a76 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001a0c: 687b ldr r3, [r7, #4] + 8001a0e: 681b ldr r3, [r3, #0] + 8001a10: f003 0304 and.w r3, r3, #4 + 8001a14: 2b00 cmp r3, #0 + 8001a16: d008 beq.n 8001a2a + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8001a18: 4b1a ldr r3, [pc, #104] @ (8001a84 ) + 8001a1a: 689b ldr r3, [r3, #8] + 8001a1c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001a20: 687b ldr r3, [r7, #4] + 8001a22: 68db ldr r3, [r3, #12] + 8001a24: 4917 ldr r1, [pc, #92] @ (8001a84 ) + 8001a26: 4313 orrs r3, r2 + 8001a28: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001a2a: 687b ldr r3, [r7, #4] + 8001a2c: 681b ldr r3, [r3, #0] + 8001a2e: f003 0308 and.w r3, r3, #8 + 8001a32: 2b00 cmp r3, #0 + 8001a34: d009 beq.n 8001a4a + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8001a36: 4b13 ldr r3, [pc, #76] @ (8001a84 ) + 8001a38: 689b ldr r3, [r3, #8] + 8001a3a: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001a3e: 687b ldr r3, [r7, #4] + 8001a40: 691b ldr r3, [r3, #16] + 8001a42: 00db lsls r3, r3, #3 + 8001a44: 490f ldr r1, [pc, #60] @ (8001a84 ) + 8001a46: 4313 orrs r3, r2 + 8001a48: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8001a4a: f000 f823 bl 8001a94 + 8001a4e: 4602 mov r2, r0 + 8001a50: 4b0c ldr r3, [pc, #48] @ (8001a84 ) + 8001a52: 689b ldr r3, [r3, #8] + 8001a54: 091b lsrs r3, r3, #4 + 8001a56: f003 030f and.w r3, r3, #15 + 8001a5a: 490b ldr r1, [pc, #44] @ (8001a88 ) + 8001a5c: 5ccb ldrb r3, [r1, r3] + 8001a5e: fa22 f303 lsr.w r3, r2, r3 + 8001a62: 4a0a ldr r2, [pc, #40] @ (8001a8c ) + 8001a64: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001a66: 4b0a ldr r3, [pc, #40] @ (8001a90 ) + 8001a68: 681b ldr r3, [r3, #0] + 8001a6a: 4618 mov r0, r3 + 8001a6c: f7ff f88a bl 8000b84 + 8001a70: 4603 mov r3, r0 + 8001a72: 72fb strb r3, [r7, #11] + + return status; + 8001a74: 7afb ldrb r3, [r7, #11] +} + 8001a76: 4618 mov r0, r3 + 8001a78: 3710 adds r7, #16 + 8001a7a: 46bd mov sp, r7 + 8001a7c: bd80 pop {r7, pc} + 8001a7e: bf00 nop + 8001a80: 40023c00 .word 0x40023c00 + 8001a84: 40023800 .word 0x40023800 + 8001a88: 08002a08 .word 0x08002a08 + 8001a8c: 20000000 .word 0x20000000 + 8001a90: 20000004 .word 0x20000004 + +08001a94 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8001a94: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001a98: b08e sub sp, #56 @ 0x38 + 8001a9a: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 8001a9c: 4b58 ldr r3, [pc, #352] @ (8001c00 ) + 8001a9e: 689b ldr r3, [r3, #8] + 8001aa0: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8001aa2: 6afb ldr r3, [r7, #44] @ 0x2c + 8001aa4: f003 030c and.w r3, r3, #12 + 8001aa8: 2b0c cmp r3, #12 + 8001aaa: d00d beq.n 8001ac8 + 8001aac: 2b0c cmp r3, #12 + 8001aae: f200 8092 bhi.w 8001bd6 + 8001ab2: 2b04 cmp r3, #4 + 8001ab4: d002 beq.n 8001abc + 8001ab6: 2b08 cmp r3, #8 + 8001ab8: d003 beq.n 8001ac2 + 8001aba: e08c b.n 8001bd6 + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8001abc: 4b51 ldr r3, [pc, #324] @ (8001c04 ) + 8001abe: 633b str r3, [r7, #48] @ 0x30 + break; + 8001ac0: e097 b.n 8001bf2 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001ac2: 4b51 ldr r3, [pc, #324] @ (8001c08 ) + 8001ac4: 633b str r3, [r7, #48] @ 0x30 + break; + 8001ac6: e094 b.n 8001bf2 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8001ac8: 6afb ldr r3, [r7, #44] @ 0x2c + 8001aca: 0c9b lsrs r3, r3, #18 + 8001acc: f003 020f and.w r2, r3, #15 + 8001ad0: 4b4e ldr r3, [pc, #312] @ (8001c0c ) + 8001ad2: 5c9b ldrb r3, [r3, r2] + 8001ad4: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8001ad6: 6afb ldr r3, [r7, #44] @ 0x2c + 8001ad8: 0d9b lsrs r3, r3, #22 + 8001ada: f003 0303 and.w r3, r3, #3 + 8001ade: 3301 adds r3, #1 + 8001ae0: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8001ae2: 4b47 ldr r3, [pc, #284] @ (8001c00 ) + 8001ae4: 689b ldr r3, [r3, #8] + 8001ae6: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001aea: 2b00 cmp r3, #0 + 8001aec: d021 beq.n 8001b32 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001aee: 6abb ldr r3, [r7, #40] @ 0x28 + 8001af0: 2200 movs r2, #0 + 8001af2: 61bb str r3, [r7, #24] + 8001af4: 61fa str r2, [r7, #28] + 8001af6: 4b44 ldr r3, [pc, #272] @ (8001c08 ) + 8001af8: e9d7 8906 ldrd r8, r9, [r7, #24] + 8001afc: 464a mov r2, r9 + 8001afe: fb03 f202 mul.w r2, r3, r2 + 8001b02: 2300 movs r3, #0 + 8001b04: 4644 mov r4, r8 + 8001b06: fb04 f303 mul.w r3, r4, r3 + 8001b0a: 4413 add r3, r2 + 8001b0c: 4a3e ldr r2, [pc, #248] @ (8001c08 ) + 8001b0e: 4644 mov r4, r8 + 8001b10: fba4 0102 umull r0, r1, r4, r2 + 8001b14: 440b add r3, r1 + 8001b16: 4619 mov r1, r3 + 8001b18: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001b1a: 2200 movs r2, #0 + 8001b1c: 613b str r3, [r7, #16] + 8001b1e: 617a str r2, [r7, #20] + 8001b20: e9d7 2304 ldrd r2, r3, [r7, #16] + 8001b24: f7fe fb2a bl 800017c <__aeabi_uldivmod> + 8001b28: 4602 mov r2, r0 + 8001b2a: 460b mov r3, r1 + 8001b2c: 4613 mov r3, r2 + 8001b2e: 637b str r3, [r7, #52] @ 0x34 + 8001b30: e04e b.n 8001bd0 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001b32: 6abb ldr r3, [r7, #40] @ 0x28 + 8001b34: 2200 movs r2, #0 + 8001b36: 469a mov sl, r3 + 8001b38: 4693 mov fp, r2 + 8001b3a: 4652 mov r2, sl + 8001b3c: 465b mov r3, fp + 8001b3e: f04f 0000 mov.w r0, #0 + 8001b42: f04f 0100 mov.w r1, #0 + 8001b46: 0159 lsls r1, r3, #5 + 8001b48: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001b4c: 0150 lsls r0, r2, #5 + 8001b4e: 4602 mov r2, r0 + 8001b50: 460b mov r3, r1 + 8001b52: ebb2 080a subs.w r8, r2, sl + 8001b56: eb63 090b sbc.w r9, r3, fp + 8001b5a: f04f 0200 mov.w r2, #0 + 8001b5e: f04f 0300 mov.w r3, #0 + 8001b62: ea4f 1389 mov.w r3, r9, lsl #6 + 8001b66: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001b6a: ea4f 1288 mov.w r2, r8, lsl #6 + 8001b6e: ebb2 0408 subs.w r4, r2, r8 + 8001b72: eb63 0509 sbc.w r5, r3, r9 + 8001b76: f04f 0200 mov.w r2, #0 + 8001b7a: f04f 0300 mov.w r3, #0 + 8001b7e: 00eb lsls r3, r5, #3 + 8001b80: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8001b84: 00e2 lsls r2, r4, #3 + 8001b86: 4614 mov r4, r2 + 8001b88: 461d mov r5, r3 + 8001b8a: eb14 030a adds.w r3, r4, sl + 8001b8e: 603b str r3, [r7, #0] + 8001b90: eb45 030b adc.w r3, r5, fp + 8001b94: 607b str r3, [r7, #4] + 8001b96: f04f 0200 mov.w r2, #0 + 8001b9a: f04f 0300 mov.w r3, #0 + 8001b9e: e9d7 4500 ldrd r4, r5, [r7] + 8001ba2: 4629 mov r1, r5 + 8001ba4: 028b lsls r3, r1, #10 + 8001ba6: 4620 mov r0, r4 + 8001ba8: 4629 mov r1, r5 + 8001baa: 4604 mov r4, r0 + 8001bac: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8001bb0: 4601 mov r1, r0 + 8001bb2: 028a lsls r2, r1, #10 + 8001bb4: 4610 mov r0, r2 + 8001bb6: 4619 mov r1, r3 + 8001bb8: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001bba: 2200 movs r2, #0 + 8001bbc: 60bb str r3, [r7, #8] + 8001bbe: 60fa str r2, [r7, #12] + 8001bc0: e9d7 2302 ldrd r2, r3, [r7, #8] + 8001bc4: f7fe fada bl 800017c <__aeabi_uldivmod> + 8001bc8: 4602 mov r2, r0 + 8001bca: 460b mov r3, r1 + 8001bcc: 4613 mov r3, r2 + 8001bce: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 8001bd0: 6b7b ldr r3, [r7, #52] @ 0x34 + 8001bd2: 633b str r3, [r7, #48] @ 0x30 + break; + 8001bd4: e00d b.n 8001bf2 + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8001bd6: 4b0a ldr r3, [pc, #40] @ (8001c00 ) + 8001bd8: 685b ldr r3, [r3, #4] + 8001bda: 0b5b lsrs r3, r3, #13 + 8001bdc: f003 0307 and.w r3, r3, #7 + 8001be0: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8001be2: 6a3b ldr r3, [r7, #32] + 8001be4: 3301 adds r3, #1 + 8001be6: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001bea: fa02 f303 lsl.w r3, r2, r3 + 8001bee: 633b str r3, [r7, #48] @ 0x30 + break; + 8001bf0: bf00 nop + } + } + return sysclockfreq; + 8001bf2: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 8001bf4: 4618 mov r0, r3 + 8001bf6: 3738 adds r7, #56 @ 0x38 + 8001bf8: 46bd mov sp, r7 + 8001bfa: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8001bfe: bf00 nop + 8001c00: 40023800 .word 0x40023800 + 8001c04: 00f42400 .word 0x00f42400 + 8001c08: 016e3600 .word 0x016e3600 + 8001c0c: 080029fc .word 0x080029fc + +08001c10 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 8001c10: b480 push {r7} + 8001c12: b087 sub sp, #28 + 8001c14: af00 add r7, sp, #0 + 8001c16: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8001c18: 2300 movs r3, #0 + 8001c1a: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 8001c1c: 4b29 ldr r3, [pc, #164] @ (8001cc4 ) + 8001c1e: 689b ldr r3, [r3, #8] + 8001c20: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001c24: 2b00 cmp r3, #0 + 8001c26: d12c bne.n 8001c82 + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 8001c28: 4b26 ldr r3, [pc, #152] @ (8001cc4 ) + 8001c2a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001c2c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001c30: 2b00 cmp r3, #0 + 8001c32: d005 beq.n 8001c40 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001c34: 4b24 ldr r3, [pc, #144] @ (8001cc8 ) + 8001c36: 681b ldr r3, [r3, #0] + 8001c38: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001c3c: 617b str r3, [r7, #20] + 8001c3e: e016 b.n 8001c6e + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001c40: 4b20 ldr r3, [pc, #128] @ (8001cc4 ) + 8001c42: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001c44: 4a1f ldr r2, [pc, #124] @ (8001cc4 ) + 8001c46: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001c4a: 6253 str r3, [r2, #36] @ 0x24 + 8001c4c: 4b1d ldr r3, [pc, #116] @ (8001cc4 ) + 8001c4e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001c50: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001c54: 60fb str r3, [r7, #12] + 8001c56: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001c58: 4b1b ldr r3, [pc, #108] @ (8001cc8 ) + 8001c5a: 681b ldr r3, [r3, #0] + 8001c5c: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001c60: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001c62: 4b18 ldr r3, [pc, #96] @ (8001cc4 ) + 8001c64: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001c66: 4a17 ldr r2, [pc, #92] @ (8001cc4 ) + 8001c68: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001c6c: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001c6e: 697b ldr r3, [r7, #20] + 8001c70: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001c74: d105 bne.n 8001c82 + 8001c76: 687b ldr r3, [r7, #4] + 8001c78: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001c7c: d101 bne.n 8001c82 + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001c7e: 2301 movs r3, #1 + 8001c80: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001c82: 693b ldr r3, [r7, #16] + 8001c84: 2b01 cmp r3, #1 + 8001c86: d105 bne.n 8001c94 + 8001c88: 4b10 ldr r3, [pc, #64] @ (8001ccc ) + 8001c8a: 681b ldr r3, [r3, #0] + 8001c8c: 4a0f ldr r2, [pc, #60] @ (8001ccc ) + 8001c8e: f043 0304 orr.w r3, r3, #4 + 8001c92: 6013 str r3, [r2, #0] + 8001c94: 4b0d ldr r3, [pc, #52] @ (8001ccc ) + 8001c96: 681b ldr r3, [r3, #0] + 8001c98: f023 0201 bic.w r2, r3, #1 + 8001c9c: 490b ldr r1, [pc, #44] @ (8001ccc ) + 8001c9e: 693b ldr r3, [r7, #16] + 8001ca0: 4313 orrs r3, r2 + 8001ca2: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001ca4: 4b09 ldr r3, [pc, #36] @ (8001ccc ) + 8001ca6: 681b ldr r3, [r3, #0] + 8001ca8: f003 0301 and.w r3, r3, #1 + 8001cac: 693a ldr r2, [r7, #16] + 8001cae: 429a cmp r2, r3 + 8001cb0: d001 beq.n 8001cb6 + { + return HAL_ERROR; + 8001cb2: 2301 movs r3, #1 + 8001cb4: e000 b.n 8001cb8 + } + + return HAL_OK; + 8001cb6: 2300 movs r3, #0 +} + 8001cb8: 4618 mov r0, r3 + 8001cba: 371c adds r7, #28 + 8001cbc: 46bd mov sp, r7 + 8001cbe: bc80 pop {r7} + 8001cc0: 4770 bx lr + 8001cc2: bf00 nop + 8001cc4: 40023800 .word 0x40023800 + 8001cc8: 40007000 .word 0x40007000 + 8001ccc: 40023c00 .word 0x40023c00 + +08001cd0 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001cd0: b580 push {r7, lr} + 8001cd2: b082 sub sp, #8 + 8001cd4: af00 add r7, sp, #0 + 8001cd6: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001cd8: 687b ldr r3, [r7, #4] + 8001cda: 2b00 cmp r3, #0 + 8001cdc: d101 bne.n 8001ce2 + { + return HAL_ERROR; + 8001cde: 2301 movs r3, #1 + 8001ce0: e07b b.n 8001dda + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001ce2: 687b ldr r3, [r7, #4] + 8001ce4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ce6: 2b00 cmp r3, #0 + 8001ce8: d108 bne.n 8001cfc + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001cea: 687b ldr r3, [r7, #4] + 8001cec: 685b ldr r3, [r3, #4] + 8001cee: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001cf2: d009 beq.n 8001d08 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001cf4: 687b ldr r3, [r7, #4] + 8001cf6: 2200 movs r2, #0 + 8001cf8: 61da str r2, [r3, #28] + 8001cfa: e005 b.n 8001d08 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001cfc: 687b ldr r3, [r7, #4] + 8001cfe: 2200 movs r2, #0 + 8001d00: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001d02: 687b ldr r3, [r7, #4] + 8001d04: 2200 movs r2, #0 + 8001d06: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001d08: 687b ldr r3, [r7, #4] + 8001d0a: 2200 movs r2, #0 + 8001d0c: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001d0e: 687b ldr r3, [r7, #4] + 8001d10: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001d14: b2db uxtb r3, r3 + 8001d16: 2b00 cmp r3, #0 + 8001d18: d106 bne.n 8001d28 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001d1a: 687b ldr r3, [r7, #4] + 8001d1c: 2200 movs r2, #0 + 8001d1e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001d22: 6878 ldr r0, [r7, #4] + 8001d24: f7fe fdae bl 8000884 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001d28: 687b ldr r3, [r7, #4] + 8001d2a: 2202 movs r2, #2 + 8001d2c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001d30: 687b ldr r3, [r7, #4] + 8001d32: 681b ldr r3, [r3, #0] + 8001d34: 681a ldr r2, [r3, #0] + 8001d36: 687b ldr r3, [r7, #4] + 8001d38: 681b ldr r3, [r3, #0] + 8001d3a: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001d3e: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001d40: 687b ldr r3, [r7, #4] + 8001d42: 685b ldr r3, [r3, #4] + 8001d44: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001d48: 687b ldr r3, [r7, #4] + 8001d4a: 689b ldr r3, [r3, #8] + 8001d4c: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001d50: 431a orrs r2, r3 + 8001d52: 687b ldr r3, [r7, #4] + 8001d54: 68db ldr r3, [r3, #12] + 8001d56: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001d5a: 431a orrs r2, r3 + 8001d5c: 687b ldr r3, [r7, #4] + 8001d5e: 691b ldr r3, [r3, #16] + 8001d60: f003 0302 and.w r3, r3, #2 + 8001d64: 431a orrs r2, r3 + 8001d66: 687b ldr r3, [r7, #4] + 8001d68: 695b ldr r3, [r3, #20] + 8001d6a: f003 0301 and.w r3, r3, #1 + 8001d6e: 431a orrs r2, r3 + 8001d70: 687b ldr r3, [r7, #4] + 8001d72: 699b ldr r3, [r3, #24] + 8001d74: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001d78: 431a orrs r2, r3 + 8001d7a: 687b ldr r3, [r7, #4] + 8001d7c: 69db ldr r3, [r3, #28] + 8001d7e: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001d82: 431a orrs r2, r3 + 8001d84: 687b ldr r3, [r7, #4] + 8001d86: 6a1b ldr r3, [r3, #32] + 8001d88: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001d8c: ea42 0103 orr.w r1, r2, r3 + 8001d90: 687b ldr r3, [r7, #4] + 8001d92: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001d94: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001d98: 687b ldr r3, [r7, #4] + 8001d9a: 681b ldr r3, [r3, #0] + 8001d9c: 430a orrs r2, r1 + 8001d9e: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8001da0: 687b ldr r3, [r7, #4] + 8001da2: 699b ldr r3, [r3, #24] + 8001da4: 0c1b lsrs r3, r3, #16 + 8001da6: f003 0104 and.w r1, r3, #4 + 8001daa: 687b ldr r3, [r7, #4] + 8001dac: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001dae: f003 0210 and.w r2, r3, #16 + 8001db2: 687b ldr r3, [r7, #4] + 8001db4: 681b ldr r3, [r3, #0] + 8001db6: 430a orrs r2, r1 + 8001db8: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8001dba: 687b ldr r3, [r7, #4] + 8001dbc: 681b ldr r3, [r3, #0] + 8001dbe: 69da ldr r2, [r3, #28] + 8001dc0: 687b ldr r3, [r7, #4] + 8001dc2: 681b ldr r3, [r3, #0] + 8001dc4: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001dc8: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001dca: 687b ldr r3, [r7, #4] + 8001dcc: 2200 movs r2, #0 + 8001dce: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8001dd0: 687b ldr r3, [r7, #4] + 8001dd2: 2201 movs r2, #1 + 8001dd4: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8001dd8: 2300 movs r3, #0 +} + 8001dda: 4618 mov r0, r3 + 8001ddc: 3708 adds r7, #8 + 8001dde: 46bd mov sp, r7 + 8001de0: bd80 pop {r7, pc} + +08001de2 : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8001de2: b580 push {r7, lr} + 8001de4: b088 sub sp, #32 + 8001de6: af00 add r7, sp, #0 + 8001de8: 60f8 str r0, [r7, #12] + 8001dea: 60b9 str r1, [r7, #8] + 8001dec: 603b str r3, [r7, #0] + 8001dee: 4613 mov r3, r2 + 8001df0: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001df2: f7fe ff13 bl 8000c1c + 8001df6: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8001df8: 88fb ldrh r3, [r7, #6] + 8001dfa: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8001dfc: 68fb ldr r3, [r7, #12] + 8001dfe: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001e02: b2db uxtb r3, r3 + 8001e04: 2b01 cmp r3, #1 + 8001e06: d001 beq.n 8001e0c + { + return HAL_BUSY; + 8001e08: 2302 movs r3, #2 + 8001e0a: e12a b.n 8002062 + } + + if ((pData == NULL) || (Size == 0U)) + 8001e0c: 68bb ldr r3, [r7, #8] + 8001e0e: 2b00 cmp r3, #0 + 8001e10: d002 beq.n 8001e18 + 8001e12: 88fb ldrh r3, [r7, #6] + 8001e14: 2b00 cmp r3, #0 + 8001e16: d101 bne.n 8001e1c + { + return HAL_ERROR; + 8001e18: 2301 movs r3, #1 + 8001e1a: e122 b.n 8002062 + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 8001e1c: 68fb ldr r3, [r7, #12] + 8001e1e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001e22: 2b01 cmp r3, #1 + 8001e24: d101 bne.n 8001e2a + 8001e26: 2302 movs r3, #2 + 8001e28: e11b b.n 8002062 + 8001e2a: 68fb ldr r3, [r7, #12] + 8001e2c: 2201 movs r2, #1 + 8001e2e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8001e32: 68fb ldr r3, [r7, #12] + 8001e34: 2203 movs r2, #3 + 8001e36: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001e3a: 68fb ldr r3, [r7, #12] + 8001e3c: 2200 movs r2, #0 + 8001e3e: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8001e40: 68fb ldr r3, [r7, #12] + 8001e42: 68ba ldr r2, [r7, #8] + 8001e44: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 8001e46: 68fb ldr r3, [r7, #12] + 8001e48: 88fa ldrh r2, [r7, #6] + 8001e4a: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8001e4c: 68fb ldr r3, [r7, #12] + 8001e4e: 88fa ldrh r2, [r7, #6] + 8001e50: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8001e52: 68fb ldr r3, [r7, #12] + 8001e54: 2200 movs r2, #0 + 8001e56: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 8001e58: 68fb ldr r3, [r7, #12] + 8001e5a: 2200 movs r2, #0 + 8001e5c: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8001e5e: 68fb ldr r3, [r7, #12] + 8001e60: 2200 movs r2, #0 + 8001e62: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 8001e64: 68fb ldr r3, [r7, #12] + 8001e66: 2200 movs r2, #0 + 8001e68: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8001e6a: 68fb ldr r3, [r7, #12] + 8001e6c: 2200 movs r2, #0 + 8001e6e: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8001e70: 68fb ldr r3, [r7, #12] + 8001e72: 689b ldr r3, [r3, #8] + 8001e74: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001e78: d10f bne.n 8001e9a + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8001e7a: 68fb ldr r3, [r7, #12] + 8001e7c: 681b ldr r3, [r3, #0] + 8001e7e: 681a ldr r2, [r3, #0] + 8001e80: 68fb ldr r3, [r7, #12] + 8001e82: 681b ldr r3, [r3, #0] + 8001e84: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001e88: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8001e8a: 68fb ldr r3, [r7, #12] + 8001e8c: 681b ldr r3, [r3, #0] + 8001e8e: 681a ldr r2, [r3, #0] + 8001e90: 68fb ldr r3, [r7, #12] + 8001e92: 681b ldr r3, [r3, #0] + 8001e94: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8001e98: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8001e9a: 68fb ldr r3, [r7, #12] + 8001e9c: 681b ldr r3, [r3, #0] + 8001e9e: 681b ldr r3, [r3, #0] + 8001ea0: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001ea4: 2b40 cmp r3, #64 @ 0x40 + 8001ea6: d007 beq.n 8001eb8 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8001ea8: 68fb ldr r3, [r7, #12] + 8001eaa: 681b ldr r3, [r3, #0] + 8001eac: 681a ldr r2, [r3, #0] + 8001eae: 68fb ldr r3, [r7, #12] + 8001eb0: 681b ldr r3, [r3, #0] + 8001eb2: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8001eb6: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8001eb8: 68fb ldr r3, [r7, #12] + 8001eba: 68db ldr r3, [r3, #12] + 8001ebc: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8001ec0: d152 bne.n 8001f68 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001ec2: 68fb ldr r3, [r7, #12] + 8001ec4: 685b ldr r3, [r3, #4] + 8001ec6: 2b00 cmp r3, #0 + 8001ec8: d002 beq.n 8001ed0 + 8001eca: 8b7b ldrh r3, [r7, #26] + 8001ecc: 2b01 cmp r3, #1 + 8001ece: d145 bne.n 8001f5c + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001ed0: 68fb ldr r3, [r7, #12] + 8001ed2: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ed4: 881a ldrh r2, [r3, #0] + 8001ed6: 68fb ldr r3, [r7, #12] + 8001ed8: 681b ldr r3, [r3, #0] + 8001eda: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001edc: 68fb ldr r3, [r7, #12] + 8001ede: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ee0: 1c9a adds r2, r3, #2 + 8001ee2: 68fb ldr r3, [r7, #12] + 8001ee4: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001ee6: 68fb ldr r3, [r7, #12] + 8001ee8: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001eea: b29b uxth r3, r3 + 8001eec: 3b01 subs r3, #1 + 8001eee: b29a uxth r2, r3 + 8001ef0: 68fb ldr r3, [r7, #12] + 8001ef2: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 8001ef4: e032 b.n 8001f5c + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001ef6: 68fb ldr r3, [r7, #12] + 8001ef8: 681b ldr r3, [r3, #0] + 8001efa: 689b ldr r3, [r3, #8] + 8001efc: f003 0302 and.w r3, r3, #2 + 8001f00: 2b02 cmp r3, #2 + 8001f02: d112 bne.n 8001f2a + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001f04: 68fb ldr r3, [r7, #12] + 8001f06: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001f08: 881a ldrh r2, [r3, #0] + 8001f0a: 68fb ldr r3, [r7, #12] + 8001f0c: 681b ldr r3, [r3, #0] + 8001f0e: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001f10: 68fb ldr r3, [r7, #12] + 8001f12: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001f14: 1c9a adds r2, r3, #2 + 8001f16: 68fb ldr r3, [r7, #12] + 8001f18: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001f1a: 68fb ldr r3, [r7, #12] + 8001f1c: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001f1e: b29b uxth r3, r3 + 8001f20: 3b01 subs r3, #1 + 8001f22: b29a uxth r2, r3 + 8001f24: 68fb ldr r3, [r7, #12] + 8001f26: 86da strh r2, [r3, #54] @ 0x36 + 8001f28: e018 b.n 8001f5c + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001f2a: f7fe fe77 bl 8000c1c + 8001f2e: 4602 mov r2, r0 + 8001f30: 69fb ldr r3, [r7, #28] + 8001f32: 1ad3 subs r3, r2, r3 + 8001f34: 683a ldr r2, [r7, #0] + 8001f36: 429a cmp r2, r3 + 8001f38: d803 bhi.n 8001f42 + 8001f3a: 683b ldr r3, [r7, #0] + 8001f3c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001f40: d102 bne.n 8001f48 + 8001f42: 683b ldr r3, [r7, #0] + 8001f44: 2b00 cmp r3, #0 + 8001f46: d109 bne.n 8001f5c + { + hspi->State = HAL_SPI_STATE_READY; + 8001f48: 68fb ldr r3, [r7, #12] + 8001f4a: 2201 movs r2, #1 + 8001f4c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001f50: 68fb ldr r3, [r7, #12] + 8001f52: 2200 movs r2, #0 + 8001f54: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001f58: 2303 movs r3, #3 + 8001f5a: e082 b.n 8002062 + while (hspi->TxXferCount > 0U) + 8001f5c: 68fb ldr r3, [r7, #12] + 8001f5e: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001f60: b29b uxth r3, r3 + 8001f62: 2b00 cmp r3, #0 + 8001f64: d1c7 bne.n 8001ef6 + 8001f66: e053 b.n 8002010 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001f68: 68fb ldr r3, [r7, #12] + 8001f6a: 685b ldr r3, [r3, #4] + 8001f6c: 2b00 cmp r3, #0 + 8001f6e: d002 beq.n 8001f76 + 8001f70: 8b7b ldrh r3, [r7, #26] + 8001f72: 2b01 cmp r3, #1 + 8001f74: d147 bne.n 8002006 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001f76: 68fb ldr r3, [r7, #12] + 8001f78: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001f7a: 68fb ldr r3, [r7, #12] + 8001f7c: 681b ldr r3, [r3, #0] + 8001f7e: 330c adds r3, #12 + 8001f80: 7812 ldrb r2, [r2, #0] + 8001f82: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001f84: 68fb ldr r3, [r7, #12] + 8001f86: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001f88: 1c5a adds r2, r3, #1 + 8001f8a: 68fb ldr r3, [r7, #12] + 8001f8c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001f8e: 68fb ldr r3, [r7, #12] + 8001f90: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001f92: b29b uxth r3, r3 + 8001f94: 3b01 subs r3, #1 + 8001f96: b29a uxth r2, r3 + 8001f98: 68fb ldr r3, [r7, #12] + 8001f9a: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8001f9c: e033 b.n 8002006 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001f9e: 68fb ldr r3, [r7, #12] + 8001fa0: 681b ldr r3, [r3, #0] + 8001fa2: 689b ldr r3, [r3, #8] + 8001fa4: f003 0302 and.w r3, r3, #2 + 8001fa8: 2b02 cmp r3, #2 + 8001faa: d113 bne.n 8001fd4 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001fac: 68fb ldr r3, [r7, #12] + 8001fae: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001fb0: 68fb ldr r3, [r7, #12] + 8001fb2: 681b ldr r3, [r3, #0] + 8001fb4: 330c adds r3, #12 + 8001fb6: 7812 ldrb r2, [r2, #0] + 8001fb8: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001fba: 68fb ldr r3, [r7, #12] + 8001fbc: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001fbe: 1c5a adds r2, r3, #1 + 8001fc0: 68fb ldr r3, [r7, #12] + 8001fc2: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001fc4: 68fb ldr r3, [r7, #12] + 8001fc6: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001fc8: b29b uxth r3, r3 + 8001fca: 3b01 subs r3, #1 + 8001fcc: b29a uxth r2, r3 + 8001fce: 68fb ldr r3, [r7, #12] + 8001fd0: 86da strh r2, [r3, #54] @ 0x36 + 8001fd2: e018 b.n 8002006 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001fd4: f7fe fe22 bl 8000c1c + 8001fd8: 4602 mov r2, r0 + 8001fda: 69fb ldr r3, [r7, #28] + 8001fdc: 1ad3 subs r3, r2, r3 + 8001fde: 683a ldr r2, [r7, #0] + 8001fe0: 429a cmp r2, r3 + 8001fe2: d803 bhi.n 8001fec + 8001fe4: 683b ldr r3, [r7, #0] + 8001fe6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001fea: d102 bne.n 8001ff2 + 8001fec: 683b ldr r3, [r7, #0] + 8001fee: 2b00 cmp r3, #0 + 8001ff0: d109 bne.n 8002006 + { + hspi->State = HAL_SPI_STATE_READY; + 8001ff2: 68fb ldr r3, [r7, #12] + 8001ff4: 2201 movs r2, #1 + 8001ff6: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001ffa: 68fb ldr r3, [r7, #12] + 8001ffc: 2200 movs r2, #0 + 8001ffe: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8002002: 2303 movs r3, #3 + 8002004: e02d b.n 8002062 + while (hspi->TxXferCount > 0U) + 8002006: 68fb ldr r3, [r7, #12] + 8002008: 8edb ldrh r3, [r3, #54] @ 0x36 + 800200a: b29b uxth r3, r3 + 800200c: 2b00 cmp r3, #0 + 800200e: d1c6 bne.n 8001f9e + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 8002010: 69fa ldr r2, [r7, #28] + 8002012: 6839 ldr r1, [r7, #0] + 8002014: 68f8 ldr r0, [r7, #12] + 8002016: f000 f8b1 bl 800217c + 800201a: 4603 mov r3, r0 + 800201c: 2b00 cmp r3, #0 + 800201e: d002 beq.n 8002026 + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 8002020: 68fb ldr r3, [r7, #12] + 8002022: 2220 movs r2, #32 + 8002024: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 8002026: 68fb ldr r3, [r7, #12] + 8002028: 689b ldr r3, [r3, #8] + 800202a: 2b00 cmp r3, #0 + 800202c: d10a bne.n 8002044 + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 800202e: 2300 movs r3, #0 + 8002030: 617b str r3, [r7, #20] + 8002032: 68fb ldr r3, [r7, #12] + 8002034: 681b ldr r3, [r3, #0] + 8002036: 68db ldr r3, [r3, #12] + 8002038: 617b str r3, [r7, #20] + 800203a: 68fb ldr r3, [r7, #12] + 800203c: 681b ldr r3, [r3, #0] + 800203e: 689b ldr r3, [r3, #8] + 8002040: 617b str r3, [r7, #20] + 8002042: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 8002044: 68fb ldr r3, [r7, #12] + 8002046: 2201 movs r2, #1 + 8002048: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 800204c: 68fb ldr r3, [r7, #12] + 800204e: 2200 movs r2, #0 + 8002050: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 8002054: 68fb ldr r3, [r7, #12] + 8002056: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002058: 2b00 cmp r3, #0 + 800205a: d001 beq.n 8002060 + { + return HAL_ERROR; + 800205c: 2301 movs r3, #1 + 800205e: e000 b.n 8002062 + } + else + { + return HAL_OK; + 8002060: 2300 movs r3, #0 + } +} + 8002062: 4618 mov r0, r3 + 8002064: 3720 adds r7, #32 + 8002066: 46bd mov sp, r7 + 8002068: bd80 pop {r7, pc} + ... + +0800206c : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 800206c: b580 push {r7, lr} + 800206e: b088 sub sp, #32 + 8002070: af00 add r7, sp, #0 + 8002072: 60f8 str r0, [r7, #12] + 8002074: 60b9 str r1, [r7, #8] + 8002076: 603b str r3, [r7, #0] + 8002078: 4613 mov r3, r2 + 800207a: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 800207c: f7fe fdce bl 8000c1c + 8002080: 4602 mov r2, r0 + 8002082: 6abb ldr r3, [r7, #40] @ 0x28 + 8002084: 1a9b subs r3, r3, r2 + 8002086: 683a ldr r2, [r7, #0] + 8002088: 4413 add r3, r2 + 800208a: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 800208c: f7fe fdc6 bl 8000c1c + 8002090: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 8002092: 4b39 ldr r3, [pc, #228] @ (8002178 ) + 8002094: 681b ldr r3, [r3, #0] + 8002096: 015b lsls r3, r3, #5 + 8002098: 0d1b lsrs r3, r3, #20 + 800209a: 69fa ldr r2, [r7, #28] + 800209c: fb02 f303 mul.w r3, r2, r3 + 80020a0: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 80020a2: e054 b.n 800214e + { + if (Timeout != HAL_MAX_DELAY) + 80020a4: 683b ldr r3, [r7, #0] + 80020a6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80020aa: d050 beq.n 800214e + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 80020ac: f7fe fdb6 bl 8000c1c + 80020b0: 4602 mov r2, r0 + 80020b2: 69bb ldr r3, [r7, #24] + 80020b4: 1ad3 subs r3, r2, r3 + 80020b6: 69fa ldr r2, [r7, #28] + 80020b8: 429a cmp r2, r3 + 80020ba: d902 bls.n 80020c2 + 80020bc: 69fb ldr r3, [r7, #28] + 80020be: 2b00 cmp r3, #0 + 80020c0: d13d bne.n 800213e + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 80020c2: 68fb ldr r3, [r7, #12] + 80020c4: 681b ldr r3, [r3, #0] + 80020c6: 685a ldr r2, [r3, #4] + 80020c8: 68fb ldr r3, [r7, #12] + 80020ca: 681b ldr r3, [r3, #0] + 80020cc: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 80020d0: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 80020d2: 68fb ldr r3, [r7, #12] + 80020d4: 685b ldr r3, [r3, #4] + 80020d6: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 80020da: d111 bne.n 8002100 + 80020dc: 68fb ldr r3, [r7, #12] + 80020de: 689b ldr r3, [r3, #8] + 80020e0: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 80020e4: d004 beq.n 80020f0 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 80020e6: 68fb ldr r3, [r7, #12] + 80020e8: 689b ldr r3, [r3, #8] + 80020ea: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 80020ee: d107 bne.n 8002100 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 80020f0: 68fb ldr r3, [r7, #12] + 80020f2: 681b ldr r3, [r3, #0] + 80020f4: 681a ldr r2, [r3, #0] + 80020f6: 68fb ldr r3, [r7, #12] + 80020f8: 681b ldr r3, [r3, #0] + 80020fa: f022 0240 bic.w r2, r2, #64 @ 0x40 + 80020fe: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8002100: 68fb ldr r3, [r7, #12] + 8002102: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002104: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002108: d10f bne.n 800212a + { + SPI_RESET_CRC(hspi); + 800210a: 68fb ldr r3, [r7, #12] + 800210c: 681b ldr r3, [r3, #0] + 800210e: 681a ldr r2, [r3, #0] + 8002110: 68fb ldr r3, [r7, #12] + 8002112: 681b ldr r3, [r3, #0] + 8002114: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 8002118: 601a str r2, [r3, #0] + 800211a: 68fb ldr r3, [r7, #12] + 800211c: 681b ldr r3, [r3, #0] + 800211e: 681a ldr r2, [r3, #0] + 8002120: 68fb ldr r3, [r7, #12] + 8002122: 681b ldr r3, [r3, #0] + 8002124: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 8002128: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 800212a: 68fb ldr r3, [r7, #12] + 800212c: 2201 movs r2, #1 + 800212e: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8002132: 68fb ldr r3, [r7, #12] + 8002134: 2200 movs r2, #0 + 8002136: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 800213a: 2303 movs r3, #3 + 800213c: e017 b.n 800216e + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 800213e: 697b ldr r3, [r7, #20] + 8002140: 2b00 cmp r3, #0 + 8002142: d101 bne.n 8002148 + { + tmp_timeout = 0U; + 8002144: 2300 movs r3, #0 + 8002146: 61fb str r3, [r7, #28] + } + count--; + 8002148: 697b ldr r3, [r7, #20] + 800214a: 3b01 subs r3, #1 + 800214c: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 800214e: 68fb ldr r3, [r7, #12] + 8002150: 681b ldr r3, [r3, #0] + 8002152: 689a ldr r2, [r3, #8] + 8002154: 68bb ldr r3, [r7, #8] + 8002156: 4013 ands r3, r2 + 8002158: 68ba ldr r2, [r7, #8] + 800215a: 429a cmp r2, r3 + 800215c: bf0c ite eq + 800215e: 2301 moveq r3, #1 + 8002160: 2300 movne r3, #0 + 8002162: b2db uxtb r3, r3 + 8002164: 461a mov r2, r3 + 8002166: 79fb ldrb r3, [r7, #7] + 8002168: 429a cmp r2, r3 + 800216a: d19b bne.n 80020a4 + } + } + + return HAL_OK; + 800216c: 2300 movs r3, #0 +} + 800216e: 4618 mov r0, r3 + 8002170: 3720 adds r7, #32 + 8002172: 46bd mov sp, r7 + 8002174: bd80 pop {r7, pc} + 8002176: bf00 nop + 8002178: 20000000 .word 0x20000000 + +0800217c : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 800217c: b580 push {r7, lr} + 800217e: b088 sub sp, #32 + 8002180: af02 add r7, sp, #8 + 8002182: 60f8 str r0, [r7, #12] + 8002184: 60b9 str r1, [r7, #8] + 8002186: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 8002188: 687b ldr r3, [r7, #4] + 800218a: 9300 str r3, [sp, #0] + 800218c: 68bb ldr r3, [r7, #8] + 800218e: 2201 movs r2, #1 + 8002190: 2102 movs r1, #2 + 8002192: 68f8 ldr r0, [r7, #12] + 8002194: f7ff ff6a bl 800206c + 8002198: 4603 mov r3, r0 + 800219a: 2b00 cmp r3, #0 + 800219c: d007 beq.n 80021ae + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800219e: 68fb ldr r3, [r7, #12] + 80021a0: 6d5b ldr r3, [r3, #84] @ 0x54 + 80021a2: f043 0220 orr.w r2, r3, #32 + 80021a6: 68fb ldr r3, [r7, #12] + 80021a8: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 80021aa: 2303 movs r3, #3 + 80021ac: e032 b.n 8002214 + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 80021ae: 4b1b ldr r3, [pc, #108] @ (800221c ) + 80021b0: 681b ldr r3, [r3, #0] + 80021b2: 4a1b ldr r2, [pc, #108] @ (8002220 ) + 80021b4: fba2 2303 umull r2, r3, r2, r3 + 80021b8: 0d5b lsrs r3, r3, #21 + 80021ba: f44f 727a mov.w r2, #1000 @ 0x3e8 + 80021be: fb02 f303 mul.w r3, r2, r3 + 80021c2: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 80021c4: 68fb ldr r3, [r7, #12] + 80021c6: 685b ldr r3, [r3, #4] + 80021c8: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 80021cc: d112 bne.n 80021f4 + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 80021ce: 687b ldr r3, [r7, #4] + 80021d0: 9300 str r3, [sp, #0] + 80021d2: 68bb ldr r3, [r7, #8] + 80021d4: 2200 movs r2, #0 + 80021d6: 2180 movs r1, #128 @ 0x80 + 80021d8: 68f8 ldr r0, [r7, #12] + 80021da: f7ff ff47 bl 800206c + 80021de: 4603 mov r3, r0 + 80021e0: 2b00 cmp r3, #0 + 80021e2: d016 beq.n 8002212 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 80021e4: 68fb ldr r3, [r7, #12] + 80021e6: 6d5b ldr r3, [r3, #84] @ 0x54 + 80021e8: f043 0220 orr.w r2, r3, #32 + 80021ec: 68fb ldr r3, [r7, #12] + 80021ee: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 80021f0: 2303 movs r3, #3 + 80021f2: e00f b.n 8002214 + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 80021f4: 697b ldr r3, [r7, #20] + 80021f6: 2b00 cmp r3, #0 + 80021f8: d00a beq.n 8002210 + { + break; + } + count--; + 80021fa: 697b ldr r3, [r7, #20] + 80021fc: 3b01 subs r3, #1 + 80021fe: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 8002200: 68fb ldr r3, [r7, #12] + 8002202: 681b ldr r3, [r3, #0] + 8002204: 689b ldr r3, [r3, #8] + 8002206: f003 0380 and.w r3, r3, #128 @ 0x80 + 800220a: 2b80 cmp r3, #128 @ 0x80 + 800220c: d0f2 beq.n 80021f4 + 800220e: e000 b.n 8002212 + break; + 8002210: bf00 nop + } + + return HAL_OK; + 8002212: 2300 movs r3, #0 +} + 8002214: 4618 mov r0, r3 + 8002216: 3718 adds r7, #24 + 8002218: 46bd mov sp, r7 + 800221a: bd80 pop {r7, pc} + 800221c: 20000000 .word 0x20000000 + 8002220: 165e9f81 .word 0x165e9f81 + +08002224 : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 8002224: b580 push {r7, lr} + 8002226: b082 sub sp, #8 + 8002228: af00 add r7, sp, #0 + 800222a: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 800222c: 687b ldr r3, [r7, #4] + 800222e: 2b00 cmp r3, #0 + 8002230: d101 bne.n 8002236 + { + return HAL_ERROR; + 8002232: 2301 movs r3, #1 + 8002234: e031 b.n 800229a + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8002236: 687b ldr r3, [r7, #4] + 8002238: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 800223c: b2db uxtb r3, r3 + 800223e: 2b00 cmp r3, #0 + 8002240: d106 bne.n 8002250 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8002242: 687b ldr r3, [r7, #4] + 8002244: 2200 movs r2, #0 + 8002246: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 800224a: 6878 ldr r0, [r7, #4] + 800224c: f7fe fb5e bl 800090c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002250: 687b ldr r3, [r7, #4] + 8002252: 2202 movs r2, #2 + 8002254: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002258: 687b ldr r3, [r7, #4] + 800225a: 681a ldr r2, [r3, #0] + 800225c: 687b ldr r3, [r7, #4] + 800225e: 3304 adds r3, #4 + 8002260: 4619 mov r1, r3 + 8002262: 4610 mov r0, r2 + 8002264: f000 fa28 bl 80026b8 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002268: 687b ldr r3, [r7, #4] + 800226a: 2201 movs r2, #1 + 800226c: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8002270: 687b ldr r3, [r7, #4] + 8002272: 2201 movs r2, #1 + 8002274: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002278: 687b ldr r3, [r7, #4] + 800227a: 2201 movs r2, #1 + 800227c: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002280: 687b ldr r3, [r7, #4] + 8002282: 2201 movs r2, #1 + 8002284: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002288: 687b ldr r3, [r7, #4] + 800228a: 2201 movs r2, #1 + 800228c: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8002290: 687b ldr r3, [r7, #4] + 8002292: 2201 movs r2, #1 + 8002294: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 8002298: 2300 movs r3, #0 +} + 800229a: 4618 mov r0, r3 + 800229c: 3708 adds r7, #8 + 800229e: 46bd mov sp, r7 + 80022a0: bd80 pop {r7, pc} + ... + +080022a4 : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 80022a4: b480 push {r7} + 80022a6: b085 sub sp, #20 + 80022a8: af00 add r7, sp, #0 + 80022aa: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + 80022ac: 687b ldr r3, [r7, #4] + 80022ae: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 80022b2: b2db uxtb r3, r3 + 80022b4: 2b01 cmp r3, #1 + 80022b6: d001 beq.n 80022bc + { + return HAL_ERROR; + 80022b8: 2301 movs r3, #1 + 80022ba: e03a b.n 8002332 + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80022bc: 687b ldr r3, [r7, #4] + 80022be: 2202 movs r2, #2 + 80022c0: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 80022c4: 687b ldr r3, [r7, #4] + 80022c6: 681b ldr r3, [r3, #0] + 80022c8: 68da ldr r2, [r3, #12] + 80022ca: 687b ldr r3, [r7, #4] + 80022cc: 681b ldr r3, [r3, #0] + 80022ce: f042 0201 orr.w r2, r2, #1 + 80022d2: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 80022d4: 687b ldr r3, [r7, #4] + 80022d6: 681b ldr r3, [r3, #0] + 80022d8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80022dc: d00e beq.n 80022fc + 80022de: 687b ldr r3, [r7, #4] + 80022e0: 681b ldr r3, [r3, #0] + 80022e2: 4a16 ldr r2, [pc, #88] @ (800233c ) + 80022e4: 4293 cmp r3, r2 + 80022e6: d009 beq.n 80022fc + 80022e8: 687b ldr r3, [r7, #4] + 80022ea: 681b ldr r3, [r3, #0] + 80022ec: 4a14 ldr r2, [pc, #80] @ (8002340 ) + 80022ee: 4293 cmp r3, r2 + 80022f0: d004 beq.n 80022fc + 80022f2: 687b ldr r3, [r7, #4] + 80022f4: 681b ldr r3, [r3, #0] + 80022f6: 4a13 ldr r2, [pc, #76] @ (8002344 ) + 80022f8: 4293 cmp r3, r2 + 80022fa: d111 bne.n 8002320 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 80022fc: 687b ldr r3, [r7, #4] + 80022fe: 681b ldr r3, [r3, #0] + 8002300: 689b ldr r3, [r3, #8] + 8002302: f003 0307 and.w r3, r3, #7 + 8002306: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8002308: 68fb ldr r3, [r7, #12] + 800230a: 2b06 cmp r3, #6 + 800230c: d010 beq.n 8002330 + { + __HAL_TIM_ENABLE(htim); + 800230e: 687b ldr r3, [r7, #4] + 8002310: 681b ldr r3, [r3, #0] + 8002312: 681a ldr r2, [r3, #0] + 8002314: 687b ldr r3, [r7, #4] + 8002316: 681b ldr r3, [r3, #0] + 8002318: f042 0201 orr.w r2, r2, #1 + 800231c: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 800231e: e007 b.n 8002330 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 8002320: 687b ldr r3, [r7, #4] + 8002322: 681b ldr r3, [r3, #0] + 8002324: 681a ldr r2, [r3, #0] + 8002326: 687b ldr r3, [r7, #4] + 8002328: 681b ldr r3, [r3, #0] + 800232a: f042 0201 orr.w r2, r2, #1 + 800232e: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8002330: 2300 movs r3, #0 +} + 8002332: 4618 mov r0, r3 + 8002334: 3714 adds r7, #20 + 8002336: 46bd mov sp, r7 + 8002338: bc80 pop {r7} + 800233a: 4770 bx lr + 800233c: 40000400 .word 0x40000400 + 8002340: 40000800 .word 0x40000800 + 8002344: 40010800 .word 0x40010800 + +08002348 : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 8002348: b580 push {r7, lr} + 800234a: b084 sub sp, #16 + 800234c: af00 add r7, sp, #0 + 800234e: 6078 str r0, [r7, #4] + uint32_t itsource = htim->Instance->DIER; + 8002350: 687b ldr r3, [r7, #4] + 8002352: 681b ldr r3, [r3, #0] + 8002354: 68db ldr r3, [r3, #12] + 8002356: 60fb str r3, [r7, #12] + uint32_t itflag = htim->Instance->SR; + 8002358: 687b ldr r3, [r7, #4] + 800235a: 681b ldr r3, [r3, #0] + 800235c: 691b ldr r3, [r3, #16] + 800235e: 60bb str r3, [r7, #8] + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + 8002360: 68bb ldr r3, [r7, #8] + 8002362: f003 0302 and.w r3, r3, #2 + 8002366: 2b00 cmp r3, #0 + 8002368: d020 beq.n 80023ac + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + 800236a: 68fb ldr r3, [r7, #12] + 800236c: f003 0302 and.w r3, r3, #2 + 8002370: 2b00 cmp r3, #0 + 8002372: d01b beq.n 80023ac + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + 8002374: 687b ldr r3, [r7, #4] + 8002376: 681b ldr r3, [r3, #0] + 8002378: f06f 0202 mvn.w r2, #2 + 800237c: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 800237e: 687b ldr r3, [r7, #4] + 8002380: 2201 movs r2, #1 + 8002382: 761a strb r2, [r3, #24] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 8002384: 687b ldr r3, [r7, #4] + 8002386: 681b ldr r3, [r3, #0] + 8002388: 699b ldr r3, [r3, #24] + 800238a: f003 0303 and.w r3, r3, #3 + 800238e: 2b00 cmp r3, #0 + 8002390: d003 beq.n 800239a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002392: 6878 ldr r0, [r7, #4] + 8002394: f000 f974 bl 8002680 + 8002398: e005 b.n 80023a6 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800239a: 6878 ldr r0, [r7, #4] + 800239c: f000 f967 bl 800266e + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80023a0: 6878 ldr r0, [r7, #4] + 80023a2: f000 f976 bl 8002692 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80023a6: 687b ldr r3, [r7, #4] + 80023a8: 2200 movs r2, #0 + 80023aa: 761a strb r2, [r3, #24] + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + 80023ac: 68bb ldr r3, [r7, #8] + 80023ae: f003 0304 and.w r3, r3, #4 + 80023b2: 2b00 cmp r3, #0 + 80023b4: d020 beq.n 80023f8 + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + 80023b6: 68fb ldr r3, [r7, #12] + 80023b8: f003 0304 and.w r3, r3, #4 + 80023bc: 2b00 cmp r3, #0 + 80023be: d01b beq.n 80023f8 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + 80023c0: 687b ldr r3, [r7, #4] + 80023c2: 681b ldr r3, [r3, #0] + 80023c4: f06f 0204 mvn.w r2, #4 + 80023c8: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 80023ca: 687b ldr r3, [r7, #4] + 80023cc: 2202 movs r2, #2 + 80023ce: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 80023d0: 687b ldr r3, [r7, #4] + 80023d2: 681b ldr r3, [r3, #0] + 80023d4: 699b ldr r3, [r3, #24] + 80023d6: f403 7340 and.w r3, r3, #768 @ 0x300 + 80023da: 2b00 cmp r3, #0 + 80023dc: d003 beq.n 80023e6 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 80023de: 6878 ldr r0, [r7, #4] + 80023e0: f000 f94e bl 8002680 + 80023e4: e005 b.n 80023f2 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80023e6: 6878 ldr r0, [r7, #4] + 80023e8: f000 f941 bl 800266e + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80023ec: 6878 ldr r0, [r7, #4] + 80023ee: f000 f950 bl 8002692 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80023f2: 687b ldr r3, [r7, #4] + 80023f4: 2200 movs r2, #0 + 80023f6: 761a strb r2, [r3, #24] + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + 80023f8: 68bb ldr r3, [r7, #8] + 80023fa: f003 0308 and.w r3, r3, #8 + 80023fe: 2b00 cmp r3, #0 + 8002400: d020 beq.n 8002444 + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + 8002402: 68fb ldr r3, [r7, #12] + 8002404: f003 0308 and.w r3, r3, #8 + 8002408: 2b00 cmp r3, #0 + 800240a: d01b beq.n 8002444 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + 800240c: 687b ldr r3, [r7, #4] + 800240e: 681b ldr r3, [r3, #0] + 8002410: f06f 0208 mvn.w r2, #8 + 8002414: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8002416: 687b ldr r3, [r7, #4] + 8002418: 2204 movs r2, #4 + 800241a: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 800241c: 687b ldr r3, [r7, #4] + 800241e: 681b ldr r3, [r3, #0] + 8002420: 69db ldr r3, [r3, #28] + 8002422: f003 0303 and.w r3, r3, #3 + 8002426: 2b00 cmp r3, #0 + 8002428: d003 beq.n 8002432 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 800242a: 6878 ldr r0, [r7, #4] + 800242c: f000 f928 bl 8002680 + 8002430: e005 b.n 800243e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002432: 6878 ldr r0, [r7, #4] + 8002434: f000 f91b bl 800266e + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002438: 6878 ldr r0, [r7, #4] + 800243a: f000 f92a bl 8002692 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 800243e: 687b ldr r3, [r7, #4] + 8002440: 2200 movs r2, #0 + 8002442: 761a strb r2, [r3, #24] + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + 8002444: 68bb ldr r3, [r7, #8] + 8002446: f003 0310 and.w r3, r3, #16 + 800244a: 2b00 cmp r3, #0 + 800244c: d020 beq.n 8002490 + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + 800244e: 68fb ldr r3, [r7, #12] + 8002450: f003 0310 and.w r3, r3, #16 + 8002454: 2b00 cmp r3, #0 + 8002456: d01b beq.n 8002490 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + 8002458: 687b ldr r3, [r7, #4] + 800245a: 681b ldr r3, [r3, #0] + 800245c: f06f 0210 mvn.w r2, #16 + 8002460: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8002462: 687b ldr r3, [r7, #4] + 8002464: 2208 movs r2, #8 + 8002466: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8002468: 687b ldr r3, [r7, #4] + 800246a: 681b ldr r3, [r3, #0] + 800246c: 69db ldr r3, [r3, #28] + 800246e: f403 7340 and.w r3, r3, #768 @ 0x300 + 8002472: 2b00 cmp r3, #0 + 8002474: d003 beq.n 800247e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002476: 6878 ldr r0, [r7, #4] + 8002478: f000 f902 bl 8002680 + 800247c: e005 b.n 800248a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800247e: 6878 ldr r0, [r7, #4] + 8002480: f000 f8f5 bl 800266e + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002484: 6878 ldr r0, [r7, #4] + 8002486: f000 f904 bl 8002692 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 800248a: 687b ldr r3, [r7, #4] + 800248c: 2200 movs r2, #0 + 800248e: 761a strb r2, [r3, #24] + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + 8002490: 68bb ldr r3, [r7, #8] + 8002492: f003 0301 and.w r3, r3, #1 + 8002496: 2b00 cmp r3, #0 + 8002498: d00c beq.n 80024b4 + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + 800249a: 68fb ldr r3, [r7, #12] + 800249c: f003 0301 and.w r3, r3, #1 + 80024a0: 2b00 cmp r3, #0 + 80024a2: d007 beq.n 80024b4 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); + 80024a4: 687b ldr r3, [r7, #4] + 80024a6: 681b ldr r3, [r3, #0] + 80024a8: f06f 0201 mvn.w r2, #1 + 80024ac: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 80024ae: 6878 ldr r0, [r7, #4] + 80024b0: f7fe f9a0 bl 80007f4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + 80024b4: 68bb ldr r3, [r7, #8] + 80024b6: f003 0340 and.w r3, r3, #64 @ 0x40 + 80024ba: 2b00 cmp r3, #0 + 80024bc: d00c beq.n 80024d8 + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + 80024be: 68fb ldr r3, [r7, #12] + 80024c0: f003 0340 and.w r3, r3, #64 @ 0x40 + 80024c4: 2b00 cmp r3, #0 + 80024c6: d007 beq.n 80024d8 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); + 80024c8: 687b ldr r3, [r7, #4] + 80024ca: 681b ldr r3, [r3, #0] + 80024cc: f06f 0240 mvn.w r2, #64 @ 0x40 + 80024d0: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 80024d2: 6878 ldr r0, [r7, #4] + 80024d4: f000 f8e6 bl 80026a4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 80024d8: bf00 nop + 80024da: 3710 adds r7, #16 + 80024dc: 46bd mov sp, r7 + 80024de: bd80 pop {r7, pc} + +080024e0 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 80024e0: b580 push {r7, lr} + 80024e2: b084 sub sp, #16 + 80024e4: af00 add r7, sp, #0 + 80024e6: 6078 str r0, [r7, #4] + 80024e8: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 80024ea: 2300 movs r3, #0 + 80024ec: 73fb strb r3, [r7, #15] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 80024ee: 687b ldr r3, [r7, #4] + 80024f0: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 80024f4: 2b01 cmp r3, #1 + 80024f6: d101 bne.n 80024fc + 80024f8: 2302 movs r3, #2 + 80024fa: e0b4 b.n 8002666 + 80024fc: 687b ldr r3, [r7, #4] + 80024fe: 2201 movs r2, #1 + 8002500: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + htim->State = HAL_TIM_STATE_BUSY; + 8002504: 687b ldr r3, [r7, #4] + 8002506: 2202 movs r2, #2 + 8002508: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 800250c: 687b ldr r3, [r7, #4] + 800250e: 681b ldr r3, [r3, #0] + 8002510: 689b ldr r3, [r3, #8] + 8002512: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8002514: 68bb ldr r3, [r7, #8] + 8002516: f023 0377 bic.w r3, r3, #119 @ 0x77 + 800251a: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 800251c: 68bb ldr r3, [r7, #8] + 800251e: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 8002522: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 8002524: 687b ldr r3, [r7, #4] + 8002526: 681b ldr r3, [r3, #0] + 8002528: 68ba ldr r2, [r7, #8] + 800252a: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 800252c: 683b ldr r3, [r7, #0] + 800252e: 681b ldr r3, [r3, #0] + 8002530: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002534: d03e beq.n 80025b4 + 8002536: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 800253a: f200 8087 bhi.w 800264c + 800253e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002542: f000 8086 beq.w 8002652 + 8002546: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800254a: d87f bhi.n 800264c + 800254c: 2b70 cmp r3, #112 @ 0x70 + 800254e: d01a beq.n 8002586 + 8002550: 2b70 cmp r3, #112 @ 0x70 + 8002552: d87b bhi.n 800264c + 8002554: 2b60 cmp r3, #96 @ 0x60 + 8002556: d050 beq.n 80025fa + 8002558: 2b60 cmp r3, #96 @ 0x60 + 800255a: d877 bhi.n 800264c + 800255c: 2b50 cmp r3, #80 @ 0x50 + 800255e: d03c beq.n 80025da + 8002560: 2b50 cmp r3, #80 @ 0x50 + 8002562: d873 bhi.n 800264c + 8002564: 2b40 cmp r3, #64 @ 0x40 + 8002566: d058 beq.n 800261a + 8002568: 2b40 cmp r3, #64 @ 0x40 + 800256a: d86f bhi.n 800264c + 800256c: 2b30 cmp r3, #48 @ 0x30 + 800256e: d064 beq.n 800263a + 8002570: 2b30 cmp r3, #48 @ 0x30 + 8002572: d86b bhi.n 800264c + 8002574: 2b20 cmp r3, #32 + 8002576: d060 beq.n 800263a + 8002578: 2b20 cmp r3, #32 + 800257a: d867 bhi.n 800264c + 800257c: 2b00 cmp r3, #0 + 800257e: d05c beq.n 800263a + 8002580: 2b10 cmp r3, #16 + 8002582: d05a beq.n 800263a + 8002584: e062 b.n 800264c + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 8002586: 687b ldr r3, [r7, #4] + 8002588: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 800258a: 683b ldr r3, [r7, #0] + 800258c: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 800258e: 683b ldr r3, [r7, #0] + 8002590: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002592: 683b ldr r3, [r7, #0] + 8002594: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 8002596: f000 f97c bl 8002892 + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 800259a: 687b ldr r3, [r7, #4] + 800259c: 681b ldr r3, [r3, #0] + 800259e: 689b ldr r3, [r3, #8] + 80025a0: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 80025a2: 68bb ldr r3, [r7, #8] + 80025a4: f043 0377 orr.w r3, r3, #119 @ 0x77 + 80025a8: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 80025aa: 687b ldr r3, [r7, #4] + 80025ac: 681b ldr r3, [r3, #0] + 80025ae: 68ba ldr r2, [r7, #8] + 80025b0: 609a str r2, [r3, #8] + break; + 80025b2: e04f b.n 8002654 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 80025b4: 687b ldr r3, [r7, #4] + 80025b6: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 80025b8: 683b ldr r3, [r7, #0] + 80025ba: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 80025bc: 683b ldr r3, [r7, #0] + 80025be: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 80025c0: 683b ldr r3, [r7, #0] + 80025c2: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 80025c4: f000 f965 bl 8002892 + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 80025c8: 687b ldr r3, [r7, #4] + 80025ca: 681b ldr r3, [r3, #0] + 80025cc: 689a ldr r2, [r3, #8] + 80025ce: 687b ldr r3, [r7, #4] + 80025d0: 681b ldr r3, [r3, #0] + 80025d2: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 80025d6: 609a str r2, [r3, #8] + break; + 80025d8: e03c b.n 8002654 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 80025da: 687b ldr r3, [r7, #4] + 80025dc: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80025de: 683b ldr r3, [r7, #0] + 80025e0: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80025e2: 683b ldr r3, [r7, #0] + 80025e4: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 80025e6: 461a mov r2, r3 + 80025e8: f000 f8dc bl 80027a4 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 80025ec: 687b ldr r3, [r7, #4] + 80025ee: 681b ldr r3, [r3, #0] + 80025f0: 2150 movs r1, #80 @ 0x50 + 80025f2: 4618 mov r0, r3 + 80025f4: f000 f933 bl 800285e + break; + 80025f8: e02c b.n 8002654 + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 80025fa: 687b ldr r3, [r7, #4] + 80025fc: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80025fe: 683b ldr r3, [r7, #0] + 8002600: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002602: 683b ldr r3, [r7, #0] + 8002604: 68db ldr r3, [r3, #12] + TIM_TI2_ConfigInputStage(htim->Instance, + 8002606: 461a mov r2, r3 + 8002608: f000 f8fa bl 8002800 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 800260c: 687b ldr r3, [r7, #4] + 800260e: 681b ldr r3, [r3, #0] + 8002610: 2160 movs r1, #96 @ 0x60 + 8002612: 4618 mov r0, r3 + 8002614: f000 f923 bl 800285e + break; + 8002618: e01c b.n 8002654 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 800261a: 687b ldr r3, [r7, #4] + 800261c: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 800261e: 683b ldr r3, [r7, #0] + 8002620: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002622: 683b ldr r3, [r7, #0] + 8002624: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 8002626: 461a mov r2, r3 + 8002628: f000 f8bc bl 80027a4 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 800262c: 687b ldr r3, [r7, #4] + 800262e: 681b ldr r3, [r3, #0] + 8002630: 2140 movs r1, #64 @ 0x40 + 8002632: 4618 mov r0, r3 + 8002634: f000 f913 bl 800285e + break; + 8002638: e00c b.n 8002654 + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 800263a: 687b ldr r3, [r7, #4] + 800263c: 681a ldr r2, [r3, #0] + 800263e: 683b ldr r3, [r7, #0] + 8002640: 681b ldr r3, [r3, #0] + 8002642: 4619 mov r1, r3 + 8002644: 4610 mov r0, r2 + 8002646: f000 f90a bl 800285e + break; + 800264a: e003 b.n 8002654 + } + + default: + status = HAL_ERROR; + 800264c: 2301 movs r3, #1 + 800264e: 73fb strb r3, [r7, #15] + break; + 8002650: e000 b.n 8002654 + break; + 8002652: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8002654: 687b ldr r3, [r7, #4] + 8002656: 2201 movs r2, #1 + 8002658: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 800265c: 687b ldr r3, [r7, #4] + 800265e: 2200 movs r2, #0 + 8002660: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 8002664: 7bfb ldrb r3, [r7, #15] +} + 8002666: 4618 mov r0, r3 + 8002668: 3710 adds r7, #16 + 800266a: 46bd mov sp, r7 + 800266c: bd80 pop {r7, pc} + +0800266e : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 800266e: b480 push {r7} + 8002670: b083 sub sp, #12 + 8002672: af00 add r7, sp, #0 + 8002674: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 8002676: bf00 nop + 8002678: 370c adds r7, #12 + 800267a: 46bd mov sp, r7 + 800267c: bc80 pop {r7} + 800267e: 4770 bx lr + +08002680 : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 8002680: b480 push {r7} + 8002682: b083 sub sp, #12 + 8002684: af00 add r7, sp, #0 + 8002686: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8002688: bf00 nop + 800268a: 370c adds r7, #12 + 800268c: 46bd mov sp, r7 + 800268e: bc80 pop {r7} + 8002690: 4770 bx lr + +08002692 : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8002692: b480 push {r7} + 8002694: b083 sub sp, #12 + 8002696: af00 add r7, sp, #0 + 8002698: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 800269a: bf00 nop + 800269c: 370c adds r7, #12 + 800269e: 46bd mov sp, r7 + 80026a0: bc80 pop {r7} + 80026a2: 4770 bx lr + +080026a4 : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 80026a4: b480 push {r7} + 80026a6: b083 sub sp, #12 + 80026a8: af00 add r7, sp, #0 + 80026aa: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 80026ac: bf00 nop + 80026ae: 370c adds r7, #12 + 80026b0: 46bd mov sp, r7 + 80026b2: bc80 pop {r7} + 80026b4: 4770 bx lr + ... + +080026b8 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 80026b8: b480 push {r7} + 80026ba: b085 sub sp, #20 + 80026bc: af00 add r7, sp, #0 + 80026be: 6078 str r0, [r7, #4] + 80026c0: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 80026c2: 687b ldr r3, [r7, #4] + 80026c4: 681b ldr r3, [r3, #0] + 80026c6: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 80026c8: 687b ldr r3, [r7, #4] + 80026ca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80026ce: d00f beq.n 80026f0 + 80026d0: 687b ldr r3, [r7, #4] + 80026d2: 4a2e ldr r2, [pc, #184] @ (800278c ) + 80026d4: 4293 cmp r3, r2 + 80026d6: d00b beq.n 80026f0 + 80026d8: 687b ldr r3, [r7, #4] + 80026da: 4a2d ldr r2, [pc, #180] @ (8002790 ) + 80026dc: 4293 cmp r3, r2 + 80026de: d007 beq.n 80026f0 + 80026e0: 687b ldr r3, [r7, #4] + 80026e2: 4a2c ldr r2, [pc, #176] @ (8002794 ) + 80026e4: 4293 cmp r3, r2 + 80026e6: d003 beq.n 80026f0 + 80026e8: 687b ldr r3, [r7, #4] + 80026ea: 4a2b ldr r2, [pc, #172] @ (8002798 ) + 80026ec: 4293 cmp r3, r2 + 80026ee: d108 bne.n 8002702 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 80026f0: 68fb ldr r3, [r7, #12] + 80026f2: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80026f6: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 80026f8: 683b ldr r3, [r7, #0] + 80026fa: 685b ldr r3, [r3, #4] + 80026fc: 68fa ldr r2, [r7, #12] + 80026fe: 4313 orrs r3, r2 + 8002700: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8002702: 687b ldr r3, [r7, #4] + 8002704: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002708: d017 beq.n 800273a + 800270a: 687b ldr r3, [r7, #4] + 800270c: 4a1f ldr r2, [pc, #124] @ (800278c ) + 800270e: 4293 cmp r3, r2 + 8002710: d013 beq.n 800273a + 8002712: 687b ldr r3, [r7, #4] + 8002714: 4a1e ldr r2, [pc, #120] @ (8002790 ) + 8002716: 4293 cmp r3, r2 + 8002718: d00f beq.n 800273a + 800271a: 687b ldr r3, [r7, #4] + 800271c: 4a1d ldr r2, [pc, #116] @ (8002794 ) + 800271e: 4293 cmp r3, r2 + 8002720: d00b beq.n 800273a + 8002722: 687b ldr r3, [r7, #4] + 8002724: 4a1c ldr r2, [pc, #112] @ (8002798 ) + 8002726: 4293 cmp r3, r2 + 8002728: d007 beq.n 800273a + 800272a: 687b ldr r3, [r7, #4] + 800272c: 4a1b ldr r2, [pc, #108] @ (800279c ) + 800272e: 4293 cmp r3, r2 + 8002730: d003 beq.n 800273a + 8002732: 687b ldr r3, [r7, #4] + 8002734: 4a1a ldr r2, [pc, #104] @ (80027a0 ) + 8002736: 4293 cmp r3, r2 + 8002738: d108 bne.n 800274c + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 800273a: 68fb ldr r3, [r7, #12] + 800273c: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002740: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8002742: 683b ldr r3, [r7, #0] + 8002744: 68db ldr r3, [r3, #12] + 8002746: 68fa ldr r2, [r7, #12] + 8002748: 4313 orrs r3, r2 + 800274a: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 800274c: 68fb ldr r3, [r7, #12] + 800274e: f023 0280 bic.w r2, r3, #128 @ 0x80 + 8002752: 683b ldr r3, [r7, #0] + 8002754: 691b ldr r3, [r3, #16] + 8002756: 4313 orrs r3, r2 + 8002758: 60fb str r3, [r7, #12] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 800275a: 683b ldr r3, [r7, #0] + 800275c: 689a ldr r2, [r3, #8] + 800275e: 687b ldr r3, [r7, #4] + 8002760: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8002762: 683b ldr r3, [r7, #0] + 8002764: 681a ldr r2, [r3, #0] + 8002766: 687b ldr r3, [r7, #4] + 8002768: 629a str r2, [r3, #40] @ 0x28 + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + 800276a: 687b ldr r3, [r7, #4] + 800276c: 681b ldr r3, [r3, #0] + 800276e: f043 0204 orr.w r2, r3, #4 + 8002772: 687b ldr r3, [r7, #4] + 8002774: 601a str r2, [r3, #0] + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8002776: 687b ldr r3, [r7, #4] + 8002778: 2201 movs r2, #1 + 800277a: 615a str r2, [r3, #20] + + TIMx->CR1 = tmpcr1; + 800277c: 687b ldr r3, [r7, #4] + 800277e: 68fa ldr r2, [r7, #12] + 8002780: 601a str r2, [r3, #0] +} + 8002782: bf00 nop + 8002784: 3714 adds r7, #20 + 8002786: 46bd mov sp, r7 + 8002788: bc80 pop {r7} + 800278a: 4770 bx lr + 800278c: 40000400 .word 0x40000400 + 8002790: 40000800 .word 0x40000800 + 8002794: 40000c00 .word 0x40000c00 + 8002798: 40010800 .word 0x40010800 + 800279c: 40010c00 .word 0x40010c00 + 80027a0: 40011000 .word 0x40011000 + +080027a4 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 80027a4: b480 push {r7} + 80027a6: b087 sub sp, #28 + 80027a8: af00 add r7, sp, #0 + 80027aa: 60f8 str r0, [r7, #12] + 80027ac: 60b9 str r1, [r7, #8] + 80027ae: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 80027b0: 68fb ldr r3, [r7, #12] + 80027b2: 6a1b ldr r3, [r3, #32] + 80027b4: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 80027b6: 68fb ldr r3, [r7, #12] + 80027b8: 6a1b ldr r3, [r3, #32] + 80027ba: f023 0201 bic.w r2, r3, #1 + 80027be: 68fb ldr r3, [r7, #12] + 80027c0: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 80027c2: 68fb ldr r3, [r7, #12] + 80027c4: 699b ldr r3, [r3, #24] + 80027c6: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 80027c8: 693b ldr r3, [r7, #16] + 80027ca: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 80027ce: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 80027d0: 687b ldr r3, [r7, #4] + 80027d2: 011b lsls r3, r3, #4 + 80027d4: 693a ldr r2, [r7, #16] + 80027d6: 4313 orrs r3, r2 + 80027d8: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 80027da: 697b ldr r3, [r7, #20] + 80027dc: f023 030a bic.w r3, r3, #10 + 80027e0: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 80027e2: 697a ldr r2, [r7, #20] + 80027e4: 68bb ldr r3, [r7, #8] + 80027e6: 4313 orrs r3, r2 + 80027e8: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 80027ea: 68fb ldr r3, [r7, #12] + 80027ec: 693a ldr r2, [r7, #16] + 80027ee: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 80027f0: 68fb ldr r3, [r7, #12] + 80027f2: 697a ldr r2, [r7, #20] + 80027f4: 621a str r2, [r3, #32] +} + 80027f6: bf00 nop + 80027f8: 371c adds r7, #28 + 80027fa: 46bd mov sp, r7 + 80027fc: bc80 pop {r7} + 80027fe: 4770 bx lr + +08002800 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002800: b480 push {r7} + 8002802: b087 sub sp, #28 + 8002804: af00 add r7, sp, #0 + 8002806: 60f8 str r0, [r7, #12] + 8002808: 60b9 str r1, [r7, #8] + 800280a: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + 800280c: 68fb ldr r3, [r7, #12] + 800280e: 6a1b ldr r3, [r3, #32] + 8002810: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002812: 68fb ldr r3, [r7, #12] + 8002814: 6a1b ldr r3, [r3, #32] + 8002816: f023 0210 bic.w r2, r3, #16 + 800281a: 68fb ldr r3, [r7, #12] + 800281c: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 800281e: 68fb ldr r3, [r7, #12] + 8002820: 699b ldr r3, [r3, #24] + 8002822: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8002824: 693b ldr r3, [r7, #16] + 8002826: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 800282a: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 12U); + 800282c: 687b ldr r3, [r7, #4] + 800282e: 031b lsls r3, r3, #12 + 8002830: 693a ldr r2, [r7, #16] + 8002832: 4313 orrs r3, r2 + 8002834: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8002836: 697b ldr r3, [r7, #20] + 8002838: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 800283c: 617b str r3, [r7, #20] + tmpccer |= (TIM_ICPolarity << 4U); + 800283e: 68bb ldr r3, [r7, #8] + 8002840: 011b lsls r3, r3, #4 + 8002842: 697a ldr r2, [r7, #20] + 8002844: 4313 orrs r3, r2 + 8002846: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 8002848: 68fb ldr r3, [r7, #12] + 800284a: 693a ldr r2, [r7, #16] + 800284c: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 800284e: 68fb ldr r3, [r7, #12] + 8002850: 697a ldr r2, [r7, #20] + 8002852: 621a str r2, [r3, #32] +} + 8002854: bf00 nop + 8002856: 371c adds r7, #28 + 8002858: 46bd mov sp, r7 + 800285a: bc80 pop {r7} + 800285c: 4770 bx lr + +0800285e : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 800285e: b480 push {r7} + 8002860: b085 sub sp, #20 + 8002862: af00 add r7, sp, #0 + 8002864: 6078 str r0, [r7, #4] + 8002866: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8002868: 687b ldr r3, [r7, #4] + 800286a: 689b ldr r3, [r3, #8] + 800286c: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 800286e: 68fb ldr r3, [r7, #12] + 8002870: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002874: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8002876: 683a ldr r2, [r7, #0] + 8002878: 68fb ldr r3, [r7, #12] + 800287a: 4313 orrs r3, r2 + 800287c: f043 0307 orr.w r3, r3, #7 + 8002880: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8002882: 687b ldr r3, [r7, #4] + 8002884: 68fa ldr r2, [r7, #12] + 8002886: 609a str r2, [r3, #8] +} + 8002888: bf00 nop + 800288a: 3714 adds r7, #20 + 800288c: 46bd mov sp, r7 + 800288e: bc80 pop {r7} + 8002890: 4770 bx lr + +08002892 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8002892: b480 push {r7} + 8002894: b087 sub sp, #28 + 8002896: af00 add r7, sp, #0 + 8002898: 60f8 str r0, [r7, #12] + 800289a: 60b9 str r1, [r7, #8] + 800289c: 607a str r2, [r7, #4] + 800289e: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 80028a0: 68fb ldr r3, [r7, #12] + 80028a2: 689b ldr r3, [r3, #8] + 80028a4: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 80028a6: 697b ldr r3, [r7, #20] + 80028a8: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 80028ac: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 80028ae: 683b ldr r3, [r7, #0] + 80028b0: 021a lsls r2, r3, #8 + 80028b2: 687b ldr r3, [r7, #4] + 80028b4: 431a orrs r2, r3 + 80028b6: 68bb ldr r3, [r7, #8] + 80028b8: 4313 orrs r3, r2 + 80028ba: 697a ldr r2, [r7, #20] + 80028bc: 4313 orrs r3, r2 + 80028be: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 80028c0: 68fb ldr r3, [r7, #12] + 80028c2: 697a ldr r2, [r7, #20] + 80028c4: 609a str r2, [r3, #8] +} + 80028c6: bf00 nop + 80028c8: 371c adds r7, #28 + 80028ca: 46bd mov sp, r7 + 80028cc: bc80 pop {r7} + 80028ce: 4770 bx lr + +080028d0 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + 80028d0: b480 push {r7} + 80028d2: b085 sub sp, #20 + 80028d4: af00 add r7, sp, #0 + 80028d6: 6078 str r0, [r7, #4] + 80028d8: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 80028da: 687b ldr r3, [r7, #4] + 80028dc: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 80028e0: 2b01 cmp r3, #1 + 80028e2: d101 bne.n 80028e8 + 80028e4: 2302 movs r3, #2 + 80028e6: e046 b.n 8002976 + 80028e8: 687b ldr r3, [r7, #4] + 80028ea: 2201 movs r2, #1 + 80028ec: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 80028f0: 687b ldr r3, [r7, #4] + 80028f2: 2202 movs r2, #2 + 80028f4: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 80028f8: 687b ldr r3, [r7, #4] + 80028fa: 681b ldr r3, [r3, #0] + 80028fc: 685b ldr r3, [r3, #4] + 80028fe: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8002900: 687b ldr r3, [r7, #4] + 8002902: 681b ldr r3, [r3, #0] + 8002904: 689b ldr r3, [r3, #8] + 8002906: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8002908: 68fb ldr r3, [r7, #12] + 800290a: f023 0370 bic.w r3, r3, #112 @ 0x70 + 800290e: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8002910: 683b ldr r3, [r7, #0] + 8002912: 681b ldr r3, [r3, #0] + 8002914: 68fa ldr r2, [r7, #12] + 8002916: 4313 orrs r3, r2 + 8002918: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 800291a: 687b ldr r3, [r7, #4] + 800291c: 681b ldr r3, [r3, #0] + 800291e: 68fa ldr r2, [r7, #12] + 8002920: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8002922: 687b ldr r3, [r7, #4] + 8002924: 681b ldr r3, [r3, #0] + 8002926: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 800292a: d00e beq.n 800294a + 800292c: 687b ldr r3, [r7, #4] + 800292e: 681b ldr r3, [r3, #0] + 8002930: 4a13 ldr r2, [pc, #76] @ (8002980 ) + 8002932: 4293 cmp r3, r2 + 8002934: d009 beq.n 800294a + 8002936: 687b ldr r3, [r7, #4] + 8002938: 681b ldr r3, [r3, #0] + 800293a: 4a12 ldr r2, [pc, #72] @ (8002984 ) + 800293c: 4293 cmp r3, r2 + 800293e: d004 beq.n 800294a + 8002940: 687b ldr r3, [r7, #4] + 8002942: 681b ldr r3, [r3, #0] + 8002944: 4a10 ldr r2, [pc, #64] @ (8002988 ) + 8002946: 4293 cmp r3, r2 + 8002948: d10c bne.n 8002964 + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 800294a: 68bb ldr r3, [r7, #8] + 800294c: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8002950: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8002952: 683b ldr r3, [r7, #0] + 8002954: 685b ldr r3, [r3, #4] + 8002956: 68ba ldr r2, [r7, #8] + 8002958: 4313 orrs r3, r2 + 800295a: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 800295c: 687b ldr r3, [r7, #4] + 800295e: 681b ldr r3, [r3, #0] + 8002960: 68ba ldr r2, [r7, #8] + 8002962: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8002964: 687b ldr r3, [r7, #4] + 8002966: 2201 movs r2, #1 + 8002968: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 800296c: 687b ldr r3, [r7, #4] + 800296e: 2200 movs r2, #0 + 8002970: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return HAL_OK; + 8002974: 2300 movs r3, #0 +} + 8002976: 4618 mov r0, r3 + 8002978: 3714 adds r7, #20 + 800297a: 46bd mov sp, r7 + 800297c: bc80 pop {r7} + 800297e: 4770 bx lr + 8002980: 40000400 .word 0x40000400 + 8002984: 40000800 .word 0x40000800 + 8002988: 40010800 .word 0x40010800 + +0800298c : + 800298c: 4603 mov r3, r0 + 800298e: 4402 add r2, r0 + 8002990: 4293 cmp r3, r2 + 8002992: d100 bne.n 8002996 + 8002994: 4770 bx lr + 8002996: f803 1b01 strb.w r1, [r3], #1 + 800299a: e7f9 b.n 8002990 + +0800299c <__libc_init_array>: + 800299c: b570 push {r4, r5, r6, lr} + 800299e: 2600 movs r6, #0 + 80029a0: 4d0c ldr r5, [pc, #48] @ (80029d4 <__libc_init_array+0x38>) + 80029a2: 4c0d ldr r4, [pc, #52] @ (80029d8 <__libc_init_array+0x3c>) + 80029a4: 1b64 subs r4, r4, r5 + 80029a6: 10a4 asrs r4, r4, #2 + 80029a8: 42a6 cmp r6, r4 + 80029aa: d109 bne.n 80029c0 <__libc_init_array+0x24> + 80029ac: f000 f81a bl 80029e4 <_init> + 80029b0: 2600 movs r6, #0 + 80029b2: 4d0a ldr r5, [pc, #40] @ (80029dc <__libc_init_array+0x40>) + 80029b4: 4c0a ldr r4, [pc, #40] @ (80029e0 <__libc_init_array+0x44>) + 80029b6: 1b64 subs r4, r4, r5 + 80029b8: 10a4 asrs r4, r4, #2 + 80029ba: 42a6 cmp r6, r4 + 80029bc: d105 bne.n 80029ca <__libc_init_array+0x2e> + 80029be: bd70 pop {r4, r5, r6, pc} + 80029c0: f855 3b04 ldr.w r3, [r5], #4 + 80029c4: 4798 blx r3 + 80029c6: 3601 adds r6, #1 + 80029c8: e7ee b.n 80029a8 <__libc_init_array+0xc> + 80029ca: f855 3b04 ldr.w r3, [r5], #4 + 80029ce: 4798 blx r3 + 80029d0: 3601 adds r6, #1 + 80029d2: e7f2 b.n 80029ba <__libc_init_array+0x1e> + 80029d4: 08002a30 .word 0x08002a30 + 80029d8: 08002a30 .word 0x08002a30 + 80029dc: 08002a30 .word 0x08002a30 + 80029e0: 08002a34 .word 0x08002a34 + +080029e4 <_init>: + 80029e4: b5f8 push {r3, r4, r5, r6, r7, lr} + 80029e6: bf00 nop + 80029e8: bcf8 pop {r3, r4, r5, r6, r7} + 80029ea: bc08 pop {r3} + 80029ec: 469e mov lr, r3 + 80029ee: 4770 bx lr + +080029f0 <_fini>: + 80029f0: b5f8 push {r3, r4, r5, r6, r7, lr} + 80029f2: bf00 nop + 80029f4: bcf8 pop {r3, r4, r5, r6, r7} + 80029f6: bc08 pop {r3} + 80029f8: 469e mov lr, r3 + 80029fa: 4770 bx lr diff --git a/TP4_INIT_TFT/Debug/TP3_M_A_TIMER_MODULO.map b/TP4_INIT_TFT/Debug/TP3_M_A_TIMER_MODULO.map new file mode 100644 index 0000000..f327511 --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP3_M_A_TIMER_MODULO.map @@ -0,0 +1,3420 @@ +Archive member included to satisfy reference by file (symbol) + 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o +START GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libm.a +END GROUP +START GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a +LOAD 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g_pfnVectors + 0x0800013c . = ALIGN (0x4) + +.text 0x0800013c 0x28c0 + 0x0800013c . = ALIGN (0x4) + *(.text) + .text 0x0800013c 0x40 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + .text 0x0800017c 0x30 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x0800017c __aeabi_uldivmod + .text 0x080001ac 0x300 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + 0x080001ac __udivmoddi4 + .text 0x080004ac 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_dvmd_tls.o) + 0x080004ac __aeabi_ldiv0 + 0x080004ac __aeabi_idiv0 + *(.text*) + .text.affiche 0x080004b0 0x60 ./Core/Src/main.o + 0x080004b0 affiche + .text.main 0x08000510 0x6c ./Core/Src/main.o + 0x08000510 main + .text.SystemClock_Config + 0x0800057c 0x8c ./Core/Src/main.o + 0x0800057c SystemClock_Config + .text.MX_SPI1_Init + 0x08000608 0x6c ./Core/Src/main.o + .text.MX_TIM2_Init + 0x08000674 0x9c ./Core/Src/main.o + .text.MX_GPIO_Init + 0x08000710 0xac ./Core/Src/main.o + .text.HAL_GPIO_EXTI_Callback + 0x080007bc 0x38 ./Core/Src/main.o + 0x080007bc HAL_GPIO_EXTI_Callback + .text.HAL_TIM_PeriodElapsedCallback + 0x080007f4 0x28 ./Core/Src/main.o + 0x080007f4 HAL_TIM_PeriodElapsedCallback + .text.Error_Handler + 0x0800081c 0xc ./Core/Src/main.o + 0x0800081c Error_Handler + .text.HAL_MspInit + 0x08000828 0x5c ./Core/Src/stm32l1xx_hal_msp.o + 0x08000828 HAL_MspInit + .text.HAL_SPI_MspInit + 0x08000884 0x88 ./Core/Src/stm32l1xx_hal_msp.o + 0x08000884 HAL_SPI_MspInit + .text.HAL_TIM_Base_MspInit + 0x0800090c 0x48 ./Core/Src/stm32l1xx_hal_msp.o + 0x0800090c HAL_TIM_Base_MspInit + .text.NMI_Handler + 0x08000954 0x8 ./Core/Src/stm32l1xx_it.o + 0x08000954 NMI_Handler + .text.HardFault_Handler + 0x0800095c 0x8 ./Core/Src/stm32l1xx_it.o + 0x0800095c HardFault_Handler + .text.MemManage_Handler + 0x08000964 0x8 ./Core/Src/stm32l1xx_it.o + 0x08000964 MemManage_Handler + .text.BusFault_Handler + 0x0800096c 0x8 ./Core/Src/stm32l1xx_it.o + 0x0800096c BusFault_Handler + .text.UsageFault_Handler + 0x08000974 0x8 ./Core/Src/stm32l1xx_it.o + 0x08000974 UsageFault_Handler + .text.SVC_Handler + 0x0800097c 0xc ./Core/Src/stm32l1xx_it.o + 0x0800097c SVC_Handler + .text.DebugMon_Handler + 0x08000988 0xc ./Core/Src/stm32l1xx_it.o + 0x08000988 DebugMon_Handler + .text.PendSV_Handler + 0x08000994 0xc ./Core/Src/stm32l1xx_it.o + 0x08000994 PendSV_Handler + .text.SysTick_Handler + 0x080009a0 0xc ./Core/Src/stm32l1xx_it.o + 0x080009a0 SysTick_Handler + .text.TIM2_IRQHandler + 0x080009ac 0x14 ./Core/Src/stm32l1xx_it.o + 0x080009ac TIM2_IRQHandler + .text.EXTI15_10_IRQHandler + 0x080009c0 0x18 ./Core/Src/stm32l1xx_it.o + 0x080009c0 EXTI15_10_IRQHandler + .text.SystemInit + 0x080009d8 0xc ./Core/Src/system_stm32l1xx.o + 0x080009d8 SystemInit + .text.Reset_Handler + 0x080009e4 0x48 ./Core/Startup/startup_stm32l152retx.o + 0x080009e4 Reset_Handler + .text.Default_Handler + 0x08000a2c 0x2 ./Core/Startup/startup_stm32l152retx.o + 0x08000a2c DMA2_Channel3_IRQHandler + 0x08000a2c EXTI2_IRQHandler + 0x08000a2c COMP_ACQ_IRQHandler + 0x08000a2c TIM10_IRQHandler + 0x08000a2c USB_HP_IRQHandler + 0x08000a2c TIM6_IRQHandler + 0x08000a2c PVD_IRQHandler + 0x08000a2c EXTI3_IRQHandler + 0x08000a2c EXTI0_IRQHandler + 0x08000a2c I2C2_EV_IRQHandler + 0x08000a2c SPI1_IRQHandler + 0x08000a2c USB_FS_WKUP_IRQHandler + 0x08000a2c DMA2_Channel2_IRQHandler + 0x08000a2c DMA1_Channel4_IRQHandler + 0x08000a2c ADC1_IRQHandler + 0x08000a2c USART3_IRQHandler + 0x08000a2c DMA1_Channel7_IRQHandler + 0x08000a2c LCD_IRQHandler + 0x08000a2c UART5_IRQHandler + 0x08000a2c TIM4_IRQHandler + 0x08000a2c DMA2_Channel1_IRQHandler + 0x08000a2c I2C1_EV_IRQHandler + 0x08000a2c DMA1_Channel6_IRQHandler + 0x08000a2c UART4_IRQHandler + 0x08000a2c DMA2_Channel4_IRQHandler + 0x08000a2c TIM3_IRQHandler + 0x08000a2c RCC_IRQHandler + 0x08000a2c DMA1_Channel1_IRQHandler + 0x08000a2c Default_Handler + 0x08000a2c TIM7_IRQHandler + 0x08000a2c TIM5_IRQHandler + 0x08000a2c EXTI9_5_IRQHandler + 0x08000a2c TIM9_IRQHandler + 0x08000a2c TAMPER_STAMP_IRQHandler + 0x08000a2c RTC_WKUP_IRQHandler + 0x08000a2c SPI2_IRQHandler + 0x08000a2c DMA2_Channel5_IRQHandler + 0x08000a2c DMA1_Channel5_IRQHandler + 0x08000a2c USB_LP_IRQHandler + 0x08000a2c EXTI4_IRQHandler + 0x08000a2c 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0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.__NVIC_SetPriority + 0x08000ccc 0x54 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.NVIC_EncodePriority + 0x08000d20 0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.SysTick_Config + 0x08000d84 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x08000dc8 0x16 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000dc8 HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x08000dde 0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000dde HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x08000e16 0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000e16 HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x08000e32 0x18 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000e32 HAL_SYSTICK_Config + *fill* 0x08000e4a 0x2 + .text.HAL_GPIO_Init + 0x08000e4c 0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000e4c HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x0800116c 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0800116c HAL_GPIO_WritePin + .text.HAL_GPIO_EXTI_IRQHandler + 0x0800119c 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0800119c HAL_GPIO_EXTI_IRQHandler + .text.HAL_RCC_OscConfig + 0x080011cc 0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x080011cc HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x0800182c 0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0800182c HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x08001a94 0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08001a94 HAL_RCC_GetSysClockFreq + .text.RCC_SetFlashLatencyFromMSIRange + 0x08001c10 0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .text.HAL_SPI_Init + 0x08001cd0 0x112 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001cd0 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_aranges + 0x000002b8 0x128 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_aranges + 0x000003e0 0x58 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_aranges + 0x00000438 0x90 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_aranges + 0x000004c8 0x1d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_aranges + 0x00000698 0x3d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_aranges + 0x00000a68 0x28 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_rnglists + 0x00000000 0x801 + .debug_rnglists + 0x00000000 0x46 ./Core/Src/main.o + .debug_rnglists + 0x00000046 0x2c ./Core/Src/stm32l1xx_hal_msp.o + .debug_rnglists + 0x00000072 0x4f ./Core/Src/stm32l1xx_it.o + .debug_rnglists + 0x000000c1 0x1a ./Core/Src/system_stm32l1xx.o + .debug_rnglists + 0x000000db 0x19 ./Core/Startup/startup_stm32l152retx.o + .debug_rnglists + 0x000000f4 0x55 ./Drivers/7Seg_MAX7219/max7219.o + .debug_rnglists + 0x00000149 0xa3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_rnglists + 0x000001ec 0xd9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_rnglists + 0x000002c5 0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_rnglists + 0x00000304 0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_rnglists + 0x00000371 0x16f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_rnglists + 0x000004e0 0x307 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_rnglists + 0x000007e7 0x1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_macro 0x00000000 0x155f9 + .debug_macro 0x00000000 0x1c2 ./Core/Src/main.o + .debug_macro 0x000001c2 0xacc ./Core/Src/main.o + .debug_macro 0x00000c8e 0x10f ./Core/Src/main.o + .debug_macro 0x00000d9d 0x2e ./Core/Src/main.o + .debug_macro 0x00000dcb 0x22 ./Core/Src/main.o + .debug_macro 0x00000ded 0x22 ./Core/Src/main.o + .debug_macro 0x00000e0f 0x8e ./Core/Src/main.o + .debug_macro 0x00000e9d 0x51 ./Core/Src/main.o + .debug_macro 0x00000eee 0x103 ./Core/Src/main.o + .debug_macro 0x00000ff1 0x6a ./Core/Src/main.o + .debug_macro 0x0000105b 0x1df ./Core/Src/main.o + .debug_macro 0x0000123a 0x1c ./Core/Src/main.o + .debug_macro 0x00001256 0x22 ./Core/Src/main.o + .debug_macro 0x00001278 0xbd ./Core/Src/main.o + .debug_macro 0x00001335 0xe49 ./Core/Src/main.o + .debug_macro 0x0000217e 0x11f ./Core/Src/main.o + .debug_macro 0x0000229d 0xb7a1 ./Core/Src/main.o + .debug_macro 0x0000da3e 0x6d ./Core/Src/main.o + .debug_macro 0x0000daab 0x34e1 ./Core/Src/main.o + .debug_macro 0x00010f8c 0x190 ./Core/Src/main.o + .debug_macro 0x0001111c 0x5b ./Core/Src/main.o + .debug_macro 0x00011177 0xe37 ./Core/Src/main.o + .debug_macro 0x00011fae 0x35b ./Core/Src/main.o + .debug_macro 0x00012309 0x1b8 ./Core/Src/main.o + .debug_macro 0x000124c1 0xc5 ./Core/Src/main.o + .debug_macro 0x00012586 0x21e ./Core/Src/main.o + .debug_macro 0x000127a4 0x236 ./Core/Src/main.o + .debug_macro 0x000129da 0x115 ./Core/Src/main.o + .debug_macro 0x00012aef 0x567 ./Core/Src/main.o + .debug_macro 0x00013056 0x1e9 ./Core/Src/main.o + .debug_macro 0x0001323f 0x22 ./Core/Src/main.o + .debug_macro 0x00013261 0x225 ./Core/Src/main.o + .debug_macro 0x00013486 0x788 ./Core/Src/main.o + .debug_macro 0x00013c0e 0xac ./Core/Src/main.o + .debug_macro 0x00013cba 0x170 ./Core/Src/main.o + .debug_macro 0x00013e2a 0x492 ./Core/Src/main.o + .debug_macro 0x000142bc 0x10 ./Core/Src/main.o + .debug_macro 0x000142cc 0x1b9 ./Core/Src/stm32l1xx_hal_msp.o + .debug_macro 0x00014485 0x1c3 ./Core/Src/stm32l1xx_it.o + .debug_macro 0x00014648 0x1af ./Core/Src/system_stm32l1xx.o + .debug_macro 0x000147f7 0x1ec ./Drivers/7Seg_MAX7219/max7219.o + .debug_macro 0x000149e3 0x1d3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_macro 0x00014bb6 0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_macro 0x00014d65 0x1b6 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_macro 0x00014f1b 0x1c1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_macro 0x000150dc 0x1be ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_macro 0x0001529a 0x1b0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_macro 0x0001544a 0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_line 0x00000000 0xa9e1 + .debug_line 0x00000000 0x8b4 ./Core/Src/main.o + .debug_line 0x000008b4 0x749 ./Core/Src/stm32l1xx_hal_msp.o + .debug_line 0x00000ffd 0x7a0 ./Core/Src/stm32l1xx_it.o + .debug_line 0x0000179d 0x761 ./Core/Src/system_stm32l1xx.o + .debug_line 0x00001efe 0x79 ./Core/Startup/startup_stm32l152retx.o + .debug_line 0x00001f77 0x80f ./Drivers/7Seg_MAX7219/max7219.o + .debug_line 0x00002786 0x98c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_line 0x00003112 0xc5b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_line 0x00003d6d 0x9d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_line 0x0000473d 0xf4f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_line 0x0000568c 0x1c4b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_line 0x000072d7 0x2fb1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_line 0x0000a288 0x759 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_str 0x00000000 0x88678 + .debug_str 0x00000000 0x88678 ./Core/Src/main.o + 0x8677f (size before relaxing) + .debug_str 0x00088678 0x863cd ./Core/Src/stm32l1xx_hal_msp.o + .debug_str 0x00088678 0x85dde ./Core/Src/stm32l1xx_it.o + .debug_str 0x00088678 0x8590b ./Core/Src/system_stm32l1xx.o + .debug_str 0x00088678 0x8c ./Core/Startup/startup_stm32l152retx.o + .debug_str 0x00088678 0x85e67 ./Drivers/7Seg_MAX7219/max7219.o + .debug_str 0x00088678 0x86033 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_str 0x00088678 0x8613f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_str 0x00088678 0x85a9e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_str 0x00088678 0x85dc7 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_str 0x00088678 0x8622d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_str 0x00088678 0x86c0e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_str 0x00088678 0x85db3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Core/Src/main.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_hal_msp.o + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_it.o + .comment 0x00000043 0x44 ./Core/Src/system_stm32l1xx.o + .comment 0x00000043 0x44 ./Drivers/7Seg_MAX7219/max7219.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_frame 0x00000000 0x2bb4 + .debug_frame 0x00000000 0x144 ./Core/Src/main.o + .debug_frame 0x00000144 0xc8 ./Core/Src/stm32l1xx_hal_msp.o + .debug_frame 0x0000020c 0x13c ./Core/Src/stm32l1xx_it.o + .debug_frame 0x00000348 0x58 ./Core/Src/system_stm32l1xx.o + .debug_frame 0x000003a0 0x198 ./Drivers/7Seg_MAX7219/max7219.o + .debug_frame 0x00000538 0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_frame 0x00000874 0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_frame 0x00000d5c 0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_frame 0x00000ea8 0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_frame 0x000010cc 0x828 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_frame 0x000018f4 0x11b4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_frame 0x00002aa8 0x60 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + .debug_frame 0x00002b08 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00002b28 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .debug_frame 0x00002b54 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00002b80 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x70 + .debug_line_str + 0x00000000 0x70 ./Core/Startup/startup_stm32l152retx.o diff --git a/TP4_INIT_TFT/Debug/TP3_PWM_GENERATOR.list b/TP4_INIT_TFT/Debug/TP3_PWM_GENERATOR.list new file mode 100644 index 0000000..94b8a8a --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP3_PWM_GENERATOR.list @@ -0,0 +1,8291 @@ + +TP3_PWM_GENERATOR.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00002e30 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000001c 08002f6c 08002f6c 00003f6c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08002f88 08002f88 0000400c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08002f88 08002f88 00003f88 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08002f90 08002f90 0000400c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08002f90 08002f90 00003f90 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 08002f94 08002f94 00003f94 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000000c 20000000 08002f98 00004000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000000f8 2000000c 08002fa4 0000400c 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20000104 08002fa4 00004104 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0 + CONTENTS, READONLY + 12 .debug_info 000097ec 00000000 00000000 00004035 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 000019a3 00000000 00000000 0000d821 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000a90 00000000 00000000 0000f1c8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 00000803 00000000 00000000 0000fc58 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000155f9 00000000 00000000 0001045b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0000aa50 00000000 00000000 00025a54 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 00088675 00000000 00000000 000304a4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000b8b19 2**0 + CONTENTS, READONLY + 20 .debug_frame 00002ba0 00000000 00000000 000b8b5c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000bb6fc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 2000000c .word 0x2000000c + 8000158: 00000000 .word 0x00000000 + 800015c: 08002f54 .word 0x08002f54 + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000010 .word 0x20000010 + 8000178: 08002f54 .word 0x08002f54 + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80004b0: b580 push {r7, lr} + 80004b2: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80004b4: f000 fb8c bl 8000bd0 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80004b8: f000 f814 bl 80004e4 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80004bc: f000 f94e bl 800075c + MX_SPI1_Init(); + 80004c0: f000 f856 bl 8000570 + MX_TIM2_Init(); + 80004c4: f000 f88a bl 80005dc + MX_TIM3_Init(); + 80004c8: f000 f8d6 bl 8000678 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 80004cc: f000 fb03 bl 8000ad6 + HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1); + 80004d0: 2100 movs r1, #0 + 80004d2: 4803 ldr r0, [pc, #12] @ (80004e0 ) + 80004d4: f001 ff76 bl 80023c4 + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 80004d8: f000 fb34 bl 8000b44 + while (1) + 80004dc: bf00 nop + 80004de: e7fd b.n 80004dc + 80004e0: 200000c0 .word 0x200000c0 + +080004e4 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 80004e4: b580 push {r7, lr} + 80004e6: b092 sub sp, #72 @ 0x48 + 80004e8: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 80004ea: f107 0314 add.w r3, r7, #20 + 80004ee: 2234 movs r2, #52 @ 0x34 + 80004f0: 2100 movs r1, #0 + 80004f2: 4618 mov r0, r3 + 80004f4: f002 fd02 bl 8002efc + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 80004f8: 463b mov r3, r7 + 80004fa: 2200 movs r2, #0 + 80004fc: 601a str r2, [r3, #0] + 80004fe: 605a str r2, [r3, #4] + 8000500: 609a str r2, [r3, #8] + 8000502: 60da str r2, [r3, #12] + 8000504: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000506: 4b19 ldr r3, [pc, #100] @ (800056c ) + 8000508: 681b ldr r3, [r3, #0] + 800050a: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 800050e: 4a17 ldr r2, [pc, #92] @ (800056c ) + 8000510: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000514: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000516: 2302 movs r3, #2 + 8000518: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 800051a: 2301 movs r3, #1 + 800051c: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 800051e: 2310 movs r3, #16 + 8000520: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000522: 2300 movs r3, #0 + 8000524: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000526: f107 0314 add.w r3, r7, #20 + 800052a: 4618 mov r0, r3 + 800052c: f000 fe96 bl 800125c + 8000530: 4603 mov r3, r0 + 8000532: 2b00 cmp r3, #0 + 8000534: d001 beq.n 800053a + { + Error_Handler(); + 8000536: f000 f967 bl 8000808 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 800053a: 230f movs r3, #15 + 800053c: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 800053e: 2301 movs r3, #1 + 8000540: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000542: 2300 movs r3, #0 + 8000544: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000546: 2300 movs r3, #0 + 8000548: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 800054a: 2300 movs r3, #0 + 800054c: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 800054e: 463b mov r3, r7 + 8000550: 2100 movs r1, #0 + 8000552: 4618 mov r0, r3 + 8000554: f001 f9b2 bl 80018bc + 8000558: 4603 mov r3, r0 + 800055a: 2b00 cmp r3, #0 + 800055c: d001 beq.n 8000562 + { + Error_Handler(); + 800055e: f000 f953 bl 8000808 + } +} + 8000562: bf00 nop + 8000564: 3748 adds r7, #72 @ 0x48 + 8000566: 46bd mov sp, r7 + 8000568: bd80 pop {r7, pc} + 800056a: bf00 nop + 800056c: 40007000 .word 0x40007000 + +08000570 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 8000570: b580 push {r7, lr} + 8000572: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 8000574: 4b17 ldr r3, [pc, #92] @ (80005d4 ) + 8000576: 4a18 ldr r2, [pc, #96] @ (80005d8 ) + 8000578: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 800057a: 4b16 ldr r3, [pc, #88] @ (80005d4 ) + 800057c: f44f 7282 mov.w r2, #260 @ 0x104 + 8000580: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 8000582: 4b14 ldr r3, [pc, #80] @ (80005d4 ) + 8000584: 2200 movs r2, #0 + 8000586: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 8000588: 4b12 ldr r3, [pc, #72] @ (80005d4 ) + 800058a: 2200 movs r2, #0 + 800058c: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 800058e: 4b11 ldr r3, [pc, #68] @ (80005d4 ) + 8000590: 2200 movs r2, #0 + 8000592: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 8000594: 4b0f ldr r3, [pc, #60] @ (80005d4 ) + 8000596: 2200 movs r2, #0 + 8000598: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 800059a: 4b0e ldr r3, [pc, #56] @ (80005d4 ) + 800059c: f44f 7200 mov.w r2, #512 @ 0x200 + 80005a0: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 80005a2: 4b0c ldr r3, [pc, #48] @ (80005d4 ) + 80005a4: 2200 movs r2, #0 + 80005a6: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 80005a8: 4b0a ldr r3, [pc, #40] @ (80005d4 ) + 80005aa: 2200 movs r2, #0 + 80005ac: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 80005ae: 4b09 ldr r3, [pc, #36] @ (80005d4 ) + 80005b0: 2200 movs r2, #0 + 80005b2: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 80005b4: 4b07 ldr r3, [pc, #28] @ (80005d4 ) + 80005b6: 2200 movs r2, #0 + 80005b8: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 80005ba: 4b06 ldr r3, [pc, #24] @ (80005d4 ) + 80005bc: 220a movs r2, #10 + 80005be: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 80005c0: 4804 ldr r0, [pc, #16] @ (80005d4 ) + 80005c2: f001 fbcd bl 8001d60 + 80005c6: 4603 mov r3, r0 + 80005c8: 2b00 cmp r3, #0 + 80005ca: d001 beq.n 80005d0 + { + Error_Handler(); + 80005cc: f000 f91c bl 8000808 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 80005d0: bf00 nop + 80005d2: bd80 pop {r7, pc} + 80005d4: 20000028 .word 0x20000028 + 80005d8: 40013000 .word 0x40013000 + +080005dc : + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 80005dc: b580 push {r7, lr} + 80005de: b086 sub sp, #24 + 80005e0: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 80005e2: f107 0308 add.w r3, r7, #8 + 80005e6: 2200 movs r2, #0 + 80005e8: 601a str r2, [r3, #0] + 80005ea: 605a str r2, [r3, #4] + 80005ec: 609a str r2, [r3, #8] + 80005ee: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 80005f0: 463b mov r3, r7 + 80005f2: 2200 movs r2, #0 + 80005f4: 601a str r2, [r3, #0] + 80005f6: 605a str r2, [r3, #4] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 80005f8: 4b1e ldr r3, [pc, #120] @ (8000674 ) + 80005fa: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 + 80005fe: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 1000-1; + 8000600: 4b1c ldr r3, [pc, #112] @ (8000674 ) + 8000602: f240 32e7 movw r2, #999 @ 0x3e7 + 8000606: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000608: 4b1a ldr r3, [pc, #104] @ (8000674 ) + 800060a: 2200 movs r2, #0 + 800060c: 609a str r2, [r3, #8] + htim2.Init.Period = 16000-1; + 800060e: 4b19 ldr r3, [pc, #100] @ (8000674 ) + 8000610: f643 627f movw r2, #15999 @ 0x3e7f + 8000614: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000616: 4b17 ldr r3, [pc, #92] @ (8000674 ) + 8000618: 2200 movs r2, #0 + 800061a: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 800061c: 4b15 ldr r3, [pc, #84] @ (8000674 ) + 800061e: 2280 movs r2, #128 @ 0x80 + 8000620: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + 8000622: 4814 ldr r0, [pc, #80] @ (8000674 ) + 8000624: f001 fe46 bl 80022b4 + 8000628: 4603 mov r3, r0 + 800062a: 2b00 cmp r3, #0 + 800062c: d001 beq.n 8000632 + { + Error_Handler(); + 800062e: f000 f8eb bl 8000808 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000632: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8000636: 60bb str r3, [r7, #8] + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + 8000638: f107 0308 add.w r3, r7, #8 + 800063c: 4619 mov r1, r3 + 800063e: 480d ldr r0, [pc, #52] @ (8000674 ) + 8000640: f002 f8e4 bl 800280c + 8000644: 4603 mov r3, r0 + 8000646: 2b00 cmp r3, #0 + 8000648: d001 beq.n 800064e + { + Error_Handler(); + 800064a: f000 f8dd bl 8000808 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 800064e: 2300 movs r3, #0 + 8000650: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000652: 2300 movs r3, #0 + 8000654: 607b str r3, [r7, #4] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 8000656: 463b mov r3, r7 + 8000658: 4619 mov r1, r3 + 800065a: 4806 ldr r0, [pc, #24] @ (8000674 ) + 800065c: f002 fbf0 bl 8002e40 + 8000660: 4603 mov r3, r0 + 8000662: 2b00 cmp r3, #0 + 8000664: d001 beq.n 800066a + { + Error_Handler(); + 8000666: f000 f8cf bl 8000808 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 800066a: bf00 nop + 800066c: 3718 adds r7, #24 + 800066e: 46bd mov sp, r7 + 8000670: bd80 pop {r7, pc} + 8000672: bf00 nop + 8000674: 20000080 .word 0x20000080 + +08000678 : + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + 8000678: b580 push {r7, lr} + 800067a: b08a sub sp, #40 @ 0x28 + 800067c: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800067e: f107 0318 add.w r3, r7, #24 + 8000682: 2200 movs r2, #0 + 8000684: 601a str r2, [r3, #0] + 8000686: 605a str r2, [r3, #4] + 8000688: 609a str r2, [r3, #8] + 800068a: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 800068c: f107 0310 add.w r3, r7, #16 + 8000690: 2200 movs r2, #0 + 8000692: 601a str r2, [r3, #0] + 8000694: 605a str r2, [r3, #4] + TIM_OC_InitTypeDef sConfigOC = {0}; + 8000696: 463b mov r3, r7 + 8000698: 2200 movs r2, #0 + 800069a: 601a str r2, [r3, #0] + 800069c: 605a str r2, [r3, #4] + 800069e: 609a str r2, [r3, #8] + 80006a0: 60da str r2, [r3, #12] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 80006a2: 4b2c ldr r3, [pc, #176] @ (8000754 ) + 80006a4: 4a2c ldr r2, [pc, #176] @ (8000758 ) + 80006a6: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 8-1; + 80006a8: 4b2a ldr r3, [pc, #168] @ (8000754 ) + 80006aa: 2207 movs r2, #7 + 80006ac: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 80006ae: 4b29 ldr r3, [pc, #164] @ (8000754 ) + 80006b0: 2200 movs r2, #0 + 80006b2: 609a str r2, [r3, #8] + htim3.Init.Period = 100-1; + 80006b4: 4b27 ldr r3, [pc, #156] @ (8000754 ) + 80006b6: 2263 movs r2, #99 @ 0x63 + 80006b8: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80006ba: 4b26 ldr r3, [pc, #152] @ (8000754 ) + 80006bc: 2200 movs r2, #0 + 80006be: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 80006c0: 4b24 ldr r3, [pc, #144] @ (8000754 ) + 80006c2: 2280 movs r2, #128 @ 0x80 + 80006c4: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + 80006c6: 4823 ldr r0, [pc, #140] @ (8000754 ) + 80006c8: f001 fdf4 bl 80022b4 + 80006cc: 4603 mov r3, r0 + 80006ce: 2b00 cmp r3, #0 + 80006d0: d001 beq.n 80006d6 + { + Error_Handler(); + 80006d2: f000 f899 bl 8000808 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 80006d6: f44f 5380 mov.w r3, #4096 @ 0x1000 + 80006da: 61bb str r3, [r7, #24] + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + 80006dc: f107 0318 add.w r3, r7, #24 + 80006e0: 4619 mov r1, r3 + 80006e2: 481c ldr r0, [pc, #112] @ (8000754 ) + 80006e4: f002 f892 bl 800280c + 80006e8: 4603 mov r3, r0 + 80006ea: 2b00 cmp r3, #0 + 80006ec: d001 beq.n 80006f2 + { + Error_Handler(); + 80006ee: f000 f88b bl 8000808 + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + 80006f2: 4818 ldr r0, [pc, #96] @ (8000754 ) + 80006f4: f001 fe1d bl 8002332 + 80006f8: 4603 mov r3, r0 + 80006fa: 2b00 cmp r3, #0 + 80006fc: d001 beq.n 8000702 + { + Error_Handler(); + 80006fe: f000 f883 bl 8000808 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000702: 2300 movs r3, #0 + 8000704: 613b str r3, [r7, #16] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000706: 2300 movs r3, #0 + 8000708: 617b str r3, [r7, #20] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 800070a: f107 0310 add.w r3, r7, #16 + 800070e: 4619 mov r1, r3 + 8000710: 4810 ldr r0, [pc, #64] @ (8000754 ) + 8000712: f002 fb95 bl 8002e40 + 8000716: 4603 mov r3, r0 + 8000718: 2b00 cmp r3, #0 + 800071a: d001 beq.n 8000720 + { + Error_Handler(); + 800071c: f000 f874 bl 8000808 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 8000720: 2360 movs r3, #96 @ 0x60 + 8000722: 603b str r3, [r7, #0] + sConfigOC.Pulse = 67; + 8000724: 2343 movs r3, #67 @ 0x43 + 8000726: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 8000728: 2300 movs r3, #0 + 800072a: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 800072c: 2300 movs r3, #0 + 800072e: 60fb str r3, [r7, #12] + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 8000730: 463b mov r3, r7 + 8000732: 2200 movs r2, #0 + 8000734: 4619 mov r1, r3 + 8000736: 4807 ldr r0, [pc, #28] @ (8000754 ) + 8000738: f001 ffa6 bl 8002688 + 800073c: 4603 mov r3, r0 + 800073e: 2b00 cmp r3, #0 + 8000740: d001 beq.n 8000746 + { + Error_Handler(); + 8000742: f000 f861 bl 8000808 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + 8000746: 4803 ldr r0, [pc, #12] @ (8000754 ) + 8000748: f000 f916 bl 8000978 + +} + 800074c: bf00 nop + 800074e: 3728 adds r7, #40 @ 0x28 + 8000750: 46bd mov sp, r7 + 8000752: bd80 pop {r7, pc} + 8000754: 200000c0 .word 0x200000c0 + 8000758: 40000400 .word 0x40000400 + +0800075c : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 800075c: b580 push {r7, lr} + 800075e: b088 sub sp, #32 + 8000760: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000762: f107 030c add.w r3, r7, #12 + 8000766: 2200 movs r2, #0 + 8000768: 601a str r2, [r3, #0] + 800076a: 605a str r2, [r3, #4] + 800076c: 609a str r2, [r3, #8] + 800076e: 60da str r2, [r3, #12] + 8000770: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000772: 4b22 ldr r3, [pc, #136] @ (80007fc ) + 8000774: 69db ldr r3, [r3, #28] + 8000776: 4a21 ldr r2, [pc, #132] @ (80007fc ) + 8000778: f043 0304 orr.w r3, r3, #4 + 800077c: 61d3 str r3, [r2, #28] + 800077e: 4b1f ldr r3, [pc, #124] @ (80007fc ) + 8000780: 69db ldr r3, [r3, #28] + 8000782: f003 0304 and.w r3, r3, #4 + 8000786: 60bb str r3, [r7, #8] + 8000788: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800078a: 4b1c ldr r3, [pc, #112] @ (80007fc ) + 800078c: 69db ldr r3, [r3, #28] + 800078e: 4a1b ldr r2, [pc, #108] @ (80007fc ) + 8000790: f043 0301 orr.w r3, r3, #1 + 8000794: 61d3 str r3, [r2, #28] + 8000796: 4b19 ldr r3, [pc, #100] @ (80007fc ) + 8000798: 69db ldr r3, [r3, #28] + 800079a: f003 0301 and.w r3, r3, #1 + 800079e: 607b str r3, [r7, #4] + 80007a0: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 80007a2: 2200 movs r2, #0 + 80007a4: 2101 movs r1, #1 + 80007a6: 4816 ldr r0, [pc, #88] @ (8000800 ) + 80007a8: f000 fd1e bl 80011e8 + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 80007ac: 2301 movs r3, #1 + 80007ae: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80007b0: 2301 movs r3, #1 + 80007b2: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007b4: 2300 movs r3, #0 + 80007b6: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80007b8: 2300 movs r3, #0 + 80007ba: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80007bc: f107 030c add.w r3, r7, #12 + 80007c0: 4619 mov r1, r3 + 80007c2: 480f ldr r0, [pc, #60] @ (8000800 ) + 80007c4: f000 fb80 bl 8000ec8 + + /*Configure GPIO pins : PA11 PA12 */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 80007c8: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 80007cc: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 80007ce: f44f 1388 mov.w r3, #1114112 @ 0x110000 + 80007d2: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007d4: 2300 movs r3, #0 + 80007d6: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80007d8: f107 030c add.w r3, r7, #12 + 80007dc: 4619 mov r1, r3 + 80007de: 4809 ldr r0, [pc, #36] @ (8000804 ) + 80007e0: f000 fb72 bl 8000ec8 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 80007e4: 2200 movs r2, #0 + 80007e6: 2100 movs r1, #0 + 80007e8: 2028 movs r0, #40 @ 0x28 + 80007ea: f000 fb36 bl 8000e5a + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 80007ee: 2028 movs r0, #40 @ 0x28 + 80007f0: f000 fb4f bl 8000e92 + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 80007f4: bf00 nop + 80007f6: 3720 adds r7, #32 + 80007f8: 46bd mov sp, r7 + 80007fa: bd80 pop {r7, pc} + 80007fc: 40023800 .word 0x40023800 + 8000800: 40020800 .word 0x40020800 + 8000804: 40020000 .word 0x40020000 + +08000808 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000808: b480 push {r7} + 800080a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800080c: b672 cpsid i +} + 800080e: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000810: bf00 nop + 8000812: e7fd b.n 8000810 + +08000814 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000814: b480 push {r7} + 8000816: b085 sub sp, #20 + 8000818: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 800081a: 4b14 ldr r3, [pc, #80] @ (800086c ) + 800081c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800081e: 4a13 ldr r2, [pc, #76] @ (800086c ) + 8000820: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 8000824: 6253 str r3, [r2, #36] @ 0x24 + 8000826: 4b11 ldr r3, [pc, #68] @ (800086c ) + 8000828: 6a5b ldr r3, [r3, #36] @ 0x24 + 800082a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 800082e: 60fb str r3, [r7, #12] + 8000830: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000832: 4b0e ldr r3, [pc, #56] @ (800086c ) + 8000834: 6a1b ldr r3, [r3, #32] + 8000836: 4a0d ldr r2, [pc, #52] @ (800086c ) + 8000838: f043 0301 orr.w r3, r3, #1 + 800083c: 6213 str r3, [r2, #32] + 800083e: 4b0b ldr r3, [pc, #44] @ (800086c ) + 8000840: 6a1b ldr r3, [r3, #32] + 8000842: f003 0301 and.w r3, r3, #1 + 8000846: 60bb str r3, [r7, #8] + 8000848: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800084a: 4b08 ldr r3, [pc, #32] @ (800086c ) + 800084c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800084e: 4a07 ldr r2, [pc, #28] @ (800086c ) + 8000850: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000854: 6253 str r3, [r2, #36] @ 0x24 + 8000856: 4b05 ldr r3, [pc, #20] @ (800086c ) + 8000858: 6a5b ldr r3, [r3, #36] @ 0x24 + 800085a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800085e: 607b str r3, [r7, #4] + 8000860: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000862: bf00 nop + 8000864: 3714 adds r7, #20 + 8000866: 46bd mov sp, r7 + 8000868: bc80 pop {r7} + 800086a: 4770 bx lr + 800086c: 40023800 .word 0x40023800 + +08000870 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8000870: b580 push {r7, lr} + 8000872: b08a sub sp, #40 @ 0x28 + 8000874: af00 add r7, sp, #0 + 8000876: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000878: f107 0314 add.w r3, r7, #20 + 800087c: 2200 movs r2, #0 + 800087e: 601a str r2, [r3, #0] + 8000880: 605a str r2, [r3, #4] + 8000882: 609a str r2, [r3, #8] + 8000884: 60da str r2, [r3, #12] + 8000886: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 8000888: 687b ldr r3, [r7, #4] + 800088a: 681b ldr r3, [r3, #0] + 800088c: 4a17 ldr r2, [pc, #92] @ (80008ec ) + 800088e: 4293 cmp r3, r2 + 8000890: d127 bne.n 80008e2 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 8000892: 4b17 ldr r3, [pc, #92] @ (80008f0 ) + 8000894: 6a1b ldr r3, [r3, #32] + 8000896: 4a16 ldr r2, [pc, #88] @ (80008f0 ) + 8000898: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 800089c: 6213 str r3, [r2, #32] + 800089e: 4b14 ldr r3, [pc, #80] @ (80008f0 ) + 80008a0: 6a1b ldr r3, [r3, #32] + 80008a2: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80008a6: 613b str r3, [r7, #16] + 80008a8: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80008aa: 4b11 ldr r3, [pc, #68] @ (80008f0 ) + 80008ac: 69db ldr r3, [r3, #28] + 80008ae: 4a10 ldr r2, [pc, #64] @ (80008f0 ) + 80008b0: f043 0301 orr.w r3, r3, #1 + 80008b4: 61d3 str r3, [r2, #28] + 80008b6: 4b0e ldr r3, [pc, #56] @ (80008f0 ) + 80008b8: 69db ldr r3, [r3, #28] + 80008ba: f003 0301 and.w r3, r3, #1 + 80008be: 60fb str r3, [r7, #12] + 80008c0: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 80008c2: 23e0 movs r3, #224 @ 0xe0 + 80008c4: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80008c6: 2302 movs r3, #2 + 80008c8: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008ca: 2300 movs r3, #0 + 80008cc: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80008ce: 2303 movs r3, #3 + 80008d0: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 80008d2: 2305 movs r3, #5 + 80008d4: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80008d6: f107 0314 add.w r3, r7, #20 + 80008da: 4619 mov r1, r3 + 80008dc: 4805 ldr r0, [pc, #20] @ (80008f4 ) + 80008de: f000 faf3 bl 8000ec8 + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 80008e2: bf00 nop + 80008e4: 3728 adds r7, #40 @ 0x28 + 80008e6: 46bd mov sp, r7 + 80008e8: bd80 pop {r7, pc} + 80008ea: bf00 nop + 80008ec: 40013000 .word 0x40013000 + 80008f0: 40023800 .word 0x40023800 + 80008f4: 40020000 .word 0x40020000 + +080008f8 : + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 80008f8: b580 push {r7, lr} + 80008fa: b084 sub sp, #16 + 80008fc: af00 add r7, sp, #0 + 80008fe: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM2) + 8000900: 687b ldr r3, [r7, #4] + 8000902: 681b ldr r3, [r3, #0] + 8000904: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8000908: d114 bne.n 8000934 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 800090a: 4b19 ldr r3, [pc, #100] @ (8000970 ) + 800090c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800090e: 4a18 ldr r2, [pc, #96] @ (8000970 ) + 8000910: f043 0301 orr.w r3, r3, #1 + 8000914: 6253 str r3, [r2, #36] @ 0x24 + 8000916: 4b16 ldr r3, [pc, #88] @ (8000970 ) + 8000918: 6a5b ldr r3, [r3, #36] @ 0x24 + 800091a: f003 0301 and.w r3, r3, #1 + 800091e: 60fb str r3, [r7, #12] + 8000920: 68fb ldr r3, [r7, #12] + /* TIM2 interrupt Init */ + HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); + 8000922: 2200 movs r2, #0 + 8000924: 2100 movs r1, #0 + 8000926: 201c movs r0, #28 + 8000928: f000 fa97 bl 8000e5a + HAL_NVIC_EnableIRQ(TIM2_IRQn); + 800092c: 201c movs r0, #28 + 800092e: f000 fab0 bl 8000e92 + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + +} + 8000932: e018 b.n 8000966 + else if(htim_base->Instance==TIM3) + 8000934: 687b ldr r3, [r7, #4] + 8000936: 681b ldr r3, [r3, #0] + 8000938: 4a0e ldr r2, [pc, #56] @ (8000974 ) + 800093a: 4293 cmp r3, r2 + 800093c: d113 bne.n 8000966 + __HAL_RCC_TIM3_CLK_ENABLE(); + 800093e: 4b0c ldr r3, [pc, #48] @ (8000970 ) + 8000940: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000942: 4a0b ldr r2, [pc, #44] @ (8000970 ) + 8000944: f043 0302 orr.w r3, r3, #2 + 8000948: 6253 str r3, [r2, #36] @ 0x24 + 800094a: 4b09 ldr r3, [pc, #36] @ (8000970 ) + 800094c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800094e: f003 0302 and.w r3, r3, #2 + 8000952: 60bb str r3, [r7, #8] + 8000954: 68bb ldr r3, [r7, #8] + HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); + 8000956: 2200 movs r2, #0 + 8000958: 2100 movs r1, #0 + 800095a: 201d movs r0, #29 + 800095c: f000 fa7d bl 8000e5a + HAL_NVIC_EnableIRQ(TIM3_IRQn); + 8000960: 201d movs r0, #29 + 8000962: f000 fa96 bl 8000e92 +} + 8000966: bf00 nop + 8000968: 3710 adds r7, #16 + 800096a: 46bd mov sp, r7 + 800096c: bd80 pop {r7, pc} + 800096e: bf00 nop + 8000970: 40023800 .word 0x40023800 + 8000974: 40000400 .word 0x40000400 + +08000978 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8000978: b580 push {r7, lr} + 800097a: b088 sub sp, #32 + 800097c: af00 add r7, sp, #0 + 800097e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000980: f107 030c add.w r3, r7, #12 + 8000984: 2200 movs r2, #0 + 8000986: 601a str r2, [r3, #0] + 8000988: 605a str r2, [r3, #4] + 800098a: 609a str r2, [r3, #8] + 800098c: 60da str r2, [r3, #12] + 800098e: 611a str r2, [r3, #16] + if(htim->Instance==TIM3) + 8000990: 687b ldr r3, [r7, #4] + 8000992: 681b ldr r3, [r3, #0] + 8000994: 4a11 ldr r2, [pc, #68] @ (80009dc ) + 8000996: 4293 cmp r3, r2 + 8000998: d11b bne.n 80009d2 + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800099a: 4b11 ldr r3, [pc, #68] @ (80009e0 ) + 800099c: 69db ldr r3, [r3, #28] + 800099e: 4a10 ldr r2, [pc, #64] @ (80009e0 ) + 80009a0: f043 0304 orr.w r3, r3, #4 + 80009a4: 61d3 str r3, [r2, #28] + 80009a6: 4b0e ldr r3, [pc, #56] @ (80009e0 ) + 80009a8: 69db ldr r3, [r3, #28] + 80009aa: f003 0304 and.w r3, r3, #4 + 80009ae: 60bb str r3, [r7, #8] + 80009b0: 68bb ldr r3, [r7, #8] + /**TIM3 GPIO Configuration + PC6 ------> TIM3_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + 80009b2: 2340 movs r3, #64 @ 0x40 + 80009b4: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80009b6: 2302 movs r3, #2 + 80009b8: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80009ba: 2300 movs r3, #0 + 80009bc: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80009be: 2300 movs r3, #0 + 80009c0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 80009c2: 2302 movs r3, #2 + 80009c4: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80009c6: f107 030c add.w r3, r7, #12 + 80009ca: 4619 mov r1, r3 + 80009cc: 4805 ldr r0, [pc, #20] @ (80009e4 ) + 80009ce: f000 fa7b bl 8000ec8 + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + +} + 80009d2: bf00 nop + 80009d4: 3720 adds r7, #32 + 80009d6: 46bd mov sp, r7 + 80009d8: bd80 pop {r7, pc} + 80009da: bf00 nop + 80009dc: 40000400 .word 0x40000400 + 80009e0: 40023800 .word 0x40023800 + 80009e4: 40020800 .word 0x40020800 + +080009e8 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 80009e8: b480 push {r7} + 80009ea: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 80009ec: bf00 nop + 80009ee: e7fd b.n 80009ec + +080009f0 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 80009f0: b480 push {r7} + 80009f2: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 80009f4: bf00 nop + 80009f6: e7fd b.n 80009f4 + +080009f8 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 80009f8: b480 push {r7} + 80009fa: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 80009fc: bf00 nop + 80009fe: e7fd b.n 80009fc + +08000a00 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000a00: b480 push {r7} + 8000a02: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000a04: bf00 nop + 8000a06: e7fd b.n 8000a04 + +08000a08 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000a08: b480 push {r7} + 8000a0a: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000a0c: bf00 nop + 8000a0e: e7fd b.n 8000a0c + +08000a10 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000a10: b480 push {r7} + 8000a12: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000a14: bf00 nop + 8000a16: 46bd mov sp, r7 + 8000a18: bc80 pop {r7} + 8000a1a: 4770 bx lr + +08000a1c : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000a1c: b480 push {r7} + 8000a1e: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000a20: bf00 nop + 8000a22: 46bd mov sp, r7 + 8000a24: bc80 pop {r7} + 8000a26: 4770 bx lr + +08000a28 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000a28: b480 push {r7} + 8000a2a: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000a2c: bf00 nop + 8000a2e: 46bd mov sp, r7 + 8000a30: bc80 pop {r7} + 8000a32: 4770 bx lr + +08000a34 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000a34: b580 push {r7, lr} + 8000a36: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000a38: f000 f91c bl 8000c74 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000a3c: bf00 nop + 8000a3e: bd80 pop {r7, pc} + +08000a40 : + +/** + * @brief This function handles TIM2 global interrupt. + */ +void TIM2_IRQHandler(void) +{ + 8000a40: b580 push {r7, lr} + 8000a42: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM2_IRQn 0 */ + + /* USER CODE END TIM2_IRQn 0 */ + HAL_TIM_IRQHandler(&htim2); + 8000a44: 4802 ldr r0, [pc, #8] @ (8000a50 ) + 8000a46: f001 fd53 bl 80024f0 + /* USER CODE BEGIN TIM2_IRQn 1 */ + + /* USER CODE END TIM2_IRQn 1 */ +} + 8000a4a: bf00 nop + 8000a4c: bd80 pop {r7, pc} + 8000a4e: bf00 nop + 8000a50: 20000080 .word 0x20000080 + +08000a54 : + +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + 8000a54: b580 push {r7, lr} + 8000a56: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + 8000a58: 4802 ldr r0, [pc, #8] @ (8000a64 ) + 8000a5a: f001 fd49 bl 80024f0 + /* USER CODE BEGIN TIM3_IRQn 1 */ + + /* USER CODE END TIM3_IRQn 1 */ +} + 8000a5e: bf00 nop + 8000a60: bd80 pop {r7, pc} + 8000a62: bf00 nop + 8000a64: 200000c0 .word 0x200000c0 + +08000a68 : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 8000a68: b580 push {r7, lr} + 8000a6a: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + 8000a6c: f44f 6000 mov.w r0, #2048 @ 0x800 + 8000a70: f000 fbd2 bl 8001218 + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + 8000a74: f44f 5080 mov.w r0, #4096 @ 0x1000 + 8000a78: f000 fbce bl 8001218 + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8000a7c: bf00 nop + 8000a7e: bd80 pop {r7, pc} + +08000a80 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000a80: b480 push {r7} + 8000a82: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000a84: bf00 nop + 8000a86: 46bd mov sp, r7 + 8000a88: bc80 pop {r7} + 8000a8a: 4770 bx lr + +08000a8c : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000a8c: f7ff fff8 bl 8000a80 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000a90: 480b ldr r0, [pc, #44] @ (8000ac0 ) + ldr r1, =_edata + 8000a92: 490c ldr r1, [pc, #48] @ (8000ac4 ) + ldr r2, =_sidata + 8000a94: 4a0c ldr r2, [pc, #48] @ (8000ac8 ) + movs r3, #0 + 8000a96: 2300 movs r3, #0 + b LoopCopyDataInit + 8000a98: e002 b.n 8000aa0 + +08000a9a : + +CopyDataInit: + ldr r4, [r2, r3] + 8000a9a: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000a9c: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000a9e: 3304 adds r3, #4 + +08000aa0 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000aa0: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000aa2: 428c cmp r4, r1 + bcc CopyDataInit + 8000aa4: d3f9 bcc.n 8000a9a + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000aa6: 4a09 ldr r2, [pc, #36] @ (8000acc ) + ldr r4, =_ebss + 8000aa8: 4c09 ldr r4, [pc, #36] @ (8000ad0 ) + movs r3, #0 + 8000aaa: 2300 movs r3, #0 + b LoopFillZerobss + 8000aac: e001 b.n 8000ab2 + +08000aae : + +FillZerobss: + str r3, [r2] + 8000aae: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000ab0: 3204 adds r2, #4 + +08000ab2 : + +LoopFillZerobss: + cmp r2, r4 + 8000ab2: 42a2 cmp r2, r4 + bcc FillZerobss + 8000ab4: d3fb bcc.n 8000aae + +/* Call static constructors */ + bl __libc_init_array + 8000ab6: f002 fa29 bl 8002f0c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8000aba: f7ff fcf9 bl 80004b0
+ bx lr + 8000abe: 4770 bx lr + ldr r0, =_sdata + 8000ac0: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000ac4: 2000000c .word 0x2000000c + ldr r2, =_sidata + 8000ac8: 08002f98 .word 0x08002f98 + ldr r2, =_sbss + 8000acc: 2000000c .word 0x2000000c + ldr r4, =_ebss + 8000ad0: 20000104 .word 0x20000104 + +08000ad4 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000ad4: e7fe b.n 8000ad4 + +08000ad6 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 8000ad6: b580 push {r7, lr} + 8000ad8: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 8000ada: 2107 movs r1, #7 + 8000adc: 200b movs r0, #11 + 8000ade: f000 f847 bl 8000b70 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 8000ae2: 2100 movs r1, #0 + 8000ae4: 2009 movs r0, #9 + 8000ae6: f000 f843 bl 8000b70 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 8000aea: f000 f809 bl 8000b00 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 8000aee: f000 f80f bl 8000b10 + MAX7219_Clear(); // clear all digits + 8000af2: f000 f827 bl 8000b44 + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 8000af6: 200f movs r0, #15 + 8000af8: f000 f812 bl 8000b20 +} + 8000afc: bf00 nop + 8000afe: bd80 pop {r7, pc} + +08000b00 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000b00: b580 push {r7, lr} + 8000b02: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000b04: 2101 movs r1, #1 + 8000b06: 200c movs r0, #12 + 8000b08: f000 f832 bl 8000b70 +} + 8000b0c: bf00 nop + 8000b0e: bd80 pop {r7, pc} + +08000b10 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 8000b10: b580 push {r7, lr} + 8000b12: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 8000b14: 2100 movs r1, #0 + 8000b16: 200f movs r0, #15 + 8000b18: f000 f82a bl 8000b70 +} + 8000b1c: bf00 nop + 8000b1e: bd80 pop {r7, pc} + +08000b20 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 8000b20: b580 push {r7, lr} + 8000b22: b082 sub sp, #8 + 8000b24: af00 add r7, sp, #0 + 8000b26: 4603 mov r3, r0 + 8000b28: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 8000b2a: 79fb ldrb r3, [r7, #7] + 8000b2c: f003 030f and.w r3, r3, #15 + 8000b30: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 8000b32: 79fb ldrb r3, [r7, #7] + 8000b34: 4619 mov r1, r3 + 8000b36: 200a movs r0, #10 + 8000b38: f000 f81a bl 8000b70 +} + 8000b3c: bf00 nop + 8000b3e: 3708 adds r7, #8 + 8000b40: 46bd mov sp, r7 + 8000b42: bd80 pop {r7, pc} + +08000b44 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 8000b44: b580 push {r7, lr} + 8000b46: b082 sub sp, #8 + 8000b48: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 8000b4a: 2300 movs r3, #0 + 8000b4c: 71fb strb r3, [r7, #7] + 8000b4e: e007 b.n 8000b60 + MAX7219_Write(i, 0x00); // turn all segments off + 8000b50: 79fb ldrb r3, [r7, #7] + 8000b52: 2100 movs r1, #0 + 8000b54: 4618 mov r0, r3 + 8000b56: f000 f80b bl 8000b70 + for (i=0; i < 8; i++) + 8000b5a: 79fb ldrb r3, [r7, #7] + 8000b5c: 3301 adds r3, #1 + 8000b5e: 71fb strb r3, [r7, #7] + 8000b60: 79fb ldrb r3, [r7, #7] + 8000b62: 2b07 cmp r3, #7 + 8000b64: d9f4 bls.n 8000b50 +} + 8000b66: bf00 nop + 8000b68: bf00 nop + 8000b6a: 3708 adds r7, #8 + 8000b6c: 46bd mov sp, r7 + 8000b6e: bd80 pop {r7, pc} + +08000b70 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8000b70: b580 push {r7, lr} + 8000b72: b082 sub sp, #8 + 8000b74: af00 add r7, sp, #0 + 8000b76: 4603 mov r3, r0 + 8000b78: 460a mov r2, r1 + 8000b7a: 71fb strb r3, [r7, #7] + 8000b7c: 4613 mov r3, r2 + 8000b7e: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8000b80: 4b09 ldr r3, [pc, #36] @ (8000ba8 ) + 8000b82: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000b86: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8000b88: 79fb ldrb r3, [r7, #7] + 8000b8a: 4618 mov r0, r3 + 8000b8c: f000 f80e bl 8000bac + MAX7219_SendByte(dataout); // write data to MAX7219 + 8000b90: 79bb ldrb r3, [r7, #6] + 8000b92: 4618 mov r0, r3 + 8000b94: f000 f80a bl 8000bac + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 8000b98: 4b03 ldr r3, [pc, #12] @ (8000ba8 ) + 8000b9a: 2201 movs r2, #1 + 8000b9c: 619a str r2, [r3, #24] + } + 8000b9e: bf00 nop + 8000ba0: 3708 adds r7, #8 + 8000ba2: 46bd mov sp, r7 + 8000ba4: bd80 pop {r7, pc} + 8000ba6: bf00 nop + 8000ba8: 40020800 .word 0x40020800 + +08000bac : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000bac: b580 push {r7, lr} + 8000bae: b082 sub sp, #8 + 8000bb0: af00 add r7, sp, #0 + 8000bb2: 4603 mov r3, r0 + 8000bb4: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 8000bb6: 1df9 adds r1, r7, #7 + 8000bb8: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000bbc: 2201 movs r2, #1 + 8000bbe: 4803 ldr r0, [pc, #12] @ (8000bcc ) + 8000bc0: f001 f957 bl 8001e72 + +} + 8000bc4: bf00 nop + 8000bc6: 3708 adds r7, #8 + 8000bc8: 46bd mov sp, r7 + 8000bca: bd80 pop {r7, pc} + 8000bcc: 20000028 .word 0x20000028 + +08000bd0 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000bd0: b580 push {r7, lr} + 8000bd2: b082 sub sp, #8 + 8000bd4: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000bd6: 2300 movs r3, #0 + 8000bd8: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000bda: 2003 movs r0, #3 + 8000bdc: f000 f932 bl 8000e44 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000be0: 200f movs r0, #15 + 8000be2: f000 f80d bl 8000c00 + 8000be6: 4603 mov r3, r0 + 8000be8: 2b00 cmp r3, #0 + 8000bea: d002 beq.n 8000bf2 + { + status = HAL_ERROR; + 8000bec: 2301 movs r3, #1 + 8000bee: 71fb strb r3, [r7, #7] + 8000bf0: e001 b.n 8000bf6 + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000bf2: f7ff fe0f bl 8000814 + } + + /* Return function status */ + return status; + 8000bf6: 79fb ldrb r3, [r7, #7] +} + 8000bf8: 4618 mov r0, r3 + 8000bfa: 3708 adds r7, #8 + 8000bfc: 46bd mov sp, r7 + 8000bfe: bd80 pop {r7, pc} + +08000c00 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000c00: b580 push {r7, lr} + 8000c02: b084 sub sp, #16 + 8000c04: af00 add r7, sp, #0 + 8000c06: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000c08: 2300 movs r3, #0 + 8000c0a: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 8000c0c: 4b16 ldr r3, [pc, #88] @ (8000c68 ) + 8000c0e: 681b ldr r3, [r3, #0] + 8000c10: 2b00 cmp r3, #0 + 8000c12: d022 beq.n 8000c5a + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 8000c14: 4b15 ldr r3, [pc, #84] @ (8000c6c ) + 8000c16: 681a ldr r2, [r3, #0] + 8000c18: 4b13 ldr r3, [pc, #76] @ (8000c68 ) + 8000c1a: 681b ldr r3, [r3, #0] + 8000c1c: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8000c20: fbb1 f3f3 udiv r3, r1, r3 + 8000c24: fbb2 f3f3 udiv r3, r2, r3 + 8000c28: 4618 mov r0, r3 + 8000c2a: f000 f940 bl 8000eae + 8000c2e: 4603 mov r3, r0 + 8000c30: 2b00 cmp r3, #0 + 8000c32: d10f bne.n 8000c54 + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000c34: 687b ldr r3, [r7, #4] + 8000c36: 2b0f cmp r3, #15 + 8000c38: d809 bhi.n 8000c4e + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000c3a: 2200 movs r2, #0 + 8000c3c: 6879 ldr r1, [r7, #4] + 8000c3e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000c42: f000 f90a bl 8000e5a + uwTickPrio = TickPriority; + 8000c46: 4a0a ldr r2, [pc, #40] @ (8000c70 ) + 8000c48: 687b ldr r3, [r7, #4] + 8000c4a: 6013 str r3, [r2, #0] + 8000c4c: e007 b.n 8000c5e + } + else + { + status = HAL_ERROR; + 8000c4e: 2301 movs r3, #1 + 8000c50: 73fb strb r3, [r7, #15] + 8000c52: e004 b.n 8000c5e + } + } + else + { + status = HAL_ERROR; + 8000c54: 2301 movs r3, #1 + 8000c56: 73fb strb r3, [r7, #15] + 8000c58: e001 b.n 8000c5e + } + } + else + { + status = HAL_ERROR; + 8000c5a: 2301 movs r3, #1 + 8000c5c: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8000c5e: 7bfb ldrb r3, [r7, #15] +} + 8000c60: 4618 mov r0, r3 + 8000c62: 3710 adds r7, #16 + 8000c64: 46bd mov sp, r7 + 8000c66: bd80 pop {r7, pc} + 8000c68: 20000008 .word 0x20000008 + 8000c6c: 20000000 .word 0x20000000 + 8000c70: 20000004 .word 0x20000004 + +08000c74 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000c74: b480 push {r7} + 8000c76: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000c78: 4b05 ldr r3, [pc, #20] @ (8000c90 ) + 8000c7a: 681a ldr r2, [r3, #0] + 8000c7c: 4b05 ldr r3, [pc, #20] @ (8000c94 ) + 8000c7e: 681b ldr r3, [r3, #0] + 8000c80: 4413 add r3, r2 + 8000c82: 4a03 ldr r2, [pc, #12] @ (8000c90 ) + 8000c84: 6013 str r3, [r2, #0] +} + 8000c86: bf00 nop + 8000c88: 46bd mov sp, r7 + 8000c8a: bc80 pop {r7} + 8000c8c: 4770 bx lr + 8000c8e: bf00 nop + 8000c90: 20000100 .word 0x20000100 + 8000c94: 20000008 .word 0x20000008 + +08000c98 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000c98: b480 push {r7} + 8000c9a: af00 add r7, sp, #0 + return uwTick; + 8000c9c: 4b02 ldr r3, [pc, #8] @ (8000ca8 ) + 8000c9e: 681b ldr r3, [r3, #0] +} + 8000ca0: 4618 mov r0, r3 + 8000ca2: 46bd mov sp, r7 + 8000ca4: bc80 pop {r7} + 8000ca6: 4770 bx lr + 8000ca8: 20000100 .word 0x20000100 + +08000cac <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000cac: b480 push {r7} + 8000cae: b085 sub sp, #20 + 8000cb0: af00 add r7, sp, #0 + 8000cb2: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000cb4: 687b ldr r3, [r7, #4] + 8000cb6: f003 0307 and.w r3, r3, #7 + 8000cba: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000cbc: 4b0c ldr r3, [pc, #48] @ (8000cf0 <__NVIC_SetPriorityGrouping+0x44>) + 8000cbe: 68db ldr r3, [r3, #12] + 8000cc0: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000cc2: 68ba ldr r2, [r7, #8] + 8000cc4: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000cc8: 4013 ands r3, r2 + 8000cca: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000ccc: 68fb ldr r3, [r7, #12] + 8000cce: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000cd0: 68bb ldr r3, [r7, #8] + 8000cd2: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000cd4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000cd8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000cdc: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000cde: 4a04 ldr r2, [pc, #16] @ (8000cf0 <__NVIC_SetPriorityGrouping+0x44>) + 8000ce0: 68bb ldr r3, [r7, #8] + 8000ce2: 60d3 str r3, [r2, #12] +} + 8000ce4: bf00 nop + 8000ce6: 3714 adds r7, #20 + 8000ce8: 46bd mov sp, r7 + 8000cea: bc80 pop {r7} + 8000cec: 4770 bx lr + 8000cee: bf00 nop + 8000cf0: e000ed00 .word 0xe000ed00 + +08000cf4 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000cf4: b480 push {r7} + 8000cf6: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000cf8: 4b04 ldr r3, [pc, #16] @ (8000d0c <__NVIC_GetPriorityGrouping+0x18>) + 8000cfa: 68db ldr r3, [r3, #12] + 8000cfc: 0a1b lsrs r3, r3, #8 + 8000cfe: f003 0307 and.w r3, r3, #7 +} + 8000d02: 4618 mov r0, r3 + 8000d04: 46bd mov sp, r7 + 8000d06: bc80 pop {r7} + 8000d08: 4770 bx lr + 8000d0a: bf00 nop + 8000d0c: e000ed00 .word 0xe000ed00 + +08000d10 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000d10: b480 push {r7} + 8000d12: b083 sub sp, #12 + 8000d14: af00 add r7, sp, #0 + 8000d16: 4603 mov r3, r0 + 8000d18: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000d1a: f997 3007 ldrsb.w r3, [r7, #7] + 8000d1e: 2b00 cmp r3, #0 + 8000d20: db0b blt.n 8000d3a <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8000d22: 79fb ldrb r3, [r7, #7] + 8000d24: f003 021f and.w r2, r3, #31 + 8000d28: 4906 ldr r1, [pc, #24] @ (8000d44 <__NVIC_EnableIRQ+0x34>) + 8000d2a: f997 3007 ldrsb.w r3, [r7, #7] + 8000d2e: 095b lsrs r3, r3, #5 + 8000d30: 2001 movs r0, #1 + 8000d32: fa00 f202 lsl.w r2, r0, r2 + 8000d36: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8000d3a: bf00 nop + 8000d3c: 370c adds r7, #12 + 8000d3e: 46bd mov sp, r7 + 8000d40: bc80 pop {r7} + 8000d42: 4770 bx lr + 8000d44: e000e100 .word 0xe000e100 + +08000d48 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000d48: b480 push {r7} + 8000d4a: b083 sub sp, #12 + 8000d4c: af00 add r7, sp, #0 + 8000d4e: 4603 mov r3, r0 + 8000d50: 6039 str r1, [r7, #0] + 8000d52: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000d54: f997 3007 ldrsb.w r3, [r7, #7] + 8000d58: 2b00 cmp r3, #0 + 8000d5a: db0a blt.n 8000d72 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000d5c: 683b ldr r3, [r7, #0] + 8000d5e: b2da uxtb r2, r3 + 8000d60: 490c ldr r1, [pc, #48] @ (8000d94 <__NVIC_SetPriority+0x4c>) + 8000d62: f997 3007 ldrsb.w r3, [r7, #7] + 8000d66: 0112 lsls r2, r2, #4 + 8000d68: b2d2 uxtb r2, r2 + 8000d6a: 440b add r3, r1 + 8000d6c: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000d70: e00a b.n 8000d88 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000d72: 683b ldr r3, [r7, #0] + 8000d74: b2da uxtb r2, r3 + 8000d76: 4908 ldr r1, [pc, #32] @ (8000d98 <__NVIC_SetPriority+0x50>) + 8000d78: 79fb ldrb r3, [r7, #7] + 8000d7a: f003 030f and.w r3, r3, #15 + 8000d7e: 3b04 subs r3, #4 + 8000d80: 0112 lsls r2, r2, #4 + 8000d82: b2d2 uxtb r2, r2 + 8000d84: 440b add r3, r1 + 8000d86: 761a strb r2, [r3, #24] +} + 8000d88: bf00 nop + 8000d8a: 370c adds r7, #12 + 8000d8c: 46bd mov sp, r7 + 8000d8e: bc80 pop {r7} + 8000d90: 4770 bx lr + 8000d92: bf00 nop + 8000d94: e000e100 .word 0xe000e100 + 8000d98: e000ed00 .word 0xe000ed00 + +08000d9c : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000d9c: b480 push {r7} + 8000d9e: b089 sub sp, #36 @ 0x24 + 8000da0: af00 add r7, sp, #0 + 8000da2: 60f8 str r0, [r7, #12] + 8000da4: 60b9 str r1, [r7, #8] + 8000da6: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000da8: 68fb ldr r3, [r7, #12] + 8000daa: f003 0307 and.w r3, r3, #7 + 8000dae: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000db0: 69fb ldr r3, [r7, #28] + 8000db2: f1c3 0307 rsb r3, r3, #7 + 8000db6: 2b04 cmp r3, #4 + 8000db8: bf28 it cs + 8000dba: 2304 movcs r3, #4 + 8000dbc: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000dbe: 69fb ldr r3, [r7, #28] + 8000dc0: 3304 adds r3, #4 + 8000dc2: 2b06 cmp r3, #6 + 8000dc4: d902 bls.n 8000dcc + 8000dc6: 69fb ldr r3, [r7, #28] + 8000dc8: 3b03 subs r3, #3 + 8000dca: e000 b.n 8000dce + 8000dcc: 2300 movs r3, #0 + 8000dce: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000dd0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000dd4: 69bb ldr r3, [r7, #24] + 8000dd6: fa02 f303 lsl.w r3, r2, r3 + 8000dda: 43da mvns r2, r3 + 8000ddc: 68bb ldr r3, [r7, #8] + 8000dde: 401a ands r2, r3 + 8000de0: 697b ldr r3, [r7, #20] + 8000de2: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000de4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000de8: 697b ldr r3, [r7, #20] + 8000dea: fa01 f303 lsl.w r3, r1, r3 + 8000dee: 43d9 mvns r1, r3 + 8000df0: 687b ldr r3, [r7, #4] + 8000df2: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000df4: 4313 orrs r3, r2 + ); +} + 8000df6: 4618 mov r0, r3 + 8000df8: 3724 adds r7, #36 @ 0x24 + 8000dfa: 46bd mov sp, r7 + 8000dfc: bc80 pop {r7} + 8000dfe: 4770 bx lr + +08000e00 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000e00: b580 push {r7, lr} + 8000e02: b082 sub sp, #8 + 8000e04: af00 add r7, sp, #0 + 8000e06: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000e08: 687b ldr r3, [r7, #4] + 8000e0a: 3b01 subs r3, #1 + 8000e0c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000e10: d301 bcc.n 8000e16 + { + return (1UL); /* Reload value impossible */ + 8000e12: 2301 movs r3, #1 + 8000e14: e00f b.n 8000e36 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000e16: 4a0a ldr r2, [pc, #40] @ (8000e40 ) + 8000e18: 687b ldr r3, [r7, #4] + 8000e1a: 3b01 subs r3, #1 + 8000e1c: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000e1e: 210f movs r1, #15 + 8000e20: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000e24: f7ff ff90 bl 8000d48 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000e28: 4b05 ldr r3, [pc, #20] @ (8000e40 ) + 8000e2a: 2200 movs r2, #0 + 8000e2c: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000e2e: 4b04 ldr r3, [pc, #16] @ (8000e40 ) + 8000e30: 2207 movs r2, #7 + 8000e32: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000e34: 2300 movs r3, #0 +} + 8000e36: 4618 mov r0, r3 + 8000e38: 3708 adds r7, #8 + 8000e3a: 46bd mov sp, r7 + 8000e3c: bd80 pop {r7, pc} + 8000e3e: bf00 nop + 8000e40: e000e010 .word 0xe000e010 + +08000e44 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000e44: b580 push {r7, lr} + 8000e46: b082 sub sp, #8 + 8000e48: af00 add r7, sp, #0 + 8000e4a: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8000e4c: 6878 ldr r0, [r7, #4] + 8000e4e: f7ff ff2d bl 8000cac <__NVIC_SetPriorityGrouping> +} + 8000e52: bf00 nop + 8000e54: 3708 adds r7, #8 + 8000e56: 46bd mov sp, r7 + 8000e58: bd80 pop {r7, pc} + +08000e5a : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000e5a: b580 push {r7, lr} + 8000e5c: b086 sub sp, #24 + 8000e5e: af00 add r7, sp, #0 + 8000e60: 4603 mov r3, r0 + 8000e62: 60b9 str r1, [r7, #8] + 8000e64: 607a str r2, [r7, #4] + 8000e66: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8000e68: 2300 movs r3, #0 + 8000e6a: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8000e6c: f7ff ff42 bl 8000cf4 <__NVIC_GetPriorityGrouping> + 8000e70: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8000e72: 687a ldr r2, [r7, #4] + 8000e74: 68b9 ldr r1, [r7, #8] + 8000e76: 6978 ldr r0, [r7, #20] + 8000e78: f7ff ff90 bl 8000d9c + 8000e7c: 4602 mov r2, r0 + 8000e7e: f997 300f ldrsb.w r3, [r7, #15] + 8000e82: 4611 mov r1, r2 + 8000e84: 4618 mov r0, r3 + 8000e86: f7ff ff5f bl 8000d48 <__NVIC_SetPriority> +} + 8000e8a: bf00 nop + 8000e8c: 3718 adds r7, #24 + 8000e8e: 46bd mov sp, r7 + 8000e90: bd80 pop {r7, pc} + +08000e92 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000e92: b580 push {r7, lr} + 8000e94: b082 sub sp, #8 + 8000e96: af00 add r7, sp, #0 + 8000e98: 4603 mov r3, r0 + 8000e9a: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8000e9c: f997 3007 ldrsb.w r3, [r7, #7] + 8000ea0: 4618 mov r0, r3 + 8000ea2: f7ff ff35 bl 8000d10 <__NVIC_EnableIRQ> +} + 8000ea6: bf00 nop + 8000ea8: 3708 adds r7, #8 + 8000eaa: 46bd mov sp, r7 + 8000eac: bd80 pop {r7, pc} + +08000eae : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000eae: b580 push {r7, lr} + 8000eb0: b082 sub sp, #8 + 8000eb2: af00 add r7, sp, #0 + 8000eb4: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000eb6: 6878 ldr r0, [r7, #4] + 8000eb8: f7ff ffa2 bl 8000e00 + 8000ebc: 4603 mov r3, r0 +} + 8000ebe: 4618 mov r0, r3 + 8000ec0: 3708 adds r7, #8 + 8000ec2: 46bd mov sp, r7 + 8000ec4: bd80 pop {r7, pc} + ... + +08000ec8 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000ec8: b480 push {r7} + 8000eca: b087 sub sp, #28 + 8000ecc: af00 add r7, sp, #0 + 8000ece: 6078 str r0, [r7, #4] + 8000ed0: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8000ed2: 2300 movs r3, #0 + 8000ed4: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8000ed6: 2300 movs r3, #0 + 8000ed8: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 8000eda: 2300 movs r3, #0 + 8000edc: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8000ede: e160 b.n 80011a2 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8000ee0: 683b ldr r3, [r7, #0] + 8000ee2: 681a ldr r2, [r3, #0] + 8000ee4: 2101 movs r1, #1 + 8000ee6: 697b ldr r3, [r7, #20] + 8000ee8: fa01 f303 lsl.w r3, r1, r3 + 8000eec: 4013 ands r3, r2 + 8000eee: 60fb str r3, [r7, #12] + + if (iocurrent) + 8000ef0: 68fb ldr r3, [r7, #12] + 8000ef2: 2b00 cmp r3, #0 + 8000ef4: f000 8152 beq.w 800119c + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000ef8: 683b ldr r3, [r7, #0] + 8000efa: 685b ldr r3, [r3, #4] + 8000efc: f003 0303 and.w r3, r3, #3 + 8000f00: 2b01 cmp r3, #1 + 8000f02: d005 beq.n 8000f10 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8000f04: 683b ldr r3, [r7, #0] + 8000f06: 685b ldr r3, [r3, #4] + 8000f08: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000f0c: 2b02 cmp r3, #2 + 8000f0e: d130 bne.n 8000f72 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8000f10: 687b ldr r3, [r7, #4] + 8000f12: 689b ldr r3, [r3, #8] + 8000f14: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8000f16: 697b ldr r3, [r7, #20] + 8000f18: 005b lsls r3, r3, #1 + 8000f1a: 2203 movs r2, #3 + 8000f1c: fa02 f303 lsl.w r3, r2, r3 + 8000f20: 43db mvns r3, r3 + 8000f22: 693a ldr r2, [r7, #16] + 8000f24: 4013 ands r3, r2 + 8000f26: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8000f28: 683b ldr r3, [r7, #0] + 8000f2a: 68da ldr r2, [r3, #12] + 8000f2c: 697b ldr r3, [r7, #20] + 8000f2e: 005b lsls r3, r3, #1 + 8000f30: fa02 f303 lsl.w r3, r2, r3 + 8000f34: 693a ldr r2, [r7, #16] + 8000f36: 4313 orrs r3, r2 + 8000f38: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8000f3a: 687b ldr r3, [r7, #4] + 8000f3c: 693a ldr r2, [r7, #16] + 8000f3e: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8000f40: 687b ldr r3, [r7, #4] + 8000f42: 685b ldr r3, [r3, #4] + 8000f44: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 8000f46: 2201 movs r2, #1 + 8000f48: 697b ldr r3, [r7, #20] + 8000f4a: fa02 f303 lsl.w r3, r2, r3 + 8000f4e: 43db mvns r3, r3 + 8000f50: 693a ldr r2, [r7, #16] + 8000f52: 4013 ands r3, r2 + 8000f54: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8000f56: 683b ldr r3, [r7, #0] + 8000f58: 685b ldr r3, [r3, #4] + 8000f5a: 091b lsrs r3, r3, #4 + 8000f5c: f003 0201 and.w r2, r3, #1 + 8000f60: 697b ldr r3, [r7, #20] + 8000f62: fa02 f303 lsl.w r3, r2, r3 + 8000f66: 693a ldr r2, [r7, #16] + 8000f68: 4313 orrs r3, r2 + 8000f6a: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8000f6c: 687b ldr r3, [r7, #4] + 8000f6e: 693a ldr r2, [r7, #16] + 8000f70: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8000f72: 683b ldr r3, [r7, #0] + 8000f74: 685b ldr r3, [r3, #4] + 8000f76: f003 0303 and.w r3, r3, #3 + 8000f7a: 2b03 cmp r3, #3 + 8000f7c: d017 beq.n 8000fae + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8000f7e: 687b ldr r3, [r7, #4] + 8000f80: 68db ldr r3, [r3, #12] + 8000f82: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 8000f84: 697b ldr r3, [r7, #20] + 8000f86: 005b lsls r3, r3, #1 + 8000f88: 2203 movs r2, #3 + 8000f8a: fa02 f303 lsl.w r3, r2, r3 + 8000f8e: 43db mvns r3, r3 + 8000f90: 693a ldr r2, [r7, #16] + 8000f92: 4013 ands r3, r2 + 8000f94: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 8000f96: 683b ldr r3, [r7, #0] + 8000f98: 689a ldr r2, [r3, #8] + 8000f9a: 697b ldr r3, [r7, #20] + 8000f9c: 005b lsls r3, r3, #1 + 8000f9e: fa02 f303 lsl.w r3, r2, r3 + 8000fa2: 693a ldr r2, [r7, #16] + 8000fa4: 4313 orrs r3, r2 + 8000fa6: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8000fa8: 687b ldr r3, [r7, #4] + 8000faa: 693a ldr r2, [r7, #16] + 8000fac: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8000fae: 683b ldr r3, [r7, #0] + 8000fb0: 685b ldr r3, [r3, #4] + 8000fb2: f003 0303 and.w r3, r3, #3 + 8000fb6: 2b02 cmp r3, #2 + 8000fb8: d123 bne.n 8001002 + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 8000fba: 697b ldr r3, [r7, #20] + 8000fbc: 08da lsrs r2, r3, #3 + 8000fbe: 687b ldr r3, [r7, #4] + 8000fc0: 3208 adds r2, #8 + 8000fc2: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8000fc6: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 8000fc8: 697b ldr r3, [r7, #20] + 8000fca: f003 0307 and.w r3, r3, #7 + 8000fce: 009b lsls r3, r3, #2 + 8000fd0: 220f movs r2, #15 + 8000fd2: fa02 f303 lsl.w r3, r2, r3 + 8000fd6: 43db mvns r3, r3 + 8000fd8: 693a ldr r2, [r7, #16] + 8000fda: 4013 ands r3, r2 + 8000fdc: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8000fde: 683b ldr r3, [r7, #0] + 8000fe0: 691a ldr r2, [r3, #16] + 8000fe2: 697b ldr r3, [r7, #20] + 8000fe4: f003 0307 and.w r3, r3, #7 + 8000fe8: 009b lsls r3, r3, #2 + 8000fea: fa02 f303 lsl.w r3, r2, r3 + 8000fee: 693a ldr r2, [r7, #16] + 8000ff0: 4313 orrs r3, r2 + 8000ff2: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 8000ff4: 697b ldr r3, [r7, #20] + 8000ff6: 08da lsrs r2, r3, #3 + 8000ff8: 687b ldr r3, [r7, #4] + 8000ffa: 3208 adds r2, #8 + 8000ffc: 6939 ldr r1, [r7, #16] + 8000ffe: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8001002: 687b ldr r3, [r7, #4] + 8001004: 681b ldr r3, [r3, #0] + 8001006: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8001008: 697b ldr r3, [r7, #20] + 800100a: 005b lsls r3, r3, #1 + 800100c: 2203 movs r2, #3 + 800100e: fa02 f303 lsl.w r3, r2, r3 + 8001012: 43db mvns r3, r3 + 8001014: 693a ldr r2, [r7, #16] + 8001016: 4013 ands r3, r2 + 8001018: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 800101a: 683b ldr r3, [r7, #0] + 800101c: 685b ldr r3, [r3, #4] + 800101e: f003 0203 and.w r2, r3, #3 + 8001022: 697b ldr r3, [r7, #20] + 8001024: 005b lsls r3, r3, #1 + 8001026: fa02 f303 lsl.w r3, r2, r3 + 800102a: 693a ldr r2, [r7, #16] + 800102c: 4313 orrs r3, r2 + 800102e: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8001030: 687b ldr r3, [r7, #4] + 8001032: 693a ldr r2, [r7, #16] + 8001034: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8001036: 683b ldr r3, [r7, #0] + 8001038: 685b ldr r3, [r3, #4] + 800103a: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 800103e: 2b00 cmp r3, #0 + 8001040: f000 80ac beq.w 800119c + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8001044: 4b5e ldr r3, [pc, #376] @ (80011c0 ) + 8001046: 6a1b ldr r3, [r3, #32] + 8001048: 4a5d ldr r2, [pc, #372] @ (80011c0 ) + 800104a: f043 0301 orr.w r3, r3, #1 + 800104e: 6213 str r3, [r2, #32] + 8001050: 4b5b ldr r3, [pc, #364] @ (80011c0 ) + 8001052: 6a1b ldr r3, [r3, #32] + 8001054: f003 0301 and.w r3, r3, #1 + 8001058: 60bb str r3, [r7, #8] + 800105a: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 800105c: 4a59 ldr r2, [pc, #356] @ (80011c4 ) + 800105e: 697b ldr r3, [r7, #20] + 8001060: 089b lsrs r3, r3, #2 + 8001062: 3302 adds r3, #2 + 8001064: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001068: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 800106a: 697b ldr r3, [r7, #20] + 800106c: f003 0303 and.w r3, r3, #3 + 8001070: 009b lsls r3, r3, #2 + 8001072: 220f movs r2, #15 + 8001074: fa02 f303 lsl.w r3, r2, r3 + 8001078: 43db mvns r3, r3 + 800107a: 693a ldr r2, [r7, #16] + 800107c: 4013 ands r3, r2 + 800107e: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 8001080: 687b ldr r3, [r7, #4] + 8001082: 4a51 ldr r2, [pc, #324] @ (80011c8 ) + 8001084: 4293 cmp r3, r2 + 8001086: d025 beq.n 80010d4 + 8001088: 687b ldr r3, [r7, #4] + 800108a: 4a50 ldr r2, [pc, #320] @ (80011cc ) + 800108c: 4293 cmp r3, r2 + 800108e: d01f beq.n 80010d0 + 8001090: 687b ldr r3, [r7, #4] + 8001092: 4a4f ldr r2, [pc, #316] @ (80011d0 ) + 8001094: 4293 cmp r3, r2 + 8001096: d019 beq.n 80010cc + 8001098: 687b ldr r3, [r7, #4] + 800109a: 4a4e ldr r2, [pc, #312] @ (80011d4 ) + 800109c: 4293 cmp r3, r2 + 800109e: d013 beq.n 80010c8 + 80010a0: 687b ldr r3, [r7, #4] + 80010a2: 4a4d ldr r2, [pc, #308] @ (80011d8 ) + 80010a4: 4293 cmp r3, r2 + 80010a6: d00d beq.n 80010c4 + 80010a8: 687b ldr r3, [r7, #4] + 80010aa: 4a4c ldr r2, [pc, #304] @ (80011dc ) + 80010ac: 4293 cmp r3, r2 + 80010ae: d007 beq.n 80010c0 + 80010b0: 687b ldr r3, [r7, #4] + 80010b2: 4a4b ldr r2, [pc, #300] @ (80011e0 ) + 80010b4: 4293 cmp r3, r2 + 80010b6: d101 bne.n 80010bc + 80010b8: 2306 movs r3, #6 + 80010ba: e00c b.n 80010d6 + 80010bc: 2307 movs r3, #7 + 80010be: e00a b.n 80010d6 + 80010c0: 2305 movs r3, #5 + 80010c2: e008 b.n 80010d6 + 80010c4: 2304 movs r3, #4 + 80010c6: e006 b.n 80010d6 + 80010c8: 2303 movs r3, #3 + 80010ca: e004 b.n 80010d6 + 80010cc: 2302 movs r3, #2 + 80010ce: e002 b.n 80010d6 + 80010d0: 2301 movs r3, #1 + 80010d2: e000 b.n 80010d6 + 80010d4: 2300 movs r3, #0 + 80010d6: 697a ldr r2, [r7, #20] + 80010d8: f002 0203 and.w r2, r2, #3 + 80010dc: 0092 lsls r2, r2, #2 + 80010de: 4093 lsls r3, r2 + 80010e0: 693a ldr r2, [r7, #16] + 80010e2: 4313 orrs r3, r2 + 80010e4: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 80010e6: 4937 ldr r1, [pc, #220] @ (80011c4 ) + 80010e8: 697b ldr r3, [r7, #20] + 80010ea: 089b lsrs r3, r3, #2 + 80010ec: 3302 adds r3, #2 + 80010ee: 693a ldr r2, [r7, #16] + 80010f0: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 80010f4: 4b3b ldr r3, [pc, #236] @ (80011e4 ) + 80010f6: 689b ldr r3, [r3, #8] + 80010f8: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 80010fa: 68fb ldr r3, [r7, #12] + 80010fc: 43db mvns r3, r3 + 80010fe: 693a ldr r2, [r7, #16] + 8001100: 4013 ands r3, r2 + 8001102: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8001104: 683b ldr r3, [r7, #0] + 8001106: 685b ldr r3, [r3, #4] + 8001108: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 800110c: 2b00 cmp r3, #0 + 800110e: d003 beq.n 8001118 + { + SET_BIT(temp, iocurrent); + 8001110: 693a ldr r2, [r7, #16] + 8001112: 68fb ldr r3, [r7, #12] + 8001114: 4313 orrs r3, r2 + 8001116: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 8001118: 4a32 ldr r2, [pc, #200] @ (80011e4 ) + 800111a: 693b ldr r3, [r7, #16] + 800111c: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 800111e: 4b31 ldr r3, [pc, #196] @ (80011e4 ) + 8001120: 68db ldr r3, [r3, #12] + 8001122: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001124: 68fb ldr r3, [r7, #12] + 8001126: 43db mvns r3, r3 + 8001128: 693a ldr r2, [r7, #16] + 800112a: 4013 ands r3, r2 + 800112c: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 800112e: 683b ldr r3, [r7, #0] + 8001130: 685b ldr r3, [r3, #4] + 8001132: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8001136: 2b00 cmp r3, #0 + 8001138: d003 beq.n 8001142 + { + SET_BIT(temp, iocurrent); + 800113a: 693a ldr r2, [r7, #16] + 800113c: 68fb ldr r3, [r7, #12] + 800113e: 4313 orrs r3, r2 + 8001140: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 8001142: 4a28 ldr r2, [pc, #160] @ (80011e4 ) + 8001144: 693b ldr r3, [r7, #16] + 8001146: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8001148: 4b26 ldr r3, [pc, #152] @ (80011e4 ) + 800114a: 685b ldr r3, [r3, #4] + 800114c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 800114e: 68fb ldr r3, [r7, #12] + 8001150: 43db mvns r3, r3 + 8001152: 693a ldr r2, [r7, #16] + 8001154: 4013 ands r3, r2 + 8001156: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8001158: 683b ldr r3, [r7, #0] + 800115a: 685b ldr r3, [r3, #4] + 800115c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001160: 2b00 cmp r3, #0 + 8001162: d003 beq.n 800116c + { + SET_BIT(temp, iocurrent); + 8001164: 693a ldr r2, [r7, #16] + 8001166: 68fb ldr r3, [r7, #12] + 8001168: 4313 orrs r3, r2 + 800116a: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 800116c: 4a1d ldr r2, [pc, #116] @ (80011e4 ) + 800116e: 693b ldr r3, [r7, #16] + 8001170: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8001172: 4b1c ldr r3, [pc, #112] @ (80011e4 ) + 8001174: 681b ldr r3, [r3, #0] + 8001176: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001178: 68fb ldr r3, [r7, #12] + 800117a: 43db mvns r3, r3 + 800117c: 693a ldr r2, [r7, #16] + 800117e: 4013 ands r3, r2 + 8001180: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 8001182: 683b ldr r3, [r7, #0] + 8001184: 685b ldr r3, [r3, #4] + 8001186: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 800118a: 2b00 cmp r3, #0 + 800118c: d003 beq.n 8001196 + { + SET_BIT(temp, iocurrent); + 800118e: 693a ldr r2, [r7, #16] + 8001190: 68fb ldr r3, [r7, #12] + 8001192: 4313 orrs r3, r2 + 8001194: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 8001196: 4a13 ldr r2, [pc, #76] @ (80011e4 ) + 8001198: 693b ldr r3, [r7, #16] + 800119a: 6013 str r3, [r2, #0] + } + } + + position++; + 800119c: 697b ldr r3, [r7, #20] + 800119e: 3301 adds r3, #1 + 80011a0: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 80011a2: 683b ldr r3, [r7, #0] + 80011a4: 681a ldr r2, [r3, #0] + 80011a6: 697b ldr r3, [r7, #20] + 80011a8: fa22 f303 lsr.w r3, r2, r3 + 80011ac: 2b00 cmp r3, #0 + 80011ae: f47f ae97 bne.w 8000ee0 + } +} + 80011b2: bf00 nop + 80011b4: bf00 nop + 80011b6: 371c adds r7, #28 + 80011b8: 46bd mov sp, r7 + 80011ba: bc80 pop {r7} + 80011bc: 4770 bx lr + 80011be: bf00 nop + 80011c0: 40023800 .word 0x40023800 + 80011c4: 40010000 .word 0x40010000 + 80011c8: 40020000 .word 0x40020000 + 80011cc: 40020400 .word 0x40020400 + 80011d0: 40020800 .word 0x40020800 + 80011d4: 40020c00 .word 0x40020c00 + 80011d8: 40021000 .word 0x40021000 + 80011dc: 40021400 .word 0x40021400 + 80011e0: 40021800 .word 0x40021800 + 80011e4: 40010400 .word 0x40010400 + +080011e8 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80011e8: b480 push {r7} + 80011ea: b083 sub sp, #12 + 80011ec: af00 add r7, sp, #0 + 80011ee: 6078 str r0, [r7, #4] + 80011f0: 460b mov r3, r1 + 80011f2: 807b strh r3, [r7, #2] + 80011f4: 4613 mov r3, r2 + 80011f6: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 80011f8: 787b ldrb r3, [r7, #1] + 80011fa: 2b00 cmp r3, #0 + 80011fc: d003 beq.n 8001206 + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 80011fe: 887a ldrh r2, [r7, #2] + 8001200: 687b ldr r3, [r7, #4] + 8001202: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 8001204: e003 b.n 800120e + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 8001206: 887b ldrh r3, [r7, #2] + 8001208: 041a lsls r2, r3, #16 + 800120a: 687b ldr r3, [r7, #4] + 800120c: 619a str r2, [r3, #24] +} + 800120e: bf00 nop + 8001210: 370c adds r7, #12 + 8001212: 46bd mov sp, r7 + 8001214: bc80 pop {r7} + 8001216: 4770 bx lr + +08001218 : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 8001218: b580 push {r7, lr} + 800121a: b082 sub sp, #8 + 800121c: af00 add r7, sp, #0 + 800121e: 4603 mov r3, r0 + 8001220: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 8001222: 4b08 ldr r3, [pc, #32] @ (8001244 ) + 8001224: 695a ldr r2, [r3, #20] + 8001226: 88fb ldrh r3, [r7, #6] + 8001228: 4013 ands r3, r2 + 800122a: 2b00 cmp r3, #0 + 800122c: d006 beq.n 800123c + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 800122e: 4a05 ldr r2, [pc, #20] @ (8001244 ) + 8001230: 88fb ldrh r3, [r7, #6] + 8001232: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 8001234: 88fb ldrh r3, [r7, #6] + 8001236: 4618 mov r0, r3 + 8001238: f000 f806 bl 8001248 + } +} + 800123c: bf00 nop + 800123e: 3708 adds r7, #8 + 8001240: 46bd mov sp, r7 + 8001242: bd80 pop {r7, pc} + 8001244: 40010400 .word 0x40010400 + +08001248 : + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 8001248: b480 push {r7} + 800124a: b083 sub sp, #12 + 800124c: af00 add r7, sp, #0 + 800124e: 4603 mov r3, r0 + 8001250: 80fb strh r3, [r7, #6] + UNUSED(GPIO_Pin); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + 8001252: bf00 nop + 8001254: 370c adds r7, #12 + 8001256: 46bd mov sp, r7 + 8001258: bc80 pop {r7} + 800125a: 4770 bx lr + +0800125c : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 800125c: b580 push {r7, lr} + 800125e: b088 sub sp, #32 + 8001260: af00 add r7, sp, #0 + 8001262: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 8001264: 687b ldr r3, [r7, #4] + 8001266: 2b00 cmp r3, #0 + 8001268: d101 bne.n 800126e + { + return HAL_ERROR; + 800126a: 2301 movs r3, #1 + 800126c: e31d b.n 80018aa + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 800126e: 4b94 ldr r3, [pc, #592] @ (80014c0 ) + 8001270: 689b ldr r3, [r3, #8] + 8001272: f003 030c and.w r3, r3, #12 + 8001276: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8001278: 4b91 ldr r3, [pc, #580] @ (80014c0 ) + 800127a: 689b ldr r3, [r3, #8] + 800127c: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001280: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8001282: 687b ldr r3, [r7, #4] + 8001284: 681b ldr r3, [r3, #0] + 8001286: f003 0301 and.w r3, r3, #1 + 800128a: 2b00 cmp r3, #0 + 800128c: d07b beq.n 8001386 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 800128e: 69bb ldr r3, [r7, #24] + 8001290: 2b08 cmp r3, #8 + 8001292: d006 beq.n 80012a2 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8001294: 69bb ldr r3, [r7, #24] + 8001296: 2b0c cmp r3, #12 + 8001298: d10f bne.n 80012ba + 800129a: 697b ldr r3, [r7, #20] + 800129c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80012a0: d10b bne.n 80012ba + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80012a2: 4b87 ldr r3, [pc, #540] @ (80014c0 ) + 80012a4: 681b ldr r3, [r3, #0] + 80012a6: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80012aa: 2b00 cmp r3, #0 + 80012ac: d06a beq.n 8001384 + 80012ae: 687b ldr r3, [r7, #4] + 80012b0: 685b ldr r3, [r3, #4] + 80012b2: 2b00 cmp r3, #0 + 80012b4: d166 bne.n 8001384 + { + return HAL_ERROR; + 80012b6: 2301 movs r3, #1 + 80012b8: e2f7 b.n 80018aa + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80012ba: 687b ldr r3, [r7, #4] + 80012bc: 685b ldr r3, [r3, #4] + 80012be: 2b01 cmp r3, #1 + 80012c0: d106 bne.n 80012d0 + 80012c2: 4b7f ldr r3, [pc, #508] @ (80014c0 ) + 80012c4: 681b ldr r3, [r3, #0] + 80012c6: 4a7e ldr r2, [pc, #504] @ (80014c0 ) + 80012c8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80012cc: 6013 str r3, [r2, #0] + 80012ce: e02d b.n 800132c + 80012d0: 687b ldr r3, [r7, #4] + 80012d2: 685b ldr r3, [r3, #4] + 80012d4: 2b00 cmp r3, #0 + 80012d6: d10c bne.n 80012f2 + 80012d8: 4b79 ldr r3, [pc, #484] @ (80014c0 ) + 80012da: 681b ldr r3, [r3, #0] + 80012dc: 4a78 ldr r2, [pc, #480] @ (80014c0 ) + 80012de: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80012e2: 6013 str r3, [r2, #0] + 80012e4: 4b76 ldr r3, [pc, #472] @ (80014c0 ) + 80012e6: 681b ldr r3, [r3, #0] + 80012e8: 4a75 ldr r2, [pc, #468] @ (80014c0 ) + 80012ea: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 80012ee: 6013 str r3, [r2, #0] + 80012f0: e01c b.n 800132c + 80012f2: 687b ldr r3, [r7, #4] + 80012f4: 685b ldr r3, [r3, #4] + 80012f6: 2b05 cmp r3, #5 + 80012f8: d10c bne.n 8001314 + 80012fa: 4b71 ldr r3, [pc, #452] @ (80014c0 ) + 80012fc: 681b ldr r3, [r3, #0] + 80012fe: 4a70 ldr r2, [pc, #448] @ (80014c0 ) + 8001300: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001304: 6013 str r3, [r2, #0] + 8001306: 4b6e ldr r3, [pc, #440] @ (80014c0 ) + 8001308: 681b ldr r3, [r3, #0] + 800130a: 4a6d ldr r2, [pc, #436] @ (80014c0 ) + 800130c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001310: 6013 str r3, [r2, #0] + 8001312: e00b b.n 800132c + 8001314: 4b6a ldr r3, [pc, #424] @ (80014c0 ) + 8001316: 681b ldr r3, [r3, #0] + 8001318: 4a69 ldr r2, [pc, #420] @ (80014c0 ) + 800131a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800131e: 6013 str r3, [r2, #0] + 8001320: 4b67 ldr r3, [pc, #412] @ (80014c0 ) + 8001322: 681b ldr r3, [r3, #0] + 8001324: 4a66 ldr r2, [pc, #408] @ (80014c0 ) + 8001326: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 800132a: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 800132c: 687b ldr r3, [r7, #4] + 800132e: 685b ldr r3, [r3, #4] + 8001330: 2b00 cmp r3, #0 + 8001332: d013 beq.n 800135c + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001334: f7ff fcb0 bl 8000c98 + 8001338: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800133a: e008 b.n 800134e + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 800133c: f7ff fcac bl 8000c98 + 8001340: 4602 mov r2, r0 + 8001342: 693b ldr r3, [r7, #16] + 8001344: 1ad3 subs r3, r2, r3 + 8001346: 2b64 cmp r3, #100 @ 0x64 + 8001348: d901 bls.n 800134e + { + return HAL_TIMEOUT; + 800134a: 2303 movs r3, #3 + 800134c: e2ad b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800134e: 4b5c ldr r3, [pc, #368] @ (80014c0 ) + 8001350: 681b ldr r3, [r3, #0] + 8001352: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001356: 2b00 cmp r3, #0 + 8001358: d0f0 beq.n 800133c + 800135a: e014 b.n 8001386 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800135c: f7ff fc9c bl 8000c98 + 8001360: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 8001362: e008 b.n 8001376 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001364: f7ff fc98 bl 8000c98 + 8001368: 4602 mov r2, r0 + 800136a: 693b ldr r3, [r7, #16] + 800136c: 1ad3 subs r3, r2, r3 + 800136e: 2b64 cmp r3, #100 @ 0x64 + 8001370: d901 bls.n 8001376 + { + return HAL_TIMEOUT; + 8001372: 2303 movs r3, #3 + 8001374: e299 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 8001376: 4b52 ldr r3, [pc, #328] @ (80014c0 ) + 8001378: 681b ldr r3, [r3, #0] + 800137a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800137e: 2b00 cmp r3, #0 + 8001380: d1f0 bne.n 8001364 + 8001382: e000 b.n 8001386 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001384: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8001386: 687b ldr r3, [r7, #4] + 8001388: 681b ldr r3, [r3, #0] + 800138a: f003 0302 and.w r3, r3, #2 + 800138e: 2b00 cmp r3, #0 + 8001390: d05a beq.n 8001448 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 8001392: 69bb ldr r3, [r7, #24] + 8001394: 2b04 cmp r3, #4 + 8001396: d005 beq.n 80013a4 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8001398: 69bb ldr r3, [r7, #24] + 800139a: 2b0c cmp r3, #12 + 800139c: d119 bne.n 80013d2 + 800139e: 697b ldr r3, [r7, #20] + 80013a0: 2b00 cmp r3, #0 + 80013a2: d116 bne.n 80013d2 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80013a4: 4b46 ldr r3, [pc, #280] @ (80014c0 ) + 80013a6: 681b ldr r3, [r3, #0] + 80013a8: f003 0302 and.w r3, r3, #2 + 80013ac: 2b00 cmp r3, #0 + 80013ae: d005 beq.n 80013bc + 80013b0: 687b ldr r3, [r7, #4] + 80013b2: 68db ldr r3, [r3, #12] + 80013b4: 2b01 cmp r3, #1 + 80013b6: d001 beq.n 80013bc + { + return HAL_ERROR; + 80013b8: 2301 movs r3, #1 + 80013ba: e276 b.n 80018aa + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80013bc: 4b40 ldr r3, [pc, #256] @ (80014c0 ) + 80013be: 685b ldr r3, [r3, #4] + 80013c0: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 80013c4: 687b ldr r3, [r7, #4] + 80013c6: 691b ldr r3, [r3, #16] + 80013c8: 021b lsls r3, r3, #8 + 80013ca: 493d ldr r1, [pc, #244] @ (80014c0 ) + 80013cc: 4313 orrs r3, r2 + 80013ce: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80013d0: e03a b.n 8001448 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 80013d2: 687b ldr r3, [r7, #4] + 80013d4: 68db ldr r3, [r3, #12] + 80013d6: 2b00 cmp r3, #0 + 80013d8: d020 beq.n 800141c + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 80013da: 4b3a ldr r3, [pc, #232] @ (80014c4 ) + 80013dc: 2201 movs r2, #1 + 80013de: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80013e0: f7ff fc5a bl 8000c98 + 80013e4: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80013e6: e008 b.n 80013fa + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80013e8: f7ff fc56 bl 8000c98 + 80013ec: 4602 mov r2, r0 + 80013ee: 693b ldr r3, [r7, #16] + 80013f0: 1ad3 subs r3, r2, r3 + 80013f2: 2b02 cmp r3, #2 + 80013f4: d901 bls.n 80013fa + { + return HAL_TIMEOUT; + 80013f6: 2303 movs r3, #3 + 80013f8: e257 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80013fa: 4b31 ldr r3, [pc, #196] @ (80014c0 ) + 80013fc: 681b ldr r3, [r3, #0] + 80013fe: f003 0302 and.w r3, r3, #2 + 8001402: 2b00 cmp r3, #0 + 8001404: d0f0 beq.n 80013e8 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001406: 4b2e ldr r3, [pc, #184] @ (80014c0 ) + 8001408: 685b ldr r3, [r3, #4] + 800140a: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 800140e: 687b ldr r3, [r7, #4] + 8001410: 691b ldr r3, [r3, #16] + 8001412: 021b lsls r3, r3, #8 + 8001414: 492a ldr r1, [pc, #168] @ (80014c0 ) + 8001416: 4313 orrs r3, r2 + 8001418: 604b str r3, [r1, #4] + 800141a: e015 b.n 8001448 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 800141c: 4b29 ldr r3, [pc, #164] @ (80014c4 ) + 800141e: 2200 movs r2, #0 + 8001420: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001422: f7ff fc39 bl 8000c98 + 8001426: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001428: e008 b.n 800143c + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 800142a: f7ff fc35 bl 8000c98 + 800142e: 4602 mov r2, r0 + 8001430: 693b ldr r3, [r7, #16] + 8001432: 1ad3 subs r3, r2, r3 + 8001434: 2b02 cmp r3, #2 + 8001436: d901 bls.n 800143c + { + return HAL_TIMEOUT; + 8001438: 2303 movs r3, #3 + 800143a: e236 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 800143c: 4b20 ldr r3, [pc, #128] @ (80014c0 ) + 800143e: 681b ldr r3, [r3, #0] + 8001440: f003 0302 and.w r3, r3, #2 + 8001444: 2b00 cmp r3, #0 + 8001446: d1f0 bne.n 800142a + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8001448: 687b ldr r3, [r7, #4] + 800144a: 681b ldr r3, [r3, #0] + 800144c: f003 0310 and.w r3, r3, #16 + 8001450: 2b00 cmp r3, #0 + 8001452: f000 80b8 beq.w 80015c6 + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 8001456: 69bb ldr r3, [r7, #24] + 8001458: 2b00 cmp r3, #0 + 800145a: d170 bne.n 800153e + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 800145c: 4b18 ldr r3, [pc, #96] @ (80014c0 ) + 800145e: 681b ldr r3, [r3, #0] + 8001460: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001464: 2b00 cmp r3, #0 + 8001466: d005 beq.n 8001474 + 8001468: 687b ldr r3, [r7, #4] + 800146a: 699b ldr r3, [r3, #24] + 800146c: 2b00 cmp r3, #0 + 800146e: d101 bne.n 8001474 + { + return HAL_ERROR; + 8001470: 2301 movs r3, #1 + 8001472: e21a b.n 80018aa + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 8001474: 687b ldr r3, [r7, #4] + 8001476: 6a1a ldr r2, [r3, #32] + 8001478: 4b11 ldr r3, [pc, #68] @ (80014c0 ) + 800147a: 685b ldr r3, [r3, #4] + 800147c: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 8001480: 429a cmp r2, r3 + 8001482: d921 bls.n 80014c8 + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001484: 687b ldr r3, [r7, #4] + 8001486: 6a1b ldr r3, [r3, #32] + 8001488: 4618 mov r0, r3 + 800148a: f000 fc09 bl 8001ca0 + 800148e: 4603 mov r3, r0 + 8001490: 2b00 cmp r3, #0 + 8001492: d001 beq.n 8001498 + { + return HAL_ERROR; + 8001494: 2301 movs r3, #1 + 8001496: e208 b.n 80018aa + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001498: 4b09 ldr r3, [pc, #36] @ (80014c0 ) + 800149a: 685b ldr r3, [r3, #4] + 800149c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80014a0: 687b ldr r3, [r7, #4] + 80014a2: 6a1b ldr r3, [r3, #32] + 80014a4: 4906 ldr r1, [pc, #24] @ (80014c0 ) + 80014a6: 4313 orrs r3, r2 + 80014a8: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80014aa: 4b05 ldr r3, [pc, #20] @ (80014c0 ) + 80014ac: 685b ldr r3, [r3, #4] + 80014ae: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80014b2: 687b ldr r3, [r7, #4] + 80014b4: 69db ldr r3, [r3, #28] + 80014b6: 061b lsls r3, r3, #24 + 80014b8: 4901 ldr r1, [pc, #4] @ (80014c0 ) + 80014ba: 4313 orrs r3, r2 + 80014bc: 604b str r3, [r1, #4] + 80014be: e020 b.n 8001502 + 80014c0: 40023800 .word 0x40023800 + 80014c4: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80014c8: 4b99 ldr r3, [pc, #612] @ (8001730 ) + 80014ca: 685b ldr r3, [r3, #4] + 80014cc: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80014d0: 687b ldr r3, [r7, #4] + 80014d2: 6a1b ldr r3, [r3, #32] + 80014d4: 4996 ldr r1, [pc, #600] @ (8001730 ) + 80014d6: 4313 orrs r3, r2 + 80014d8: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80014da: 4b95 ldr r3, [pc, #596] @ (8001730 ) + 80014dc: 685b ldr r3, [r3, #4] + 80014de: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80014e2: 687b ldr r3, [r7, #4] + 80014e4: 69db ldr r3, [r3, #28] + 80014e6: 061b lsls r3, r3, #24 + 80014e8: 4991 ldr r1, [pc, #580] @ (8001730 ) + 80014ea: 4313 orrs r3, r2 + 80014ec: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80014ee: 687b ldr r3, [r7, #4] + 80014f0: 6a1b ldr r3, [r3, #32] + 80014f2: 4618 mov r0, r3 + 80014f4: f000 fbd4 bl 8001ca0 + 80014f8: 4603 mov r3, r0 + 80014fa: 2b00 cmp r3, #0 + 80014fc: d001 beq.n 8001502 + { + return HAL_ERROR; + 80014fe: 2301 movs r3, #1 + 8001500: e1d3 b.n 80018aa + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001502: 687b ldr r3, [r7, #4] + 8001504: 6a1b ldr r3, [r3, #32] + 8001506: 0b5b lsrs r3, r3, #13 + 8001508: 3301 adds r3, #1 + 800150a: f44f 4200 mov.w r2, #32768 @ 0x8000 + 800150e: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 8001512: 4a87 ldr r2, [pc, #540] @ (8001730 ) + 8001514: 6892 ldr r2, [r2, #8] + 8001516: 0912 lsrs r2, r2, #4 + 8001518: f002 020f and.w r2, r2, #15 + 800151c: 4985 ldr r1, [pc, #532] @ (8001734 ) + 800151e: 5c8a ldrb r2, [r1, r2] + 8001520: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001522: 4a85 ldr r2, [pc, #532] @ (8001738 ) + 8001524: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001526: 4b85 ldr r3, [pc, #532] @ (800173c ) + 8001528: 681b ldr r3, [r3, #0] + 800152a: 4618 mov r0, r3 + 800152c: f7ff fb68 bl 8000c00 + 8001530: 4603 mov r3, r0 + 8001532: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 8001534: 7bfb ldrb r3, [r7, #15] + 8001536: 2b00 cmp r3, #0 + 8001538: d045 beq.n 80015c6 + { + return status; + 800153a: 7bfb ldrb r3, [r7, #15] + 800153c: e1b5 b.n 80018aa + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 800153e: 687b ldr r3, [r7, #4] + 8001540: 699b ldr r3, [r3, #24] + 8001542: 2b00 cmp r3, #0 + 8001544: d029 beq.n 800159a + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 8001546: 4b7e ldr r3, [pc, #504] @ (8001740 ) + 8001548: 2201 movs r2, #1 + 800154a: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800154c: f7ff fba4 bl 8000c98 + 8001550: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001552: e008 b.n 8001566 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001554: f7ff fba0 bl 8000c98 + 8001558: 4602 mov r2, r0 + 800155a: 693b ldr r3, [r7, #16] + 800155c: 1ad3 subs r3, r2, r3 + 800155e: 2b02 cmp r3, #2 + 8001560: d901 bls.n 8001566 + { + return HAL_TIMEOUT; + 8001562: 2303 movs r3, #3 + 8001564: e1a1 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001566: 4b72 ldr r3, [pc, #456] @ (8001730 ) + 8001568: 681b ldr r3, [r3, #0] + 800156a: f403 7300 and.w r3, r3, #512 @ 0x200 + 800156e: 2b00 cmp r3, #0 + 8001570: d0f0 beq.n 8001554 + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001572: 4b6f ldr r3, [pc, #444] @ (8001730 ) + 8001574: 685b ldr r3, [r3, #4] + 8001576: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 800157a: 687b ldr r3, [r7, #4] + 800157c: 6a1b ldr r3, [r3, #32] + 800157e: 496c ldr r1, [pc, #432] @ (8001730 ) + 8001580: 4313 orrs r3, r2 + 8001582: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001584: 4b6a ldr r3, [pc, #424] @ (8001730 ) + 8001586: 685b ldr r3, [r3, #4] + 8001588: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 800158c: 687b ldr r3, [r7, #4] + 800158e: 69db ldr r3, [r3, #28] + 8001590: 061b lsls r3, r3, #24 + 8001592: 4967 ldr r1, [pc, #412] @ (8001730 ) + 8001594: 4313 orrs r3, r2 + 8001596: 604b str r3, [r1, #4] + 8001598: e015 b.n 80015c6 + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 800159a: 4b69 ldr r3, [pc, #420] @ (8001740 ) + 800159c: 2200 movs r2, #0 + 800159e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80015a0: f7ff fb7a bl 8000c98 + 80015a4: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80015a6: e008 b.n 80015ba + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80015a8: f7ff fb76 bl 8000c98 + 80015ac: 4602 mov r2, r0 + 80015ae: 693b ldr r3, [r7, #16] + 80015b0: 1ad3 subs r3, r2, r3 + 80015b2: 2b02 cmp r3, #2 + 80015b4: d901 bls.n 80015ba + { + return HAL_TIMEOUT; + 80015b6: 2303 movs r3, #3 + 80015b8: e177 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80015ba: 4b5d ldr r3, [pc, #372] @ (8001730 ) + 80015bc: 681b ldr r3, [r3, #0] + 80015be: f403 7300 and.w r3, r3, #512 @ 0x200 + 80015c2: 2b00 cmp r3, #0 + 80015c4: d1f0 bne.n 80015a8 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80015c6: 687b ldr r3, [r7, #4] + 80015c8: 681b ldr r3, [r3, #0] + 80015ca: f003 0308 and.w r3, r3, #8 + 80015ce: 2b00 cmp r3, #0 + 80015d0: d030 beq.n 8001634 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 80015d2: 687b ldr r3, [r7, #4] + 80015d4: 695b ldr r3, [r3, #20] + 80015d6: 2b00 cmp r3, #0 + 80015d8: d016 beq.n 8001608 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 80015da: 4b5a ldr r3, [pc, #360] @ (8001744 ) + 80015dc: 2201 movs r2, #1 + 80015de: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80015e0: f7ff fb5a bl 8000c98 + 80015e4: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 80015e6: e008 b.n 80015fa + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 80015e8: f7ff fb56 bl 8000c98 + 80015ec: 4602 mov r2, r0 + 80015ee: 693b ldr r3, [r7, #16] + 80015f0: 1ad3 subs r3, r2, r3 + 80015f2: 2b02 cmp r3, #2 + 80015f4: d901 bls.n 80015fa + { + return HAL_TIMEOUT; + 80015f6: 2303 movs r3, #3 + 80015f8: e157 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 80015fa: 4b4d ldr r3, [pc, #308] @ (8001730 ) + 80015fc: 6b5b ldr r3, [r3, #52] @ 0x34 + 80015fe: f003 0302 and.w r3, r3, #2 + 8001602: 2b00 cmp r3, #0 + 8001604: d0f0 beq.n 80015e8 + 8001606: e015 b.n 8001634 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001608: 4b4e ldr r3, [pc, #312] @ (8001744 ) + 800160a: 2200 movs r2, #0 + 800160c: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800160e: f7ff fb43 bl 8000c98 + 8001612: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001614: e008 b.n 8001628 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001616: f7ff fb3f bl 8000c98 + 800161a: 4602 mov r2, r0 + 800161c: 693b ldr r3, [r7, #16] + 800161e: 1ad3 subs r3, r2, r3 + 8001620: 2b02 cmp r3, #2 + 8001622: d901 bls.n 8001628 + { + return HAL_TIMEOUT; + 8001624: 2303 movs r3, #3 + 8001626: e140 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001628: 4b41 ldr r3, [pc, #260] @ (8001730 ) + 800162a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800162c: f003 0302 and.w r3, r3, #2 + 8001630: 2b00 cmp r3, #0 + 8001632: d1f0 bne.n 8001616 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8001634: 687b ldr r3, [r7, #4] + 8001636: 681b ldr r3, [r3, #0] + 8001638: f003 0304 and.w r3, r3, #4 + 800163c: 2b00 cmp r3, #0 + 800163e: f000 80b5 beq.w 80017ac + { + FlagStatus pwrclkchanged = RESET; + 8001642: 2300 movs r3, #0 + 8001644: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8001646: 4b3a ldr r3, [pc, #232] @ (8001730 ) + 8001648: 6a5b ldr r3, [r3, #36] @ 0x24 + 800164a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800164e: 2b00 cmp r3, #0 + 8001650: d10d bne.n 800166e + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001652: 4b37 ldr r3, [pc, #220] @ (8001730 ) + 8001654: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001656: 4a36 ldr r2, [pc, #216] @ (8001730 ) + 8001658: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800165c: 6253 str r3, [r2, #36] @ 0x24 + 800165e: 4b34 ldr r3, [pc, #208] @ (8001730 ) + 8001660: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001662: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001666: 60bb str r3, [r7, #8] + 8001668: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 800166a: 2301 movs r3, #1 + 800166c: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 800166e: 4b36 ldr r3, [pc, #216] @ (8001748 ) + 8001670: 681b ldr r3, [r3, #0] + 8001672: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001676: 2b00 cmp r3, #0 + 8001678: d118 bne.n 80016ac + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 800167a: 4b33 ldr r3, [pc, #204] @ (8001748 ) + 800167c: 681b ldr r3, [r3, #0] + 800167e: 4a32 ldr r2, [pc, #200] @ (8001748 ) + 8001680: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001684: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8001686: f7ff fb07 bl 8000c98 + 800168a: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 800168c: e008 b.n 80016a0 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 800168e: f7ff fb03 bl 8000c98 + 8001692: 4602 mov r2, r0 + 8001694: 693b ldr r3, [r7, #16] + 8001696: 1ad3 subs r3, r2, r3 + 8001698: 2b64 cmp r3, #100 @ 0x64 + 800169a: d901 bls.n 80016a0 + { + return HAL_TIMEOUT; + 800169c: 2303 movs r3, #3 + 800169e: e104 b.n 80018aa + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80016a0: 4b29 ldr r3, [pc, #164] @ (8001748 ) + 80016a2: 681b ldr r3, [r3, #0] + 80016a4: f403 7380 and.w r3, r3, #256 @ 0x100 + 80016a8: 2b00 cmp r3, #0 + 80016aa: d0f0 beq.n 800168e + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80016ac: 687b ldr r3, [r7, #4] + 80016ae: 689b ldr r3, [r3, #8] + 80016b0: 2b01 cmp r3, #1 + 80016b2: d106 bne.n 80016c2 + 80016b4: 4b1e ldr r3, [pc, #120] @ (8001730 ) + 80016b6: 6b5b ldr r3, [r3, #52] @ 0x34 + 80016b8: 4a1d ldr r2, [pc, #116] @ (8001730 ) + 80016ba: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80016be: 6353 str r3, [r2, #52] @ 0x34 + 80016c0: e02d b.n 800171e + 80016c2: 687b ldr r3, [r7, #4] + 80016c4: 689b ldr r3, [r3, #8] + 80016c6: 2b00 cmp r3, #0 + 80016c8: d10c bne.n 80016e4 + 80016ca: 4b19 ldr r3, [pc, #100] @ (8001730 ) + 80016cc: 6b5b ldr r3, [r3, #52] @ 0x34 + 80016ce: 4a18 ldr r2, [pc, #96] @ (8001730 ) + 80016d0: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80016d4: 6353 str r3, [r2, #52] @ 0x34 + 80016d6: 4b16 ldr r3, [pc, #88] @ (8001730 ) + 80016d8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80016da: 4a15 ldr r2, [pc, #84] @ (8001730 ) + 80016dc: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 80016e0: 6353 str r3, [r2, #52] @ 0x34 + 80016e2: e01c b.n 800171e + 80016e4: 687b ldr r3, [r7, #4] + 80016e6: 689b ldr r3, [r3, #8] + 80016e8: 2b05 cmp r3, #5 + 80016ea: d10c bne.n 8001706 + 80016ec: 4b10 ldr r3, [pc, #64] @ (8001730 ) + 80016ee: 6b5b ldr r3, [r3, #52] @ 0x34 + 80016f0: 4a0f ldr r2, [pc, #60] @ (8001730 ) + 80016f2: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 80016f6: 6353 str r3, [r2, #52] @ 0x34 + 80016f8: 4b0d ldr r3, [pc, #52] @ (8001730 ) + 80016fa: 6b5b ldr r3, [r3, #52] @ 0x34 + 80016fc: 4a0c ldr r2, [pc, #48] @ (8001730 ) + 80016fe: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001702: 6353 str r3, [r2, #52] @ 0x34 + 8001704: e00b b.n 800171e + 8001706: 4b0a ldr r3, [pc, #40] @ (8001730 ) + 8001708: 6b5b ldr r3, [r3, #52] @ 0x34 + 800170a: 4a09 ldr r2, [pc, #36] @ (8001730 ) + 800170c: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001710: 6353 str r3, [r2, #52] @ 0x34 + 8001712: 4b07 ldr r3, [pc, #28] @ (8001730 ) + 8001714: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001716: 4a06 ldr r2, [pc, #24] @ (8001730 ) + 8001718: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 800171c: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 800171e: 687b ldr r3, [r7, #4] + 8001720: 689b ldr r3, [r3, #8] + 8001722: 2b00 cmp r3, #0 + 8001724: d024 beq.n 8001770 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001726: f7ff fab7 bl 8000c98 + 800172a: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800172c: e019 b.n 8001762 + 800172e: bf00 nop + 8001730: 40023800 .word 0x40023800 + 8001734: 08002f78 .word 0x08002f78 + 8001738: 20000000 .word 0x20000000 + 800173c: 20000004 .word 0x20000004 + 8001740: 42470020 .word 0x42470020 + 8001744: 42470680 .word 0x42470680 + 8001748: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800174c: f7ff faa4 bl 8000c98 + 8001750: 4602 mov r2, r0 + 8001752: 693b ldr r3, [r7, #16] + 8001754: 1ad3 subs r3, r2, r3 + 8001756: f241 3288 movw r2, #5000 @ 0x1388 + 800175a: 4293 cmp r3, r2 + 800175c: d901 bls.n 8001762 + { + return HAL_TIMEOUT; + 800175e: 2303 movs r3, #3 + 8001760: e0a3 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001762: 4b54 ldr r3, [pc, #336] @ (80018b4 ) + 8001764: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001766: f403 7300 and.w r3, r3, #512 @ 0x200 + 800176a: 2b00 cmp r3, #0 + 800176c: d0ee beq.n 800174c + 800176e: e014 b.n 800179a + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001770: f7ff fa92 bl 8000c98 + 8001774: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8001776: e00a b.n 800178e + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001778: f7ff fa8e bl 8000c98 + 800177c: 4602 mov r2, r0 + 800177e: 693b ldr r3, [r7, #16] + 8001780: 1ad3 subs r3, r2, r3 + 8001782: f241 3288 movw r2, #5000 @ 0x1388 + 8001786: 4293 cmp r3, r2 + 8001788: d901 bls.n 800178e + { + return HAL_TIMEOUT; + 800178a: 2303 movs r3, #3 + 800178c: e08d b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 800178e: 4b49 ldr r3, [pc, #292] @ (80018b4 ) + 8001790: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001792: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001796: 2b00 cmp r3, #0 + 8001798: d1ee bne.n 8001778 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 800179a: 7ffb ldrb r3, [r7, #31] + 800179c: 2b01 cmp r3, #1 + 800179e: d105 bne.n 80017ac + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80017a0: 4b44 ldr r3, [pc, #272] @ (80018b4 ) + 80017a2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80017a4: 4a43 ldr r2, [pc, #268] @ (80018b4 ) + 80017a6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80017aa: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80017ac: 687b ldr r3, [r7, #4] + 80017ae: 6a5b ldr r3, [r3, #36] @ 0x24 + 80017b0: 2b00 cmp r3, #0 + 80017b2: d079 beq.n 80018a8 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80017b4: 69bb ldr r3, [r7, #24] + 80017b6: 2b0c cmp r3, #12 + 80017b8: d056 beq.n 8001868 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80017ba: 687b ldr r3, [r7, #4] + 80017bc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80017be: 2b02 cmp r3, #2 + 80017c0: d13b bne.n 800183a + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80017c2: 4b3d ldr r3, [pc, #244] @ (80018b8 ) + 80017c4: 2200 movs r2, #0 + 80017c6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80017c8: f7ff fa66 bl 8000c98 + 80017cc: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80017ce: e008 b.n 80017e2 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80017d0: f7ff fa62 bl 8000c98 + 80017d4: 4602 mov r2, r0 + 80017d6: 693b ldr r3, [r7, #16] + 80017d8: 1ad3 subs r3, r2, r3 + 80017da: 2b02 cmp r3, #2 + 80017dc: d901 bls.n 80017e2 + { + return HAL_TIMEOUT; + 80017de: 2303 movs r3, #3 + 80017e0: e063 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80017e2: 4b34 ldr r3, [pc, #208] @ (80018b4 ) + 80017e4: 681b ldr r3, [r3, #0] + 80017e6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80017ea: 2b00 cmp r3, #0 + 80017ec: d1f0 bne.n 80017d0 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 80017ee: 4b31 ldr r3, [pc, #196] @ (80018b4 ) + 80017f0: 689b ldr r3, [r3, #8] + 80017f2: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 80017f6: 687b ldr r3, [r7, #4] + 80017f8: 6a99 ldr r1, [r3, #40] @ 0x28 + 80017fa: 687b ldr r3, [r7, #4] + 80017fc: 6adb ldr r3, [r3, #44] @ 0x2c + 80017fe: 4319 orrs r1, r3 + 8001800: 687b ldr r3, [r7, #4] + 8001802: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001804: 430b orrs r3, r1 + 8001806: 492b ldr r1, [pc, #172] @ (80018b4 ) + 8001808: 4313 orrs r3, r2 + 800180a: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 800180c: 4b2a ldr r3, [pc, #168] @ (80018b8 ) + 800180e: 2201 movs r2, #1 + 8001810: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001812: f7ff fa41 bl 8000c98 + 8001816: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001818: e008 b.n 800182c + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800181a: f7ff fa3d bl 8000c98 + 800181e: 4602 mov r2, r0 + 8001820: 693b ldr r3, [r7, #16] + 8001822: 1ad3 subs r3, r2, r3 + 8001824: 2b02 cmp r3, #2 + 8001826: d901 bls.n 800182c + { + return HAL_TIMEOUT; + 8001828: 2303 movs r3, #3 + 800182a: e03e b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 800182c: 4b21 ldr r3, [pc, #132] @ (80018b4 ) + 800182e: 681b ldr r3, [r3, #0] + 8001830: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001834: 2b00 cmp r3, #0 + 8001836: d0f0 beq.n 800181a + 8001838: e036 b.n 80018a8 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 800183a: 4b1f ldr r3, [pc, #124] @ (80018b8 ) + 800183c: 2200 movs r2, #0 + 800183e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001840: f7ff fa2a bl 8000c98 + 8001844: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001846: e008 b.n 800185a + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001848: f7ff fa26 bl 8000c98 + 800184c: 4602 mov r2, r0 + 800184e: 693b ldr r3, [r7, #16] + 8001850: 1ad3 subs r3, r2, r3 + 8001852: 2b02 cmp r3, #2 + 8001854: d901 bls.n 800185a + { + return HAL_TIMEOUT; + 8001856: 2303 movs r3, #3 + 8001858: e027 b.n 80018aa + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800185a: 4b16 ldr r3, [pc, #88] @ (80018b4 ) + 800185c: 681b ldr r3, [r3, #0] + 800185e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001862: 2b00 cmp r3, #0 + 8001864: d1f0 bne.n 8001848 + 8001866: e01f b.n 80018a8 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8001868: 687b ldr r3, [r7, #4] + 800186a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800186c: 2b01 cmp r3, #1 + 800186e: d101 bne.n 8001874 + { + return HAL_ERROR; + 8001870: 2301 movs r3, #1 + 8001872: e01a b.n 80018aa + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8001874: 4b0f ldr r3, [pc, #60] @ (80018b4 ) + 8001876: 689b ldr r3, [r3, #8] + 8001878: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 800187a: 697b ldr r3, [r7, #20] + 800187c: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 8001880: 687b ldr r3, [r7, #4] + 8001882: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001884: 429a cmp r2, r3 + 8001886: d10d bne.n 80018a4 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8001888: 697b ldr r3, [r7, #20] + 800188a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 800188e: 687b ldr r3, [r7, #4] + 8001890: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8001892: 429a cmp r2, r3 + 8001894: d106 bne.n 80018a4 + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 8001896: 697b ldr r3, [r7, #20] + 8001898: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 800189c: 687b ldr r3, [r7, #4] + 800189e: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80018a0: 429a cmp r2, r3 + 80018a2: d001 beq.n 80018a8 + { + return HAL_ERROR; + 80018a4: 2301 movs r3, #1 + 80018a6: e000 b.n 80018aa + } + } + } + } + + return HAL_OK; + 80018a8: 2300 movs r3, #0 +} + 80018aa: 4618 mov r0, r3 + 80018ac: 3720 adds r7, #32 + 80018ae: 46bd mov sp, r7 + 80018b0: bd80 pop {r7, pc} + 80018b2: bf00 nop + 80018b4: 40023800 .word 0x40023800 + 80018b8: 42470060 .word 0x42470060 + +080018bc : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80018bc: b580 push {r7, lr} + 80018be: b084 sub sp, #16 + 80018c0: af00 add r7, sp, #0 + 80018c2: 6078 str r0, [r7, #4] + 80018c4: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 80018c6: 687b ldr r3, [r7, #4] + 80018c8: 2b00 cmp r3, #0 + 80018ca: d101 bne.n 80018d0 + { + return HAL_ERROR; + 80018cc: 2301 movs r3, #1 + 80018ce: e11a b.n 8001b06 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 80018d0: 4b8f ldr r3, [pc, #572] @ (8001b10 ) + 80018d2: 681b ldr r3, [r3, #0] + 80018d4: f003 0301 and.w r3, r3, #1 + 80018d8: 683a ldr r2, [r7, #0] + 80018da: 429a cmp r2, r3 + 80018dc: d919 bls.n 8001912 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80018de: 683b ldr r3, [r7, #0] + 80018e0: 2b01 cmp r3, #1 + 80018e2: d105 bne.n 80018f0 + 80018e4: 4b8a ldr r3, [pc, #552] @ (8001b10 ) + 80018e6: 681b ldr r3, [r3, #0] + 80018e8: 4a89 ldr r2, [pc, #548] @ (8001b10 ) + 80018ea: f043 0304 orr.w r3, r3, #4 + 80018ee: 6013 str r3, [r2, #0] + 80018f0: 4b87 ldr r3, [pc, #540] @ (8001b10 ) + 80018f2: 681b ldr r3, [r3, #0] + 80018f4: f023 0201 bic.w r2, r3, #1 + 80018f8: 4985 ldr r1, [pc, #532] @ (8001b10 ) + 80018fa: 683b ldr r3, [r7, #0] + 80018fc: 4313 orrs r3, r2 + 80018fe: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001900: 4b83 ldr r3, [pc, #524] @ (8001b10 ) + 8001902: 681b ldr r3, [r3, #0] + 8001904: f003 0301 and.w r3, r3, #1 + 8001908: 683a ldr r2, [r7, #0] + 800190a: 429a cmp r2, r3 + 800190c: d001 beq.n 8001912 + { + return HAL_ERROR; + 800190e: 2301 movs r3, #1 + 8001910: e0f9 b.n 8001b06 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8001912: 687b ldr r3, [r7, #4] + 8001914: 681b ldr r3, [r3, #0] + 8001916: f003 0302 and.w r3, r3, #2 + 800191a: 2b00 cmp r3, #0 + 800191c: d008 beq.n 8001930 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 800191e: 4b7d ldr r3, [pc, #500] @ (8001b14 ) + 8001920: 689b ldr r3, [r3, #8] + 8001922: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8001926: 687b ldr r3, [r7, #4] + 8001928: 689b ldr r3, [r3, #8] + 800192a: 497a ldr r1, [pc, #488] @ (8001b14 ) + 800192c: 4313 orrs r3, r2 + 800192e: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8001930: 687b ldr r3, [r7, #4] + 8001932: 681b ldr r3, [r3, #0] + 8001934: f003 0301 and.w r3, r3, #1 + 8001938: 2b00 cmp r3, #0 + 800193a: f000 808e beq.w 8001a5a + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800193e: 687b ldr r3, [r7, #4] + 8001940: 685b ldr r3, [r3, #4] + 8001942: 2b02 cmp r3, #2 + 8001944: d107 bne.n 8001956 + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001946: 4b73 ldr r3, [pc, #460] @ (8001b14 ) + 8001948: 681b ldr r3, [r3, #0] + 800194a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800194e: 2b00 cmp r3, #0 + 8001950: d121 bne.n 8001996 + { + return HAL_ERROR; + 8001952: 2301 movs r3, #1 + 8001954: e0d7 b.n 8001b06 + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001956: 687b ldr r3, [r7, #4] + 8001958: 685b ldr r3, [r3, #4] + 800195a: 2b03 cmp r3, #3 + 800195c: d107 bne.n 800196e + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 800195e: 4b6d ldr r3, [pc, #436] @ (8001b14 ) + 8001960: 681b ldr r3, [r3, #0] + 8001962: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001966: 2b00 cmp r3, #0 + 8001968: d115 bne.n 8001996 + { + return HAL_ERROR; + 800196a: 2301 movs r3, #1 + 800196c: e0cb b.n 8001b06 + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 800196e: 687b ldr r3, [r7, #4] + 8001970: 685b ldr r3, [r3, #4] + 8001972: 2b01 cmp r3, #1 + 8001974: d107 bne.n 8001986 + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001976: 4b67 ldr r3, [pc, #412] @ (8001b14 ) + 8001978: 681b ldr r3, [r3, #0] + 800197a: f003 0302 and.w r3, r3, #2 + 800197e: 2b00 cmp r3, #0 + 8001980: d109 bne.n 8001996 + { + return HAL_ERROR; + 8001982: 2301 movs r3, #1 + 8001984: e0bf b.n 8001b06 + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001986: 4b63 ldr r3, [pc, #396] @ (8001b14 ) + 8001988: 681b ldr r3, [r3, #0] + 800198a: f403 7300 and.w r3, r3, #512 @ 0x200 + 800198e: 2b00 cmp r3, #0 + 8001990: d101 bne.n 8001996 + { + return HAL_ERROR; + 8001992: 2301 movs r3, #1 + 8001994: e0b7 b.n 8001b06 + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8001996: 4b5f ldr r3, [pc, #380] @ (8001b14 ) + 8001998: 689b ldr r3, [r3, #8] + 800199a: f023 0203 bic.w r2, r3, #3 + 800199e: 687b ldr r3, [r7, #4] + 80019a0: 685b ldr r3, [r3, #4] + 80019a2: 495c ldr r1, [pc, #368] @ (8001b14 ) + 80019a4: 4313 orrs r3, r2 + 80019a6: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80019a8: f7ff f976 bl 8000c98 + 80019ac: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80019ae: 687b ldr r3, [r7, #4] + 80019b0: 685b ldr r3, [r3, #4] + 80019b2: 2b02 cmp r3, #2 + 80019b4: d112 bne.n 80019dc + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 80019b6: e00a b.n 80019ce + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80019b8: f7ff f96e bl 8000c98 + 80019bc: 4602 mov r2, r0 + 80019be: 68fb ldr r3, [r7, #12] + 80019c0: 1ad3 subs r3, r2, r3 + 80019c2: f241 3288 movw r2, #5000 @ 0x1388 + 80019c6: 4293 cmp r3, r2 + 80019c8: d901 bls.n 80019ce + { + return HAL_TIMEOUT; + 80019ca: 2303 movs r3, #3 + 80019cc: e09b b.n 8001b06 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 80019ce: 4b51 ldr r3, [pc, #324] @ (8001b14 ) + 80019d0: 689b ldr r3, [r3, #8] + 80019d2: f003 030c and.w r3, r3, #12 + 80019d6: 2b08 cmp r3, #8 + 80019d8: d1ee bne.n 80019b8 + 80019da: e03e b.n 8001a5a + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80019dc: 687b ldr r3, [r7, #4] + 80019de: 685b ldr r3, [r3, #4] + 80019e0: 2b03 cmp r3, #3 + 80019e2: d112 bne.n 8001a0a + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80019e4: e00a b.n 80019fc + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80019e6: f7ff f957 bl 8000c98 + 80019ea: 4602 mov r2, r0 + 80019ec: 68fb ldr r3, [r7, #12] + 80019ee: 1ad3 subs r3, r2, r3 + 80019f0: f241 3288 movw r2, #5000 @ 0x1388 + 80019f4: 4293 cmp r3, r2 + 80019f6: d901 bls.n 80019fc + { + return HAL_TIMEOUT; + 80019f8: 2303 movs r3, #3 + 80019fa: e084 b.n 8001b06 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80019fc: 4b45 ldr r3, [pc, #276] @ (8001b14 ) + 80019fe: 689b ldr r3, [r3, #8] + 8001a00: f003 030c and.w r3, r3, #12 + 8001a04: 2b0c cmp r3, #12 + 8001a06: d1ee bne.n 80019e6 + 8001a08: e027 b.n 8001a5a + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001a0a: 687b ldr r3, [r7, #4] + 8001a0c: 685b ldr r3, [r3, #4] + 8001a0e: 2b01 cmp r3, #1 + 8001a10: d11d bne.n 8001a4e + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001a12: e00a b.n 8001a2a + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001a14: f7ff f940 bl 8000c98 + 8001a18: 4602 mov r2, r0 + 8001a1a: 68fb ldr r3, [r7, #12] + 8001a1c: 1ad3 subs r3, r2, r3 + 8001a1e: f241 3288 movw r2, #5000 @ 0x1388 + 8001a22: 4293 cmp r3, r2 + 8001a24: d901 bls.n 8001a2a + { + return HAL_TIMEOUT; + 8001a26: 2303 movs r3, #3 + 8001a28: e06d b.n 8001b06 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001a2a: 4b3a ldr r3, [pc, #232] @ (8001b14 ) + 8001a2c: 689b ldr r3, [r3, #8] + 8001a2e: f003 030c and.w r3, r3, #12 + 8001a32: 2b04 cmp r3, #4 + 8001a34: d1ee bne.n 8001a14 + 8001a36: e010 b.n 8001a5a + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001a38: f7ff f92e bl 8000c98 + 8001a3c: 4602 mov r2, r0 + 8001a3e: 68fb ldr r3, [r7, #12] + 8001a40: 1ad3 subs r3, r2, r3 + 8001a42: f241 3288 movw r2, #5000 @ 0x1388 + 8001a46: 4293 cmp r3, r2 + 8001a48: d901 bls.n 8001a4e + { + return HAL_TIMEOUT; + 8001a4a: 2303 movs r3, #3 + 8001a4c: e05b b.n 8001b06 + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 8001a4e: 4b31 ldr r3, [pc, #196] @ (8001b14 ) + 8001a50: 689b ldr r3, [r3, #8] + 8001a52: f003 030c and.w r3, r3, #12 + 8001a56: 2b00 cmp r3, #0 + 8001a58: d1ee bne.n 8001a38 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8001a5a: 4b2d ldr r3, [pc, #180] @ (8001b10 ) + 8001a5c: 681b ldr r3, [r3, #0] + 8001a5e: f003 0301 and.w r3, r3, #1 + 8001a62: 683a ldr r2, [r7, #0] + 8001a64: 429a cmp r2, r3 + 8001a66: d219 bcs.n 8001a9c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001a68: 683b ldr r3, [r7, #0] + 8001a6a: 2b01 cmp r3, #1 + 8001a6c: d105 bne.n 8001a7a + 8001a6e: 4b28 ldr r3, [pc, #160] @ (8001b10 ) + 8001a70: 681b ldr r3, [r3, #0] + 8001a72: 4a27 ldr r2, [pc, #156] @ (8001b10 ) + 8001a74: f043 0304 orr.w r3, r3, #4 + 8001a78: 6013 str r3, [r2, #0] + 8001a7a: 4b25 ldr r3, [pc, #148] @ (8001b10 ) + 8001a7c: 681b ldr r3, [r3, #0] + 8001a7e: f023 0201 bic.w r2, r3, #1 + 8001a82: 4923 ldr r1, [pc, #140] @ (8001b10 ) + 8001a84: 683b ldr r3, [r7, #0] + 8001a86: 4313 orrs r3, r2 + 8001a88: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001a8a: 4b21 ldr r3, [pc, #132] @ (8001b10 ) + 8001a8c: 681b ldr r3, [r3, #0] + 8001a8e: f003 0301 and.w r3, r3, #1 + 8001a92: 683a ldr r2, [r7, #0] + 8001a94: 429a cmp r2, r3 + 8001a96: d001 beq.n 8001a9c + { + return HAL_ERROR; + 8001a98: 2301 movs r3, #1 + 8001a9a: e034 b.n 8001b06 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001a9c: 687b ldr r3, [r7, #4] + 8001a9e: 681b ldr r3, [r3, #0] + 8001aa0: f003 0304 and.w r3, r3, #4 + 8001aa4: 2b00 cmp r3, #0 + 8001aa6: d008 beq.n 8001aba + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8001aa8: 4b1a ldr r3, [pc, #104] @ (8001b14 ) + 8001aaa: 689b ldr r3, [r3, #8] + 8001aac: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001ab0: 687b ldr r3, [r7, #4] + 8001ab2: 68db ldr r3, [r3, #12] + 8001ab4: 4917 ldr r1, [pc, #92] @ (8001b14 ) + 8001ab6: 4313 orrs r3, r2 + 8001ab8: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001aba: 687b ldr r3, [r7, #4] + 8001abc: 681b ldr r3, [r3, #0] + 8001abe: f003 0308 and.w r3, r3, #8 + 8001ac2: 2b00 cmp r3, #0 + 8001ac4: d009 beq.n 8001ada + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8001ac6: 4b13 ldr r3, [pc, #76] @ (8001b14 ) + 8001ac8: 689b ldr r3, [r3, #8] + 8001aca: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001ace: 687b ldr r3, [r7, #4] + 8001ad0: 691b ldr r3, [r3, #16] + 8001ad2: 00db lsls r3, r3, #3 + 8001ad4: 490f ldr r1, [pc, #60] @ (8001b14 ) + 8001ad6: 4313 orrs r3, r2 + 8001ad8: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8001ada: f000 f823 bl 8001b24 + 8001ade: 4602 mov r2, r0 + 8001ae0: 4b0c ldr r3, [pc, #48] @ (8001b14 ) + 8001ae2: 689b ldr r3, [r3, #8] + 8001ae4: 091b lsrs r3, r3, #4 + 8001ae6: f003 030f and.w r3, r3, #15 + 8001aea: 490b ldr r1, [pc, #44] @ (8001b18 ) + 8001aec: 5ccb ldrb r3, [r1, r3] + 8001aee: fa22 f303 lsr.w r3, r2, r3 + 8001af2: 4a0a ldr r2, [pc, #40] @ (8001b1c ) + 8001af4: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001af6: 4b0a ldr r3, [pc, #40] @ (8001b20 ) + 8001af8: 681b ldr r3, [r3, #0] + 8001afa: 4618 mov r0, r3 + 8001afc: f7ff f880 bl 8000c00 + 8001b00: 4603 mov r3, r0 + 8001b02: 72fb strb r3, [r7, #11] + + return status; + 8001b04: 7afb ldrb r3, [r7, #11] +} + 8001b06: 4618 mov r0, r3 + 8001b08: 3710 adds r7, #16 + 8001b0a: 46bd mov sp, r7 + 8001b0c: bd80 pop {r7, pc} + 8001b0e: bf00 nop + 8001b10: 40023c00 .word 0x40023c00 + 8001b14: 40023800 .word 0x40023800 + 8001b18: 08002f78 .word 0x08002f78 + 8001b1c: 20000000 .word 0x20000000 + 8001b20: 20000004 .word 0x20000004 + +08001b24 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8001b24: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001b28: b08e sub sp, #56 @ 0x38 + 8001b2a: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 8001b2c: 4b58 ldr r3, [pc, #352] @ (8001c90 ) + 8001b2e: 689b ldr r3, [r3, #8] + 8001b30: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8001b32: 6afb ldr r3, [r7, #44] @ 0x2c + 8001b34: f003 030c and.w r3, r3, #12 + 8001b38: 2b0c cmp r3, #12 + 8001b3a: d00d beq.n 8001b58 + 8001b3c: 2b0c cmp r3, #12 + 8001b3e: f200 8092 bhi.w 8001c66 + 8001b42: 2b04 cmp r3, #4 + 8001b44: d002 beq.n 8001b4c + 8001b46: 2b08 cmp r3, #8 + 8001b48: d003 beq.n 8001b52 + 8001b4a: e08c b.n 8001c66 + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8001b4c: 4b51 ldr r3, [pc, #324] @ (8001c94 ) + 8001b4e: 633b str r3, [r7, #48] @ 0x30 + break; + 8001b50: e097 b.n 8001c82 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001b52: 4b51 ldr r3, [pc, #324] @ (8001c98 ) + 8001b54: 633b str r3, [r7, #48] @ 0x30 + break; + 8001b56: e094 b.n 8001c82 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8001b58: 6afb ldr r3, [r7, #44] @ 0x2c + 8001b5a: 0c9b lsrs r3, r3, #18 + 8001b5c: f003 020f and.w r2, r3, #15 + 8001b60: 4b4e ldr r3, [pc, #312] @ (8001c9c ) + 8001b62: 5c9b ldrb r3, [r3, r2] + 8001b64: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8001b66: 6afb ldr r3, [r7, #44] @ 0x2c + 8001b68: 0d9b lsrs r3, r3, #22 + 8001b6a: f003 0303 and.w r3, r3, #3 + 8001b6e: 3301 adds r3, #1 + 8001b70: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8001b72: 4b47 ldr r3, [pc, #284] @ (8001c90 ) + 8001b74: 689b ldr r3, [r3, #8] + 8001b76: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001b7a: 2b00 cmp r3, #0 + 8001b7c: d021 beq.n 8001bc2 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001b7e: 6abb ldr r3, [r7, #40] @ 0x28 + 8001b80: 2200 movs r2, #0 + 8001b82: 61bb str r3, [r7, #24] + 8001b84: 61fa str r2, [r7, #28] + 8001b86: 4b44 ldr r3, [pc, #272] @ (8001c98 ) + 8001b88: e9d7 8906 ldrd r8, r9, [r7, #24] + 8001b8c: 464a mov r2, r9 + 8001b8e: fb03 f202 mul.w r2, r3, r2 + 8001b92: 2300 movs r3, #0 + 8001b94: 4644 mov r4, r8 + 8001b96: fb04 f303 mul.w r3, r4, r3 + 8001b9a: 4413 add r3, r2 + 8001b9c: 4a3e ldr r2, [pc, #248] @ (8001c98 ) + 8001b9e: 4644 mov r4, r8 + 8001ba0: fba4 0102 umull r0, r1, r4, r2 + 8001ba4: 440b add r3, r1 + 8001ba6: 4619 mov r1, r3 + 8001ba8: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001baa: 2200 movs r2, #0 + 8001bac: 613b str r3, [r7, #16] + 8001bae: 617a str r2, [r7, #20] + 8001bb0: e9d7 2304 ldrd r2, r3, [r7, #16] + 8001bb4: f7fe fae2 bl 800017c <__aeabi_uldivmod> + 8001bb8: 4602 mov r2, r0 + 8001bba: 460b mov r3, r1 + 8001bbc: 4613 mov r3, r2 + 8001bbe: 637b str r3, [r7, #52] @ 0x34 + 8001bc0: e04e b.n 8001c60 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001bc2: 6abb ldr r3, [r7, #40] @ 0x28 + 8001bc4: 2200 movs r2, #0 + 8001bc6: 469a mov sl, r3 + 8001bc8: 4693 mov fp, r2 + 8001bca: 4652 mov r2, sl + 8001bcc: 465b mov r3, fp + 8001bce: f04f 0000 mov.w r0, #0 + 8001bd2: f04f 0100 mov.w r1, #0 + 8001bd6: 0159 lsls r1, r3, #5 + 8001bd8: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001bdc: 0150 lsls r0, r2, #5 + 8001bde: 4602 mov r2, r0 + 8001be0: 460b mov r3, r1 + 8001be2: ebb2 080a subs.w r8, r2, sl + 8001be6: eb63 090b sbc.w r9, r3, fp + 8001bea: f04f 0200 mov.w r2, #0 + 8001bee: f04f 0300 mov.w r3, #0 + 8001bf2: ea4f 1389 mov.w r3, r9, lsl #6 + 8001bf6: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001bfa: ea4f 1288 mov.w r2, r8, lsl #6 + 8001bfe: ebb2 0408 subs.w r4, r2, r8 + 8001c02: eb63 0509 sbc.w r5, r3, r9 + 8001c06: f04f 0200 mov.w r2, #0 + 8001c0a: f04f 0300 mov.w r3, #0 + 8001c0e: 00eb lsls r3, r5, #3 + 8001c10: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8001c14: 00e2 lsls r2, r4, #3 + 8001c16: 4614 mov r4, r2 + 8001c18: 461d mov r5, r3 + 8001c1a: eb14 030a adds.w r3, r4, sl + 8001c1e: 603b str r3, [r7, #0] + 8001c20: eb45 030b adc.w r3, r5, fp + 8001c24: 607b str r3, [r7, #4] + 8001c26: f04f 0200 mov.w r2, #0 + 8001c2a: f04f 0300 mov.w r3, #0 + 8001c2e: e9d7 4500 ldrd r4, r5, [r7] + 8001c32: 4629 mov r1, r5 + 8001c34: 028b lsls r3, r1, #10 + 8001c36: 4620 mov r0, r4 + 8001c38: 4629 mov r1, r5 + 8001c3a: 4604 mov r4, r0 + 8001c3c: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8001c40: 4601 mov r1, r0 + 8001c42: 028a lsls r2, r1, #10 + 8001c44: 4610 mov r0, r2 + 8001c46: 4619 mov r1, r3 + 8001c48: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001c4a: 2200 movs r2, #0 + 8001c4c: 60bb str r3, [r7, #8] + 8001c4e: 60fa str r2, [r7, #12] + 8001c50: e9d7 2302 ldrd r2, r3, [r7, #8] + 8001c54: f7fe fa92 bl 800017c <__aeabi_uldivmod> + 8001c58: 4602 mov r2, r0 + 8001c5a: 460b mov r3, r1 + 8001c5c: 4613 mov r3, r2 + 8001c5e: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 8001c60: 6b7b ldr r3, [r7, #52] @ 0x34 + 8001c62: 633b str r3, [r7, #48] @ 0x30 + break; + 8001c64: e00d b.n 8001c82 + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8001c66: 4b0a ldr r3, [pc, #40] @ (8001c90 ) + 8001c68: 685b ldr r3, [r3, #4] + 8001c6a: 0b5b lsrs r3, r3, #13 + 8001c6c: f003 0307 and.w r3, r3, #7 + 8001c70: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8001c72: 6a3b ldr r3, [r7, #32] + 8001c74: 3301 adds r3, #1 + 8001c76: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001c7a: fa02 f303 lsl.w r3, r2, r3 + 8001c7e: 633b str r3, [r7, #48] @ 0x30 + break; + 8001c80: bf00 nop + } + } + return sysclockfreq; + 8001c82: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 8001c84: 4618 mov r0, r3 + 8001c86: 3738 adds r7, #56 @ 0x38 + 8001c88: 46bd mov sp, r7 + 8001c8a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8001c8e: bf00 nop + 8001c90: 40023800 .word 0x40023800 + 8001c94: 00f42400 .word 0x00f42400 + 8001c98: 016e3600 .word 0x016e3600 + 8001c9c: 08002f6c .word 0x08002f6c + +08001ca0 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 8001ca0: b480 push {r7} + 8001ca2: b087 sub sp, #28 + 8001ca4: af00 add r7, sp, #0 + 8001ca6: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8001ca8: 2300 movs r3, #0 + 8001caa: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 8001cac: 4b29 ldr r3, [pc, #164] @ (8001d54 ) + 8001cae: 689b ldr r3, [r3, #8] + 8001cb0: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001cb4: 2b00 cmp r3, #0 + 8001cb6: d12c bne.n 8001d12 + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 8001cb8: 4b26 ldr r3, [pc, #152] @ (8001d54 ) + 8001cba: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001cbc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001cc0: 2b00 cmp r3, #0 + 8001cc2: d005 beq.n 8001cd0 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001cc4: 4b24 ldr r3, [pc, #144] @ (8001d58 ) + 8001cc6: 681b ldr r3, [r3, #0] + 8001cc8: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001ccc: 617b str r3, [r7, #20] + 8001cce: e016 b.n 8001cfe + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001cd0: 4b20 ldr r3, [pc, #128] @ (8001d54 ) + 8001cd2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001cd4: 4a1f ldr r2, [pc, #124] @ (8001d54 ) + 8001cd6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001cda: 6253 str r3, [r2, #36] @ 0x24 + 8001cdc: 4b1d ldr r3, [pc, #116] @ (8001d54 ) + 8001cde: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ce0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001ce4: 60fb str r3, [r7, #12] + 8001ce6: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001ce8: 4b1b ldr r3, [pc, #108] @ (8001d58 ) + 8001cea: 681b ldr r3, [r3, #0] + 8001cec: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001cf0: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001cf2: 4b18 ldr r3, [pc, #96] @ (8001d54 ) + 8001cf4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001cf6: 4a17 ldr r2, [pc, #92] @ (8001d54 ) + 8001cf8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001cfc: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001cfe: 697b ldr r3, [r7, #20] + 8001d00: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001d04: d105 bne.n 8001d12 + 8001d06: 687b ldr r3, [r7, #4] + 8001d08: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001d0c: d101 bne.n 8001d12 + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001d0e: 2301 movs r3, #1 + 8001d10: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001d12: 693b ldr r3, [r7, #16] + 8001d14: 2b01 cmp r3, #1 + 8001d16: d105 bne.n 8001d24 + 8001d18: 4b10 ldr r3, [pc, #64] @ (8001d5c ) + 8001d1a: 681b ldr r3, [r3, #0] + 8001d1c: 4a0f ldr r2, [pc, #60] @ (8001d5c ) + 8001d1e: f043 0304 orr.w r3, r3, #4 + 8001d22: 6013 str r3, [r2, #0] + 8001d24: 4b0d ldr r3, [pc, #52] @ (8001d5c ) + 8001d26: 681b ldr r3, [r3, #0] + 8001d28: f023 0201 bic.w r2, r3, #1 + 8001d2c: 490b ldr r1, [pc, #44] @ (8001d5c ) + 8001d2e: 693b ldr r3, [r7, #16] + 8001d30: 4313 orrs r3, r2 + 8001d32: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001d34: 4b09 ldr r3, [pc, #36] @ (8001d5c ) + 8001d36: 681b ldr r3, [r3, #0] + 8001d38: f003 0301 and.w r3, r3, #1 + 8001d3c: 693a ldr r2, [r7, #16] + 8001d3e: 429a cmp r2, r3 + 8001d40: d001 beq.n 8001d46 + { + return HAL_ERROR; + 8001d42: 2301 movs r3, #1 + 8001d44: e000 b.n 8001d48 + } + + return HAL_OK; + 8001d46: 2300 movs r3, #0 +} + 8001d48: 4618 mov r0, r3 + 8001d4a: 371c adds r7, #28 + 8001d4c: 46bd mov sp, r7 + 8001d4e: bc80 pop {r7} + 8001d50: 4770 bx lr + 8001d52: bf00 nop + 8001d54: 40023800 .word 0x40023800 + 8001d58: 40007000 .word 0x40007000 + 8001d5c: 40023c00 .word 0x40023c00 + +08001d60 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001d60: b580 push {r7, lr} + 8001d62: b082 sub sp, #8 + 8001d64: af00 add r7, sp, #0 + 8001d66: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001d68: 687b ldr r3, [r7, #4] + 8001d6a: 2b00 cmp r3, #0 + 8001d6c: d101 bne.n 8001d72 + { + return HAL_ERROR; + 8001d6e: 2301 movs r3, #1 + 8001d70: e07b b.n 8001e6a + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001d72: 687b ldr r3, [r7, #4] + 8001d74: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001d76: 2b00 cmp r3, #0 + 8001d78: d108 bne.n 8001d8c + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001d7a: 687b ldr r3, [r7, #4] + 8001d7c: 685b ldr r3, [r3, #4] + 8001d7e: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001d82: d009 beq.n 8001d98 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001d84: 687b ldr r3, [r7, #4] + 8001d86: 2200 movs r2, #0 + 8001d88: 61da str r2, [r3, #28] + 8001d8a: e005 b.n 8001d98 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001d8c: 687b ldr r3, [r7, #4] + 8001d8e: 2200 movs r2, #0 + 8001d90: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001d92: 687b ldr r3, [r7, #4] + 8001d94: 2200 movs r2, #0 + 8001d96: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001d98: 687b ldr r3, [r7, #4] + 8001d9a: 2200 movs r2, #0 + 8001d9c: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001d9e: 687b ldr r3, [r7, #4] + 8001da0: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001da4: b2db uxtb r3, r3 + 8001da6: 2b00 cmp r3, #0 + 8001da8: d106 bne.n 8001db8 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001daa: 687b ldr r3, [r7, #4] + 8001dac: 2200 movs r2, #0 + 8001dae: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001db2: 6878 ldr r0, [r7, #4] + 8001db4: f7fe fd5c bl 8000870 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001db8: 687b ldr r3, [r7, #4] + 8001dba: 2202 movs r2, #2 + 8001dbc: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001dc0: 687b ldr r3, [r7, #4] + 8001dc2: 681b ldr r3, [r3, #0] + 8001dc4: 681a ldr r2, [r3, #0] + 8001dc6: 687b ldr r3, [r7, #4] + 8001dc8: 681b ldr r3, [r3, #0] + 8001dca: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001dce: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001dd0: 687b ldr r3, [r7, #4] + 8001dd2: 685b ldr r3, [r3, #4] + 8001dd4: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001dd8: 687b ldr r3, [r7, #4] + 8001dda: 689b ldr r3, [r3, #8] + 8001ddc: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001de0: 431a orrs r2, r3 + 8001de2: 687b ldr r3, [r7, #4] + 8001de4: 68db ldr r3, [r3, #12] + 8001de6: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001dea: 431a orrs r2, r3 + 8001dec: 687b ldr r3, [r7, #4] + 8001dee: 691b ldr r3, [r3, #16] + 8001df0: f003 0302 and.w r3, r3, #2 + 8001df4: 431a orrs r2, r3 + 8001df6: 687b ldr r3, [r7, #4] + 8001df8: 695b ldr r3, [r3, #20] + 8001dfa: f003 0301 and.w r3, r3, #1 + 8001dfe: 431a orrs r2, r3 + 8001e00: 687b ldr r3, [r7, #4] + 8001e02: 699b ldr r3, [r3, #24] + 8001e04: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001e08: 431a orrs r2, r3 + 8001e0a: 687b ldr r3, [r7, #4] + 8001e0c: 69db ldr r3, [r3, #28] + 8001e0e: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001e12: 431a orrs r2, r3 + 8001e14: 687b ldr r3, [r7, #4] + 8001e16: 6a1b ldr r3, [r3, #32] + 8001e18: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001e1c: ea42 0103 orr.w r1, r2, r3 + 8001e20: 687b ldr r3, [r7, #4] + 8001e22: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001e24: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001e28: 687b ldr r3, [r7, #4] + 8001e2a: 681b ldr r3, [r3, #0] + 8001e2c: 430a orrs r2, r1 + 8001e2e: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8001e30: 687b ldr r3, [r7, #4] + 8001e32: 699b ldr r3, [r3, #24] + 8001e34: 0c1b lsrs r3, r3, #16 + 8001e36: f003 0104 and.w r1, r3, #4 + 8001e3a: 687b ldr r3, [r7, #4] + 8001e3c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e3e: f003 0210 and.w r2, r3, #16 + 8001e42: 687b ldr r3, [r7, #4] + 8001e44: 681b ldr r3, [r3, #0] + 8001e46: 430a orrs r2, r1 + 8001e48: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8001e4a: 687b ldr r3, [r7, #4] + 8001e4c: 681b ldr r3, [r3, #0] + 8001e4e: 69da ldr r2, [r3, #28] + 8001e50: 687b ldr r3, [r7, #4] + 8001e52: 681b ldr r3, [r3, #0] + 8001e54: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001e58: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001e5a: 687b ldr r3, [r7, #4] + 8001e5c: 2200 movs r2, #0 + 8001e5e: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8001e60: 687b ldr r3, [r7, #4] + 8001e62: 2201 movs r2, #1 + 8001e64: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8001e68: 2300 movs r3, #0 +} + 8001e6a: 4618 mov r0, r3 + 8001e6c: 3708 adds r7, #8 + 8001e6e: 46bd mov sp, r7 + 8001e70: bd80 pop {r7, pc} + +08001e72 : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8001e72: b580 push {r7, lr} + 8001e74: b088 sub sp, #32 + 8001e76: af00 add r7, sp, #0 + 8001e78: 60f8 str r0, [r7, #12] + 8001e7a: 60b9 str r1, [r7, #8] + 8001e7c: 603b str r3, [r7, #0] + 8001e7e: 4613 mov r3, r2 + 8001e80: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001e82: f7fe ff09 bl 8000c98 + 8001e86: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8001e88: 88fb ldrh r3, [r7, #6] + 8001e8a: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8001e8c: 68fb ldr r3, [r7, #12] + 8001e8e: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001e92: b2db uxtb r3, r3 + 8001e94: 2b01 cmp r3, #1 + 8001e96: d001 beq.n 8001e9c + { + return HAL_BUSY; + 8001e98: 2302 movs r3, #2 + 8001e9a: e12a b.n 80020f2 + } + + if ((pData == NULL) || (Size == 0U)) + 8001e9c: 68bb ldr r3, [r7, #8] + 8001e9e: 2b00 cmp r3, #0 + 8001ea0: d002 beq.n 8001ea8 + 8001ea2: 88fb ldrh r3, [r7, #6] + 8001ea4: 2b00 cmp r3, #0 + 8001ea6: d101 bne.n 8001eac + { + return HAL_ERROR; + 8001ea8: 2301 movs r3, #1 + 8001eaa: e122 b.n 80020f2 + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 8001eac: 68fb ldr r3, [r7, #12] + 8001eae: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001eb2: 2b01 cmp r3, #1 + 8001eb4: d101 bne.n 8001eba + 8001eb6: 2302 movs r3, #2 + 8001eb8: e11b b.n 80020f2 + 8001eba: 68fb ldr r3, [r7, #12] + 8001ebc: 2201 movs r2, #1 + 8001ebe: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8001ec2: 68fb ldr r3, [r7, #12] + 8001ec4: 2203 movs r2, #3 + 8001ec6: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001eca: 68fb ldr r3, [r7, #12] + 8001ecc: 2200 movs r2, #0 + 8001ece: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8001ed0: 68fb ldr r3, [r7, #12] + 8001ed2: 68ba ldr r2, [r7, #8] + 8001ed4: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 8001ed6: 68fb ldr r3, [r7, #12] + 8001ed8: 88fa ldrh r2, [r7, #6] + 8001eda: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8001edc: 68fb ldr r3, [r7, #12] + 8001ede: 88fa ldrh r2, [r7, #6] + 8001ee0: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8001ee2: 68fb ldr r3, [r7, #12] + 8001ee4: 2200 movs r2, #0 + 8001ee6: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 8001ee8: 68fb ldr r3, [r7, #12] + 8001eea: 2200 movs r2, #0 + 8001eec: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8001eee: 68fb ldr r3, [r7, #12] + 8001ef0: 2200 movs r2, #0 + 8001ef2: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 8001ef4: 68fb ldr r3, [r7, #12] + 8001ef6: 2200 movs r2, #0 + 8001ef8: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8001efa: 68fb ldr r3, [r7, #12] + 8001efc: 2200 movs r2, #0 + 8001efe: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8001f00: 68fb ldr r3, [r7, #12] + 8001f02: 689b ldr r3, [r3, #8] + 8001f04: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001f08: d10f bne.n 8001f2a + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8001f0a: 68fb ldr r3, [r7, #12] + 8001f0c: 681b ldr r3, [r3, #0] + 8001f0e: 681a ldr r2, [r3, #0] + 8001f10: 68fb ldr r3, [r7, #12] + 8001f12: 681b ldr r3, [r3, #0] + 8001f14: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001f18: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8001f1a: 68fb ldr r3, [r7, #12] + 8001f1c: 681b ldr r3, [r3, #0] + 8001f1e: 681a ldr r2, [r3, #0] + 8001f20: 68fb ldr r3, [r7, #12] + 8001f22: 681b ldr r3, [r3, #0] + 8001f24: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8001f28: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8001f2a: 68fb ldr r3, [r7, #12] + 8001f2c: 681b ldr r3, [r3, #0] + 8001f2e: 681b ldr r3, [r3, #0] + 8001f30: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001f34: 2b40 cmp r3, #64 @ 0x40 + 8001f36: d007 beq.n 8001f48 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8001f38: 68fb ldr r3, [r7, #12] + 8001f3a: 681b ldr r3, [r3, #0] + 8001f3c: 681a ldr r2, [r3, #0] + 8001f3e: 68fb ldr r3, [r7, #12] + 8001f40: 681b ldr r3, [r3, #0] + 8001f42: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8001f46: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8001f48: 68fb ldr r3, [r7, #12] + 8001f4a: 68db ldr r3, [r3, #12] + 8001f4c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8001f50: d152 bne.n 8001ff8 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001f52: 68fb ldr r3, [r7, #12] + 8001f54: 685b ldr r3, [r3, #4] + 8001f56: 2b00 cmp r3, #0 + 8001f58: d002 beq.n 8001f60 + 8001f5a: 8b7b ldrh r3, [r7, #26] + 8001f5c: 2b01 cmp r3, #1 + 8001f5e: d145 bne.n 8001fec + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001f60: 68fb ldr r3, [r7, #12] + 8001f62: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001f64: 881a ldrh r2, [r3, #0] + 8001f66: 68fb ldr r3, [r7, #12] + 8001f68: 681b ldr r3, [r3, #0] + 8001f6a: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001f6c: 68fb ldr r3, [r7, #12] + 8001f6e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001f70: 1c9a adds r2, r3, #2 + 8001f72: 68fb ldr r3, [r7, #12] + 8001f74: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001f76: 68fb ldr r3, [r7, #12] + 8001f78: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001f7a: b29b uxth r3, r3 + 8001f7c: 3b01 subs r3, #1 + 8001f7e: b29a uxth r2, r3 + 8001f80: 68fb ldr r3, [r7, #12] + 8001f82: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 8001f84: e032 b.n 8001fec + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001f86: 68fb ldr r3, [r7, #12] + 8001f88: 681b ldr r3, [r3, #0] + 8001f8a: 689b ldr r3, [r3, #8] + 8001f8c: f003 0302 and.w r3, r3, #2 + 8001f90: 2b02 cmp r3, #2 + 8001f92: d112 bne.n 8001fba + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001f94: 68fb ldr r3, [r7, #12] + 8001f96: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001f98: 881a ldrh r2, [r3, #0] + 8001f9a: 68fb ldr r3, [r7, #12] + 8001f9c: 681b ldr r3, [r3, #0] + 8001f9e: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001fa0: 68fb ldr r3, [r7, #12] + 8001fa2: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001fa4: 1c9a adds r2, r3, #2 + 8001fa6: 68fb ldr r3, [r7, #12] + 8001fa8: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001faa: 68fb ldr r3, [r7, #12] + 8001fac: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001fae: b29b uxth r3, r3 + 8001fb0: 3b01 subs r3, #1 + 8001fb2: b29a uxth r2, r3 + 8001fb4: 68fb ldr r3, [r7, #12] + 8001fb6: 86da strh r2, [r3, #54] @ 0x36 + 8001fb8: e018 b.n 8001fec + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001fba: f7fe fe6d bl 8000c98 + 8001fbe: 4602 mov r2, r0 + 8001fc0: 69fb ldr r3, [r7, #28] + 8001fc2: 1ad3 subs r3, r2, r3 + 8001fc4: 683a ldr r2, [r7, #0] + 8001fc6: 429a cmp r2, r3 + 8001fc8: d803 bhi.n 8001fd2 + 8001fca: 683b ldr r3, [r7, #0] + 8001fcc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001fd0: d102 bne.n 8001fd8 + 8001fd2: 683b ldr r3, [r7, #0] + 8001fd4: 2b00 cmp r3, #0 + 8001fd6: d109 bne.n 8001fec + { + hspi->State = HAL_SPI_STATE_READY; + 8001fd8: 68fb ldr r3, [r7, #12] + 8001fda: 2201 movs r2, #1 + 8001fdc: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001fe0: 68fb ldr r3, [r7, #12] + 8001fe2: 2200 movs r2, #0 + 8001fe4: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001fe8: 2303 movs r3, #3 + 8001fea: e082 b.n 80020f2 + while (hspi->TxXferCount > 0U) + 8001fec: 68fb ldr r3, [r7, #12] + 8001fee: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001ff0: b29b uxth r3, r3 + 8001ff2: 2b00 cmp r3, #0 + 8001ff4: d1c7 bne.n 8001f86 + 8001ff6: e053 b.n 80020a0 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001ff8: 68fb ldr r3, [r7, #12] + 8001ffa: 685b ldr r3, [r3, #4] + 8001ffc: 2b00 cmp r3, #0 + 8001ffe: d002 beq.n 8002006 + 8002000: 8b7b ldrh r3, [r7, #26] + 8002002: 2b01 cmp r3, #1 + 8002004: d147 bne.n 8002096 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8002006: 68fb ldr r3, [r7, #12] + 8002008: 6b1a ldr r2, [r3, #48] @ 0x30 + 800200a: 68fb ldr r3, [r7, #12] + 800200c: 681b ldr r3, [r3, #0] + 800200e: 330c adds r3, #12 + 8002010: 7812 ldrb r2, [r2, #0] + 8002012: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8002014: 68fb ldr r3, [r7, #12] + 8002016: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002018: 1c5a adds r2, r3, #1 + 800201a: 68fb ldr r3, [r7, #12] + 800201c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 800201e: 68fb ldr r3, [r7, #12] + 8002020: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002022: b29b uxth r3, r3 + 8002024: 3b01 subs r3, #1 + 8002026: b29a uxth r2, r3 + 8002028: 68fb ldr r3, [r7, #12] + 800202a: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 800202c: e033 b.n 8002096 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 800202e: 68fb ldr r3, [r7, #12] + 8002030: 681b ldr r3, [r3, #0] + 8002032: 689b ldr r3, [r3, #8] + 8002034: f003 0302 and.w r3, r3, #2 + 8002038: 2b02 cmp r3, #2 + 800203a: d113 bne.n 8002064 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 800203c: 68fb ldr r3, [r7, #12] + 800203e: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002040: 68fb ldr r3, [r7, #12] + 8002042: 681b ldr r3, [r3, #0] + 8002044: 330c adds r3, #12 + 8002046: 7812 ldrb r2, [r2, #0] + 8002048: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 800204a: 68fb ldr r3, [r7, #12] + 800204c: 6b1b ldr r3, [r3, #48] @ 0x30 + 800204e: 1c5a adds r2, r3, #1 + 8002050: 68fb ldr r3, [r7, #12] + 8002052: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8002054: 68fb ldr r3, [r7, #12] + 8002056: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002058: b29b uxth r3, r3 + 800205a: 3b01 subs r3, #1 + 800205c: b29a uxth r2, r3 + 800205e: 68fb ldr r3, [r7, #12] + 8002060: 86da strh r2, [r3, #54] @ 0x36 + 8002062: e018 b.n 8002096 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8002064: f7fe fe18 bl 8000c98 + 8002068: 4602 mov r2, r0 + 800206a: 69fb ldr r3, [r7, #28] + 800206c: 1ad3 subs r3, r2, r3 + 800206e: 683a ldr r2, [r7, #0] + 8002070: 429a cmp r2, r3 + 8002072: d803 bhi.n 800207c + 8002074: 683b ldr r3, [r7, #0] + 8002076: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800207a: d102 bne.n 8002082 + 800207c: 683b ldr r3, [r7, #0] + 800207e: 2b00 cmp r3, #0 + 8002080: d109 bne.n 8002096 + { + hspi->State = HAL_SPI_STATE_READY; + 8002082: 68fb ldr r3, [r7, #12] + 8002084: 2201 movs r2, #1 + 8002086: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 800208a: 68fb ldr r3, [r7, #12] + 800208c: 2200 movs r2, #0 + 800208e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8002092: 2303 movs r3, #3 + 8002094: e02d b.n 80020f2 + while (hspi->TxXferCount > 0U) + 8002096: 68fb ldr r3, [r7, #12] + 8002098: 8edb ldrh r3, [r3, #54] @ 0x36 + 800209a: b29b uxth r3, r3 + 800209c: 2b00 cmp r3, #0 + 800209e: d1c6 bne.n 800202e + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 80020a0: 69fa ldr r2, [r7, #28] + 80020a2: 6839 ldr r1, [r7, #0] + 80020a4: 68f8 ldr r0, [r7, #12] + 80020a6: f000 f8b1 bl 800220c + 80020aa: 4603 mov r3, r0 + 80020ac: 2b00 cmp r3, #0 + 80020ae: d002 beq.n 80020b6 + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 80020b0: 68fb ldr r3, [r7, #12] + 80020b2: 2220 movs r2, #32 + 80020b4: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 80020b6: 68fb ldr r3, [r7, #12] + 80020b8: 689b ldr r3, [r3, #8] + 80020ba: 2b00 cmp r3, #0 + 80020bc: d10a bne.n 80020d4 + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 80020be: 2300 movs r3, #0 + 80020c0: 617b str r3, [r7, #20] + 80020c2: 68fb ldr r3, [r7, #12] + 80020c4: 681b ldr r3, [r3, #0] + 80020c6: 68db ldr r3, [r3, #12] + 80020c8: 617b str r3, [r7, #20] + 80020ca: 68fb ldr r3, [r7, #12] + 80020cc: 681b ldr r3, [r3, #0] + 80020ce: 689b ldr r3, [r3, #8] + 80020d0: 617b str r3, [r7, #20] + 80020d2: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 80020d4: 68fb ldr r3, [r7, #12] + 80020d6: 2201 movs r2, #1 + 80020d8: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80020dc: 68fb ldr r3, [r7, #12] + 80020de: 2200 movs r2, #0 + 80020e0: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 80020e4: 68fb ldr r3, [r7, #12] + 80020e6: 6d5b ldr r3, [r3, #84] @ 0x54 + 80020e8: 2b00 cmp r3, #0 + 80020ea: d001 beq.n 80020f0 + { + return HAL_ERROR; + 80020ec: 2301 movs r3, #1 + 80020ee: e000 b.n 80020f2 + } + else + { + return HAL_OK; + 80020f0: 2300 movs r3, #0 + } +} + 80020f2: 4618 mov r0, r3 + 80020f4: 3720 adds r7, #32 + 80020f6: 46bd mov sp, r7 + 80020f8: bd80 pop {r7, pc} + ... + +080020fc : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 80020fc: b580 push {r7, lr} + 80020fe: b088 sub sp, #32 + 8002100: af00 add r7, sp, #0 + 8002102: 60f8 str r0, [r7, #12] + 8002104: 60b9 str r1, [r7, #8] + 8002106: 603b str r3, [r7, #0] + 8002108: 4613 mov r3, r2 + 800210a: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 800210c: f7fe fdc4 bl 8000c98 + 8002110: 4602 mov r2, r0 + 8002112: 6abb ldr r3, [r7, #40] @ 0x28 + 8002114: 1a9b subs r3, r3, r2 + 8002116: 683a ldr r2, [r7, #0] + 8002118: 4413 add r3, r2 + 800211a: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 800211c: f7fe fdbc bl 8000c98 + 8002120: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 8002122: 4b39 ldr r3, [pc, #228] @ (8002208 ) + 8002124: 681b ldr r3, [r3, #0] + 8002126: 015b lsls r3, r3, #5 + 8002128: 0d1b lsrs r3, r3, #20 + 800212a: 69fa ldr r2, [r7, #28] + 800212c: fb02 f303 mul.w r3, r2, r3 + 8002130: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8002132: e054 b.n 80021de + { + if (Timeout != HAL_MAX_DELAY) + 8002134: 683b ldr r3, [r7, #0] + 8002136: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800213a: d050 beq.n 80021de + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 800213c: f7fe fdac bl 8000c98 + 8002140: 4602 mov r2, r0 + 8002142: 69bb ldr r3, [r7, #24] + 8002144: 1ad3 subs r3, r2, r3 + 8002146: 69fa ldr r2, [r7, #28] + 8002148: 429a cmp r2, r3 + 800214a: d902 bls.n 8002152 + 800214c: 69fb ldr r3, [r7, #28] + 800214e: 2b00 cmp r3, #0 + 8002150: d13d bne.n 80021ce + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8002152: 68fb ldr r3, [r7, #12] + 8002154: 681b ldr r3, [r3, #0] + 8002156: 685a ldr r2, [r3, #4] + 8002158: 68fb ldr r3, [r7, #12] + 800215a: 681b ldr r3, [r3, #0] + 800215c: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8002160: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8002162: 68fb ldr r3, [r7, #12] + 8002164: 685b ldr r3, [r3, #4] + 8002166: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 800216a: d111 bne.n 8002190 + 800216c: 68fb ldr r3, [r7, #12] + 800216e: 689b ldr r3, [r3, #8] + 8002170: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8002174: d004 beq.n 8002180 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 8002176: 68fb ldr r3, [r7, #12] + 8002178: 689b ldr r3, [r3, #8] + 800217a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 800217e: d107 bne.n 8002190 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8002180: 68fb ldr r3, [r7, #12] + 8002182: 681b ldr r3, [r3, #0] + 8002184: 681a ldr r2, [r3, #0] + 8002186: 68fb ldr r3, [r7, #12] + 8002188: 681b ldr r3, [r3, #0] + 800218a: f022 0240 bic.w r2, r2, #64 @ 0x40 + 800218e: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8002190: 68fb ldr r3, [r7, #12] + 8002192: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002194: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002198: d10f bne.n 80021ba + { + SPI_RESET_CRC(hspi); + 800219a: 68fb ldr r3, [r7, #12] + 800219c: 681b ldr r3, [r3, #0] + 800219e: 681a ldr r2, [r3, #0] + 80021a0: 68fb ldr r3, [r7, #12] + 80021a2: 681b ldr r3, [r3, #0] + 80021a4: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 80021a8: 601a str r2, [r3, #0] + 80021aa: 68fb ldr r3, [r7, #12] + 80021ac: 681b ldr r3, [r3, #0] + 80021ae: 681a ldr r2, [r3, #0] + 80021b0: 68fb ldr r3, [r7, #12] + 80021b2: 681b ldr r3, [r3, #0] + 80021b4: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 80021b8: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 80021ba: 68fb ldr r3, [r7, #12] + 80021bc: 2201 movs r2, #1 + 80021be: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80021c2: 68fb ldr r3, [r7, #12] + 80021c4: 2200 movs r2, #0 + 80021c6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 80021ca: 2303 movs r3, #3 + 80021cc: e017 b.n 80021fe + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 80021ce: 697b ldr r3, [r7, #20] + 80021d0: 2b00 cmp r3, #0 + 80021d2: d101 bne.n 80021d8 + { + tmp_timeout = 0U; + 80021d4: 2300 movs r3, #0 + 80021d6: 61fb str r3, [r7, #28] + } + count--; + 80021d8: 697b ldr r3, [r7, #20] + 80021da: 3b01 subs r3, #1 + 80021dc: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 80021de: 68fb ldr r3, [r7, #12] + 80021e0: 681b ldr r3, [r3, #0] + 80021e2: 689a ldr r2, [r3, #8] + 80021e4: 68bb ldr r3, [r7, #8] + 80021e6: 4013 ands r3, r2 + 80021e8: 68ba ldr r2, [r7, #8] + 80021ea: 429a cmp r2, r3 + 80021ec: bf0c ite eq + 80021ee: 2301 moveq r3, #1 + 80021f0: 2300 movne r3, #0 + 80021f2: b2db uxtb r3, r3 + 80021f4: 461a mov r2, r3 + 80021f6: 79fb ldrb r3, [r7, #7] + 80021f8: 429a cmp r2, r3 + 80021fa: d19b bne.n 8002134 + } + } + + return HAL_OK; + 80021fc: 2300 movs r3, #0 +} + 80021fe: 4618 mov r0, r3 + 8002200: 3720 adds r7, #32 + 8002202: 46bd mov sp, r7 + 8002204: bd80 pop {r7, pc} + 8002206: bf00 nop + 8002208: 20000000 .word 0x20000000 + +0800220c : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 800220c: b580 push {r7, lr} + 800220e: b088 sub sp, #32 + 8002210: af02 add r7, sp, #8 + 8002212: 60f8 str r0, [r7, #12] + 8002214: 60b9 str r1, [r7, #8] + 8002216: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 8002218: 687b ldr r3, [r7, #4] + 800221a: 9300 str r3, [sp, #0] + 800221c: 68bb ldr r3, [r7, #8] + 800221e: 2201 movs r2, #1 + 8002220: 2102 movs r1, #2 + 8002222: 68f8 ldr r0, [r7, #12] + 8002224: f7ff ff6a bl 80020fc + 8002228: 4603 mov r3, r0 + 800222a: 2b00 cmp r3, #0 + 800222c: d007 beq.n 800223e + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800222e: 68fb ldr r3, [r7, #12] + 8002230: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002232: f043 0220 orr.w r2, r3, #32 + 8002236: 68fb ldr r3, [r7, #12] + 8002238: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 800223a: 2303 movs r3, #3 + 800223c: e032 b.n 80022a4 + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 800223e: 4b1b ldr r3, [pc, #108] @ (80022ac ) + 8002240: 681b ldr r3, [r3, #0] + 8002242: 4a1b ldr r2, [pc, #108] @ (80022b0 ) + 8002244: fba2 2303 umull r2, r3, r2, r3 + 8002248: 0d5b lsrs r3, r3, #21 + 800224a: f44f 727a mov.w r2, #1000 @ 0x3e8 + 800224e: fb02 f303 mul.w r3, r2, r3 + 8002252: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8002254: 68fb ldr r3, [r7, #12] + 8002256: 685b ldr r3, [r3, #4] + 8002258: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 800225c: d112 bne.n 8002284 + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 800225e: 687b ldr r3, [r7, #4] + 8002260: 9300 str r3, [sp, #0] + 8002262: 68bb ldr r3, [r7, #8] + 8002264: 2200 movs r2, #0 + 8002266: 2180 movs r1, #128 @ 0x80 + 8002268: 68f8 ldr r0, [r7, #12] + 800226a: f7ff ff47 bl 80020fc + 800226e: 4603 mov r3, r0 + 8002270: 2b00 cmp r3, #0 + 8002272: d016 beq.n 80022a2 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002274: 68fb ldr r3, [r7, #12] + 8002276: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002278: f043 0220 orr.w r2, r3, #32 + 800227c: 68fb ldr r3, [r7, #12] + 800227e: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8002280: 2303 movs r3, #3 + 8002282: e00f b.n 80022a4 + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 8002284: 697b ldr r3, [r7, #20] + 8002286: 2b00 cmp r3, #0 + 8002288: d00a beq.n 80022a0 + { + break; + } + count--; + 800228a: 697b ldr r3, [r7, #20] + 800228c: 3b01 subs r3, #1 + 800228e: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 8002290: 68fb ldr r3, [r7, #12] + 8002292: 681b ldr r3, [r3, #0] + 8002294: 689b ldr r3, [r3, #8] + 8002296: f003 0380 and.w r3, r3, #128 @ 0x80 + 800229a: 2b80 cmp r3, #128 @ 0x80 + 800229c: d0f2 beq.n 8002284 + 800229e: e000 b.n 80022a2 + break; + 80022a0: bf00 nop + } + + return HAL_OK; + 80022a2: 2300 movs r3, #0 +} + 80022a4: 4618 mov r0, r3 + 80022a6: 3718 adds r7, #24 + 80022a8: 46bd mov sp, r7 + 80022aa: bd80 pop {r7, pc} + 80022ac: 20000000 .word 0x20000000 + 80022b0: 165e9f81 .word 0x165e9f81 + +080022b4 : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 80022b4: b580 push {r7, lr} + 80022b6: b082 sub sp, #8 + 80022b8: af00 add r7, sp, #0 + 80022ba: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80022bc: 687b ldr r3, [r7, #4] + 80022be: 2b00 cmp r3, #0 + 80022c0: d101 bne.n 80022c6 + { + return HAL_ERROR; + 80022c2: 2301 movs r3, #1 + 80022c4: e031 b.n 800232a + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80022c6: 687b ldr r3, [r7, #4] + 80022c8: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 80022cc: b2db uxtb r3, r3 + 80022ce: 2b00 cmp r3, #0 + 80022d0: d106 bne.n 80022e0 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80022d2: 687b ldr r3, [r7, #4] + 80022d4: 2200 movs r2, #0 + 80022d6: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 80022da: 6878 ldr r0, [r7, #4] + 80022dc: f7fe fb0c bl 80008f8 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 80022e0: 687b ldr r3, [r7, #4] + 80022e2: 2202 movs r2, #2 + 80022e4: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 80022e8: 687b ldr r3, [r7, #4] + 80022ea: 681a ldr r2, [r3, #0] + 80022ec: 687b ldr r3, [r7, #4] + 80022ee: 3304 adds r3, #4 + 80022f0: 4619 mov r1, r3 + 80022f2: 4610 mov r0, r2 + 80022f4: f000 fb7e bl 80029f4 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 80022f8: 687b ldr r3, [r7, #4] + 80022fa: 2201 movs r2, #1 + 80022fc: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8002300: 687b ldr r3, [r7, #4] + 8002302: 2201 movs r2, #1 + 8002304: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002308: 687b ldr r3, [r7, #4] + 800230a: 2201 movs r2, #1 + 800230c: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002310: 687b ldr r3, [r7, #4] + 8002312: 2201 movs r2, #1 + 8002314: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002318: 687b ldr r3, [r7, #4] + 800231a: 2201 movs r2, #1 + 800231c: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8002320: 687b ldr r3, [r7, #4] + 8002322: 2201 movs r2, #1 + 8002324: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 8002328: 2300 movs r3, #0 +} + 800232a: 4618 mov r0, r3 + 800232c: 3708 adds r7, #8 + 800232e: 46bd mov sp, r7 + 8002330: bd80 pop {r7, pc} + +08002332 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8002332: b580 push {r7, lr} + 8002334: b082 sub sp, #8 + 8002336: af00 add r7, sp, #0 + 8002338: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 800233a: 687b ldr r3, [r7, #4] + 800233c: 2b00 cmp r3, #0 + 800233e: d101 bne.n 8002344 + { + return HAL_ERROR; + 8002340: 2301 movs r3, #1 + 8002342: e031 b.n 80023a8 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8002344: 687b ldr r3, [r7, #4] + 8002346: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 800234a: b2db uxtb r3, r3 + 800234c: 2b00 cmp r3, #0 + 800234e: d106 bne.n 800235e + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8002350: 687b ldr r3, [r7, #4] + 8002352: 2200 movs r2, #0 + 8002354: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 8002358: 6878 ldr r0, [r7, #4] + 800235a: f000 f829 bl 80023b0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800235e: 687b ldr r3, [r7, #4] + 8002360: 2202 movs r2, #2 + 8002362: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002366: 687b ldr r3, [r7, #4] + 8002368: 681a ldr r2, [r3, #0] + 800236a: 687b ldr r3, [r7, #4] + 800236c: 3304 adds r3, #4 + 800236e: 4619 mov r1, r3 + 8002370: 4610 mov r0, r2 + 8002372: f000 fb3f bl 80029f4 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002376: 687b ldr r3, [r7, #4] + 8002378: 2201 movs r2, #1 + 800237a: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 800237e: 687b ldr r3, [r7, #4] + 8002380: 2201 movs r2, #1 + 8002382: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002386: 687b ldr r3, [r7, #4] + 8002388: 2201 movs r2, #1 + 800238a: f883 203b strb.w r2, [r3, #59] @ 0x3b + 800238e: 687b ldr r3, [r7, #4] + 8002390: 2201 movs r2, #1 + 8002392: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002396: 687b ldr r3, [r7, #4] + 8002398: 2201 movs r2, #1 + 800239a: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800239e: 687b ldr r3, [r7, #4] + 80023a0: 2201 movs r2, #1 + 80023a2: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 80023a6: 2300 movs r3, #0 +} + 80023a8: 4618 mov r0, r3 + 80023aa: 3708 adds r7, #8 + 80023ac: 46bd mov sp, r7 + 80023ae: bd80 pop {r7, pc} + +080023b0 : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 80023b0: b480 push {r7} + 80023b2: b083 sub sp, #12 + 80023b4: af00 add r7, sp, #0 + 80023b6: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 80023b8: bf00 nop + 80023ba: 370c adds r7, #12 + 80023bc: 46bd mov sp, r7 + 80023be: bc80 pop {r7} + 80023c0: 4770 bx lr + ... + +080023c4 : + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 80023c4: b580 push {r7, lr} + 80023c6: b084 sub sp, #16 + 80023c8: af00 add r7, sp, #0 + 80023ca: 6078 str r0, [r7, #4] + 80023cc: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 80023ce: 683b ldr r3, [r7, #0] + 80023d0: 2b00 cmp r3, #0 + 80023d2: d109 bne.n 80023e8 + 80023d4: 687b ldr r3, [r7, #4] + 80023d6: f893 303a ldrb.w r3, [r3, #58] @ 0x3a + 80023da: b2db uxtb r3, r3 + 80023dc: 2b01 cmp r3, #1 + 80023de: bf14 ite ne + 80023e0: 2301 movne r3, #1 + 80023e2: 2300 moveq r3, #0 + 80023e4: b2db uxtb r3, r3 + 80023e6: e022 b.n 800242e + 80023e8: 683b ldr r3, [r7, #0] + 80023ea: 2b04 cmp r3, #4 + 80023ec: d109 bne.n 8002402 + 80023ee: 687b ldr r3, [r7, #4] + 80023f0: f893 303b ldrb.w r3, [r3, #59] @ 0x3b + 80023f4: b2db uxtb r3, r3 + 80023f6: 2b01 cmp r3, #1 + 80023f8: bf14 ite ne + 80023fa: 2301 movne r3, #1 + 80023fc: 2300 moveq r3, #0 + 80023fe: b2db uxtb r3, r3 + 8002400: e015 b.n 800242e + 8002402: 683b ldr r3, [r7, #0] + 8002404: 2b08 cmp r3, #8 + 8002406: d109 bne.n 800241c + 8002408: 687b ldr r3, [r7, #4] + 800240a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 800240e: b2db uxtb r3, r3 + 8002410: 2b01 cmp r3, #1 + 8002412: bf14 ite ne + 8002414: 2301 movne r3, #1 + 8002416: 2300 moveq r3, #0 + 8002418: b2db uxtb r3, r3 + 800241a: e008 b.n 800242e + 800241c: 687b ldr r3, [r7, #4] + 800241e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8002422: b2db uxtb r3, r3 + 8002424: 2b01 cmp r3, #1 + 8002426: bf14 ite ne + 8002428: 2301 movne r3, #1 + 800242a: 2300 moveq r3, #0 + 800242c: b2db uxtb r3, r3 + 800242e: 2b00 cmp r3, #0 + 8002430: d001 beq.n 8002436 + { + return HAL_ERROR; + 8002432: 2301 movs r3, #1 + 8002434: e051 b.n 80024da + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 8002436: 683b ldr r3, [r7, #0] + 8002438: 2b00 cmp r3, #0 + 800243a: d104 bne.n 8002446 + 800243c: 687b ldr r3, [r7, #4] + 800243e: 2202 movs r2, #2 + 8002440: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002444: e013 b.n 800246e + 8002446: 683b ldr r3, [r7, #0] + 8002448: 2b04 cmp r3, #4 + 800244a: d104 bne.n 8002456 + 800244c: 687b ldr r3, [r7, #4] + 800244e: 2202 movs r2, #2 + 8002450: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002454: e00b b.n 800246e + 8002456: 683b ldr r3, [r7, #0] + 8002458: 2b08 cmp r3, #8 + 800245a: d104 bne.n 8002466 + 800245c: 687b ldr r3, [r7, #4] + 800245e: 2202 movs r2, #2 + 8002460: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002464: e003 b.n 800246e + 8002466: 687b ldr r3, [r7, #4] + 8002468: 2202 movs r2, #2 + 800246a: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 800246e: 687b ldr r3, [r7, #4] + 8002470: 681b ldr r3, [r3, #0] + 8002472: 2201 movs r2, #1 + 8002474: 6839 ldr r1, [r7, #0] + 8002476: 4618 mov r0, r3 + 8002478: f000 fcbd bl 8002df6 + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 800247c: 687b ldr r3, [r7, #4] + 800247e: 681b ldr r3, [r3, #0] + 8002480: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002484: d00e beq.n 80024a4 + 8002486: 687b ldr r3, [r7, #4] + 8002488: 681b ldr r3, [r3, #0] + 800248a: 4a16 ldr r2, [pc, #88] @ (80024e4 ) + 800248c: 4293 cmp r3, r2 + 800248e: d009 beq.n 80024a4 + 8002490: 687b ldr r3, [r7, #4] + 8002492: 681b ldr r3, [r3, #0] + 8002494: 4a14 ldr r2, [pc, #80] @ (80024e8 ) + 8002496: 4293 cmp r3, r2 + 8002498: d004 beq.n 80024a4 + 800249a: 687b ldr r3, [r7, #4] + 800249c: 681b ldr r3, [r3, #0] + 800249e: 4a13 ldr r2, [pc, #76] @ (80024ec ) + 80024a0: 4293 cmp r3, r2 + 80024a2: d111 bne.n 80024c8 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 80024a4: 687b ldr r3, [r7, #4] + 80024a6: 681b ldr r3, [r3, #0] + 80024a8: 689b ldr r3, [r3, #8] + 80024aa: f003 0307 and.w r3, r3, #7 + 80024ae: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80024b0: 68fb ldr r3, [r7, #12] + 80024b2: 2b06 cmp r3, #6 + 80024b4: d010 beq.n 80024d8 + { + __HAL_TIM_ENABLE(htim); + 80024b6: 687b ldr r3, [r7, #4] + 80024b8: 681b ldr r3, [r3, #0] + 80024ba: 681a ldr r2, [r3, #0] + 80024bc: 687b ldr r3, [r7, #4] + 80024be: 681b ldr r3, [r3, #0] + 80024c0: f042 0201 orr.w r2, r2, #1 + 80024c4: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80024c6: e007 b.n 80024d8 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 80024c8: 687b ldr r3, [r7, #4] + 80024ca: 681b ldr r3, [r3, #0] + 80024cc: 681a ldr r2, [r3, #0] + 80024ce: 687b ldr r3, [r7, #4] + 80024d0: 681b ldr r3, [r3, #0] + 80024d2: f042 0201 orr.w r2, r2, #1 + 80024d6: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 80024d8: 2300 movs r3, #0 +} + 80024da: 4618 mov r0, r3 + 80024dc: 3710 adds r7, #16 + 80024de: 46bd mov sp, r7 + 80024e0: bd80 pop {r7, pc} + 80024e2: bf00 nop + 80024e4: 40000400 .word 0x40000400 + 80024e8: 40000800 .word 0x40000800 + 80024ec: 40010800 .word 0x40010800 + +080024f0 : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 80024f0: b580 push {r7, lr} + 80024f2: b084 sub sp, #16 + 80024f4: af00 add r7, sp, #0 + 80024f6: 6078 str r0, [r7, #4] + uint32_t itsource = htim->Instance->DIER; + 80024f8: 687b ldr r3, [r7, #4] + 80024fa: 681b ldr r3, [r3, #0] + 80024fc: 68db ldr r3, [r3, #12] + 80024fe: 60fb str r3, [r7, #12] + uint32_t itflag = htim->Instance->SR; + 8002500: 687b ldr r3, [r7, #4] + 8002502: 681b ldr r3, [r3, #0] + 8002504: 691b ldr r3, [r3, #16] + 8002506: 60bb str r3, [r7, #8] + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + 8002508: 68bb ldr r3, [r7, #8] + 800250a: f003 0302 and.w r3, r3, #2 + 800250e: 2b00 cmp r3, #0 + 8002510: d020 beq.n 8002554 + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + 8002512: 68fb ldr r3, [r7, #12] + 8002514: f003 0302 and.w r3, r3, #2 + 8002518: 2b00 cmp r3, #0 + 800251a: d01b beq.n 8002554 + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + 800251c: 687b ldr r3, [r7, #4] + 800251e: 681b ldr r3, [r3, #0] + 8002520: f06f 0202 mvn.w r2, #2 + 8002524: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 8002526: 687b ldr r3, [r7, #4] + 8002528: 2201 movs r2, #1 + 800252a: 761a strb r2, [r3, #24] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 800252c: 687b ldr r3, [r7, #4] + 800252e: 681b ldr r3, [r3, #0] + 8002530: 699b ldr r3, [r3, #24] + 8002532: f003 0303 and.w r3, r3, #3 + 8002536: 2b00 cmp r3, #0 + 8002538: d003 beq.n 8002542 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 800253a: 6878 ldr r0, [r7, #4] + 800253c: f000 fa3f bl 80029be + 8002540: e005 b.n 800254e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002542: 6878 ldr r0, [r7, #4] + 8002544: f000 fa32 bl 80029ac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002548: 6878 ldr r0, [r7, #4] + 800254a: f000 fa41 bl 80029d0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 800254e: 687b ldr r3, [r7, #4] + 8002550: 2200 movs r2, #0 + 8002552: 761a strb r2, [r3, #24] + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + 8002554: 68bb ldr r3, [r7, #8] + 8002556: f003 0304 and.w r3, r3, #4 + 800255a: 2b00 cmp r3, #0 + 800255c: d020 beq.n 80025a0 + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + 800255e: 68fb ldr r3, [r7, #12] + 8002560: f003 0304 and.w r3, r3, #4 + 8002564: 2b00 cmp r3, #0 + 8002566: d01b beq.n 80025a0 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + 8002568: 687b ldr r3, [r7, #4] + 800256a: 681b ldr r3, [r3, #0] + 800256c: f06f 0204 mvn.w r2, #4 + 8002570: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8002572: 687b ldr r3, [r7, #4] + 8002574: 2202 movs r2, #2 + 8002576: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8002578: 687b ldr r3, [r7, #4] + 800257a: 681b ldr r3, [r3, #0] + 800257c: 699b ldr r3, [r3, #24] + 800257e: f403 7340 and.w r3, r3, #768 @ 0x300 + 8002582: 2b00 cmp r3, #0 + 8002584: d003 beq.n 800258e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002586: 6878 ldr r0, [r7, #4] + 8002588: f000 fa19 bl 80029be + 800258c: e005 b.n 800259a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800258e: 6878 ldr r0, [r7, #4] + 8002590: f000 fa0c bl 80029ac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002594: 6878 ldr r0, [r7, #4] + 8002596: f000 fa1b bl 80029d0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 800259a: 687b ldr r3, [r7, #4] + 800259c: 2200 movs r2, #0 + 800259e: 761a strb r2, [r3, #24] + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + 80025a0: 68bb ldr r3, [r7, #8] + 80025a2: f003 0308 and.w r3, r3, #8 + 80025a6: 2b00 cmp r3, #0 + 80025a8: d020 beq.n 80025ec + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + 80025aa: 68fb ldr r3, [r7, #12] + 80025ac: f003 0308 and.w r3, r3, #8 + 80025b0: 2b00 cmp r3, #0 + 80025b2: d01b beq.n 80025ec + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + 80025b4: 687b ldr r3, [r7, #4] + 80025b6: 681b ldr r3, [r3, #0] + 80025b8: f06f 0208 mvn.w r2, #8 + 80025bc: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 80025be: 687b ldr r3, [r7, #4] + 80025c0: 2204 movs r2, #4 + 80025c2: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 80025c4: 687b ldr r3, [r7, #4] + 80025c6: 681b ldr r3, [r3, #0] + 80025c8: 69db ldr r3, [r3, #28] + 80025ca: f003 0303 and.w r3, r3, #3 + 80025ce: 2b00 cmp r3, #0 + 80025d0: d003 beq.n 80025da + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 80025d2: 6878 ldr r0, [r7, #4] + 80025d4: f000 f9f3 bl 80029be + 80025d8: e005 b.n 80025e6 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80025da: 6878 ldr r0, [r7, #4] + 80025dc: f000 f9e6 bl 80029ac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80025e0: 6878 ldr r0, [r7, #4] + 80025e2: f000 f9f5 bl 80029d0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80025e6: 687b ldr r3, [r7, #4] + 80025e8: 2200 movs r2, #0 + 80025ea: 761a strb r2, [r3, #24] + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + 80025ec: 68bb ldr r3, [r7, #8] + 80025ee: f003 0310 and.w r3, r3, #16 + 80025f2: 2b00 cmp r3, #0 + 80025f4: d020 beq.n 8002638 + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + 80025f6: 68fb ldr r3, [r7, #12] + 80025f8: f003 0310 and.w r3, r3, #16 + 80025fc: 2b00 cmp r3, #0 + 80025fe: d01b beq.n 8002638 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + 8002600: 687b ldr r3, [r7, #4] + 8002602: 681b ldr r3, [r3, #0] + 8002604: f06f 0210 mvn.w r2, #16 + 8002608: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 800260a: 687b ldr r3, [r7, #4] + 800260c: 2208 movs r2, #8 + 800260e: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8002610: 687b ldr r3, [r7, #4] + 8002612: 681b ldr r3, [r3, #0] + 8002614: 69db ldr r3, [r3, #28] + 8002616: f403 7340 and.w r3, r3, #768 @ 0x300 + 800261a: 2b00 cmp r3, #0 + 800261c: d003 beq.n 8002626 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 800261e: 6878 ldr r0, [r7, #4] + 8002620: f000 f9cd bl 80029be + 8002624: e005 b.n 8002632 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002626: 6878 ldr r0, [r7, #4] + 8002628: f000 f9c0 bl 80029ac + HAL_TIM_PWM_PulseFinishedCallback(htim); + 800262c: 6878 ldr r0, [r7, #4] + 800262e: f000 f9cf bl 80029d0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002632: 687b ldr r3, [r7, #4] + 8002634: 2200 movs r2, #0 + 8002636: 761a strb r2, [r3, #24] + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + 8002638: 68bb ldr r3, [r7, #8] + 800263a: f003 0301 and.w r3, r3, #1 + 800263e: 2b00 cmp r3, #0 + 8002640: d00c beq.n 800265c + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + 8002642: 68fb ldr r3, [r7, #12] + 8002644: f003 0301 and.w r3, r3, #1 + 8002648: 2b00 cmp r3, #0 + 800264a: d007 beq.n 800265c + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); + 800264c: 687b ldr r3, [r7, #4] + 800264e: 681b ldr r3, [r3, #0] + 8002650: f06f 0201 mvn.w r2, #1 + 8002654: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 8002656: 6878 ldr r0, [r7, #4] + 8002658: f000 f99f bl 800299a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + 800265c: 68bb ldr r3, [r7, #8] + 800265e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002662: 2b00 cmp r3, #0 + 8002664: d00c beq.n 8002680 + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + 8002666: 68fb ldr r3, [r7, #12] + 8002668: f003 0340 and.w r3, r3, #64 @ 0x40 + 800266c: 2b00 cmp r3, #0 + 800266e: d007 beq.n 8002680 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); + 8002670: 687b ldr r3, [r7, #4] + 8002672: 681b ldr r3, [r3, #0] + 8002674: f06f 0240 mvn.w r2, #64 @ 0x40 + 8002678: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 800267a: 6878 ldr r0, [r7, #4] + 800267c: f000 f9b1 bl 80029e2 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 8002680: bf00 nop + 8002682: 3710 adds r7, #16 + 8002684: 46bd mov sp, r7 + 8002686: bd80 pop {r7, pc} + +08002688 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8002688: b580 push {r7, lr} + 800268a: b086 sub sp, #24 + 800268c: af00 add r7, sp, #0 + 800268e: 60f8 str r0, [r7, #12] + 8002690: 60b9 str r1, [r7, #8] + 8002692: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002694: 2300 movs r3, #0 + 8002696: 75fb strb r3, [r7, #23] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8002698: 68fb ldr r3, [r7, #12] + 800269a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 800269e: 2b01 cmp r3, #1 + 80026a0: d101 bne.n 80026a6 + 80026a2: 2302 movs r3, #2 + 80026a4: e0ae b.n 8002804 + 80026a6: 68fb ldr r3, [r7, #12] + 80026a8: 2201 movs r2, #1 + 80026aa: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + switch (Channel) + 80026ae: 687b ldr r3, [r7, #4] + 80026b0: 2b0c cmp r3, #12 + 80026b2: f200 809f bhi.w 80027f4 + 80026b6: a201 add r2, pc, #4 @ (adr r2, 80026bc ) + 80026b8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80026bc: 080026f1 .word 0x080026f1 + 80026c0: 080027f5 .word 0x080027f5 + 80026c4: 080027f5 .word 0x080027f5 + 80026c8: 080027f5 .word 0x080027f5 + 80026cc: 08002731 .word 0x08002731 + 80026d0: 080027f5 .word 0x080027f5 + 80026d4: 080027f5 .word 0x080027f5 + 80026d8: 080027f5 .word 0x080027f5 + 80026dc: 08002773 .word 0x08002773 + 80026e0: 080027f5 .word 0x080027f5 + 80026e4: 080027f5 .word 0x080027f5 + 80026e8: 080027f5 .word 0x080027f5 + 80026ec: 080027b3 .word 0x080027b3 + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 80026f0: 68fb ldr r3, [r7, #12] + 80026f2: 681b ldr r3, [r3, #0] + 80026f4: 68b9 ldr r1, [r7, #8] + 80026f6: 4618 mov r0, r3 + 80026f8: f000 f9f2 bl 8002ae0 + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 80026fc: 68fb ldr r3, [r7, #12] + 80026fe: 681b ldr r3, [r3, #0] + 8002700: 699a ldr r2, [r3, #24] + 8002702: 68fb ldr r3, [r7, #12] + 8002704: 681b ldr r3, [r3, #0] + 8002706: f042 0208 orr.w r2, r2, #8 + 800270a: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 800270c: 68fb ldr r3, [r7, #12] + 800270e: 681b ldr r3, [r3, #0] + 8002710: 699a ldr r2, [r3, #24] + 8002712: 68fb ldr r3, [r7, #12] + 8002714: 681b ldr r3, [r3, #0] + 8002716: f022 0204 bic.w r2, r2, #4 + 800271a: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 800271c: 68fb ldr r3, [r7, #12] + 800271e: 681b ldr r3, [r3, #0] + 8002720: 6999 ldr r1, [r3, #24] + 8002722: 68bb ldr r3, [r7, #8] + 8002724: 68da ldr r2, [r3, #12] + 8002726: 68fb ldr r3, [r7, #12] + 8002728: 681b ldr r3, [r3, #0] + 800272a: 430a orrs r2, r1 + 800272c: 619a str r2, [r3, #24] + break; + 800272e: e064 b.n 80027fa + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 8002730: 68fb ldr r3, [r7, #12] + 8002732: 681b ldr r3, [r3, #0] + 8002734: 68b9 ldr r1, [r7, #8] + 8002736: 4618 mov r0, r3 + 8002738: f000 fa0e bl 8002b58 + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 800273c: 68fb ldr r3, [r7, #12] + 800273e: 681b ldr r3, [r3, #0] + 8002740: 699a ldr r2, [r3, #24] + 8002742: 68fb ldr r3, [r7, #12] + 8002744: 681b ldr r3, [r3, #0] + 8002746: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 800274a: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 800274c: 68fb ldr r3, [r7, #12] + 800274e: 681b ldr r3, [r3, #0] + 8002750: 699a ldr r2, [r3, #24] + 8002752: 68fb ldr r3, [r7, #12] + 8002754: 681b ldr r3, [r3, #0] + 8002756: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 800275a: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 800275c: 68fb ldr r3, [r7, #12] + 800275e: 681b ldr r3, [r3, #0] + 8002760: 6999 ldr r1, [r3, #24] + 8002762: 68bb ldr r3, [r7, #8] + 8002764: 68db ldr r3, [r3, #12] + 8002766: 021a lsls r2, r3, #8 + 8002768: 68fb ldr r3, [r7, #12] + 800276a: 681b ldr r3, [r3, #0] + 800276c: 430a orrs r2, r1 + 800276e: 619a str r2, [r3, #24] + break; + 8002770: e043 b.n 80027fa + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 8002772: 68fb ldr r3, [r7, #12] + 8002774: 681b ldr r3, [r3, #0] + 8002776: 68b9 ldr r1, [r7, #8] + 8002778: 4618 mov r0, r3 + 800277a: f000 fa2b bl 8002bd4 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 800277e: 68fb ldr r3, [r7, #12] + 8002780: 681b ldr r3, [r3, #0] + 8002782: 69da ldr r2, [r3, #28] + 8002784: 68fb ldr r3, [r7, #12] + 8002786: 681b ldr r3, [r3, #0] + 8002788: f042 0208 orr.w r2, r2, #8 + 800278c: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 800278e: 68fb ldr r3, [r7, #12] + 8002790: 681b ldr r3, [r3, #0] + 8002792: 69da ldr r2, [r3, #28] + 8002794: 68fb ldr r3, [r7, #12] + 8002796: 681b ldr r3, [r3, #0] + 8002798: f022 0204 bic.w r2, r2, #4 + 800279c: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 800279e: 68fb ldr r3, [r7, #12] + 80027a0: 681b ldr r3, [r3, #0] + 80027a2: 69d9 ldr r1, [r3, #28] + 80027a4: 68bb ldr r3, [r7, #8] + 80027a6: 68da ldr r2, [r3, #12] + 80027a8: 68fb ldr r3, [r7, #12] + 80027aa: 681b ldr r3, [r3, #0] + 80027ac: 430a orrs r2, r1 + 80027ae: 61da str r2, [r3, #28] + break; + 80027b0: e023 b.n 80027fa + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 80027b2: 68fb ldr r3, [r7, #12] + 80027b4: 681b ldr r3, [r3, #0] + 80027b6: 68b9 ldr r1, [r7, #8] + 80027b8: 4618 mov r0, r3 + 80027ba: f000 fa48 bl 8002c4e + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 80027be: 68fb ldr r3, [r7, #12] + 80027c0: 681b ldr r3, [r3, #0] + 80027c2: 69da ldr r2, [r3, #28] + 80027c4: 68fb ldr r3, [r7, #12] + 80027c6: 681b ldr r3, [r3, #0] + 80027c8: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 80027cc: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 80027ce: 68fb ldr r3, [r7, #12] + 80027d0: 681b ldr r3, [r3, #0] + 80027d2: 69da ldr r2, [r3, #28] + 80027d4: 68fb ldr r3, [r7, #12] + 80027d6: 681b ldr r3, [r3, #0] + 80027d8: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 80027dc: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 80027de: 68fb ldr r3, [r7, #12] + 80027e0: 681b ldr r3, [r3, #0] + 80027e2: 69d9 ldr r1, [r3, #28] + 80027e4: 68bb ldr r3, [r7, #8] + 80027e6: 68db ldr r3, [r3, #12] + 80027e8: 021a lsls r2, r3, #8 + 80027ea: 68fb ldr r3, [r7, #12] + 80027ec: 681b ldr r3, [r3, #0] + 80027ee: 430a orrs r2, r1 + 80027f0: 61da str r2, [r3, #28] + break; + 80027f2: e002 b.n 80027fa + } + + default: + status = HAL_ERROR; + 80027f4: 2301 movs r3, #1 + 80027f6: 75fb strb r3, [r7, #23] + break; + 80027f8: bf00 nop + } + + __HAL_UNLOCK(htim); + 80027fa: 68fb ldr r3, [r7, #12] + 80027fc: 2200 movs r2, #0 + 80027fe: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 8002802: 7dfb ldrb r3, [r7, #23] +} + 8002804: 4618 mov r0, r3 + 8002806: 3718 adds r7, #24 + 8002808: 46bd mov sp, r7 + 800280a: bd80 pop {r7, pc} + +0800280c : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 800280c: b580 push {r7, lr} + 800280e: b084 sub sp, #16 + 8002810: af00 add r7, sp, #0 + 8002812: 6078 str r0, [r7, #4] + 8002814: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8002816: 2300 movs r3, #0 + 8002818: 73fb strb r3, [r7, #15] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 800281a: 687b ldr r3, [r7, #4] + 800281c: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 8002820: 2b01 cmp r3, #1 + 8002822: d101 bne.n 8002828 + 8002824: 2302 movs r3, #2 + 8002826: e0b4 b.n 8002992 + 8002828: 687b ldr r3, [r7, #4] + 800282a: 2201 movs r2, #1 + 800282c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + htim->State = HAL_TIM_STATE_BUSY; + 8002830: 687b ldr r3, [r7, #4] + 8002832: 2202 movs r2, #2 + 8002834: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 8002838: 687b ldr r3, [r7, #4] + 800283a: 681b ldr r3, [r3, #0] + 800283c: 689b ldr r3, [r3, #8] + 800283e: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8002840: 68bb ldr r3, [r7, #8] + 8002842: f023 0377 bic.w r3, r3, #119 @ 0x77 + 8002846: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8002848: 68bb ldr r3, [r7, #8] + 800284a: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 800284e: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 8002850: 687b ldr r3, [r7, #4] + 8002852: 681b ldr r3, [r3, #0] + 8002854: 68ba ldr r2, [r7, #8] + 8002856: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8002858: 683b ldr r3, [r7, #0] + 800285a: 681b ldr r3, [r3, #0] + 800285c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002860: d03e beq.n 80028e0 + 8002862: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002866: f200 8087 bhi.w 8002978 + 800286a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800286e: f000 8086 beq.w 800297e + 8002872: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002876: d87f bhi.n 8002978 + 8002878: 2b70 cmp r3, #112 @ 0x70 + 800287a: d01a beq.n 80028b2 + 800287c: 2b70 cmp r3, #112 @ 0x70 + 800287e: d87b bhi.n 8002978 + 8002880: 2b60 cmp r3, #96 @ 0x60 + 8002882: d050 beq.n 8002926 + 8002884: 2b60 cmp r3, #96 @ 0x60 + 8002886: d877 bhi.n 8002978 + 8002888: 2b50 cmp r3, #80 @ 0x50 + 800288a: d03c beq.n 8002906 + 800288c: 2b50 cmp r3, #80 @ 0x50 + 800288e: d873 bhi.n 8002978 + 8002890: 2b40 cmp r3, #64 @ 0x40 + 8002892: d058 beq.n 8002946 + 8002894: 2b40 cmp r3, #64 @ 0x40 + 8002896: d86f bhi.n 8002978 + 8002898: 2b30 cmp r3, #48 @ 0x30 + 800289a: d064 beq.n 8002966 + 800289c: 2b30 cmp r3, #48 @ 0x30 + 800289e: d86b bhi.n 8002978 + 80028a0: 2b20 cmp r3, #32 + 80028a2: d060 beq.n 8002966 + 80028a4: 2b20 cmp r3, #32 + 80028a6: d867 bhi.n 8002978 + 80028a8: 2b00 cmp r3, #0 + 80028aa: d05c beq.n 8002966 + 80028ac: 2b10 cmp r3, #16 + 80028ae: d05a beq.n 8002966 + 80028b0: e062 b.n 8002978 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 80028b2: 687b ldr r3, [r7, #4] + 80028b4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 80028b6: 683b ldr r3, [r7, #0] + 80028b8: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 80028ba: 683b ldr r3, [r7, #0] + 80028bc: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 80028be: 683b ldr r3, [r7, #0] + 80028c0: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 80028c2: f000 fa79 bl 8002db8 + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 80028c6: 687b ldr r3, [r7, #4] + 80028c8: 681b ldr r3, [r3, #0] + 80028ca: 689b ldr r3, [r3, #8] + 80028cc: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 80028ce: 68bb ldr r3, [r7, #8] + 80028d0: f043 0377 orr.w r3, r3, #119 @ 0x77 + 80028d4: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 80028d6: 687b ldr r3, [r7, #4] + 80028d8: 681b ldr r3, [r3, #0] + 80028da: 68ba ldr r2, [r7, #8] + 80028dc: 609a str r2, [r3, #8] + break; + 80028de: e04f b.n 8002980 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 80028e0: 687b ldr r3, [r7, #4] + 80028e2: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 80028e4: 683b ldr r3, [r7, #0] + 80028e6: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 80028e8: 683b ldr r3, [r7, #0] + 80028ea: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 80028ec: 683b ldr r3, [r7, #0] + 80028ee: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 80028f0: f000 fa62 bl 8002db8 + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 80028f4: 687b ldr r3, [r7, #4] + 80028f6: 681b ldr r3, [r3, #0] + 80028f8: 689a ldr r2, [r3, #8] + 80028fa: 687b ldr r3, [r7, #4] + 80028fc: 681b ldr r3, [r3, #0] + 80028fe: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8002902: 609a str r2, [r3, #8] + break; + 8002904: e03c b.n 8002980 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 8002906: 687b ldr r3, [r7, #4] + 8002908: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 800290a: 683b ldr r3, [r7, #0] + 800290c: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 800290e: 683b ldr r3, [r7, #0] + 8002910: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 8002912: 461a mov r2, r3 + 8002914: f000 f9d9 bl 8002cca + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 8002918: 687b ldr r3, [r7, #4] + 800291a: 681b ldr r3, [r3, #0] + 800291c: 2150 movs r1, #80 @ 0x50 + 800291e: 4618 mov r0, r3 + 8002920: f000 fa30 bl 8002d84 + break; + 8002924: e02c b.n 8002980 + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 8002926: 687b ldr r3, [r7, #4] + 8002928: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 800292a: 683b ldr r3, [r7, #0] + 800292c: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 800292e: 683b ldr r3, [r7, #0] + 8002930: 68db ldr r3, [r3, #12] + TIM_TI2_ConfigInputStage(htim->Instance, + 8002932: 461a mov r2, r3 + 8002934: f000 f9f7 bl 8002d26 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 8002938: 687b ldr r3, [r7, #4] + 800293a: 681b ldr r3, [r3, #0] + 800293c: 2160 movs r1, #96 @ 0x60 + 800293e: 4618 mov r0, r3 + 8002940: f000 fa20 bl 8002d84 + break; + 8002944: e01c b.n 8002980 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 8002946: 687b ldr r3, [r7, #4] + 8002948: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 800294a: 683b ldr r3, [r7, #0] + 800294c: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 800294e: 683b ldr r3, [r7, #0] + 8002950: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 8002952: 461a mov r2, r3 + 8002954: f000 f9b9 bl 8002cca + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 8002958: 687b ldr r3, [r7, #4] + 800295a: 681b ldr r3, [r3, #0] + 800295c: 2140 movs r1, #64 @ 0x40 + 800295e: 4618 mov r0, r3 + 8002960: f000 fa10 bl 8002d84 + break; + 8002964: e00c b.n 8002980 + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 8002966: 687b ldr r3, [r7, #4] + 8002968: 681a ldr r2, [r3, #0] + 800296a: 683b ldr r3, [r7, #0] + 800296c: 681b ldr r3, [r3, #0] + 800296e: 4619 mov r1, r3 + 8002970: 4610 mov r0, r2 + 8002972: f000 fa07 bl 8002d84 + break; + 8002976: e003 b.n 8002980 + } + + default: + status = HAL_ERROR; + 8002978: 2301 movs r3, #1 + 800297a: 73fb strb r3, [r7, #15] + break; + 800297c: e000 b.n 8002980 + break; + 800297e: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8002980: 687b ldr r3, [r7, #4] + 8002982: 2201 movs r2, #1 + 8002984: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8002988: 687b ldr r3, [r7, #4] + 800298a: 2200 movs r2, #0 + 800298c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 8002990: 7bfb ldrb r3, [r7, #15] +} + 8002992: 4618 mov r0, r3 + 8002994: 3710 adds r7, #16 + 8002996: 46bd mov sp, r7 + 8002998: bd80 pop {r7, pc} + +0800299a : + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + 800299a: b480 push {r7} + 800299c: b083 sub sp, #12 + 800299e: af00 add r7, sp, #0 + 80029a0: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + 80029a2: bf00 nop + 80029a4: 370c adds r7, #12 + 80029a6: 46bd mov sp, r7 + 80029a8: bc80 pop {r7} + 80029aa: 4770 bx lr + +080029ac : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 80029ac: b480 push {r7} + 80029ae: b083 sub sp, #12 + 80029b0: af00 add r7, sp, #0 + 80029b2: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 80029b4: bf00 nop + 80029b6: 370c adds r7, #12 + 80029b8: 46bd mov sp, r7 + 80029ba: bc80 pop {r7} + 80029bc: 4770 bx lr + +080029be : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 80029be: b480 push {r7} + 80029c0: b083 sub sp, #12 + 80029c2: af00 add r7, sp, #0 + 80029c4: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 80029c6: bf00 nop + 80029c8: 370c adds r7, #12 + 80029ca: 46bd mov sp, r7 + 80029cc: bc80 pop {r7} + 80029ce: 4770 bx lr + +080029d0 : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 80029d0: b480 push {r7} + 80029d2: b083 sub sp, #12 + 80029d4: af00 add r7, sp, #0 + 80029d6: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 80029d8: bf00 nop + 80029da: 370c adds r7, #12 + 80029dc: 46bd mov sp, r7 + 80029de: bc80 pop {r7} + 80029e0: 4770 bx lr + +080029e2 : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 80029e2: b480 push {r7} + 80029e4: b083 sub sp, #12 + 80029e6: af00 add r7, sp, #0 + 80029e8: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 80029ea: bf00 nop + 80029ec: 370c adds r7, #12 + 80029ee: 46bd mov sp, r7 + 80029f0: bc80 pop {r7} + 80029f2: 4770 bx lr + +080029f4 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 80029f4: b480 push {r7} + 80029f6: b085 sub sp, #20 + 80029f8: af00 add r7, sp, #0 + 80029fa: 6078 str r0, [r7, #4] + 80029fc: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 80029fe: 687b ldr r3, [r7, #4] + 8002a00: 681b ldr r3, [r3, #0] + 8002a02: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8002a04: 687b ldr r3, [r7, #4] + 8002a06: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002a0a: d00f beq.n 8002a2c + 8002a0c: 687b ldr r3, [r7, #4] + 8002a0e: 4a2e ldr r2, [pc, #184] @ (8002ac8 ) + 8002a10: 4293 cmp r3, r2 + 8002a12: d00b beq.n 8002a2c + 8002a14: 687b ldr r3, [r7, #4] + 8002a16: 4a2d ldr r2, [pc, #180] @ (8002acc ) + 8002a18: 4293 cmp r3, r2 + 8002a1a: d007 beq.n 8002a2c + 8002a1c: 687b ldr r3, [r7, #4] + 8002a1e: 4a2c ldr r2, [pc, #176] @ (8002ad0 ) + 8002a20: 4293 cmp r3, r2 + 8002a22: d003 beq.n 8002a2c + 8002a24: 687b ldr r3, [r7, #4] + 8002a26: 4a2b ldr r2, [pc, #172] @ (8002ad4 ) + 8002a28: 4293 cmp r3, r2 + 8002a2a: d108 bne.n 8002a3e + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8002a2c: 68fb ldr r3, [r7, #12] + 8002a2e: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002a32: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8002a34: 683b ldr r3, [r7, #0] + 8002a36: 685b ldr r3, [r3, #4] + 8002a38: 68fa ldr r2, [r7, #12] + 8002a3a: 4313 orrs r3, r2 + 8002a3c: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8002a3e: 687b ldr r3, [r7, #4] + 8002a40: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002a44: d017 beq.n 8002a76 + 8002a46: 687b ldr r3, [r7, #4] + 8002a48: 4a1f ldr r2, [pc, #124] @ (8002ac8 ) + 8002a4a: 4293 cmp r3, r2 + 8002a4c: d013 beq.n 8002a76 + 8002a4e: 687b ldr r3, [r7, #4] + 8002a50: 4a1e ldr r2, [pc, #120] @ (8002acc ) + 8002a52: 4293 cmp r3, r2 + 8002a54: d00f beq.n 8002a76 + 8002a56: 687b ldr r3, [r7, #4] + 8002a58: 4a1d ldr r2, [pc, #116] @ (8002ad0 ) + 8002a5a: 4293 cmp r3, r2 + 8002a5c: d00b beq.n 8002a76 + 8002a5e: 687b ldr r3, [r7, #4] + 8002a60: 4a1c ldr r2, [pc, #112] @ (8002ad4 ) + 8002a62: 4293 cmp r3, r2 + 8002a64: d007 beq.n 8002a76 + 8002a66: 687b ldr r3, [r7, #4] + 8002a68: 4a1b ldr r2, [pc, #108] @ (8002ad8 ) + 8002a6a: 4293 cmp r3, r2 + 8002a6c: d003 beq.n 8002a76 + 8002a6e: 687b ldr r3, [r7, #4] + 8002a70: 4a1a ldr r2, [pc, #104] @ (8002adc ) + 8002a72: 4293 cmp r3, r2 + 8002a74: d108 bne.n 8002a88 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8002a76: 68fb ldr r3, [r7, #12] + 8002a78: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002a7c: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8002a7e: 683b ldr r3, [r7, #0] + 8002a80: 68db ldr r3, [r3, #12] + 8002a82: 68fa ldr r2, [r7, #12] + 8002a84: 4313 orrs r3, r2 + 8002a86: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8002a88: 68fb ldr r3, [r7, #12] + 8002a8a: f023 0280 bic.w r2, r3, #128 @ 0x80 + 8002a8e: 683b ldr r3, [r7, #0] + 8002a90: 691b ldr r3, [r3, #16] + 8002a92: 4313 orrs r3, r2 + 8002a94: 60fb str r3, [r7, #12] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8002a96: 683b ldr r3, [r7, #0] + 8002a98: 689a ldr r2, [r3, #8] + 8002a9a: 687b ldr r3, [r7, #4] + 8002a9c: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8002a9e: 683b ldr r3, [r7, #0] + 8002aa0: 681a ldr r2, [r3, #0] + 8002aa2: 687b ldr r3, [r7, #4] + 8002aa4: 629a str r2, [r3, #40] @ 0x28 + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + 8002aa6: 687b ldr r3, [r7, #4] + 8002aa8: 681b ldr r3, [r3, #0] + 8002aaa: f043 0204 orr.w r2, r3, #4 + 8002aae: 687b ldr r3, [r7, #4] + 8002ab0: 601a str r2, [r3, #0] + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8002ab2: 687b ldr r3, [r7, #4] + 8002ab4: 2201 movs r2, #1 + 8002ab6: 615a str r2, [r3, #20] + + TIMx->CR1 = tmpcr1; + 8002ab8: 687b ldr r3, [r7, #4] + 8002aba: 68fa ldr r2, [r7, #12] + 8002abc: 601a str r2, [r3, #0] +} + 8002abe: bf00 nop + 8002ac0: 3714 adds r7, #20 + 8002ac2: 46bd mov sp, r7 + 8002ac4: bc80 pop {r7} + 8002ac6: 4770 bx lr + 8002ac8: 40000400 .word 0x40000400 + 8002acc: 40000800 .word 0x40000800 + 8002ad0: 40000c00 .word 0x40000c00 + 8002ad4: 40010800 .word 0x40010800 + 8002ad8: 40010c00 .word 0x40010c00 + 8002adc: 40011000 .word 0x40011000 + +08002ae0 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002ae0: b480 push {r7} + 8002ae2: b087 sub sp, #28 + 8002ae4: af00 add r7, sp, #0 + 8002ae6: 6078 str r0, [r7, #4] + 8002ae8: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002aea: 687b ldr r3, [r7, #4] + 8002aec: 6a1b ldr r3, [r3, #32] + 8002aee: 617b str r3, [r7, #20] + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002af0: 687b ldr r3, [r7, #4] + 8002af2: 6a1b ldr r3, [r3, #32] + 8002af4: f023 0201 bic.w r2, r3, #1 + 8002af8: 687b ldr r3, [r7, #4] + 8002afa: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002afc: 687b ldr r3, [r7, #4] + 8002afe: 685b ldr r3, [r3, #4] + 8002b00: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002b02: 687b ldr r3, [r7, #4] + 8002b04: 699b ldr r3, [r3, #24] + 8002b06: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 8002b08: 68fb ldr r3, [r7, #12] + 8002b0a: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002b0e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 8002b10: 68fb ldr r3, [r7, #12] + 8002b12: f023 0303 bic.w r3, r3, #3 + 8002b16: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002b18: 683b ldr r3, [r7, #0] + 8002b1a: 681b ldr r3, [r3, #0] + 8002b1c: 68fa ldr r2, [r7, #12] + 8002b1e: 4313 orrs r3, r2 + 8002b20: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 8002b22: 697b ldr r3, [r7, #20] + 8002b24: f023 0302 bic.w r3, r3, #2 + 8002b28: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 8002b2a: 683b ldr r3, [r7, #0] + 8002b2c: 689b ldr r3, [r3, #8] + 8002b2e: 697a ldr r2, [r7, #20] + 8002b30: 4313 orrs r3, r2 + 8002b32: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002b34: 687b ldr r3, [r7, #4] + 8002b36: 693a ldr r2, [r7, #16] + 8002b38: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002b3a: 687b ldr r3, [r7, #4] + 8002b3c: 68fa ldr r2, [r7, #12] + 8002b3e: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 8002b40: 683b ldr r3, [r7, #0] + 8002b42: 685a ldr r2, [r3, #4] + 8002b44: 687b ldr r3, [r7, #4] + 8002b46: 635a str r2, [r3, #52] @ 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002b48: 687b ldr r3, [r7, #4] + 8002b4a: 697a ldr r2, [r7, #20] + 8002b4c: 621a str r2, [r3, #32] +} + 8002b4e: bf00 nop + 8002b50: 371c adds r7, #28 + 8002b52: 46bd mov sp, r7 + 8002b54: bc80 pop {r7} + 8002b56: 4770 bx lr + +08002b58 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002b58: b480 push {r7} + 8002b5a: b087 sub sp, #28 + 8002b5c: af00 add r7, sp, #0 + 8002b5e: 6078 str r0, [r7, #4] + 8002b60: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002b62: 687b ldr r3, [r7, #4] + 8002b64: 6a1b ldr r3, [r3, #32] + 8002b66: 617b str r3, [r7, #20] + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002b68: 687b ldr r3, [r7, #4] + 8002b6a: 6a1b ldr r3, [r3, #32] + 8002b6c: f023 0210 bic.w r2, r3, #16 + 8002b70: 687b ldr r3, [r7, #4] + 8002b72: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002b74: 687b ldr r3, [r7, #4] + 8002b76: 685b ldr r3, [r3, #4] + 8002b78: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002b7a: 687b ldr r3, [r7, #4] + 8002b7c: 699b ldr r3, [r3, #24] + 8002b7e: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8002b80: 68fb ldr r3, [r7, #12] + 8002b82: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002b86: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8002b88: 68fb ldr r3, [r7, #12] + 8002b8a: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002b8e: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002b90: 683b ldr r3, [r7, #0] + 8002b92: 681b ldr r3, [r3, #0] + 8002b94: 021b lsls r3, r3, #8 + 8002b96: 68fa ldr r2, [r7, #12] + 8002b98: 4313 orrs r3, r2 + 8002b9a: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8002b9c: 697b ldr r3, [r7, #20] + 8002b9e: f023 0320 bic.w r3, r3, #32 + 8002ba2: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 8002ba4: 683b ldr r3, [r7, #0] + 8002ba6: 689b ldr r3, [r3, #8] + 8002ba8: 011b lsls r3, r3, #4 + 8002baa: 697a ldr r2, [r7, #20] + 8002bac: 4313 orrs r3, r2 + 8002bae: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002bb0: 687b ldr r3, [r7, #4] + 8002bb2: 693a ldr r2, [r7, #16] + 8002bb4: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002bb6: 687b ldr r3, [r7, #4] + 8002bb8: 68fa ldr r2, [r7, #12] + 8002bba: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8002bbc: 683b ldr r3, [r7, #0] + 8002bbe: 685a ldr r2, [r3, #4] + 8002bc0: 687b ldr r3, [r7, #4] + 8002bc2: 639a str r2, [r3, #56] @ 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002bc4: 687b ldr r3, [r7, #4] + 8002bc6: 697a ldr r2, [r7, #20] + 8002bc8: 621a str r2, [r3, #32] +} + 8002bca: bf00 nop + 8002bcc: 371c adds r7, #28 + 8002bce: 46bd mov sp, r7 + 8002bd0: bc80 pop {r7} + 8002bd2: 4770 bx lr + +08002bd4 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002bd4: b480 push {r7} + 8002bd6: b087 sub sp, #28 + 8002bd8: af00 add r7, sp, #0 + 8002bda: 6078 str r0, [r7, #4] + 8002bdc: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002bde: 687b ldr r3, [r7, #4] + 8002be0: 6a1b ldr r3, [r3, #32] + 8002be2: 617b str r3, [r7, #20] + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8002be4: 687b ldr r3, [r7, #4] + 8002be6: 6a1b ldr r3, [r3, #32] + 8002be8: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8002bec: 687b ldr r3, [r7, #4] + 8002bee: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002bf0: 687b ldr r3, [r7, #4] + 8002bf2: 685b ldr r3, [r3, #4] + 8002bf4: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002bf6: 687b ldr r3, [r7, #4] + 8002bf8: 69db ldr r3, [r3, #28] + 8002bfa: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8002bfc: 68fb ldr r3, [r7, #12] + 8002bfe: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002c02: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8002c04: 68fb ldr r3, [r7, #12] + 8002c06: f023 0303 bic.w r3, r3, #3 + 8002c0a: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002c0c: 683b ldr r3, [r7, #0] + 8002c0e: 681b ldr r3, [r3, #0] + 8002c10: 68fa ldr r2, [r7, #12] + 8002c12: 4313 orrs r3, r2 + 8002c14: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8002c16: 697b ldr r3, [r7, #20] + 8002c18: f423 7300 bic.w r3, r3, #512 @ 0x200 + 8002c1c: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 8002c1e: 683b ldr r3, [r7, #0] + 8002c20: 689b ldr r3, [r3, #8] + 8002c22: 021b lsls r3, r3, #8 + 8002c24: 697a ldr r2, [r7, #20] + 8002c26: 4313 orrs r3, r2 + 8002c28: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002c2a: 687b ldr r3, [r7, #4] + 8002c2c: 693a ldr r2, [r7, #16] + 8002c2e: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002c30: 687b ldr r3, [r7, #4] + 8002c32: 68fa ldr r2, [r7, #12] + 8002c34: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 8002c36: 683b ldr r3, [r7, #0] + 8002c38: 685a ldr r2, [r3, #4] + 8002c3a: 687b ldr r3, [r7, #4] + 8002c3c: 63da str r2, [r3, #60] @ 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002c3e: 687b ldr r3, [r7, #4] + 8002c40: 697a ldr r2, [r7, #20] + 8002c42: 621a str r2, [r3, #32] +} + 8002c44: bf00 nop + 8002c46: 371c adds r7, #28 + 8002c48: 46bd mov sp, r7 + 8002c4a: bc80 pop {r7} + 8002c4c: 4770 bx lr + +08002c4e : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002c4e: b480 push {r7} + 8002c50: b087 sub sp, #28 + 8002c52: af00 add r7, sp, #0 + 8002c54: 6078 str r0, [r7, #4] + 8002c56: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002c58: 687b ldr r3, [r7, #4] + 8002c5a: 6a1b ldr r3, [r3, #32] + 8002c5c: 617b str r3, [r7, #20] + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8002c5e: 687b ldr r3, [r7, #4] + 8002c60: 6a1b ldr r3, [r3, #32] + 8002c62: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8002c66: 687b ldr r3, [r7, #4] + 8002c68: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002c6a: 687b ldr r3, [r7, #4] + 8002c6c: 685b ldr r3, [r3, #4] + 8002c6e: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002c70: 687b ldr r3, [r7, #4] + 8002c72: 69db ldr r3, [r3, #28] + 8002c74: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8002c76: 68fb ldr r3, [r7, #12] + 8002c78: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002c7c: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8002c7e: 68fb ldr r3, [r7, #12] + 8002c80: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002c84: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002c86: 683b ldr r3, [r7, #0] + 8002c88: 681b ldr r3, [r3, #0] + 8002c8a: 021b lsls r3, r3, #8 + 8002c8c: 68fa ldr r2, [r7, #12] + 8002c8e: 4313 orrs r3, r2 + 8002c90: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8002c92: 697b ldr r3, [r7, #20] + 8002c94: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 8002c98: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8002c9a: 683b ldr r3, [r7, #0] + 8002c9c: 689b ldr r3, [r3, #8] + 8002c9e: 031b lsls r3, r3, #12 + 8002ca0: 697a ldr r2, [r7, #20] + 8002ca2: 4313 orrs r3, r2 + 8002ca4: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002ca6: 687b ldr r3, [r7, #4] + 8002ca8: 693a ldr r2, [r7, #16] + 8002caa: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002cac: 687b ldr r3, [r7, #4] + 8002cae: 68fa ldr r2, [r7, #12] + 8002cb0: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 8002cb2: 683b ldr r3, [r7, #0] + 8002cb4: 685a ldr r2, [r3, #4] + 8002cb6: 687b ldr r3, [r7, #4] + 8002cb8: 641a str r2, [r3, #64] @ 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002cba: 687b ldr r3, [r7, #4] + 8002cbc: 697a ldr r2, [r7, #20] + 8002cbe: 621a str r2, [r3, #32] +} + 8002cc0: bf00 nop + 8002cc2: 371c adds r7, #28 + 8002cc4: 46bd mov sp, r7 + 8002cc6: bc80 pop {r7} + 8002cc8: 4770 bx lr + +08002cca : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002cca: b480 push {r7} + 8002ccc: b087 sub sp, #28 + 8002cce: af00 add r7, sp, #0 + 8002cd0: 60f8 str r0, [r7, #12] + 8002cd2: 60b9 str r1, [r7, #8] + 8002cd4: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8002cd6: 68fb ldr r3, [r7, #12] + 8002cd8: 6a1b ldr r3, [r3, #32] + 8002cda: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002cdc: 68fb ldr r3, [r7, #12] + 8002cde: 6a1b ldr r3, [r3, #32] + 8002ce0: f023 0201 bic.w r2, r3, #1 + 8002ce4: 68fb ldr r3, [r7, #12] + 8002ce6: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8002ce8: 68fb ldr r3, [r7, #12] + 8002cea: 699b ldr r3, [r3, #24] + 8002cec: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8002cee: 693b ldr r3, [r7, #16] + 8002cf0: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8002cf4: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8002cf6: 687b ldr r3, [r7, #4] + 8002cf8: 011b lsls r3, r3, #4 + 8002cfa: 693a ldr r2, [r7, #16] + 8002cfc: 4313 orrs r3, r2 + 8002cfe: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 8002d00: 697b ldr r3, [r7, #20] + 8002d02: f023 030a bic.w r3, r3, #10 + 8002d06: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8002d08: 697a ldr r2, [r7, #20] + 8002d0a: 68bb ldr r3, [r7, #8] + 8002d0c: 4313 orrs r3, r2 + 8002d0e: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 8002d10: 68fb ldr r3, [r7, #12] + 8002d12: 693a ldr r2, [r7, #16] + 8002d14: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8002d16: 68fb ldr r3, [r7, #12] + 8002d18: 697a ldr r2, [r7, #20] + 8002d1a: 621a str r2, [r3, #32] +} + 8002d1c: bf00 nop + 8002d1e: 371c adds r7, #28 + 8002d20: 46bd mov sp, r7 + 8002d22: bc80 pop {r7} + 8002d24: 4770 bx lr + +08002d26 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002d26: b480 push {r7} + 8002d28: b087 sub sp, #28 + 8002d2a: af00 add r7, sp, #0 + 8002d2c: 60f8 str r0, [r7, #12] + 8002d2e: 60b9 str r1, [r7, #8] + 8002d30: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + 8002d32: 68fb ldr r3, [r7, #12] + 8002d34: 6a1b ldr r3, [r3, #32] + 8002d36: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002d38: 68fb ldr r3, [r7, #12] + 8002d3a: 6a1b ldr r3, [r3, #32] + 8002d3c: f023 0210 bic.w r2, r3, #16 + 8002d40: 68fb ldr r3, [r7, #12] + 8002d42: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8002d44: 68fb ldr r3, [r7, #12] + 8002d46: 699b ldr r3, [r3, #24] + 8002d48: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8002d4a: 693b ldr r3, [r7, #16] + 8002d4c: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 8002d50: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 12U); + 8002d52: 687b ldr r3, [r7, #4] + 8002d54: 031b lsls r3, r3, #12 + 8002d56: 693a ldr r2, [r7, #16] + 8002d58: 4313 orrs r3, r2 + 8002d5a: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8002d5c: 697b ldr r3, [r7, #20] + 8002d5e: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 8002d62: 617b str r3, [r7, #20] + tmpccer |= (TIM_ICPolarity << 4U); + 8002d64: 68bb ldr r3, [r7, #8] + 8002d66: 011b lsls r3, r3, #4 + 8002d68: 697a ldr r2, [r7, #20] + 8002d6a: 4313 orrs r3, r2 + 8002d6c: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 8002d6e: 68fb ldr r3, [r7, #12] + 8002d70: 693a ldr r2, [r7, #16] + 8002d72: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8002d74: 68fb ldr r3, [r7, #12] + 8002d76: 697a ldr r2, [r7, #20] + 8002d78: 621a str r2, [r3, #32] +} + 8002d7a: bf00 nop + 8002d7c: 371c adds r7, #28 + 8002d7e: 46bd mov sp, r7 + 8002d80: bc80 pop {r7} + 8002d82: 4770 bx lr + +08002d84 : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 8002d84: b480 push {r7} + 8002d86: b085 sub sp, #20 + 8002d88: af00 add r7, sp, #0 + 8002d8a: 6078 str r0, [r7, #4] + 8002d8c: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8002d8e: 687b ldr r3, [r7, #4] + 8002d90: 689b ldr r3, [r3, #8] + 8002d92: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8002d94: 68fb ldr r3, [r7, #12] + 8002d96: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002d9a: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8002d9c: 683a ldr r2, [r7, #0] + 8002d9e: 68fb ldr r3, [r7, #12] + 8002da0: 4313 orrs r3, r2 + 8002da2: f043 0307 orr.w r3, r3, #7 + 8002da6: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8002da8: 687b ldr r3, [r7, #4] + 8002daa: 68fa ldr r2, [r7, #12] + 8002dac: 609a str r2, [r3, #8] +} + 8002dae: bf00 nop + 8002db0: 3714 adds r7, #20 + 8002db2: 46bd mov sp, r7 + 8002db4: bc80 pop {r7} + 8002db6: 4770 bx lr + +08002db8 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8002db8: b480 push {r7} + 8002dba: b087 sub sp, #28 + 8002dbc: af00 add r7, sp, #0 + 8002dbe: 60f8 str r0, [r7, #12] + 8002dc0: 60b9 str r1, [r7, #8] + 8002dc2: 607a str r2, [r7, #4] + 8002dc4: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 8002dc6: 68fb ldr r3, [r7, #12] + 8002dc8: 689b ldr r3, [r3, #8] + 8002dca: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8002dcc: 697b ldr r3, [r7, #20] + 8002dce: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 8002dd2: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8002dd4: 683b ldr r3, [r7, #0] + 8002dd6: 021a lsls r2, r3, #8 + 8002dd8: 687b ldr r3, [r7, #4] + 8002dda: 431a orrs r2, r3 + 8002ddc: 68bb ldr r3, [r7, #8] + 8002dde: 4313 orrs r3, r2 + 8002de0: 697a ldr r2, [r7, #20] + 8002de2: 4313 orrs r3, r2 + 8002de4: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8002de6: 68fb ldr r3, [r7, #12] + 8002de8: 697a ldr r2, [r7, #20] + 8002dea: 609a str r2, [r3, #8] +} + 8002dec: bf00 nop + 8002dee: 371c adds r7, #28 + 8002df0: 46bd mov sp, r7 + 8002df2: bc80 pop {r7} + 8002df4: 4770 bx lr + +08002df6 : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 8002df6: b480 push {r7} + 8002df8: b087 sub sp, #28 + 8002dfa: af00 add r7, sp, #0 + 8002dfc: 60f8 str r0, [r7, #12] + 8002dfe: 60b9 str r1, [r7, #8] + 8002e00: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 8002e02: 68bb ldr r3, [r7, #8] + 8002e04: f003 031f and.w r3, r3, #31 + 8002e08: 2201 movs r2, #1 + 8002e0a: fa02 f303 lsl.w r3, r2, r3 + 8002e0e: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 8002e10: 68fb ldr r3, [r7, #12] + 8002e12: 6a1a ldr r2, [r3, #32] + 8002e14: 697b ldr r3, [r7, #20] + 8002e16: 43db mvns r3, r3 + 8002e18: 401a ands r2, r3 + 8002e1a: 68fb ldr r3, [r7, #12] + 8002e1c: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8002e1e: 68fb ldr r3, [r7, #12] + 8002e20: 6a1a ldr r2, [r3, #32] + 8002e22: 68bb ldr r3, [r7, #8] + 8002e24: f003 031f and.w r3, r3, #31 + 8002e28: 6879 ldr r1, [r7, #4] + 8002e2a: fa01 f303 lsl.w r3, r1, r3 + 8002e2e: 431a orrs r2, r3 + 8002e30: 68fb ldr r3, [r7, #12] + 8002e32: 621a str r2, [r3, #32] +} + 8002e34: bf00 nop + 8002e36: 371c adds r7, #28 + 8002e38: 46bd mov sp, r7 + 8002e3a: bc80 pop {r7} + 8002e3c: 4770 bx lr + ... + +08002e40 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8002e40: b480 push {r7} + 8002e42: b085 sub sp, #20 + 8002e44: af00 add r7, sp, #0 + 8002e46: 6078 str r0, [r7, #4] + 8002e48: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 8002e4a: 687b ldr r3, [r7, #4] + 8002e4c: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 8002e50: 2b01 cmp r3, #1 + 8002e52: d101 bne.n 8002e58 + 8002e54: 2302 movs r3, #2 + 8002e56: e046 b.n 8002ee6 + 8002e58: 687b ldr r3, [r7, #4] + 8002e5a: 2201 movs r2, #1 + 8002e5c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002e60: 687b ldr r3, [r7, #4] + 8002e62: 2202 movs r2, #2 + 8002e64: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8002e68: 687b ldr r3, [r7, #4] + 8002e6a: 681b ldr r3, [r3, #0] + 8002e6c: 685b ldr r3, [r3, #4] + 8002e6e: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8002e70: 687b ldr r3, [r7, #4] + 8002e72: 681b ldr r3, [r3, #0] + 8002e74: 689b ldr r3, [r3, #8] + 8002e76: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8002e78: 68fb ldr r3, [r7, #12] + 8002e7a: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002e7e: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8002e80: 683b ldr r3, [r7, #0] + 8002e82: 681b ldr r3, [r3, #0] + 8002e84: 68fa ldr r2, [r7, #12] + 8002e86: 4313 orrs r3, r2 + 8002e88: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8002e8a: 687b ldr r3, [r7, #4] + 8002e8c: 681b ldr r3, [r3, #0] + 8002e8e: 68fa ldr r2, [r7, #12] + 8002e90: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8002e92: 687b ldr r3, [r7, #4] + 8002e94: 681b ldr r3, [r3, #0] + 8002e96: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002e9a: d00e beq.n 8002eba + 8002e9c: 687b ldr r3, [r7, #4] + 8002e9e: 681b ldr r3, [r3, #0] + 8002ea0: 4a13 ldr r2, [pc, #76] @ (8002ef0 ) + 8002ea2: 4293 cmp r3, r2 + 8002ea4: d009 beq.n 8002eba + 8002ea6: 687b ldr r3, [r7, #4] + 8002ea8: 681b ldr r3, [r3, #0] + 8002eaa: 4a12 ldr r2, [pc, #72] @ (8002ef4 ) + 8002eac: 4293 cmp r3, r2 + 8002eae: d004 beq.n 8002eba + 8002eb0: 687b ldr r3, [r7, #4] + 8002eb2: 681b ldr r3, [r3, #0] + 8002eb4: 4a10 ldr r2, [pc, #64] @ (8002ef8 ) + 8002eb6: 4293 cmp r3, r2 + 8002eb8: d10c bne.n 8002ed4 + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8002eba: 68bb ldr r3, [r7, #8] + 8002ebc: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8002ec0: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8002ec2: 683b ldr r3, [r7, #0] + 8002ec4: 685b ldr r3, [r3, #4] + 8002ec6: 68ba ldr r2, [r7, #8] + 8002ec8: 4313 orrs r3, r2 + 8002eca: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8002ecc: 687b ldr r3, [r7, #4] + 8002ece: 681b ldr r3, [r3, #0] + 8002ed0: 68ba ldr r2, [r7, #8] + 8002ed2: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8002ed4: 687b ldr r3, [r7, #4] + 8002ed6: 2201 movs r2, #1 + 8002ed8: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8002edc: 687b ldr r3, [r7, #4] + 8002ede: 2200 movs r2, #0 + 8002ee0: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return HAL_OK; + 8002ee4: 2300 movs r3, #0 +} + 8002ee6: 4618 mov r0, r3 + 8002ee8: 3714 adds r7, #20 + 8002eea: 46bd mov sp, r7 + 8002eec: bc80 pop {r7} + 8002eee: 4770 bx lr + 8002ef0: 40000400 .word 0x40000400 + 8002ef4: 40000800 .word 0x40000800 + 8002ef8: 40010800 .word 0x40010800 + +08002efc : + 8002efc: 4603 mov r3, r0 + 8002efe: 4402 add r2, r0 + 8002f00: 4293 cmp r3, r2 + 8002f02: d100 bne.n 8002f06 + 8002f04: 4770 bx lr + 8002f06: f803 1b01 strb.w r1, [r3], #1 + 8002f0a: e7f9 b.n 8002f00 + +08002f0c <__libc_init_array>: + 8002f0c: b570 push {r4, r5, r6, lr} + 8002f0e: 2600 movs r6, #0 + 8002f10: 4d0c ldr r5, [pc, #48] @ (8002f44 <__libc_init_array+0x38>) + 8002f12: 4c0d ldr r4, [pc, #52] @ (8002f48 <__libc_init_array+0x3c>) + 8002f14: 1b64 subs r4, r4, r5 + 8002f16: 10a4 asrs r4, r4, #2 + 8002f18: 42a6 cmp r6, r4 + 8002f1a: d109 bne.n 8002f30 <__libc_init_array+0x24> + 8002f1c: f000 f81a bl 8002f54 <_init> + 8002f20: 2600 movs r6, #0 + 8002f22: 4d0a ldr r5, [pc, #40] @ (8002f4c <__libc_init_array+0x40>) + 8002f24: 4c0a ldr r4, [pc, #40] @ (8002f50 <__libc_init_array+0x44>) + 8002f26: 1b64 subs r4, r4, r5 + 8002f28: 10a4 asrs r4, r4, #2 + 8002f2a: 42a6 cmp r6, r4 + 8002f2c: d105 bne.n 8002f3a <__libc_init_array+0x2e> + 8002f2e: bd70 pop {r4, r5, r6, pc} + 8002f30: f855 3b04 ldr.w r3, [r5], #4 + 8002f34: 4798 blx r3 + 8002f36: 3601 adds r6, #1 + 8002f38: e7ee b.n 8002f18 <__libc_init_array+0xc> + 8002f3a: f855 3b04 ldr.w r3, [r5], #4 + 8002f3e: 4798 blx r3 + 8002f40: 3601 adds r6, #1 + 8002f42: e7f2 b.n 8002f2a <__libc_init_array+0x1e> + 8002f44: 08002f90 .word 0x08002f90 + 8002f48: 08002f90 .word 0x08002f90 + 8002f4c: 08002f90 .word 0x08002f90 + 8002f50: 08002f94 .word 0x08002f94 + +08002f54 <_init>: + 8002f54: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002f56: bf00 nop + 8002f58: bcf8 pop {r3, r4, r5, r6, r7} + 8002f5a: bc08 pop {r3} + 8002f5c: 469e mov lr, r3 + 8002f5e: 4770 bx lr + +08002f60 <_fini>: + 8002f60: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002f62: bf00 nop + 8002f64: bcf8 pop {r3, r4, r5, r6, r7} + 8002f66: bc08 pop {r3} + 8002f68: 469e mov lr, r3 + 8002f6a: 4770 bx lr diff --git a/TP4_INIT_TFT/Debug/TP3_PWM_GENERATOR.map b/TP4_INIT_TFT/Debug/TP3_PWM_GENERATOR.map new file mode 100644 index 0000000..dc6feb1 --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP3_PWM_GENERATOR.map @@ -0,0 +1,3419 @@ +Archive member included to satisfy reference by file (symbol) + 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(RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0x13c + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x13c ./Core/Startup/startup_stm32l152retx.o + 0x08000000 g_pfnVectors + 0x0800013c . = ALIGN (0x4) + +.text 0x0800013c 0x2e30 + 0x0800013c . = ALIGN (0x4) + *(.text) + .text 0x0800013c 0x40 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + .text 0x0800017c 0x30 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x0800017c __aeabi_uldivmod + .text 0x080001ac 0x300 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0xc ./Core/Src/stm32l1xx_it.o + 0x08000a10 SVC_Handler + .text.DebugMon_Handler + 0x08000a1c 0xc ./Core/Src/stm32l1xx_it.o + 0x08000a1c DebugMon_Handler + .text.PendSV_Handler + 0x08000a28 0xc ./Core/Src/stm32l1xx_it.o + 0x08000a28 PendSV_Handler + .text.SysTick_Handler + 0x08000a34 0xc ./Core/Src/stm32l1xx_it.o + 0x08000a34 SysTick_Handler + .text.TIM2_IRQHandler + 0x08000a40 0x14 ./Core/Src/stm32l1xx_it.o + 0x08000a40 TIM2_IRQHandler + .text.TIM3_IRQHandler + 0x08000a54 0x14 ./Core/Src/stm32l1xx_it.o + 0x08000a54 TIM3_IRQHandler + .text.EXTI15_10_IRQHandler + 0x08000a68 0x18 ./Core/Src/stm32l1xx_it.o + 0x08000a68 EXTI15_10_IRQHandler + .text.SystemInit + 0x08000a80 0xc ./Core/Src/system_stm32l1xx.o + 0x08000a80 SystemInit + .text.Reset_Handler + 0x08000a8c 0x48 ./Core/Startup/startup_stm32l152retx.o + 0x08000a8c Reset_Handler + .text.Default_Handler + 0x08000ad4 0x2 ./Core/Startup/startup_stm32l152retx.o + 0x08000ad4 DMA2_Channel3_IRQHandler + 0x08000ad4 EXTI2_IRQHandler + 0x08000ad4 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0x08000eae HAL_SYSTICK_Config + *fill* 0x08000ec6 0x2 + .text.HAL_GPIO_Init + 0x08000ec8 0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000ec8 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x080011e8 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x080011e8 HAL_GPIO_WritePin + .text.HAL_GPIO_EXTI_IRQHandler + 0x08001218 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08001218 HAL_GPIO_EXTI_IRQHandler + .text.HAL_GPIO_EXTI_Callback + 0x08001248 0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08001248 HAL_GPIO_EXTI_Callback + .text.HAL_RCC_OscConfig + 0x0800125c 0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0800125c HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x080018bc 0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x080018bc HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x08001b24 0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08001b24 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./Drivers/7Seg_MAX7219/max7219.o + .debug_rnglists + 0x0000014b 0xa3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_rnglists + 0x000001ee 0xd9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_rnglists + 0x000002c7 0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_rnglists + 0x00000306 0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_rnglists + 0x00000373 0x16f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_rnglists + 0x000004e2 0x307 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_rnglists + 0x000007e9 0x1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_macro 0x00000000 0x155f9 + .debug_macro 0x00000000 0x1c2 ./Core/Src/main.o + .debug_macro 0x000001c2 0xacc ./Core/Src/main.o + .debug_macro 0x00000c8e 0x10f ./Core/Src/main.o + .debug_macro 0x00000d9d 0x2e ./Core/Src/main.o + .debug_macro 0x00000dcb 0x22 ./Core/Src/main.o + .debug_macro 0x00000ded 0x22 ./Core/Src/main.o + .debug_macro 0x00000e0f 0x8e ./Core/Src/main.o + .debug_macro 0x00000e9d 0x51 ./Core/Src/main.o + .debug_macro 0x00000eee 0x103 ./Core/Src/main.o + .debug_macro 0x00000ff1 0x6a ./Core/Src/main.o + .debug_macro 0x0000105b 0x1df ./Core/Src/main.o + .debug_macro 0x0000123a 0x1c ./Core/Src/main.o + .debug_macro 0x00001256 0x22 ./Core/Src/main.o + .debug_macro 0x00001278 0xbd ./Core/Src/main.o + .debug_macro 0x00001335 0xe49 ./Core/Src/main.o + .debug_macro 0x0000217e 0x11f ./Core/Src/main.o + .debug_macro 0x0000229d 0xb7a1 ./Core/Src/main.o + .debug_macro 0x0000da3e 0x6d ./Core/Src/main.o + .debug_macro 0x0000daab 0x34e1 ./Core/Src/main.o + .debug_macro 0x00010f8c 0x190 ./Core/Src/main.o + .debug_macro 0x0001111c 0x5b ./Core/Src/main.o + .debug_macro 0x00011177 0xe37 ./Core/Src/main.o + .debug_macro 0x00011fae 0x35b ./Core/Src/main.o + .debug_macro 0x00012309 0x1b8 ./Core/Src/main.o + .debug_macro 0x000124c1 0xc5 ./Core/Src/main.o + .debug_macro 0x00012586 0x21e ./Core/Src/main.o + .debug_macro 0x000127a4 0x236 ./Core/Src/main.o + .debug_macro 0x000129da 0x115 ./Core/Src/main.o + .debug_macro 0x00012aef 0x567 ./Core/Src/main.o + .debug_macro 0x00013056 0x1e9 ./Core/Src/main.o + .debug_macro 0x0001323f 0x22 ./Core/Src/main.o + .debug_macro 0x00013261 0x225 ./Core/Src/main.o + .debug_macro 0x00013486 0x788 ./Core/Src/main.o + .debug_macro 0x00013c0e 0xac ./Core/Src/main.o + .debug_macro 0x00013cba 0x170 ./Core/Src/main.o + .debug_macro 0x00013e2a 0x492 ./Core/Src/main.o + .debug_macro 0x000142bc 0x10 ./Core/Src/main.o + .debug_macro 0x000142cc 0x1b9 ./Core/Src/stm32l1xx_hal_msp.o + .debug_macro 0x00014485 0x1c3 ./Core/Src/stm32l1xx_it.o + .debug_macro 0x00014648 0x1af ./Core/Src/system_stm32l1xx.o + .debug_macro 0x000147f7 0x1ec ./Drivers/7Seg_MAX7219/max7219.o + .debug_macro 0x000149e3 0x1d3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_macro 0x00014bb6 0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_macro 0x00014d65 0x1b6 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_macro 0x00014f1b 0x1c1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_macro 0x000150dc 0x1be ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_macro 0x0001529a 0x1b0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_macro 0x0001544a 0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_line 0x00000000 0xaa50 + .debug_line 0x00000000 0x8b8 ./Core/Src/main.o + .debug_line 0x000008b8 0x79c ./Core/Src/stm32l1xx_hal_msp.o + .debug_line 0x00001054 0x7b8 ./Core/Src/stm32l1xx_it.o + .debug_line 0x0000180c 0x761 ./Core/Src/system_stm32l1xx.o + .debug_line 0x00001f6d 0x79 ./Core/Startup/startup_stm32l152retx.o + .debug_line 0x00001fe6 0x80f ./Drivers/7Seg_MAX7219/max7219.o + .debug_line 0x000027f5 0x98c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_line 0x00003181 0xc5b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_line 0x00003ddc 0x9d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_line 0x000047ac 0xf4f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_line 0x000056fb 0x1c4b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_line 0x00007346 0x2fb1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_line 0x0000a2f7 0x759 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_str 0x00000000 0x88675 + .debug_str 0x00000000 0x88675 ./Core/Src/main.o + 0x86772 (size before relaxing) + .debug_str 0x00088675 0x863e3 ./Core/Src/stm32l1xx_hal_msp.o + .debug_str 0x00088675 0x85df1 ./Core/Src/stm32l1xx_it.o + .debug_str 0x00088675 0x85908 ./Core/Src/system_stm32l1xx.o + .debug_str 0x00088675 0x8c ./Core/Startup/startup_stm32l152retx.o + .debug_str 0x00088675 0x85e64 ./Drivers/7Seg_MAX7219/max7219.o + .debug_str 0x00088675 0x86030 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_str 0x00088675 0x8613c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_str 0x00088675 0x85a9b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_str 0x00088675 0x85dc4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_str 0x00088675 0x8622a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_str 0x00088675 0x86c0b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_str 0x00088675 0x85db0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Core/Src/main.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_hal_msp.o + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_it.o + .comment 0x00000043 0x44 ./Core/Src/system_stm32l1xx.o + .comment 0x00000043 0x44 ./Drivers/7Seg_MAX7219/max7219.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_frame 0x00000000 0x2ba0 + .debug_frame 0x00000000 0xf0 ./Core/Src/main.o + .debug_frame 0x000000f0 0xec ./Core/Src/stm32l1xx_hal_msp.o + .debug_frame 0x000001dc 0x158 ./Core/Src/stm32l1xx_it.o + .debug_frame 0x00000334 0x58 ./Core/Src/system_stm32l1xx.o + .debug_frame 0x0000038c 0x198 ./Drivers/7Seg_MAX7219/max7219.o + .debug_frame 0x00000524 0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_frame 0x00000860 0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_frame 0x00000d48 0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_frame 0x00000e94 0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_frame 0x000010b8 0x828 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_frame 0x000018e0 0x11b4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_frame 0x00002a94 0x60 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + .debug_frame 0x00002af4 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00002b14 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .debug_frame 0x00002b40 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00002b6c 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x70 + .debug_line_str + 0x00000000 0x70 ./Core/Startup/startup_stm32l152retx.o diff --git a/TP4_INIT_TFT/Debug/TP3_PWM_LED.list b/TP4_INIT_TFT/Debug/TP3_PWM_LED.list new file mode 100644 index 0000000..6c31734 --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP3_PWM_LED.list @@ -0,0 +1,8719 @@ + +TP3_PWM_LED.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000030ec 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000001c 08003228 08003228 00004228 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08003244 08003244 00005010 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08003244 08003244 00004244 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800324c 0800324c 00005010 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800324c 0800324c 0000424c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 08003250 08003250 00004250 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 00000010 20000000 08003254 00005000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 0000013c 20000010 08003264 00005010 2**2 + ALLOC + 10 ._user_heap_stack 00000604 2000014c 08003264 0000514c 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 00005010 2**0 + CONTENTS, READONLY + 12 .debug_info 0000998e 00000000 00000000 00005039 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 000019f6 00000000 00000000 0000e9c7 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000ab0 00000000 00000000 000103c0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 0000081f 00000000 00000000 00010e70 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000155f9 00000000 00000000 0001168f 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0000ab8c 00000000 00000000 00026c88 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 000886ff 00000000 00000000 00031814 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000b9f13 2**0 + CONTENTS, READONLY + 20 .debug_frame 00002c2c 00000000 00000000 000b9f58 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000bcb84 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 20000010 .word 0x20000010 + 8000158: 00000000 .word 0x00000000 + 800015c: 08003210 .word 0x08003210 + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000014 .word 0x20000014 + 8000178: 08003210 .word 0x08003210 + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80004b0: b580 push {r7, lr} + 80004b2: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80004b4: f000 fca0 bl 8000df8 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80004b8: f000 f822 bl 8000500 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80004bc: f000 f9be bl 800083c + MX_SPI1_Init(); + 80004c0: f000 f864 bl 800058c + MX_TIM4_Init(); + 80004c4: f000 f8e6 bl 8000694 + MX_TIM11_Init(); + 80004c8: f000 f958 bl 800077c + MX_TIM2_Init(); + 80004cc: f000 f894 bl 80005f8 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 80004d0: f000 fc15 bl 8000cfe + HAL_TIM_Base_Start_IT(&htim2); + 80004d4: 4807 ldr r0, [pc, #28] @ (80004f4 ) + 80004d6: f002 f841 bl 800255c + HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_2); + 80004da: 2104 movs r1, #4 + 80004dc: 4806 ldr r0, [pc, #24] @ (80004f8 ) + 80004de: f002 f8d7 bl 8002690 + HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); + 80004e2: 2100 movs r1, #0 + 80004e4: 4805 ldr r0, [pc, #20] @ (80004fc ) + 80004e6: f002 f8d3 bl 8002690 + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 80004ea: f000 fc3f bl 8000d6c + while (1) + 80004ee: bf00 nop + 80004f0: e7fd b.n 80004ee + 80004f2: bf00 nop + 80004f4: 20000084 .word 0x20000084 + 80004f8: 200000c4 .word 0x200000c4 + 80004fc: 20000104 .word 0x20000104 + +08000500 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000500: b580 push {r7, lr} + 8000502: b092 sub sp, #72 @ 0x48 + 8000504: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000506: f107 0314 add.w r3, r7, #20 + 800050a: 2234 movs r2, #52 @ 0x34 + 800050c: 2100 movs r1, #0 + 800050e: 4618 mov r0, r3 + 8000510: f002 fe52 bl 80031b8 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000514: 463b mov r3, r7 + 8000516: 2200 movs r2, #0 + 8000518: 601a str r2, [r3, #0] + 800051a: 605a str r2, [r3, #4] + 800051c: 609a str r2, [r3, #8] + 800051e: 60da str r2, [r3, #12] + 8000520: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000522: 4b19 ldr r3, [pc, #100] @ (8000588 ) + 8000524: 681b ldr r3, [r3, #0] + 8000526: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 800052a: 4a17 ldr r2, [pc, #92] @ (8000588 ) + 800052c: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000530: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000532: 2302 movs r3, #2 + 8000534: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000536: 2301 movs r3, #1 + 8000538: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 800053a: 2310 movs r3, #16 + 800053c: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 800053e: 2300 movs r3, #0 + 8000540: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000542: f107 0314 add.w r3, r7, #20 + 8000546: 4618 mov r0, r3 + 8000548: f000 ff9c bl 8001484 + 800054c: 4603 mov r3, r0 + 800054e: 2b00 cmp r3, #0 + 8000550: d001 beq.n 8000556 + { + Error_Handler(); + 8000552: f000 fa23 bl 800099c + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000556: 230f movs r3, #15 + 8000558: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 800055a: 2301 movs r3, #1 + 800055c: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 800055e: 2300 movs r3, #0 + 8000560: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000562: 2300 movs r3, #0 + 8000564: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000566: 2300 movs r3, #0 + 8000568: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 800056a: 463b mov r3, r7 + 800056c: 2100 movs r1, #0 + 800056e: 4618 mov r0, r3 + 8000570: f001 fab8 bl 8001ae4 + 8000574: 4603 mov r3, r0 + 8000576: 2b00 cmp r3, #0 + 8000578: d001 beq.n 800057e + { + Error_Handler(); + 800057a: f000 fa0f bl 800099c + } +} + 800057e: bf00 nop + 8000580: 3748 adds r7, #72 @ 0x48 + 8000582: 46bd mov sp, r7 + 8000584: bd80 pop {r7, pc} + 8000586: bf00 nop + 8000588: 40007000 .word 0x40007000 + +0800058c : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 800058c: b580 push {r7, lr} + 800058e: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 8000590: 4b17 ldr r3, [pc, #92] @ (80005f0 ) + 8000592: 4a18 ldr r2, [pc, #96] @ (80005f4 ) + 8000594: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 8000596: 4b16 ldr r3, [pc, #88] @ (80005f0 ) + 8000598: f44f 7282 mov.w r2, #260 @ 0x104 + 800059c: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 800059e: 4b14 ldr r3, [pc, #80] @ (80005f0 ) + 80005a0: 2200 movs r2, #0 + 80005a2: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 80005a4: 4b12 ldr r3, [pc, #72] @ (80005f0 ) + 80005a6: 2200 movs r2, #0 + 80005a8: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 80005aa: 4b11 ldr r3, [pc, #68] @ (80005f0 ) + 80005ac: 2200 movs r2, #0 + 80005ae: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 80005b0: 4b0f ldr r3, [pc, #60] @ (80005f0 ) + 80005b2: 2200 movs r2, #0 + 80005b4: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 80005b6: 4b0e ldr r3, [pc, #56] @ (80005f0 ) + 80005b8: f44f 7200 mov.w r2, #512 @ 0x200 + 80005bc: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 80005be: 4b0c ldr r3, [pc, #48] @ (80005f0 ) + 80005c0: 2200 movs r2, #0 + 80005c2: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 80005c4: 4b0a ldr r3, [pc, #40] @ (80005f0 ) + 80005c6: 2200 movs r2, #0 + 80005c8: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 80005ca: 4b09 ldr r3, [pc, #36] @ (80005f0 ) + 80005cc: 2200 movs r2, #0 + 80005ce: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 80005d0: 4b07 ldr r3, [pc, #28] @ (80005f0 ) + 80005d2: 2200 movs r2, #0 + 80005d4: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 80005d6: 4b06 ldr r3, [pc, #24] @ (80005f0 ) + 80005d8: 220a movs r2, #10 + 80005da: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 80005dc: 4804 ldr r0, [pc, #16] @ (80005f0 ) + 80005de: f001 fcd3 bl 8001f88 + 80005e2: 4603 mov r3, r0 + 80005e4: 2b00 cmp r3, #0 + 80005e6: d001 beq.n 80005ec + { + Error_Handler(); + 80005e8: f000 f9d8 bl 800099c + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 80005ec: bf00 nop + 80005ee: bd80 pop {r7, pc} + 80005f0: 2000002c .word 0x2000002c + 80005f4: 40013000 .word 0x40013000 + +080005f8 : + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 80005f8: b580 push {r7, lr} + 80005fa: b086 sub sp, #24 + 80005fc: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 80005fe: f107 0308 add.w r3, r7, #8 + 8000602: 2200 movs r2, #0 + 8000604: 601a str r2, [r3, #0] + 8000606: 605a str r2, [r3, #4] + 8000608: 609a str r2, [r3, #8] + 800060a: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 800060c: 463b mov r3, r7 + 800060e: 2200 movs r2, #0 + 8000610: 601a str r2, [r3, #0] + 8000612: 605a str r2, [r3, #4] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8000614: 4b1e ldr r3, [pc, #120] @ (8000690 ) + 8000616: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 + 800061a: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 1000-1; + 800061c: 4b1c ldr r3, [pc, #112] @ (8000690 ) + 800061e: f240 32e7 movw r2, #999 @ 0x3e7 + 8000622: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000624: 4b1a ldr r3, [pc, #104] @ (8000690 ) + 8000626: 2200 movs r2, #0 + 8000628: 609a str r2, [r3, #8] + htim2.Init.Period = 16000-1; + 800062a: 4b19 ldr r3, [pc, #100] @ (8000690 ) + 800062c: f643 627f movw r2, #15999 @ 0x3e7f + 8000630: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000632: 4b17 ldr r3, [pc, #92] @ (8000690 ) + 8000634: 2200 movs r2, #0 + 8000636: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 8000638: 4b15 ldr r3, [pc, #84] @ (8000690 ) + 800063a: 2280 movs r2, #128 @ 0x80 + 800063c: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + 800063e: 4814 ldr r0, [pc, #80] @ (8000690 ) + 8000640: f001 ff4c bl 80024dc + 8000644: 4603 mov r3, r0 + 8000646: 2b00 cmp r3, #0 + 8000648: d001 beq.n 800064e + { + Error_Handler(); + 800064a: f000 f9a7 bl 800099c + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 800064e: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8000652: 60bb str r3, [r7, #8] + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + 8000654: f107 0308 add.w r3, r7, #8 + 8000658: 4619 mov r1, r3 + 800065a: 480d ldr r0, [pc, #52] @ (8000690 ) + 800065c: f002 fa3c bl 8002ad8 + 8000660: 4603 mov r3, r0 + 8000662: 2b00 cmp r3, #0 + 8000664: d001 beq.n 800066a + { + Error_Handler(); + 8000666: f000 f999 bl 800099c + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 800066a: 2300 movs r3, #0 + 800066c: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 800066e: 2300 movs r3, #0 + 8000670: 607b str r3, [r7, #4] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 8000672: 463b mov r3, r7 + 8000674: 4619 mov r1, r3 + 8000676: 4806 ldr r0, [pc, #24] @ (8000690 ) + 8000678: f002 fd40 bl 80030fc + 800067c: 4603 mov r3, r0 + 800067e: 2b00 cmp r3, #0 + 8000680: d001 beq.n 8000686 + { + Error_Handler(); + 8000682: f000 f98b bl 800099c + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 8000686: bf00 nop + 8000688: 3718 adds r7, #24 + 800068a: 46bd mov sp, r7 + 800068c: bd80 pop {r7, pc} + 800068e: bf00 nop + 8000690: 20000084 .word 0x20000084 + +08000694 : + * @brief TIM4 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM4_Init(void) +{ + 8000694: b580 push {r7, lr} + 8000696: b08a sub sp, #40 @ 0x28 + 8000698: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM4_Init 0 */ + + /* USER CODE END TIM4_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800069a: f107 0318 add.w r3, r7, #24 + 800069e: 2200 movs r2, #0 + 80006a0: 601a str r2, [r3, #0] + 80006a2: 605a str r2, [r3, #4] + 80006a4: 609a str r2, [r3, #8] + 80006a6: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 80006a8: f107 0310 add.w r3, r7, #16 + 80006ac: 2200 movs r2, #0 + 80006ae: 601a str r2, [r3, #0] + 80006b0: 605a str r2, [r3, #4] + TIM_OC_InitTypeDef sConfigOC = {0}; + 80006b2: 463b mov r3, r7 + 80006b4: 2200 movs r2, #0 + 80006b6: 601a str r2, [r3, #0] + 80006b8: 605a str r2, [r3, #4] + 80006ba: 609a str r2, [r3, #8] + 80006bc: 60da str r2, [r3, #12] + + /* USER CODE BEGIN TIM4_Init 1 */ + + /* USER CODE END TIM4_Init 1 */ + htim4.Instance = TIM4; + 80006be: 4b2d ldr r3, [pc, #180] @ (8000774 ) + 80006c0: 4a2d ldr r2, [pc, #180] @ (8000778 ) + 80006c2: 601a str r2, [r3, #0] + htim4.Init.Prescaler = 20-1; + 80006c4: 4b2b ldr r3, [pc, #172] @ (8000774 ) + 80006c6: 2213 movs r2, #19 + 80006c8: 605a str r2, [r3, #4] + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 80006ca: 4b2a ldr r3, [pc, #168] @ (8000774 ) + 80006cc: 2200 movs r2, #0 + 80006ce: 609a str r2, [r3, #8] + htim4.Init.Period = 16000-1; + 80006d0: 4b28 ldr r3, [pc, #160] @ (8000774 ) + 80006d2: f643 627f movw r2, #15999 @ 0x3e7f + 80006d6: 60da str r2, [r3, #12] + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80006d8: 4b26 ldr r3, [pc, #152] @ (8000774 ) + 80006da: 2200 movs r2, #0 + 80006dc: 611a str r2, [r3, #16] + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 80006de: 4b25 ldr r3, [pc, #148] @ (8000774 ) + 80006e0: 2280 movs r2, #128 @ 0x80 + 80006e2: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + 80006e4: 4823 ldr r0, [pc, #140] @ (8000774 ) + 80006e6: f001 fef9 bl 80024dc + 80006ea: 4603 mov r3, r0 + 80006ec: 2b00 cmp r3, #0 + 80006ee: d001 beq.n 80006f4 + { + Error_Handler(); + 80006f0: f000 f954 bl 800099c + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 80006f4: f44f 5380 mov.w r3, #4096 @ 0x1000 + 80006f8: 61bb str r3, [r7, #24] + if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + 80006fa: f107 0318 add.w r3, r7, #24 + 80006fe: 4619 mov r1, r3 + 8000700: 481c ldr r0, [pc, #112] @ (8000774 ) + 8000702: f002 f9e9 bl 8002ad8 + 8000706: 4603 mov r3, r0 + 8000708: 2b00 cmp r3, #0 + 800070a: d001 beq.n 8000710 + { + Error_Handler(); + 800070c: f000 f946 bl 800099c + } + if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + 8000710: 4818 ldr r0, [pc, #96] @ (8000774 ) + 8000712: f001 ff75 bl 8002600 + 8000716: 4603 mov r3, r0 + 8000718: 2b00 cmp r3, #0 + 800071a: d001 beq.n 8000720 + { + Error_Handler(); + 800071c: f000 f93e bl 800099c + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000720: 2300 movs r3, #0 + 8000722: 613b str r3, [r7, #16] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000724: 2300 movs r3, #0 + 8000726: 617b str r3, [r7, #20] + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + 8000728: f107 0310 add.w r3, r7, #16 + 800072c: 4619 mov r1, r3 + 800072e: 4811 ldr r0, [pc, #68] @ (8000774 ) + 8000730: f002 fce4 bl 80030fc + 8000734: 4603 mov r3, r0 + 8000736: 2b00 cmp r3, #0 + 8000738: d001 beq.n 800073e + { + Error_Handler(); + 800073a: f000 f92f bl 800099c + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 800073e: 2360 movs r3, #96 @ 0x60 + 8000740: 603b str r3, [r7, #0] + sConfigOC.Pulse = 800-1; + 8000742: f240 331f movw r3, #799 @ 0x31f + 8000746: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 8000748: 2300 movs r3, #0 + 800074a: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 800074c: 2300 movs r3, #0 + 800074e: 60fb str r3, [r7, #12] + if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + 8000750: 463b mov r3, r7 + 8000752: 2204 movs r2, #4 + 8000754: 4619 mov r1, r3 + 8000756: 4807 ldr r0, [pc, #28] @ (8000774 ) + 8000758: f002 f8fc bl 8002954 + 800075c: 4603 mov r3, r0 + 800075e: 2b00 cmp r3, #0 + 8000760: d001 beq.n 8000766 + { + Error_Handler(); + 8000762: f000 f91b bl 800099c + } + /* USER CODE BEGIN TIM4_Init 2 */ + + /* USER CODE END TIM4_Init 2 */ + HAL_TIM_MspPostInit(&htim4); + 8000766: 4803 ldr r0, [pc, #12] @ (8000774 ) + 8000768: f000 f9ec bl 8000b44 + +} + 800076c: bf00 nop + 800076e: 3728 adds r7, #40 @ 0x28 + 8000770: 46bd mov sp, r7 + 8000772: bd80 pop {r7, pc} + 8000774: 200000c4 .word 0x200000c4 + 8000778: 40000800 .word 0x40000800 + +0800077c : + * @brief TIM11 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM11_Init(void) +{ + 800077c: b580 push {r7, lr} + 800077e: b088 sub sp, #32 + 8000780: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8000782: f107 0310 add.w r3, r7, #16 + 8000786: 2200 movs r2, #0 + 8000788: 601a str r2, [r3, #0] + 800078a: 605a str r2, [r3, #4] + 800078c: 609a str r2, [r3, #8] + 800078e: 60da str r2, [r3, #12] + TIM_OC_InitTypeDef sConfigOC = {0}; + 8000790: 463b mov r3, r7 + 8000792: 2200 movs r2, #0 + 8000794: 601a str r2, [r3, #0] + 8000796: 605a str r2, [r3, #4] + 8000798: 609a str r2, [r3, #8] + 800079a: 60da str r2, [r3, #12] + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + 800079c: 4b25 ldr r3, [pc, #148] @ (8000834 ) + 800079e: 4a26 ldr r2, [pc, #152] @ (8000838 ) + 80007a0: 601a str r2, [r3, #0] + htim11.Init.Prescaler = 20-1; + 80007a2: 4b24 ldr r3, [pc, #144] @ (8000834 ) + 80007a4: 2213 movs r2, #19 + 80007a6: 605a str r2, [r3, #4] + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + 80007a8: 4b22 ldr r3, [pc, #136] @ (8000834 ) + 80007aa: 2200 movs r2, #0 + 80007ac: 609a str r2, [r3, #8] + htim11.Init.Period = 16000-1; + 80007ae: 4b21 ldr r3, [pc, #132] @ (8000834 ) + 80007b0: f643 627f movw r2, #15999 @ 0x3e7f + 80007b4: 60da str r2, [r3, #12] + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80007b6: 4b1f ldr r3, [pc, #124] @ (8000834 ) + 80007b8: 2200 movs r2, #0 + 80007ba: 611a str r2, [r3, #16] + htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 80007bc: 4b1d ldr r3, [pc, #116] @ (8000834 ) + 80007be: 2280 movs r2, #128 @ 0x80 + 80007c0: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + 80007c2: 481c ldr r0, [pc, #112] @ (8000834 ) + 80007c4: f001 fe8a bl 80024dc + 80007c8: 4603 mov r3, r0 + 80007ca: 2b00 cmp r3, #0 + 80007cc: d001 beq.n 80007d2 + { + Error_Handler(); + 80007ce: f000 f8e5 bl 800099c + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 80007d2: f44f 5380 mov.w r3, #4096 @ 0x1000 + 80007d6: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim11, &sClockSourceConfig) != HAL_OK) + 80007d8: f107 0310 add.w r3, r7, #16 + 80007dc: 4619 mov r1, r3 + 80007de: 4815 ldr r0, [pc, #84] @ (8000834 ) + 80007e0: f002 f97a bl 8002ad8 + 80007e4: 4603 mov r3, r0 + 80007e6: 2b00 cmp r3, #0 + 80007e8: d001 beq.n 80007ee + { + Error_Handler(); + 80007ea: f000 f8d7 bl 800099c + } + if (HAL_TIM_PWM_Init(&htim11) != HAL_OK) + 80007ee: 4811 ldr r0, [pc, #68] @ (8000834 ) + 80007f0: f001 ff06 bl 8002600 + 80007f4: 4603 mov r3, r0 + 80007f6: 2b00 cmp r3, #0 + 80007f8: d001 beq.n 80007fe + { + Error_Handler(); + 80007fa: f000 f8cf bl 800099c + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 80007fe: 2360 movs r3, #96 @ 0x60 + 8000800: 603b str r3, [r7, #0] + sConfigOC.Pulse = 800-1; + 8000802: f240 331f movw r3, #799 @ 0x31f + 8000806: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 8000808: 2300 movs r3, #0 + 800080a: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 800080c: 2300 movs r3, #0 + 800080e: 60fb str r3, [r7, #12] + if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 8000810: 463b mov r3, r7 + 8000812: 2200 movs r2, #0 + 8000814: 4619 mov r1, r3 + 8000816: 4807 ldr r0, [pc, #28] @ (8000834 ) + 8000818: f002 f89c bl 8002954 + 800081c: 4603 mov r3, r0 + 800081e: 2b00 cmp r3, #0 + 8000820: d001 beq.n 8000826 + { + Error_Handler(); + 8000822: f000 f8bb bl 800099c + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + HAL_TIM_MspPostInit(&htim11); + 8000826: 4803 ldr r0, [pc, #12] @ (8000834 ) + 8000828: f000 f98c bl 8000b44 + +} + 800082c: bf00 nop + 800082e: 3720 adds r7, #32 + 8000830: 46bd mov sp, r7 + 8000832: bd80 pop {r7, pc} + 8000834: 20000104 .word 0x20000104 + 8000838: 40011000 .word 0x40011000 + +0800083c : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 800083c: b580 push {r7, lr} + 800083e: b088 sub sp, #32 + 8000840: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000842: f107 030c add.w r3, r7, #12 + 8000846: 2200 movs r2, #0 + 8000848: 601a str r2, [r3, #0] + 800084a: 605a str r2, [r3, #4] + 800084c: 609a str r2, [r3, #8] + 800084e: 60da str r2, [r3, #12] + 8000850: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000852: 4b28 ldr r3, [pc, #160] @ (80008f4 ) + 8000854: 69db ldr r3, [r3, #28] + 8000856: 4a27 ldr r2, [pc, #156] @ (80008f4 ) + 8000858: f043 0304 orr.w r3, r3, #4 + 800085c: 61d3 str r3, [r2, #28] + 800085e: 4b25 ldr r3, [pc, #148] @ (80008f4 ) + 8000860: 69db ldr r3, [r3, #28] + 8000862: f003 0304 and.w r3, r3, #4 + 8000866: 60bb str r3, [r7, #8] + 8000868: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800086a: 4b22 ldr r3, [pc, #136] @ (80008f4 ) + 800086c: 69db ldr r3, [r3, #28] + 800086e: 4a21 ldr r2, [pc, #132] @ (80008f4 ) + 8000870: f043 0301 orr.w r3, r3, #1 + 8000874: 61d3 str r3, [r2, #28] + 8000876: 4b1f ldr r3, [pc, #124] @ (80008f4 ) + 8000878: 69db ldr r3, [r3, #28] + 800087a: f003 0301 and.w r3, r3, #1 + 800087e: 607b str r3, [r7, #4] + 8000880: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000882: 4b1c ldr r3, [pc, #112] @ (80008f4 ) + 8000884: 69db ldr r3, [r3, #28] + 8000886: 4a1b ldr r2, [pc, #108] @ (80008f4 ) + 8000888: f043 0302 orr.w r3, r3, #2 + 800088c: 61d3 str r3, [r2, #28] + 800088e: 4b19 ldr r3, [pc, #100] @ (80008f4 ) + 8000890: 69db ldr r3, [r3, #28] + 8000892: f003 0302 and.w r3, r3, #2 + 8000896: 603b str r3, [r7, #0] + 8000898: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 800089a: 2200 movs r2, #0 + 800089c: 2101 movs r1, #1 + 800089e: 4816 ldr r0, [pc, #88] @ (80008f8 ) + 80008a0: f000 fdb6 bl 8001410 + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 80008a4: 2301 movs r3, #1 + 80008a6: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80008a8: 2301 movs r3, #1 + 80008aa: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008ac: 2300 movs r3, #0 + 80008ae: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80008b0: 2300 movs r3, #0 + 80008b2: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80008b4: f107 030c add.w r3, r7, #12 + 80008b8: 4619 mov r1, r3 + 80008ba: 480f ldr r0, [pc, #60] @ (80008f8 ) + 80008bc: f000 fc18 bl 80010f0 + + /*Configure GPIO pins : PA11 PA12 */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 80008c0: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 80008c4: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 80008c6: f44f 1388 mov.w r3, #1114112 @ 0x110000 + 80008ca: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008cc: 2300 movs r3, #0 + 80008ce: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80008d0: f107 030c add.w r3, r7, #12 + 80008d4: 4619 mov r1, r3 + 80008d6: 4809 ldr r0, [pc, #36] @ (80008fc ) + 80008d8: f000 fc0a bl 80010f0 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 80008dc: 2200 movs r2, #0 + 80008de: 2100 movs r1, #0 + 80008e0: 2028 movs r0, #40 @ 0x28 + 80008e2: f000 fbce bl 8001082 + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 80008e6: 2028 movs r0, #40 @ 0x28 + 80008e8: f000 fbe7 bl 80010ba + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 80008ec: bf00 nop + 80008ee: 3720 adds r7, #32 + 80008f0: 46bd mov sp, r7 + 80008f2: bd80 pop {r7, pc} + 80008f4: 40023800 .word 0x40023800 + 80008f8: 40020800 .word 0x40020800 + 80008fc: 40020000 .word 0x40020000 + +08000900 : + +/* USER CODE BEGIN 4 */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + 8000900: b480 push {r7} + 8000902: b083 sub sp, #12 + 8000904: af00 add r7, sp, #0 + 8000906: 6078 str r0, [r7, #4] + if (htim->Instance == TIM2) { + 8000908: 687b ldr r3, [r7, #4] + 800090a: 681b ldr r3, [r3, #0] + 800090c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8000910: d137 bne.n 8000982 + if (sens) { + 8000912: 4b1e ldr r3, [pc, #120] @ (800098c ) + 8000914: 781b ldrb r3, [r3, #0] + 8000916: b2db uxtb r3, r3 + 8000918: 2b00 cmp r3, #0 + 800091a: d00f beq.n 800093c + angle ++; + 800091c: 4b1c ldr r3, [pc, #112] @ (8000990 ) + 800091e: 781b ldrb r3, [r3, #0] + 8000920: b2db uxtb r3, r3 + 8000922: 3301 adds r3, #1 + 8000924: b2da uxtb r2, r3 + 8000926: 4b1a ldr r3, [pc, #104] @ (8000990 ) + 8000928: 701a strb r2, [r3, #0] + if (angle >= 20) { + 800092a: 4b19 ldr r3, [pc, #100] @ (8000990 ) + 800092c: 781b ldrb r3, [r3, #0] + 800092e: b2db uxtb r3, r3 + 8000930: 2b13 cmp r3, #19 + 8000932: d912 bls.n 800095a + sens = 0; + 8000934: 4b15 ldr r3, [pc, #84] @ (800098c ) + 8000936: 2200 movs r2, #0 + 8000938: 701a strb r2, [r3, #0] + 800093a: e00e b.n 800095a + } + } else { + angle --; + 800093c: 4b14 ldr r3, [pc, #80] @ (8000990 ) + 800093e: 781b ldrb r3, [r3, #0] + 8000940: b2db uxtb r3, r3 + 8000942: 3b01 subs r3, #1 + 8000944: b2da uxtb r2, r3 + 8000946: 4b12 ldr r3, [pc, #72] @ (8000990 ) + 8000948: 701a strb r2, [r3, #0] + if (angle <= 0) { + 800094a: 4b11 ldr r3, [pc, #68] @ (8000990 ) + 800094c: 781b ldrb r3, [r3, #0] + 800094e: b2db uxtb r3, r3 + 8000950: 2b00 cmp r3, #0 + 8000952: d102 bne.n 800095a + sens = 1; + 8000954: 4b0d ldr r3, [pc, #52] @ (800098c ) + 8000956: 2201 movs r2, #1 + 8000958: 701a strb r2, [r3, #0] + } + } + + TIM11 -> CCR1 = angle * 800; + 800095a: 4b0d ldr r3, [pc, #52] @ (8000990 ) + 800095c: 781b ldrb r3, [r3, #0] + 800095e: b2db uxtb r3, r3 + 8000960: 461a mov r2, r3 + 8000962: f44f 7348 mov.w r3, #800 @ 0x320 + 8000966: fb03 f202 mul.w r2, r3, r2 + 800096a: 4b0a ldr r3, [pc, #40] @ (8000994 ) + 800096c: 635a str r2, [r3, #52] @ 0x34 + TIM4 -> CCR2 = angle * 800; + 800096e: 4b08 ldr r3, [pc, #32] @ (8000990 ) + 8000970: 781b ldrb r3, [r3, #0] + 8000972: b2db uxtb r3, r3 + 8000974: 461a mov r2, r3 + 8000976: f44f 7348 mov.w r3, #800 @ 0x320 + 800097a: fb03 f202 mul.w r2, r3, r2 + 800097e: 4b06 ldr r3, [pc, #24] @ (8000998 ) + 8000980: 639a str r2, [r3, #56] @ 0x38 + } +} + 8000982: bf00 nop + 8000984: 370c adds r7, #12 + 8000986: 46bd mov sp, r7 + 8000988: bc80 pop {r7} + 800098a: 4770 bx lr + 800098c: 20000000 .word 0x20000000 + 8000990: 20000144 .word 0x20000144 + 8000994: 40011000 .word 0x40011000 + 8000998: 40000800 .word 0x40000800 + +0800099c : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 800099c: b480 push {r7} + 800099e: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 80009a0: b672 cpsid i +} + 80009a2: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 80009a4: bf00 nop + 80009a6: e7fd b.n 80009a4 + +080009a8 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80009a8: b480 push {r7} + 80009aa: b085 sub sp, #20 + 80009ac: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 80009ae: 4b14 ldr r3, [pc, #80] @ (8000a00 ) + 80009b0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80009b2: 4a13 ldr r2, [pc, #76] @ (8000a00 ) + 80009b4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 80009b8: 6253 str r3, [r2, #36] @ 0x24 + 80009ba: 4b11 ldr r3, [pc, #68] @ (8000a00 ) + 80009bc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80009be: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 80009c2: 60fb str r3, [r7, #12] + 80009c4: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80009c6: 4b0e ldr r3, [pc, #56] @ (8000a00 ) + 80009c8: 6a1b ldr r3, [r3, #32] + 80009ca: 4a0d ldr r2, [pc, #52] @ (8000a00 ) + 80009cc: f043 0301 orr.w r3, r3, #1 + 80009d0: 6213 str r3, [r2, #32] + 80009d2: 4b0b ldr r3, [pc, #44] @ (8000a00 ) + 80009d4: 6a1b ldr r3, [r3, #32] + 80009d6: f003 0301 and.w r3, r3, #1 + 80009da: 60bb str r3, [r7, #8] + 80009dc: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 80009de: 4b08 ldr r3, [pc, #32] @ (8000a00 ) + 80009e0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80009e2: 4a07 ldr r2, [pc, #28] @ (8000a00 ) + 80009e4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80009e8: 6253 str r3, [r2, #36] @ 0x24 + 80009ea: 4b05 ldr r3, [pc, #20] @ (8000a00 ) + 80009ec: 6a5b ldr r3, [r3, #36] @ 0x24 + 80009ee: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80009f2: 607b str r3, [r7, #4] + 80009f4: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80009f6: bf00 nop + 80009f8: 3714 adds r7, #20 + 80009fa: 46bd mov sp, r7 + 80009fc: bc80 pop {r7} + 80009fe: 4770 bx lr + 8000a00: 40023800 .word 0x40023800 + +08000a04 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8000a04: b580 push {r7, lr} + 8000a06: b08a sub sp, #40 @ 0x28 + 8000a08: af00 add r7, sp, #0 + 8000a0a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000a0c: f107 0314 add.w r3, r7, #20 + 8000a10: 2200 movs r2, #0 + 8000a12: 601a str r2, [r3, #0] + 8000a14: 605a str r2, [r3, #4] + 8000a16: 609a str r2, [r3, #8] + 8000a18: 60da str r2, [r3, #12] + 8000a1a: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 8000a1c: 687b ldr r3, [r7, #4] + 8000a1e: 681b ldr r3, [r3, #0] + 8000a20: 4a17 ldr r2, [pc, #92] @ (8000a80 ) + 8000a22: 4293 cmp r3, r2 + 8000a24: d127 bne.n 8000a76 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 8000a26: 4b17 ldr r3, [pc, #92] @ (8000a84 ) + 8000a28: 6a1b ldr r3, [r3, #32] + 8000a2a: 4a16 ldr r2, [pc, #88] @ (8000a84 ) + 8000a2c: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 8000a30: 6213 str r3, [r2, #32] + 8000a32: 4b14 ldr r3, [pc, #80] @ (8000a84 ) + 8000a34: 6a1b ldr r3, [r3, #32] + 8000a36: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8000a3a: 613b str r3, [r7, #16] + 8000a3c: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000a3e: 4b11 ldr r3, [pc, #68] @ (8000a84 ) + 8000a40: 69db ldr r3, [r3, #28] + 8000a42: 4a10 ldr r2, [pc, #64] @ (8000a84 ) + 8000a44: f043 0301 orr.w r3, r3, #1 + 8000a48: 61d3 str r3, [r2, #28] + 8000a4a: 4b0e ldr r3, [pc, #56] @ (8000a84 ) + 8000a4c: 69db ldr r3, [r3, #28] + 8000a4e: f003 0301 and.w r3, r3, #1 + 8000a52: 60fb str r3, [r7, #12] + 8000a54: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 8000a56: 23e0 movs r3, #224 @ 0xe0 + 8000a58: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000a5a: 2302 movs r3, #2 + 8000a5c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000a5e: 2300 movs r3, #0 + 8000a60: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000a62: 2303 movs r3, #3 + 8000a64: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8000a66: 2305 movs r3, #5 + 8000a68: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000a6a: f107 0314 add.w r3, r7, #20 + 8000a6e: 4619 mov r1, r3 + 8000a70: 4805 ldr r0, [pc, #20] @ (8000a88 ) + 8000a72: f000 fb3d bl 80010f0 + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 8000a76: bf00 nop + 8000a78: 3728 adds r7, #40 @ 0x28 + 8000a7a: 46bd mov sp, r7 + 8000a7c: bd80 pop {r7, pc} + 8000a7e: bf00 nop + 8000a80: 40013000 .word 0x40013000 + 8000a84: 40023800 .word 0x40023800 + 8000a88: 40020000 .word 0x40020000 + +08000a8c : + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8000a8c: b580 push {r7, lr} + 8000a8e: b086 sub sp, #24 + 8000a90: af00 add r7, sp, #0 + 8000a92: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM2) + 8000a94: 687b ldr r3, [r7, #4] + 8000a96: 681b ldr r3, [r3, #0] + 8000a98: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8000a9c: d114 bne.n 8000ac8 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 8000a9e: 4b26 ldr r3, [pc, #152] @ (8000b38 ) + 8000aa0: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000aa2: 4a25 ldr r2, [pc, #148] @ (8000b38 ) + 8000aa4: f043 0301 orr.w r3, r3, #1 + 8000aa8: 6253 str r3, [r2, #36] @ 0x24 + 8000aaa: 4b23 ldr r3, [pc, #140] @ (8000b38 ) + 8000aac: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000aae: f003 0301 and.w r3, r3, #1 + 8000ab2: 617b str r3, [r7, #20] + 8000ab4: 697b ldr r3, [r7, #20] + /* TIM2 interrupt Init */ + HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); + 8000ab6: 2200 movs r2, #0 + 8000ab8: 2100 movs r1, #0 + 8000aba: 201c movs r0, #28 + 8000abc: f000 fae1 bl 8001082 + HAL_NVIC_EnableIRQ(TIM2_IRQn); + 8000ac0: 201c movs r0, #28 + 8000ac2: f000 fafa bl 80010ba + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } + +} + 8000ac6: e032 b.n 8000b2e + else if(htim_base->Instance==TIM4) + 8000ac8: 687b ldr r3, [r7, #4] + 8000aca: 681b ldr r3, [r3, #0] + 8000acc: 4a1b ldr r2, [pc, #108] @ (8000b3c ) + 8000ace: 4293 cmp r3, r2 + 8000ad0: d114 bne.n 8000afc + __HAL_RCC_TIM4_CLK_ENABLE(); + 8000ad2: 4b19 ldr r3, [pc, #100] @ (8000b38 ) + 8000ad4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000ad6: 4a18 ldr r2, [pc, #96] @ (8000b38 ) + 8000ad8: f043 0304 orr.w r3, r3, #4 + 8000adc: 6253 str r3, [r2, #36] @ 0x24 + 8000ade: 4b16 ldr r3, [pc, #88] @ (8000b38 ) + 8000ae0: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000ae2: f003 0304 and.w r3, r3, #4 + 8000ae6: 613b str r3, [r7, #16] + 8000ae8: 693b ldr r3, [r7, #16] + HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0); + 8000aea: 2200 movs r2, #0 + 8000aec: 2100 movs r1, #0 + 8000aee: 201e movs r0, #30 + 8000af0: f000 fac7 bl 8001082 + HAL_NVIC_EnableIRQ(TIM4_IRQn); + 8000af4: 201e movs r0, #30 + 8000af6: f000 fae0 bl 80010ba +} + 8000afa: e018 b.n 8000b2e + else if(htim_base->Instance==TIM11) + 8000afc: 687b ldr r3, [r7, #4] + 8000afe: 681b ldr r3, [r3, #0] + 8000b00: 4a0f ldr r2, [pc, #60] @ (8000b40 ) + 8000b02: 4293 cmp r3, r2 + 8000b04: d113 bne.n 8000b2e + __HAL_RCC_TIM11_CLK_ENABLE(); + 8000b06: 4b0c ldr r3, [pc, #48] @ (8000b38 ) + 8000b08: 6a1b ldr r3, [r3, #32] + 8000b0a: 4a0b ldr r2, [pc, #44] @ (8000b38 ) + 8000b0c: f043 0310 orr.w r3, r3, #16 + 8000b10: 6213 str r3, [r2, #32] + 8000b12: 4b09 ldr r3, [pc, #36] @ (8000b38 ) + 8000b14: 6a1b ldr r3, [r3, #32] + 8000b16: f003 0310 and.w r3, r3, #16 + 8000b1a: 60fb str r3, [r7, #12] + 8000b1c: 68fb ldr r3, [r7, #12] + HAL_NVIC_SetPriority(TIM11_IRQn, 0, 0); + 8000b1e: 2200 movs r2, #0 + 8000b20: 2100 movs r1, #0 + 8000b22: 201b movs r0, #27 + 8000b24: f000 faad bl 8001082 + HAL_NVIC_EnableIRQ(TIM11_IRQn); + 8000b28: 201b movs r0, #27 + 8000b2a: f000 fac6 bl 80010ba +} + 8000b2e: bf00 nop + 8000b30: 3718 adds r7, #24 + 8000b32: 46bd mov sp, r7 + 8000b34: bd80 pop {r7, pc} + 8000b36: bf00 nop + 8000b38: 40023800 .word 0x40023800 + 8000b3c: 40000800 .word 0x40000800 + 8000b40: 40011000 .word 0x40011000 + +08000b44 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8000b44: b580 push {r7, lr} + 8000b46: b08a sub sp, #40 @ 0x28 + 8000b48: af00 add r7, sp, #0 + 8000b4a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000b4c: f107 0314 add.w r3, r7, #20 + 8000b50: 2200 movs r2, #0 + 8000b52: 601a str r2, [r3, #0] + 8000b54: 605a str r2, [r3, #4] + 8000b56: 609a str r2, [r3, #8] + 8000b58: 60da str r2, [r3, #12] + 8000b5a: 611a str r2, [r3, #16] + if(htim->Instance==TIM4) + 8000b5c: 687b ldr r3, [r7, #4] + 8000b5e: 681b ldr r3, [r3, #0] + 8000b60: 4a22 ldr r2, [pc, #136] @ (8000bec ) + 8000b62: 4293 cmp r3, r2 + 8000b64: d11c bne.n 8000ba0 + { + /* USER CODE BEGIN TIM4_MspPostInit 0 */ + + /* USER CODE END TIM4_MspPostInit 0 */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000b66: 4b22 ldr r3, [pc, #136] @ (8000bf0 ) + 8000b68: 69db ldr r3, [r3, #28] + 8000b6a: 4a21 ldr r2, [pc, #132] @ (8000bf0 ) + 8000b6c: f043 0302 orr.w r3, r3, #2 + 8000b70: 61d3 str r3, [r2, #28] + 8000b72: 4b1f ldr r3, [pc, #124] @ (8000bf0 ) + 8000b74: 69db ldr r3, [r3, #28] + 8000b76: f003 0302 and.w r3, r3, #2 + 8000b7a: 613b str r3, [r7, #16] + 8000b7c: 693b ldr r3, [r7, #16] + /**TIM4 GPIO Configuration + PB7 ------> TIM4_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + 8000b7e: 2380 movs r3, #128 @ 0x80 + 8000b80: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000b82: 2302 movs r3, #2 + 8000b84: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000b86: 2300 movs r3, #0 + 8000b88: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000b8a: 2300 movs r3, #0 + 8000b8c: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 8000b8e: 2302 movs r3, #2 + 8000b90: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000b92: f107 0314 add.w r3, r7, #20 + 8000b96: 4619 mov r1, r3 + 8000b98: 4816 ldr r0, [pc, #88] @ (8000bf4 ) + 8000b9a: f000 faa9 bl 80010f0 + /* USER CODE BEGIN TIM11_MspPostInit 1 */ + + /* USER CODE END TIM11_MspPostInit 1 */ + } + +} + 8000b9e: e021 b.n 8000be4 + else if(htim->Instance==TIM11) + 8000ba0: 687b ldr r3, [r7, #4] + 8000ba2: 681b ldr r3, [r3, #0] + 8000ba4: 4a14 ldr r2, [pc, #80] @ (8000bf8 ) + 8000ba6: 4293 cmp r3, r2 + 8000ba8: d11c bne.n 8000be4 + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000baa: 4b11 ldr r3, [pc, #68] @ (8000bf0 ) + 8000bac: 69db ldr r3, [r3, #28] + 8000bae: 4a10 ldr r2, [pc, #64] @ (8000bf0 ) + 8000bb0: f043 0302 orr.w r3, r3, #2 + 8000bb4: 61d3 str r3, [r2, #28] + 8000bb6: 4b0e ldr r3, [pc, #56] @ (8000bf0 ) + 8000bb8: 69db ldr r3, [r3, #28] + 8000bba: f003 0302 and.w r3, r3, #2 + 8000bbe: 60fb str r3, [r7, #12] + 8000bc0: 68fb ldr r3, [r7, #12] + GPIO_InitStruct.Pin = GPIO_PIN_15; + 8000bc2: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8000bc6: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000bc8: 2302 movs r3, #2 + 8000bca: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000bcc: 2300 movs r3, #0 + 8000bce: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000bd0: 2300 movs r3, #0 + 8000bd2: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + 8000bd4: 2303 movs r3, #3 + 8000bd6: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000bd8: f107 0314 add.w r3, r7, #20 + 8000bdc: 4619 mov r1, r3 + 8000bde: 4805 ldr r0, [pc, #20] @ (8000bf4 ) + 8000be0: f000 fa86 bl 80010f0 +} + 8000be4: bf00 nop + 8000be6: 3728 adds r7, #40 @ 0x28 + 8000be8: 46bd mov sp, r7 + 8000bea: bd80 pop {r7, pc} + 8000bec: 40000800 .word 0x40000800 + 8000bf0: 40023800 .word 0x40023800 + 8000bf4: 40020400 .word 0x40020400 + 8000bf8: 40011000 .word 0x40011000 + +08000bfc : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000bfc: b480 push {r7} + 8000bfe: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000c00: bf00 nop + 8000c02: e7fd b.n 8000c00 + +08000c04 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000c04: b480 push {r7} + 8000c06: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000c08: bf00 nop + 8000c0a: e7fd b.n 8000c08 + +08000c0c : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000c0c: b480 push {r7} + 8000c0e: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000c10: bf00 nop + 8000c12: e7fd b.n 8000c10 + +08000c14 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000c14: b480 push {r7} + 8000c16: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000c18: bf00 nop + 8000c1a: e7fd b.n 8000c18 + +08000c1c : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000c1c: b480 push {r7} + 8000c1e: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000c20: bf00 nop + 8000c22: e7fd b.n 8000c20 + +08000c24 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000c24: b480 push {r7} + 8000c26: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000c28: bf00 nop + 8000c2a: 46bd mov sp, r7 + 8000c2c: bc80 pop {r7} + 8000c2e: 4770 bx lr + +08000c30 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000c30: b480 push {r7} + 8000c32: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000c34: bf00 nop + 8000c36: 46bd mov sp, r7 + 8000c38: bc80 pop {r7} + 8000c3a: 4770 bx lr + +08000c3c : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000c3c: b480 push {r7} + 8000c3e: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000c40: bf00 nop + 8000c42: 46bd mov sp, r7 + 8000c44: bc80 pop {r7} + 8000c46: 4770 bx lr + +08000c48 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000c48: b580 push {r7, lr} + 8000c4a: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000c4c: f000 f926 bl 8000e9c + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000c50: bf00 nop + 8000c52: bd80 pop {r7, pc} + +08000c54 : + +/** + * @brief This function handles TIM11 global interrupt. + */ +void TIM11_IRQHandler(void) +{ + 8000c54: b580 push {r7, lr} + 8000c56: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM11_IRQn 0 */ + + /* USER CODE END TIM11_IRQn 0 */ + HAL_TIM_IRQHandler(&htim11); + 8000c58: 4802 ldr r0, [pc, #8] @ (8000c64 ) + 8000c5a: f001 fdaf bl 80027bc + /* USER CODE BEGIN TIM11_IRQn 1 */ + + /* USER CODE END TIM11_IRQn 1 */ +} + 8000c5e: bf00 nop + 8000c60: bd80 pop {r7, pc} + 8000c62: bf00 nop + 8000c64: 20000104 .word 0x20000104 + +08000c68 : + +/** + * @brief This function handles TIM2 global interrupt. + */ +void TIM2_IRQHandler(void) +{ + 8000c68: b580 push {r7, lr} + 8000c6a: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM2_IRQn 0 */ + + /* USER CODE END TIM2_IRQn 0 */ + HAL_TIM_IRQHandler(&htim2); + 8000c6c: 4802 ldr r0, [pc, #8] @ (8000c78 ) + 8000c6e: f001 fda5 bl 80027bc + /* USER CODE BEGIN TIM2_IRQn 1 */ + + /* USER CODE END TIM2_IRQn 1 */ +} + 8000c72: bf00 nop + 8000c74: bd80 pop {r7, pc} + 8000c76: bf00 nop + 8000c78: 20000084 .word 0x20000084 + +08000c7c : + +/** + * @brief This function handles TIM4 global interrupt. + */ +void TIM4_IRQHandler(void) +{ + 8000c7c: b580 push {r7, lr} + 8000c7e: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM4_IRQn 0 */ + + /* USER CODE END TIM4_IRQn 0 */ + HAL_TIM_IRQHandler(&htim4); + 8000c80: 4802 ldr r0, [pc, #8] @ (8000c8c ) + 8000c82: f001 fd9b bl 80027bc + /* USER CODE BEGIN TIM4_IRQn 1 */ + + /* USER CODE END TIM4_IRQn 1 */ +} + 8000c86: bf00 nop + 8000c88: bd80 pop {r7, pc} + 8000c8a: bf00 nop + 8000c8c: 200000c4 .word 0x200000c4 + +08000c90 : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 8000c90: b580 push {r7, lr} + 8000c92: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + 8000c94: f44f 6000 mov.w r0, #2048 @ 0x800 + 8000c98: f000 fbd2 bl 8001440 + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + 8000c9c: f44f 5080 mov.w r0, #4096 @ 0x1000 + 8000ca0: f000 fbce bl 8001440 + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8000ca4: bf00 nop + 8000ca6: bd80 pop {r7, pc} + +08000ca8 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000ca8: b480 push {r7} + 8000caa: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000cac: bf00 nop + 8000cae: 46bd mov sp, r7 + 8000cb0: bc80 pop {r7} + 8000cb2: 4770 bx lr + +08000cb4 : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000cb4: f7ff fff8 bl 8000ca8 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000cb8: 480b ldr r0, [pc, #44] @ (8000ce8 ) + ldr r1, =_edata + 8000cba: 490c ldr r1, [pc, #48] @ (8000cec ) + ldr r2, =_sidata + 8000cbc: 4a0c ldr r2, [pc, #48] @ (8000cf0 ) + movs r3, #0 + 8000cbe: 2300 movs r3, #0 + b LoopCopyDataInit + 8000cc0: e002 b.n 8000cc8 + +08000cc2 : + +CopyDataInit: + ldr r4, [r2, r3] + 8000cc2: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000cc4: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000cc6: 3304 adds r3, #4 + +08000cc8 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000cc8: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000cca: 428c cmp r4, r1 + bcc CopyDataInit + 8000ccc: d3f9 bcc.n 8000cc2 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000cce: 4a09 ldr r2, [pc, #36] @ (8000cf4 ) + ldr r4, =_ebss + 8000cd0: 4c09 ldr r4, [pc, #36] @ (8000cf8 ) + movs r3, #0 + 8000cd2: 2300 movs r3, #0 + b LoopFillZerobss + 8000cd4: e001 b.n 8000cda + +08000cd6 : + +FillZerobss: + str r3, [r2] + 8000cd6: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000cd8: 3204 adds r2, #4 + +08000cda : + +LoopFillZerobss: + cmp r2, r4 + 8000cda: 42a2 cmp r2, r4 + bcc FillZerobss + 8000cdc: d3fb bcc.n 8000cd6 + +/* Call static constructors */ + bl __libc_init_array + 8000cde: f002 fa73 bl 80031c8 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8000ce2: f7ff fbe5 bl 80004b0
+ bx lr + 8000ce6: 4770 bx lr + ldr r0, =_sdata + 8000ce8: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000cec: 20000010 .word 0x20000010 + ldr r2, =_sidata + 8000cf0: 08003254 .word 0x08003254 + ldr r2, =_sbss + 8000cf4: 20000010 .word 0x20000010 + ldr r4, =_ebss + 8000cf8: 2000014c .word 0x2000014c + +08000cfc : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000cfc: e7fe b.n 8000cfc + +08000cfe : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 8000cfe: b580 push {r7, lr} + 8000d00: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 8000d02: 2107 movs r1, #7 + 8000d04: 200b movs r0, #11 + 8000d06: f000 f847 bl 8000d98 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 8000d0a: 2100 movs r1, #0 + 8000d0c: 2009 movs r0, #9 + 8000d0e: f000 f843 bl 8000d98 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 8000d12: f000 f809 bl 8000d28 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 8000d16: f000 f80f bl 8000d38 + MAX7219_Clear(); // clear all digits + 8000d1a: f000 f827 bl 8000d6c + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 8000d1e: 200f movs r0, #15 + 8000d20: f000 f812 bl 8000d48 +} + 8000d24: bf00 nop + 8000d26: bd80 pop {r7, pc} + +08000d28 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000d28: b580 push {r7, lr} + 8000d2a: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000d2c: 2101 movs r1, #1 + 8000d2e: 200c movs r0, #12 + 8000d30: f000 f832 bl 8000d98 +} + 8000d34: bf00 nop + 8000d36: bd80 pop {r7, pc} + +08000d38 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 8000d38: b580 push {r7, lr} + 8000d3a: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 8000d3c: 2100 movs r1, #0 + 8000d3e: 200f movs r0, #15 + 8000d40: f000 f82a bl 8000d98 +} + 8000d44: bf00 nop + 8000d46: bd80 pop {r7, pc} + +08000d48 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 8000d48: b580 push {r7, lr} + 8000d4a: b082 sub sp, #8 + 8000d4c: af00 add r7, sp, #0 + 8000d4e: 4603 mov r3, r0 + 8000d50: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 8000d52: 79fb ldrb r3, [r7, #7] + 8000d54: f003 030f and.w r3, r3, #15 + 8000d58: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 8000d5a: 79fb ldrb r3, [r7, #7] + 8000d5c: 4619 mov r1, r3 + 8000d5e: 200a movs r0, #10 + 8000d60: f000 f81a bl 8000d98 +} + 8000d64: bf00 nop + 8000d66: 3708 adds r7, #8 + 8000d68: 46bd mov sp, r7 + 8000d6a: bd80 pop {r7, pc} + +08000d6c : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 8000d6c: b580 push {r7, lr} + 8000d6e: b082 sub sp, #8 + 8000d70: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 8000d72: 2300 movs r3, #0 + 8000d74: 71fb strb r3, [r7, #7] + 8000d76: e007 b.n 8000d88 + MAX7219_Write(i, 0x00); // turn all segments off + 8000d78: 79fb ldrb r3, [r7, #7] + 8000d7a: 2100 movs r1, #0 + 8000d7c: 4618 mov r0, r3 + 8000d7e: f000 f80b bl 8000d98 + for (i=0; i < 8; i++) + 8000d82: 79fb ldrb r3, [r7, #7] + 8000d84: 3301 adds r3, #1 + 8000d86: 71fb strb r3, [r7, #7] + 8000d88: 79fb ldrb r3, [r7, #7] + 8000d8a: 2b07 cmp r3, #7 + 8000d8c: d9f4 bls.n 8000d78 +} + 8000d8e: bf00 nop + 8000d90: bf00 nop + 8000d92: 3708 adds r7, #8 + 8000d94: 46bd mov sp, r7 + 8000d96: bd80 pop {r7, pc} + +08000d98 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8000d98: b580 push {r7, lr} + 8000d9a: b082 sub sp, #8 + 8000d9c: af00 add r7, sp, #0 + 8000d9e: 4603 mov r3, r0 + 8000da0: 460a mov r2, r1 + 8000da2: 71fb strb r3, [r7, #7] + 8000da4: 4613 mov r3, r2 + 8000da6: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8000da8: 4b09 ldr r3, [pc, #36] @ (8000dd0 ) + 8000daa: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000dae: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8000db0: 79fb ldrb r3, [r7, #7] + 8000db2: 4618 mov r0, r3 + 8000db4: f000 f80e bl 8000dd4 + MAX7219_SendByte(dataout); // write data to MAX7219 + 8000db8: 79bb ldrb r3, [r7, #6] + 8000dba: 4618 mov r0, r3 + 8000dbc: f000 f80a bl 8000dd4 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 8000dc0: 4b03 ldr r3, [pc, #12] @ (8000dd0 ) + 8000dc2: 2201 movs r2, #1 + 8000dc4: 619a str r2, [r3, #24] + } + 8000dc6: bf00 nop + 8000dc8: 3708 adds r7, #8 + 8000dca: 46bd mov sp, r7 + 8000dcc: bd80 pop {r7, pc} + 8000dce: bf00 nop + 8000dd0: 40020800 .word 0x40020800 + +08000dd4 : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000dd4: b580 push {r7, lr} + 8000dd6: b082 sub sp, #8 + 8000dd8: af00 add r7, sp, #0 + 8000dda: 4603 mov r3, r0 + 8000ddc: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 8000dde: 1df9 adds r1, r7, #7 + 8000de0: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000de4: 2201 movs r2, #1 + 8000de6: 4803 ldr r0, [pc, #12] @ (8000df4 ) + 8000de8: f001 f957 bl 800209a + +} + 8000dec: bf00 nop + 8000dee: 3708 adds r7, #8 + 8000df0: 46bd mov sp, r7 + 8000df2: bd80 pop {r7, pc} + 8000df4: 2000002c .word 0x2000002c + +08000df8 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000df8: b580 push {r7, lr} + 8000dfa: b082 sub sp, #8 + 8000dfc: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000dfe: 2300 movs r3, #0 + 8000e00: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000e02: 2003 movs r0, #3 + 8000e04: f000 f932 bl 800106c + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000e08: 200f movs r0, #15 + 8000e0a: f000 f80d bl 8000e28 + 8000e0e: 4603 mov r3, r0 + 8000e10: 2b00 cmp r3, #0 + 8000e12: d002 beq.n 8000e1a + { + status = HAL_ERROR; + 8000e14: 2301 movs r3, #1 + 8000e16: 71fb strb r3, [r7, #7] + 8000e18: e001 b.n 8000e1e + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000e1a: f7ff fdc5 bl 80009a8 + } + + /* Return function status */ + return status; + 8000e1e: 79fb ldrb r3, [r7, #7] +} + 8000e20: 4618 mov r0, r3 + 8000e22: 3708 adds r7, #8 + 8000e24: 46bd mov sp, r7 + 8000e26: bd80 pop {r7, pc} + +08000e28 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000e28: b580 push {r7, lr} + 8000e2a: b084 sub sp, #16 + 8000e2c: af00 add r7, sp, #0 + 8000e2e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000e30: 2300 movs r3, #0 + 8000e32: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 8000e34: 4b16 ldr r3, [pc, #88] @ (8000e90 ) + 8000e36: 681b ldr r3, [r3, #0] + 8000e38: 2b00 cmp r3, #0 + 8000e3a: d022 beq.n 8000e82 + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 8000e3c: 4b15 ldr r3, [pc, #84] @ (8000e94 ) + 8000e3e: 681a ldr r2, [r3, #0] + 8000e40: 4b13 ldr r3, [pc, #76] @ (8000e90 ) + 8000e42: 681b ldr r3, [r3, #0] + 8000e44: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8000e48: fbb1 f3f3 udiv r3, r1, r3 + 8000e4c: fbb2 f3f3 udiv r3, r2, r3 + 8000e50: 4618 mov r0, r3 + 8000e52: f000 f940 bl 80010d6 + 8000e56: 4603 mov r3, r0 + 8000e58: 2b00 cmp r3, #0 + 8000e5a: d10f bne.n 8000e7c + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000e5c: 687b ldr r3, [r7, #4] + 8000e5e: 2b0f cmp r3, #15 + 8000e60: d809 bhi.n 8000e76 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000e62: 2200 movs r2, #0 + 8000e64: 6879 ldr r1, [r7, #4] + 8000e66: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000e6a: f000 f90a bl 8001082 + uwTickPrio = TickPriority; + 8000e6e: 4a0a ldr r2, [pc, #40] @ (8000e98 ) + 8000e70: 687b ldr r3, [r7, #4] + 8000e72: 6013 str r3, [r2, #0] + 8000e74: e007 b.n 8000e86 + } + else + { + status = HAL_ERROR; + 8000e76: 2301 movs r3, #1 + 8000e78: 73fb strb r3, [r7, #15] + 8000e7a: e004 b.n 8000e86 + } + } + else + { + status = HAL_ERROR; + 8000e7c: 2301 movs r3, #1 + 8000e7e: 73fb strb r3, [r7, #15] + 8000e80: e001 b.n 8000e86 + } + } + else + { + status = HAL_ERROR; + 8000e82: 2301 movs r3, #1 + 8000e84: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8000e86: 7bfb ldrb r3, [r7, #15] +} + 8000e88: 4618 mov r0, r3 + 8000e8a: 3710 adds r7, #16 + 8000e8c: 46bd mov sp, r7 + 8000e8e: bd80 pop {r7, pc} + 8000e90: 2000000c .word 0x2000000c + 8000e94: 20000004 .word 0x20000004 + 8000e98: 20000008 .word 0x20000008 + +08000e9c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000e9c: b480 push {r7} + 8000e9e: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000ea0: 4b05 ldr r3, [pc, #20] @ (8000eb8 ) + 8000ea2: 681a ldr r2, [r3, #0] + 8000ea4: 4b05 ldr r3, [pc, #20] @ (8000ebc ) + 8000ea6: 681b ldr r3, [r3, #0] + 8000ea8: 4413 add r3, r2 + 8000eaa: 4a03 ldr r2, [pc, #12] @ (8000eb8 ) + 8000eac: 6013 str r3, [r2, #0] +} + 8000eae: bf00 nop + 8000eb0: 46bd mov sp, r7 + 8000eb2: bc80 pop {r7} + 8000eb4: 4770 bx lr + 8000eb6: bf00 nop + 8000eb8: 20000148 .word 0x20000148 + 8000ebc: 2000000c .word 0x2000000c + +08000ec0 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000ec0: b480 push {r7} + 8000ec2: af00 add r7, sp, #0 + return uwTick; + 8000ec4: 4b02 ldr r3, [pc, #8] @ (8000ed0 ) + 8000ec6: 681b ldr r3, [r3, #0] +} + 8000ec8: 4618 mov r0, r3 + 8000eca: 46bd mov sp, r7 + 8000ecc: bc80 pop {r7} + 8000ece: 4770 bx lr + 8000ed0: 20000148 .word 0x20000148 + +08000ed4 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000ed4: b480 push {r7} + 8000ed6: b085 sub sp, #20 + 8000ed8: af00 add r7, sp, #0 + 8000eda: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000edc: 687b ldr r3, [r7, #4] + 8000ede: f003 0307 and.w r3, r3, #7 + 8000ee2: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000ee4: 4b0c ldr r3, [pc, #48] @ (8000f18 <__NVIC_SetPriorityGrouping+0x44>) + 8000ee6: 68db ldr r3, [r3, #12] + 8000ee8: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000eea: 68ba ldr r2, [r7, #8] + 8000eec: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000ef0: 4013 ands r3, r2 + 8000ef2: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000ef4: 68fb ldr r3, [r7, #12] + 8000ef6: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000ef8: 68bb ldr r3, [r7, #8] + 8000efa: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000efc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000f00: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000f04: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000f06: 4a04 ldr r2, [pc, #16] @ (8000f18 <__NVIC_SetPriorityGrouping+0x44>) + 8000f08: 68bb ldr r3, [r7, #8] + 8000f0a: 60d3 str r3, [r2, #12] +} + 8000f0c: bf00 nop + 8000f0e: 3714 adds r7, #20 + 8000f10: 46bd mov sp, r7 + 8000f12: bc80 pop {r7} + 8000f14: 4770 bx lr + 8000f16: bf00 nop + 8000f18: e000ed00 .word 0xe000ed00 + +08000f1c <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000f1c: b480 push {r7} + 8000f1e: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000f20: 4b04 ldr r3, [pc, #16] @ (8000f34 <__NVIC_GetPriorityGrouping+0x18>) + 8000f22: 68db ldr r3, [r3, #12] + 8000f24: 0a1b lsrs r3, r3, #8 + 8000f26: f003 0307 and.w r3, r3, #7 +} + 8000f2a: 4618 mov r0, r3 + 8000f2c: 46bd mov sp, r7 + 8000f2e: bc80 pop {r7} + 8000f30: 4770 bx lr + 8000f32: bf00 nop + 8000f34: e000ed00 .word 0xe000ed00 + +08000f38 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000f38: b480 push {r7} + 8000f3a: b083 sub sp, #12 + 8000f3c: af00 add r7, sp, #0 + 8000f3e: 4603 mov r3, r0 + 8000f40: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000f42: f997 3007 ldrsb.w r3, [r7, #7] + 8000f46: 2b00 cmp r3, #0 + 8000f48: db0b blt.n 8000f62 <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8000f4a: 79fb ldrb r3, [r7, #7] + 8000f4c: f003 021f and.w r2, r3, #31 + 8000f50: 4906 ldr r1, [pc, #24] @ (8000f6c <__NVIC_EnableIRQ+0x34>) + 8000f52: f997 3007 ldrsb.w r3, [r7, #7] + 8000f56: 095b lsrs r3, r3, #5 + 8000f58: 2001 movs r0, #1 + 8000f5a: fa00 f202 lsl.w r2, r0, r2 + 8000f5e: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8000f62: bf00 nop + 8000f64: 370c adds r7, #12 + 8000f66: 46bd mov sp, r7 + 8000f68: bc80 pop {r7} + 8000f6a: 4770 bx lr + 8000f6c: e000e100 .word 0xe000e100 + +08000f70 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000f70: b480 push {r7} + 8000f72: b083 sub sp, #12 + 8000f74: af00 add r7, sp, #0 + 8000f76: 4603 mov r3, r0 + 8000f78: 6039 str r1, [r7, #0] + 8000f7a: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000f7c: f997 3007 ldrsb.w r3, [r7, #7] + 8000f80: 2b00 cmp r3, #0 + 8000f82: db0a blt.n 8000f9a <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000f84: 683b ldr r3, [r7, #0] + 8000f86: b2da uxtb r2, r3 + 8000f88: 490c ldr r1, [pc, #48] @ (8000fbc <__NVIC_SetPriority+0x4c>) + 8000f8a: f997 3007 ldrsb.w r3, [r7, #7] + 8000f8e: 0112 lsls r2, r2, #4 + 8000f90: b2d2 uxtb r2, r2 + 8000f92: 440b add r3, r1 + 8000f94: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000f98: e00a b.n 8000fb0 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000f9a: 683b ldr r3, [r7, #0] + 8000f9c: b2da uxtb r2, r3 + 8000f9e: 4908 ldr r1, [pc, #32] @ (8000fc0 <__NVIC_SetPriority+0x50>) + 8000fa0: 79fb ldrb r3, [r7, #7] + 8000fa2: f003 030f and.w r3, r3, #15 + 8000fa6: 3b04 subs r3, #4 + 8000fa8: 0112 lsls r2, r2, #4 + 8000faa: b2d2 uxtb r2, r2 + 8000fac: 440b add r3, r1 + 8000fae: 761a strb r2, [r3, #24] +} + 8000fb0: bf00 nop + 8000fb2: 370c adds r7, #12 + 8000fb4: 46bd mov sp, r7 + 8000fb6: bc80 pop {r7} + 8000fb8: 4770 bx lr + 8000fba: bf00 nop + 8000fbc: e000e100 .word 0xe000e100 + 8000fc0: e000ed00 .word 0xe000ed00 + +08000fc4 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000fc4: b480 push {r7} + 8000fc6: b089 sub sp, #36 @ 0x24 + 8000fc8: af00 add r7, sp, #0 + 8000fca: 60f8 str r0, [r7, #12] + 8000fcc: 60b9 str r1, [r7, #8] + 8000fce: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000fd0: 68fb ldr r3, [r7, #12] + 8000fd2: f003 0307 and.w r3, r3, #7 + 8000fd6: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000fd8: 69fb ldr r3, [r7, #28] + 8000fda: f1c3 0307 rsb r3, r3, #7 + 8000fde: 2b04 cmp r3, #4 + 8000fe0: bf28 it cs + 8000fe2: 2304 movcs r3, #4 + 8000fe4: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000fe6: 69fb ldr r3, [r7, #28] + 8000fe8: 3304 adds r3, #4 + 8000fea: 2b06 cmp r3, #6 + 8000fec: d902 bls.n 8000ff4 + 8000fee: 69fb ldr r3, [r7, #28] + 8000ff0: 3b03 subs r3, #3 + 8000ff2: e000 b.n 8000ff6 + 8000ff4: 2300 movs r3, #0 + 8000ff6: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000ff8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000ffc: 69bb ldr r3, [r7, #24] + 8000ffe: fa02 f303 lsl.w r3, r2, r3 + 8001002: 43da mvns r2, r3 + 8001004: 68bb ldr r3, [r7, #8] + 8001006: 401a ands r2, r3 + 8001008: 697b ldr r3, [r7, #20] + 800100a: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 800100c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8001010: 697b ldr r3, [r7, #20] + 8001012: fa01 f303 lsl.w r3, r1, r3 + 8001016: 43d9 mvns r1, r3 + 8001018: 687b ldr r3, [r7, #4] + 800101a: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 800101c: 4313 orrs r3, r2 + ); +} + 800101e: 4618 mov r0, r3 + 8001020: 3724 adds r7, #36 @ 0x24 + 8001022: 46bd mov sp, r7 + 8001024: bc80 pop {r7} + 8001026: 4770 bx lr + +08001028 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001028: b580 push {r7, lr} + 800102a: b082 sub sp, #8 + 800102c: af00 add r7, sp, #0 + 800102e: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001030: 687b ldr r3, [r7, #4] + 8001032: 3b01 subs r3, #1 + 8001034: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8001038: d301 bcc.n 800103e + { + return (1UL); /* Reload value impossible */ + 800103a: 2301 movs r3, #1 + 800103c: e00f b.n 800105e + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 800103e: 4a0a ldr r2, [pc, #40] @ (8001068 ) + 8001040: 687b ldr r3, [r7, #4] + 8001042: 3b01 subs r3, #1 + 8001044: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8001046: 210f movs r1, #15 + 8001048: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800104c: f7ff ff90 bl 8000f70 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8001050: 4b05 ldr r3, [pc, #20] @ (8001068 ) + 8001052: 2200 movs r2, #0 + 8001054: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001056: 4b04 ldr r3, [pc, #16] @ (8001068 ) + 8001058: 2207 movs r2, #7 + 800105a: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 800105c: 2300 movs r3, #0 +} + 800105e: 4618 mov r0, r3 + 8001060: 3708 adds r7, #8 + 8001062: 46bd mov sp, r7 + 8001064: bd80 pop {r7, pc} + 8001066: bf00 nop + 8001068: e000e010 .word 0xe000e010 + +0800106c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 800106c: b580 push {r7, lr} + 800106e: b082 sub sp, #8 + 8001070: af00 add r7, sp, #0 + 8001072: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001074: 6878 ldr r0, [r7, #4] + 8001076: f7ff ff2d bl 8000ed4 <__NVIC_SetPriorityGrouping> +} + 800107a: bf00 nop + 800107c: 3708 adds r7, #8 + 800107e: 46bd mov sp, r7 + 8001080: bd80 pop {r7, pc} + +08001082 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001082: b580 push {r7, lr} + 8001084: b086 sub sp, #24 + 8001086: af00 add r7, sp, #0 + 8001088: 4603 mov r3, r0 + 800108a: 60b9 str r1, [r7, #8] + 800108c: 607a str r2, [r7, #4] + 800108e: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8001090: 2300 movs r3, #0 + 8001092: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001094: f7ff ff42 bl 8000f1c <__NVIC_GetPriorityGrouping> + 8001098: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 800109a: 687a ldr r2, [r7, #4] + 800109c: 68b9 ldr r1, [r7, #8] + 800109e: 6978 ldr r0, [r7, #20] + 80010a0: f7ff ff90 bl 8000fc4 + 80010a4: 4602 mov r2, r0 + 80010a6: f997 300f ldrsb.w r3, [r7, #15] + 80010aa: 4611 mov r1, r2 + 80010ac: 4618 mov r0, r3 + 80010ae: f7ff ff5f bl 8000f70 <__NVIC_SetPriority> +} + 80010b2: bf00 nop + 80010b4: 3718 adds r7, #24 + 80010b6: 46bd mov sp, r7 + 80010b8: bd80 pop {r7, pc} + +080010ba : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80010ba: b580 push {r7, lr} + 80010bc: b082 sub sp, #8 + 80010be: af00 add r7, sp, #0 + 80010c0: 4603 mov r3, r0 + 80010c2: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 80010c4: f997 3007 ldrsb.w r3, [r7, #7] + 80010c8: 4618 mov r0, r3 + 80010ca: f7ff ff35 bl 8000f38 <__NVIC_EnableIRQ> +} + 80010ce: bf00 nop + 80010d0: 3708 adds r7, #8 + 80010d2: 46bd mov sp, r7 + 80010d4: bd80 pop {r7, pc} + +080010d6 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 80010d6: b580 push {r7, lr} + 80010d8: b082 sub sp, #8 + 80010da: af00 add r7, sp, #0 + 80010dc: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 80010de: 6878 ldr r0, [r7, #4] + 80010e0: f7ff ffa2 bl 8001028 + 80010e4: 4603 mov r3, r0 +} + 80010e6: 4618 mov r0, r3 + 80010e8: 3708 adds r7, #8 + 80010ea: 46bd mov sp, r7 + 80010ec: bd80 pop {r7, pc} + ... + +080010f0 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 80010f0: b480 push {r7} + 80010f2: b087 sub sp, #28 + 80010f4: af00 add r7, sp, #0 + 80010f6: 6078 str r0, [r7, #4] + 80010f8: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 80010fa: 2300 movs r3, #0 + 80010fc: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 80010fe: 2300 movs r3, #0 + 8001100: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 8001102: 2300 movs r3, #0 + 8001104: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8001106: e160 b.n 80013ca + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8001108: 683b ldr r3, [r7, #0] + 800110a: 681a ldr r2, [r3, #0] + 800110c: 2101 movs r1, #1 + 800110e: 697b ldr r3, [r7, #20] + 8001110: fa01 f303 lsl.w r3, r1, r3 + 8001114: 4013 ands r3, r2 + 8001116: 60fb str r3, [r7, #12] + + if (iocurrent) + 8001118: 68fb ldr r3, [r7, #12] + 800111a: 2b00 cmp r3, #0 + 800111c: f000 8152 beq.w 80013c4 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8001120: 683b ldr r3, [r7, #0] + 8001122: 685b ldr r3, [r3, #4] + 8001124: f003 0303 and.w r3, r3, #3 + 8001128: 2b01 cmp r3, #1 + 800112a: d005 beq.n 8001138 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 800112c: 683b ldr r3, [r7, #0] + 800112e: 685b ldr r3, [r3, #4] + 8001130: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8001134: 2b02 cmp r3, #2 + 8001136: d130 bne.n 800119a + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001138: 687b ldr r3, [r7, #4] + 800113a: 689b ldr r3, [r3, #8] + 800113c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 800113e: 697b ldr r3, [r7, #20] + 8001140: 005b lsls r3, r3, #1 + 8001142: 2203 movs r2, #3 + 8001144: fa02 f303 lsl.w r3, r2, r3 + 8001148: 43db mvns r3, r3 + 800114a: 693a ldr r2, [r7, #16] + 800114c: 4013 ands r3, r2 + 800114e: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8001150: 683b ldr r3, [r7, #0] + 8001152: 68da ldr r2, [r3, #12] + 8001154: 697b ldr r3, [r7, #20] + 8001156: 005b lsls r3, r3, #1 + 8001158: fa02 f303 lsl.w r3, r2, r3 + 800115c: 693a ldr r2, [r7, #16] + 800115e: 4313 orrs r3, r2 + 8001160: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8001162: 687b ldr r3, [r7, #4] + 8001164: 693a ldr r2, [r7, #16] + 8001166: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8001168: 687b ldr r3, [r7, #4] + 800116a: 685b ldr r3, [r3, #4] + 800116c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 800116e: 2201 movs r2, #1 + 8001170: 697b ldr r3, [r7, #20] + 8001172: fa02 f303 lsl.w r3, r2, r3 + 8001176: 43db mvns r3, r3 + 8001178: 693a ldr r2, [r7, #16] + 800117a: 4013 ands r3, r2 + 800117c: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 800117e: 683b ldr r3, [r7, #0] + 8001180: 685b ldr r3, [r3, #4] + 8001182: 091b lsrs r3, r3, #4 + 8001184: f003 0201 and.w r2, r3, #1 + 8001188: 697b ldr r3, [r7, #20] + 800118a: fa02 f303 lsl.w r3, r2, r3 + 800118e: 693a ldr r2, [r7, #16] + 8001190: 4313 orrs r3, r2 + 8001192: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8001194: 687b ldr r3, [r7, #4] + 8001196: 693a ldr r2, [r7, #16] + 8001198: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 800119a: 683b ldr r3, [r7, #0] + 800119c: 685b ldr r3, [r3, #4] + 800119e: f003 0303 and.w r3, r3, #3 + 80011a2: 2b03 cmp r3, #3 + 80011a4: d017 beq.n 80011d6 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 80011a6: 687b ldr r3, [r7, #4] + 80011a8: 68db ldr r3, [r3, #12] + 80011aa: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 80011ac: 697b ldr r3, [r7, #20] + 80011ae: 005b lsls r3, r3, #1 + 80011b0: 2203 movs r2, #3 + 80011b2: fa02 f303 lsl.w r3, r2, r3 + 80011b6: 43db mvns r3, r3 + 80011b8: 693a ldr r2, [r7, #16] + 80011ba: 4013 ands r3, r2 + 80011bc: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 80011be: 683b ldr r3, [r7, #0] + 80011c0: 689a ldr r2, [r3, #8] + 80011c2: 697b ldr r3, [r7, #20] + 80011c4: 005b lsls r3, r3, #1 + 80011c6: fa02 f303 lsl.w r3, r2, r3 + 80011ca: 693a ldr r2, [r7, #16] + 80011cc: 4313 orrs r3, r2 + 80011ce: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 80011d0: 687b ldr r3, [r7, #4] + 80011d2: 693a ldr r2, [r7, #16] + 80011d4: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 80011d6: 683b ldr r3, [r7, #0] + 80011d8: 685b ldr r3, [r3, #4] + 80011da: f003 0303 and.w r3, r3, #3 + 80011de: 2b02 cmp r3, #2 + 80011e0: d123 bne.n 800122a + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 80011e2: 697b ldr r3, [r7, #20] + 80011e4: 08da lsrs r2, r3, #3 + 80011e6: 687b ldr r3, [r7, #4] + 80011e8: 3208 adds r2, #8 + 80011ea: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80011ee: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 80011f0: 697b ldr r3, [r7, #20] + 80011f2: f003 0307 and.w r3, r3, #7 + 80011f6: 009b lsls r3, r3, #2 + 80011f8: 220f movs r2, #15 + 80011fa: fa02 f303 lsl.w r3, r2, r3 + 80011fe: 43db mvns r3, r3 + 8001200: 693a ldr r2, [r7, #16] + 8001202: 4013 ands r3, r2 + 8001204: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8001206: 683b ldr r3, [r7, #0] + 8001208: 691a ldr r2, [r3, #16] + 800120a: 697b ldr r3, [r7, #20] + 800120c: f003 0307 and.w r3, r3, #7 + 8001210: 009b lsls r3, r3, #2 + 8001212: fa02 f303 lsl.w r3, r2, r3 + 8001216: 693a ldr r2, [r7, #16] + 8001218: 4313 orrs r3, r2 + 800121a: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 800121c: 697b ldr r3, [r7, #20] + 800121e: 08da lsrs r2, r3, #3 + 8001220: 687b ldr r3, [r7, #4] + 8001222: 3208 adds r2, #8 + 8001224: 6939 ldr r1, [r7, #16] + 8001226: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 800122a: 687b ldr r3, [r7, #4] + 800122c: 681b ldr r3, [r3, #0] + 800122e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8001230: 697b ldr r3, [r7, #20] + 8001232: 005b lsls r3, r3, #1 + 8001234: 2203 movs r2, #3 + 8001236: fa02 f303 lsl.w r3, r2, r3 + 800123a: 43db mvns r3, r3 + 800123c: 693a ldr r2, [r7, #16] + 800123e: 4013 ands r3, r2 + 8001240: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8001242: 683b ldr r3, [r7, #0] + 8001244: 685b ldr r3, [r3, #4] + 8001246: f003 0203 and.w r2, r3, #3 + 800124a: 697b ldr r3, [r7, #20] + 800124c: 005b lsls r3, r3, #1 + 800124e: fa02 f303 lsl.w r3, r2, r3 + 8001252: 693a ldr r2, [r7, #16] + 8001254: 4313 orrs r3, r2 + 8001256: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8001258: 687b ldr r3, [r7, #4] + 800125a: 693a ldr r2, [r7, #16] + 800125c: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 800125e: 683b ldr r3, [r7, #0] + 8001260: 685b ldr r3, [r3, #4] + 8001262: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001266: 2b00 cmp r3, #0 + 8001268: f000 80ac beq.w 80013c4 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800126c: 4b5e ldr r3, [pc, #376] @ (80013e8 ) + 800126e: 6a1b ldr r3, [r3, #32] + 8001270: 4a5d ldr r2, [pc, #372] @ (80013e8 ) + 8001272: f043 0301 orr.w r3, r3, #1 + 8001276: 6213 str r3, [r2, #32] + 8001278: 4b5b ldr r3, [pc, #364] @ (80013e8 ) + 800127a: 6a1b ldr r3, [r3, #32] + 800127c: f003 0301 and.w r3, r3, #1 + 8001280: 60bb str r3, [r7, #8] + 8001282: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8001284: 4a59 ldr r2, [pc, #356] @ (80013ec ) + 8001286: 697b ldr r3, [r7, #20] + 8001288: 089b lsrs r3, r3, #2 + 800128a: 3302 adds r3, #2 + 800128c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001290: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 8001292: 697b ldr r3, [r7, #20] + 8001294: f003 0303 and.w r3, r3, #3 + 8001298: 009b lsls r3, r3, #2 + 800129a: 220f movs r2, #15 + 800129c: fa02 f303 lsl.w r3, r2, r3 + 80012a0: 43db mvns r3, r3 + 80012a2: 693a ldr r2, [r7, #16] + 80012a4: 4013 ands r3, r2 + 80012a6: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 80012a8: 687b ldr r3, [r7, #4] + 80012aa: 4a51 ldr r2, [pc, #324] @ (80013f0 ) + 80012ac: 4293 cmp r3, r2 + 80012ae: d025 beq.n 80012fc + 80012b0: 687b ldr r3, [r7, #4] + 80012b2: 4a50 ldr r2, [pc, #320] @ (80013f4 ) + 80012b4: 4293 cmp r3, r2 + 80012b6: d01f beq.n 80012f8 + 80012b8: 687b ldr r3, [r7, #4] + 80012ba: 4a4f ldr r2, [pc, #316] @ (80013f8 ) + 80012bc: 4293 cmp r3, r2 + 80012be: d019 beq.n 80012f4 + 80012c0: 687b ldr r3, [r7, #4] + 80012c2: 4a4e ldr r2, [pc, #312] @ (80013fc ) + 80012c4: 4293 cmp r3, r2 + 80012c6: d013 beq.n 80012f0 + 80012c8: 687b ldr r3, [r7, #4] + 80012ca: 4a4d ldr r2, [pc, #308] @ (8001400 ) + 80012cc: 4293 cmp r3, r2 + 80012ce: d00d beq.n 80012ec + 80012d0: 687b ldr r3, [r7, #4] + 80012d2: 4a4c ldr r2, [pc, #304] @ (8001404 ) + 80012d4: 4293 cmp r3, r2 + 80012d6: d007 beq.n 80012e8 + 80012d8: 687b ldr r3, [r7, #4] + 80012da: 4a4b ldr r2, [pc, #300] @ (8001408 ) + 80012dc: 4293 cmp r3, r2 + 80012de: d101 bne.n 80012e4 + 80012e0: 2306 movs r3, #6 + 80012e2: e00c b.n 80012fe + 80012e4: 2307 movs r3, #7 + 80012e6: e00a b.n 80012fe + 80012e8: 2305 movs r3, #5 + 80012ea: e008 b.n 80012fe + 80012ec: 2304 movs r3, #4 + 80012ee: e006 b.n 80012fe + 80012f0: 2303 movs r3, #3 + 80012f2: e004 b.n 80012fe + 80012f4: 2302 movs r3, #2 + 80012f6: e002 b.n 80012fe + 80012f8: 2301 movs r3, #1 + 80012fa: e000 b.n 80012fe + 80012fc: 2300 movs r3, #0 + 80012fe: 697a ldr r2, [r7, #20] + 8001300: f002 0203 and.w r2, r2, #3 + 8001304: 0092 lsls r2, r2, #2 + 8001306: 4093 lsls r3, r2 + 8001308: 693a ldr r2, [r7, #16] + 800130a: 4313 orrs r3, r2 + 800130c: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 800130e: 4937 ldr r1, [pc, #220] @ (80013ec ) + 8001310: 697b ldr r3, [r7, #20] + 8001312: 089b lsrs r3, r3, #2 + 8001314: 3302 adds r3, #2 + 8001316: 693a ldr r2, [r7, #16] + 8001318: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 800131c: 4b3b ldr r3, [pc, #236] @ (800140c ) + 800131e: 689b ldr r3, [r3, #8] + 8001320: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001322: 68fb ldr r3, [r7, #12] + 8001324: 43db mvns r3, r3 + 8001326: 693a ldr r2, [r7, #16] + 8001328: 4013 ands r3, r2 + 800132a: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 800132c: 683b ldr r3, [r7, #0] + 800132e: 685b ldr r3, [r3, #4] + 8001330: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001334: 2b00 cmp r3, #0 + 8001336: d003 beq.n 8001340 + { + SET_BIT(temp, iocurrent); + 8001338: 693a ldr r2, [r7, #16] + 800133a: 68fb ldr r3, [r7, #12] + 800133c: 4313 orrs r3, r2 + 800133e: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 8001340: 4a32 ldr r2, [pc, #200] @ (800140c ) + 8001342: 693b ldr r3, [r7, #16] + 8001344: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8001346: 4b31 ldr r3, [pc, #196] @ (800140c ) + 8001348: 68db ldr r3, [r3, #12] + 800134a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 800134c: 68fb ldr r3, [r7, #12] + 800134e: 43db mvns r3, r3 + 8001350: 693a ldr r2, [r7, #16] + 8001352: 4013 ands r3, r2 + 8001354: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8001356: 683b ldr r3, [r7, #0] + 8001358: 685b ldr r3, [r3, #4] + 800135a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800135e: 2b00 cmp r3, #0 + 8001360: d003 beq.n 800136a + { + SET_BIT(temp, iocurrent); + 8001362: 693a ldr r2, [r7, #16] + 8001364: 68fb ldr r3, [r7, #12] + 8001366: 4313 orrs r3, r2 + 8001368: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 800136a: 4a28 ldr r2, [pc, #160] @ (800140c ) + 800136c: 693b ldr r3, [r7, #16] + 800136e: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8001370: 4b26 ldr r3, [pc, #152] @ (800140c ) + 8001372: 685b ldr r3, [r3, #4] + 8001374: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001376: 68fb ldr r3, [r7, #12] + 8001378: 43db mvns r3, r3 + 800137a: 693a ldr r2, [r7, #16] + 800137c: 4013 ands r3, r2 + 800137e: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8001380: 683b ldr r3, [r7, #0] + 8001382: 685b ldr r3, [r3, #4] + 8001384: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001388: 2b00 cmp r3, #0 + 800138a: d003 beq.n 8001394 + { + SET_BIT(temp, iocurrent); + 800138c: 693a ldr r2, [r7, #16] + 800138e: 68fb ldr r3, [r7, #12] + 8001390: 4313 orrs r3, r2 + 8001392: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8001394: 4a1d ldr r2, [pc, #116] @ (800140c ) + 8001396: 693b ldr r3, [r7, #16] + 8001398: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 800139a: 4b1c ldr r3, [pc, #112] @ (800140c ) + 800139c: 681b ldr r3, [r3, #0] + 800139e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 80013a0: 68fb ldr r3, [r7, #12] + 80013a2: 43db mvns r3, r3 + 80013a4: 693a ldr r2, [r7, #16] + 80013a6: 4013 ands r3, r2 + 80013a8: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 80013aa: 683b ldr r3, [r7, #0] + 80013ac: 685b ldr r3, [r3, #4] + 80013ae: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80013b2: 2b00 cmp r3, #0 + 80013b4: d003 beq.n 80013be + { + SET_BIT(temp, iocurrent); + 80013b6: 693a ldr r2, [r7, #16] + 80013b8: 68fb ldr r3, [r7, #12] + 80013ba: 4313 orrs r3, r2 + 80013bc: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 80013be: 4a13 ldr r2, [pc, #76] @ (800140c ) + 80013c0: 693b ldr r3, [r7, #16] + 80013c2: 6013 str r3, [r2, #0] + } + } + + position++; + 80013c4: 697b ldr r3, [r7, #20] + 80013c6: 3301 adds r3, #1 + 80013c8: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 80013ca: 683b ldr r3, [r7, #0] + 80013cc: 681a ldr r2, [r3, #0] + 80013ce: 697b ldr r3, [r7, #20] + 80013d0: fa22 f303 lsr.w r3, r2, r3 + 80013d4: 2b00 cmp r3, #0 + 80013d6: f47f ae97 bne.w 8001108 + } +} + 80013da: bf00 nop + 80013dc: bf00 nop + 80013de: 371c adds r7, #28 + 80013e0: 46bd mov sp, r7 + 80013e2: bc80 pop {r7} + 80013e4: 4770 bx lr + 80013e6: bf00 nop + 80013e8: 40023800 .word 0x40023800 + 80013ec: 40010000 .word 0x40010000 + 80013f0: 40020000 .word 0x40020000 + 80013f4: 40020400 .word 0x40020400 + 80013f8: 40020800 .word 0x40020800 + 80013fc: 40020c00 .word 0x40020c00 + 8001400: 40021000 .word 0x40021000 + 8001404: 40021400 .word 0x40021400 + 8001408: 40021800 .word 0x40021800 + 800140c: 40010400 .word 0x40010400 + +08001410 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8001410: b480 push {r7} + 8001412: b083 sub sp, #12 + 8001414: af00 add r7, sp, #0 + 8001416: 6078 str r0, [r7, #4] + 8001418: 460b mov r3, r1 + 800141a: 807b strh r3, [r7, #2] + 800141c: 4613 mov r3, r2 + 800141e: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8001420: 787b ldrb r3, [r7, #1] + 8001422: 2b00 cmp r3, #0 + 8001424: d003 beq.n 800142e + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8001426: 887a ldrh r2, [r7, #2] + 8001428: 687b ldr r3, [r7, #4] + 800142a: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 800142c: e003 b.n 8001436 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 800142e: 887b ldrh r3, [r7, #2] + 8001430: 041a lsls r2, r3, #16 + 8001432: 687b ldr r3, [r7, #4] + 8001434: 619a str r2, [r3, #24] +} + 8001436: bf00 nop + 8001438: 370c adds r7, #12 + 800143a: 46bd mov sp, r7 + 800143c: bc80 pop {r7} + 800143e: 4770 bx lr + +08001440 : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 8001440: b580 push {r7, lr} + 8001442: b082 sub sp, #8 + 8001444: af00 add r7, sp, #0 + 8001446: 4603 mov r3, r0 + 8001448: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 800144a: 4b08 ldr r3, [pc, #32] @ (800146c ) + 800144c: 695a ldr r2, [r3, #20] + 800144e: 88fb ldrh r3, [r7, #6] + 8001450: 4013 ands r3, r2 + 8001452: 2b00 cmp r3, #0 + 8001454: d006 beq.n 8001464 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 8001456: 4a05 ldr r2, [pc, #20] @ (800146c ) + 8001458: 88fb ldrh r3, [r7, #6] + 800145a: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 800145c: 88fb ldrh r3, [r7, #6] + 800145e: 4618 mov r0, r3 + 8001460: f000 f806 bl 8001470 + } +} + 8001464: bf00 nop + 8001466: 3708 adds r7, #8 + 8001468: 46bd mov sp, r7 + 800146a: bd80 pop {r7, pc} + 800146c: 40010400 .word 0x40010400 + +08001470 : + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 8001470: b480 push {r7} + 8001472: b083 sub sp, #12 + 8001474: af00 add r7, sp, #0 + 8001476: 4603 mov r3, r0 + 8001478: 80fb strh r3, [r7, #6] + UNUSED(GPIO_Pin); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + 800147a: bf00 nop + 800147c: 370c adds r7, #12 + 800147e: 46bd mov sp, r7 + 8001480: bc80 pop {r7} + 8001482: 4770 bx lr + +08001484 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8001484: b580 push {r7, lr} + 8001486: b088 sub sp, #32 + 8001488: af00 add r7, sp, #0 + 800148a: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 800148c: 687b ldr r3, [r7, #4] + 800148e: 2b00 cmp r3, #0 + 8001490: d101 bne.n 8001496 + { + return HAL_ERROR; + 8001492: 2301 movs r3, #1 + 8001494: e31d b.n 8001ad2 + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8001496: 4b94 ldr r3, [pc, #592] @ (80016e8 ) + 8001498: 689b ldr r3, [r3, #8] + 800149a: f003 030c and.w r3, r3, #12 + 800149e: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80014a0: 4b91 ldr r3, [pc, #580] @ (80016e8 ) + 80014a2: 689b ldr r3, [r3, #8] + 80014a4: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80014a8: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80014aa: 687b ldr r3, [r7, #4] + 80014ac: 681b ldr r3, [r3, #0] + 80014ae: f003 0301 and.w r3, r3, #1 + 80014b2: 2b00 cmp r3, #0 + 80014b4: d07b beq.n 80015ae + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 80014b6: 69bb ldr r3, [r7, #24] + 80014b8: 2b08 cmp r3, #8 + 80014ba: d006 beq.n 80014ca + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 80014bc: 69bb ldr r3, [r7, #24] + 80014be: 2b0c cmp r3, #12 + 80014c0: d10f bne.n 80014e2 + 80014c2: 697b ldr r3, [r7, #20] + 80014c4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80014c8: d10b bne.n 80014e2 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80014ca: 4b87 ldr r3, [pc, #540] @ (80016e8 ) + 80014cc: 681b ldr r3, [r3, #0] + 80014ce: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80014d2: 2b00 cmp r3, #0 + 80014d4: d06a beq.n 80015ac + 80014d6: 687b ldr r3, [r7, #4] + 80014d8: 685b ldr r3, [r3, #4] + 80014da: 2b00 cmp r3, #0 + 80014dc: d166 bne.n 80015ac + { + return HAL_ERROR; + 80014de: 2301 movs r3, #1 + 80014e0: e2f7 b.n 8001ad2 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80014e2: 687b ldr r3, [r7, #4] + 80014e4: 685b ldr r3, [r3, #4] + 80014e6: 2b01 cmp r3, #1 + 80014e8: d106 bne.n 80014f8 + 80014ea: 4b7f ldr r3, [pc, #508] @ (80016e8 ) + 80014ec: 681b ldr r3, [r3, #0] + 80014ee: 4a7e ldr r2, [pc, #504] @ (80016e8 ) + 80014f0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80014f4: 6013 str r3, [r2, #0] + 80014f6: e02d b.n 8001554 + 80014f8: 687b ldr r3, [r7, #4] + 80014fa: 685b ldr r3, [r3, #4] + 80014fc: 2b00 cmp r3, #0 + 80014fe: d10c bne.n 800151a + 8001500: 4b79 ldr r3, [pc, #484] @ (80016e8 ) + 8001502: 681b ldr r3, [r3, #0] + 8001504: 4a78 ldr r2, [pc, #480] @ (80016e8 ) + 8001506: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800150a: 6013 str r3, [r2, #0] + 800150c: 4b76 ldr r3, [pc, #472] @ (80016e8 ) + 800150e: 681b ldr r3, [r3, #0] + 8001510: 4a75 ldr r2, [pc, #468] @ (80016e8 ) + 8001512: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001516: 6013 str r3, [r2, #0] + 8001518: e01c b.n 8001554 + 800151a: 687b ldr r3, [r7, #4] + 800151c: 685b ldr r3, [r3, #4] + 800151e: 2b05 cmp r3, #5 + 8001520: d10c bne.n 800153c + 8001522: 4b71 ldr r3, [pc, #452] @ (80016e8 ) + 8001524: 681b ldr r3, [r3, #0] + 8001526: 4a70 ldr r2, [pc, #448] @ (80016e8 ) + 8001528: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 800152c: 6013 str r3, [r2, #0] + 800152e: 4b6e ldr r3, [pc, #440] @ (80016e8 ) + 8001530: 681b ldr r3, [r3, #0] + 8001532: 4a6d ldr r2, [pc, #436] @ (80016e8 ) + 8001534: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001538: 6013 str r3, [r2, #0] + 800153a: e00b b.n 8001554 + 800153c: 4b6a ldr r3, [pc, #424] @ (80016e8 ) + 800153e: 681b ldr r3, [r3, #0] + 8001540: 4a69 ldr r2, [pc, #420] @ (80016e8 ) + 8001542: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001546: 6013 str r3, [r2, #0] + 8001548: 4b67 ldr r3, [pc, #412] @ (80016e8 ) + 800154a: 681b ldr r3, [r3, #0] + 800154c: 4a66 ldr r2, [pc, #408] @ (80016e8 ) + 800154e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001552: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8001554: 687b ldr r3, [r7, #4] + 8001556: 685b ldr r3, [r3, #4] + 8001558: 2b00 cmp r3, #0 + 800155a: d013 beq.n 8001584 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800155c: f7ff fcb0 bl 8000ec0 + 8001560: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001562: e008 b.n 8001576 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001564: f7ff fcac bl 8000ec0 + 8001568: 4602 mov r2, r0 + 800156a: 693b ldr r3, [r7, #16] + 800156c: 1ad3 subs r3, r2, r3 + 800156e: 2b64 cmp r3, #100 @ 0x64 + 8001570: d901 bls.n 8001576 + { + return HAL_TIMEOUT; + 8001572: 2303 movs r3, #3 + 8001574: e2ad b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001576: 4b5c ldr r3, [pc, #368] @ (80016e8 ) + 8001578: 681b ldr r3, [r3, #0] + 800157a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800157e: 2b00 cmp r3, #0 + 8001580: d0f0 beq.n 8001564 + 8001582: e014 b.n 80015ae + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001584: f7ff fc9c bl 8000ec0 + 8001588: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 800158a: e008 b.n 800159e + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 800158c: f7ff fc98 bl 8000ec0 + 8001590: 4602 mov r2, r0 + 8001592: 693b ldr r3, [r7, #16] + 8001594: 1ad3 subs r3, r2, r3 + 8001596: 2b64 cmp r3, #100 @ 0x64 + 8001598: d901 bls.n 800159e + { + return HAL_TIMEOUT; + 800159a: 2303 movs r3, #3 + 800159c: e299 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 800159e: 4b52 ldr r3, [pc, #328] @ (80016e8 ) + 80015a0: 681b ldr r3, [r3, #0] + 80015a2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80015a6: 2b00 cmp r3, #0 + 80015a8: d1f0 bne.n 800158c + 80015aa: e000 b.n 80015ae + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80015ac: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80015ae: 687b ldr r3, [r7, #4] + 80015b0: 681b ldr r3, [r3, #0] + 80015b2: f003 0302 and.w r3, r3, #2 + 80015b6: 2b00 cmp r3, #0 + 80015b8: d05a beq.n 8001670 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 80015ba: 69bb ldr r3, [r7, #24] + 80015bc: 2b04 cmp r3, #4 + 80015be: d005 beq.n 80015cc + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 80015c0: 69bb ldr r3, [r7, #24] + 80015c2: 2b0c cmp r3, #12 + 80015c4: d119 bne.n 80015fa + 80015c6: 697b ldr r3, [r7, #20] + 80015c8: 2b00 cmp r3, #0 + 80015ca: d116 bne.n 80015fa + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80015cc: 4b46 ldr r3, [pc, #280] @ (80016e8 ) + 80015ce: 681b ldr r3, [r3, #0] + 80015d0: f003 0302 and.w r3, r3, #2 + 80015d4: 2b00 cmp r3, #0 + 80015d6: d005 beq.n 80015e4 + 80015d8: 687b ldr r3, [r7, #4] + 80015da: 68db ldr r3, [r3, #12] + 80015dc: 2b01 cmp r3, #1 + 80015de: d001 beq.n 80015e4 + { + return HAL_ERROR; + 80015e0: 2301 movs r3, #1 + 80015e2: e276 b.n 8001ad2 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80015e4: 4b40 ldr r3, [pc, #256] @ (80016e8 ) + 80015e6: 685b ldr r3, [r3, #4] + 80015e8: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 80015ec: 687b ldr r3, [r7, #4] + 80015ee: 691b ldr r3, [r3, #16] + 80015f0: 021b lsls r3, r3, #8 + 80015f2: 493d ldr r1, [pc, #244] @ (80016e8 ) + 80015f4: 4313 orrs r3, r2 + 80015f6: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80015f8: e03a b.n 8001670 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 80015fa: 687b ldr r3, [r7, #4] + 80015fc: 68db ldr r3, [r3, #12] + 80015fe: 2b00 cmp r3, #0 + 8001600: d020 beq.n 8001644 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8001602: 4b3a ldr r3, [pc, #232] @ (80016ec ) + 8001604: 2201 movs r2, #1 + 8001606: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001608: f7ff fc5a bl 8000ec0 + 800160c: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800160e: e008 b.n 8001622 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001610: f7ff fc56 bl 8000ec0 + 8001614: 4602 mov r2, r0 + 8001616: 693b ldr r3, [r7, #16] + 8001618: 1ad3 subs r3, r2, r3 + 800161a: 2b02 cmp r3, #2 + 800161c: d901 bls.n 8001622 + { + return HAL_TIMEOUT; + 800161e: 2303 movs r3, #3 + 8001620: e257 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001622: 4b31 ldr r3, [pc, #196] @ (80016e8 ) + 8001624: 681b ldr r3, [r3, #0] + 8001626: f003 0302 and.w r3, r3, #2 + 800162a: 2b00 cmp r3, #0 + 800162c: d0f0 beq.n 8001610 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800162e: 4b2e ldr r3, [pc, #184] @ (80016e8 ) + 8001630: 685b ldr r3, [r3, #4] + 8001632: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001636: 687b ldr r3, [r7, #4] + 8001638: 691b ldr r3, [r3, #16] + 800163a: 021b lsls r3, r3, #8 + 800163c: 492a ldr r1, [pc, #168] @ (80016e8 ) + 800163e: 4313 orrs r3, r2 + 8001640: 604b str r3, [r1, #4] + 8001642: e015 b.n 8001670 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8001644: 4b29 ldr r3, [pc, #164] @ (80016ec ) + 8001646: 2200 movs r2, #0 + 8001648: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800164a: f7ff fc39 bl 8000ec0 + 800164e: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001650: e008 b.n 8001664 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001652: f7ff fc35 bl 8000ec0 + 8001656: 4602 mov r2, r0 + 8001658: 693b ldr r3, [r7, #16] + 800165a: 1ad3 subs r3, r2, r3 + 800165c: 2b02 cmp r3, #2 + 800165e: d901 bls.n 8001664 + { + return HAL_TIMEOUT; + 8001660: 2303 movs r3, #3 + 8001662: e236 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001664: 4b20 ldr r3, [pc, #128] @ (80016e8 ) + 8001666: 681b ldr r3, [r3, #0] + 8001668: f003 0302 and.w r3, r3, #2 + 800166c: 2b00 cmp r3, #0 + 800166e: d1f0 bne.n 8001652 + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8001670: 687b ldr r3, [r7, #4] + 8001672: 681b ldr r3, [r3, #0] + 8001674: f003 0310 and.w r3, r3, #16 + 8001678: 2b00 cmp r3, #0 + 800167a: f000 80b8 beq.w 80017ee + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 800167e: 69bb ldr r3, [r7, #24] + 8001680: 2b00 cmp r3, #0 + 8001682: d170 bne.n 8001766 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8001684: 4b18 ldr r3, [pc, #96] @ (80016e8 ) + 8001686: 681b ldr r3, [r3, #0] + 8001688: f403 7300 and.w r3, r3, #512 @ 0x200 + 800168c: 2b00 cmp r3, #0 + 800168e: d005 beq.n 800169c + 8001690: 687b ldr r3, [r7, #4] + 8001692: 699b ldr r3, [r3, #24] + 8001694: 2b00 cmp r3, #0 + 8001696: d101 bne.n 800169c + { + return HAL_ERROR; + 8001698: 2301 movs r3, #1 + 800169a: e21a b.n 8001ad2 + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 800169c: 687b ldr r3, [r7, #4] + 800169e: 6a1a ldr r2, [r3, #32] + 80016a0: 4b11 ldr r3, [pc, #68] @ (80016e8 ) + 80016a2: 685b ldr r3, [r3, #4] + 80016a4: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 80016a8: 429a cmp r2, r3 + 80016aa: d921 bls.n 80016f0 + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80016ac: 687b ldr r3, [r7, #4] + 80016ae: 6a1b ldr r3, [r3, #32] + 80016b0: 4618 mov r0, r3 + 80016b2: f000 fc09 bl 8001ec8 + 80016b6: 4603 mov r3, r0 + 80016b8: 2b00 cmp r3, #0 + 80016ba: d001 beq.n 80016c0 + { + return HAL_ERROR; + 80016bc: 2301 movs r3, #1 + 80016be: e208 b.n 8001ad2 + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80016c0: 4b09 ldr r3, [pc, #36] @ (80016e8 ) + 80016c2: 685b ldr r3, [r3, #4] + 80016c4: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80016c8: 687b ldr r3, [r7, #4] + 80016ca: 6a1b ldr r3, [r3, #32] + 80016cc: 4906 ldr r1, [pc, #24] @ (80016e8 ) + 80016ce: 4313 orrs r3, r2 + 80016d0: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80016d2: 4b05 ldr r3, [pc, #20] @ (80016e8 ) + 80016d4: 685b ldr r3, [r3, #4] + 80016d6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80016da: 687b ldr r3, [r7, #4] + 80016dc: 69db ldr r3, [r3, #28] + 80016de: 061b lsls r3, r3, #24 + 80016e0: 4901 ldr r1, [pc, #4] @ (80016e8 ) + 80016e2: 4313 orrs r3, r2 + 80016e4: 604b str r3, [r1, #4] + 80016e6: e020 b.n 800172a + 80016e8: 40023800 .word 0x40023800 + 80016ec: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80016f0: 4b99 ldr r3, [pc, #612] @ (8001958 ) + 80016f2: 685b ldr r3, [r3, #4] + 80016f4: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80016f8: 687b ldr r3, [r7, #4] + 80016fa: 6a1b ldr r3, [r3, #32] + 80016fc: 4996 ldr r1, [pc, #600] @ (8001958 ) + 80016fe: 4313 orrs r3, r2 + 8001700: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001702: 4b95 ldr r3, [pc, #596] @ (8001958 ) + 8001704: 685b ldr r3, [r3, #4] + 8001706: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 800170a: 687b ldr r3, [r7, #4] + 800170c: 69db ldr r3, [r3, #28] + 800170e: 061b lsls r3, r3, #24 + 8001710: 4991 ldr r1, [pc, #580] @ (8001958 ) + 8001712: 4313 orrs r3, r2 + 8001714: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001716: 687b ldr r3, [r7, #4] + 8001718: 6a1b ldr r3, [r3, #32] + 800171a: 4618 mov r0, r3 + 800171c: f000 fbd4 bl 8001ec8 + 8001720: 4603 mov r3, r0 + 8001722: 2b00 cmp r3, #0 + 8001724: d001 beq.n 800172a + { + return HAL_ERROR; + 8001726: 2301 movs r3, #1 + 8001728: e1d3 b.n 8001ad2 + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 800172a: 687b ldr r3, [r7, #4] + 800172c: 6a1b ldr r3, [r3, #32] + 800172e: 0b5b lsrs r3, r3, #13 + 8001730: 3301 adds r3, #1 + 8001732: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001736: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 800173a: 4a87 ldr r2, [pc, #540] @ (8001958 ) + 800173c: 6892 ldr r2, [r2, #8] + 800173e: 0912 lsrs r2, r2, #4 + 8001740: f002 020f and.w r2, r2, #15 + 8001744: 4985 ldr r1, [pc, #532] @ (800195c ) + 8001746: 5c8a ldrb r2, [r1, r2] + 8001748: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 800174a: 4a85 ldr r2, [pc, #532] @ (8001960 ) + 800174c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 800174e: 4b85 ldr r3, [pc, #532] @ (8001964 ) + 8001750: 681b ldr r3, [r3, #0] + 8001752: 4618 mov r0, r3 + 8001754: f7ff fb68 bl 8000e28 + 8001758: 4603 mov r3, r0 + 800175a: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 800175c: 7bfb ldrb r3, [r7, #15] + 800175e: 2b00 cmp r3, #0 + 8001760: d045 beq.n 80017ee + { + return status; + 8001762: 7bfb ldrb r3, [r7, #15] + 8001764: e1b5 b.n 8001ad2 + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8001766: 687b ldr r3, [r7, #4] + 8001768: 699b ldr r3, [r3, #24] + 800176a: 2b00 cmp r3, #0 + 800176c: d029 beq.n 80017c2 + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 800176e: 4b7e ldr r3, [pc, #504] @ (8001968 ) + 8001770: 2201 movs r2, #1 + 8001772: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001774: f7ff fba4 bl 8000ec0 + 8001778: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800177a: e008 b.n 800178e + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 800177c: f7ff fba0 bl 8000ec0 + 8001780: 4602 mov r2, r0 + 8001782: 693b ldr r3, [r7, #16] + 8001784: 1ad3 subs r3, r2, r3 + 8001786: 2b02 cmp r3, #2 + 8001788: d901 bls.n 800178e + { + return HAL_TIMEOUT; + 800178a: 2303 movs r3, #3 + 800178c: e1a1 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800178e: 4b72 ldr r3, [pc, #456] @ (8001958 ) + 8001790: 681b ldr r3, [r3, #0] + 8001792: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001796: 2b00 cmp r3, #0 + 8001798: d0f0 beq.n 800177c + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800179a: 4b6f ldr r3, [pc, #444] @ (8001958 ) + 800179c: 685b ldr r3, [r3, #4] + 800179e: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80017a2: 687b ldr r3, [r7, #4] + 80017a4: 6a1b ldr r3, [r3, #32] + 80017a6: 496c ldr r1, [pc, #432] @ (8001958 ) + 80017a8: 4313 orrs r3, r2 + 80017aa: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80017ac: 4b6a ldr r3, [pc, #424] @ (8001958 ) + 80017ae: 685b ldr r3, [r3, #4] + 80017b0: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80017b4: 687b ldr r3, [r7, #4] + 80017b6: 69db ldr r3, [r3, #28] + 80017b8: 061b lsls r3, r3, #24 + 80017ba: 4967 ldr r1, [pc, #412] @ (8001958 ) + 80017bc: 4313 orrs r3, r2 + 80017be: 604b str r3, [r1, #4] + 80017c0: e015 b.n 80017ee + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 80017c2: 4b69 ldr r3, [pc, #420] @ (8001968 ) + 80017c4: 2200 movs r2, #0 + 80017c6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80017c8: f7ff fb7a bl 8000ec0 + 80017cc: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80017ce: e008 b.n 80017e2 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80017d0: f7ff fb76 bl 8000ec0 + 80017d4: 4602 mov r2, r0 + 80017d6: 693b ldr r3, [r7, #16] + 80017d8: 1ad3 subs r3, r2, r3 + 80017da: 2b02 cmp r3, #2 + 80017dc: d901 bls.n 80017e2 + { + return HAL_TIMEOUT; + 80017de: 2303 movs r3, #3 + 80017e0: e177 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80017e2: 4b5d ldr r3, [pc, #372] @ (8001958 ) + 80017e4: 681b ldr r3, [r3, #0] + 80017e6: f403 7300 and.w r3, r3, #512 @ 0x200 + 80017ea: 2b00 cmp r3, #0 + 80017ec: d1f0 bne.n 80017d0 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80017ee: 687b ldr r3, [r7, #4] + 80017f0: 681b ldr r3, [r3, #0] + 80017f2: f003 0308 and.w r3, r3, #8 + 80017f6: 2b00 cmp r3, #0 + 80017f8: d030 beq.n 800185c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 80017fa: 687b ldr r3, [r7, #4] + 80017fc: 695b ldr r3, [r3, #20] + 80017fe: 2b00 cmp r3, #0 + 8001800: d016 beq.n 8001830 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8001802: 4b5a ldr r3, [pc, #360] @ (800196c ) + 8001804: 2201 movs r2, #1 + 8001806: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001808: f7ff fb5a bl 8000ec0 + 800180c: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800180e: e008 b.n 8001822 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001810: f7ff fb56 bl 8000ec0 + 8001814: 4602 mov r2, r0 + 8001816: 693b ldr r3, [r7, #16] + 8001818: 1ad3 subs r3, r2, r3 + 800181a: 2b02 cmp r3, #2 + 800181c: d901 bls.n 8001822 + { + return HAL_TIMEOUT; + 800181e: 2303 movs r3, #3 + 8001820: e157 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8001822: 4b4d ldr r3, [pc, #308] @ (8001958 ) + 8001824: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001826: f003 0302 and.w r3, r3, #2 + 800182a: 2b00 cmp r3, #0 + 800182c: d0f0 beq.n 8001810 + 800182e: e015 b.n 800185c + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001830: 4b4e ldr r3, [pc, #312] @ (800196c ) + 8001832: 2200 movs r2, #0 + 8001834: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001836: f7ff fb43 bl 8000ec0 + 800183a: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 800183c: e008 b.n 8001850 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800183e: f7ff fb3f bl 8000ec0 + 8001842: 4602 mov r2, r0 + 8001844: 693b ldr r3, [r7, #16] + 8001846: 1ad3 subs r3, r2, r3 + 8001848: 2b02 cmp r3, #2 + 800184a: d901 bls.n 8001850 + { + return HAL_TIMEOUT; + 800184c: 2303 movs r3, #3 + 800184e: e140 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001850: 4b41 ldr r3, [pc, #260] @ (8001958 ) + 8001852: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001854: f003 0302 and.w r3, r3, #2 + 8001858: 2b00 cmp r3, #0 + 800185a: d1f0 bne.n 800183e + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800185c: 687b ldr r3, [r7, #4] + 800185e: 681b ldr r3, [r3, #0] + 8001860: f003 0304 and.w r3, r3, #4 + 8001864: 2b00 cmp r3, #0 + 8001866: f000 80b5 beq.w 80019d4 + { + FlagStatus pwrclkchanged = RESET; + 800186a: 2300 movs r3, #0 + 800186c: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800186e: 4b3a ldr r3, [pc, #232] @ (8001958 ) + 8001870: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001872: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001876: 2b00 cmp r3, #0 + 8001878: d10d bne.n 8001896 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 800187a: 4b37 ldr r3, [pc, #220] @ (8001958 ) + 800187c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800187e: 4a36 ldr r2, [pc, #216] @ (8001958 ) + 8001880: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001884: 6253 str r3, [r2, #36] @ 0x24 + 8001886: 4b34 ldr r3, [pc, #208] @ (8001958 ) + 8001888: 6a5b ldr r3, [r3, #36] @ 0x24 + 800188a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800188e: 60bb str r3, [r7, #8] + 8001890: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8001892: 2301 movs r3, #1 + 8001894: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001896: 4b36 ldr r3, [pc, #216] @ (8001970 ) + 8001898: 681b ldr r3, [r3, #0] + 800189a: f403 7380 and.w r3, r3, #256 @ 0x100 + 800189e: 2b00 cmp r3, #0 + 80018a0: d118 bne.n 80018d4 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80018a2: 4b33 ldr r3, [pc, #204] @ (8001970 ) + 80018a4: 681b ldr r3, [r3, #0] + 80018a6: 4a32 ldr r2, [pc, #200] @ (8001970 ) + 80018a8: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80018ac: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80018ae: f7ff fb07 bl 8000ec0 + 80018b2: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80018b4: e008 b.n 80018c8 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80018b6: f7ff fb03 bl 8000ec0 + 80018ba: 4602 mov r2, r0 + 80018bc: 693b ldr r3, [r7, #16] + 80018be: 1ad3 subs r3, r2, r3 + 80018c0: 2b64 cmp r3, #100 @ 0x64 + 80018c2: d901 bls.n 80018c8 + { + return HAL_TIMEOUT; + 80018c4: 2303 movs r3, #3 + 80018c6: e104 b.n 8001ad2 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80018c8: 4b29 ldr r3, [pc, #164] @ (8001970 ) + 80018ca: 681b ldr r3, [r3, #0] + 80018cc: f403 7380 and.w r3, r3, #256 @ 0x100 + 80018d0: 2b00 cmp r3, #0 + 80018d2: d0f0 beq.n 80018b6 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80018d4: 687b ldr r3, [r7, #4] + 80018d6: 689b ldr r3, [r3, #8] + 80018d8: 2b01 cmp r3, #1 + 80018da: d106 bne.n 80018ea + 80018dc: 4b1e ldr r3, [pc, #120] @ (8001958 ) + 80018de: 6b5b ldr r3, [r3, #52] @ 0x34 + 80018e0: 4a1d ldr r2, [pc, #116] @ (8001958 ) + 80018e2: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80018e6: 6353 str r3, [r2, #52] @ 0x34 + 80018e8: e02d b.n 8001946 + 80018ea: 687b ldr r3, [r7, #4] + 80018ec: 689b ldr r3, [r3, #8] + 80018ee: 2b00 cmp r3, #0 + 80018f0: d10c bne.n 800190c + 80018f2: 4b19 ldr r3, [pc, #100] @ (8001958 ) + 80018f4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80018f6: 4a18 ldr r2, [pc, #96] @ (8001958 ) + 80018f8: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80018fc: 6353 str r3, [r2, #52] @ 0x34 + 80018fe: 4b16 ldr r3, [pc, #88] @ (8001958 ) + 8001900: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001902: 4a15 ldr r2, [pc, #84] @ (8001958 ) + 8001904: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001908: 6353 str r3, [r2, #52] @ 0x34 + 800190a: e01c b.n 8001946 + 800190c: 687b ldr r3, [r7, #4] + 800190e: 689b ldr r3, [r3, #8] + 8001910: 2b05 cmp r3, #5 + 8001912: d10c bne.n 800192e + 8001914: 4b10 ldr r3, [pc, #64] @ (8001958 ) + 8001916: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001918: 4a0f ldr r2, [pc, #60] @ (8001958 ) + 800191a: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 800191e: 6353 str r3, [r2, #52] @ 0x34 + 8001920: 4b0d ldr r3, [pc, #52] @ (8001958 ) + 8001922: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001924: 4a0c ldr r2, [pc, #48] @ (8001958 ) + 8001926: f443 7380 orr.w r3, r3, #256 @ 0x100 + 800192a: 6353 str r3, [r2, #52] @ 0x34 + 800192c: e00b b.n 8001946 + 800192e: 4b0a ldr r3, [pc, #40] @ (8001958 ) + 8001930: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001932: 4a09 ldr r2, [pc, #36] @ (8001958 ) + 8001934: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001938: 6353 str r3, [r2, #52] @ 0x34 + 800193a: 4b07 ldr r3, [pc, #28] @ (8001958 ) + 800193c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800193e: 4a06 ldr r2, [pc, #24] @ (8001958 ) + 8001940: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001944: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8001946: 687b ldr r3, [r7, #4] + 8001948: 689b ldr r3, [r3, #8] + 800194a: 2b00 cmp r3, #0 + 800194c: d024 beq.n 8001998 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800194e: f7ff fab7 bl 8000ec0 + 8001952: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001954: e019 b.n 800198a + 8001956: bf00 nop + 8001958: 40023800 .word 0x40023800 + 800195c: 08003234 .word 0x08003234 + 8001960: 20000004 .word 0x20000004 + 8001964: 20000008 .word 0x20000008 + 8001968: 42470020 .word 0x42470020 + 800196c: 42470680 .word 0x42470680 + 8001970: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001974: f7ff faa4 bl 8000ec0 + 8001978: 4602 mov r2, r0 + 800197a: 693b ldr r3, [r7, #16] + 800197c: 1ad3 subs r3, r2, r3 + 800197e: f241 3288 movw r2, #5000 @ 0x1388 + 8001982: 4293 cmp r3, r2 + 8001984: d901 bls.n 800198a + { + return HAL_TIMEOUT; + 8001986: 2303 movs r3, #3 + 8001988: e0a3 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800198a: 4b54 ldr r3, [pc, #336] @ (8001adc ) + 800198c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800198e: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001992: 2b00 cmp r3, #0 + 8001994: d0ee beq.n 8001974 + 8001996: e014 b.n 80019c2 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001998: f7ff fa92 bl 8000ec0 + 800199c: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 800199e: e00a b.n 80019b6 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80019a0: f7ff fa8e bl 8000ec0 + 80019a4: 4602 mov r2, r0 + 80019a6: 693b ldr r3, [r7, #16] + 80019a8: 1ad3 subs r3, r2, r3 + 80019aa: f241 3288 movw r2, #5000 @ 0x1388 + 80019ae: 4293 cmp r3, r2 + 80019b0: d901 bls.n 80019b6 + { + return HAL_TIMEOUT; + 80019b2: 2303 movs r3, #3 + 80019b4: e08d b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80019b6: 4b49 ldr r3, [pc, #292] @ (8001adc ) + 80019b8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80019ba: f403 7300 and.w r3, r3, #512 @ 0x200 + 80019be: 2b00 cmp r3, #0 + 80019c0: d1ee bne.n 80019a0 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 80019c2: 7ffb ldrb r3, [r7, #31] + 80019c4: 2b01 cmp r3, #1 + 80019c6: d105 bne.n 80019d4 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80019c8: 4b44 ldr r3, [pc, #272] @ (8001adc ) + 80019ca: 6a5b ldr r3, [r3, #36] @ 0x24 + 80019cc: 4a43 ldr r2, [pc, #268] @ (8001adc ) + 80019ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80019d2: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80019d4: 687b ldr r3, [r7, #4] + 80019d6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80019d8: 2b00 cmp r3, #0 + 80019da: d079 beq.n 8001ad0 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80019dc: 69bb ldr r3, [r7, #24] + 80019de: 2b0c cmp r3, #12 + 80019e0: d056 beq.n 8001a90 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80019e2: 687b ldr r3, [r7, #4] + 80019e4: 6a5b ldr r3, [r3, #36] @ 0x24 + 80019e6: 2b02 cmp r3, #2 + 80019e8: d13b bne.n 8001a62 + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80019ea: 4b3d ldr r3, [pc, #244] @ (8001ae0 ) + 80019ec: 2200 movs r2, #0 + 80019ee: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80019f0: f7ff fa66 bl 8000ec0 + 80019f4: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80019f6: e008 b.n 8001a0a + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80019f8: f7ff fa62 bl 8000ec0 + 80019fc: 4602 mov r2, r0 + 80019fe: 693b ldr r3, [r7, #16] + 8001a00: 1ad3 subs r3, r2, r3 + 8001a02: 2b02 cmp r3, #2 + 8001a04: d901 bls.n 8001a0a + { + return HAL_TIMEOUT; + 8001a06: 2303 movs r3, #3 + 8001a08: e063 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001a0a: 4b34 ldr r3, [pc, #208] @ (8001adc ) + 8001a0c: 681b ldr r3, [r3, #0] + 8001a0e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001a12: 2b00 cmp r3, #0 + 8001a14: d1f0 bne.n 80019f8 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8001a16: 4b31 ldr r3, [pc, #196] @ (8001adc ) + 8001a18: 689b ldr r3, [r3, #8] + 8001a1a: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 8001a1e: 687b ldr r3, [r7, #4] + 8001a20: 6a99 ldr r1, [r3, #40] @ 0x28 + 8001a22: 687b ldr r3, [r7, #4] + 8001a24: 6adb ldr r3, [r3, #44] @ 0x2c + 8001a26: 4319 orrs r1, r3 + 8001a28: 687b ldr r3, [r7, #4] + 8001a2a: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001a2c: 430b orrs r3, r1 + 8001a2e: 492b ldr r1, [pc, #172] @ (8001adc ) + 8001a30: 4313 orrs r3, r2 + 8001a32: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8001a34: 4b2a ldr r3, [pc, #168] @ (8001ae0 ) + 8001a36: 2201 movs r2, #1 + 8001a38: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001a3a: f7ff fa41 bl 8000ec0 + 8001a3e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001a40: e008 b.n 8001a54 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001a42: f7ff fa3d bl 8000ec0 + 8001a46: 4602 mov r2, r0 + 8001a48: 693b ldr r3, [r7, #16] + 8001a4a: 1ad3 subs r3, r2, r3 + 8001a4c: 2b02 cmp r3, #2 + 8001a4e: d901 bls.n 8001a54 + { + return HAL_TIMEOUT; + 8001a50: 2303 movs r3, #3 + 8001a52: e03e b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001a54: 4b21 ldr r3, [pc, #132] @ (8001adc ) + 8001a56: 681b ldr r3, [r3, #0] + 8001a58: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001a5c: 2b00 cmp r3, #0 + 8001a5e: d0f0 beq.n 8001a42 + 8001a60: e036 b.n 8001ad0 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001a62: 4b1f ldr r3, [pc, #124] @ (8001ae0 ) + 8001a64: 2200 movs r2, #0 + 8001a66: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001a68: f7ff fa2a bl 8000ec0 + 8001a6c: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001a6e: e008 b.n 8001a82 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001a70: f7ff fa26 bl 8000ec0 + 8001a74: 4602 mov r2, r0 + 8001a76: 693b ldr r3, [r7, #16] + 8001a78: 1ad3 subs r3, r2, r3 + 8001a7a: 2b02 cmp r3, #2 + 8001a7c: d901 bls.n 8001a82 + { + return HAL_TIMEOUT; + 8001a7e: 2303 movs r3, #3 + 8001a80: e027 b.n 8001ad2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001a82: 4b16 ldr r3, [pc, #88] @ (8001adc ) + 8001a84: 681b ldr r3, [r3, #0] + 8001a86: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001a8a: 2b00 cmp r3, #0 + 8001a8c: d1f0 bne.n 8001a70 + 8001a8e: e01f b.n 8001ad0 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8001a90: 687b ldr r3, [r7, #4] + 8001a92: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a94: 2b01 cmp r3, #1 + 8001a96: d101 bne.n 8001a9c + { + return HAL_ERROR; + 8001a98: 2301 movs r3, #1 + 8001a9a: e01a b.n 8001ad2 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8001a9c: 4b0f ldr r3, [pc, #60] @ (8001adc ) + 8001a9e: 689b ldr r3, [r3, #8] + 8001aa0: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8001aa2: 697b ldr r3, [r7, #20] + 8001aa4: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 8001aa8: 687b ldr r3, [r7, #4] + 8001aaa: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001aac: 429a cmp r2, r3 + 8001aae: d10d bne.n 8001acc + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8001ab0: 697b ldr r3, [r7, #20] + 8001ab2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 8001ab6: 687b ldr r3, [r7, #4] + 8001ab8: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8001aba: 429a cmp r2, r3 + 8001abc: d106 bne.n 8001acc + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 8001abe: 697b ldr r3, [r7, #20] + 8001ac0: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 8001ac4: 687b ldr r3, [r7, #4] + 8001ac6: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8001ac8: 429a cmp r2, r3 + 8001aca: d001 beq.n 8001ad0 + { + return HAL_ERROR; + 8001acc: 2301 movs r3, #1 + 8001ace: e000 b.n 8001ad2 + } + } + } + } + + return HAL_OK; + 8001ad0: 2300 movs r3, #0 +} + 8001ad2: 4618 mov r0, r3 + 8001ad4: 3720 adds r7, #32 + 8001ad6: 46bd mov sp, r7 + 8001ad8: bd80 pop {r7, pc} + 8001ada: bf00 nop + 8001adc: 40023800 .word 0x40023800 + 8001ae0: 42470060 .word 0x42470060 + +08001ae4 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8001ae4: b580 push {r7, lr} + 8001ae6: b084 sub sp, #16 + 8001ae8: af00 add r7, sp, #0 + 8001aea: 6078 str r0, [r7, #4] + 8001aec: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 8001aee: 687b ldr r3, [r7, #4] + 8001af0: 2b00 cmp r3, #0 + 8001af2: d101 bne.n 8001af8 + { + return HAL_ERROR; + 8001af4: 2301 movs r3, #1 + 8001af6: e11a b.n 8001d2e + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8001af8: 4b8f ldr r3, [pc, #572] @ (8001d38 ) + 8001afa: 681b ldr r3, [r3, #0] + 8001afc: f003 0301 and.w r3, r3, #1 + 8001b00: 683a ldr r2, [r7, #0] + 8001b02: 429a cmp r2, r3 + 8001b04: d919 bls.n 8001b3a + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001b06: 683b ldr r3, [r7, #0] + 8001b08: 2b01 cmp r3, #1 + 8001b0a: d105 bne.n 8001b18 + 8001b0c: 4b8a ldr r3, [pc, #552] @ (8001d38 ) + 8001b0e: 681b ldr r3, [r3, #0] + 8001b10: 4a89 ldr r2, [pc, #548] @ (8001d38 ) + 8001b12: f043 0304 orr.w r3, r3, #4 + 8001b16: 6013 str r3, [r2, #0] + 8001b18: 4b87 ldr r3, [pc, #540] @ (8001d38 ) + 8001b1a: 681b ldr r3, [r3, #0] + 8001b1c: f023 0201 bic.w r2, r3, #1 + 8001b20: 4985 ldr r1, [pc, #532] @ (8001d38 ) + 8001b22: 683b ldr r3, [r7, #0] + 8001b24: 4313 orrs r3, r2 + 8001b26: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001b28: 4b83 ldr r3, [pc, #524] @ (8001d38 ) + 8001b2a: 681b ldr r3, [r3, #0] + 8001b2c: f003 0301 and.w r3, r3, #1 + 8001b30: 683a ldr r2, [r7, #0] + 8001b32: 429a cmp r2, r3 + 8001b34: d001 beq.n 8001b3a + { + return HAL_ERROR; + 8001b36: 2301 movs r3, #1 + 8001b38: e0f9 b.n 8001d2e + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8001b3a: 687b ldr r3, [r7, #4] + 8001b3c: 681b ldr r3, [r3, #0] + 8001b3e: f003 0302 and.w r3, r3, #2 + 8001b42: 2b00 cmp r3, #0 + 8001b44: d008 beq.n 8001b58 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8001b46: 4b7d ldr r3, [pc, #500] @ (8001d3c ) + 8001b48: 689b ldr r3, [r3, #8] + 8001b4a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8001b4e: 687b ldr r3, [r7, #4] + 8001b50: 689b ldr r3, [r3, #8] + 8001b52: 497a ldr r1, [pc, #488] @ (8001d3c ) + 8001b54: 4313 orrs r3, r2 + 8001b56: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8001b58: 687b ldr r3, [r7, #4] + 8001b5a: 681b ldr r3, [r3, #0] + 8001b5c: f003 0301 and.w r3, r3, #1 + 8001b60: 2b00 cmp r3, #0 + 8001b62: f000 808e beq.w 8001c82 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001b66: 687b ldr r3, [r7, #4] + 8001b68: 685b ldr r3, [r3, #4] + 8001b6a: 2b02 cmp r3, #2 + 8001b6c: d107 bne.n 8001b7e + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001b6e: 4b73 ldr r3, [pc, #460] @ (8001d3c ) + 8001b70: 681b ldr r3, [r3, #0] + 8001b72: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001b76: 2b00 cmp r3, #0 + 8001b78: d121 bne.n 8001bbe + { + return HAL_ERROR; + 8001b7a: 2301 movs r3, #1 + 8001b7c: e0d7 b.n 8001d2e + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001b7e: 687b ldr r3, [r7, #4] + 8001b80: 685b ldr r3, [r3, #4] + 8001b82: 2b03 cmp r3, #3 + 8001b84: d107 bne.n 8001b96 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001b86: 4b6d ldr r3, [pc, #436] @ (8001d3c ) + 8001b88: 681b ldr r3, [r3, #0] + 8001b8a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001b8e: 2b00 cmp r3, #0 + 8001b90: d115 bne.n 8001bbe + { + return HAL_ERROR; + 8001b92: 2301 movs r3, #1 + 8001b94: e0cb b.n 8001d2e + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001b96: 687b ldr r3, [r7, #4] + 8001b98: 685b ldr r3, [r3, #4] + 8001b9a: 2b01 cmp r3, #1 + 8001b9c: d107 bne.n 8001bae + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001b9e: 4b67 ldr r3, [pc, #412] @ (8001d3c ) + 8001ba0: 681b ldr r3, [r3, #0] + 8001ba2: f003 0302 and.w r3, r3, #2 + 8001ba6: 2b00 cmp r3, #0 + 8001ba8: d109 bne.n 8001bbe + { + return HAL_ERROR; + 8001baa: 2301 movs r3, #1 + 8001bac: e0bf b.n 8001d2e + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001bae: 4b63 ldr r3, [pc, #396] @ (8001d3c ) + 8001bb0: 681b ldr r3, [r3, #0] + 8001bb2: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001bb6: 2b00 cmp r3, #0 + 8001bb8: d101 bne.n 8001bbe + { + return HAL_ERROR; + 8001bba: 2301 movs r3, #1 + 8001bbc: e0b7 b.n 8001d2e + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8001bbe: 4b5f ldr r3, [pc, #380] @ (8001d3c ) + 8001bc0: 689b ldr r3, [r3, #8] + 8001bc2: f023 0203 bic.w r2, r3, #3 + 8001bc6: 687b ldr r3, [r7, #4] + 8001bc8: 685b ldr r3, [r3, #4] + 8001bca: 495c ldr r1, [pc, #368] @ (8001d3c ) + 8001bcc: 4313 orrs r3, r2 + 8001bce: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001bd0: f7ff f976 bl 8000ec0 + 8001bd4: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001bd6: 687b ldr r3, [r7, #4] + 8001bd8: 685b ldr r3, [r3, #4] + 8001bda: 2b02 cmp r3, #2 + 8001bdc: d112 bne.n 8001c04 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001bde: e00a b.n 8001bf6 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001be0: f7ff f96e bl 8000ec0 + 8001be4: 4602 mov r2, r0 + 8001be6: 68fb ldr r3, [r7, #12] + 8001be8: 1ad3 subs r3, r2, r3 + 8001bea: f241 3288 movw r2, #5000 @ 0x1388 + 8001bee: 4293 cmp r3, r2 + 8001bf0: d901 bls.n 8001bf6 + { + return HAL_TIMEOUT; + 8001bf2: 2303 movs r3, #3 + 8001bf4: e09b b.n 8001d2e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001bf6: 4b51 ldr r3, [pc, #324] @ (8001d3c ) + 8001bf8: 689b ldr r3, [r3, #8] + 8001bfa: f003 030c and.w r3, r3, #12 + 8001bfe: 2b08 cmp r3, #8 + 8001c00: d1ee bne.n 8001be0 + 8001c02: e03e b.n 8001c82 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001c04: 687b ldr r3, [r7, #4] + 8001c06: 685b ldr r3, [r3, #4] + 8001c08: 2b03 cmp r3, #3 + 8001c0a: d112 bne.n 8001c32 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001c0c: e00a b.n 8001c24 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001c0e: f7ff f957 bl 8000ec0 + 8001c12: 4602 mov r2, r0 + 8001c14: 68fb ldr r3, [r7, #12] + 8001c16: 1ad3 subs r3, r2, r3 + 8001c18: f241 3288 movw r2, #5000 @ 0x1388 + 8001c1c: 4293 cmp r3, r2 + 8001c1e: d901 bls.n 8001c24 + { + return HAL_TIMEOUT; + 8001c20: 2303 movs r3, #3 + 8001c22: e084 b.n 8001d2e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001c24: 4b45 ldr r3, [pc, #276] @ (8001d3c ) + 8001c26: 689b ldr r3, [r3, #8] + 8001c28: f003 030c and.w r3, r3, #12 + 8001c2c: 2b0c cmp r3, #12 + 8001c2e: d1ee bne.n 8001c0e + 8001c30: e027 b.n 8001c82 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001c32: 687b ldr r3, [r7, #4] + 8001c34: 685b ldr r3, [r3, #4] + 8001c36: 2b01 cmp r3, #1 + 8001c38: d11d bne.n 8001c76 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001c3a: e00a b.n 8001c52 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001c3c: f7ff f940 bl 8000ec0 + 8001c40: 4602 mov r2, r0 + 8001c42: 68fb ldr r3, [r7, #12] + 8001c44: 1ad3 subs r3, r2, r3 + 8001c46: f241 3288 movw r2, #5000 @ 0x1388 + 8001c4a: 4293 cmp r3, r2 + 8001c4c: d901 bls.n 8001c52 + { + return HAL_TIMEOUT; + 8001c4e: 2303 movs r3, #3 + 8001c50: e06d b.n 8001d2e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001c52: 4b3a ldr r3, [pc, #232] @ (8001d3c ) + 8001c54: 689b ldr r3, [r3, #8] + 8001c56: f003 030c and.w r3, r3, #12 + 8001c5a: 2b04 cmp r3, #4 + 8001c5c: d1ee bne.n 8001c3c + 8001c5e: e010 b.n 8001c82 + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001c60: f7ff f92e bl 8000ec0 + 8001c64: 4602 mov r2, r0 + 8001c66: 68fb ldr r3, [r7, #12] + 8001c68: 1ad3 subs r3, r2, r3 + 8001c6a: f241 3288 movw r2, #5000 @ 0x1388 + 8001c6e: 4293 cmp r3, r2 + 8001c70: d901 bls.n 8001c76 + { + return HAL_TIMEOUT; + 8001c72: 2303 movs r3, #3 + 8001c74: e05b b.n 8001d2e + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 8001c76: 4b31 ldr r3, [pc, #196] @ (8001d3c ) + 8001c78: 689b ldr r3, [r3, #8] + 8001c7a: f003 030c and.w r3, r3, #12 + 8001c7e: 2b00 cmp r3, #0 + 8001c80: d1ee bne.n 8001c60 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8001c82: 4b2d ldr r3, [pc, #180] @ (8001d38 ) + 8001c84: 681b ldr r3, [r3, #0] + 8001c86: f003 0301 and.w r3, r3, #1 + 8001c8a: 683a ldr r2, [r7, #0] + 8001c8c: 429a cmp r2, r3 + 8001c8e: d219 bcs.n 8001cc4 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001c90: 683b ldr r3, [r7, #0] + 8001c92: 2b01 cmp r3, #1 + 8001c94: d105 bne.n 8001ca2 + 8001c96: 4b28 ldr r3, [pc, #160] @ (8001d38 ) + 8001c98: 681b ldr r3, [r3, #0] + 8001c9a: 4a27 ldr r2, [pc, #156] @ (8001d38 ) + 8001c9c: f043 0304 orr.w r3, r3, #4 + 8001ca0: 6013 str r3, [r2, #0] + 8001ca2: 4b25 ldr r3, [pc, #148] @ (8001d38 ) + 8001ca4: 681b ldr r3, [r3, #0] + 8001ca6: f023 0201 bic.w r2, r3, #1 + 8001caa: 4923 ldr r1, [pc, #140] @ (8001d38 ) + 8001cac: 683b ldr r3, [r7, #0] + 8001cae: 4313 orrs r3, r2 + 8001cb0: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001cb2: 4b21 ldr r3, [pc, #132] @ (8001d38 ) + 8001cb4: 681b ldr r3, [r3, #0] + 8001cb6: f003 0301 and.w r3, r3, #1 + 8001cba: 683a ldr r2, [r7, #0] + 8001cbc: 429a cmp r2, r3 + 8001cbe: d001 beq.n 8001cc4 + { + return HAL_ERROR; + 8001cc0: 2301 movs r3, #1 + 8001cc2: e034 b.n 8001d2e + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001cc4: 687b ldr r3, [r7, #4] + 8001cc6: 681b ldr r3, [r3, #0] + 8001cc8: f003 0304 and.w r3, r3, #4 + 8001ccc: 2b00 cmp r3, #0 + 8001cce: d008 beq.n 8001ce2 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8001cd0: 4b1a ldr r3, [pc, #104] @ (8001d3c ) + 8001cd2: 689b ldr r3, [r3, #8] + 8001cd4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001cd8: 687b ldr r3, [r7, #4] + 8001cda: 68db ldr r3, [r3, #12] + 8001cdc: 4917 ldr r1, [pc, #92] @ (8001d3c ) + 8001cde: 4313 orrs r3, r2 + 8001ce0: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001ce2: 687b ldr r3, [r7, #4] + 8001ce4: 681b ldr r3, [r3, #0] + 8001ce6: f003 0308 and.w r3, r3, #8 + 8001cea: 2b00 cmp r3, #0 + 8001cec: d009 beq.n 8001d02 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8001cee: 4b13 ldr r3, [pc, #76] @ (8001d3c ) + 8001cf0: 689b ldr r3, [r3, #8] + 8001cf2: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001cf6: 687b ldr r3, [r7, #4] + 8001cf8: 691b ldr r3, [r3, #16] + 8001cfa: 00db lsls r3, r3, #3 + 8001cfc: 490f ldr r1, [pc, #60] @ (8001d3c ) + 8001cfe: 4313 orrs r3, r2 + 8001d00: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8001d02: f000 f823 bl 8001d4c + 8001d06: 4602 mov r2, r0 + 8001d08: 4b0c ldr r3, [pc, #48] @ (8001d3c ) + 8001d0a: 689b ldr r3, [r3, #8] + 8001d0c: 091b lsrs r3, r3, #4 + 8001d0e: f003 030f and.w r3, r3, #15 + 8001d12: 490b ldr r1, [pc, #44] @ (8001d40 ) + 8001d14: 5ccb ldrb r3, [r1, r3] + 8001d16: fa22 f303 lsr.w r3, r2, r3 + 8001d1a: 4a0a ldr r2, [pc, #40] @ (8001d44 ) + 8001d1c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001d1e: 4b0a ldr r3, [pc, #40] @ (8001d48 ) + 8001d20: 681b ldr r3, [r3, #0] + 8001d22: 4618 mov r0, r3 + 8001d24: f7ff f880 bl 8000e28 + 8001d28: 4603 mov r3, r0 + 8001d2a: 72fb strb r3, [r7, #11] + + return status; + 8001d2c: 7afb ldrb r3, [r7, #11] +} + 8001d2e: 4618 mov r0, r3 + 8001d30: 3710 adds r7, #16 + 8001d32: 46bd mov sp, r7 + 8001d34: bd80 pop {r7, pc} + 8001d36: bf00 nop + 8001d38: 40023c00 .word 0x40023c00 + 8001d3c: 40023800 .word 0x40023800 + 8001d40: 08003234 .word 0x08003234 + 8001d44: 20000004 .word 0x20000004 + 8001d48: 20000008 .word 0x20000008 + +08001d4c : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8001d4c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001d50: b08e sub sp, #56 @ 0x38 + 8001d52: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 8001d54: 4b58 ldr r3, [pc, #352] @ (8001eb8 ) + 8001d56: 689b ldr r3, [r3, #8] + 8001d58: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8001d5a: 6afb ldr r3, [r7, #44] @ 0x2c + 8001d5c: f003 030c and.w r3, r3, #12 + 8001d60: 2b0c cmp r3, #12 + 8001d62: d00d beq.n 8001d80 + 8001d64: 2b0c cmp r3, #12 + 8001d66: f200 8092 bhi.w 8001e8e + 8001d6a: 2b04 cmp r3, #4 + 8001d6c: d002 beq.n 8001d74 + 8001d6e: 2b08 cmp r3, #8 + 8001d70: d003 beq.n 8001d7a + 8001d72: e08c b.n 8001e8e + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8001d74: 4b51 ldr r3, [pc, #324] @ (8001ebc ) + 8001d76: 633b str r3, [r7, #48] @ 0x30 + break; + 8001d78: e097 b.n 8001eaa + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001d7a: 4b51 ldr r3, [pc, #324] @ (8001ec0 ) + 8001d7c: 633b str r3, [r7, #48] @ 0x30 + break; + 8001d7e: e094 b.n 8001eaa + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8001d80: 6afb ldr r3, [r7, #44] @ 0x2c + 8001d82: 0c9b lsrs r3, r3, #18 + 8001d84: f003 020f and.w r2, r3, #15 + 8001d88: 4b4e ldr r3, [pc, #312] @ (8001ec4 ) + 8001d8a: 5c9b ldrb r3, [r3, r2] + 8001d8c: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8001d8e: 6afb ldr r3, [r7, #44] @ 0x2c + 8001d90: 0d9b lsrs r3, r3, #22 + 8001d92: f003 0303 and.w r3, r3, #3 + 8001d96: 3301 adds r3, #1 + 8001d98: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8001d9a: 4b47 ldr r3, [pc, #284] @ (8001eb8 ) + 8001d9c: 689b ldr r3, [r3, #8] + 8001d9e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001da2: 2b00 cmp r3, #0 + 8001da4: d021 beq.n 8001dea + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001da6: 6abb ldr r3, [r7, #40] @ 0x28 + 8001da8: 2200 movs r2, #0 + 8001daa: 61bb str r3, [r7, #24] + 8001dac: 61fa str r2, [r7, #28] + 8001dae: 4b44 ldr r3, [pc, #272] @ (8001ec0 ) + 8001db0: e9d7 8906 ldrd r8, r9, [r7, #24] + 8001db4: 464a mov r2, r9 + 8001db6: fb03 f202 mul.w r2, r3, r2 + 8001dba: 2300 movs r3, #0 + 8001dbc: 4644 mov r4, r8 + 8001dbe: fb04 f303 mul.w r3, r4, r3 + 8001dc2: 4413 add r3, r2 + 8001dc4: 4a3e ldr r2, [pc, #248] @ (8001ec0 ) + 8001dc6: 4644 mov r4, r8 + 8001dc8: fba4 0102 umull r0, r1, r4, r2 + 8001dcc: 440b add r3, r1 + 8001dce: 4619 mov r1, r3 + 8001dd0: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001dd2: 2200 movs r2, #0 + 8001dd4: 613b str r3, [r7, #16] + 8001dd6: 617a str r2, [r7, #20] + 8001dd8: e9d7 2304 ldrd r2, r3, [r7, #16] + 8001ddc: f7fe f9ce bl 800017c <__aeabi_uldivmod> + 8001de0: 4602 mov r2, r0 + 8001de2: 460b mov r3, r1 + 8001de4: 4613 mov r3, r2 + 8001de6: 637b str r3, [r7, #52] @ 0x34 + 8001de8: e04e b.n 8001e88 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001dea: 6abb ldr r3, [r7, #40] @ 0x28 + 8001dec: 2200 movs r2, #0 + 8001dee: 469a mov sl, r3 + 8001df0: 4693 mov fp, r2 + 8001df2: 4652 mov r2, sl + 8001df4: 465b mov r3, fp + 8001df6: f04f 0000 mov.w r0, #0 + 8001dfa: f04f 0100 mov.w r1, #0 + 8001dfe: 0159 lsls r1, r3, #5 + 8001e00: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001e04: 0150 lsls r0, r2, #5 + 8001e06: 4602 mov r2, r0 + 8001e08: 460b mov r3, r1 + 8001e0a: ebb2 080a subs.w r8, r2, sl + 8001e0e: eb63 090b sbc.w r9, r3, fp + 8001e12: f04f 0200 mov.w r2, #0 + 8001e16: f04f 0300 mov.w r3, #0 + 8001e1a: ea4f 1389 mov.w r3, r9, lsl #6 + 8001e1e: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001e22: ea4f 1288 mov.w r2, r8, lsl #6 + 8001e26: ebb2 0408 subs.w r4, r2, r8 + 8001e2a: eb63 0509 sbc.w r5, r3, r9 + 8001e2e: f04f 0200 mov.w r2, #0 + 8001e32: f04f 0300 mov.w r3, #0 + 8001e36: 00eb lsls r3, r5, #3 + 8001e38: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8001e3c: 00e2 lsls r2, r4, #3 + 8001e3e: 4614 mov r4, r2 + 8001e40: 461d mov r5, r3 + 8001e42: eb14 030a adds.w r3, r4, sl + 8001e46: 603b str r3, [r7, #0] + 8001e48: eb45 030b adc.w r3, r5, fp + 8001e4c: 607b str r3, [r7, #4] + 8001e4e: f04f 0200 mov.w r2, #0 + 8001e52: f04f 0300 mov.w r3, #0 + 8001e56: e9d7 4500 ldrd r4, r5, [r7] + 8001e5a: 4629 mov r1, r5 + 8001e5c: 028b lsls r3, r1, #10 + 8001e5e: 4620 mov r0, r4 + 8001e60: 4629 mov r1, r5 + 8001e62: 4604 mov r4, r0 + 8001e64: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8001e68: 4601 mov r1, r0 + 8001e6a: 028a lsls r2, r1, #10 + 8001e6c: 4610 mov r0, r2 + 8001e6e: 4619 mov r1, r3 + 8001e70: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001e72: 2200 movs r2, #0 + 8001e74: 60bb str r3, [r7, #8] + 8001e76: 60fa str r2, [r7, #12] + 8001e78: e9d7 2302 ldrd r2, r3, [r7, #8] + 8001e7c: f7fe f97e bl 800017c <__aeabi_uldivmod> + 8001e80: 4602 mov r2, r0 + 8001e82: 460b mov r3, r1 + 8001e84: 4613 mov r3, r2 + 8001e86: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 8001e88: 6b7b ldr r3, [r7, #52] @ 0x34 + 8001e8a: 633b str r3, [r7, #48] @ 0x30 + break; + 8001e8c: e00d b.n 8001eaa + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8001e8e: 4b0a ldr r3, [pc, #40] @ (8001eb8 ) + 8001e90: 685b ldr r3, [r3, #4] + 8001e92: 0b5b lsrs r3, r3, #13 + 8001e94: f003 0307 and.w r3, r3, #7 + 8001e98: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8001e9a: 6a3b ldr r3, [r7, #32] + 8001e9c: 3301 adds r3, #1 + 8001e9e: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001ea2: fa02 f303 lsl.w r3, r2, r3 + 8001ea6: 633b str r3, [r7, #48] @ 0x30 + break; + 8001ea8: bf00 nop + } + } + return sysclockfreq; + 8001eaa: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 8001eac: 4618 mov r0, r3 + 8001eae: 3738 adds r7, #56 @ 0x38 + 8001eb0: 46bd mov sp, r7 + 8001eb2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8001eb6: bf00 nop + 8001eb8: 40023800 .word 0x40023800 + 8001ebc: 00f42400 .word 0x00f42400 + 8001ec0: 016e3600 .word 0x016e3600 + 8001ec4: 08003228 .word 0x08003228 + +08001ec8 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 8001ec8: b480 push {r7} + 8001eca: b087 sub sp, #28 + 8001ecc: af00 add r7, sp, #0 + 8001ece: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8001ed0: 2300 movs r3, #0 + 8001ed2: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 8001ed4: 4b29 ldr r3, [pc, #164] @ (8001f7c ) + 8001ed6: 689b ldr r3, [r3, #8] + 8001ed8: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001edc: 2b00 cmp r3, #0 + 8001ede: d12c bne.n 8001f3a + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 8001ee0: 4b26 ldr r3, [pc, #152] @ (8001f7c ) + 8001ee2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ee4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001ee8: 2b00 cmp r3, #0 + 8001eea: d005 beq.n 8001ef8 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001eec: 4b24 ldr r3, [pc, #144] @ (8001f80 ) + 8001eee: 681b ldr r3, [r3, #0] + 8001ef0: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001ef4: 617b str r3, [r7, #20] + 8001ef6: e016 b.n 8001f26 + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001ef8: 4b20 ldr r3, [pc, #128] @ (8001f7c ) + 8001efa: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001efc: 4a1f ldr r2, [pc, #124] @ (8001f7c ) + 8001efe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001f02: 6253 str r3, [r2, #36] @ 0x24 + 8001f04: 4b1d ldr r3, [pc, #116] @ (8001f7c ) + 8001f06: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001f08: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001f0c: 60fb str r3, [r7, #12] + 8001f0e: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001f10: 4b1b ldr r3, [pc, #108] @ (8001f80 ) + 8001f12: 681b ldr r3, [r3, #0] + 8001f14: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001f18: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001f1a: 4b18 ldr r3, [pc, #96] @ (8001f7c ) + 8001f1c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001f1e: 4a17 ldr r2, [pc, #92] @ (8001f7c ) + 8001f20: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001f24: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001f26: 697b ldr r3, [r7, #20] + 8001f28: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001f2c: d105 bne.n 8001f3a + 8001f2e: 687b ldr r3, [r7, #4] + 8001f30: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001f34: d101 bne.n 8001f3a + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001f36: 2301 movs r3, #1 + 8001f38: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001f3a: 693b ldr r3, [r7, #16] + 8001f3c: 2b01 cmp r3, #1 + 8001f3e: d105 bne.n 8001f4c + 8001f40: 4b10 ldr r3, [pc, #64] @ (8001f84 ) + 8001f42: 681b ldr r3, [r3, #0] + 8001f44: 4a0f ldr r2, [pc, #60] @ (8001f84 ) + 8001f46: f043 0304 orr.w r3, r3, #4 + 8001f4a: 6013 str r3, [r2, #0] + 8001f4c: 4b0d ldr r3, [pc, #52] @ (8001f84 ) + 8001f4e: 681b ldr r3, [r3, #0] + 8001f50: f023 0201 bic.w r2, r3, #1 + 8001f54: 490b ldr r1, [pc, #44] @ (8001f84 ) + 8001f56: 693b ldr r3, [r7, #16] + 8001f58: 4313 orrs r3, r2 + 8001f5a: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001f5c: 4b09 ldr r3, [pc, #36] @ (8001f84 ) + 8001f5e: 681b ldr r3, [r3, #0] + 8001f60: f003 0301 and.w r3, r3, #1 + 8001f64: 693a ldr r2, [r7, #16] + 8001f66: 429a cmp r2, r3 + 8001f68: d001 beq.n 8001f6e + { + return HAL_ERROR; + 8001f6a: 2301 movs r3, #1 + 8001f6c: e000 b.n 8001f70 + } + + return HAL_OK; + 8001f6e: 2300 movs r3, #0 +} + 8001f70: 4618 mov r0, r3 + 8001f72: 371c adds r7, #28 + 8001f74: 46bd mov sp, r7 + 8001f76: bc80 pop {r7} + 8001f78: 4770 bx lr + 8001f7a: bf00 nop + 8001f7c: 40023800 .word 0x40023800 + 8001f80: 40007000 .word 0x40007000 + 8001f84: 40023c00 .word 0x40023c00 + +08001f88 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001f88: b580 push {r7, lr} + 8001f8a: b082 sub sp, #8 + 8001f8c: af00 add r7, sp, #0 + 8001f8e: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001f90: 687b ldr r3, [r7, #4] + 8001f92: 2b00 cmp r3, #0 + 8001f94: d101 bne.n 8001f9a + { + return HAL_ERROR; + 8001f96: 2301 movs r3, #1 + 8001f98: e07b b.n 8002092 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001f9a: 687b ldr r3, [r7, #4] + 8001f9c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001f9e: 2b00 cmp r3, #0 + 8001fa0: d108 bne.n 8001fb4 + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001fa2: 687b ldr r3, [r7, #4] + 8001fa4: 685b ldr r3, [r3, #4] + 8001fa6: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001faa: d009 beq.n 8001fc0 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001fac: 687b ldr r3, [r7, #4] + 8001fae: 2200 movs r2, #0 + 8001fb0: 61da str r2, [r3, #28] + 8001fb2: e005 b.n 8001fc0 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001fb4: 687b ldr r3, [r7, #4] + 8001fb6: 2200 movs r2, #0 + 8001fb8: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001fba: 687b ldr r3, [r7, #4] + 8001fbc: 2200 movs r2, #0 + 8001fbe: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001fc0: 687b ldr r3, [r7, #4] + 8001fc2: 2200 movs r2, #0 + 8001fc4: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001fc6: 687b ldr r3, [r7, #4] + 8001fc8: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001fcc: b2db uxtb r3, r3 + 8001fce: 2b00 cmp r3, #0 + 8001fd0: d106 bne.n 8001fe0 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001fd2: 687b ldr r3, [r7, #4] + 8001fd4: 2200 movs r2, #0 + 8001fd6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001fda: 6878 ldr r0, [r7, #4] + 8001fdc: f7fe fd12 bl 8000a04 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001fe0: 687b ldr r3, [r7, #4] + 8001fe2: 2202 movs r2, #2 + 8001fe4: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001fe8: 687b ldr r3, [r7, #4] + 8001fea: 681b ldr r3, [r3, #0] + 8001fec: 681a ldr r2, [r3, #0] + 8001fee: 687b ldr r3, [r7, #4] + 8001ff0: 681b ldr r3, [r3, #0] + 8001ff2: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001ff6: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001ff8: 687b ldr r3, [r7, #4] + 8001ffa: 685b ldr r3, [r3, #4] + 8001ffc: f403 7282 and.w r2, r3, #260 @ 0x104 + 8002000: 687b ldr r3, [r7, #4] + 8002002: 689b ldr r3, [r3, #8] + 8002004: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8002008: 431a orrs r2, r3 + 800200a: 687b ldr r3, [r7, #4] + 800200c: 68db ldr r3, [r3, #12] + 800200e: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8002012: 431a orrs r2, r3 + 8002014: 687b ldr r3, [r7, #4] + 8002016: 691b ldr r3, [r3, #16] + 8002018: f003 0302 and.w r3, r3, #2 + 800201c: 431a orrs r2, r3 + 800201e: 687b ldr r3, [r7, #4] + 8002020: 695b ldr r3, [r3, #20] + 8002022: f003 0301 and.w r3, r3, #1 + 8002026: 431a orrs r2, r3 + 8002028: 687b ldr r3, [r7, #4] + 800202a: 699b ldr r3, [r3, #24] + 800202c: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002030: 431a orrs r2, r3 + 8002032: 687b ldr r3, [r7, #4] + 8002034: 69db ldr r3, [r3, #28] + 8002036: f003 0338 and.w r3, r3, #56 @ 0x38 + 800203a: 431a orrs r2, r3 + 800203c: 687b ldr r3, [r7, #4] + 800203e: 6a1b ldr r3, [r3, #32] + 8002040: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002044: ea42 0103 orr.w r1, r2, r3 + 8002048: 687b ldr r3, [r7, #4] + 800204a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800204c: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8002050: 687b ldr r3, [r7, #4] + 8002052: 681b ldr r3, [r3, #0] + 8002054: 430a orrs r2, r1 + 8002056: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8002058: 687b ldr r3, [r7, #4] + 800205a: 699b ldr r3, [r3, #24] + 800205c: 0c1b lsrs r3, r3, #16 + 800205e: f003 0104 and.w r1, r3, #4 + 8002062: 687b ldr r3, [r7, #4] + 8002064: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002066: f003 0210 and.w r2, r3, #16 + 800206a: 687b ldr r3, [r7, #4] + 800206c: 681b ldr r3, [r3, #0] + 800206e: 430a orrs r2, r1 + 8002070: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8002072: 687b ldr r3, [r7, #4] + 8002074: 681b ldr r3, [r3, #0] + 8002076: 69da ldr r2, [r3, #28] + 8002078: 687b ldr r3, [r7, #4] + 800207a: 681b ldr r3, [r3, #0] + 800207c: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8002080: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8002082: 687b ldr r3, [r7, #4] + 8002084: 2200 movs r2, #0 + 8002086: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8002088: 687b ldr r3, [r7, #4] + 800208a: 2201 movs r2, #1 + 800208c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8002090: 2300 movs r3, #0 +} + 8002092: 4618 mov r0, r3 + 8002094: 3708 adds r7, #8 + 8002096: 46bd mov sp, r7 + 8002098: bd80 pop {r7, pc} + +0800209a : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 800209a: b580 push {r7, lr} + 800209c: b088 sub sp, #32 + 800209e: af00 add r7, sp, #0 + 80020a0: 60f8 str r0, [r7, #12] + 80020a2: 60b9 str r1, [r7, #8] + 80020a4: 603b str r3, [r7, #0] + 80020a6: 4613 mov r3, r2 + 80020a8: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 80020aa: f7fe ff09 bl 8000ec0 + 80020ae: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 80020b0: 88fb ldrh r3, [r7, #6] + 80020b2: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 80020b4: 68fb ldr r3, [r7, #12] + 80020b6: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 80020ba: b2db uxtb r3, r3 + 80020bc: 2b01 cmp r3, #1 + 80020be: d001 beq.n 80020c4 + { + return HAL_BUSY; + 80020c0: 2302 movs r3, #2 + 80020c2: e12a b.n 800231a + } + + if ((pData == NULL) || (Size == 0U)) + 80020c4: 68bb ldr r3, [r7, #8] + 80020c6: 2b00 cmp r3, #0 + 80020c8: d002 beq.n 80020d0 + 80020ca: 88fb ldrh r3, [r7, #6] + 80020cc: 2b00 cmp r3, #0 + 80020ce: d101 bne.n 80020d4 + { + return HAL_ERROR; + 80020d0: 2301 movs r3, #1 + 80020d2: e122 b.n 800231a + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 80020d4: 68fb ldr r3, [r7, #12] + 80020d6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 80020da: 2b01 cmp r3, #1 + 80020dc: d101 bne.n 80020e2 + 80020de: 2302 movs r3, #2 + 80020e0: e11b b.n 800231a + 80020e2: 68fb ldr r3, [r7, #12] + 80020e4: 2201 movs r2, #1 + 80020e6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 80020ea: 68fb ldr r3, [r7, #12] + 80020ec: 2203 movs r2, #3 + 80020ee: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 80020f2: 68fb ldr r3, [r7, #12] + 80020f4: 2200 movs r2, #0 + 80020f6: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 80020f8: 68fb ldr r3, [r7, #12] + 80020fa: 68ba ldr r2, [r7, #8] + 80020fc: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 80020fe: 68fb ldr r3, [r7, #12] + 8002100: 88fa ldrh r2, [r7, #6] + 8002102: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8002104: 68fb ldr r3, [r7, #12] + 8002106: 88fa ldrh r2, [r7, #6] + 8002108: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 800210a: 68fb ldr r3, [r7, #12] + 800210c: 2200 movs r2, #0 + 800210e: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 8002110: 68fb ldr r3, [r7, #12] + 8002112: 2200 movs r2, #0 + 8002114: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8002116: 68fb ldr r3, [r7, #12] + 8002118: 2200 movs r2, #0 + 800211a: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 800211c: 68fb ldr r3, [r7, #12] + 800211e: 2200 movs r2, #0 + 8002120: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8002122: 68fb ldr r3, [r7, #12] + 8002124: 2200 movs r2, #0 + 8002126: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8002128: 68fb ldr r3, [r7, #12] + 800212a: 689b ldr r3, [r3, #8] + 800212c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8002130: d10f bne.n 8002152 + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8002132: 68fb ldr r3, [r7, #12] + 8002134: 681b ldr r3, [r3, #0] + 8002136: 681a ldr r2, [r3, #0] + 8002138: 68fb ldr r3, [r7, #12] + 800213a: 681b ldr r3, [r3, #0] + 800213c: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8002140: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8002142: 68fb ldr r3, [r7, #12] + 8002144: 681b ldr r3, [r3, #0] + 8002146: 681a ldr r2, [r3, #0] + 8002148: 68fb ldr r3, [r7, #12] + 800214a: 681b ldr r3, [r3, #0] + 800214c: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8002150: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8002152: 68fb ldr r3, [r7, #12] + 8002154: 681b ldr r3, [r3, #0] + 8002156: 681b ldr r3, [r3, #0] + 8002158: f003 0340 and.w r3, r3, #64 @ 0x40 + 800215c: 2b40 cmp r3, #64 @ 0x40 + 800215e: d007 beq.n 8002170 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8002160: 68fb ldr r3, [r7, #12] + 8002162: 681b ldr r3, [r3, #0] + 8002164: 681a ldr r2, [r3, #0] + 8002166: 68fb ldr r3, [r7, #12] + 8002168: 681b ldr r3, [r3, #0] + 800216a: f042 0240 orr.w r2, r2, #64 @ 0x40 + 800216e: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8002170: 68fb ldr r3, [r7, #12] + 8002172: 68db ldr r3, [r3, #12] + 8002174: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8002178: d152 bne.n 8002220 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800217a: 68fb ldr r3, [r7, #12] + 800217c: 685b ldr r3, [r3, #4] + 800217e: 2b00 cmp r3, #0 + 8002180: d002 beq.n 8002188 + 8002182: 8b7b ldrh r3, [r7, #26] + 8002184: 2b01 cmp r3, #1 + 8002186: d145 bne.n 8002214 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8002188: 68fb ldr r3, [r7, #12] + 800218a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800218c: 881a ldrh r2, [r3, #0] + 800218e: 68fb ldr r3, [r7, #12] + 8002190: 681b ldr r3, [r3, #0] + 8002192: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8002194: 68fb ldr r3, [r7, #12] + 8002196: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002198: 1c9a adds r2, r3, #2 + 800219a: 68fb ldr r3, [r7, #12] + 800219c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 800219e: 68fb ldr r3, [r7, #12] + 80021a0: 8edb ldrh r3, [r3, #54] @ 0x36 + 80021a2: b29b uxth r3, r3 + 80021a4: 3b01 subs r3, #1 + 80021a6: b29a uxth r2, r3 + 80021a8: 68fb ldr r3, [r7, #12] + 80021aa: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 80021ac: e032 b.n 8002214 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 80021ae: 68fb ldr r3, [r7, #12] + 80021b0: 681b ldr r3, [r3, #0] + 80021b2: 689b ldr r3, [r3, #8] + 80021b4: f003 0302 and.w r3, r3, #2 + 80021b8: 2b02 cmp r3, #2 + 80021ba: d112 bne.n 80021e2 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 80021bc: 68fb ldr r3, [r7, #12] + 80021be: 6b1b ldr r3, [r3, #48] @ 0x30 + 80021c0: 881a ldrh r2, [r3, #0] + 80021c2: 68fb ldr r3, [r7, #12] + 80021c4: 681b ldr r3, [r3, #0] + 80021c6: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 80021c8: 68fb ldr r3, [r7, #12] + 80021ca: 6b1b ldr r3, [r3, #48] @ 0x30 + 80021cc: 1c9a adds r2, r3, #2 + 80021ce: 68fb ldr r3, [r7, #12] + 80021d0: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 80021d2: 68fb ldr r3, [r7, #12] + 80021d4: 8edb ldrh r3, [r3, #54] @ 0x36 + 80021d6: b29b uxth r3, r3 + 80021d8: 3b01 subs r3, #1 + 80021da: b29a uxth r2, r3 + 80021dc: 68fb ldr r3, [r7, #12] + 80021de: 86da strh r2, [r3, #54] @ 0x36 + 80021e0: e018 b.n 8002214 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 80021e2: f7fe fe6d bl 8000ec0 + 80021e6: 4602 mov r2, r0 + 80021e8: 69fb ldr r3, [r7, #28] + 80021ea: 1ad3 subs r3, r2, r3 + 80021ec: 683a ldr r2, [r7, #0] + 80021ee: 429a cmp r2, r3 + 80021f0: d803 bhi.n 80021fa + 80021f2: 683b ldr r3, [r7, #0] + 80021f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80021f8: d102 bne.n 8002200 + 80021fa: 683b ldr r3, [r7, #0] + 80021fc: 2b00 cmp r3, #0 + 80021fe: d109 bne.n 8002214 + { + hspi->State = HAL_SPI_STATE_READY; + 8002200: 68fb ldr r3, [r7, #12] + 8002202: 2201 movs r2, #1 + 8002204: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8002208: 68fb ldr r3, [r7, #12] + 800220a: 2200 movs r2, #0 + 800220c: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8002210: 2303 movs r3, #3 + 8002212: e082 b.n 800231a + while (hspi->TxXferCount > 0U) + 8002214: 68fb ldr r3, [r7, #12] + 8002216: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002218: b29b uxth r3, r3 + 800221a: 2b00 cmp r3, #0 + 800221c: d1c7 bne.n 80021ae + 800221e: e053 b.n 80022c8 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8002220: 68fb ldr r3, [r7, #12] + 8002222: 685b ldr r3, [r3, #4] + 8002224: 2b00 cmp r3, #0 + 8002226: d002 beq.n 800222e + 8002228: 8b7b ldrh r3, [r7, #26] + 800222a: 2b01 cmp r3, #1 + 800222c: d147 bne.n 80022be + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 800222e: 68fb ldr r3, [r7, #12] + 8002230: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002232: 68fb ldr r3, [r7, #12] + 8002234: 681b ldr r3, [r3, #0] + 8002236: 330c adds r3, #12 + 8002238: 7812 ldrb r2, [r2, #0] + 800223a: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 800223c: 68fb ldr r3, [r7, #12] + 800223e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002240: 1c5a adds r2, r3, #1 + 8002242: 68fb ldr r3, [r7, #12] + 8002244: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8002246: 68fb ldr r3, [r7, #12] + 8002248: 8edb ldrh r3, [r3, #54] @ 0x36 + 800224a: b29b uxth r3, r3 + 800224c: 3b01 subs r3, #1 + 800224e: b29a uxth r2, r3 + 8002250: 68fb ldr r3, [r7, #12] + 8002252: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8002254: e033 b.n 80022be + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8002256: 68fb ldr r3, [r7, #12] + 8002258: 681b ldr r3, [r3, #0] + 800225a: 689b ldr r3, [r3, #8] + 800225c: f003 0302 and.w r3, r3, #2 + 8002260: 2b02 cmp r3, #2 + 8002262: d113 bne.n 800228c + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8002264: 68fb ldr r3, [r7, #12] + 8002266: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002268: 68fb ldr r3, [r7, #12] + 800226a: 681b ldr r3, [r3, #0] + 800226c: 330c adds r3, #12 + 800226e: 7812 ldrb r2, [r2, #0] + 8002270: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8002272: 68fb ldr r3, [r7, #12] + 8002274: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002276: 1c5a adds r2, r3, #1 + 8002278: 68fb ldr r3, [r7, #12] + 800227a: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 800227c: 68fb ldr r3, [r7, #12] + 800227e: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002280: b29b uxth r3, r3 + 8002282: 3b01 subs r3, #1 + 8002284: b29a uxth r2, r3 + 8002286: 68fb ldr r3, [r7, #12] + 8002288: 86da strh r2, [r3, #54] @ 0x36 + 800228a: e018 b.n 80022be + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800228c: f7fe fe18 bl 8000ec0 + 8002290: 4602 mov r2, r0 + 8002292: 69fb ldr r3, [r7, #28] + 8002294: 1ad3 subs r3, r2, r3 + 8002296: 683a ldr r2, [r7, #0] + 8002298: 429a cmp r2, r3 + 800229a: d803 bhi.n 80022a4 + 800229c: 683b ldr r3, [r7, #0] + 800229e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80022a2: d102 bne.n 80022aa + 80022a4: 683b ldr r3, [r7, #0] + 80022a6: 2b00 cmp r3, #0 + 80022a8: d109 bne.n 80022be + { + hspi->State = HAL_SPI_STATE_READY; + 80022aa: 68fb ldr r3, [r7, #12] + 80022ac: 2201 movs r2, #1 + 80022ae: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 80022b2: 68fb ldr r3, [r7, #12] + 80022b4: 2200 movs r2, #0 + 80022b6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 80022ba: 2303 movs r3, #3 + 80022bc: e02d b.n 800231a + while (hspi->TxXferCount > 0U) + 80022be: 68fb ldr r3, [r7, #12] + 80022c0: 8edb ldrh r3, [r3, #54] @ 0x36 + 80022c2: b29b uxth r3, r3 + 80022c4: 2b00 cmp r3, #0 + 80022c6: d1c6 bne.n 8002256 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 80022c8: 69fa ldr r2, [r7, #28] + 80022ca: 6839 ldr r1, [r7, #0] + 80022cc: 68f8 ldr r0, [r7, #12] + 80022ce: f000 f8b1 bl 8002434 + 80022d2: 4603 mov r3, r0 + 80022d4: 2b00 cmp r3, #0 + 80022d6: d002 beq.n 80022de + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 80022d8: 68fb ldr r3, [r7, #12] + 80022da: 2220 movs r2, #32 + 80022dc: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 80022de: 68fb ldr r3, [r7, #12] + 80022e0: 689b ldr r3, [r3, #8] + 80022e2: 2b00 cmp r3, #0 + 80022e4: d10a bne.n 80022fc + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 80022e6: 2300 movs r3, #0 + 80022e8: 617b str r3, [r7, #20] + 80022ea: 68fb ldr r3, [r7, #12] + 80022ec: 681b ldr r3, [r3, #0] + 80022ee: 68db ldr r3, [r3, #12] + 80022f0: 617b str r3, [r7, #20] + 80022f2: 68fb ldr r3, [r7, #12] + 80022f4: 681b ldr r3, [r3, #0] + 80022f6: 689b ldr r3, [r3, #8] + 80022f8: 617b str r3, [r7, #20] + 80022fa: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 80022fc: 68fb ldr r3, [r7, #12] + 80022fe: 2201 movs r2, #1 + 8002300: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8002304: 68fb ldr r3, [r7, #12] + 8002306: 2200 movs r2, #0 + 8002308: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 800230c: 68fb ldr r3, [r7, #12] + 800230e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002310: 2b00 cmp r3, #0 + 8002312: d001 beq.n 8002318 + { + return HAL_ERROR; + 8002314: 2301 movs r3, #1 + 8002316: e000 b.n 800231a + } + else + { + return HAL_OK; + 8002318: 2300 movs r3, #0 + } +} + 800231a: 4618 mov r0, r3 + 800231c: 3720 adds r7, #32 + 800231e: 46bd mov sp, r7 + 8002320: bd80 pop {r7, pc} + ... + +08002324 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8002324: b580 push {r7, lr} + 8002326: b088 sub sp, #32 + 8002328: af00 add r7, sp, #0 + 800232a: 60f8 str r0, [r7, #12] + 800232c: 60b9 str r1, [r7, #8] + 800232e: 603b str r3, [r7, #0] + 8002330: 4613 mov r3, r2 + 8002332: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 8002334: f7fe fdc4 bl 8000ec0 + 8002338: 4602 mov r2, r0 + 800233a: 6abb ldr r3, [r7, #40] @ 0x28 + 800233c: 1a9b subs r3, r3, r2 + 800233e: 683a ldr r2, [r7, #0] + 8002340: 4413 add r3, r2 + 8002342: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 8002344: f7fe fdbc bl 8000ec0 + 8002348: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 800234a: 4b39 ldr r3, [pc, #228] @ (8002430 ) + 800234c: 681b ldr r3, [r3, #0] + 800234e: 015b lsls r3, r3, #5 + 8002350: 0d1b lsrs r3, r3, #20 + 8002352: 69fa ldr r2, [r7, #28] + 8002354: fb02 f303 mul.w r3, r2, r3 + 8002358: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 800235a: e054 b.n 8002406 + { + if (Timeout != HAL_MAX_DELAY) + 800235c: 683b ldr r3, [r7, #0] + 800235e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8002362: d050 beq.n 8002406 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8002364: f7fe fdac bl 8000ec0 + 8002368: 4602 mov r2, r0 + 800236a: 69bb ldr r3, [r7, #24] + 800236c: 1ad3 subs r3, r2, r3 + 800236e: 69fa ldr r2, [r7, #28] + 8002370: 429a cmp r2, r3 + 8002372: d902 bls.n 800237a + 8002374: 69fb ldr r3, [r7, #28] + 8002376: 2b00 cmp r3, #0 + 8002378: d13d bne.n 80023f6 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 800237a: 68fb ldr r3, [r7, #12] + 800237c: 681b ldr r3, [r3, #0] + 800237e: 685a ldr r2, [r3, #4] + 8002380: 68fb ldr r3, [r7, #12] + 8002382: 681b ldr r3, [r3, #0] + 8002384: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8002388: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800238a: 68fb ldr r3, [r7, #12] + 800238c: 685b ldr r3, [r3, #4] + 800238e: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002392: d111 bne.n 80023b8 + 8002394: 68fb ldr r3, [r7, #12] + 8002396: 689b ldr r3, [r3, #8] + 8002398: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 800239c: d004 beq.n 80023a8 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800239e: 68fb ldr r3, [r7, #12] + 80023a0: 689b ldr r3, [r3, #8] + 80023a2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 80023a6: d107 bne.n 80023b8 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 80023a8: 68fb ldr r3, [r7, #12] + 80023aa: 681b ldr r3, [r3, #0] + 80023ac: 681a ldr r2, [r3, #0] + 80023ae: 68fb ldr r3, [r7, #12] + 80023b0: 681b ldr r3, [r3, #0] + 80023b2: f022 0240 bic.w r2, r2, #64 @ 0x40 + 80023b6: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 80023b8: 68fb ldr r3, [r7, #12] + 80023ba: 6a9b ldr r3, [r3, #40] @ 0x28 + 80023bc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80023c0: d10f bne.n 80023e2 + { + SPI_RESET_CRC(hspi); + 80023c2: 68fb ldr r3, [r7, #12] + 80023c4: 681b ldr r3, [r3, #0] + 80023c6: 681a ldr r2, [r3, #0] + 80023c8: 68fb ldr r3, [r7, #12] + 80023ca: 681b ldr r3, [r3, #0] + 80023cc: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 80023d0: 601a str r2, [r3, #0] + 80023d2: 68fb ldr r3, [r7, #12] + 80023d4: 681b ldr r3, [r3, #0] + 80023d6: 681a ldr r2, [r3, #0] + 80023d8: 68fb ldr r3, [r7, #12] + 80023da: 681b ldr r3, [r3, #0] + 80023dc: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 80023e0: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 80023e2: 68fb ldr r3, [r7, #12] + 80023e4: 2201 movs r2, #1 + 80023e6: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80023ea: 68fb ldr r3, [r7, #12] + 80023ec: 2200 movs r2, #0 + 80023ee: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 80023f2: 2303 movs r3, #3 + 80023f4: e017 b.n 8002426 + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 80023f6: 697b ldr r3, [r7, #20] + 80023f8: 2b00 cmp r3, #0 + 80023fa: d101 bne.n 8002400 + { + tmp_timeout = 0U; + 80023fc: 2300 movs r3, #0 + 80023fe: 61fb str r3, [r7, #28] + } + count--; + 8002400: 697b ldr r3, [r7, #20] + 8002402: 3b01 subs r3, #1 + 8002404: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8002406: 68fb ldr r3, [r7, #12] + 8002408: 681b ldr r3, [r3, #0] + 800240a: 689a ldr r2, [r3, #8] + 800240c: 68bb ldr r3, [r7, #8] + 800240e: 4013 ands r3, r2 + 8002410: 68ba ldr r2, [r7, #8] + 8002412: 429a cmp r2, r3 + 8002414: bf0c ite eq + 8002416: 2301 moveq r3, #1 + 8002418: 2300 movne r3, #0 + 800241a: b2db uxtb r3, r3 + 800241c: 461a mov r2, r3 + 800241e: 79fb ldrb r3, [r7, #7] + 8002420: 429a cmp r2, r3 + 8002422: d19b bne.n 800235c + } + } + + return HAL_OK; + 8002424: 2300 movs r3, #0 +} + 8002426: 4618 mov r0, r3 + 8002428: 3720 adds r7, #32 + 800242a: 46bd mov sp, r7 + 800242c: bd80 pop {r7, pc} + 800242e: bf00 nop + 8002430: 20000004 .word 0x20000004 + +08002434 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 8002434: b580 push {r7, lr} + 8002436: b088 sub sp, #32 + 8002438: af02 add r7, sp, #8 + 800243a: 60f8 str r0, [r7, #12] + 800243c: 60b9 str r1, [r7, #8] + 800243e: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 8002440: 687b ldr r3, [r7, #4] + 8002442: 9300 str r3, [sp, #0] + 8002444: 68bb ldr r3, [r7, #8] + 8002446: 2201 movs r2, #1 + 8002448: 2102 movs r1, #2 + 800244a: 68f8 ldr r0, [r7, #12] + 800244c: f7ff ff6a bl 8002324 + 8002450: 4603 mov r3, r0 + 8002452: 2b00 cmp r3, #0 + 8002454: d007 beq.n 8002466 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002456: 68fb ldr r3, [r7, #12] + 8002458: 6d5b ldr r3, [r3, #84] @ 0x54 + 800245a: f043 0220 orr.w r2, r3, #32 + 800245e: 68fb ldr r3, [r7, #12] + 8002460: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8002462: 2303 movs r3, #3 + 8002464: e032 b.n 80024cc + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 8002466: 4b1b ldr r3, [pc, #108] @ (80024d4 ) + 8002468: 681b ldr r3, [r3, #0] + 800246a: 4a1b ldr r2, [pc, #108] @ (80024d8 ) + 800246c: fba2 2303 umull r2, r3, r2, r3 + 8002470: 0d5b lsrs r3, r3, #21 + 8002472: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8002476: fb02 f303 mul.w r3, r2, r3 + 800247a: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 800247c: 68fb ldr r3, [r7, #12] + 800247e: 685b ldr r3, [r3, #4] + 8002480: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002484: d112 bne.n 80024ac + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8002486: 687b ldr r3, [r7, #4] + 8002488: 9300 str r3, [sp, #0] + 800248a: 68bb ldr r3, [r7, #8] + 800248c: 2200 movs r2, #0 + 800248e: 2180 movs r1, #128 @ 0x80 + 8002490: 68f8 ldr r0, [r7, #12] + 8002492: f7ff ff47 bl 8002324 + 8002496: 4603 mov r3, r0 + 8002498: 2b00 cmp r3, #0 + 800249a: d016 beq.n 80024ca + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800249c: 68fb ldr r3, [r7, #12] + 800249e: 6d5b ldr r3, [r3, #84] @ 0x54 + 80024a0: f043 0220 orr.w r2, r3, #32 + 80024a4: 68fb ldr r3, [r7, #12] + 80024a6: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 80024a8: 2303 movs r3, #3 + 80024aa: e00f b.n 80024cc + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 80024ac: 697b ldr r3, [r7, #20] + 80024ae: 2b00 cmp r3, #0 + 80024b0: d00a beq.n 80024c8 + { + break; + } + count--; + 80024b2: 697b ldr r3, [r7, #20] + 80024b4: 3b01 subs r3, #1 + 80024b6: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 80024b8: 68fb ldr r3, [r7, #12] + 80024ba: 681b ldr r3, [r3, #0] + 80024bc: 689b ldr r3, [r3, #8] + 80024be: f003 0380 and.w r3, r3, #128 @ 0x80 + 80024c2: 2b80 cmp r3, #128 @ 0x80 + 80024c4: d0f2 beq.n 80024ac + 80024c6: e000 b.n 80024ca + break; + 80024c8: bf00 nop + } + + return HAL_OK; + 80024ca: 2300 movs r3, #0 +} + 80024cc: 4618 mov r0, r3 + 80024ce: 3718 adds r7, #24 + 80024d0: 46bd mov sp, r7 + 80024d2: bd80 pop {r7, pc} + 80024d4: 20000004 .word 0x20000004 + 80024d8: 165e9f81 .word 0x165e9f81 + +080024dc : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 80024dc: b580 push {r7, lr} + 80024de: b082 sub sp, #8 + 80024e0: af00 add r7, sp, #0 + 80024e2: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80024e4: 687b ldr r3, [r7, #4] + 80024e6: 2b00 cmp r3, #0 + 80024e8: d101 bne.n 80024ee + { + return HAL_ERROR; + 80024ea: 2301 movs r3, #1 + 80024ec: e031 b.n 8002552 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80024ee: 687b ldr r3, [r7, #4] + 80024f0: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 80024f4: b2db uxtb r3, r3 + 80024f6: 2b00 cmp r3, #0 + 80024f8: d106 bne.n 8002508 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80024fa: 687b ldr r3, [r7, #4] + 80024fc: 2200 movs r2, #0 + 80024fe: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8002502: 6878 ldr r0, [r7, #4] + 8002504: f7fe fac2 bl 8000a8c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002508: 687b ldr r3, [r7, #4] + 800250a: 2202 movs r2, #2 + 800250c: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002510: 687b ldr r3, [r7, #4] + 8002512: 681a ldr r2, [r3, #0] + 8002514: 687b ldr r3, [r7, #4] + 8002516: 3304 adds r3, #4 + 8002518: 4619 mov r1, r3 + 800251a: 4610 mov r0, r2 + 800251c: f000 fbc8 bl 8002cb0 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002520: 687b ldr r3, [r7, #4] + 8002522: 2201 movs r2, #1 + 8002524: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8002528: 687b ldr r3, [r7, #4] + 800252a: 2201 movs r2, #1 + 800252c: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002530: 687b ldr r3, [r7, #4] + 8002532: 2201 movs r2, #1 + 8002534: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002538: 687b ldr r3, [r7, #4] + 800253a: 2201 movs r2, #1 + 800253c: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002540: 687b ldr r3, [r7, #4] + 8002542: 2201 movs r2, #1 + 8002544: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8002548: 687b ldr r3, [r7, #4] + 800254a: 2201 movs r2, #1 + 800254c: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 8002550: 2300 movs r3, #0 +} + 8002552: 4618 mov r0, r3 + 8002554: 3708 adds r7, #8 + 8002556: 46bd mov sp, r7 + 8002558: bd80 pop {r7, pc} + ... + +0800255c : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 800255c: b480 push {r7} + 800255e: b085 sub sp, #20 + 8002560: af00 add r7, sp, #0 + 8002562: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + 8002564: 687b ldr r3, [r7, #4] + 8002566: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 800256a: b2db uxtb r3, r3 + 800256c: 2b01 cmp r3, #1 + 800256e: d001 beq.n 8002574 + { + return HAL_ERROR; + 8002570: 2301 movs r3, #1 + 8002572: e03a b.n 80025ea + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002574: 687b ldr r3, [r7, #4] + 8002576: 2202 movs r2, #2 + 8002578: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 800257c: 687b ldr r3, [r7, #4] + 800257e: 681b ldr r3, [r3, #0] + 8002580: 68da ldr r2, [r3, #12] + 8002582: 687b ldr r3, [r7, #4] + 8002584: 681b ldr r3, [r3, #0] + 8002586: f042 0201 orr.w r2, r2, #1 + 800258a: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 800258c: 687b ldr r3, [r7, #4] + 800258e: 681b ldr r3, [r3, #0] + 8002590: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002594: d00e beq.n 80025b4 + 8002596: 687b ldr r3, [r7, #4] + 8002598: 681b ldr r3, [r3, #0] + 800259a: 4a16 ldr r2, [pc, #88] @ (80025f4 ) + 800259c: 4293 cmp r3, r2 + 800259e: d009 beq.n 80025b4 + 80025a0: 687b ldr r3, [r7, #4] + 80025a2: 681b ldr r3, [r3, #0] + 80025a4: 4a14 ldr r2, [pc, #80] @ (80025f8 ) + 80025a6: 4293 cmp r3, r2 + 80025a8: d004 beq.n 80025b4 + 80025aa: 687b ldr r3, [r7, #4] + 80025ac: 681b ldr r3, [r3, #0] + 80025ae: 4a13 ldr r2, [pc, #76] @ (80025fc ) + 80025b0: 4293 cmp r3, r2 + 80025b2: d111 bne.n 80025d8 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 80025b4: 687b ldr r3, [r7, #4] + 80025b6: 681b ldr r3, [r3, #0] + 80025b8: 689b ldr r3, [r3, #8] + 80025ba: f003 0307 and.w r3, r3, #7 + 80025be: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80025c0: 68fb ldr r3, [r7, #12] + 80025c2: 2b06 cmp r3, #6 + 80025c4: d010 beq.n 80025e8 + { + __HAL_TIM_ENABLE(htim); + 80025c6: 687b ldr r3, [r7, #4] + 80025c8: 681b ldr r3, [r3, #0] + 80025ca: 681a ldr r2, [r3, #0] + 80025cc: 687b ldr r3, [r7, #4] + 80025ce: 681b ldr r3, [r3, #0] + 80025d0: f042 0201 orr.w r2, r2, #1 + 80025d4: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80025d6: e007 b.n 80025e8 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 80025d8: 687b ldr r3, [r7, #4] + 80025da: 681b ldr r3, [r3, #0] + 80025dc: 681a ldr r2, [r3, #0] + 80025de: 687b ldr r3, [r7, #4] + 80025e0: 681b ldr r3, [r3, #0] + 80025e2: f042 0201 orr.w r2, r2, #1 + 80025e6: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 80025e8: 2300 movs r3, #0 +} + 80025ea: 4618 mov r0, r3 + 80025ec: 3714 adds r7, #20 + 80025ee: 46bd mov sp, r7 + 80025f0: bc80 pop {r7} + 80025f2: 4770 bx lr + 80025f4: 40000400 .word 0x40000400 + 80025f8: 40000800 .word 0x40000800 + 80025fc: 40010800 .word 0x40010800 + +08002600 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8002600: b580 push {r7, lr} + 8002602: b082 sub sp, #8 + 8002604: af00 add r7, sp, #0 + 8002606: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8002608: 687b ldr r3, [r7, #4] + 800260a: 2b00 cmp r3, #0 + 800260c: d101 bne.n 8002612 + { + return HAL_ERROR; + 800260e: 2301 movs r3, #1 + 8002610: e031 b.n 8002676 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8002612: 687b ldr r3, [r7, #4] + 8002614: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 8002618: b2db uxtb r3, r3 + 800261a: 2b00 cmp r3, #0 + 800261c: d106 bne.n 800262c + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 800261e: 687b ldr r3, [r7, #4] + 8002620: 2200 movs r2, #0 + 8002622: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 8002626: 6878 ldr r0, [r7, #4] + 8002628: f000 f829 bl 800267e +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 800262c: 687b ldr r3, [r7, #4] + 800262e: 2202 movs r2, #2 + 8002630: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002634: 687b ldr r3, [r7, #4] + 8002636: 681a ldr r2, [r3, #0] + 8002638: 687b ldr r3, [r7, #4] + 800263a: 3304 adds r3, #4 + 800263c: 4619 mov r1, r3 + 800263e: 4610 mov r0, r2 + 8002640: f000 fb36 bl 8002cb0 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002644: 687b ldr r3, [r7, #4] + 8002646: 2201 movs r2, #1 + 8002648: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 800264c: 687b ldr r3, [r7, #4] + 800264e: 2201 movs r2, #1 + 8002650: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002654: 687b ldr r3, [r7, #4] + 8002656: 2201 movs r2, #1 + 8002658: f883 203b strb.w r2, [r3, #59] @ 0x3b + 800265c: 687b ldr r3, [r7, #4] + 800265e: 2201 movs r2, #1 + 8002660: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002664: 687b ldr r3, [r7, #4] + 8002666: 2201 movs r2, #1 + 8002668: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 800266c: 687b ldr r3, [r7, #4] + 800266e: 2201 movs r2, #1 + 8002670: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 8002674: 2300 movs r3, #0 +} + 8002676: 4618 mov r0, r3 + 8002678: 3708 adds r7, #8 + 800267a: 46bd mov sp, r7 + 800267c: bd80 pop {r7, pc} + +0800267e : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 800267e: b480 push {r7} + 8002680: b083 sub sp, #12 + 8002682: af00 add r7, sp, #0 + 8002684: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 8002686: bf00 nop + 8002688: 370c adds r7, #12 + 800268a: 46bd mov sp, r7 + 800268c: bc80 pop {r7} + 800268e: 4770 bx lr + +08002690 : + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 8002690: b580 push {r7, lr} + 8002692: b084 sub sp, #16 + 8002694: af00 add r7, sp, #0 + 8002696: 6078 str r0, [r7, #4] + 8002698: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 800269a: 683b ldr r3, [r7, #0] + 800269c: 2b00 cmp r3, #0 + 800269e: d109 bne.n 80026b4 + 80026a0: 687b ldr r3, [r7, #4] + 80026a2: f893 303a ldrb.w r3, [r3, #58] @ 0x3a + 80026a6: b2db uxtb r3, r3 + 80026a8: 2b01 cmp r3, #1 + 80026aa: bf14 ite ne + 80026ac: 2301 movne r3, #1 + 80026ae: 2300 moveq r3, #0 + 80026b0: b2db uxtb r3, r3 + 80026b2: e022 b.n 80026fa + 80026b4: 683b ldr r3, [r7, #0] + 80026b6: 2b04 cmp r3, #4 + 80026b8: d109 bne.n 80026ce + 80026ba: 687b ldr r3, [r7, #4] + 80026bc: f893 303b ldrb.w r3, [r3, #59] @ 0x3b + 80026c0: b2db uxtb r3, r3 + 80026c2: 2b01 cmp r3, #1 + 80026c4: bf14 ite ne + 80026c6: 2301 movne r3, #1 + 80026c8: 2300 moveq r3, #0 + 80026ca: b2db uxtb r3, r3 + 80026cc: e015 b.n 80026fa + 80026ce: 683b ldr r3, [r7, #0] + 80026d0: 2b08 cmp r3, #8 + 80026d2: d109 bne.n 80026e8 + 80026d4: 687b ldr r3, [r7, #4] + 80026d6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 80026da: b2db uxtb r3, r3 + 80026dc: 2b01 cmp r3, #1 + 80026de: bf14 ite ne + 80026e0: 2301 movne r3, #1 + 80026e2: 2300 moveq r3, #0 + 80026e4: b2db uxtb r3, r3 + 80026e6: e008 b.n 80026fa + 80026e8: 687b ldr r3, [r7, #4] + 80026ea: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 80026ee: b2db uxtb r3, r3 + 80026f0: 2b01 cmp r3, #1 + 80026f2: bf14 ite ne + 80026f4: 2301 movne r3, #1 + 80026f6: 2300 moveq r3, #0 + 80026f8: b2db uxtb r3, r3 + 80026fa: 2b00 cmp r3, #0 + 80026fc: d001 beq.n 8002702 + { + return HAL_ERROR; + 80026fe: 2301 movs r3, #1 + 8002700: e051 b.n 80027a6 + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 8002702: 683b ldr r3, [r7, #0] + 8002704: 2b00 cmp r3, #0 + 8002706: d104 bne.n 8002712 + 8002708: 687b ldr r3, [r7, #4] + 800270a: 2202 movs r2, #2 + 800270c: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002710: e013 b.n 800273a + 8002712: 683b ldr r3, [r7, #0] + 8002714: 2b04 cmp r3, #4 + 8002716: d104 bne.n 8002722 + 8002718: 687b ldr r3, [r7, #4] + 800271a: 2202 movs r2, #2 + 800271c: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002720: e00b b.n 800273a + 8002722: 683b ldr r3, [r7, #0] + 8002724: 2b08 cmp r3, #8 + 8002726: d104 bne.n 8002732 + 8002728: 687b ldr r3, [r7, #4] + 800272a: 2202 movs r2, #2 + 800272c: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002730: e003 b.n 800273a + 8002732: 687b ldr r3, [r7, #4] + 8002734: 2202 movs r2, #2 + 8002736: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 800273a: 687b ldr r3, [r7, #4] + 800273c: 681b ldr r3, [r3, #0] + 800273e: 2201 movs r2, #1 + 8002740: 6839 ldr r1, [r7, #0] + 8002742: 4618 mov r0, r3 + 8002744: f000 fcb5 bl 80030b2 + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8002748: 687b ldr r3, [r7, #4] + 800274a: 681b ldr r3, [r3, #0] + 800274c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002750: d00e beq.n 8002770 + 8002752: 687b ldr r3, [r7, #4] + 8002754: 681b ldr r3, [r3, #0] + 8002756: 4a16 ldr r2, [pc, #88] @ (80027b0 ) + 8002758: 4293 cmp r3, r2 + 800275a: d009 beq.n 8002770 + 800275c: 687b ldr r3, [r7, #4] + 800275e: 681b ldr r3, [r3, #0] + 8002760: 4a14 ldr r2, [pc, #80] @ (80027b4 ) + 8002762: 4293 cmp r3, r2 + 8002764: d004 beq.n 8002770 + 8002766: 687b ldr r3, [r7, #4] + 8002768: 681b ldr r3, [r3, #0] + 800276a: 4a13 ldr r2, [pc, #76] @ (80027b8 ) + 800276c: 4293 cmp r3, r2 + 800276e: d111 bne.n 8002794 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8002770: 687b ldr r3, [r7, #4] + 8002772: 681b ldr r3, [r3, #0] + 8002774: 689b ldr r3, [r3, #8] + 8002776: f003 0307 and.w r3, r3, #7 + 800277a: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 800277c: 68fb ldr r3, [r7, #12] + 800277e: 2b06 cmp r3, #6 + 8002780: d010 beq.n 80027a4 + { + __HAL_TIM_ENABLE(htim); + 8002782: 687b ldr r3, [r7, #4] + 8002784: 681b ldr r3, [r3, #0] + 8002786: 681a ldr r2, [r3, #0] + 8002788: 687b ldr r3, [r7, #4] + 800278a: 681b ldr r3, [r3, #0] + 800278c: f042 0201 orr.w r2, r2, #1 + 8002790: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8002792: e007 b.n 80027a4 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 8002794: 687b ldr r3, [r7, #4] + 8002796: 681b ldr r3, [r3, #0] + 8002798: 681a ldr r2, [r3, #0] + 800279a: 687b ldr r3, [r7, #4] + 800279c: 681b ldr r3, [r3, #0] + 800279e: f042 0201 orr.w r2, r2, #1 + 80027a2: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 80027a4: 2300 movs r3, #0 +} + 80027a6: 4618 mov r0, r3 + 80027a8: 3710 adds r7, #16 + 80027aa: 46bd mov sp, r7 + 80027ac: bd80 pop {r7, pc} + 80027ae: bf00 nop + 80027b0: 40000400 .word 0x40000400 + 80027b4: 40000800 .word 0x40000800 + 80027b8: 40010800 .word 0x40010800 + +080027bc : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 80027bc: b580 push {r7, lr} + 80027be: b084 sub sp, #16 + 80027c0: af00 add r7, sp, #0 + 80027c2: 6078 str r0, [r7, #4] + uint32_t itsource = htim->Instance->DIER; + 80027c4: 687b ldr r3, [r7, #4] + 80027c6: 681b ldr r3, [r3, #0] + 80027c8: 68db ldr r3, [r3, #12] + 80027ca: 60fb str r3, [r7, #12] + uint32_t itflag = htim->Instance->SR; + 80027cc: 687b ldr r3, [r7, #4] + 80027ce: 681b ldr r3, [r3, #0] + 80027d0: 691b ldr r3, [r3, #16] + 80027d2: 60bb str r3, [r7, #8] + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + 80027d4: 68bb ldr r3, [r7, #8] + 80027d6: f003 0302 and.w r3, r3, #2 + 80027da: 2b00 cmp r3, #0 + 80027dc: d020 beq.n 8002820 + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + 80027de: 68fb ldr r3, [r7, #12] + 80027e0: f003 0302 and.w r3, r3, #2 + 80027e4: 2b00 cmp r3, #0 + 80027e6: d01b beq.n 8002820 + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + 80027e8: 687b ldr r3, [r7, #4] + 80027ea: 681b ldr r3, [r3, #0] + 80027ec: f06f 0202 mvn.w r2, #2 + 80027f0: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 80027f2: 687b ldr r3, [r7, #4] + 80027f4: 2201 movs r2, #1 + 80027f6: 761a strb r2, [r3, #24] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 80027f8: 687b ldr r3, [r7, #4] + 80027fa: 681b ldr r3, [r3, #0] + 80027fc: 699b ldr r3, [r3, #24] + 80027fe: f003 0303 and.w r3, r3, #3 + 8002802: 2b00 cmp r3, #0 + 8002804: d003 beq.n 800280e + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002806: 6878 ldr r0, [r7, #4] + 8002808: f000 fa36 bl 8002c78 + 800280c: e005 b.n 800281a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800280e: 6878 ldr r0, [r7, #4] + 8002810: f000 fa29 bl 8002c66 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002814: 6878 ldr r0, [r7, #4] + 8002816: f000 fa38 bl 8002c8a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 800281a: 687b ldr r3, [r7, #4] + 800281c: 2200 movs r2, #0 + 800281e: 761a strb r2, [r3, #24] + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + 8002820: 68bb ldr r3, [r7, #8] + 8002822: f003 0304 and.w r3, r3, #4 + 8002826: 2b00 cmp r3, #0 + 8002828: d020 beq.n 800286c + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + 800282a: 68fb ldr r3, [r7, #12] + 800282c: f003 0304 and.w r3, r3, #4 + 8002830: 2b00 cmp r3, #0 + 8002832: d01b beq.n 800286c + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + 8002834: 687b ldr r3, [r7, #4] + 8002836: 681b ldr r3, [r3, #0] + 8002838: f06f 0204 mvn.w r2, #4 + 800283c: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 800283e: 687b ldr r3, [r7, #4] + 8002840: 2202 movs r2, #2 + 8002842: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8002844: 687b ldr r3, [r7, #4] + 8002846: 681b ldr r3, [r3, #0] + 8002848: 699b ldr r3, [r3, #24] + 800284a: f403 7340 and.w r3, r3, #768 @ 0x300 + 800284e: 2b00 cmp r3, #0 + 8002850: d003 beq.n 800285a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002852: 6878 ldr r0, [r7, #4] + 8002854: f000 fa10 bl 8002c78 + 8002858: e005 b.n 8002866 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 800285a: 6878 ldr r0, [r7, #4] + 800285c: f000 fa03 bl 8002c66 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002860: 6878 ldr r0, [r7, #4] + 8002862: f000 fa12 bl 8002c8a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002866: 687b ldr r3, [r7, #4] + 8002868: 2200 movs r2, #0 + 800286a: 761a strb r2, [r3, #24] + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + 800286c: 68bb ldr r3, [r7, #8] + 800286e: f003 0308 and.w r3, r3, #8 + 8002872: 2b00 cmp r3, #0 + 8002874: d020 beq.n 80028b8 + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + 8002876: 68fb ldr r3, [r7, #12] + 8002878: f003 0308 and.w r3, r3, #8 + 800287c: 2b00 cmp r3, #0 + 800287e: d01b beq.n 80028b8 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + 8002880: 687b ldr r3, [r7, #4] + 8002882: 681b ldr r3, [r3, #0] + 8002884: f06f 0208 mvn.w r2, #8 + 8002888: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 800288a: 687b ldr r3, [r7, #4] + 800288c: 2204 movs r2, #4 + 800288e: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 8002890: 687b ldr r3, [r7, #4] + 8002892: 681b ldr r3, [r3, #0] + 8002894: 69db ldr r3, [r3, #28] + 8002896: f003 0303 and.w r3, r3, #3 + 800289a: 2b00 cmp r3, #0 + 800289c: d003 beq.n 80028a6 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 800289e: 6878 ldr r0, [r7, #4] + 80028a0: f000 f9ea bl 8002c78 + 80028a4: e005 b.n 80028b2 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80028a6: 6878 ldr r0, [r7, #4] + 80028a8: f000 f9dd bl 8002c66 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80028ac: 6878 ldr r0, [r7, #4] + 80028ae: f000 f9ec bl 8002c8a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80028b2: 687b ldr r3, [r7, #4] + 80028b4: 2200 movs r2, #0 + 80028b6: 761a strb r2, [r3, #24] + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + 80028b8: 68bb ldr r3, [r7, #8] + 80028ba: f003 0310 and.w r3, r3, #16 + 80028be: 2b00 cmp r3, #0 + 80028c0: d020 beq.n 8002904 + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + 80028c2: 68fb ldr r3, [r7, #12] + 80028c4: f003 0310 and.w r3, r3, #16 + 80028c8: 2b00 cmp r3, #0 + 80028ca: d01b beq.n 8002904 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + 80028cc: 687b ldr r3, [r7, #4] + 80028ce: 681b ldr r3, [r3, #0] + 80028d0: f06f 0210 mvn.w r2, #16 + 80028d4: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 80028d6: 687b ldr r3, [r7, #4] + 80028d8: 2208 movs r2, #8 + 80028da: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 80028dc: 687b ldr r3, [r7, #4] + 80028de: 681b ldr r3, [r3, #0] + 80028e0: 69db ldr r3, [r3, #28] + 80028e2: f403 7340 and.w r3, r3, #768 @ 0x300 + 80028e6: 2b00 cmp r3, #0 + 80028e8: d003 beq.n 80028f2 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 80028ea: 6878 ldr r0, [r7, #4] + 80028ec: f000 f9c4 bl 8002c78 + 80028f0: e005 b.n 80028fe + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 80028f2: 6878 ldr r0, [r7, #4] + 80028f4: f000 f9b7 bl 8002c66 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 80028f8: 6878 ldr r0, [r7, #4] + 80028fa: f000 f9c6 bl 8002c8a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 80028fe: 687b ldr r3, [r7, #4] + 8002900: 2200 movs r2, #0 + 8002902: 761a strb r2, [r3, #24] + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + 8002904: 68bb ldr r3, [r7, #8] + 8002906: f003 0301 and.w r3, r3, #1 + 800290a: 2b00 cmp r3, #0 + 800290c: d00c beq.n 8002928 + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + 800290e: 68fb ldr r3, [r7, #12] + 8002910: f003 0301 and.w r3, r3, #1 + 8002914: 2b00 cmp r3, #0 + 8002916: d007 beq.n 8002928 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); + 8002918: 687b ldr r3, [r7, #4] + 800291a: 681b ldr r3, [r3, #0] + 800291c: f06f 0201 mvn.w r2, #1 + 8002920: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 8002922: 6878 ldr r0, [r7, #4] + 8002924: f7fd ffec bl 8000900 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + 8002928: 68bb ldr r3, [r7, #8] + 800292a: f003 0340 and.w r3, r3, #64 @ 0x40 + 800292e: 2b00 cmp r3, #0 + 8002930: d00c beq.n 800294c + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + 8002932: 68fb ldr r3, [r7, #12] + 8002934: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002938: 2b00 cmp r3, #0 + 800293a: d007 beq.n 800294c + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); + 800293c: 687b ldr r3, [r7, #4] + 800293e: 681b ldr r3, [r3, #0] + 8002940: f06f 0240 mvn.w r2, #64 @ 0x40 + 8002944: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 8002946: 6878 ldr r0, [r7, #4] + 8002948: f000 f9a8 bl 8002c9c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 800294c: bf00 nop + 800294e: 3710 adds r7, #16 + 8002950: 46bd mov sp, r7 + 8002952: bd80 pop {r7, pc} + +08002954 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8002954: b580 push {r7, lr} + 8002956: b086 sub sp, #24 + 8002958: af00 add r7, sp, #0 + 800295a: 60f8 str r0, [r7, #12] + 800295c: 60b9 str r1, [r7, #8] + 800295e: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002960: 2300 movs r3, #0 + 8002962: 75fb strb r3, [r7, #23] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8002964: 68fb ldr r3, [r7, #12] + 8002966: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 800296a: 2b01 cmp r3, #1 + 800296c: d101 bne.n 8002972 + 800296e: 2302 movs r3, #2 + 8002970: e0ae b.n 8002ad0 + 8002972: 68fb ldr r3, [r7, #12] + 8002974: 2201 movs r2, #1 + 8002976: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + switch (Channel) + 800297a: 687b ldr r3, [r7, #4] + 800297c: 2b0c cmp r3, #12 + 800297e: f200 809f bhi.w 8002ac0 + 8002982: a201 add r2, pc, #4 @ (adr r2, 8002988 ) + 8002984: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002988: 080029bd .word 0x080029bd + 800298c: 08002ac1 .word 0x08002ac1 + 8002990: 08002ac1 .word 0x08002ac1 + 8002994: 08002ac1 .word 0x08002ac1 + 8002998: 080029fd .word 0x080029fd + 800299c: 08002ac1 .word 0x08002ac1 + 80029a0: 08002ac1 .word 0x08002ac1 + 80029a4: 08002ac1 .word 0x08002ac1 + 80029a8: 08002a3f .word 0x08002a3f + 80029ac: 08002ac1 .word 0x08002ac1 + 80029b0: 08002ac1 .word 0x08002ac1 + 80029b4: 08002ac1 .word 0x08002ac1 + 80029b8: 08002a7f .word 0x08002a7f + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 80029bc: 68fb ldr r3, [r7, #12] + 80029be: 681b ldr r3, [r3, #0] + 80029c0: 68b9 ldr r1, [r7, #8] + 80029c2: 4618 mov r0, r3 + 80029c4: f000 f9ea bl 8002d9c + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 80029c8: 68fb ldr r3, [r7, #12] + 80029ca: 681b ldr r3, [r3, #0] + 80029cc: 699a ldr r2, [r3, #24] + 80029ce: 68fb ldr r3, [r7, #12] + 80029d0: 681b ldr r3, [r3, #0] + 80029d2: f042 0208 orr.w r2, r2, #8 + 80029d6: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 80029d8: 68fb ldr r3, [r7, #12] + 80029da: 681b ldr r3, [r3, #0] + 80029dc: 699a ldr r2, [r3, #24] + 80029de: 68fb ldr r3, [r7, #12] + 80029e0: 681b ldr r3, [r3, #0] + 80029e2: f022 0204 bic.w r2, r2, #4 + 80029e6: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 80029e8: 68fb ldr r3, [r7, #12] + 80029ea: 681b ldr r3, [r3, #0] + 80029ec: 6999 ldr r1, [r3, #24] + 80029ee: 68bb ldr r3, [r7, #8] + 80029f0: 68da ldr r2, [r3, #12] + 80029f2: 68fb ldr r3, [r7, #12] + 80029f4: 681b ldr r3, [r3, #0] + 80029f6: 430a orrs r2, r1 + 80029f8: 619a str r2, [r3, #24] + break; + 80029fa: e064 b.n 8002ac6 + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 80029fc: 68fb ldr r3, [r7, #12] + 80029fe: 681b ldr r3, [r3, #0] + 8002a00: 68b9 ldr r1, [r7, #8] + 8002a02: 4618 mov r0, r3 + 8002a04: f000 fa06 bl 8002e14 + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 8002a08: 68fb ldr r3, [r7, #12] + 8002a0a: 681b ldr r3, [r3, #0] + 8002a0c: 699a ldr r2, [r3, #24] + 8002a0e: 68fb ldr r3, [r7, #12] + 8002a10: 681b ldr r3, [r3, #0] + 8002a12: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8002a16: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 8002a18: 68fb ldr r3, [r7, #12] + 8002a1a: 681b ldr r3, [r3, #0] + 8002a1c: 699a ldr r2, [r3, #24] + 8002a1e: 68fb ldr r3, [r7, #12] + 8002a20: 681b ldr r3, [r3, #0] + 8002a22: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8002a26: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 8002a28: 68fb ldr r3, [r7, #12] + 8002a2a: 681b ldr r3, [r3, #0] + 8002a2c: 6999 ldr r1, [r3, #24] + 8002a2e: 68bb ldr r3, [r7, #8] + 8002a30: 68db ldr r3, [r3, #12] + 8002a32: 021a lsls r2, r3, #8 + 8002a34: 68fb ldr r3, [r7, #12] + 8002a36: 681b ldr r3, [r3, #0] + 8002a38: 430a orrs r2, r1 + 8002a3a: 619a str r2, [r3, #24] + break; + 8002a3c: e043 b.n 8002ac6 + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 8002a3e: 68fb ldr r3, [r7, #12] + 8002a40: 681b ldr r3, [r3, #0] + 8002a42: 68b9 ldr r1, [r7, #8] + 8002a44: 4618 mov r0, r3 + 8002a46: f000 fa23 bl 8002e90 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 8002a4a: 68fb ldr r3, [r7, #12] + 8002a4c: 681b ldr r3, [r3, #0] + 8002a4e: 69da ldr r2, [r3, #28] + 8002a50: 68fb ldr r3, [r7, #12] + 8002a52: 681b ldr r3, [r3, #0] + 8002a54: f042 0208 orr.w r2, r2, #8 + 8002a58: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 8002a5a: 68fb ldr r3, [r7, #12] + 8002a5c: 681b ldr r3, [r3, #0] + 8002a5e: 69da ldr r2, [r3, #28] + 8002a60: 68fb ldr r3, [r7, #12] + 8002a62: 681b ldr r3, [r3, #0] + 8002a64: f022 0204 bic.w r2, r2, #4 + 8002a68: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 8002a6a: 68fb ldr r3, [r7, #12] + 8002a6c: 681b ldr r3, [r3, #0] + 8002a6e: 69d9 ldr r1, [r3, #28] + 8002a70: 68bb ldr r3, [r7, #8] + 8002a72: 68da ldr r2, [r3, #12] + 8002a74: 68fb ldr r3, [r7, #12] + 8002a76: 681b ldr r3, [r3, #0] + 8002a78: 430a orrs r2, r1 + 8002a7a: 61da str r2, [r3, #28] + break; + 8002a7c: e023 b.n 8002ac6 + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 8002a7e: 68fb ldr r3, [r7, #12] + 8002a80: 681b ldr r3, [r3, #0] + 8002a82: 68b9 ldr r1, [r7, #8] + 8002a84: 4618 mov r0, r3 + 8002a86: f000 fa40 bl 8002f0a + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 8002a8a: 68fb ldr r3, [r7, #12] + 8002a8c: 681b ldr r3, [r3, #0] + 8002a8e: 69da ldr r2, [r3, #28] + 8002a90: 68fb ldr r3, [r7, #12] + 8002a92: 681b ldr r3, [r3, #0] + 8002a94: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8002a98: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 8002a9a: 68fb ldr r3, [r7, #12] + 8002a9c: 681b ldr r3, [r3, #0] + 8002a9e: 69da ldr r2, [r3, #28] + 8002aa0: 68fb ldr r3, [r7, #12] + 8002aa2: 681b ldr r3, [r3, #0] + 8002aa4: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8002aa8: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 8002aaa: 68fb ldr r3, [r7, #12] + 8002aac: 681b ldr r3, [r3, #0] + 8002aae: 69d9 ldr r1, [r3, #28] + 8002ab0: 68bb ldr r3, [r7, #8] + 8002ab2: 68db ldr r3, [r3, #12] + 8002ab4: 021a lsls r2, r3, #8 + 8002ab6: 68fb ldr r3, [r7, #12] + 8002ab8: 681b ldr r3, [r3, #0] + 8002aba: 430a orrs r2, r1 + 8002abc: 61da str r2, [r3, #28] + break; + 8002abe: e002 b.n 8002ac6 + } + + default: + status = HAL_ERROR; + 8002ac0: 2301 movs r3, #1 + 8002ac2: 75fb strb r3, [r7, #23] + break; + 8002ac4: bf00 nop + } + + __HAL_UNLOCK(htim); + 8002ac6: 68fb ldr r3, [r7, #12] + 8002ac8: 2200 movs r2, #0 + 8002aca: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 8002ace: 7dfb ldrb r3, [r7, #23] +} + 8002ad0: 4618 mov r0, r3 + 8002ad2: 3718 adds r7, #24 + 8002ad4: 46bd mov sp, r7 + 8002ad6: bd80 pop {r7, pc} + +08002ad8 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 8002ad8: b580 push {r7, lr} + 8002ada: b084 sub sp, #16 + 8002adc: af00 add r7, sp, #0 + 8002ade: 6078 str r0, [r7, #4] + 8002ae0: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8002ae2: 2300 movs r3, #0 + 8002ae4: 73fb strb r3, [r7, #15] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 8002ae6: 687b ldr r3, [r7, #4] + 8002ae8: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 8002aec: 2b01 cmp r3, #1 + 8002aee: d101 bne.n 8002af4 + 8002af0: 2302 movs r3, #2 + 8002af2: e0b4 b.n 8002c5e + 8002af4: 687b ldr r3, [r7, #4] + 8002af6: 2201 movs r2, #1 + 8002af8: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + htim->State = HAL_TIM_STATE_BUSY; + 8002afc: 687b ldr r3, [r7, #4] + 8002afe: 2202 movs r2, #2 + 8002b00: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 8002b04: 687b ldr r3, [r7, #4] + 8002b06: 681b ldr r3, [r3, #0] + 8002b08: 689b ldr r3, [r3, #8] + 8002b0a: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8002b0c: 68bb ldr r3, [r7, #8] + 8002b0e: f023 0377 bic.w r3, r3, #119 @ 0x77 + 8002b12: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8002b14: 68bb ldr r3, [r7, #8] + 8002b16: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 8002b1a: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 8002b1c: 687b ldr r3, [r7, #4] + 8002b1e: 681b ldr r3, [r3, #0] + 8002b20: 68ba ldr r2, [r7, #8] + 8002b22: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8002b24: 683b ldr r3, [r7, #0] + 8002b26: 681b ldr r3, [r3, #0] + 8002b28: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002b2c: d03e beq.n 8002bac + 8002b2e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002b32: f200 8087 bhi.w 8002c44 + 8002b36: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002b3a: f000 8086 beq.w 8002c4a + 8002b3e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002b42: d87f bhi.n 8002c44 + 8002b44: 2b70 cmp r3, #112 @ 0x70 + 8002b46: d01a beq.n 8002b7e + 8002b48: 2b70 cmp r3, #112 @ 0x70 + 8002b4a: d87b bhi.n 8002c44 + 8002b4c: 2b60 cmp r3, #96 @ 0x60 + 8002b4e: d050 beq.n 8002bf2 + 8002b50: 2b60 cmp r3, #96 @ 0x60 + 8002b52: d877 bhi.n 8002c44 + 8002b54: 2b50 cmp r3, #80 @ 0x50 + 8002b56: d03c beq.n 8002bd2 + 8002b58: 2b50 cmp r3, #80 @ 0x50 + 8002b5a: d873 bhi.n 8002c44 + 8002b5c: 2b40 cmp r3, #64 @ 0x40 + 8002b5e: d058 beq.n 8002c12 + 8002b60: 2b40 cmp r3, #64 @ 0x40 + 8002b62: d86f bhi.n 8002c44 + 8002b64: 2b30 cmp r3, #48 @ 0x30 + 8002b66: d064 beq.n 8002c32 + 8002b68: 2b30 cmp r3, #48 @ 0x30 + 8002b6a: d86b bhi.n 8002c44 + 8002b6c: 2b20 cmp r3, #32 + 8002b6e: d060 beq.n 8002c32 + 8002b70: 2b20 cmp r3, #32 + 8002b72: d867 bhi.n 8002c44 + 8002b74: 2b00 cmp r3, #0 + 8002b76: d05c beq.n 8002c32 + 8002b78: 2b10 cmp r3, #16 + 8002b7a: d05a beq.n 8002c32 + 8002b7c: e062 b.n 8002c44 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 8002b7e: 687b ldr r3, [r7, #4] + 8002b80: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8002b82: 683b ldr r3, [r7, #0] + 8002b84: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8002b86: 683b ldr r3, [r7, #0] + 8002b88: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002b8a: 683b ldr r3, [r7, #0] + 8002b8c: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 8002b8e: f000 fa71 bl 8003074 + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 8002b92: 687b ldr r3, [r7, #4] + 8002b94: 681b ldr r3, [r3, #0] + 8002b96: 689b ldr r3, [r3, #8] + 8002b98: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8002b9a: 68bb ldr r3, [r7, #8] + 8002b9c: f043 0377 orr.w r3, r3, #119 @ 0x77 + 8002ba0: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8002ba2: 687b ldr r3, [r7, #4] + 8002ba4: 681b ldr r3, [r3, #0] + 8002ba6: 68ba ldr r2, [r7, #8] + 8002ba8: 609a str r2, [r3, #8] + break; + 8002baa: e04f b.n 8002c4c + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 8002bac: 687b ldr r3, [r7, #4] + 8002bae: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8002bb0: 683b ldr r3, [r7, #0] + 8002bb2: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8002bb4: 683b ldr r3, [r7, #0] + 8002bb6: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002bb8: 683b ldr r3, [r7, #0] + 8002bba: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 8002bbc: f000 fa5a bl 8003074 + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 8002bc0: 687b ldr r3, [r7, #4] + 8002bc2: 681b ldr r3, [r3, #0] + 8002bc4: 689a ldr r2, [r3, #8] + 8002bc6: 687b ldr r3, [r7, #4] + 8002bc8: 681b ldr r3, [r3, #0] + 8002bca: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8002bce: 609a str r2, [r3, #8] + break; + 8002bd0: e03c b.n 8002c4c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 8002bd2: 687b ldr r3, [r7, #4] + 8002bd4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 8002bd6: 683b ldr r3, [r7, #0] + 8002bd8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002bda: 683b ldr r3, [r7, #0] + 8002bdc: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 8002bde: 461a mov r2, r3 + 8002be0: f000 f9d1 bl 8002f86 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 8002be4: 687b ldr r3, [r7, #4] + 8002be6: 681b ldr r3, [r3, #0] + 8002be8: 2150 movs r1, #80 @ 0x50 + 8002bea: 4618 mov r0, r3 + 8002bec: f000 fa28 bl 8003040 + break; + 8002bf0: e02c b.n 8002c4c + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 8002bf2: 687b ldr r3, [r7, #4] + 8002bf4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 8002bf6: 683b ldr r3, [r7, #0] + 8002bf8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002bfa: 683b ldr r3, [r7, #0] + 8002bfc: 68db ldr r3, [r3, #12] + TIM_TI2_ConfigInputStage(htim->Instance, + 8002bfe: 461a mov r2, r3 + 8002c00: f000 f9ef bl 8002fe2 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 8002c04: 687b ldr r3, [r7, #4] + 8002c06: 681b ldr r3, [r3, #0] + 8002c08: 2160 movs r1, #96 @ 0x60 + 8002c0a: 4618 mov r0, r3 + 8002c0c: f000 fa18 bl 8003040 + break; + 8002c10: e01c b.n 8002c4c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 8002c12: 687b ldr r3, [r7, #4] + 8002c14: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 8002c16: 683b ldr r3, [r7, #0] + 8002c18: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002c1a: 683b ldr r3, [r7, #0] + 8002c1c: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 8002c1e: 461a mov r2, r3 + 8002c20: f000 f9b1 bl 8002f86 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 8002c24: 687b ldr r3, [r7, #4] + 8002c26: 681b ldr r3, [r3, #0] + 8002c28: 2140 movs r1, #64 @ 0x40 + 8002c2a: 4618 mov r0, r3 + 8002c2c: f000 fa08 bl 8003040 + break; + 8002c30: e00c b.n 8002c4c + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 8002c32: 687b ldr r3, [r7, #4] + 8002c34: 681a ldr r2, [r3, #0] + 8002c36: 683b ldr r3, [r7, #0] + 8002c38: 681b ldr r3, [r3, #0] + 8002c3a: 4619 mov r1, r3 + 8002c3c: 4610 mov r0, r2 + 8002c3e: f000 f9ff bl 8003040 + break; + 8002c42: e003 b.n 8002c4c + } + + default: + status = HAL_ERROR; + 8002c44: 2301 movs r3, #1 + 8002c46: 73fb strb r3, [r7, #15] + break; + 8002c48: e000 b.n 8002c4c + break; + 8002c4a: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8002c4c: 687b ldr r3, [r7, #4] + 8002c4e: 2201 movs r2, #1 + 8002c50: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8002c54: 687b ldr r3, [r7, #4] + 8002c56: 2200 movs r2, #0 + 8002c58: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 8002c5c: 7bfb ldrb r3, [r7, #15] +} + 8002c5e: 4618 mov r0, r3 + 8002c60: 3710 adds r7, #16 + 8002c62: 46bd mov sp, r7 + 8002c64: bd80 pop {r7, pc} + +08002c66 : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8002c66: b480 push {r7} + 8002c68: b083 sub sp, #12 + 8002c6a: af00 add r7, sp, #0 + 8002c6c: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 8002c6e: bf00 nop + 8002c70: 370c adds r7, #12 + 8002c72: 46bd mov sp, r7 + 8002c74: bc80 pop {r7} + 8002c76: 4770 bx lr + +08002c78 : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 8002c78: b480 push {r7} + 8002c7a: b083 sub sp, #12 + 8002c7c: af00 add r7, sp, #0 + 8002c7e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8002c80: bf00 nop + 8002c82: 370c adds r7, #12 + 8002c84: 46bd mov sp, r7 + 8002c86: bc80 pop {r7} + 8002c88: 4770 bx lr + +08002c8a : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8002c8a: b480 push {r7} + 8002c8c: b083 sub sp, #12 + 8002c8e: af00 add r7, sp, #0 + 8002c90: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 8002c92: bf00 nop + 8002c94: 370c adds r7, #12 + 8002c96: 46bd mov sp, r7 + 8002c98: bc80 pop {r7} + 8002c9a: 4770 bx lr + +08002c9c : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 8002c9c: b480 push {r7} + 8002c9e: b083 sub sp, #12 + 8002ca0: af00 add r7, sp, #0 + 8002ca2: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 8002ca4: bf00 nop + 8002ca6: 370c adds r7, #12 + 8002ca8: 46bd mov sp, r7 + 8002caa: bc80 pop {r7} + 8002cac: 4770 bx lr + ... + +08002cb0 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 8002cb0: b480 push {r7} + 8002cb2: b085 sub sp, #20 + 8002cb4: af00 add r7, sp, #0 + 8002cb6: 6078 str r0, [r7, #4] + 8002cb8: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8002cba: 687b ldr r3, [r7, #4] + 8002cbc: 681b ldr r3, [r3, #0] + 8002cbe: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8002cc0: 687b ldr r3, [r7, #4] + 8002cc2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002cc6: d00f beq.n 8002ce8 + 8002cc8: 687b ldr r3, [r7, #4] + 8002cca: 4a2e ldr r2, [pc, #184] @ (8002d84 ) + 8002ccc: 4293 cmp r3, r2 + 8002cce: d00b beq.n 8002ce8 + 8002cd0: 687b ldr r3, [r7, #4] + 8002cd2: 4a2d ldr r2, [pc, #180] @ (8002d88 ) + 8002cd4: 4293 cmp r3, r2 + 8002cd6: d007 beq.n 8002ce8 + 8002cd8: 687b ldr r3, [r7, #4] + 8002cda: 4a2c ldr r2, [pc, #176] @ (8002d8c ) + 8002cdc: 4293 cmp r3, r2 + 8002cde: d003 beq.n 8002ce8 + 8002ce0: 687b ldr r3, [r7, #4] + 8002ce2: 4a2b ldr r2, [pc, #172] @ (8002d90 ) + 8002ce4: 4293 cmp r3, r2 + 8002ce6: d108 bne.n 8002cfa + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8002ce8: 68fb ldr r3, [r7, #12] + 8002cea: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002cee: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8002cf0: 683b ldr r3, [r7, #0] + 8002cf2: 685b ldr r3, [r3, #4] + 8002cf4: 68fa ldr r2, [r7, #12] + 8002cf6: 4313 orrs r3, r2 + 8002cf8: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8002cfa: 687b ldr r3, [r7, #4] + 8002cfc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002d00: d017 beq.n 8002d32 + 8002d02: 687b ldr r3, [r7, #4] + 8002d04: 4a1f ldr r2, [pc, #124] @ (8002d84 ) + 8002d06: 4293 cmp r3, r2 + 8002d08: d013 beq.n 8002d32 + 8002d0a: 687b ldr r3, [r7, #4] + 8002d0c: 4a1e ldr r2, [pc, #120] @ (8002d88 ) + 8002d0e: 4293 cmp r3, r2 + 8002d10: d00f beq.n 8002d32 + 8002d12: 687b ldr r3, [r7, #4] + 8002d14: 4a1d ldr r2, [pc, #116] @ (8002d8c ) + 8002d16: 4293 cmp r3, r2 + 8002d18: d00b beq.n 8002d32 + 8002d1a: 687b ldr r3, [r7, #4] + 8002d1c: 4a1c ldr r2, [pc, #112] @ (8002d90 ) + 8002d1e: 4293 cmp r3, r2 + 8002d20: d007 beq.n 8002d32 + 8002d22: 687b ldr r3, [r7, #4] + 8002d24: 4a1b ldr r2, [pc, #108] @ (8002d94 ) + 8002d26: 4293 cmp r3, r2 + 8002d28: d003 beq.n 8002d32 + 8002d2a: 687b ldr r3, [r7, #4] + 8002d2c: 4a1a ldr r2, [pc, #104] @ (8002d98 ) + 8002d2e: 4293 cmp r3, r2 + 8002d30: d108 bne.n 8002d44 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8002d32: 68fb ldr r3, [r7, #12] + 8002d34: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002d38: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8002d3a: 683b ldr r3, [r7, #0] + 8002d3c: 68db ldr r3, [r3, #12] + 8002d3e: 68fa ldr r2, [r7, #12] + 8002d40: 4313 orrs r3, r2 + 8002d42: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8002d44: 68fb ldr r3, [r7, #12] + 8002d46: f023 0280 bic.w r2, r3, #128 @ 0x80 + 8002d4a: 683b ldr r3, [r7, #0] + 8002d4c: 691b ldr r3, [r3, #16] + 8002d4e: 4313 orrs r3, r2 + 8002d50: 60fb str r3, [r7, #12] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8002d52: 683b ldr r3, [r7, #0] + 8002d54: 689a ldr r2, [r3, #8] + 8002d56: 687b ldr r3, [r7, #4] + 8002d58: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8002d5a: 683b ldr r3, [r7, #0] + 8002d5c: 681a ldr r2, [r3, #0] + 8002d5e: 687b ldr r3, [r7, #4] + 8002d60: 629a str r2, [r3, #40] @ 0x28 + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + 8002d62: 687b ldr r3, [r7, #4] + 8002d64: 681b ldr r3, [r3, #0] + 8002d66: f043 0204 orr.w r2, r3, #4 + 8002d6a: 687b ldr r3, [r7, #4] + 8002d6c: 601a str r2, [r3, #0] + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8002d6e: 687b ldr r3, [r7, #4] + 8002d70: 2201 movs r2, #1 + 8002d72: 615a str r2, [r3, #20] + + TIMx->CR1 = tmpcr1; + 8002d74: 687b ldr r3, [r7, #4] + 8002d76: 68fa ldr r2, [r7, #12] + 8002d78: 601a str r2, [r3, #0] +} + 8002d7a: bf00 nop + 8002d7c: 3714 adds r7, #20 + 8002d7e: 46bd mov sp, r7 + 8002d80: bc80 pop {r7} + 8002d82: 4770 bx lr + 8002d84: 40000400 .word 0x40000400 + 8002d88: 40000800 .word 0x40000800 + 8002d8c: 40000c00 .word 0x40000c00 + 8002d90: 40010800 .word 0x40010800 + 8002d94: 40010c00 .word 0x40010c00 + 8002d98: 40011000 .word 0x40011000 + +08002d9c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002d9c: b480 push {r7} + 8002d9e: b087 sub sp, #28 + 8002da0: af00 add r7, sp, #0 + 8002da2: 6078 str r0, [r7, #4] + 8002da4: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002da6: 687b ldr r3, [r7, #4] + 8002da8: 6a1b ldr r3, [r3, #32] + 8002daa: 617b str r3, [r7, #20] + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002dac: 687b ldr r3, [r7, #4] + 8002dae: 6a1b ldr r3, [r3, #32] + 8002db0: f023 0201 bic.w r2, r3, #1 + 8002db4: 687b ldr r3, [r7, #4] + 8002db6: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002db8: 687b ldr r3, [r7, #4] + 8002dba: 685b ldr r3, [r3, #4] + 8002dbc: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002dbe: 687b ldr r3, [r7, #4] + 8002dc0: 699b ldr r3, [r3, #24] + 8002dc2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 8002dc4: 68fb ldr r3, [r7, #12] + 8002dc6: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002dca: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 8002dcc: 68fb ldr r3, [r7, #12] + 8002dce: f023 0303 bic.w r3, r3, #3 + 8002dd2: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002dd4: 683b ldr r3, [r7, #0] + 8002dd6: 681b ldr r3, [r3, #0] + 8002dd8: 68fa ldr r2, [r7, #12] + 8002dda: 4313 orrs r3, r2 + 8002ddc: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 8002dde: 697b ldr r3, [r7, #20] + 8002de0: f023 0302 bic.w r3, r3, #2 + 8002de4: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 8002de6: 683b ldr r3, [r7, #0] + 8002de8: 689b ldr r3, [r3, #8] + 8002dea: 697a ldr r2, [r7, #20] + 8002dec: 4313 orrs r3, r2 + 8002dee: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002df0: 687b ldr r3, [r7, #4] + 8002df2: 693a ldr r2, [r7, #16] + 8002df4: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002df6: 687b ldr r3, [r7, #4] + 8002df8: 68fa ldr r2, [r7, #12] + 8002dfa: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 8002dfc: 683b ldr r3, [r7, #0] + 8002dfe: 685a ldr r2, [r3, #4] + 8002e00: 687b ldr r3, [r7, #4] + 8002e02: 635a str r2, [r3, #52] @ 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002e04: 687b ldr r3, [r7, #4] + 8002e06: 697a ldr r2, [r7, #20] + 8002e08: 621a str r2, [r3, #32] +} + 8002e0a: bf00 nop + 8002e0c: 371c adds r7, #28 + 8002e0e: 46bd mov sp, r7 + 8002e10: bc80 pop {r7} + 8002e12: 4770 bx lr + +08002e14 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002e14: b480 push {r7} + 8002e16: b087 sub sp, #28 + 8002e18: af00 add r7, sp, #0 + 8002e1a: 6078 str r0, [r7, #4] + 8002e1c: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002e1e: 687b ldr r3, [r7, #4] + 8002e20: 6a1b ldr r3, [r3, #32] + 8002e22: 617b str r3, [r7, #20] + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002e24: 687b ldr r3, [r7, #4] + 8002e26: 6a1b ldr r3, [r3, #32] + 8002e28: f023 0210 bic.w r2, r3, #16 + 8002e2c: 687b ldr r3, [r7, #4] + 8002e2e: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002e30: 687b ldr r3, [r7, #4] + 8002e32: 685b ldr r3, [r3, #4] + 8002e34: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002e36: 687b ldr r3, [r7, #4] + 8002e38: 699b ldr r3, [r3, #24] + 8002e3a: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8002e3c: 68fb ldr r3, [r7, #12] + 8002e3e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002e42: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8002e44: 68fb ldr r3, [r7, #12] + 8002e46: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002e4a: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002e4c: 683b ldr r3, [r7, #0] + 8002e4e: 681b ldr r3, [r3, #0] + 8002e50: 021b lsls r3, r3, #8 + 8002e52: 68fa ldr r2, [r7, #12] + 8002e54: 4313 orrs r3, r2 + 8002e56: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8002e58: 697b ldr r3, [r7, #20] + 8002e5a: f023 0320 bic.w r3, r3, #32 + 8002e5e: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 8002e60: 683b ldr r3, [r7, #0] + 8002e62: 689b ldr r3, [r3, #8] + 8002e64: 011b lsls r3, r3, #4 + 8002e66: 697a ldr r2, [r7, #20] + 8002e68: 4313 orrs r3, r2 + 8002e6a: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002e6c: 687b ldr r3, [r7, #4] + 8002e6e: 693a ldr r2, [r7, #16] + 8002e70: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002e72: 687b ldr r3, [r7, #4] + 8002e74: 68fa ldr r2, [r7, #12] + 8002e76: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8002e78: 683b ldr r3, [r7, #0] + 8002e7a: 685a ldr r2, [r3, #4] + 8002e7c: 687b ldr r3, [r7, #4] + 8002e7e: 639a str r2, [r3, #56] @ 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002e80: 687b ldr r3, [r7, #4] + 8002e82: 697a ldr r2, [r7, #20] + 8002e84: 621a str r2, [r3, #32] +} + 8002e86: bf00 nop + 8002e88: 371c adds r7, #28 + 8002e8a: 46bd mov sp, r7 + 8002e8c: bc80 pop {r7} + 8002e8e: 4770 bx lr + +08002e90 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002e90: b480 push {r7} + 8002e92: b087 sub sp, #28 + 8002e94: af00 add r7, sp, #0 + 8002e96: 6078 str r0, [r7, #4] + 8002e98: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002e9a: 687b ldr r3, [r7, #4] + 8002e9c: 6a1b ldr r3, [r3, #32] + 8002e9e: 617b str r3, [r7, #20] + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8002ea0: 687b ldr r3, [r7, #4] + 8002ea2: 6a1b ldr r3, [r3, #32] + 8002ea4: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8002ea8: 687b ldr r3, [r7, #4] + 8002eaa: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002eac: 687b ldr r3, [r7, #4] + 8002eae: 685b ldr r3, [r3, #4] + 8002eb0: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002eb2: 687b ldr r3, [r7, #4] + 8002eb4: 69db ldr r3, [r3, #28] + 8002eb6: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8002eb8: 68fb ldr r3, [r7, #12] + 8002eba: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002ebe: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8002ec0: 68fb ldr r3, [r7, #12] + 8002ec2: f023 0303 bic.w r3, r3, #3 + 8002ec6: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002ec8: 683b ldr r3, [r7, #0] + 8002eca: 681b ldr r3, [r3, #0] + 8002ecc: 68fa ldr r2, [r7, #12] + 8002ece: 4313 orrs r3, r2 + 8002ed0: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8002ed2: 697b ldr r3, [r7, #20] + 8002ed4: f423 7300 bic.w r3, r3, #512 @ 0x200 + 8002ed8: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 8002eda: 683b ldr r3, [r7, #0] + 8002edc: 689b ldr r3, [r3, #8] + 8002ede: 021b lsls r3, r3, #8 + 8002ee0: 697a ldr r2, [r7, #20] + 8002ee2: 4313 orrs r3, r2 + 8002ee4: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002ee6: 687b ldr r3, [r7, #4] + 8002ee8: 693a ldr r2, [r7, #16] + 8002eea: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002eec: 687b ldr r3, [r7, #4] + 8002eee: 68fa ldr r2, [r7, #12] + 8002ef0: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 8002ef2: 683b ldr r3, [r7, #0] + 8002ef4: 685a ldr r2, [r3, #4] + 8002ef6: 687b ldr r3, [r7, #4] + 8002ef8: 63da str r2, [r3, #60] @ 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002efa: 687b ldr r3, [r7, #4] + 8002efc: 697a ldr r2, [r7, #20] + 8002efe: 621a str r2, [r3, #32] +} + 8002f00: bf00 nop + 8002f02: 371c adds r7, #28 + 8002f04: 46bd mov sp, r7 + 8002f06: bc80 pop {r7} + 8002f08: 4770 bx lr + +08002f0a : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002f0a: b480 push {r7} + 8002f0c: b087 sub sp, #28 + 8002f0e: af00 add r7, sp, #0 + 8002f10: 6078 str r0, [r7, #4] + 8002f12: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002f14: 687b ldr r3, [r7, #4] + 8002f16: 6a1b ldr r3, [r3, #32] + 8002f18: 617b str r3, [r7, #20] + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8002f1a: 687b ldr r3, [r7, #4] + 8002f1c: 6a1b ldr r3, [r3, #32] + 8002f1e: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8002f22: 687b ldr r3, [r7, #4] + 8002f24: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002f26: 687b ldr r3, [r7, #4] + 8002f28: 685b ldr r3, [r3, #4] + 8002f2a: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002f2c: 687b ldr r3, [r7, #4] + 8002f2e: 69db ldr r3, [r3, #28] + 8002f30: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8002f32: 68fb ldr r3, [r7, #12] + 8002f34: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002f38: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8002f3a: 68fb ldr r3, [r7, #12] + 8002f3c: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002f40: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002f42: 683b ldr r3, [r7, #0] + 8002f44: 681b ldr r3, [r3, #0] + 8002f46: 021b lsls r3, r3, #8 + 8002f48: 68fa ldr r2, [r7, #12] + 8002f4a: 4313 orrs r3, r2 + 8002f4c: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8002f4e: 697b ldr r3, [r7, #20] + 8002f50: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 8002f54: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8002f56: 683b ldr r3, [r7, #0] + 8002f58: 689b ldr r3, [r3, #8] + 8002f5a: 031b lsls r3, r3, #12 + 8002f5c: 697a ldr r2, [r7, #20] + 8002f5e: 4313 orrs r3, r2 + 8002f60: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002f62: 687b ldr r3, [r7, #4] + 8002f64: 693a ldr r2, [r7, #16] + 8002f66: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002f68: 687b ldr r3, [r7, #4] + 8002f6a: 68fa ldr r2, [r7, #12] + 8002f6c: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 8002f6e: 683b ldr r3, [r7, #0] + 8002f70: 685a ldr r2, [r3, #4] + 8002f72: 687b ldr r3, [r7, #4] + 8002f74: 641a str r2, [r3, #64] @ 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002f76: 687b ldr r3, [r7, #4] + 8002f78: 697a ldr r2, [r7, #20] + 8002f7a: 621a str r2, [r3, #32] +} + 8002f7c: bf00 nop + 8002f7e: 371c adds r7, #28 + 8002f80: 46bd mov sp, r7 + 8002f82: bc80 pop {r7} + 8002f84: 4770 bx lr + +08002f86 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002f86: b480 push {r7} + 8002f88: b087 sub sp, #28 + 8002f8a: af00 add r7, sp, #0 + 8002f8c: 60f8 str r0, [r7, #12] + 8002f8e: 60b9 str r1, [r7, #8] + 8002f90: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8002f92: 68fb ldr r3, [r7, #12] + 8002f94: 6a1b ldr r3, [r3, #32] + 8002f96: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002f98: 68fb ldr r3, [r7, #12] + 8002f9a: 6a1b ldr r3, [r3, #32] + 8002f9c: f023 0201 bic.w r2, r3, #1 + 8002fa0: 68fb ldr r3, [r7, #12] + 8002fa2: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8002fa4: 68fb ldr r3, [r7, #12] + 8002fa6: 699b ldr r3, [r3, #24] + 8002fa8: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8002faa: 693b ldr r3, [r7, #16] + 8002fac: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8002fb0: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8002fb2: 687b ldr r3, [r7, #4] + 8002fb4: 011b lsls r3, r3, #4 + 8002fb6: 693a ldr r2, [r7, #16] + 8002fb8: 4313 orrs r3, r2 + 8002fba: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 8002fbc: 697b ldr r3, [r7, #20] + 8002fbe: f023 030a bic.w r3, r3, #10 + 8002fc2: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8002fc4: 697a ldr r2, [r7, #20] + 8002fc6: 68bb ldr r3, [r7, #8] + 8002fc8: 4313 orrs r3, r2 + 8002fca: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 8002fcc: 68fb ldr r3, [r7, #12] + 8002fce: 693a ldr r2, [r7, #16] + 8002fd0: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8002fd2: 68fb ldr r3, [r7, #12] + 8002fd4: 697a ldr r2, [r7, #20] + 8002fd6: 621a str r2, [r3, #32] +} + 8002fd8: bf00 nop + 8002fda: 371c adds r7, #28 + 8002fdc: 46bd mov sp, r7 + 8002fde: bc80 pop {r7} + 8002fe0: 4770 bx lr + +08002fe2 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002fe2: b480 push {r7} + 8002fe4: b087 sub sp, #28 + 8002fe6: af00 add r7, sp, #0 + 8002fe8: 60f8 str r0, [r7, #12] + 8002fea: 60b9 str r1, [r7, #8] + 8002fec: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + 8002fee: 68fb ldr r3, [r7, #12] + 8002ff0: 6a1b ldr r3, [r3, #32] + 8002ff2: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002ff4: 68fb ldr r3, [r7, #12] + 8002ff6: 6a1b ldr r3, [r3, #32] + 8002ff8: f023 0210 bic.w r2, r3, #16 + 8002ffc: 68fb ldr r3, [r7, #12] + 8002ffe: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8003000: 68fb ldr r3, [r7, #12] + 8003002: 699b ldr r3, [r3, #24] + 8003004: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8003006: 693b ldr r3, [r7, #16] + 8003008: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 800300c: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 12U); + 800300e: 687b ldr r3, [r7, #4] + 8003010: 031b lsls r3, r3, #12 + 8003012: 693a ldr r2, [r7, #16] + 8003014: 4313 orrs r3, r2 + 8003016: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8003018: 697b ldr r3, [r7, #20] + 800301a: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 800301e: 617b str r3, [r7, #20] + tmpccer |= (TIM_ICPolarity << 4U); + 8003020: 68bb ldr r3, [r7, #8] + 8003022: 011b lsls r3, r3, #4 + 8003024: 697a ldr r2, [r7, #20] + 8003026: 4313 orrs r3, r2 + 8003028: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 800302a: 68fb ldr r3, [r7, #12] + 800302c: 693a ldr r2, [r7, #16] + 800302e: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8003030: 68fb ldr r3, [r7, #12] + 8003032: 697a ldr r2, [r7, #20] + 8003034: 621a str r2, [r3, #32] +} + 8003036: bf00 nop + 8003038: 371c adds r7, #28 + 800303a: 46bd mov sp, r7 + 800303c: bc80 pop {r7} + 800303e: 4770 bx lr + +08003040 : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 8003040: b480 push {r7} + 8003042: b085 sub sp, #20 + 8003044: af00 add r7, sp, #0 + 8003046: 6078 str r0, [r7, #4] + 8003048: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 800304a: 687b ldr r3, [r7, #4] + 800304c: 689b ldr r3, [r3, #8] + 800304e: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8003050: 68fb ldr r3, [r7, #12] + 8003052: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8003056: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8003058: 683a ldr r2, [r7, #0] + 800305a: 68fb ldr r3, [r7, #12] + 800305c: 4313 orrs r3, r2 + 800305e: f043 0307 orr.w r3, r3, #7 + 8003062: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8003064: 687b ldr r3, [r7, #4] + 8003066: 68fa ldr r2, [r7, #12] + 8003068: 609a str r2, [r3, #8] +} + 800306a: bf00 nop + 800306c: 3714 adds r7, #20 + 800306e: 46bd mov sp, r7 + 8003070: bc80 pop {r7} + 8003072: 4770 bx lr + +08003074 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8003074: b480 push {r7} + 8003076: b087 sub sp, #28 + 8003078: af00 add r7, sp, #0 + 800307a: 60f8 str r0, [r7, #12] + 800307c: 60b9 str r1, [r7, #8] + 800307e: 607a str r2, [r7, #4] + 8003080: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 8003082: 68fb ldr r3, [r7, #12] + 8003084: 689b ldr r3, [r3, #8] + 8003086: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8003088: 697b ldr r3, [r7, #20] + 800308a: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 800308e: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8003090: 683b ldr r3, [r7, #0] + 8003092: 021a lsls r2, r3, #8 + 8003094: 687b ldr r3, [r7, #4] + 8003096: 431a orrs r2, r3 + 8003098: 68bb ldr r3, [r7, #8] + 800309a: 4313 orrs r3, r2 + 800309c: 697a ldr r2, [r7, #20] + 800309e: 4313 orrs r3, r2 + 80030a0: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 80030a2: 68fb ldr r3, [r7, #12] + 80030a4: 697a ldr r2, [r7, #20] + 80030a6: 609a str r2, [r3, #8] +} + 80030a8: bf00 nop + 80030aa: 371c adds r7, #28 + 80030ac: 46bd mov sp, r7 + 80030ae: bc80 pop {r7} + 80030b0: 4770 bx lr + +080030b2 : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 80030b2: b480 push {r7} + 80030b4: b087 sub sp, #28 + 80030b6: af00 add r7, sp, #0 + 80030b8: 60f8 str r0, [r7, #12] + 80030ba: 60b9 str r1, [r7, #8] + 80030bc: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 80030be: 68bb ldr r3, [r7, #8] + 80030c0: f003 031f and.w r3, r3, #31 + 80030c4: 2201 movs r2, #1 + 80030c6: fa02 f303 lsl.w r3, r2, r3 + 80030ca: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 80030cc: 68fb ldr r3, [r7, #12] + 80030ce: 6a1a ldr r2, [r3, #32] + 80030d0: 697b ldr r3, [r7, #20] + 80030d2: 43db mvns r3, r3 + 80030d4: 401a ands r2, r3 + 80030d6: 68fb ldr r3, [r7, #12] + 80030d8: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 80030da: 68fb ldr r3, [r7, #12] + 80030dc: 6a1a ldr r2, [r3, #32] + 80030de: 68bb ldr r3, [r7, #8] + 80030e0: f003 031f and.w r3, r3, #31 + 80030e4: 6879 ldr r1, [r7, #4] + 80030e6: fa01 f303 lsl.w r3, r1, r3 + 80030ea: 431a orrs r2, r3 + 80030ec: 68fb ldr r3, [r7, #12] + 80030ee: 621a str r2, [r3, #32] +} + 80030f0: bf00 nop + 80030f2: 371c adds r7, #28 + 80030f4: 46bd mov sp, r7 + 80030f6: bc80 pop {r7} + 80030f8: 4770 bx lr + ... + +080030fc : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + 80030fc: b480 push {r7} + 80030fe: b085 sub sp, #20 + 8003100: af00 add r7, sp, #0 + 8003102: 6078 str r0, [r7, #4] + 8003104: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 8003106: 687b ldr r3, [r7, #4] + 8003108: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 800310c: 2b01 cmp r3, #1 + 800310e: d101 bne.n 8003114 + 8003110: 2302 movs r3, #2 + 8003112: e046 b.n 80031a2 + 8003114: 687b ldr r3, [r7, #4] + 8003116: 2201 movs r2, #1 + 8003118: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 800311c: 687b ldr r3, [r7, #4] + 800311e: 2202 movs r2, #2 + 8003120: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8003124: 687b ldr r3, [r7, #4] + 8003126: 681b ldr r3, [r3, #0] + 8003128: 685b ldr r3, [r3, #4] + 800312a: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 800312c: 687b ldr r3, [r7, #4] + 800312e: 681b ldr r3, [r3, #0] + 8003130: 689b ldr r3, [r3, #8] + 8003132: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8003134: 68fb ldr r3, [r7, #12] + 8003136: f023 0370 bic.w r3, r3, #112 @ 0x70 + 800313a: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 800313c: 683b ldr r3, [r7, #0] + 800313e: 681b ldr r3, [r3, #0] + 8003140: 68fa ldr r2, [r7, #12] + 8003142: 4313 orrs r3, r2 + 8003144: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8003146: 687b ldr r3, [r7, #4] + 8003148: 681b ldr r3, [r3, #0] + 800314a: 68fa ldr r2, [r7, #12] + 800314c: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 800314e: 687b ldr r3, [r7, #4] + 8003150: 681b ldr r3, [r3, #0] + 8003152: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8003156: d00e beq.n 8003176 + 8003158: 687b ldr r3, [r7, #4] + 800315a: 681b ldr r3, [r3, #0] + 800315c: 4a13 ldr r2, [pc, #76] @ (80031ac ) + 800315e: 4293 cmp r3, r2 + 8003160: d009 beq.n 8003176 + 8003162: 687b ldr r3, [r7, #4] + 8003164: 681b ldr r3, [r3, #0] + 8003166: 4a12 ldr r2, [pc, #72] @ (80031b0 ) + 8003168: 4293 cmp r3, r2 + 800316a: d004 beq.n 8003176 + 800316c: 687b ldr r3, [r7, #4] + 800316e: 681b ldr r3, [r3, #0] + 8003170: 4a10 ldr r2, [pc, #64] @ (80031b4 ) + 8003172: 4293 cmp r3, r2 + 8003174: d10c bne.n 8003190 + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8003176: 68bb ldr r3, [r7, #8] + 8003178: f023 0380 bic.w r3, r3, #128 @ 0x80 + 800317c: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 800317e: 683b ldr r3, [r7, #0] + 8003180: 685b ldr r3, [r3, #4] + 8003182: 68ba ldr r2, [r7, #8] + 8003184: 4313 orrs r3, r2 + 8003186: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8003188: 687b ldr r3, [r7, #4] + 800318a: 681b ldr r3, [r3, #0] + 800318c: 68ba ldr r2, [r7, #8] + 800318e: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8003190: 687b ldr r3, [r7, #4] + 8003192: 2201 movs r2, #1 + 8003194: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8003198: 687b ldr r3, [r7, #4] + 800319a: 2200 movs r2, #0 + 800319c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return HAL_OK; + 80031a0: 2300 movs r3, #0 +} + 80031a2: 4618 mov r0, r3 + 80031a4: 3714 adds r7, #20 + 80031a6: 46bd mov sp, r7 + 80031a8: bc80 pop {r7} + 80031aa: 4770 bx lr + 80031ac: 40000400 .word 0x40000400 + 80031b0: 40000800 .word 0x40000800 + 80031b4: 40010800 .word 0x40010800 + +080031b8 : + 80031b8: 4603 mov r3, r0 + 80031ba: 4402 add r2, r0 + 80031bc: 4293 cmp r3, r2 + 80031be: d100 bne.n 80031c2 + 80031c0: 4770 bx lr + 80031c2: f803 1b01 strb.w r1, [r3], #1 + 80031c6: e7f9 b.n 80031bc + +080031c8 <__libc_init_array>: + 80031c8: b570 push {r4, r5, r6, lr} + 80031ca: 2600 movs r6, #0 + 80031cc: 4d0c ldr r5, [pc, #48] @ (8003200 <__libc_init_array+0x38>) + 80031ce: 4c0d ldr r4, [pc, #52] @ (8003204 <__libc_init_array+0x3c>) + 80031d0: 1b64 subs r4, r4, r5 + 80031d2: 10a4 asrs r4, r4, #2 + 80031d4: 42a6 cmp r6, r4 + 80031d6: d109 bne.n 80031ec <__libc_init_array+0x24> + 80031d8: f000 f81a bl 8003210 <_init> + 80031dc: 2600 movs r6, #0 + 80031de: 4d0a ldr r5, [pc, #40] @ (8003208 <__libc_init_array+0x40>) + 80031e0: 4c0a ldr r4, [pc, #40] @ (800320c <__libc_init_array+0x44>) + 80031e2: 1b64 subs r4, r4, r5 + 80031e4: 10a4 asrs r4, r4, #2 + 80031e6: 42a6 cmp r6, r4 + 80031e8: d105 bne.n 80031f6 <__libc_init_array+0x2e> + 80031ea: bd70 pop {r4, r5, r6, pc} + 80031ec: f855 3b04 ldr.w r3, [r5], #4 + 80031f0: 4798 blx r3 + 80031f2: 3601 adds r6, #1 + 80031f4: e7ee b.n 80031d4 <__libc_init_array+0xc> + 80031f6: f855 3b04 ldr.w r3, [r5], #4 + 80031fa: 4798 blx r3 + 80031fc: 3601 adds r6, #1 + 80031fe: e7f2 b.n 80031e6 <__libc_init_array+0x1e> + 8003200: 0800324c .word 0x0800324c + 8003204: 0800324c .word 0x0800324c + 8003208: 0800324c .word 0x0800324c + 800320c: 08003250 .word 0x08003250 + +08003210 <_init>: + 8003210: b5f8 push {r3, r4, r5, r6, r7, lr} + 8003212: bf00 nop + 8003214: bcf8 pop {r3, r4, r5, r6, r7} + 8003216: bc08 pop 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/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + 0x08003250 PROVIDE (__init_array_end = .) + 0x08003250 . = ALIGN (0x4) + +.fini_array 0x08003250 0x4 + 0x08003250 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x08003250 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08003254 . = ALIGN (0x4) + 0x08003254 _sidata = LOADADDR (.data) + +.rel.dyn 0x08003254 0x0 + .rel.iplt 0x08003254 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + +.data 0x20000000 0x10 load address 0x08003254 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.sens 0x20000000 0x1 ./Core/Src/main.o + 0x20000000 sens + *fill* 0x20000001 0x3 + .data.SystemCoreClock + 0x20000004 0x4 ./Core/Src/system_stm32l1xx.o + 0x20000004 SystemCoreClock + .data.uwTickPrio + 0x20000008 0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x20000008 uwTickPrio + .data.uwTickFreq + 0x2000000c 0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x2000000c uwTickFreq + *(.RamFunc) + *(.RamFunc*) + 0x20000010 . = ALIGN (0x4) + 0x20000010 _edata = . + +.igot.plt 0x20000010 0x0 load address 0x08003264 + .igot.plt 0x20000010 0x0 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0x20000148 0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x20000148 uwTick + *(COMMON) + 0x2000014c . = ALIGN (0x4) + 0x2000014c _ebss = . + 0x2000014c __bss_end__ = _ebss + +._user_heap_stack + 0x2000014c 0x604 load address 0x08003264 + 0x20000150 . = ALIGN (0x8) + *fill* 0x2000014c 0x4 + [!provide] PROVIDE (end = .) + 0x20000150 PROVIDE (_end = .) + 0x20000350 . = (. + _Min_Heap_Size) + *fill* 0x20000150 0x200 + 0x20000750 . = (. + _Min_Stack_Size) + *fill* 0x20000350 0x400 + 0x20000750 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x29 + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + .ARM.attributes + 0x0000001d 0x2d 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./Core/Src/main.o + .debug_macro 0x00013261 0x225 ./Core/Src/main.o + .debug_macro 0x00013486 0x788 ./Core/Src/main.o + .debug_macro 0x00013c0e 0xac ./Core/Src/main.o + .debug_macro 0x00013cba 0x170 ./Core/Src/main.o + .debug_macro 0x00013e2a 0x492 ./Core/Src/main.o + .debug_macro 0x000142bc 0x10 ./Core/Src/main.o + .debug_macro 0x000142cc 0x1b9 ./Core/Src/stm32l1xx_hal_msp.o + .debug_macro 0x00014485 0x1c3 ./Core/Src/stm32l1xx_it.o + .debug_macro 0x00014648 0x1af ./Core/Src/system_stm32l1xx.o + .debug_macro 0x000147f7 0x1ec ./Drivers/7Seg_MAX7219/max7219.o + .debug_macro 0x000149e3 0x1d3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_macro 0x00014bb6 0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_macro 0x00014d65 0x1b6 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_macro 0x00014f1b 0x1c1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_macro 0x000150dc 0x1be ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_macro 0x0001529a 0x1b0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_macro 0x0001544a 0x1af ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_line 0x00000000 0xab8c + .debug_line 0x00000000 0x999 ./Core/Src/main.o + .debug_line 0x00000999 0x7df ./Core/Src/stm32l1xx_hal_msp.o + .debug_line 0x00001178 0x7d0 ./Core/Src/stm32l1xx_it.o + .debug_line 0x00001948 0x761 ./Core/Src/system_stm32l1xx.o + .debug_line 0x000020a9 0x79 ./Core/Startup/startup_stm32l152retx.o + .debug_line 0x00002122 0x80f ./Drivers/7Seg_MAX7219/max7219.o + .debug_line 0x00002931 0x98c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_line 0x000032bd 0xc5b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_line 0x00003f18 0x9d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_line 0x000048e8 0xf4f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_line 0x00005837 0x1c4b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_line 0x00007482 0x2fb1 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_line 0x0000a433 0x759 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_str 0x00000000 0x886ff + .debug_str 0x00000000 0x886ff ./Core/Src/main.o + 0x86838 (size before relaxing) + .debug_str 0x000886ff 0x863dd ./Core/Src/stm32l1xx_hal_msp.o + .debug_str 0x000886ff 0x85e03 ./Core/Src/stm32l1xx_it.o + .debug_str 0x000886ff 0x85902 ./Core/Src/system_stm32l1xx.o + .debug_str 0x000886ff 0x8c ./Core/Startup/startup_stm32l152retx.o + .debug_str 0x000886ff 0x85e5e ./Drivers/7Seg_MAX7219/max7219.o + .debug_str 0x000886ff 0x8602a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_str 0x000886ff 0x86136 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_str 0x000886ff 0x85a95 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_str 0x000886ff 0x85dbe ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_str 0x000886ff 0x86224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_str 0x000886ff 0x86c05 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_str 0x000886ff 0x85daa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.comment 0x00000000 0x43 + .comment 0x00000000 0x43 ./Core/Src/main.o + 0x44 (size before relaxing) + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_hal_msp.o + .comment 0x00000043 0x44 ./Core/Src/stm32l1xx_it.o + .comment 0x00000043 0x44 ./Core/Src/system_stm32l1xx.o + .comment 0x00000043 0x44 ./Drivers/7Seg_MAX7219/max7219.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_frame 0x00000000 0x2c2c + .debug_frame 0x00000000 0x160 ./Core/Src/main.o + .debug_frame 0x00000160 0xec ./Core/Src/stm32l1xx_hal_msp.o + .debug_frame 0x0000024c 0x174 ./Core/Src/stm32l1xx_it.o + .debug_frame 0x000003c0 0x58 ./Core/Src/system_stm32l1xx.o + .debug_frame 0x00000418 0x198 ./Drivers/7Seg_MAX7219/max7219.o + .debug_frame 0x000005b0 0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_frame 0x000008ec 0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_frame 0x00000dd4 0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_frame 0x00000f20 0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_frame 0x00001144 0x828 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_frame 0x0000196c 0x11b4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_frame 0x00002b20 0x60 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + .debug_frame 0x00002b80 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00002ba0 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .debug_frame 0x00002bcc 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00002bf8 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x70 + .debug_line_str + 0x00000000 0x70 ./Core/Startup/startup_stm32l152retx.o diff --git a/TP4_INIT_TFT/Debug/TP3_PWM_MOTOR.list b/TP4_INIT_TFT/Debug/TP3_PWM_MOTOR.list new file mode 100644 index 0000000..c42f0b6 --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP3_PWM_MOTOR.list @@ -0,0 +1,9179 @@ + +TP3_PWM_MOTOR.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000036c8 08000140 08000140 00001140 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000002c 08003808 08003808 00004808 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08003834 08003834 00005010 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08003834 08003834 00004834 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800383c 0800383c 00005010 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800383c 0800383c 0000483c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 08003840 08003840 00004840 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 00000010 20000000 08003844 00005000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000000fc 20000010 08003854 00005010 2**2 + ALLOC + 10 ._user_heap_stack 00000604 2000010c 08003854 0000510c 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 00005010 2**0 + CONTENTS, READONLY + 12 .debug_info 00009912 00000000 00000000 00005039 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 000019e3 00000000 00000000 0000e94b 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000aa0 00000000 00000000 00010330 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 00000812 00000000 00000000 00010dd0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000155f9 00000000 00000000 000115e2 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0000aade 00000000 00000000 00026bdb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 000886db 00000000 00000000 000316b9 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000b9d94 2**0 + CONTENTS, READONLY + 20 .debug_frame 00002cec 00000000 00000000 000b9dd8 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000bcac4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +08000140 <__do_global_dtors_aux>: + 8000140: b510 push {r4, lr} + 8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>) + 8000144: 7823 ldrb r3, [r4, #0] + 8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16> + 8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>) + 800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12> + 800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>) + 800014e: f3af 8000 nop.w + 8000152: 2301 movs r3, #1 + 8000154: 7023 strb r3, [r4, #0] + 8000156: bd10 pop {r4, pc} + 8000158: 20000010 .word 0x20000010 + 800015c: 00000000 .word 0x00000000 + 8000160: 080037f0 .word 0x080037f0 + +08000164 : + 8000164: b508 push {r3, lr} + 8000166: 4b03 ldr r3, [pc, #12] @ (8000174 ) + 8000168: b11b cbz r3, 8000172 + 800016a: 4903 ldr r1, [pc, #12] @ (8000178 ) + 800016c: 4803 ldr r0, [pc, #12] @ (800017c ) + 800016e: f3af 8000 nop.w + 8000172: bd08 pop {r3, pc} + 8000174: 00000000 .word 0x00000000 + 8000178: 20000014 .word 0x20000014 + 800017c: 080037f0 .word 0x080037f0 + +08000180 <__aeabi_dmul>: + 8000180: b570 push {r4, r5, r6, lr} + 8000182: f04f 0cff mov.w ip, #255 @ 0xff + 8000186: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700 + 800018a: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 800018e: bf1d ittte ne + 8000190: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8000194: ea94 0f0c teqne r4, ip + 8000198: ea95 0f0c teqne r5, ip + 800019c: f000 f8de bleq 800035c <__aeabi_dmul+0x1dc> + 80001a0: 442c add r4, r5 + 80001a2: ea81 0603 eor.w r6, r1, r3 + 80001a6: ea21 514c bic.w r1, r1, ip, lsl #21 + 80001aa: ea23 534c bic.w r3, r3, ip, lsl #21 + 80001ae: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 80001b2: bf18 it ne + 80001b4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 80001b8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 + 80001bc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 80001c0: d038 beq.n 8000234 <__aeabi_dmul+0xb4> + 80001c2: fba0 ce02 umull ip, lr, r0, r2 + 80001c6: f04f 0500 mov.w r5, #0 + 80001ca: fbe1 e502 umlal lr, r5, r1, r2 + 80001ce: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000 + 80001d2: fbe0 e503 umlal lr, r5, r0, r3 + 80001d6: f04f 0600 mov.w r6, #0 + 80001da: fbe1 5603 umlal r5, r6, r1, r3 + 80001de: f09c 0f00 teq ip, #0 + 80001e2: bf18 it ne + 80001e4: f04e 0e01 orrne.w lr, lr, #1 + 80001e8: f1a4 04ff sub.w r4, r4, #255 @ 0xff + 80001ec: f5b6 7f00 cmp.w r6, #512 @ 0x200 + 80001f0: f564 7440 sbc.w r4, r4, #768 @ 0x300 + 80001f4: d204 bcs.n 8000200 <__aeabi_dmul+0x80> + 80001f6: ea5f 0e4e movs.w lr, lr, lsl #1 + 80001fa: 416d adcs r5, r5 + 80001fc: eb46 0606 adc.w r6, r6, r6 + 8000200: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 8000204: ea41 5155 orr.w r1, r1, r5, lsr #21 + 8000208: ea4f 20c5 mov.w r0, r5, lsl #11 + 800020c: ea40 505e orr.w r0, r0, lr, lsr #21 + 8000210: ea4f 2ece mov.w lr, lr, lsl #11 + 8000214: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd + 8000218: bf88 it hi + 800021a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700 + 800021e: d81e bhi.n 800025e <__aeabi_dmul+0xde> + 8000220: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000 + 8000224: bf08 it eq + 8000226: ea5f 0e50 movseq.w lr, r0, lsr #1 + 800022a: f150 0000 adcs.w r0, r0, #0 + 800022e: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8000232: bd70 pop {r4, r5, r6, pc} + 8000234: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000 + 8000238: ea46 0101 orr.w r1, r6, r1 + 800023c: ea40 0002 orr.w r0, r0, r2 + 8000240: ea81 0103 eor.w r1, r1, r3 + 8000244: ebb4 045c subs.w r4, r4, ip, lsr #1 + 8000248: bfc2 ittt gt + 800024a: ebd4 050c rsbsgt r5, r4, ip + 800024e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 8000252: bd70 popgt {r4, r5, r6, pc} + 8000254: f441 1180 orr.w r1, r1, #1048576 @ 0x100000 + 8000258: f04f 0e00 mov.w lr, #0 + 800025c: 3c01 subs r4, #1 + 800025e: f300 80ab bgt.w 80003b8 <__aeabi_dmul+0x238> + 8000262: f114 0f36 cmn.w r4, #54 @ 0x36 + 8000266: bfde ittt le + 8000268: 2000 movle r0, #0 + 800026a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000 + 800026e: bd70 pople {r4, r5, r6, pc} + 8000270: f1c4 0400 rsb r4, r4, #0 + 8000274: 3c20 subs r4, #32 + 8000276: da35 bge.n 80002e4 <__aeabi_dmul+0x164> + 8000278: 340c adds r4, #12 + 800027a: dc1b bgt.n 80002b4 <__aeabi_dmul+0x134> + 800027c: f104 0414 add.w r4, r4, #20 + 8000280: f1c4 0520 rsb r5, r4, #32 + 8000284: fa00 f305 lsl.w r3, r0, r5 + 8000288: fa20 f004 lsr.w r0, r0, r4 + 800028c: fa01 f205 lsl.w r2, r1, r5 + 8000290: ea40 0002 orr.w r0, r0, r2 + 8000294: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000 + 8000298: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 + 800029c: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 80002a0: fa21 f604 lsr.w r6, r1, r4 + 80002a4: eb42 0106 adc.w r1, r2, r6 + 80002a8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80002ac: bf08 it eq + 80002ae: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80002b2: bd70 pop {r4, r5, r6, pc} + 80002b4: f1c4 040c rsb r4, r4, #12 + 80002b8: f1c4 0520 rsb r5, r4, #32 + 80002bc: fa00 f304 lsl.w r3, r0, r4 + 80002c0: fa20 f005 lsr.w r0, r0, r5 + 80002c4: fa01 f204 lsl.w r2, r1, r4 + 80002c8: ea40 0002 orr.w r0, r0, r2 + 80002cc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 80002d0: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 80002d4: f141 0100 adc.w r1, r1, #0 + 80002d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80002dc: bf08 it eq + 80002de: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80002e2: bd70 pop {r4, r5, r6, pc} + 80002e4: f1c4 0520 rsb r5, r4, #32 + 80002e8: fa00 f205 lsl.w r2, r0, r5 + 80002ec: ea4e 0e02 orr.w lr, lr, r2 + 80002f0: fa20 f304 lsr.w r3, r0, r4 + 80002f4: fa01 f205 lsl.w r2, r1, r5 + 80002f8: ea43 0302 orr.w r3, r3, r2 + 80002fc: fa21 f004 lsr.w r0, r1, r4 + 8000300: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 8000304: fa21 f204 lsr.w r2, r1, r4 + 8000308: ea20 0002 bic.w r0, r0, r2 + 800030c: eb00 70d3 add.w r0, r0, r3, lsr #31 + 8000310: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 8000314: bf08 it eq + 8000316: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 800031a: bd70 pop {r4, r5, r6, pc} + 800031c: f094 0f00 teq r4, #0 + 8000320: d10f bne.n 8000342 <__aeabi_dmul+0x1c2> + 8000322: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000 + 8000326: 0040 lsls r0, r0, #1 + 8000328: eb41 0101 adc.w r1, r1, r1 + 800032c: f411 1f80 tst.w r1, #1048576 @ 0x100000 + 8000330: bf08 it eq + 8000332: 3c01 subeq r4, #1 + 8000334: d0f7 beq.n 8000326 <__aeabi_dmul+0x1a6> + 8000336: ea41 0106 orr.w r1, r1, r6 + 800033a: f095 0f00 teq r5, #0 + 800033e: bf18 it ne + 8000340: 4770 bxne lr + 8000342: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000 + 8000346: 0052 lsls r2, r2, #1 + 8000348: eb43 0303 adc.w r3, r3, r3 + 800034c: f413 1f80 tst.w r3, #1048576 @ 0x100000 + 8000350: bf08 it eq + 8000352: 3d01 subeq r5, #1 + 8000354: d0f7 beq.n 8000346 <__aeabi_dmul+0x1c6> + 8000356: ea43 0306 orr.w r3, r3, r6 + 800035a: 4770 bx lr + 800035c: ea94 0f0c teq r4, ip + 8000360: ea0c 5513 and.w r5, ip, r3, lsr #20 + 8000364: bf18 it ne + 8000366: ea95 0f0c teqne r5, ip + 800036a: d00c beq.n 8000386 <__aeabi_dmul+0x206> + 800036c: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000370: bf18 it ne + 8000372: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 8000376: d1d1 bne.n 800031c <__aeabi_dmul+0x19c> + 8000378: ea81 0103 eor.w r1, r1, r3 + 800037c: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 8000380: f04f 0000 mov.w r0, #0 + 8000384: bd70 pop {r4, r5, r6, pc} + 8000386: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 800038a: bf06 itte eq + 800038c: 4610 moveq r0, r2 + 800038e: 4619 moveq r1, r3 + 8000390: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 8000394: d019 beq.n 80003ca <__aeabi_dmul+0x24a> + 8000396: ea94 0f0c teq r4, ip + 800039a: d102 bne.n 80003a2 <__aeabi_dmul+0x222> + 800039c: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 80003a0: d113 bne.n 80003ca <__aeabi_dmul+0x24a> + 80003a2: ea95 0f0c teq r5, ip + 80003a6: d105 bne.n 80003b4 <__aeabi_dmul+0x234> + 80003a8: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 80003ac: bf1c itt ne + 80003ae: 4610 movne r0, r2 + 80003b0: 4619 movne r1, r3 + 80003b2: d10a bne.n 80003ca <__aeabi_dmul+0x24a> + 80003b4: ea81 0103 eor.w r1, r1, r3 + 80003b8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 + 80003bc: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 + 80003c0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 + 80003c4: f04f 0000 mov.w r0, #0 + 80003c8: bd70 pop {r4, r5, r6, pc} + 80003ca: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000 + 80003ce: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000 + 80003d2: bd70 pop {r4, r5, r6, pc} + +080003d4 <__aeabi_drsub>: + 80003d4: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000 + 80003d8: e002 b.n 80003e0 <__adddf3> + 80003da: bf00 nop + +080003dc <__aeabi_dsub>: + 80003dc: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000 + +080003e0 <__adddf3>: + 80003e0: b530 push {r4, r5, lr} + 80003e2: ea4f 0441 mov.w r4, r1, lsl #1 + 80003e6: ea4f 0543 mov.w r5, r3, lsl #1 + 80003ea: ea94 0f05 teq r4, r5 + 80003ee: bf08 it eq + 80003f0: ea90 0f02 teqeq r0, r2 + 80003f4: bf1f itttt ne + 80003f6: ea54 0c00 orrsne.w ip, r4, r0 + 80003fa: ea55 0c02 orrsne.w ip, r5, r2 + 80003fe: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 8000402: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 8000406: f000 80e2 beq.w 80005ce <__adddf3+0x1ee> + 800040a: ea4f 5454 mov.w r4, r4, lsr #21 + 800040e: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 8000412: bfb8 it lt + 8000414: 426d neglt r5, r5 + 8000416: dd0c ble.n 8000432 <__adddf3+0x52> + 8000418: 442c add r4, r5 + 800041a: ea80 0202 eor.w r2, r0, r2 + 800041e: ea81 0303 eor.w r3, r1, r3 + 8000422: ea82 0000 eor.w r0, r2, r0 + 8000426: ea83 0101 eor.w r1, r3, r1 + 800042a: ea80 0202 eor.w r2, r0, r2 + 800042e: ea81 0303 eor.w r3, r1, r3 + 8000432: 2d36 cmp r5, #54 @ 0x36 + 8000434: bf88 it hi + 8000436: bd30 pophi {r4, r5, pc} + 8000438: f011 4f00 tst.w r1, #2147483648 @ 0x80000000 + 800043c: ea4f 3101 mov.w r1, r1, lsl #12 + 8000440: f44f 1c80 mov.w ip, #1048576 @ 0x100000 + 8000444: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 8000448: d002 beq.n 8000450 <__adddf3+0x70> + 800044a: 4240 negs r0, r0 + 800044c: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8000450: f013 4f00 tst.w r3, #2147483648 @ 0x80000000 + 8000454: ea4f 3303 mov.w r3, r3, lsl #12 + 8000458: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 800045c: d002 beq.n 8000464 <__adddf3+0x84> + 800045e: 4252 negs r2, r2 + 8000460: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8000464: ea94 0f05 teq r4, r5 + 8000468: f000 80a7 beq.w 80005ba <__adddf3+0x1da> + 800046c: f1a4 0401 sub.w r4, r4, #1 + 8000470: f1d5 0e20 rsbs lr, r5, #32 + 8000474: db0d blt.n 8000492 <__adddf3+0xb2> + 8000476: fa02 fc0e lsl.w ip, r2, lr + 800047a: fa22 f205 lsr.w r2, r2, r5 + 800047e: 1880 adds r0, r0, r2 + 8000480: f141 0100 adc.w r1, r1, #0 + 8000484: fa03 f20e lsl.w r2, r3, lr + 8000488: 1880 adds r0, r0, r2 + 800048a: fa43 f305 asr.w r3, r3, r5 + 800048e: 4159 adcs r1, r3 + 8000490: e00e b.n 80004b0 <__adddf3+0xd0> + 8000492: f1a5 0520 sub.w r5, r5, #32 + 8000496: f10e 0e20 add.w lr, lr, #32 + 800049a: 2a01 cmp r2, #1 + 800049c: fa03 fc0e lsl.w ip, r3, lr + 80004a0: bf28 it cs + 80004a2: f04c 0c02 orrcs.w ip, ip, #2 + 80004a6: fa43 f305 asr.w r3, r3, r5 + 80004aa: 18c0 adds r0, r0, r3 + 80004ac: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 80004b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 + 80004b4: d507 bpl.n 80004c6 <__adddf3+0xe6> + 80004b6: f04f 0e00 mov.w lr, #0 + 80004ba: f1dc 0c00 rsbs ip, ip, #0 + 80004be: eb7e 0000 sbcs.w r0, lr, r0 + 80004c2: eb6e 0101 sbc.w r1, lr, r1 + 80004c6: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 + 80004ca: d31b bcc.n 8000504 <__adddf3+0x124> + 80004cc: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 + 80004d0: d30c bcc.n 80004ec <__adddf3+0x10c> + 80004d2: 0849 lsrs r1, r1, #1 + 80004d4: ea5f 0030 movs.w r0, r0, rrx + 80004d8: ea4f 0c3c mov.w ip, ip, rrx + 80004dc: f104 0401 add.w r4, r4, #1 + 80004e0: ea4f 5244 mov.w r2, r4, lsl #21 + 80004e4: f512 0f80 cmn.w r2, #4194304 @ 0x400000 + 80004e8: f080 809a bcs.w 8000620 <__adddf3+0x240> + 80004ec: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000 + 80004f0: bf08 it eq + 80004f2: ea5f 0c50 movseq.w ip, r0, lsr #1 + 80004f6: f150 0000 adcs.w r0, r0, #0 + 80004fa: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80004fe: ea41 0105 orr.w r1, r1, r5 + 8000502: bd30 pop {r4, r5, pc} + 8000504: ea5f 0c4c movs.w ip, ip, lsl #1 + 8000508: 4140 adcs r0, r0 + 800050a: eb41 0101 adc.w r1, r1, r1 + 800050e: 3c01 subs r4, #1 + 8000510: bf28 it cs + 8000512: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000 + 8000516: d2e9 bcs.n 80004ec <__adddf3+0x10c> + 8000518: f091 0f00 teq r1, #0 + 800051c: bf04 itt eq + 800051e: 4601 moveq r1, r0 + 8000520: 2000 moveq r0, #0 + 8000522: fab1 f381 clz r3, r1 + 8000526: bf08 it eq + 8000528: 3320 addeq r3, #32 + 800052a: f1a3 030b sub.w r3, r3, #11 + 800052e: f1b3 0220 subs.w r2, r3, #32 + 8000532: da0c bge.n 800054e <__adddf3+0x16e> + 8000534: 320c adds r2, #12 + 8000536: dd08 ble.n 800054a <__adddf3+0x16a> + 8000538: f102 0c14 add.w ip, r2, #20 + 800053c: f1c2 020c rsb r2, r2, #12 + 8000540: fa01 f00c lsl.w r0, r1, ip + 8000544: fa21 f102 lsr.w r1, r1, r2 + 8000548: e00c b.n 8000564 <__adddf3+0x184> + 800054a: f102 0214 add.w r2, r2, #20 + 800054e: bfd8 it le + 8000550: f1c2 0c20 rsble ip, r2, #32 + 8000554: fa01 f102 lsl.w r1, r1, r2 + 8000558: fa20 fc0c lsr.w ip, r0, ip + 800055c: bfdc itt le + 800055e: ea41 010c orrle.w r1, r1, ip + 8000562: 4090 lslle r0, r2 + 8000564: 1ae4 subs r4, r4, r3 + 8000566: bfa2 ittt ge + 8000568: eb01 5104 addge.w r1, r1, r4, lsl #20 + 800056c: 4329 orrge r1, r5 + 800056e: bd30 popge {r4, r5, pc} + 8000570: ea6f 0404 mvn.w r4, r4 + 8000574: 3c1f subs r4, #31 + 8000576: da1c bge.n 80005b2 <__adddf3+0x1d2> + 8000578: 340c adds r4, #12 + 800057a: dc0e bgt.n 800059a <__adddf3+0x1ba> + 800057c: f104 0414 add.w r4, r4, #20 + 8000580: f1c4 0220 rsb r2, r4, #32 + 8000584: fa20 f004 lsr.w r0, r0, r4 + 8000588: fa01 f302 lsl.w r3, r1, r2 + 800058c: ea40 0003 orr.w r0, r0, r3 + 8000590: fa21 f304 lsr.w r3, r1, r4 + 8000594: ea45 0103 orr.w r1, r5, r3 + 8000598: bd30 pop {r4, r5, pc} + 800059a: f1c4 040c rsb r4, r4, #12 + 800059e: f1c4 0220 rsb r2, r4, #32 + 80005a2: fa20 f002 lsr.w r0, r0, r2 + 80005a6: fa01 f304 lsl.w r3, r1, r4 + 80005aa: ea40 0003 orr.w r0, r0, r3 + 80005ae: 4629 mov r1, r5 + 80005b0: bd30 pop {r4, r5, pc} + 80005b2: fa21 f004 lsr.w r0, r1, r4 + 80005b6: 4629 mov r1, r5 + 80005b8: bd30 pop {r4, r5, pc} + 80005ba: f094 0f00 teq r4, #0 + 80005be: f483 1380 eor.w r3, r3, #1048576 @ 0x100000 + 80005c2: bf06 itte eq + 80005c4: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000 + 80005c8: 3401 addeq r4, #1 + 80005ca: 3d01 subne r5, #1 + 80005cc: e74e b.n 800046c <__adddf3+0x8c> + 80005ce: ea7f 5c64 mvns.w ip, r4, asr #21 + 80005d2: bf18 it ne + 80005d4: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 80005d8: d029 beq.n 800062e <__adddf3+0x24e> + 80005da: ea94 0f05 teq r4, r5 + 80005de: bf08 it eq + 80005e0: ea90 0f02 teqeq r0, r2 + 80005e4: d005 beq.n 80005f2 <__adddf3+0x212> + 80005e6: ea54 0c00 orrs.w ip, r4, r0 + 80005ea: bf04 itt eq + 80005ec: 4619 moveq r1, r3 + 80005ee: 4610 moveq r0, r2 + 80005f0: bd30 pop {r4, r5, pc} + 80005f2: ea91 0f03 teq r1, r3 + 80005f6: bf1e ittt ne + 80005f8: 2100 movne r1, #0 + 80005fa: 2000 movne r0, #0 + 80005fc: bd30 popne {r4, r5, pc} + 80005fe: ea5f 5c54 movs.w ip, r4, lsr #21 + 8000602: d105 bne.n 8000610 <__adddf3+0x230> + 8000604: 0040 lsls r0, r0, #1 + 8000606: 4149 adcs r1, r1 + 8000608: bf28 it cs + 800060a: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000 + 800060e: bd30 pop {r4, r5, pc} + 8000610: f514 0480 adds.w r4, r4, #4194304 @ 0x400000 + 8000614: bf3c itt cc + 8000616: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000 + 800061a: bd30 popcc {r4, r5, pc} + 800061c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 + 8000620: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000 + 8000624: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 + 8000628: f04f 0000 mov.w r0, #0 + 800062c: bd30 pop {r4, r5, pc} + 800062e: ea7f 5c64 mvns.w ip, r4, asr #21 + 8000632: bf1a itte ne + 8000634: 4619 movne r1, r3 + 8000636: 4610 movne r0, r2 + 8000638: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 800063c: bf1c itt ne + 800063e: 460b movne r3, r1 + 8000640: 4602 movne r2, r0 + 8000642: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 8000646: bf06 itte eq + 8000648: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 800064c: ea91 0f03 teqeq r1, r3 + 8000650: f441 2100 orrne.w r1, r1, #524288 @ 0x80000 + 8000654: bd30 pop {r4, r5, pc} + 8000656: bf00 nop + +08000658 <__aeabi_ui2d>: + 8000658: f090 0f00 teq r0, #0 + 800065c: bf04 itt eq + 800065e: 2100 moveq r1, #0 + 8000660: 4770 bxeq lr + 8000662: b530 push {r4, r5, lr} + 8000664: f44f 6480 mov.w r4, #1024 @ 0x400 + 8000668: f104 0432 add.w r4, r4, #50 @ 0x32 + 800066c: f04f 0500 mov.w r5, #0 + 8000670: f04f 0100 mov.w r1, #0 + 8000674: e750 b.n 8000518 <__adddf3+0x138> + 8000676: bf00 nop + +08000678 <__aeabi_i2d>: + 8000678: f090 0f00 teq r0, #0 + 800067c: bf04 itt eq + 800067e: 2100 moveq r1, #0 + 8000680: 4770 bxeq lr + 8000682: b530 push {r4, r5, lr} + 8000684: f44f 6480 mov.w r4, #1024 @ 0x400 + 8000688: f104 0432 add.w r4, r4, #50 @ 0x32 + 800068c: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000 + 8000690: bf48 it mi + 8000692: 4240 negmi r0, r0 + 8000694: f04f 0100 mov.w r1, #0 + 8000698: e73e b.n 8000518 <__adddf3+0x138> + 800069a: bf00 nop + +0800069c <__aeabi_f2d>: + 800069c: 0042 lsls r2, r0, #1 + 800069e: ea4f 01e2 mov.w r1, r2, asr #3 + 80006a2: ea4f 0131 mov.w r1, r1, rrx + 80006a6: ea4f 7002 mov.w r0, r2, lsl #28 + 80006aa: bf1f itttt ne + 80006ac: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000 + 80006b0: f093 4f7f teqne r3, #4278190080 @ 0xff000000 + 80006b4: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000 + 80006b8: 4770 bxne lr + 80006ba: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000 + 80006be: bf08 it eq + 80006c0: 4770 bxeq lr + 80006c2: f093 4f7f teq r3, #4278190080 @ 0xff000000 + 80006c6: bf04 itt eq + 80006c8: f441 2100 orreq.w r1, r1, #524288 @ 0x80000 + 80006cc: 4770 bxeq lr + 80006ce: b530 push {r4, r5, lr} + 80006d0: f44f 7460 mov.w r4, #896 @ 0x380 + 80006d4: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000 + 80006d8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 + 80006dc: e71c b.n 8000518 <__adddf3+0x138> + 80006de: bf00 nop + +080006e0 <__aeabi_ul2d>: + 80006e0: ea50 0201 orrs.w r2, r0, r1 + 80006e4: bf08 it eq + 80006e6: 4770 bxeq lr + 80006e8: b530 push {r4, r5, lr} + 80006ea: f04f 0500 mov.w r5, #0 + 80006ee: e00a b.n 8000706 <__aeabi_l2d+0x16> + +080006f0 <__aeabi_l2d>: + 80006f0: ea50 0201 orrs.w r2, r0, r1 + 80006f4: bf08 it eq + 80006f6: 4770 bxeq lr + 80006f8: b530 push {r4, r5, lr} + 80006fa: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000 + 80006fe: d502 bpl.n 8000706 <__aeabi_l2d+0x16> + 8000700: 4240 negs r0, r0 + 8000702: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8000706: f44f 6480 mov.w r4, #1024 @ 0x400 + 800070a: f104 0432 add.w r4, r4, #50 @ 0x32 + 800070e: ea5f 5c91 movs.w ip, r1, lsr #22 + 8000712: f43f aed8 beq.w 80004c6 <__adddf3+0xe6> + 8000716: f04f 0203 mov.w r2, #3 + 800071a: ea5f 0cdc movs.w ip, ip, lsr #3 + 800071e: bf18 it ne + 8000720: 3203 addne r2, #3 + 8000722: ea5f 0cdc movs.w ip, ip, lsr #3 + 8000726: bf18 it ne + 8000728: 3203 addne r2, #3 + 800072a: eb02 02dc add.w r2, r2, ip, lsr #3 + 800072e: f1c2 0320 rsb r3, r2, #32 + 8000732: fa00 fc03 lsl.w ip, r0, r3 + 8000736: fa20 f002 lsr.w r0, r0, r2 + 800073a: fa01 fe03 lsl.w lr, r1, r3 + 800073e: ea40 000e orr.w r0, r0, lr + 8000742: fa21 f102 lsr.w r1, r1, r2 + 8000746: 4414 add r4, r2 + 8000748: e6bd b.n 80004c6 <__adddf3+0xe6> + 800074a: bf00 nop + +0800074c <__aeabi_d2uiz>: + 800074c: 004a lsls r2, r1, #1 + 800074e: d211 bcs.n 8000774 <__aeabi_d2uiz+0x28> + 8000750: f512 1200 adds.w r2, r2, #2097152 @ 0x200000 + 8000754: d211 bcs.n 800077a <__aeabi_d2uiz+0x2e> + 8000756: d50d bpl.n 8000774 <__aeabi_d2uiz+0x28> + 8000758: f46f 7378 mvn.w r3, #992 @ 0x3e0 + 800075c: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000760: d40e bmi.n 8000780 <__aeabi_d2uiz+0x34> + 8000762: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000766: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 800076a: ea43 5350 orr.w r3, r3, r0, lsr #21 + 800076e: fa23 f002 lsr.w r0, r3, r2 + 8000772: 4770 bx lr + 8000774: f04f 0000 mov.w r0, #0 + 8000778: 4770 bx lr + 800077a: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 800077e: d102 bne.n 8000786 <__aeabi_d2uiz+0x3a> + 8000780: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000784: 4770 bx lr + 8000786: f04f 0000 mov.w r0, #0 + 800078a: 4770 bx lr + +0800078c <__aeabi_uldivmod>: + 800078c: b953 cbnz r3, 80007a4 <__aeabi_uldivmod+0x18> + 800078e: b94a cbnz r2, 80007a4 <__aeabi_uldivmod+0x18> + 8000790: 2900 cmp r1, #0 + 8000792: bf08 it eq + 8000794: 2800 cmpeq r0, #0 + 8000796: bf1c itt ne + 8000798: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800079c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 80007a0: f000 b98c b.w 8000abc <__aeabi_idiv0> + 80007a4: f1ad 0c08 sub.w ip, sp, #8 + 80007a8: e96d ce04 strd ip, lr, [sp, #-16]! + 80007ac: f000 f806 bl 80007bc <__udivmoddi4> + 80007b0: f8dd e004 ldr.w lr, [sp, #4] + 80007b4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80007b8: b004 add sp, #16 + 80007ba: 4770 bx lr + +080007bc <__udivmoddi4>: + 80007bc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80007c0: 9d08 ldr r5, [sp, #32] + 80007c2: 468e mov lr, r1 + 80007c4: 4604 mov r4, r0 + 80007c6: 4688 mov r8, r1 + 80007c8: 2b00 cmp r3, #0 + 80007ca: d14a bne.n 8000862 <__udivmoddi4+0xa6> + 80007cc: 428a cmp r2, r1 + 80007ce: 4617 mov r7, r2 + 80007d0: d962 bls.n 8000898 <__udivmoddi4+0xdc> + 80007d2: fab2 f682 clz r6, r2 + 80007d6: b14e cbz r6, 80007ec <__udivmoddi4+0x30> + 80007d8: f1c6 0320 rsb r3, r6, #32 + 80007dc: fa01 f806 lsl.w r8, r1, r6 + 80007e0: fa20 f303 lsr.w r3, r0, r3 + 80007e4: 40b7 lsls r7, r6 + 80007e6: ea43 0808 orr.w r8, r3, r8 + 80007ea: 40b4 lsls r4, r6 + 80007ec: ea4f 4e17 mov.w lr, r7, lsr #16 + 80007f0: fbb8 f1fe udiv r1, r8, lr + 80007f4: fa1f fc87 uxth.w ip, r7 + 80007f8: fb0e 8811 mls r8, lr, r1, r8 + 80007fc: fb01 f20c mul.w r2, r1, ip + 8000800: 0c23 lsrs r3, r4, #16 + 8000802: ea43 4308 orr.w r3, r3, r8, lsl #16 + 8000806: 429a cmp r2, r3 + 8000808: d909 bls.n 800081e <__udivmoddi4+0x62> + 800080a: 18fb adds r3, r7, r3 + 800080c: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000810: f080 80eb bcs.w 80009ea <__udivmoddi4+0x22e> + 8000814: 429a cmp r2, r3 + 8000816: f240 80e8 bls.w 80009ea <__udivmoddi4+0x22e> + 800081a: 3902 subs r1, #2 + 800081c: 443b add r3, r7 + 800081e: 1a9a subs r2, r3, r2 + 8000820: fbb2 f0fe udiv r0, r2, lr + 8000824: fb0e 2210 mls r2, lr, r0, r2 + 8000828: fb00 fc0c mul.w ip, r0, ip + 800082c: b2a3 uxth r3, r4 + 800082e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000832: 459c cmp ip, r3 + 8000834: d909 bls.n 800084a <__udivmoddi4+0x8e> + 8000836: 18fb adds r3, r7, r3 + 8000838: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800083c: f080 80d7 bcs.w 80009ee <__udivmoddi4+0x232> + 8000840: 459c cmp ip, r3 + 8000842: f240 80d4 bls.w 80009ee <__udivmoddi4+0x232> + 8000846: 443b add r3, r7 + 8000848: 3802 subs r0, #2 + 800084a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800084e: 2100 movs r1, #0 + 8000850: eba3 030c sub.w r3, r3, ip + 8000854: b11d cbz r5, 800085e <__udivmoddi4+0xa2> + 8000856: 2200 movs r2, #0 + 8000858: 40f3 lsrs r3, r6 + 800085a: e9c5 3200 strd r3, r2, [r5] + 800085e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000862: 428b cmp r3, r1 + 8000864: d905 bls.n 8000872 <__udivmoddi4+0xb6> + 8000866: b10d cbz r5, 800086c <__udivmoddi4+0xb0> + 8000868: e9c5 0100 strd r0, r1, [r5] + 800086c: 2100 movs r1, #0 + 800086e: 4608 mov r0, r1 + 8000870: e7f5 b.n 800085e <__udivmoddi4+0xa2> + 8000872: fab3 f183 clz r1, r3 + 8000876: 2900 cmp r1, #0 + 8000878: d146 bne.n 8000908 <__udivmoddi4+0x14c> + 800087a: 4573 cmp r3, lr + 800087c: d302 bcc.n 8000884 <__udivmoddi4+0xc8> + 800087e: 4282 cmp r2, r0 + 8000880: f200 8108 bhi.w 8000a94 <__udivmoddi4+0x2d8> + 8000884: 1a84 subs r4, r0, r2 + 8000886: eb6e 0203 sbc.w r2, lr, r3 + 800088a: 2001 movs r0, #1 + 800088c: 4690 mov r8, r2 + 800088e: 2d00 cmp r5, #0 + 8000890: d0e5 beq.n 800085e <__udivmoddi4+0xa2> + 8000892: e9c5 4800 strd r4, r8, [r5] + 8000896: e7e2 b.n 800085e <__udivmoddi4+0xa2> + 8000898: 2a00 cmp r2, #0 + 800089a: f000 8091 beq.w 80009c0 <__udivmoddi4+0x204> + 800089e: fab2 f682 clz r6, r2 + 80008a2: 2e00 cmp r6, #0 + 80008a4: f040 80a5 bne.w 80009f2 <__udivmoddi4+0x236> + 80008a8: 1a8a subs r2, r1, r2 + 80008aa: 2101 movs r1, #1 + 80008ac: 0c03 lsrs r3, r0, #16 + 80008ae: ea4f 4e17 mov.w lr, r7, lsr #16 + 80008b2: b280 uxth r0, r0 + 80008b4: b2bc uxth r4, r7 + 80008b6: fbb2 fcfe udiv ip, r2, lr + 80008ba: fb0e 221c mls r2, lr, ip, r2 + 80008be: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80008c2: fb04 f20c mul.w r2, r4, ip + 80008c6: 429a cmp r2, r3 + 80008c8: d907 bls.n 80008da <__udivmoddi4+0x11e> + 80008ca: 18fb adds r3, r7, r3 + 80008cc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80008d0: d202 bcs.n 80008d8 <__udivmoddi4+0x11c> + 80008d2: 429a cmp r2, r3 + 80008d4: f200 80e3 bhi.w 8000a9e <__udivmoddi4+0x2e2> + 80008d8: 46c4 mov ip, r8 + 80008da: 1a9b subs r3, r3, r2 + 80008dc: fbb3 f2fe udiv r2, r3, lr + 80008e0: fb0e 3312 mls r3, lr, r2, r3 + 80008e4: fb02 f404 mul.w r4, r2, r4 + 80008e8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80008ec: 429c cmp r4, r3 + 80008ee: d907 bls.n 8000900 <__udivmoddi4+0x144> + 80008f0: 18fb adds r3, r7, r3 + 80008f2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80008f6: d202 bcs.n 80008fe <__udivmoddi4+0x142> + 80008f8: 429c cmp r4, r3 + 80008fa: f200 80cd bhi.w 8000a98 <__udivmoddi4+0x2dc> + 80008fe: 4602 mov r2, r0 + 8000900: 1b1b subs r3, r3, r4 + 8000902: ea42 400c orr.w r0, r2, ip, lsl #16 + 8000906: e7a5 b.n 8000854 <__udivmoddi4+0x98> + 8000908: f1c1 0620 rsb r6, r1, #32 + 800090c: 408b lsls r3, r1 + 800090e: fa22 f706 lsr.w r7, r2, r6 + 8000912: 431f orrs r7, r3 + 8000914: fa2e fa06 lsr.w sl, lr, r6 + 8000918: ea4f 4917 mov.w r9, r7, lsr #16 + 800091c: fbba f8f9 udiv r8, sl, r9 + 8000920: fa0e fe01 lsl.w lr, lr, r1 + 8000924: fa20 f306 lsr.w r3, r0, r6 + 8000928: fb09 aa18 mls sl, r9, r8, sl + 800092c: fa1f fc87 uxth.w ip, r7 + 8000930: ea43 030e orr.w r3, r3, lr + 8000934: fa00 fe01 lsl.w lr, r0, r1 + 8000938: fb08 f00c mul.w r0, r8, ip + 800093c: 0c1c lsrs r4, r3, #16 + 800093e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000942: 42a0 cmp r0, r4 + 8000944: fa02 f201 lsl.w r2, r2, r1 + 8000948: d90a bls.n 8000960 <__udivmoddi4+0x1a4> + 800094a: 193c adds r4, r7, r4 + 800094c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000950: f080 809e bcs.w 8000a90 <__udivmoddi4+0x2d4> + 8000954: 42a0 cmp r0, r4 + 8000956: f240 809b bls.w 8000a90 <__udivmoddi4+0x2d4> + 800095a: f1a8 0802 sub.w r8, r8, #2 + 800095e: 443c add r4, r7 + 8000960: 1a24 subs r4, r4, r0 + 8000962: b298 uxth r0, r3 + 8000964: fbb4 f3f9 udiv r3, r4, r9 + 8000968: fb09 4413 mls r4, r9, r3, r4 + 800096c: fb03 fc0c mul.w ip, r3, ip + 8000970: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000974: 45a4 cmp ip, r4 + 8000976: d909 bls.n 800098c <__udivmoddi4+0x1d0> + 8000978: 193c adds r4, r7, r4 + 800097a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800097e: f080 8085 bcs.w 8000a8c <__udivmoddi4+0x2d0> + 8000982: 45a4 cmp ip, r4 + 8000984: f240 8082 bls.w 8000a8c <__udivmoddi4+0x2d0> + 8000988: 3b02 subs r3, #2 + 800098a: 443c add r4, r7 + 800098c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000990: eba4 040c sub.w r4, r4, ip + 8000994: fba0 8c02 umull r8, ip, r0, r2 + 8000998: 4564 cmp r4, ip + 800099a: 4643 mov r3, r8 + 800099c: 46e1 mov r9, ip + 800099e: d364 bcc.n 8000a6a <__udivmoddi4+0x2ae> + 80009a0: d061 beq.n 8000a66 <__udivmoddi4+0x2aa> + 80009a2: b15d cbz r5, 80009bc <__udivmoddi4+0x200> + 80009a4: ebbe 0203 subs.w r2, lr, r3 + 80009a8: eb64 0409 sbc.w r4, r4, r9 + 80009ac: fa04 f606 lsl.w r6, r4, r6 + 80009b0: fa22 f301 lsr.w r3, r2, r1 + 80009b4: 431e orrs r6, r3 + 80009b6: 40cc lsrs r4, r1 + 80009b8: e9c5 6400 strd r6, r4, [r5] + 80009bc: 2100 movs r1, #0 + 80009be: e74e b.n 800085e <__udivmoddi4+0xa2> + 80009c0: fbb1 fcf2 udiv ip, r1, r2 + 80009c4: 0c01 lsrs r1, r0, #16 + 80009c6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80009ca: b280 uxth r0, r0 + 80009cc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80009d0: 463b mov r3, r7 + 80009d2: fbb1 f1f7 udiv r1, r1, r7 + 80009d6: 4638 mov r0, r7 + 80009d8: 463c mov r4, r7 + 80009da: 46b8 mov r8, r7 + 80009dc: 46be mov lr, r7 + 80009de: 2620 movs r6, #32 + 80009e0: eba2 0208 sub.w r2, r2, r8 + 80009e4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80009e8: e765 b.n 80008b6 <__udivmoddi4+0xfa> + 80009ea: 4601 mov r1, r0 + 80009ec: e717 b.n 800081e <__udivmoddi4+0x62> + 80009ee: 4610 mov r0, r2 + 80009f0: e72b b.n 800084a <__udivmoddi4+0x8e> + 80009f2: f1c6 0120 rsb r1, r6, #32 + 80009f6: fa2e fc01 lsr.w ip, lr, r1 + 80009fa: 40b7 lsls r7, r6 + 80009fc: fa0e fe06 lsl.w lr, lr, r6 + 8000a00: fa20 f101 lsr.w r1, r0, r1 + 8000a04: ea41 010e orr.w r1, r1, lr + 8000a08: ea4f 4e17 mov.w lr, r7, lsr #16 + 8000a0c: fbbc f8fe udiv r8, ip, lr + 8000a10: b2bc uxth r4, r7 + 8000a12: fb0e cc18 mls ip, lr, r8, ip + 8000a16: fb08 f904 mul.w r9, r8, r4 + 8000a1a: 0c0a lsrs r2, r1, #16 + 8000a1c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000a20: 40b0 lsls r0, r6 + 8000a22: 4591 cmp r9, r2 + 8000a24: ea4f 4310 mov.w r3, r0, lsr #16 + 8000a28: b280 uxth r0, r0 + 8000a2a: d93e bls.n 8000aaa <__udivmoddi4+0x2ee> + 8000a2c: 18ba adds r2, r7, r2 + 8000a2e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000a32: d201 bcs.n 8000a38 <__udivmoddi4+0x27c> + 8000a34: 4591 cmp r9, r2 + 8000a36: d81f bhi.n 8000a78 <__udivmoddi4+0x2bc> + 8000a38: eba2 0209 sub.w r2, r2, r9 + 8000a3c: fbb2 f9fe udiv r9, r2, lr + 8000a40: fb09 f804 mul.w r8, r9, r4 + 8000a44: fb0e 2a19 mls sl, lr, r9, r2 + 8000a48: b28a uxth r2, r1 + 8000a4a: ea42 420a orr.w r2, r2, sl, lsl #16 + 8000a4e: 4542 cmp r2, r8 + 8000a50: d229 bcs.n 8000aa6 <__udivmoddi4+0x2ea> + 8000a52: 18ba adds r2, r7, r2 + 8000a54: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000a58: d2c2 bcs.n 80009e0 <__udivmoddi4+0x224> + 8000a5a: 4542 cmp r2, r8 + 8000a5c: d2c0 bcs.n 80009e0 <__udivmoddi4+0x224> + 8000a5e: f1a9 0102 sub.w r1, r9, #2 + 8000a62: 443a add r2, r7 + 8000a64: e7bc b.n 80009e0 <__udivmoddi4+0x224> + 8000a66: 45c6 cmp lr, r8 + 8000a68: d29b bcs.n 80009a2 <__udivmoddi4+0x1e6> + 8000a6a: ebb8 0302 subs.w r3, r8, r2 + 8000a6e: eb6c 0c07 sbc.w ip, ip, r7 + 8000a72: 3801 subs r0, #1 + 8000a74: 46e1 mov r9, ip + 8000a76: e794 b.n 80009a2 <__udivmoddi4+0x1e6> + 8000a78: eba7 0909 sub.w r9, r7, r9 + 8000a7c: 444a add r2, r9 + 8000a7e: fbb2 f9fe udiv r9, r2, lr + 8000a82: f1a8 0c02 sub.w ip, r8, #2 + 8000a86: fb09 f804 mul.w r8, r9, r4 + 8000a8a: e7db b.n 8000a44 <__udivmoddi4+0x288> + 8000a8c: 4603 mov r3, r0 + 8000a8e: e77d b.n 800098c <__udivmoddi4+0x1d0> + 8000a90: 46d0 mov r8, sl + 8000a92: e765 b.n 8000960 <__udivmoddi4+0x1a4> + 8000a94: 4608 mov r0, r1 + 8000a96: e6fa b.n 800088e <__udivmoddi4+0xd2> + 8000a98: 443b add r3, r7 + 8000a9a: 3a02 subs r2, #2 + 8000a9c: e730 b.n 8000900 <__udivmoddi4+0x144> + 8000a9e: f1ac 0c02 sub.w ip, ip, #2 + 8000aa2: 443b add r3, r7 + 8000aa4: e719 b.n 80008da <__udivmoddi4+0x11e> + 8000aa6: 4649 mov r1, r9 + 8000aa8: e79a b.n 80009e0 <__udivmoddi4+0x224> + 8000aaa: eba2 0209 sub.w r2, r2, r9 + 8000aae: fbb2 f9fe udiv r9, r2, lr + 8000ab2: 46c4 mov ip, r8 + 8000ab4: fb09 f804 mul.w r8, r9, r4 + 8000ab8: e7c4 b.n 8000a44 <__udivmoddi4+0x288> + 8000aba: bf00 nop + +08000abc <__aeabi_idiv0>: + 8000abc: 4770 bx lr + 8000abe: bf00 nop + +08000ac0 : +/* USER CODE BEGIN 0 */ +volatile uint8_t angle = 0; +volatile uint8_t sens = 1; + + +void affiche(uint8_t nombre_entier, uint8_t nombre_decimal) { + 8000ac0: b580 push {r7, lr} + 8000ac2: b084 sub sp, #16 + 8000ac4: af00 add r7, sp, #0 + 8000ac6: 4603 mov r3, r0 + 8000ac8: 460a mov r2, r1 + 8000aca: 71fb strb r3, [r7, #7] + 8000acc: 4613 mov r3, r2 + 8000ace: 71bb strb r3, [r7, #6] + uint8_t compt_uni_ent; + uint8_t compt_diz_ent; + uint8_t compt_uni_deci; + uint8_t compt_diz_deci; + + compt_uni_ent = nombre_entier % 10; + 8000ad0: 79fa ldrb r2, [r7, #7] + 8000ad2: 4b1c ldr r3, [pc, #112] @ (8000b44 ) + 8000ad4: fba3 1302 umull r1, r3, r3, r2 + 8000ad8: 08d9 lsrs r1, r3, #3 + 8000ada: 460b mov r3, r1 + 8000adc: 009b lsls r3, r3, #2 + 8000ade: 440b add r3, r1 + 8000ae0: 005b lsls r3, r3, #1 + 8000ae2: 1ad3 subs r3, r2, r3 + 8000ae4: 73fb strb r3, [r7, #15] + compt_diz_ent = nombre_entier / 10; + 8000ae6: 79fb ldrb r3, [r7, #7] + 8000ae8: 4a16 ldr r2, [pc, #88] @ (8000b44 ) + 8000aea: fba2 2303 umull r2, r3, r2, r3 + 8000aee: 08db lsrs r3, r3, #3 + 8000af0: 73bb strb r3, [r7, #14] + + compt_uni_deci = nombre_decimal % 10; + 8000af2: 79ba ldrb r2, [r7, #6] + 8000af4: 4b13 ldr r3, [pc, #76] @ (8000b44 ) + 8000af6: fba3 1302 umull r1, r3, r3, r2 + 8000afa: 08d9 lsrs r1, r3, #3 + 8000afc: 460b mov r3, r1 + 8000afe: 009b lsls r3, r3, #2 + 8000b00: 440b add r3, r1 + 8000b02: 005b lsls r3, r3, #1 + 8000b04: 1ad3 subs r3, r2, r3 + 8000b06: 737b strb r3, [r7, #13] + compt_diz_deci = nombre_decimal / 10; + 8000b08: 79bb ldrb r3, [r7, #6] + 8000b0a: 4a0e ldr r2, [pc, #56] @ (8000b44 ) + 8000b0c: fba2 2303 umull r2, r3, r2, r3 + 8000b10: 08db lsrs r3, r3, #3 + 8000b12: 733b strb r3, [r7, #12] + + MAX7219_DisplayChar(1, compt_diz_ent); + 8000b14: 7bbb ldrb r3, [r7, #14] + 8000b16: 4619 mov r1, r3 + 8000b18: 2001 movs r0, #1 + 8000b1a: f000 fc17 bl 800134c + MAX7219_DisplayChar(2, compt_uni_ent); + 8000b1e: 7bfb ldrb r3, [r7, #15] + 8000b20: 4619 mov r1, r3 + 8000b22: 2002 movs r0, #2 + 8000b24: f000 fc12 bl 800134c + MAX7219_DisplayChar(3, compt_diz_deci); + 8000b28: 7b3b ldrb r3, [r7, #12] + 8000b2a: 4619 mov r1, r3 + 8000b2c: 2003 movs r0, #3 + 8000b2e: f000 fc0d bl 800134c + MAX7219_DisplayChar(4, compt_uni_deci); + 8000b32: 7b7b ldrb r3, [r7, #13] + 8000b34: 4619 mov r1, r3 + 8000b36: 2004 movs r0, #4 + 8000b38: f000 fc08 bl 800134c +} + 8000b3c: bf00 nop + 8000b3e: 3710 adds r7, #16 + 8000b40: 46bd mov sp, r7 + 8000b42: bd80 pop {r7, pc} + 8000b44: cccccccd .word 0xcccccccd + +08000b48
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000b48: b580 push {r7, lr} + 8000b4a: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000b4c: f000 fc44 bl 80013d8 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000b50: f000 f81a bl 8000b88 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000b54: f000 f960 bl 8000e18 + MX_SPI1_Init(); + 8000b58: f000 f85c bl 8000c14 + MX_TIM2_Init(); + 8000b5c: f000 f890 bl 8000c80 + MX_TIM3_Init(); + 8000b60: f000 f8da bl 8000d18 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 8000b64: f000 fba5 bl 80012b2 + HAL_TIM_Base_Start_IT(&htim2); + 8000b68: 4805 ldr r0, [pc, #20] @ (8000b80 ) + 8000b6a: f001 ffe7 bl 8002b3c + HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2); + 8000b6e: 2104 movs r1, #4 + 8000b70: 4804 ldr r0, [pc, #16] @ (8000b84 ) + 8000b72: f002 f87d bl 8002c70 + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 8000b76: f000 fbd3 bl 8001320 + while (1) + 8000b7a: bf00 nop + 8000b7c: e7fd b.n 8000b7a + 8000b7e: bf00 nop + 8000b80: 20000084 .word 0x20000084 + 8000b84: 200000c4 .word 0x200000c4 + +08000b88 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000b88: b580 push {r7, lr} + 8000b8a: b092 sub sp, #72 @ 0x48 + 8000b8c: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000b8e: f107 0314 add.w r3, r7, #20 + 8000b92: 2234 movs r2, #52 @ 0x34 + 8000b94: 2100 movs r1, #0 + 8000b96: 4618 mov r0, r3 + 8000b98: f002 fdfe bl 8003798 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000b9c: 463b mov r3, r7 + 8000b9e: 2200 movs r2, #0 + 8000ba0: 601a str r2, [r3, #0] + 8000ba2: 605a str r2, [r3, #4] + 8000ba4: 609a str r2, [r3, #8] + 8000ba6: 60da str r2, [r3, #12] + 8000ba8: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000baa: 4b19 ldr r3, [pc, #100] @ (8000c10 ) + 8000bac: 681b ldr r3, [r3, #0] + 8000bae: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 8000bb2: 4a17 ldr r2, [pc, #92] @ (8000c10 ) + 8000bb4: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000bb8: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000bba: 2302 movs r3, #2 + 8000bbc: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000bbe: 2301 movs r3, #1 + 8000bc0: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000bc2: 2310 movs r3, #16 + 8000bc4: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8000bc6: 2300 movs r3, #0 + 8000bc8: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000bca: f107 0314 add.w r3, r7, #20 + 8000bce: 4618 mov r0, r3 + 8000bd0: f000 ff48 bl 8001a64 + 8000bd4: 4603 mov r3, r0 + 8000bd6: 2b00 cmp r3, #0 + 8000bd8: d001 beq.n 8000bde + { + Error_Handler(); + 8000bda: f000 f9e5 bl 8000fa8 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000bde: 230f movs r3, #15 + 8000be0: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 8000be2: 2301 movs r3, #1 + 8000be4: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000be6: 2300 movs r3, #0 + 8000be8: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000bea: 2300 movs r3, #0 + 8000bec: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000bee: 2300 movs r3, #0 + 8000bf0: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 8000bf2: 463b mov r3, r7 + 8000bf4: 2100 movs r1, #0 + 8000bf6: 4618 mov r0, r3 + 8000bf8: f001 fa64 bl 80020c4 + 8000bfc: 4603 mov r3, r0 + 8000bfe: 2b00 cmp r3, #0 + 8000c00: d001 beq.n 8000c06 + { + Error_Handler(); + 8000c02: f000 f9d1 bl 8000fa8 + } +} + 8000c06: bf00 nop + 8000c08: 3748 adds r7, #72 @ 0x48 + 8000c0a: 46bd mov sp, r7 + 8000c0c: bd80 pop {r7, pc} + 8000c0e: bf00 nop + 8000c10: 40007000 .word 0x40007000 + +08000c14 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 8000c14: b580 push {r7, lr} + 8000c16: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 8000c18: 4b17 ldr r3, [pc, #92] @ (8000c78 ) + 8000c1a: 4a18 ldr r2, [pc, #96] @ (8000c7c ) + 8000c1c: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 8000c1e: 4b16 ldr r3, [pc, #88] @ (8000c78 ) + 8000c20: f44f 7282 mov.w r2, #260 @ 0x104 + 8000c24: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 8000c26: 4b14 ldr r3, [pc, #80] @ (8000c78 ) + 8000c28: 2200 movs r2, #0 + 8000c2a: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 8000c2c: 4b12 ldr r3, [pc, #72] @ (8000c78 ) + 8000c2e: 2200 movs r2, #0 + 8000c30: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 8000c32: 4b11 ldr r3, [pc, #68] @ (8000c78 ) + 8000c34: 2200 movs r2, #0 + 8000c36: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 8000c38: 4b0f ldr r3, [pc, #60] @ (8000c78 ) + 8000c3a: 2200 movs r2, #0 + 8000c3c: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 8000c3e: 4b0e ldr r3, [pc, #56] @ (8000c78 ) + 8000c40: f44f 7200 mov.w r2, #512 @ 0x200 + 8000c44: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8000c46: 4b0c ldr r3, [pc, #48] @ (8000c78 ) + 8000c48: 2200 movs r2, #0 + 8000c4a: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 8000c4c: 4b0a ldr r3, [pc, #40] @ (8000c78 ) + 8000c4e: 2200 movs r2, #0 + 8000c50: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 8000c52: 4b09 ldr r3, [pc, #36] @ (8000c78 ) + 8000c54: 2200 movs r2, #0 + 8000c56: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8000c58: 4b07 ldr r3, [pc, #28] @ (8000c78 ) + 8000c5a: 2200 movs r2, #0 + 8000c5c: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 8000c5e: 4b06 ldr r3, [pc, #24] @ (8000c78 ) + 8000c60: 220a movs r2, #10 + 8000c62: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8000c64: 4804 ldr r0, [pc, #16] @ (8000c78 ) + 8000c66: f001 fc7f bl 8002568 + 8000c6a: 4603 mov r3, r0 + 8000c6c: 2b00 cmp r3, #0 + 8000c6e: d001 beq.n 8000c74 + { + Error_Handler(); + 8000c70: f000 f99a bl 8000fa8 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 8000c74: bf00 nop + 8000c76: bd80 pop {r7, pc} + 8000c78: 2000002c .word 0x2000002c + 8000c7c: 40013000 .word 0x40013000 + +08000c80 : + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 8000c80: b580 push {r7, lr} + 8000c82: b086 sub sp, #24 + 8000c84: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8000c86: f107 0308 add.w r3, r7, #8 + 8000c8a: 2200 movs r2, #0 + 8000c8c: 601a str r2, [r3, #0] + 8000c8e: 605a str r2, [r3, #4] + 8000c90: 609a str r2, [r3, #8] + 8000c92: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000c94: 463b mov r3, r7 + 8000c96: 2200 movs r2, #0 + 8000c98: 601a str r2, [r3, #0] + 8000c9a: 605a str r2, [r3, #4] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8000c9c: 4b1d ldr r3, [pc, #116] @ (8000d14 ) + 8000c9e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 + 8000ca2: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 167-1; + 8000ca4: 4b1b ldr r3, [pc, #108] @ (8000d14 ) + 8000ca6: 22a6 movs r2, #166 @ 0xa6 + 8000ca8: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000caa: 4b1a ldr r3, [pc, #104] @ (8000d14 ) + 8000cac: 2200 movs r2, #0 + 8000cae: 609a str r2, [r3, #8] + htim2.Init.Period = 16000-1; + 8000cb0: 4b18 ldr r3, [pc, #96] @ (8000d14 ) + 8000cb2: f643 627f movw r2, #15999 @ 0x3e7f + 8000cb6: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000cb8: 4b16 ldr r3, [pc, #88] @ (8000d14 ) + 8000cba: 2200 movs r2, #0 + 8000cbc: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 8000cbe: 4b15 ldr r3, [pc, #84] @ (8000d14 ) + 8000cc0: 2280 movs r2, #128 @ 0x80 + 8000cc2: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + 8000cc4: 4813 ldr r0, [pc, #76] @ (8000d14 ) + 8000cc6: f001 fef9 bl 8002abc + 8000cca: 4603 mov r3, r0 + 8000ccc: 2b00 cmp r3, #0 + 8000cce: d001 beq.n 8000cd4 + { + Error_Handler(); + 8000cd0: f000 f96a bl 8000fa8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000cd4: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8000cd8: 60bb str r3, [r7, #8] + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + 8000cda: f107 0308 add.w r3, r7, #8 + 8000cde: 4619 mov r1, r3 + 8000ce0: 480c ldr r0, [pc, #48] @ (8000d14 ) + 8000ce2: f002 f9e9 bl 80030b8 + 8000ce6: 4603 mov r3, r0 + 8000ce8: 2b00 cmp r3, #0 + 8000cea: d001 beq.n 8000cf0 + { + Error_Handler(); + 8000cec: f000 f95c bl 8000fa8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000cf0: 2300 movs r3, #0 + 8000cf2: 603b str r3, [r7, #0] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000cf4: 2300 movs r3, #0 + 8000cf6: 607b str r3, [r7, #4] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 8000cf8: 463b mov r3, r7 + 8000cfa: 4619 mov r1, r3 + 8000cfc: 4805 ldr r0, [pc, #20] @ (8000d14 ) + 8000cfe: f002 fced bl 80036dc + 8000d02: 4603 mov r3, r0 + 8000d04: 2b00 cmp r3, #0 + 8000d06: d001 beq.n 8000d0c + { + Error_Handler(); + 8000d08: f000 f94e bl 8000fa8 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 8000d0c: bf00 nop + 8000d0e: 3718 adds r7, #24 + 8000d10: 46bd mov sp, r7 + 8000d12: bd80 pop {r7, pc} + 8000d14: 20000084 .word 0x20000084 + +08000d18 : + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + 8000d18: b580 push {r7, lr} + 8000d1a: b08a sub sp, #40 @ 0x28 + 8000d1c: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8000d1e: f107 0318 add.w r3, r7, #24 + 8000d22: 2200 movs r2, #0 + 8000d24: 601a str r2, [r3, #0] + 8000d26: 605a str r2, [r3, #4] + 8000d28: 609a str r2, [r3, #8] + 8000d2a: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000d2c: f107 0310 add.w r3, r7, #16 + 8000d30: 2200 movs r2, #0 + 8000d32: 601a str r2, [r3, #0] + 8000d34: 605a str r2, [r3, #4] + TIM_OC_InitTypeDef sConfigOC = {0}; + 8000d36: 463b mov r3, r7 + 8000d38: 2200 movs r2, #0 + 8000d3a: 601a str r2, [r3, #0] + 8000d3c: 605a str r2, [r3, #4] + 8000d3e: 609a str r2, [r3, #8] + 8000d40: 60da str r2, [r3, #12] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 8000d42: 4b33 ldr r3, [pc, #204] @ (8000e10 ) + 8000d44: 4a33 ldr r2, [pc, #204] @ (8000e14 ) + 8000d46: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 20-1; + 8000d48: 4b31 ldr r3, [pc, #196] @ (8000e10 ) + 8000d4a: 2213 movs r2, #19 + 8000d4c: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 8000d4e: 4b30 ldr r3, [pc, #192] @ (8000e10 ) + 8000d50: 2200 movs r2, #0 + 8000d52: 609a str r2, [r3, #8] + htim3.Init.Period = 16000-1; + 8000d54: 4b2e ldr r3, [pc, #184] @ (8000e10 ) + 8000d56: f643 627f movw r2, #15999 @ 0x3e7f + 8000d5a: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000d5c: 4b2c ldr r3, [pc, #176] @ (8000e10 ) + 8000d5e: 2200 movs r2, #0 + 8000d60: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 8000d62: 4b2b ldr r3, [pc, #172] @ (8000e10 ) + 8000d64: 2280 movs r2, #128 @ 0x80 + 8000d66: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + 8000d68: 4829 ldr r0, [pc, #164] @ (8000e10 ) + 8000d6a: f001 fea7 bl 8002abc + 8000d6e: 4603 mov r3, r0 + 8000d70: 2b00 cmp r3, #0 + 8000d72: d001 beq.n 8000d78 + { + Error_Handler(); + 8000d74: f000 f918 bl 8000fa8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000d78: f44f 5380 mov.w r3, #4096 @ 0x1000 + 8000d7c: 61bb str r3, [r7, #24] + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + 8000d7e: f107 0318 add.w r3, r7, #24 + 8000d82: 4619 mov r1, r3 + 8000d84: 4822 ldr r0, [pc, #136] @ (8000e10 ) + 8000d86: f002 f997 bl 80030b8 + 8000d8a: 4603 mov r3, r0 + 8000d8c: 2b00 cmp r3, #0 + 8000d8e: d001 beq.n 8000d94 + { + Error_Handler(); + 8000d90: f000 f90a bl 8000fa8 + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + 8000d94: 481e ldr r0, [pc, #120] @ (8000e10 ) + 8000d96: f001 ff23 bl 8002be0 + 8000d9a: 4603 mov r3, r0 + 8000d9c: 2b00 cmp r3, #0 + 8000d9e: d001 beq.n 8000da4 + { + Error_Handler(); + 8000da0: f000 f902 bl 8000fa8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8000da4: 2300 movs r3, #0 + 8000da6: 613b str r3, [r7, #16] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8000da8: 2300 movs r3, #0 + 8000daa: 617b str r3, [r7, #20] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 8000dac: f107 0310 add.w r3, r7, #16 + 8000db0: 4619 mov r1, r3 + 8000db2: 4817 ldr r0, [pc, #92] @ (8000e10 ) + 8000db4: f002 fc92 bl 80036dc + 8000db8: 4603 mov r3, r0 + 8000dba: 2b00 cmp r3, #0 + 8000dbc: d001 beq.n 8000dc2 + { + Error_Handler(); + 8000dbe: f000 f8f3 bl 8000fa8 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 8000dc2: 2360 movs r3, #96 @ 0x60 + 8000dc4: 603b str r3, [r7, #0] + sConfigOC.Pulse = 80-1; + 8000dc6: 234f movs r3, #79 @ 0x4f + 8000dc8: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 8000dca: 2300 movs r3, #0 + 8000dcc: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 8000dce: 2300 movs r3, #0 + 8000dd0: 60fb str r3, [r7, #12] + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 8000dd2: 463b mov r3, r7 + 8000dd4: 2200 movs r2, #0 + 8000dd6: 4619 mov r1, r3 + 8000dd8: 480d ldr r0, [pc, #52] @ (8000e10 ) + 8000dda: f002 f8ab bl 8002f34 + 8000dde: 4603 mov r3, r0 + 8000de0: 2b00 cmp r3, #0 + 8000de2: d001 beq.n 8000de8 + { + Error_Handler(); + 8000de4: f000 f8e0 bl 8000fa8 + } + sConfigOC.Pulse = 0; + 8000de8: 2300 movs r3, #0 + 8000dea: 607b str r3, [r7, #4] + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + 8000dec: 463b mov r3, r7 + 8000dee: 2204 movs r2, #4 + 8000df0: 4619 mov r1, r3 + 8000df2: 4807 ldr r0, [pc, #28] @ (8000e10 ) + 8000df4: f002 f89e bl 8002f34 + 8000df8: 4603 mov r3, r0 + 8000dfa: 2b00 cmp r3, #0 + 8000dfc: d001 beq.n 8000e02 + { + Error_Handler(); + 8000dfe: f000 f8d3 bl 8000fa8 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + 8000e02: 4803 ldr r0, [pc, #12] @ (8000e10 ) + 8000e04: f000 f988 bl 8001118 + +} + 8000e08: bf00 nop + 8000e0a: 3728 adds r7, #40 @ 0x28 + 8000e0c: 46bd mov sp, r7 + 8000e0e: bd80 pop {r7, pc} + 8000e10: 200000c4 .word 0x200000c4 + 8000e14: 40000400 .word 0x40000400 + +08000e18 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000e18: b580 push {r7, lr} + 8000e1a: b088 sub sp, #32 + 8000e1c: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000e1e: f107 030c add.w r3, r7, #12 + 8000e22: 2200 movs r2, #0 + 8000e24: 601a str r2, [r3, #0] + 8000e26: 605a str r2, [r3, #4] + 8000e28: 609a str r2, [r3, #8] + 8000e2a: 60da str r2, [r3, #12] + 8000e2c: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000e2e: 4b28 ldr r3, [pc, #160] @ (8000ed0 ) + 8000e30: 69db ldr r3, [r3, #28] + 8000e32: 4a27 ldr r2, [pc, #156] @ (8000ed0 ) + 8000e34: f043 0304 orr.w r3, r3, #4 + 8000e38: 61d3 str r3, [r2, #28] + 8000e3a: 4b25 ldr r3, [pc, #148] @ (8000ed0 ) + 8000e3c: 69db ldr r3, [r3, #28] + 8000e3e: f003 0304 and.w r3, r3, #4 + 8000e42: 60bb str r3, [r7, #8] + 8000e44: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000e46: 4b22 ldr r3, [pc, #136] @ (8000ed0 ) + 8000e48: 69db ldr r3, [r3, #28] + 8000e4a: 4a21 ldr r2, [pc, #132] @ (8000ed0 ) + 8000e4c: f043 0301 orr.w r3, r3, #1 + 8000e50: 61d3 str r3, [r2, #28] + 8000e52: 4b1f ldr r3, [pc, #124] @ (8000ed0 ) + 8000e54: 69db ldr r3, [r3, #28] + 8000e56: f003 0301 and.w r3, r3, #1 + 8000e5a: 607b str r3, [r7, #4] + 8000e5c: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000e5e: 4b1c ldr r3, [pc, #112] @ (8000ed0 ) + 8000e60: 69db ldr r3, [r3, #28] + 8000e62: 4a1b ldr r2, [pc, #108] @ (8000ed0 ) + 8000e64: f043 0302 orr.w r3, r3, #2 + 8000e68: 61d3 str r3, [r2, #28] + 8000e6a: 4b19 ldr r3, [pc, #100] @ (8000ed0 ) + 8000e6c: 69db ldr r3, [r3, #28] + 8000e6e: f003 0302 and.w r3, r3, #2 + 8000e72: 603b str r3, [r7, #0] + 8000e74: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 8000e76: 2200 movs r2, #0 + 8000e78: 2101 movs r1, #1 + 8000e7a: 4816 ldr r0, [pc, #88] @ (8000ed4 ) + 8000e7c: f000 fdb8 bl 80019f0 + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 8000e80: 2301 movs r3, #1 + 8000e82: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000e84: 2301 movs r3, #1 + 8000e86: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000e88: 2300 movs r3, #0 + 8000e8a: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000e8c: 2300 movs r3, #0 + 8000e8e: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8000e90: f107 030c add.w r3, r7, #12 + 8000e94: 4619 mov r1, r3 + 8000e96: 480f ldr r0, [pc, #60] @ (8000ed4 ) + 8000e98: f000 fc1a bl 80016d0 + + /*Configure GPIO pins : PA11 PA12 */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 8000e9c: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 8000ea0: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 8000ea2: f44f 1388 mov.w r3, #1114112 @ 0x110000 + 8000ea6: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000ea8: 2300 movs r3, #0 + 8000eaa: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000eac: f107 030c add.w r3, r7, #12 + 8000eb0: 4619 mov r1, r3 + 8000eb2: 4809 ldr r0, [pc, #36] @ (8000ed8 ) + 8000eb4: f000 fc0c bl 80016d0 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 8000eb8: 2200 movs r2, #0 + 8000eba: 2100 movs r1, #0 + 8000ebc: 2028 movs r0, #40 @ 0x28 + 8000ebe: f000 fbd0 bl 8001662 + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 8000ec2: 2028 movs r0, #40 @ 0x28 + 8000ec4: f000 fbe9 bl 800169a + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 8000ec8: bf00 nop + 8000eca: 3720 adds r7, #32 + 8000ecc: 46bd mov sp, r7 + 8000ece: bd80 pop {r7, pc} + 8000ed0: 40023800 .word 0x40023800 + 8000ed4: 40020800 .word 0x40020800 + 8000ed8: 40020000 .word 0x40020000 + 8000edc: 00000000 .word 0x00000000 + +08000ee0 : + +/* USER CODE BEGIN 4 */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { + 8000ee0: b590 push {r4, r7, lr} + 8000ee2: b083 sub sp, #12 + 8000ee4: af00 add r7, sp, #0 + 8000ee6: 6078 str r0, [r7, #4] + if (htim->Instance == TIM2) { + 8000ee8: 687b ldr r3, [r7, #4] + 8000eea: 681b ldr r3, [r3, #0] + 8000eec: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8000ef0: d147 bne.n 8000f82 + if (sens) { + 8000ef2: 4b29 ldr r3, [pc, #164] @ (8000f98 ) + 8000ef4: 781b ldrb r3, [r3, #0] + 8000ef6: b2db uxtb r3, r3 + 8000ef8: 2b00 cmp r3, #0 + 8000efa: d00f beq.n 8000f1c + angle++; + 8000efc: 4b27 ldr r3, [pc, #156] @ (8000f9c ) + 8000efe: 781b ldrb r3, [r3, #0] + 8000f00: b2db uxtb r3, r3 + 8000f02: 3301 adds r3, #1 + 8000f04: b2da uxtb r2, r3 + 8000f06: 4b25 ldr r3, [pc, #148] @ (8000f9c ) + 8000f08: 701a strb r2, [r3, #0] + if (angle >= 90) { + 8000f0a: 4b24 ldr r3, [pc, #144] @ (8000f9c ) + 8000f0c: 781b ldrb r3, [r3, #0] + 8000f0e: b2db uxtb r3, r3 + 8000f10: 2b59 cmp r3, #89 @ 0x59 + 8000f12: d912 bls.n 8000f3a + sens = 0; + 8000f14: 4b20 ldr r3, [pc, #128] @ (8000f98 ) + 8000f16: 2200 movs r2, #0 + 8000f18: 701a strb r2, [r3, #0] + 8000f1a: e00e b.n 8000f3a + } + } else { + angle--; + 8000f1c: 4b1f ldr r3, [pc, #124] @ (8000f9c ) + 8000f1e: 781b ldrb r3, [r3, #0] + 8000f20: b2db uxtb r3, r3 + 8000f22: 3b01 subs r3, #1 + 8000f24: b2da uxtb r2, r3 + 8000f26: 4b1d ldr r3, [pc, #116] @ (8000f9c ) + 8000f28: 701a strb r2, [r3, #0] + if (angle <= 0) { + 8000f2a: 4b1c ldr r3, [pc, #112] @ (8000f9c ) + 8000f2c: 781b ldrb r3, [r3, #0] + 8000f2e: b2db uxtb r3, r3 + 8000f30: 2b00 cmp r3, #0 + 8000f32: d102 bne.n 8000f3a + sens = 1; + 8000f34: 4b18 ldr r3, [pc, #96] @ (8000f98 ) + 8000f36: 2201 movs r2, #1 + 8000f38: 701a strb r2, [r3, #0] + } + } + affiche(angle, 0); + 8000f3a: 4b18 ldr r3, [pc, #96] @ (8000f9c ) + 8000f3c: 781b ldrb r3, [r3, #0] + 8000f3e: b2db uxtb r3, r3 + 8000f40: 2100 movs r1, #0 + 8000f42: 4618 mov r0, r3 + 8000f44: f7ff fdbc bl 8000ac0 + + TIM3->CCR2 = 800 + angle * 8.9; + 8000f48: 4b14 ldr r3, [pc, #80] @ (8000f9c ) + 8000f4a: 781b ldrb r3, [r3, #0] + 8000f4c: b2db uxtb r3, r3 + 8000f4e: 4618 mov r0, r3 + 8000f50: f7ff fb92 bl 8000678 <__aeabi_i2d> + 8000f54: a30e add r3, pc, #56 @ (adr r3, 8000f90 ) + 8000f56: e9d3 2300 ldrd r2, r3, [r3] + 8000f5a: f7ff f911 bl 8000180 <__aeabi_dmul> + 8000f5e: 4602 mov r2, r0 + 8000f60: 460b mov r3, r1 + 8000f62: 4610 mov r0, r2 + 8000f64: 4619 mov r1, r3 + 8000f66: f04f 0200 mov.w r2, #0 + 8000f6a: 4b0d ldr r3, [pc, #52] @ (8000fa0 ) + 8000f6c: f7ff fa38 bl 80003e0 <__adddf3> + 8000f70: 4602 mov r2, r0 + 8000f72: 460b mov r3, r1 + 8000f74: 4c0b ldr r4, [pc, #44] @ (8000fa4 ) + 8000f76: 4610 mov r0, r2 + 8000f78: 4619 mov r1, r3 + 8000f7a: f7ff fbe7 bl 800074c <__aeabi_d2uiz> + 8000f7e: 4603 mov r3, r0 + 8000f80: 63a3 str r3, [r4, #56] @ 0x38 + + //__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_2, 800 + angle * 8.9); + } +} + 8000f82: bf00 nop + 8000f84: 370c adds r7, #12 + 8000f86: 46bd mov sp, r7 + 8000f88: bd90 pop {r4, r7, pc} + 8000f8a: bf00 nop + 8000f8c: f3af 8000 nop.w + 8000f90: cccccccd .word 0xcccccccd + 8000f94: 4021cccc .word 0x4021cccc + 8000f98: 20000000 .word 0x20000000 + 8000f9c: 20000104 .word 0x20000104 + 8000fa0: 40890000 .word 0x40890000 + 8000fa4: 40000400 .word 0x40000400 + +08000fa8 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000fa8: b480 push {r7} + 8000faa: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000fac: b672 cpsid i +} + 8000fae: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000fb0: bf00 nop + 8000fb2: e7fd b.n 8000fb0 + +08000fb4 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000fb4: b480 push {r7} + 8000fb6: b085 sub sp, #20 + 8000fb8: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 8000fba: 4b14 ldr r3, [pc, #80] @ (800100c ) + 8000fbc: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000fbe: 4a13 ldr r2, [pc, #76] @ (800100c ) + 8000fc0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 8000fc4: 6253 str r3, [r2, #36] @ 0x24 + 8000fc6: 4b11 ldr r3, [pc, #68] @ (800100c ) + 8000fc8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000fca: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8000fce: 60fb str r3, [r7, #12] + 8000fd0: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000fd2: 4b0e ldr r3, [pc, #56] @ (800100c ) + 8000fd4: 6a1b ldr r3, [r3, #32] + 8000fd6: 4a0d ldr r2, [pc, #52] @ (800100c ) + 8000fd8: f043 0301 orr.w r3, r3, #1 + 8000fdc: 6213 str r3, [r2, #32] + 8000fde: 4b0b ldr r3, [pc, #44] @ (800100c ) + 8000fe0: 6a1b ldr r3, [r3, #32] + 8000fe2: f003 0301 and.w r3, r3, #1 + 8000fe6: 60bb str r3, [r7, #8] + 8000fe8: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 8000fea: 4b08 ldr r3, [pc, #32] @ (800100c ) + 8000fec: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000fee: 4a07 ldr r2, [pc, #28] @ (800100c ) + 8000ff0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000ff4: 6253 str r3, [r2, #36] @ 0x24 + 8000ff6: 4b05 ldr r3, [pc, #20] @ (800100c ) + 8000ff8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000ffa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000ffe: 607b str r3, [r7, #4] + 8001000: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8001002: bf00 nop + 8001004: 3714 adds r7, #20 + 8001006: 46bd mov sp, r7 + 8001008: bc80 pop {r7} + 800100a: 4770 bx lr + 800100c: 40023800 .word 0x40023800 + +08001010 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8001010: b580 push {r7, lr} + 8001012: b08a sub sp, #40 @ 0x28 + 8001014: af00 add r7, sp, #0 + 8001016: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001018: f107 0314 add.w r3, r7, #20 + 800101c: 2200 movs r2, #0 + 800101e: 601a str r2, [r3, #0] + 8001020: 605a str r2, [r3, #4] + 8001022: 609a str r2, [r3, #8] + 8001024: 60da str r2, [r3, #12] + 8001026: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 8001028: 687b ldr r3, [r7, #4] + 800102a: 681b ldr r3, [r3, #0] + 800102c: 4a17 ldr r2, [pc, #92] @ (800108c ) + 800102e: 4293 cmp r3, r2 + 8001030: d127 bne.n 8001082 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 8001032: 4b17 ldr r3, [pc, #92] @ (8001090 ) + 8001034: 6a1b ldr r3, [r3, #32] + 8001036: 4a16 ldr r2, [pc, #88] @ (8001090 ) + 8001038: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 800103c: 6213 str r3, [r2, #32] + 800103e: 4b14 ldr r3, [pc, #80] @ (8001090 ) + 8001040: 6a1b ldr r3, [r3, #32] + 8001042: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8001046: 613b str r3, [r7, #16] + 8001048: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800104a: 4b11 ldr r3, [pc, #68] @ (8001090 ) + 800104c: 69db ldr r3, [r3, #28] + 800104e: 4a10 ldr r2, [pc, #64] @ (8001090 ) + 8001050: f043 0301 orr.w r3, r3, #1 + 8001054: 61d3 str r3, [r2, #28] + 8001056: 4b0e ldr r3, [pc, #56] @ (8001090 ) + 8001058: 69db ldr r3, [r3, #28] + 800105a: f003 0301 and.w r3, r3, #1 + 800105e: 60fb str r3, [r7, #12] + 8001060: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 8001062: 23e0 movs r3, #224 @ 0xe0 + 8001064: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001066: 2302 movs r3, #2 + 8001068: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800106a: 2300 movs r3, #0 + 800106c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800106e: 2303 movs r3, #3 + 8001070: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8001072: 2305 movs r3, #5 + 8001074: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001076: f107 0314 add.w r3, r7, #20 + 800107a: 4619 mov r1, r3 + 800107c: 4805 ldr r0, [pc, #20] @ (8001094 ) + 800107e: f000 fb27 bl 80016d0 + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 8001082: bf00 nop + 8001084: 3728 adds r7, #40 @ 0x28 + 8001086: 46bd mov sp, r7 + 8001088: bd80 pop {r7, pc} + 800108a: bf00 nop + 800108c: 40013000 .word 0x40013000 + 8001090: 40023800 .word 0x40023800 + 8001094: 40020000 .word 0x40020000 + +08001098 : + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8001098: b580 push {r7, lr} + 800109a: b084 sub sp, #16 + 800109c: af00 add r7, sp, #0 + 800109e: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM2) + 80010a0: 687b ldr r3, [r7, #4] + 80010a2: 681b ldr r3, [r3, #0] + 80010a4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80010a8: d114 bne.n 80010d4 + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + 80010aa: 4b19 ldr r3, [pc, #100] @ (8001110 ) + 80010ac: 6a5b ldr r3, [r3, #36] @ 0x24 + 80010ae: 4a18 ldr r2, [pc, #96] @ (8001110 ) + 80010b0: f043 0301 orr.w r3, r3, #1 + 80010b4: 6253 str r3, [r2, #36] @ 0x24 + 80010b6: 4b16 ldr r3, [pc, #88] @ (8001110 ) + 80010b8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80010ba: f003 0301 and.w r3, r3, #1 + 80010be: 60fb str r3, [r7, #12] + 80010c0: 68fb ldr r3, [r7, #12] + /* TIM2 interrupt Init */ + HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); + 80010c2: 2200 movs r2, #0 + 80010c4: 2100 movs r1, #0 + 80010c6: 201c movs r0, #28 + 80010c8: f000 facb bl 8001662 + HAL_NVIC_EnableIRQ(TIM2_IRQn); + 80010cc: 201c movs r0, #28 + 80010ce: f000 fae4 bl 800169a + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + +} + 80010d2: e018 b.n 8001106 + else if(htim_base->Instance==TIM3) + 80010d4: 687b ldr r3, [r7, #4] + 80010d6: 681b ldr r3, [r3, #0] + 80010d8: 4a0e ldr r2, [pc, #56] @ (8001114 ) + 80010da: 4293 cmp r3, r2 + 80010dc: d113 bne.n 8001106 + __HAL_RCC_TIM3_CLK_ENABLE(); + 80010de: 4b0c ldr r3, [pc, #48] @ (8001110 ) + 80010e0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80010e2: 4a0b ldr r2, [pc, #44] @ (8001110 ) + 80010e4: f043 0302 orr.w r3, r3, #2 + 80010e8: 6253 str r3, [r2, #36] @ 0x24 + 80010ea: 4b09 ldr r3, [pc, #36] @ (8001110 ) + 80010ec: 6a5b ldr r3, [r3, #36] @ 0x24 + 80010ee: f003 0302 and.w r3, r3, #2 + 80010f2: 60bb str r3, [r7, #8] + 80010f4: 68bb ldr r3, [r7, #8] + HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); + 80010f6: 2200 movs r2, #0 + 80010f8: 2100 movs r1, #0 + 80010fa: 201d movs r0, #29 + 80010fc: f000 fab1 bl 8001662 + HAL_NVIC_EnableIRQ(TIM3_IRQn); + 8001100: 201d movs r0, #29 + 8001102: f000 faca bl 800169a +} + 8001106: bf00 nop + 8001108: 3710 adds r7, #16 + 800110a: 46bd mov sp, r7 + 800110c: bd80 pop {r7, pc} + 800110e: bf00 nop + 8001110: 40023800 .word 0x40023800 + 8001114: 40000400 .word 0x40000400 + +08001118 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8001118: b580 push {r7, lr} + 800111a: b08a sub sp, #40 @ 0x28 + 800111c: af00 add r7, sp, #0 + 800111e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001120: f107 0314 add.w r3, r7, #20 + 8001124: 2200 movs r2, #0 + 8001126: 601a str r2, [r3, #0] + 8001128: 605a str r2, [r3, #4] + 800112a: 609a str r2, [r3, #8] + 800112c: 60da str r2, [r3, #12] + 800112e: 611a str r2, [r3, #16] + if(htim->Instance==TIM3) + 8001130: 687b ldr r3, [r7, #4] + 8001132: 681b ldr r3, [r3, #0] + 8001134: 4a1f ldr r2, [pc, #124] @ (80011b4 ) + 8001136: 4293 cmp r3, r2 + 8001138: d137 bne.n 80011aa + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800113a: 4b1f ldr r3, [pc, #124] @ (80011b8 ) + 800113c: 69db ldr r3, [r3, #28] + 800113e: 4a1e ldr r2, [pc, #120] @ (80011b8 ) + 8001140: f043 0304 orr.w r3, r3, #4 + 8001144: 61d3 str r3, [r2, #28] + 8001146: 4b1c ldr r3, [pc, #112] @ (80011b8 ) + 8001148: 69db ldr r3, [r3, #28] + 800114a: f003 0304 and.w r3, r3, #4 + 800114e: 613b str r3, [r7, #16] + 8001150: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001152: 4b19 ldr r3, [pc, #100] @ (80011b8 ) + 8001154: 69db ldr r3, [r3, #28] + 8001156: 4a18 ldr r2, [pc, #96] @ (80011b8 ) + 8001158: f043 0302 orr.w r3, r3, #2 + 800115c: 61d3 str r3, [r2, #28] + 800115e: 4b16 ldr r3, [pc, #88] @ (80011b8 ) + 8001160: 69db ldr r3, [r3, #28] + 8001162: f003 0302 and.w r3, r3, #2 + 8001166: 60fb str r3, [r7, #12] + 8001168: 68fb ldr r3, [r7, #12] + /**TIM3 GPIO Configuration + PC6 ------> TIM3_CH1 + PB5 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + 800116a: 2340 movs r3, #64 @ 0x40 + 800116c: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800116e: 2302 movs r3, #2 + 8001170: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001172: 2300 movs r3, #0 + 8001174: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001176: 2300 movs r3, #0 + 8001178: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 800117a: 2302 movs r3, #2 + 800117c: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 800117e: f107 0314 add.w r3, r7, #20 + 8001182: 4619 mov r1, r3 + 8001184: 480d ldr r0, [pc, #52] @ (80011bc ) + 8001186: f000 faa3 bl 80016d0 + + GPIO_InitStruct.Pin = GPIO_PIN_5; + 800118a: 2320 movs r3, #32 + 800118c: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800118e: 2302 movs r3, #2 + 8001190: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001192: 2300 movs r3, #0 + 8001194: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001196: 2300 movs r3, #0 + 8001198: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 800119a: 2302 movs r3, #2 + 800119c: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800119e: f107 0314 add.w r3, r7, #20 + 80011a2: 4619 mov r1, r3 + 80011a4: 4806 ldr r0, [pc, #24] @ (80011c0 ) + 80011a6: f000 fa93 bl 80016d0 + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + +} + 80011aa: bf00 nop + 80011ac: 3728 adds r7, #40 @ 0x28 + 80011ae: 46bd mov sp, r7 + 80011b0: bd80 pop {r7, pc} + 80011b2: bf00 nop + 80011b4: 40000400 .word 0x40000400 + 80011b8: 40023800 .word 0x40023800 + 80011bc: 40020800 .word 0x40020800 + 80011c0: 40020400 .word 0x40020400 + +080011c4 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 80011c4: b480 push {r7} + 80011c6: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 80011c8: bf00 nop + 80011ca: e7fd b.n 80011c8 + +080011cc : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 80011cc: b480 push {r7} + 80011ce: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 80011d0: bf00 nop + 80011d2: e7fd b.n 80011d0 + +080011d4 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 80011d4: b480 push {r7} + 80011d6: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 80011d8: bf00 nop + 80011da: e7fd b.n 80011d8 + +080011dc : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 80011dc: b480 push {r7} + 80011de: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 80011e0: bf00 nop + 80011e2: e7fd b.n 80011e0 + +080011e4 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 80011e4: b480 push {r7} + 80011e6: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 80011e8: bf00 nop + 80011ea: e7fd b.n 80011e8 + +080011ec : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 80011ec: b480 push {r7} + 80011ee: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 80011f0: bf00 nop + 80011f2: 46bd mov sp, r7 + 80011f4: bc80 pop {r7} + 80011f6: 4770 bx lr + +080011f8 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 80011f8: b480 push {r7} + 80011fa: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 80011fc: bf00 nop + 80011fe: 46bd mov sp, r7 + 8001200: bc80 pop {r7} + 8001202: 4770 bx lr + +08001204 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8001204: b480 push {r7} + 8001206: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8001208: bf00 nop + 800120a: 46bd mov sp, r7 + 800120c: bc80 pop {r7} + 800120e: 4770 bx lr + +08001210 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8001210: b580 push {r7, lr} + 8001212: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8001214: f000 f932 bl 800147c + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8001218: bf00 nop + 800121a: bd80 pop {r7, pc} + +0800121c : + +/** + * @brief This function handles TIM2 global interrupt. + */ +void TIM2_IRQHandler(void) +{ + 800121c: b580 push {r7, lr} + 800121e: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM2_IRQn 0 */ + + /* USER CODE END TIM2_IRQn 0 */ + HAL_TIM_IRQHandler(&htim2); + 8001220: 4802 ldr r0, [pc, #8] @ (800122c ) + 8001222: f001 fdbb bl 8002d9c + /* USER CODE BEGIN TIM2_IRQn 1 */ + + /* USER CODE END TIM2_IRQn 1 */ +} + 8001226: bf00 nop + 8001228: bd80 pop {r7, pc} + 800122a: bf00 nop + 800122c: 20000084 .word 0x20000084 + +08001230 : + +/** + * @brief This function handles TIM3 global interrupt. + */ +void TIM3_IRQHandler(void) +{ + 8001230: b580 push {r7, lr} + 8001232: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM3_IRQn 0 */ + + /* USER CODE END TIM3_IRQn 0 */ + HAL_TIM_IRQHandler(&htim3); + 8001234: 4802 ldr r0, [pc, #8] @ (8001240 ) + 8001236: f001 fdb1 bl 8002d9c + /* USER CODE BEGIN TIM3_IRQn 1 */ + + /* USER CODE END TIM3_IRQn 1 */ +} + 800123a: bf00 nop + 800123c: bd80 pop {r7, pc} + 800123e: bf00 nop + 8001240: 200000c4 .word 0x200000c4 + +08001244 : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 8001244: b580 push {r7, lr} + 8001246: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + 8001248: f44f 6000 mov.w r0, #2048 @ 0x800 + 800124c: f000 fbe8 bl 8001a20 + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + 8001250: f44f 5080 mov.w r0, #4096 @ 0x1000 + 8001254: f000 fbe4 bl 8001a20 + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8001258: bf00 nop + 800125a: bd80 pop {r7, pc} + +0800125c : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 800125c: b480 push {r7} + 800125e: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8001260: bf00 nop + 8001262: 46bd mov sp, r7 + 8001264: bc80 pop {r7} + 8001266: 4770 bx lr + +08001268 : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 8001268: f7ff fff8 bl 800125c + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 800126c: 480b ldr r0, [pc, #44] @ (800129c ) + ldr r1, =_edata + 800126e: 490c ldr r1, [pc, #48] @ (80012a0 ) + ldr r2, =_sidata + 8001270: 4a0c ldr r2, [pc, #48] @ (80012a4 ) + movs r3, #0 + 8001272: 2300 movs r3, #0 + b LoopCopyDataInit + 8001274: e002 b.n 800127c + +08001276 : + +CopyDataInit: + ldr r4, [r2, r3] + 8001276: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8001278: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 800127a: 3304 adds r3, #4 + +0800127c : + +LoopCopyDataInit: + adds r4, r0, r3 + 800127c: 18c4 adds r4, r0, r3 + cmp r4, r1 + 800127e: 428c cmp r4, r1 + bcc CopyDataInit + 8001280: d3f9 bcc.n 8001276 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8001282: 4a09 ldr r2, [pc, #36] @ (80012a8 ) + ldr r4, =_ebss + 8001284: 4c09 ldr r4, [pc, #36] @ (80012ac ) + movs r3, #0 + 8001286: 2300 movs r3, #0 + b LoopFillZerobss + 8001288: e001 b.n 800128e + +0800128a : + +FillZerobss: + str r3, [r2] + 800128a: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 800128c: 3204 adds r2, #4 + +0800128e : + +LoopFillZerobss: + cmp r2, r4 + 800128e: 42a2 cmp r2, r4 + bcc FillZerobss + 8001290: d3fb bcc.n 800128a + +/* Call static constructors */ + bl __libc_init_array + 8001292: f002 fa89 bl 80037a8 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8001296: f7ff fc57 bl 8000b48
+ bx lr + 800129a: 4770 bx lr + ldr r0, =_sdata + 800129c: 20000000 .word 0x20000000 + ldr r1, =_edata + 80012a0: 20000010 .word 0x20000010 + ldr r2, =_sidata + 80012a4: 08003844 .word 0x08003844 + ldr r2, =_sbss + 80012a8: 20000010 .word 0x20000010 + ldr r4, =_ebss + 80012ac: 2000010c .word 0x2000010c + +080012b0 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80012b0: e7fe b.n 80012b0 + +080012b2 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 80012b2: b580 push {r7, lr} + 80012b4: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 80012b6: 2107 movs r1, #7 + 80012b8: 200b movs r0, #11 + 80012ba: f000 f85d bl 8001378 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 80012be: 2100 movs r1, #0 + 80012c0: 2009 movs r0, #9 + 80012c2: f000 f859 bl 8001378 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 80012c6: f000 f809 bl 80012dc + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 80012ca: f000 f80f bl 80012ec + MAX7219_Clear(); // clear all digits + 80012ce: f000 f827 bl 8001320 + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 80012d2: 200f movs r0, #15 + 80012d4: f000 f812 bl 80012fc +} + 80012d8: bf00 nop + 80012da: bd80 pop {r7, pc} + +080012dc : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 80012dc: b580 push {r7, lr} + 80012de: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 80012e0: 2101 movs r1, #1 + 80012e2: 200c movs r0, #12 + 80012e4: f000 f848 bl 8001378 +} + 80012e8: bf00 nop + 80012ea: bd80 pop {r7, pc} + +080012ec : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 80012ec: b580 push {r7, lr} + 80012ee: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 80012f0: 2100 movs r1, #0 + 80012f2: 200f movs r0, #15 + 80012f4: f000 f840 bl 8001378 +} + 80012f8: bf00 nop + 80012fa: bd80 pop {r7, pc} + +080012fc : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 80012fc: b580 push {r7, lr} + 80012fe: b082 sub sp, #8 + 8001300: af00 add r7, sp, #0 + 8001302: 4603 mov r3, r0 + 8001304: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 8001306: 79fb ldrb r3, [r7, #7] + 8001308: f003 030f and.w r3, r3, #15 + 800130c: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 800130e: 79fb ldrb r3, [r7, #7] + 8001310: 4619 mov r1, r3 + 8001312: 200a movs r0, #10 + 8001314: f000 f830 bl 8001378 +} + 8001318: bf00 nop + 800131a: 3708 adds r7, #8 + 800131c: 46bd mov sp, r7 + 800131e: bd80 pop {r7, pc} + +08001320 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 8001320: b580 push {r7, lr} + 8001322: b082 sub sp, #8 + 8001324: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 8001326: 2300 movs r3, #0 + 8001328: 71fb strb r3, [r7, #7] + 800132a: e007 b.n 800133c + MAX7219_Write(i, 0x00); // turn all segments off + 800132c: 79fb ldrb r3, [r7, #7] + 800132e: 2100 movs r1, #0 + 8001330: 4618 mov r0, r3 + 8001332: f000 f821 bl 8001378 + for (i=0; i < 8; i++) + 8001336: 79fb ldrb r3, [r7, #7] + 8001338: 3301 adds r3, #1 + 800133a: 71fb strb r3, [r7, #7] + 800133c: 79fb ldrb r3, [r7, #7] + 800133e: 2b07 cmp r3, #7 + 8001340: d9f4 bls.n 800132c +} + 8001342: bf00 nop + 8001344: bf00 nop + 8001346: 3708 adds r7, #8 + 8001348: 46bd mov sp, r7 + 800134a: bd80 pop {r7, pc} + +0800134c : +* character = character to display (0-9, A-Z) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayChar(char digit, char character) +{ + 800134c: b580 push {r7, lr} + 800134e: b082 sub sp, #8 + 8001350: af00 add r7, sp, #0 + 8001352: 4603 mov r3, r0 + 8001354: 460a mov r2, r1 + 8001356: 71fb strb r3, [r7, #7] + 8001358: 4613 mov r3, r2 + 800135a: 71bb strb r3, [r7, #6] + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]); + 800135c: 79bb ldrb r3, [r7, #6] + 800135e: 4a05 ldr r2, [pc, #20] @ (8001374 ) + 8001360: 5cd2 ldrb r2, [r2, r3] + 8001362: 79fb ldrb r3, [r7, #7] + 8001364: 4611 mov r1, r2 + 8001366: 4618 mov r0, r3 + 8001368: f000 f806 bl 8001378 +} + 800136c: bf00 nop + 800136e: 3708 adds r7, #8 + 8001370: 46bd mov sp, r7 + 8001372: bd80 pop {r7, pc} + 8001374: 08003824 .word 0x08003824 + +08001378 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8001378: b580 push {r7, lr} + 800137a: b082 sub sp, #8 + 800137c: af00 add r7, sp, #0 + 800137e: 4603 mov r3, r0 + 8001380: 460a mov r2, r1 + 8001382: 71fb strb r3, [r7, #7] + 8001384: 4613 mov r3, r2 + 8001386: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8001388: 4b09 ldr r3, [pc, #36] @ (80013b0 ) + 800138a: f44f 3280 mov.w r2, #65536 @ 0x10000 + 800138e: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8001390: 79fb ldrb r3, [r7, #7] + 8001392: 4618 mov r0, r3 + 8001394: f000 f80e bl 80013b4 + MAX7219_SendByte(dataout); // write data to MAX7219 + 8001398: 79bb ldrb r3, [r7, #6] + 800139a: 4618 mov r0, r3 + 800139c: f000 f80a bl 80013b4 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 80013a0: 4b03 ldr r3, [pc, #12] @ (80013b0 ) + 80013a2: 2201 movs r2, #1 + 80013a4: 619a str r2, [r3, #24] + } + 80013a6: bf00 nop + 80013a8: 3708 adds r7, #8 + 80013aa: 46bd mov sp, r7 + 80013ac: bd80 pop {r7, pc} + 80013ae: bf00 nop + 80013b0: 40020800 .word 0x40020800 + +080013b4 : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 80013b4: b580 push {r7, lr} + 80013b6: b082 sub sp, #8 + 80013b8: af00 add r7, sp, #0 + 80013ba: 4603 mov r3, r0 + 80013bc: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 80013be: 1df9 adds r1, r7, #7 + 80013c0: f44f 737a mov.w r3, #1000 @ 0x3e8 + 80013c4: 2201 movs r2, #1 + 80013c6: 4803 ldr r0, [pc, #12] @ (80013d4 ) + 80013c8: f001 f957 bl 800267a + +} + 80013cc: bf00 nop + 80013ce: 3708 adds r7, #8 + 80013d0: 46bd mov sp, r7 + 80013d2: bd80 pop {r7, pc} + 80013d4: 2000002c .word 0x2000002c + +080013d8 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 80013d8: b580 push {r7, lr} + 80013da: b082 sub sp, #8 + 80013dc: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 80013de: 2300 movs r3, #0 + 80013e0: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 80013e2: 2003 movs r0, #3 + 80013e4: f000 f932 bl 800164c + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 80013e8: 200f movs r0, #15 + 80013ea: f000 f80d bl 8001408 + 80013ee: 4603 mov r3, r0 + 80013f0: 2b00 cmp r3, #0 + 80013f2: d002 beq.n 80013fa + { + status = HAL_ERROR; + 80013f4: 2301 movs r3, #1 + 80013f6: 71fb strb r3, [r7, #7] + 80013f8: e001 b.n 80013fe + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 80013fa: f7ff fddb bl 8000fb4 + } + + /* Return function status */ + return status; + 80013fe: 79fb ldrb r3, [r7, #7] +} + 8001400: 4618 mov r0, r3 + 8001402: 3708 adds r7, #8 + 8001404: 46bd mov sp, r7 + 8001406: bd80 pop {r7, pc} + +08001408 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8001408: b580 push {r7, lr} + 800140a: b084 sub sp, #16 + 800140c: af00 add r7, sp, #0 + 800140e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8001410: 2300 movs r3, #0 + 8001412: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 8001414: 4b16 ldr r3, [pc, #88] @ (8001470 ) + 8001416: 681b ldr r3, [r3, #0] + 8001418: 2b00 cmp r3, #0 + 800141a: d022 beq.n 8001462 + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 800141c: 4b15 ldr r3, [pc, #84] @ (8001474 ) + 800141e: 681a ldr r2, [r3, #0] + 8001420: 4b13 ldr r3, [pc, #76] @ (8001470 ) + 8001422: 681b ldr r3, [r3, #0] + 8001424: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8001428: fbb1 f3f3 udiv r3, r1, r3 + 800142c: fbb2 f3f3 udiv r3, r2, r3 + 8001430: 4618 mov r0, r3 + 8001432: f000 f940 bl 80016b6 + 8001436: 4603 mov r3, r0 + 8001438: 2b00 cmp r3, #0 + 800143a: d10f bne.n 800145c + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 800143c: 687b ldr r3, [r7, #4] + 800143e: 2b0f cmp r3, #15 + 8001440: d809 bhi.n 8001456 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001442: 2200 movs r2, #0 + 8001444: 6879 ldr r1, [r7, #4] + 8001446: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800144a: f000 f90a bl 8001662 + uwTickPrio = TickPriority; + 800144e: 4a0a ldr r2, [pc, #40] @ (8001478 ) + 8001450: 687b ldr r3, [r7, #4] + 8001452: 6013 str r3, [r2, #0] + 8001454: e007 b.n 8001466 + } + else + { + status = HAL_ERROR; + 8001456: 2301 movs r3, #1 + 8001458: 73fb strb r3, [r7, #15] + 800145a: e004 b.n 8001466 + } + } + else + { + status = HAL_ERROR; + 800145c: 2301 movs r3, #1 + 800145e: 73fb strb r3, [r7, #15] + 8001460: e001 b.n 8001466 + } + } + else + { + status = HAL_ERROR; + 8001462: 2301 movs r3, #1 + 8001464: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8001466: 7bfb ldrb r3, [r7, #15] +} + 8001468: 4618 mov r0, r3 + 800146a: 3710 adds r7, #16 + 800146c: 46bd mov sp, r7 + 800146e: bd80 pop {r7, pc} + 8001470: 2000000c .word 0x2000000c + 8001474: 20000004 .word 0x20000004 + 8001478: 20000008 .word 0x20000008 + +0800147c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 800147c: b480 push {r7} + 800147e: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8001480: 4b05 ldr r3, [pc, #20] @ (8001498 ) + 8001482: 681a ldr r2, [r3, #0] + 8001484: 4b05 ldr r3, [pc, #20] @ (800149c ) + 8001486: 681b ldr r3, [r3, #0] + 8001488: 4413 add r3, r2 + 800148a: 4a03 ldr r2, [pc, #12] @ (8001498 ) + 800148c: 6013 str r3, [r2, #0] +} + 800148e: bf00 nop + 8001490: 46bd mov sp, r7 + 8001492: bc80 pop {r7} + 8001494: 4770 bx lr + 8001496: bf00 nop + 8001498: 20000108 .word 0x20000108 + 800149c: 2000000c .word 0x2000000c + +080014a0 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 80014a0: b480 push {r7} + 80014a2: af00 add r7, sp, #0 + return uwTick; + 80014a4: 4b02 ldr r3, [pc, #8] @ (80014b0 ) + 80014a6: 681b ldr r3, [r3, #0] +} + 80014a8: 4618 mov r0, r3 + 80014aa: 46bd mov sp, r7 + 80014ac: bc80 pop {r7} + 80014ae: 4770 bx lr + 80014b0: 20000108 .word 0x20000108 + +080014b4 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80014b4: b480 push {r7} + 80014b6: b085 sub sp, #20 + 80014b8: af00 add r7, sp, #0 + 80014ba: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80014bc: 687b ldr r3, [r7, #4] + 80014be: f003 0307 and.w r3, r3, #7 + 80014c2: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 80014c4: 4b0c ldr r3, [pc, #48] @ (80014f8 <__NVIC_SetPriorityGrouping+0x44>) + 80014c6: 68db ldr r3, [r3, #12] + 80014c8: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 80014ca: 68ba ldr r2, [r7, #8] + 80014cc: f64f 03ff movw r3, #63743 @ 0xf8ff + 80014d0: 4013 ands r3, r2 + 80014d2: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 80014d4: 68fb ldr r3, [r7, #12] + 80014d6: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 80014d8: 68bb ldr r3, [r7, #8] + 80014da: 4313 orrs r3, r2 + reg_value = (reg_value | + 80014dc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80014e0: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80014e4: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 80014e6: 4a04 ldr r2, [pc, #16] @ (80014f8 <__NVIC_SetPriorityGrouping+0x44>) + 80014e8: 68bb ldr r3, [r7, #8] + 80014ea: 60d3 str r3, [r2, #12] +} + 80014ec: bf00 nop + 80014ee: 3714 adds r7, #20 + 80014f0: 46bd mov sp, r7 + 80014f2: bc80 pop {r7} + 80014f4: 4770 bx lr + 80014f6: bf00 nop + 80014f8: e000ed00 .word 0xe000ed00 + +080014fc <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 80014fc: b480 push {r7} + 80014fe: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001500: 4b04 ldr r3, [pc, #16] @ (8001514 <__NVIC_GetPriorityGrouping+0x18>) + 8001502: 68db ldr r3, [r3, #12] + 8001504: 0a1b lsrs r3, r3, #8 + 8001506: f003 0307 and.w r3, r3, #7 +} + 800150a: 4618 mov r0, r3 + 800150c: 46bd mov sp, r7 + 800150e: bc80 pop {r7} + 8001510: 4770 bx lr + 8001512: bf00 nop + 8001514: e000ed00 .word 0xe000ed00 + +08001518 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001518: b480 push {r7} + 800151a: b083 sub sp, #12 + 800151c: af00 add r7, sp, #0 + 800151e: 4603 mov r3, r0 + 8001520: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8001522: f997 3007 ldrsb.w r3, [r7, #7] + 8001526: 2b00 cmp r3, #0 + 8001528: db0b blt.n 8001542 <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 800152a: 79fb ldrb r3, [r7, #7] + 800152c: f003 021f and.w r2, r3, #31 + 8001530: 4906 ldr r1, [pc, #24] @ (800154c <__NVIC_EnableIRQ+0x34>) + 8001532: f997 3007 ldrsb.w r3, [r7, #7] + 8001536: 095b lsrs r3, r3, #5 + 8001538: 2001 movs r0, #1 + 800153a: fa00 f202 lsl.w r2, r0, r2 + 800153e: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8001542: bf00 nop + 8001544: 370c adds r7, #12 + 8001546: 46bd mov sp, r7 + 8001548: bc80 pop {r7} + 800154a: 4770 bx lr + 800154c: e000e100 .word 0xe000e100 + +08001550 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8001550: b480 push {r7} + 8001552: b083 sub sp, #12 + 8001554: af00 add r7, sp, #0 + 8001556: 4603 mov r3, r0 + 8001558: 6039 str r1, [r7, #0] + 800155a: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 800155c: f997 3007 ldrsb.w r3, [r7, #7] + 8001560: 2b00 cmp r3, #0 + 8001562: db0a blt.n 800157a <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001564: 683b ldr r3, [r7, #0] + 8001566: b2da uxtb r2, r3 + 8001568: 490c ldr r1, [pc, #48] @ (800159c <__NVIC_SetPriority+0x4c>) + 800156a: f997 3007 ldrsb.w r3, [r7, #7] + 800156e: 0112 lsls r2, r2, #4 + 8001570: b2d2 uxtb r2, r2 + 8001572: 440b add r3, r1 + 8001574: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8001578: e00a b.n 8001590 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 800157a: 683b ldr r3, [r7, #0] + 800157c: b2da uxtb r2, r3 + 800157e: 4908 ldr r1, [pc, #32] @ (80015a0 <__NVIC_SetPriority+0x50>) + 8001580: 79fb ldrb r3, [r7, #7] + 8001582: f003 030f and.w r3, r3, #15 + 8001586: 3b04 subs r3, #4 + 8001588: 0112 lsls r2, r2, #4 + 800158a: b2d2 uxtb r2, r2 + 800158c: 440b add r3, r1 + 800158e: 761a strb r2, [r3, #24] +} + 8001590: bf00 nop + 8001592: 370c adds r7, #12 + 8001594: 46bd mov sp, r7 + 8001596: bc80 pop {r7} + 8001598: 4770 bx lr + 800159a: bf00 nop + 800159c: e000e100 .word 0xe000e100 + 80015a0: e000ed00 .word 0xe000ed00 + +080015a4 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80015a4: b480 push {r7} + 80015a6: b089 sub sp, #36 @ 0x24 + 80015a8: af00 add r7, sp, #0 + 80015aa: 60f8 str r0, [r7, #12] + 80015ac: 60b9 str r1, [r7, #8] + 80015ae: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80015b0: 68fb ldr r3, [r7, #12] + 80015b2: f003 0307 and.w r3, r3, #7 + 80015b6: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 80015b8: 69fb ldr r3, [r7, #28] + 80015ba: f1c3 0307 rsb r3, r3, #7 + 80015be: 2b04 cmp r3, #4 + 80015c0: bf28 it cs + 80015c2: 2304 movcs r3, #4 + 80015c4: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 80015c6: 69fb ldr r3, [r7, #28] + 80015c8: 3304 adds r3, #4 + 80015ca: 2b06 cmp r3, #6 + 80015cc: d902 bls.n 80015d4 + 80015ce: 69fb ldr r3, [r7, #28] + 80015d0: 3b03 subs r3, #3 + 80015d2: e000 b.n 80015d6 + 80015d4: 2300 movs r3, #0 + 80015d6: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80015d8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80015dc: 69bb ldr r3, [r7, #24] + 80015de: fa02 f303 lsl.w r3, r2, r3 + 80015e2: 43da mvns r2, r3 + 80015e4: 68bb ldr r3, [r7, #8] + 80015e6: 401a ands r2, r3 + 80015e8: 697b ldr r3, [r7, #20] + 80015ea: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 80015ec: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 80015f0: 697b ldr r3, [r7, #20] + 80015f2: fa01 f303 lsl.w r3, r1, r3 + 80015f6: 43d9 mvns r1, r3 + 80015f8: 687b ldr r3, [r7, #4] + 80015fa: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80015fc: 4313 orrs r3, r2 + ); +} + 80015fe: 4618 mov r0, r3 + 8001600: 3724 adds r7, #36 @ 0x24 + 8001602: 46bd mov sp, r7 + 8001604: bc80 pop {r7} + 8001606: 4770 bx lr + +08001608 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8001608: b580 push {r7, lr} + 800160a: b082 sub sp, #8 + 800160c: af00 add r7, sp, #0 + 800160e: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8001610: 687b ldr r3, [r7, #4] + 8001612: 3b01 subs r3, #1 + 8001614: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8001618: d301 bcc.n 800161e + { + return (1UL); /* Reload value impossible */ + 800161a: 2301 movs r3, #1 + 800161c: e00f b.n 800163e + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 800161e: 4a0a ldr r2, [pc, #40] @ (8001648 ) + 8001620: 687b ldr r3, [r7, #4] + 8001622: 3b01 subs r3, #1 + 8001624: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8001626: 210f movs r1, #15 + 8001628: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 800162c: f7ff ff90 bl 8001550 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8001630: 4b05 ldr r3, [pc, #20] @ (8001648 ) + 8001632: 2200 movs r2, #0 + 8001634: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001636: 4b04 ldr r3, [pc, #16] @ (8001648 ) + 8001638: 2207 movs r2, #7 + 800163a: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 800163c: 2300 movs r3, #0 +} + 800163e: 4618 mov r0, r3 + 8001640: 3708 adds r7, #8 + 8001642: 46bd mov sp, r7 + 8001644: bd80 pop {r7, pc} + 8001646: bf00 nop + 8001648: e000e010 .word 0xe000e010 + +0800164c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 800164c: b580 push {r7, lr} + 800164e: b082 sub sp, #8 + 8001650: af00 add r7, sp, #0 + 8001652: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8001654: 6878 ldr r0, [r7, #4] + 8001656: f7ff ff2d bl 80014b4 <__NVIC_SetPriorityGrouping> +} + 800165a: bf00 nop + 800165c: 3708 adds r7, #8 + 800165e: 46bd mov sp, r7 + 8001660: bd80 pop {r7, pc} + +08001662 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001662: b580 push {r7, lr} + 8001664: b086 sub sp, #24 + 8001666: af00 add r7, sp, #0 + 8001668: 4603 mov r3, r0 + 800166a: 60b9 str r1, [r7, #8] + 800166c: 607a str r2, [r7, #4] + 800166e: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8001670: 2300 movs r3, #0 + 8001672: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001674: f7ff ff42 bl 80014fc <__NVIC_GetPriorityGrouping> + 8001678: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 800167a: 687a ldr r2, [r7, #4] + 800167c: 68b9 ldr r1, [r7, #8] + 800167e: 6978 ldr r0, [r7, #20] + 8001680: f7ff ff90 bl 80015a4 + 8001684: 4602 mov r2, r0 + 8001686: f997 300f ldrsb.w r3, [r7, #15] + 800168a: 4611 mov r1, r2 + 800168c: 4618 mov r0, r3 + 800168e: f7ff ff5f bl 8001550 <__NVIC_SetPriority> +} + 8001692: bf00 nop + 8001694: 3718 adds r7, #24 + 8001696: 46bd mov sp, r7 + 8001698: bd80 pop {r7, pc} + +0800169a : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 800169a: b580 push {r7, lr} + 800169c: b082 sub sp, #8 + 800169e: af00 add r7, sp, #0 + 80016a0: 4603 mov r3, r0 + 80016a2: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 80016a4: f997 3007 ldrsb.w r3, [r7, #7] + 80016a8: 4618 mov r0, r3 + 80016aa: f7ff ff35 bl 8001518 <__NVIC_EnableIRQ> +} + 80016ae: bf00 nop + 80016b0: 3708 adds r7, #8 + 80016b2: 46bd mov sp, r7 + 80016b4: bd80 pop {r7, pc} + +080016b6 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 80016b6: b580 push {r7, lr} + 80016b8: b082 sub sp, #8 + 80016ba: af00 add r7, sp, #0 + 80016bc: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 80016be: 6878 ldr r0, [r7, #4] + 80016c0: f7ff ffa2 bl 8001608 + 80016c4: 4603 mov r3, r0 +} + 80016c6: 4618 mov r0, r3 + 80016c8: 3708 adds r7, #8 + 80016ca: 46bd mov sp, r7 + 80016cc: bd80 pop {r7, pc} + ... + +080016d0 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 80016d0: b480 push {r7} + 80016d2: b087 sub sp, #28 + 80016d4: af00 add r7, sp, #0 + 80016d6: 6078 str r0, [r7, #4] + 80016d8: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 80016da: 2300 movs r3, #0 + 80016dc: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 80016de: 2300 movs r3, #0 + 80016e0: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 80016e2: 2300 movs r3, #0 + 80016e4: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 80016e6: e160 b.n 80019aa + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 80016e8: 683b ldr r3, [r7, #0] + 80016ea: 681a ldr r2, [r3, #0] + 80016ec: 2101 movs r1, #1 + 80016ee: 697b ldr r3, [r7, #20] + 80016f0: fa01 f303 lsl.w r3, r1, r3 + 80016f4: 4013 ands r3, r2 + 80016f6: 60fb str r3, [r7, #12] + + if (iocurrent) + 80016f8: 68fb ldr r3, [r7, #12] + 80016fa: 2b00 cmp r3, #0 + 80016fc: f000 8152 beq.w 80019a4 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8001700: 683b ldr r3, [r7, #0] + 8001702: 685b ldr r3, [r3, #4] + 8001704: f003 0303 and.w r3, r3, #3 + 8001708: 2b01 cmp r3, #1 + 800170a: d005 beq.n 8001718 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 800170c: 683b ldr r3, [r7, #0] + 800170e: 685b ldr r3, [r3, #4] + 8001710: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8001714: 2b02 cmp r3, #2 + 8001716: d130 bne.n 800177a + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001718: 687b ldr r3, [r7, #4] + 800171a: 689b ldr r3, [r3, #8] + 800171c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 800171e: 697b ldr r3, [r7, #20] + 8001720: 005b lsls r3, r3, #1 + 8001722: 2203 movs r2, #3 + 8001724: fa02 f303 lsl.w r3, r2, r3 + 8001728: 43db mvns r3, r3 + 800172a: 693a ldr r2, [r7, #16] + 800172c: 4013 ands r3, r2 + 800172e: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8001730: 683b ldr r3, [r7, #0] + 8001732: 68da ldr r2, [r3, #12] + 8001734: 697b ldr r3, [r7, #20] + 8001736: 005b lsls r3, r3, #1 + 8001738: fa02 f303 lsl.w r3, r2, r3 + 800173c: 693a ldr r2, [r7, #16] + 800173e: 4313 orrs r3, r2 + 8001740: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8001742: 687b ldr r3, [r7, #4] + 8001744: 693a ldr r2, [r7, #16] + 8001746: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8001748: 687b ldr r3, [r7, #4] + 800174a: 685b ldr r3, [r3, #4] + 800174c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 800174e: 2201 movs r2, #1 + 8001750: 697b ldr r3, [r7, #20] + 8001752: fa02 f303 lsl.w r3, r2, r3 + 8001756: 43db mvns r3, r3 + 8001758: 693a ldr r2, [r7, #16] + 800175a: 4013 ands r3, r2 + 800175c: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 800175e: 683b ldr r3, [r7, #0] + 8001760: 685b ldr r3, [r3, #4] + 8001762: 091b lsrs r3, r3, #4 + 8001764: f003 0201 and.w r2, r3, #1 + 8001768: 697b ldr r3, [r7, #20] + 800176a: fa02 f303 lsl.w r3, r2, r3 + 800176e: 693a ldr r2, [r7, #16] + 8001770: 4313 orrs r3, r2 + 8001772: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8001774: 687b ldr r3, [r7, #4] + 8001776: 693a ldr r2, [r7, #16] + 8001778: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 800177a: 683b ldr r3, [r7, #0] + 800177c: 685b ldr r3, [r3, #4] + 800177e: f003 0303 and.w r3, r3, #3 + 8001782: 2b03 cmp r3, #3 + 8001784: d017 beq.n 80017b6 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8001786: 687b ldr r3, [r7, #4] + 8001788: 68db ldr r3, [r3, #12] + 800178a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 800178c: 697b ldr r3, [r7, #20] + 800178e: 005b lsls r3, r3, #1 + 8001790: 2203 movs r2, #3 + 8001792: fa02 f303 lsl.w r3, r2, r3 + 8001796: 43db mvns r3, r3 + 8001798: 693a ldr r2, [r7, #16] + 800179a: 4013 ands r3, r2 + 800179c: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 800179e: 683b ldr r3, [r7, #0] + 80017a0: 689a ldr r2, [r3, #8] + 80017a2: 697b ldr r3, [r7, #20] + 80017a4: 005b lsls r3, r3, #1 + 80017a6: fa02 f303 lsl.w r3, r2, r3 + 80017aa: 693a ldr r2, [r7, #16] + 80017ac: 4313 orrs r3, r2 + 80017ae: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 80017b0: 687b ldr r3, [r7, #4] + 80017b2: 693a ldr r2, [r7, #16] + 80017b4: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 80017b6: 683b ldr r3, [r7, #0] + 80017b8: 685b ldr r3, [r3, #4] + 80017ba: f003 0303 and.w r3, r3, #3 + 80017be: 2b02 cmp r3, #2 + 80017c0: d123 bne.n 800180a + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 80017c2: 697b ldr r3, [r7, #20] + 80017c4: 08da lsrs r2, r3, #3 + 80017c6: 687b ldr r3, [r7, #4] + 80017c8: 3208 adds r2, #8 + 80017ca: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80017ce: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 80017d0: 697b ldr r3, [r7, #20] + 80017d2: f003 0307 and.w r3, r3, #7 + 80017d6: 009b lsls r3, r3, #2 + 80017d8: 220f movs r2, #15 + 80017da: fa02 f303 lsl.w r3, r2, r3 + 80017de: 43db mvns r3, r3 + 80017e0: 693a ldr r2, [r7, #16] + 80017e2: 4013 ands r3, r2 + 80017e4: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 80017e6: 683b ldr r3, [r7, #0] + 80017e8: 691a ldr r2, [r3, #16] + 80017ea: 697b ldr r3, [r7, #20] + 80017ec: f003 0307 and.w r3, r3, #7 + 80017f0: 009b lsls r3, r3, #2 + 80017f2: fa02 f303 lsl.w r3, r2, r3 + 80017f6: 693a ldr r2, [r7, #16] + 80017f8: 4313 orrs r3, r2 + 80017fa: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 80017fc: 697b ldr r3, [r7, #20] + 80017fe: 08da lsrs r2, r3, #3 + 8001800: 687b ldr r3, [r7, #4] + 8001802: 3208 adds r2, #8 + 8001804: 6939 ldr r1, [r7, #16] + 8001806: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 800180a: 687b ldr r3, [r7, #4] + 800180c: 681b ldr r3, [r3, #0] + 800180e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8001810: 697b ldr r3, [r7, #20] + 8001812: 005b lsls r3, r3, #1 + 8001814: 2203 movs r2, #3 + 8001816: fa02 f303 lsl.w r3, r2, r3 + 800181a: 43db mvns r3, r3 + 800181c: 693a ldr r2, [r7, #16] + 800181e: 4013 ands r3, r2 + 8001820: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8001822: 683b ldr r3, [r7, #0] + 8001824: 685b ldr r3, [r3, #4] + 8001826: f003 0203 and.w r2, r3, #3 + 800182a: 697b ldr r3, [r7, #20] + 800182c: 005b lsls r3, r3, #1 + 800182e: fa02 f303 lsl.w r3, r2, r3 + 8001832: 693a ldr r2, [r7, #16] + 8001834: 4313 orrs r3, r2 + 8001836: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8001838: 687b ldr r3, [r7, #4] + 800183a: 693a ldr r2, [r7, #16] + 800183c: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 800183e: 683b ldr r3, [r7, #0] + 8001840: 685b ldr r3, [r3, #4] + 8001842: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001846: 2b00 cmp r3, #0 + 8001848: f000 80ac beq.w 80019a4 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800184c: 4b5e ldr r3, [pc, #376] @ (80019c8 ) + 800184e: 6a1b ldr r3, [r3, #32] + 8001850: 4a5d ldr r2, [pc, #372] @ (80019c8 ) + 8001852: f043 0301 orr.w r3, r3, #1 + 8001856: 6213 str r3, [r2, #32] + 8001858: 4b5b ldr r3, [pc, #364] @ (80019c8 ) + 800185a: 6a1b ldr r3, [r3, #32] + 800185c: f003 0301 and.w r3, r3, #1 + 8001860: 60bb str r3, [r7, #8] + 8001862: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8001864: 4a59 ldr r2, [pc, #356] @ (80019cc ) + 8001866: 697b ldr r3, [r7, #20] + 8001868: 089b lsrs r3, r3, #2 + 800186a: 3302 adds r3, #2 + 800186c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001870: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 8001872: 697b ldr r3, [r7, #20] + 8001874: f003 0303 and.w r3, r3, #3 + 8001878: 009b lsls r3, r3, #2 + 800187a: 220f movs r2, #15 + 800187c: fa02 f303 lsl.w r3, r2, r3 + 8001880: 43db mvns r3, r3 + 8001882: 693a ldr r2, [r7, #16] + 8001884: 4013 ands r3, r2 + 8001886: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 8001888: 687b ldr r3, [r7, #4] + 800188a: 4a51 ldr r2, [pc, #324] @ (80019d0 ) + 800188c: 4293 cmp r3, r2 + 800188e: d025 beq.n 80018dc + 8001890: 687b ldr r3, [r7, #4] + 8001892: 4a50 ldr r2, [pc, #320] @ (80019d4 ) + 8001894: 4293 cmp r3, r2 + 8001896: d01f beq.n 80018d8 + 8001898: 687b ldr r3, [r7, #4] + 800189a: 4a4f ldr r2, [pc, #316] @ (80019d8 ) + 800189c: 4293 cmp r3, r2 + 800189e: d019 beq.n 80018d4 + 80018a0: 687b ldr r3, [r7, #4] + 80018a2: 4a4e ldr r2, [pc, #312] @ (80019dc ) + 80018a4: 4293 cmp r3, r2 + 80018a6: d013 beq.n 80018d0 + 80018a8: 687b ldr r3, [r7, #4] + 80018aa: 4a4d ldr r2, [pc, #308] @ (80019e0 ) + 80018ac: 4293 cmp r3, r2 + 80018ae: d00d beq.n 80018cc + 80018b0: 687b ldr r3, [r7, #4] + 80018b2: 4a4c ldr r2, [pc, #304] @ (80019e4 ) + 80018b4: 4293 cmp r3, r2 + 80018b6: d007 beq.n 80018c8 + 80018b8: 687b ldr r3, [r7, #4] + 80018ba: 4a4b ldr r2, [pc, #300] @ (80019e8 ) + 80018bc: 4293 cmp r3, r2 + 80018be: d101 bne.n 80018c4 + 80018c0: 2306 movs r3, #6 + 80018c2: e00c b.n 80018de + 80018c4: 2307 movs r3, #7 + 80018c6: e00a b.n 80018de + 80018c8: 2305 movs r3, #5 + 80018ca: e008 b.n 80018de + 80018cc: 2304 movs r3, #4 + 80018ce: e006 b.n 80018de + 80018d0: 2303 movs r3, #3 + 80018d2: e004 b.n 80018de + 80018d4: 2302 movs r3, #2 + 80018d6: e002 b.n 80018de + 80018d8: 2301 movs r3, #1 + 80018da: e000 b.n 80018de + 80018dc: 2300 movs r3, #0 + 80018de: 697a ldr r2, [r7, #20] + 80018e0: f002 0203 and.w r2, r2, #3 + 80018e4: 0092 lsls r2, r2, #2 + 80018e6: 4093 lsls r3, r2 + 80018e8: 693a ldr r2, [r7, #16] + 80018ea: 4313 orrs r3, r2 + 80018ec: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 80018ee: 4937 ldr r1, [pc, #220] @ (80019cc ) + 80018f0: 697b ldr r3, [r7, #20] + 80018f2: 089b lsrs r3, r3, #2 + 80018f4: 3302 adds r3, #2 + 80018f6: 693a ldr r2, [r7, #16] + 80018f8: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 80018fc: 4b3b ldr r3, [pc, #236] @ (80019ec ) + 80018fe: 689b ldr r3, [r3, #8] + 8001900: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001902: 68fb ldr r3, [r7, #12] + 8001904: 43db mvns r3, r3 + 8001906: 693a ldr r2, [r7, #16] + 8001908: 4013 ands r3, r2 + 800190a: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 800190c: 683b ldr r3, [r7, #0] + 800190e: 685b ldr r3, [r3, #4] + 8001910: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001914: 2b00 cmp r3, #0 + 8001916: d003 beq.n 8001920 + { + SET_BIT(temp, iocurrent); + 8001918: 693a ldr r2, [r7, #16] + 800191a: 68fb ldr r3, [r7, #12] + 800191c: 4313 orrs r3, r2 + 800191e: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 8001920: 4a32 ldr r2, [pc, #200] @ (80019ec ) + 8001922: 693b ldr r3, [r7, #16] + 8001924: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8001926: 4b31 ldr r3, [pc, #196] @ (80019ec ) + 8001928: 68db ldr r3, [r3, #12] + 800192a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 800192c: 68fb ldr r3, [r7, #12] + 800192e: 43db mvns r3, r3 + 8001930: 693a ldr r2, [r7, #16] + 8001932: 4013 ands r3, r2 + 8001934: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8001936: 683b ldr r3, [r7, #0] + 8001938: 685b ldr r3, [r3, #4] + 800193a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800193e: 2b00 cmp r3, #0 + 8001940: d003 beq.n 800194a + { + SET_BIT(temp, iocurrent); + 8001942: 693a ldr r2, [r7, #16] + 8001944: 68fb ldr r3, [r7, #12] + 8001946: 4313 orrs r3, r2 + 8001948: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 800194a: 4a28 ldr r2, [pc, #160] @ (80019ec ) + 800194c: 693b ldr r3, [r7, #16] + 800194e: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8001950: 4b26 ldr r3, [pc, #152] @ (80019ec ) + 8001952: 685b ldr r3, [r3, #4] + 8001954: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001956: 68fb ldr r3, [r7, #12] + 8001958: 43db mvns r3, r3 + 800195a: 693a ldr r2, [r7, #16] + 800195c: 4013 ands r3, r2 + 800195e: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8001960: 683b ldr r3, [r7, #0] + 8001962: 685b ldr r3, [r3, #4] + 8001964: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001968: 2b00 cmp r3, #0 + 800196a: d003 beq.n 8001974 + { + SET_BIT(temp, iocurrent); + 800196c: 693a ldr r2, [r7, #16] + 800196e: 68fb ldr r3, [r7, #12] + 8001970: 4313 orrs r3, r2 + 8001972: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8001974: 4a1d ldr r2, [pc, #116] @ (80019ec ) + 8001976: 693b ldr r3, [r7, #16] + 8001978: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 800197a: 4b1c ldr r3, [pc, #112] @ (80019ec ) + 800197c: 681b ldr r3, [r3, #0] + 800197e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001980: 68fb ldr r3, [r7, #12] + 8001982: 43db mvns r3, r3 + 8001984: 693a ldr r2, [r7, #16] + 8001986: 4013 ands r3, r2 + 8001988: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 800198a: 683b ldr r3, [r7, #0] + 800198c: 685b ldr r3, [r3, #4] + 800198e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001992: 2b00 cmp r3, #0 + 8001994: d003 beq.n 800199e + { + SET_BIT(temp, iocurrent); + 8001996: 693a ldr r2, [r7, #16] + 8001998: 68fb ldr r3, [r7, #12] + 800199a: 4313 orrs r3, r2 + 800199c: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 800199e: 4a13 ldr r2, [pc, #76] @ (80019ec ) + 80019a0: 693b ldr r3, [r7, #16] + 80019a2: 6013 str r3, [r2, #0] + } + } + + position++; + 80019a4: 697b ldr r3, [r7, #20] + 80019a6: 3301 adds r3, #1 + 80019a8: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 80019aa: 683b ldr r3, [r7, #0] + 80019ac: 681a ldr r2, [r3, #0] + 80019ae: 697b ldr r3, [r7, #20] + 80019b0: fa22 f303 lsr.w r3, r2, r3 + 80019b4: 2b00 cmp r3, #0 + 80019b6: f47f ae97 bne.w 80016e8 + } +} + 80019ba: bf00 nop + 80019bc: bf00 nop + 80019be: 371c adds r7, #28 + 80019c0: 46bd mov sp, r7 + 80019c2: bc80 pop {r7} + 80019c4: 4770 bx lr + 80019c6: bf00 nop + 80019c8: 40023800 .word 0x40023800 + 80019cc: 40010000 .word 0x40010000 + 80019d0: 40020000 .word 0x40020000 + 80019d4: 40020400 .word 0x40020400 + 80019d8: 40020800 .word 0x40020800 + 80019dc: 40020c00 .word 0x40020c00 + 80019e0: 40021000 .word 0x40021000 + 80019e4: 40021400 .word 0x40021400 + 80019e8: 40021800 .word 0x40021800 + 80019ec: 40010400 .word 0x40010400 + +080019f0 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80019f0: b480 push {r7} + 80019f2: b083 sub sp, #12 + 80019f4: af00 add r7, sp, #0 + 80019f6: 6078 str r0, [r7, #4] + 80019f8: 460b mov r3, r1 + 80019fa: 807b strh r3, [r7, #2] + 80019fc: 4613 mov r3, r2 + 80019fe: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8001a00: 787b ldrb r3, [r7, #1] + 8001a02: 2b00 cmp r3, #0 + 8001a04: d003 beq.n 8001a0e + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8001a06: 887a ldrh r2, [r7, #2] + 8001a08: 687b ldr r3, [r7, #4] + 8001a0a: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 8001a0c: e003 b.n 8001a16 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 8001a0e: 887b ldrh r3, [r7, #2] + 8001a10: 041a lsls r2, r3, #16 + 8001a12: 687b ldr r3, [r7, #4] + 8001a14: 619a str r2, [r3, #24] +} + 8001a16: bf00 nop + 8001a18: 370c adds r7, #12 + 8001a1a: 46bd mov sp, r7 + 8001a1c: bc80 pop {r7} + 8001a1e: 4770 bx lr + +08001a20 : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 8001a20: b580 push {r7, lr} + 8001a22: b082 sub sp, #8 + 8001a24: af00 add r7, sp, #0 + 8001a26: 4603 mov r3, r0 + 8001a28: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 8001a2a: 4b08 ldr r3, [pc, #32] @ (8001a4c ) + 8001a2c: 695a ldr r2, [r3, #20] + 8001a2e: 88fb ldrh r3, [r7, #6] + 8001a30: 4013 ands r3, r2 + 8001a32: 2b00 cmp r3, #0 + 8001a34: d006 beq.n 8001a44 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 8001a36: 4a05 ldr r2, [pc, #20] @ (8001a4c ) + 8001a38: 88fb ldrh r3, [r7, #6] + 8001a3a: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 8001a3c: 88fb ldrh r3, [r7, #6] + 8001a3e: 4618 mov r0, r3 + 8001a40: f000 f806 bl 8001a50 + } +} + 8001a44: bf00 nop + 8001a46: 3708 adds r7, #8 + 8001a48: 46bd mov sp, r7 + 8001a4a: bd80 pop {r7, pc} + 8001a4c: 40010400 .word 0x40010400 + +08001a50 : + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 8001a50: b480 push {r7} + 8001a52: b083 sub sp, #12 + 8001a54: af00 add r7, sp, #0 + 8001a56: 4603 mov r3, r0 + 8001a58: 80fb strh r3, [r7, #6] + UNUSED(GPIO_Pin); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + 8001a5a: bf00 nop + 8001a5c: 370c adds r7, #12 + 8001a5e: 46bd mov sp, r7 + 8001a60: bc80 pop {r7} + 8001a62: 4770 bx lr + +08001a64 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8001a64: b580 push {r7, lr} + 8001a66: b088 sub sp, #32 + 8001a68: af00 add r7, sp, #0 + 8001a6a: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 8001a6c: 687b ldr r3, [r7, #4] + 8001a6e: 2b00 cmp r3, #0 + 8001a70: d101 bne.n 8001a76 + { + return HAL_ERROR; + 8001a72: 2301 movs r3, #1 + 8001a74: e31d b.n 80020b2 + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8001a76: 4b94 ldr r3, [pc, #592] @ (8001cc8 ) + 8001a78: 689b ldr r3, [r3, #8] + 8001a7a: f003 030c and.w r3, r3, #12 + 8001a7e: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8001a80: 4b91 ldr r3, [pc, #580] @ (8001cc8 ) + 8001a82: 689b ldr r3, [r3, #8] + 8001a84: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001a88: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8001a8a: 687b ldr r3, [r7, #4] + 8001a8c: 681b ldr r3, [r3, #0] + 8001a8e: f003 0301 and.w r3, r3, #1 + 8001a92: 2b00 cmp r3, #0 + 8001a94: d07b beq.n 8001b8e + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 8001a96: 69bb ldr r3, [r7, #24] + 8001a98: 2b08 cmp r3, #8 + 8001a9a: d006 beq.n 8001aaa + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8001a9c: 69bb ldr r3, [r7, #24] + 8001a9e: 2b0c cmp r3, #12 + 8001aa0: d10f bne.n 8001ac2 + 8001aa2: 697b ldr r3, [r7, #20] + 8001aa4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001aa8: d10b bne.n 8001ac2 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001aaa: 4b87 ldr r3, [pc, #540] @ (8001cc8 ) + 8001aac: 681b ldr r3, [r3, #0] + 8001aae: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001ab2: 2b00 cmp r3, #0 + 8001ab4: d06a beq.n 8001b8c + 8001ab6: 687b ldr r3, [r7, #4] + 8001ab8: 685b ldr r3, [r3, #4] + 8001aba: 2b00 cmp r3, #0 + 8001abc: d166 bne.n 8001b8c + { + return HAL_ERROR; + 8001abe: 2301 movs r3, #1 + 8001ac0: e2f7 b.n 80020b2 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8001ac2: 687b ldr r3, [r7, #4] + 8001ac4: 685b ldr r3, [r3, #4] + 8001ac6: 2b01 cmp r3, #1 + 8001ac8: d106 bne.n 8001ad8 + 8001aca: 4b7f ldr r3, [pc, #508] @ (8001cc8 ) + 8001acc: 681b ldr r3, [r3, #0] + 8001ace: 4a7e ldr r2, [pc, #504] @ (8001cc8 ) + 8001ad0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001ad4: 6013 str r3, [r2, #0] + 8001ad6: e02d b.n 8001b34 + 8001ad8: 687b ldr r3, [r7, #4] + 8001ada: 685b ldr r3, [r3, #4] + 8001adc: 2b00 cmp r3, #0 + 8001ade: d10c bne.n 8001afa + 8001ae0: 4b79 ldr r3, [pc, #484] @ (8001cc8 ) + 8001ae2: 681b ldr r3, [r3, #0] + 8001ae4: 4a78 ldr r2, [pc, #480] @ (8001cc8 ) + 8001ae6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001aea: 6013 str r3, [r2, #0] + 8001aec: 4b76 ldr r3, [pc, #472] @ (8001cc8 ) + 8001aee: 681b ldr r3, [r3, #0] + 8001af0: 4a75 ldr r2, [pc, #468] @ (8001cc8 ) + 8001af2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001af6: 6013 str r3, [r2, #0] + 8001af8: e01c b.n 8001b34 + 8001afa: 687b ldr r3, [r7, #4] + 8001afc: 685b ldr r3, [r3, #4] + 8001afe: 2b05 cmp r3, #5 + 8001b00: d10c bne.n 8001b1c + 8001b02: 4b71 ldr r3, [pc, #452] @ (8001cc8 ) + 8001b04: 681b ldr r3, [r3, #0] + 8001b06: 4a70 ldr r2, [pc, #448] @ (8001cc8 ) + 8001b08: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001b0c: 6013 str r3, [r2, #0] + 8001b0e: 4b6e ldr r3, [pc, #440] @ (8001cc8 ) + 8001b10: 681b ldr r3, [r3, #0] + 8001b12: 4a6d ldr r2, [pc, #436] @ (8001cc8 ) + 8001b14: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001b18: 6013 str r3, [r2, #0] + 8001b1a: e00b b.n 8001b34 + 8001b1c: 4b6a ldr r3, [pc, #424] @ (8001cc8 ) + 8001b1e: 681b ldr r3, [r3, #0] + 8001b20: 4a69 ldr r2, [pc, #420] @ (8001cc8 ) + 8001b22: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001b26: 6013 str r3, [r2, #0] + 8001b28: 4b67 ldr r3, [pc, #412] @ (8001cc8 ) + 8001b2a: 681b ldr r3, [r3, #0] + 8001b2c: 4a66 ldr r2, [pc, #408] @ (8001cc8 ) + 8001b2e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001b32: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8001b34: 687b ldr r3, [r7, #4] + 8001b36: 685b ldr r3, [r3, #4] + 8001b38: 2b00 cmp r3, #0 + 8001b3a: d013 beq.n 8001b64 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001b3c: f7ff fcb0 bl 80014a0 + 8001b40: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001b42: e008 b.n 8001b56 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001b44: f7ff fcac bl 80014a0 + 8001b48: 4602 mov r2, r0 + 8001b4a: 693b ldr r3, [r7, #16] + 8001b4c: 1ad3 subs r3, r2, r3 + 8001b4e: 2b64 cmp r3, #100 @ 0x64 + 8001b50: d901 bls.n 8001b56 + { + return HAL_TIMEOUT; + 8001b52: 2303 movs r3, #3 + 8001b54: e2ad b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001b56: 4b5c ldr r3, [pc, #368] @ (8001cc8 ) + 8001b58: 681b ldr r3, [r3, #0] + 8001b5a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001b5e: 2b00 cmp r3, #0 + 8001b60: d0f0 beq.n 8001b44 + 8001b62: e014 b.n 8001b8e + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001b64: f7ff fc9c bl 80014a0 + 8001b68: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 8001b6a: e008 b.n 8001b7e + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001b6c: f7ff fc98 bl 80014a0 + 8001b70: 4602 mov r2, r0 + 8001b72: 693b ldr r3, [r7, #16] + 8001b74: 1ad3 subs r3, r2, r3 + 8001b76: 2b64 cmp r3, #100 @ 0x64 + 8001b78: d901 bls.n 8001b7e + { + return HAL_TIMEOUT; + 8001b7a: 2303 movs r3, #3 + 8001b7c: e299 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 8001b7e: 4b52 ldr r3, [pc, #328] @ (8001cc8 ) + 8001b80: 681b ldr r3, [r3, #0] + 8001b82: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001b86: 2b00 cmp r3, #0 + 8001b88: d1f0 bne.n 8001b6c + 8001b8a: e000 b.n 8001b8e + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001b8c: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8001b8e: 687b ldr r3, [r7, #4] + 8001b90: 681b ldr r3, [r3, #0] + 8001b92: f003 0302 and.w r3, r3, #2 + 8001b96: 2b00 cmp r3, #0 + 8001b98: d05a beq.n 8001c50 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 8001b9a: 69bb ldr r3, [r7, #24] + 8001b9c: 2b04 cmp r3, #4 + 8001b9e: d005 beq.n 8001bac + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8001ba0: 69bb ldr r3, [r7, #24] + 8001ba2: 2b0c cmp r3, #12 + 8001ba4: d119 bne.n 8001bda + 8001ba6: 697b ldr r3, [r7, #20] + 8001ba8: 2b00 cmp r3, #0 + 8001baa: d116 bne.n 8001bda + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001bac: 4b46 ldr r3, [pc, #280] @ (8001cc8 ) + 8001bae: 681b ldr r3, [r3, #0] + 8001bb0: f003 0302 and.w r3, r3, #2 + 8001bb4: 2b00 cmp r3, #0 + 8001bb6: d005 beq.n 8001bc4 + 8001bb8: 687b ldr r3, [r7, #4] + 8001bba: 68db ldr r3, [r3, #12] + 8001bbc: 2b01 cmp r3, #1 + 8001bbe: d001 beq.n 8001bc4 + { + return HAL_ERROR; + 8001bc0: 2301 movs r3, #1 + 8001bc2: e276 b.n 80020b2 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001bc4: 4b40 ldr r3, [pc, #256] @ (8001cc8 ) + 8001bc6: 685b ldr r3, [r3, #4] + 8001bc8: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001bcc: 687b ldr r3, [r7, #4] + 8001bce: 691b ldr r3, [r3, #16] + 8001bd0: 021b lsls r3, r3, #8 + 8001bd2: 493d ldr r1, [pc, #244] @ (8001cc8 ) + 8001bd4: 4313 orrs r3, r2 + 8001bd6: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001bd8: e03a b.n 8001c50 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8001bda: 687b ldr r3, [r7, #4] + 8001bdc: 68db ldr r3, [r3, #12] + 8001bde: 2b00 cmp r3, #0 + 8001be0: d020 beq.n 8001c24 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8001be2: 4b3a ldr r3, [pc, #232] @ (8001ccc ) + 8001be4: 2201 movs r2, #1 + 8001be6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001be8: f7ff fc5a bl 80014a0 + 8001bec: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001bee: e008 b.n 8001c02 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001bf0: f7ff fc56 bl 80014a0 + 8001bf4: 4602 mov r2, r0 + 8001bf6: 693b ldr r3, [r7, #16] + 8001bf8: 1ad3 subs r3, r2, r3 + 8001bfa: 2b02 cmp r3, #2 + 8001bfc: d901 bls.n 8001c02 + { + return HAL_TIMEOUT; + 8001bfe: 2303 movs r3, #3 + 8001c00: e257 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001c02: 4b31 ldr r3, [pc, #196] @ (8001cc8 ) + 8001c04: 681b ldr r3, [r3, #0] + 8001c06: f003 0302 and.w r3, r3, #2 + 8001c0a: 2b00 cmp r3, #0 + 8001c0c: d0f0 beq.n 8001bf0 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001c0e: 4b2e ldr r3, [pc, #184] @ (8001cc8 ) + 8001c10: 685b ldr r3, [r3, #4] + 8001c12: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001c16: 687b ldr r3, [r7, #4] + 8001c18: 691b ldr r3, [r3, #16] + 8001c1a: 021b lsls r3, r3, #8 + 8001c1c: 492a ldr r1, [pc, #168] @ (8001cc8 ) + 8001c1e: 4313 orrs r3, r2 + 8001c20: 604b str r3, [r1, #4] + 8001c22: e015 b.n 8001c50 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8001c24: 4b29 ldr r3, [pc, #164] @ (8001ccc ) + 8001c26: 2200 movs r2, #0 + 8001c28: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001c2a: f7ff fc39 bl 80014a0 + 8001c2e: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001c30: e008 b.n 8001c44 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001c32: f7ff fc35 bl 80014a0 + 8001c36: 4602 mov r2, r0 + 8001c38: 693b ldr r3, [r7, #16] + 8001c3a: 1ad3 subs r3, r2, r3 + 8001c3c: 2b02 cmp r3, #2 + 8001c3e: d901 bls.n 8001c44 + { + return HAL_TIMEOUT; + 8001c40: 2303 movs r3, #3 + 8001c42: e236 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001c44: 4b20 ldr r3, [pc, #128] @ (8001cc8 ) + 8001c46: 681b ldr r3, [r3, #0] + 8001c48: f003 0302 and.w r3, r3, #2 + 8001c4c: 2b00 cmp r3, #0 + 8001c4e: d1f0 bne.n 8001c32 + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8001c50: 687b ldr r3, [r7, #4] + 8001c52: 681b ldr r3, [r3, #0] + 8001c54: f003 0310 and.w r3, r3, #16 + 8001c58: 2b00 cmp r3, #0 + 8001c5a: f000 80b8 beq.w 8001dce + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 8001c5e: 69bb ldr r3, [r7, #24] + 8001c60: 2b00 cmp r3, #0 + 8001c62: d170 bne.n 8001d46 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8001c64: 4b18 ldr r3, [pc, #96] @ (8001cc8 ) + 8001c66: 681b ldr r3, [r3, #0] + 8001c68: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001c6c: 2b00 cmp r3, #0 + 8001c6e: d005 beq.n 8001c7c + 8001c70: 687b ldr r3, [r7, #4] + 8001c72: 699b ldr r3, [r3, #24] + 8001c74: 2b00 cmp r3, #0 + 8001c76: d101 bne.n 8001c7c + { + return HAL_ERROR; + 8001c78: 2301 movs r3, #1 + 8001c7a: e21a b.n 80020b2 + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 8001c7c: 687b ldr r3, [r7, #4] + 8001c7e: 6a1a ldr r2, [r3, #32] + 8001c80: 4b11 ldr r3, [pc, #68] @ (8001cc8 ) + 8001c82: 685b ldr r3, [r3, #4] + 8001c84: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 8001c88: 429a cmp r2, r3 + 8001c8a: d921 bls.n 8001cd0 + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001c8c: 687b ldr r3, [r7, #4] + 8001c8e: 6a1b ldr r3, [r3, #32] + 8001c90: 4618 mov r0, r3 + 8001c92: f000 fc09 bl 80024a8 + 8001c96: 4603 mov r3, r0 + 8001c98: 2b00 cmp r3, #0 + 8001c9a: d001 beq.n 8001ca0 + { + return HAL_ERROR; + 8001c9c: 2301 movs r3, #1 + 8001c9e: e208 b.n 80020b2 + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001ca0: 4b09 ldr r3, [pc, #36] @ (8001cc8 ) + 8001ca2: 685b ldr r3, [r3, #4] + 8001ca4: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001ca8: 687b ldr r3, [r7, #4] + 8001caa: 6a1b ldr r3, [r3, #32] + 8001cac: 4906 ldr r1, [pc, #24] @ (8001cc8 ) + 8001cae: 4313 orrs r3, r2 + 8001cb0: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001cb2: 4b05 ldr r3, [pc, #20] @ (8001cc8 ) + 8001cb4: 685b ldr r3, [r3, #4] + 8001cb6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001cba: 687b ldr r3, [r7, #4] + 8001cbc: 69db ldr r3, [r3, #28] + 8001cbe: 061b lsls r3, r3, #24 + 8001cc0: 4901 ldr r1, [pc, #4] @ (8001cc8 ) + 8001cc2: 4313 orrs r3, r2 + 8001cc4: 604b str r3, [r1, #4] + 8001cc6: e020 b.n 8001d0a + 8001cc8: 40023800 .word 0x40023800 + 8001ccc: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001cd0: 4b99 ldr r3, [pc, #612] @ (8001f38 ) + 8001cd2: 685b ldr r3, [r3, #4] + 8001cd4: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001cd8: 687b ldr r3, [r7, #4] + 8001cda: 6a1b ldr r3, [r3, #32] + 8001cdc: 4996 ldr r1, [pc, #600] @ (8001f38 ) + 8001cde: 4313 orrs r3, r2 + 8001ce0: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001ce2: 4b95 ldr r3, [pc, #596] @ (8001f38 ) + 8001ce4: 685b ldr r3, [r3, #4] + 8001ce6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001cea: 687b ldr r3, [r7, #4] + 8001cec: 69db ldr r3, [r3, #28] + 8001cee: 061b lsls r3, r3, #24 + 8001cf0: 4991 ldr r1, [pc, #580] @ (8001f38 ) + 8001cf2: 4313 orrs r3, r2 + 8001cf4: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001cf6: 687b ldr r3, [r7, #4] + 8001cf8: 6a1b ldr r3, [r3, #32] + 8001cfa: 4618 mov r0, r3 + 8001cfc: f000 fbd4 bl 80024a8 + 8001d00: 4603 mov r3, r0 + 8001d02: 2b00 cmp r3, #0 + 8001d04: d001 beq.n 8001d0a + { + return HAL_ERROR; + 8001d06: 2301 movs r3, #1 + 8001d08: e1d3 b.n 80020b2 + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001d0a: 687b ldr r3, [r7, #4] + 8001d0c: 6a1b ldr r3, [r3, #32] + 8001d0e: 0b5b lsrs r3, r3, #13 + 8001d10: 3301 adds r3, #1 + 8001d12: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001d16: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 8001d1a: 4a87 ldr r2, [pc, #540] @ (8001f38 ) + 8001d1c: 6892 ldr r2, [r2, #8] + 8001d1e: 0912 lsrs r2, r2, #4 + 8001d20: f002 020f and.w r2, r2, #15 + 8001d24: 4985 ldr r1, [pc, #532] @ (8001f3c ) + 8001d26: 5c8a ldrb r2, [r1, r2] + 8001d28: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001d2a: 4a85 ldr r2, [pc, #532] @ (8001f40 ) + 8001d2c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001d2e: 4b85 ldr r3, [pc, #532] @ (8001f44 ) + 8001d30: 681b ldr r3, [r3, #0] + 8001d32: 4618 mov r0, r3 + 8001d34: f7ff fb68 bl 8001408 + 8001d38: 4603 mov r3, r0 + 8001d3a: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 8001d3c: 7bfb ldrb r3, [r7, #15] + 8001d3e: 2b00 cmp r3, #0 + 8001d40: d045 beq.n 8001dce + { + return status; + 8001d42: 7bfb ldrb r3, [r7, #15] + 8001d44: e1b5 b.n 80020b2 + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8001d46: 687b ldr r3, [r7, #4] + 8001d48: 699b ldr r3, [r3, #24] + 8001d4a: 2b00 cmp r3, #0 + 8001d4c: d029 beq.n 8001da2 + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 8001d4e: 4b7e ldr r3, [pc, #504] @ (8001f48 ) + 8001d50: 2201 movs r2, #1 + 8001d52: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001d54: f7ff fba4 bl 80014a0 + 8001d58: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001d5a: e008 b.n 8001d6e + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001d5c: f7ff fba0 bl 80014a0 + 8001d60: 4602 mov r2, r0 + 8001d62: 693b ldr r3, [r7, #16] + 8001d64: 1ad3 subs r3, r2, r3 + 8001d66: 2b02 cmp r3, #2 + 8001d68: d901 bls.n 8001d6e + { + return HAL_TIMEOUT; + 8001d6a: 2303 movs r3, #3 + 8001d6c: e1a1 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001d6e: 4b72 ldr r3, [pc, #456] @ (8001f38 ) + 8001d70: 681b ldr r3, [r3, #0] + 8001d72: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001d76: 2b00 cmp r3, #0 + 8001d78: d0f0 beq.n 8001d5c + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001d7a: 4b6f ldr r3, [pc, #444] @ (8001f38 ) + 8001d7c: 685b ldr r3, [r3, #4] + 8001d7e: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001d82: 687b ldr r3, [r7, #4] + 8001d84: 6a1b ldr r3, [r3, #32] + 8001d86: 496c ldr r1, [pc, #432] @ (8001f38 ) + 8001d88: 4313 orrs r3, r2 + 8001d8a: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001d8c: 4b6a ldr r3, [pc, #424] @ (8001f38 ) + 8001d8e: 685b ldr r3, [r3, #4] + 8001d90: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001d94: 687b ldr r3, [r7, #4] + 8001d96: 69db ldr r3, [r3, #28] + 8001d98: 061b lsls r3, r3, #24 + 8001d9a: 4967 ldr r1, [pc, #412] @ (8001f38 ) + 8001d9c: 4313 orrs r3, r2 + 8001d9e: 604b str r3, [r1, #4] + 8001da0: e015 b.n 8001dce + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8001da2: 4b69 ldr r3, [pc, #420] @ (8001f48 ) + 8001da4: 2200 movs r2, #0 + 8001da6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001da8: f7ff fb7a bl 80014a0 + 8001dac: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 8001dae: e008 b.n 8001dc2 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001db0: f7ff fb76 bl 80014a0 + 8001db4: 4602 mov r2, r0 + 8001db6: 693b ldr r3, [r7, #16] + 8001db8: 1ad3 subs r3, r2, r3 + 8001dba: 2b02 cmp r3, #2 + 8001dbc: d901 bls.n 8001dc2 + { + return HAL_TIMEOUT; + 8001dbe: 2303 movs r3, #3 + 8001dc0: e177 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 8001dc2: 4b5d ldr r3, [pc, #372] @ (8001f38 ) + 8001dc4: 681b ldr r3, [r3, #0] + 8001dc6: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001dca: 2b00 cmp r3, #0 + 8001dcc: d1f0 bne.n 8001db0 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8001dce: 687b ldr r3, [r7, #4] + 8001dd0: 681b ldr r3, [r3, #0] + 8001dd2: f003 0308 and.w r3, r3, #8 + 8001dd6: 2b00 cmp r3, #0 + 8001dd8: d030 beq.n 8001e3c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8001dda: 687b ldr r3, [r7, #4] + 8001ddc: 695b ldr r3, [r3, #20] + 8001dde: 2b00 cmp r3, #0 + 8001de0: d016 beq.n 8001e10 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8001de2: 4b5a ldr r3, [pc, #360] @ (8001f4c ) + 8001de4: 2201 movs r2, #1 + 8001de6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001de8: f7ff fb5a bl 80014a0 + 8001dec: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8001dee: e008 b.n 8001e02 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001df0: f7ff fb56 bl 80014a0 + 8001df4: 4602 mov r2, r0 + 8001df6: 693b ldr r3, [r7, #16] + 8001df8: 1ad3 subs r3, r2, r3 + 8001dfa: 2b02 cmp r3, #2 + 8001dfc: d901 bls.n 8001e02 + { + return HAL_TIMEOUT; + 8001dfe: 2303 movs r3, #3 + 8001e00: e157 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8001e02: 4b4d ldr r3, [pc, #308] @ (8001f38 ) + 8001e04: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001e06: f003 0302 and.w r3, r3, #2 + 8001e0a: 2b00 cmp r3, #0 + 8001e0c: d0f0 beq.n 8001df0 + 8001e0e: e015 b.n 8001e3c + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001e10: 4b4e ldr r3, [pc, #312] @ (8001f4c ) + 8001e12: 2200 movs r2, #0 + 8001e14: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001e16: f7ff fb43 bl 80014a0 + 8001e1a: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001e1c: e008 b.n 8001e30 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001e1e: f7ff fb3f bl 80014a0 + 8001e22: 4602 mov r2, r0 + 8001e24: 693b ldr r3, [r7, #16] + 8001e26: 1ad3 subs r3, r2, r3 + 8001e28: 2b02 cmp r3, #2 + 8001e2a: d901 bls.n 8001e30 + { + return HAL_TIMEOUT; + 8001e2c: 2303 movs r3, #3 + 8001e2e: e140 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001e30: 4b41 ldr r3, [pc, #260] @ (8001f38 ) + 8001e32: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001e34: f003 0302 and.w r3, r3, #2 + 8001e38: 2b00 cmp r3, #0 + 8001e3a: d1f0 bne.n 8001e1e + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8001e3c: 687b ldr r3, [r7, #4] + 8001e3e: 681b ldr r3, [r3, #0] + 8001e40: f003 0304 and.w r3, r3, #4 + 8001e44: 2b00 cmp r3, #0 + 8001e46: f000 80b5 beq.w 8001fb4 + { + FlagStatus pwrclkchanged = RESET; + 8001e4a: 2300 movs r3, #0 + 8001e4c: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8001e4e: 4b3a ldr r3, [pc, #232] @ (8001f38 ) + 8001e50: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e52: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001e56: 2b00 cmp r3, #0 + 8001e58: d10d bne.n 8001e76 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001e5a: 4b37 ldr r3, [pc, #220] @ (8001f38 ) + 8001e5c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e5e: 4a36 ldr r2, [pc, #216] @ (8001f38 ) + 8001e60: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001e64: 6253 str r3, [r2, #36] @ 0x24 + 8001e66: 4b34 ldr r3, [pc, #208] @ (8001f38 ) + 8001e68: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e6a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001e6e: 60bb str r3, [r7, #8] + 8001e70: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8001e72: 2301 movs r3, #1 + 8001e74: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001e76: 4b36 ldr r3, [pc, #216] @ (8001f50 ) + 8001e78: 681b ldr r3, [r3, #0] + 8001e7a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001e7e: 2b00 cmp r3, #0 + 8001e80: d118 bne.n 8001eb4 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8001e82: 4b33 ldr r3, [pc, #204] @ (8001f50 ) + 8001e84: 681b ldr r3, [r3, #0] + 8001e86: 4a32 ldr r2, [pc, #200] @ (8001f50 ) + 8001e88: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001e8c: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8001e8e: f7ff fb07 bl 80014a0 + 8001e92: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001e94: e008 b.n 8001ea8 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8001e96: f7ff fb03 bl 80014a0 + 8001e9a: 4602 mov r2, r0 + 8001e9c: 693b ldr r3, [r7, #16] + 8001e9e: 1ad3 subs r3, r2, r3 + 8001ea0: 2b64 cmp r3, #100 @ 0x64 + 8001ea2: d901 bls.n 8001ea8 + { + return HAL_TIMEOUT; + 8001ea4: 2303 movs r3, #3 + 8001ea6: e104 b.n 80020b2 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001ea8: 4b29 ldr r3, [pc, #164] @ (8001f50 ) + 8001eaa: 681b ldr r3, [r3, #0] + 8001eac: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001eb0: 2b00 cmp r3, #0 + 8001eb2: d0f0 beq.n 8001e96 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8001eb4: 687b ldr r3, [r7, #4] + 8001eb6: 689b ldr r3, [r3, #8] + 8001eb8: 2b01 cmp r3, #1 + 8001eba: d106 bne.n 8001eca + 8001ebc: 4b1e ldr r3, [pc, #120] @ (8001f38 ) + 8001ebe: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001ec0: 4a1d ldr r2, [pc, #116] @ (8001f38 ) + 8001ec2: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001ec6: 6353 str r3, [r2, #52] @ 0x34 + 8001ec8: e02d b.n 8001f26 + 8001eca: 687b ldr r3, [r7, #4] + 8001ecc: 689b ldr r3, [r3, #8] + 8001ece: 2b00 cmp r3, #0 + 8001ed0: d10c bne.n 8001eec + 8001ed2: 4b19 ldr r3, [pc, #100] @ (8001f38 ) + 8001ed4: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001ed6: 4a18 ldr r2, [pc, #96] @ (8001f38 ) + 8001ed8: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001edc: 6353 str r3, [r2, #52] @ 0x34 + 8001ede: 4b16 ldr r3, [pc, #88] @ (8001f38 ) + 8001ee0: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001ee2: 4a15 ldr r2, [pc, #84] @ (8001f38 ) + 8001ee4: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001ee8: 6353 str r3, [r2, #52] @ 0x34 + 8001eea: e01c b.n 8001f26 + 8001eec: 687b ldr r3, [r7, #4] + 8001eee: 689b ldr r3, [r3, #8] + 8001ef0: 2b05 cmp r3, #5 + 8001ef2: d10c bne.n 8001f0e + 8001ef4: 4b10 ldr r3, [pc, #64] @ (8001f38 ) + 8001ef6: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001ef8: 4a0f ldr r2, [pc, #60] @ (8001f38 ) + 8001efa: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8001efe: 6353 str r3, [r2, #52] @ 0x34 + 8001f00: 4b0d ldr r3, [pc, #52] @ (8001f38 ) + 8001f02: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001f04: 4a0c ldr r2, [pc, #48] @ (8001f38 ) + 8001f06: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001f0a: 6353 str r3, [r2, #52] @ 0x34 + 8001f0c: e00b b.n 8001f26 + 8001f0e: 4b0a ldr r3, [pc, #40] @ (8001f38 ) + 8001f10: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001f12: 4a09 ldr r2, [pc, #36] @ (8001f38 ) + 8001f14: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001f18: 6353 str r3, [r2, #52] @ 0x34 + 8001f1a: 4b07 ldr r3, [pc, #28] @ (8001f38 ) + 8001f1c: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001f1e: 4a06 ldr r2, [pc, #24] @ (8001f38 ) + 8001f20: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001f24: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8001f26: 687b ldr r3, [r7, #4] + 8001f28: 689b ldr r3, [r3, #8] + 8001f2a: 2b00 cmp r3, #0 + 8001f2c: d024 beq.n 8001f78 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001f2e: f7ff fab7 bl 80014a0 + 8001f32: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001f34: e019 b.n 8001f6a + 8001f36: bf00 nop + 8001f38: 40023800 .word 0x40023800 + 8001f3c: 08003814 .word 0x08003814 + 8001f40: 20000004 .word 0x20000004 + 8001f44: 20000008 .word 0x20000008 + 8001f48: 42470020 .word 0x42470020 + 8001f4c: 42470680 .word 0x42470680 + 8001f50: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001f54: f7ff faa4 bl 80014a0 + 8001f58: 4602 mov r2, r0 + 8001f5a: 693b ldr r3, [r7, #16] + 8001f5c: 1ad3 subs r3, r2, r3 + 8001f5e: f241 3288 movw r2, #5000 @ 0x1388 + 8001f62: 4293 cmp r3, r2 + 8001f64: d901 bls.n 8001f6a + { + return HAL_TIMEOUT; + 8001f66: 2303 movs r3, #3 + 8001f68: e0a3 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001f6a: 4b54 ldr r3, [pc, #336] @ (80020bc ) + 8001f6c: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001f6e: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001f72: 2b00 cmp r3, #0 + 8001f74: d0ee beq.n 8001f54 + 8001f76: e014 b.n 8001fa2 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001f78: f7ff fa92 bl 80014a0 + 8001f7c: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8001f7e: e00a b.n 8001f96 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001f80: f7ff fa8e bl 80014a0 + 8001f84: 4602 mov r2, r0 + 8001f86: 693b ldr r3, [r7, #16] + 8001f88: 1ad3 subs r3, r2, r3 + 8001f8a: f241 3288 movw r2, #5000 @ 0x1388 + 8001f8e: 4293 cmp r3, r2 + 8001f90: d901 bls.n 8001f96 + { + return HAL_TIMEOUT; + 8001f92: 2303 movs r3, #3 + 8001f94: e08d b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8001f96: 4b49 ldr r3, [pc, #292] @ (80020bc ) + 8001f98: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001f9a: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001f9e: 2b00 cmp r3, #0 + 8001fa0: d1ee bne.n 8001f80 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 8001fa2: 7ffb ldrb r3, [r7, #31] + 8001fa4: 2b01 cmp r3, #1 + 8001fa6: d105 bne.n 8001fb4 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8001fa8: 4b44 ldr r3, [pc, #272] @ (80020bc ) + 8001faa: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001fac: 4a43 ldr r2, [pc, #268] @ (80020bc ) + 8001fae: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001fb2: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8001fb4: 687b ldr r3, [r7, #4] + 8001fb6: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001fb8: 2b00 cmp r3, #0 + 8001fba: d079 beq.n 80020b0 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001fbc: 69bb ldr r3, [r7, #24] + 8001fbe: 2b0c cmp r3, #12 + 8001fc0: d056 beq.n 8002070 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8001fc2: 687b ldr r3, [r7, #4] + 8001fc4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001fc6: 2b02 cmp r3, #2 + 8001fc8: d13b bne.n 8002042 + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001fca: 4b3d ldr r3, [pc, #244] @ (80020c0 ) + 8001fcc: 2200 movs r2, #0 + 8001fce: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001fd0: f7ff fa66 bl 80014a0 + 8001fd4: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001fd6: e008 b.n 8001fea + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001fd8: f7ff fa62 bl 80014a0 + 8001fdc: 4602 mov r2, r0 + 8001fde: 693b ldr r3, [r7, #16] + 8001fe0: 1ad3 subs r3, r2, r3 + 8001fe2: 2b02 cmp r3, #2 + 8001fe4: d901 bls.n 8001fea + { + return HAL_TIMEOUT; + 8001fe6: 2303 movs r3, #3 + 8001fe8: e063 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001fea: 4b34 ldr r3, [pc, #208] @ (80020bc ) + 8001fec: 681b ldr r3, [r3, #0] + 8001fee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001ff2: 2b00 cmp r3, #0 + 8001ff4: d1f0 bne.n 8001fd8 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8001ff6: 4b31 ldr r3, [pc, #196] @ (80020bc ) + 8001ff8: 689b ldr r3, [r3, #8] + 8001ffa: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 8001ffe: 687b ldr r3, [r7, #4] + 8002000: 6a99 ldr r1, [r3, #40] @ 0x28 + 8002002: 687b ldr r3, [r7, #4] + 8002004: 6adb ldr r3, [r3, #44] @ 0x2c + 8002006: 4319 orrs r1, r3 + 8002008: 687b ldr r3, [r7, #4] + 800200a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800200c: 430b orrs r3, r1 + 800200e: 492b ldr r1, [pc, #172] @ (80020bc ) + 8002010: 4313 orrs r3, r2 + 8002012: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8002014: 4b2a ldr r3, [pc, #168] @ (80020c0 ) + 8002016: 2201 movs r2, #1 + 8002018: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800201a: f7ff fa41 bl 80014a0 + 800201e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8002020: e008 b.n 8002034 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8002022: f7ff fa3d bl 80014a0 + 8002026: 4602 mov r2, r0 + 8002028: 693b ldr r3, [r7, #16] + 800202a: 1ad3 subs r3, r2, r3 + 800202c: 2b02 cmp r3, #2 + 800202e: d901 bls.n 8002034 + { + return HAL_TIMEOUT; + 8002030: 2303 movs r3, #3 + 8002032: e03e b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8002034: 4b21 ldr r3, [pc, #132] @ (80020bc ) + 8002036: 681b ldr r3, [r3, #0] + 8002038: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800203c: 2b00 cmp r3, #0 + 800203e: d0f0 beq.n 8002022 + 8002040: e036 b.n 80020b0 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8002042: 4b1f ldr r3, [pc, #124] @ (80020c0 ) + 8002044: 2200 movs r2, #0 + 8002046: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8002048: f7ff fa2a bl 80014a0 + 800204c: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800204e: e008 b.n 8002062 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8002050: f7ff fa26 bl 80014a0 + 8002054: 4602 mov r2, r0 + 8002056: 693b ldr r3, [r7, #16] + 8002058: 1ad3 subs r3, r2, r3 + 800205a: 2b02 cmp r3, #2 + 800205c: d901 bls.n 8002062 + { + return HAL_TIMEOUT; + 800205e: 2303 movs r3, #3 + 8002060: e027 b.n 80020b2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8002062: 4b16 ldr r3, [pc, #88] @ (80020bc ) + 8002064: 681b ldr r3, [r3, #0] + 8002066: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800206a: 2b00 cmp r3, #0 + 800206c: d1f0 bne.n 8002050 + 800206e: e01f b.n 80020b0 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8002070: 687b ldr r3, [r7, #4] + 8002072: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002074: 2b01 cmp r3, #1 + 8002076: d101 bne.n 800207c + { + return HAL_ERROR; + 8002078: 2301 movs r3, #1 + 800207a: e01a b.n 80020b2 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 800207c: 4b0f ldr r3, [pc, #60] @ (80020bc ) + 800207e: 689b ldr r3, [r3, #8] + 8002080: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8002082: 697b ldr r3, [r7, #20] + 8002084: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 8002088: 687b ldr r3, [r7, #4] + 800208a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800208c: 429a cmp r2, r3 + 800208e: d10d bne.n 80020ac + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8002090: 697b ldr r3, [r7, #20] + 8002092: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 8002096: 687b ldr r3, [r7, #4] + 8002098: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 800209a: 429a cmp r2, r3 + 800209c: d106 bne.n 80020ac + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 800209e: 697b ldr r3, [r7, #20] + 80020a0: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 80020a4: 687b ldr r3, [r7, #4] + 80020a6: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80020a8: 429a cmp r2, r3 + 80020aa: d001 beq.n 80020b0 + { + return HAL_ERROR; + 80020ac: 2301 movs r3, #1 + 80020ae: e000 b.n 80020b2 + } + } + } + } + + return HAL_OK; + 80020b0: 2300 movs r3, #0 +} + 80020b2: 4618 mov r0, r3 + 80020b4: 3720 adds r7, #32 + 80020b6: 46bd mov sp, r7 + 80020b8: bd80 pop {r7, pc} + 80020ba: bf00 nop + 80020bc: 40023800 .word 0x40023800 + 80020c0: 42470060 .word 0x42470060 + +080020c4 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80020c4: b580 push {r7, lr} + 80020c6: b084 sub sp, #16 + 80020c8: af00 add r7, sp, #0 + 80020ca: 6078 str r0, [r7, #4] + 80020cc: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 80020ce: 687b ldr r3, [r7, #4] + 80020d0: 2b00 cmp r3, #0 + 80020d2: d101 bne.n 80020d8 + { + return HAL_ERROR; + 80020d4: 2301 movs r3, #1 + 80020d6: e11a b.n 800230e + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 80020d8: 4b8f ldr r3, [pc, #572] @ (8002318 ) + 80020da: 681b ldr r3, [r3, #0] + 80020dc: f003 0301 and.w r3, r3, #1 + 80020e0: 683a ldr r2, [r7, #0] + 80020e2: 429a cmp r2, r3 + 80020e4: d919 bls.n 800211a + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80020e6: 683b ldr r3, [r7, #0] + 80020e8: 2b01 cmp r3, #1 + 80020ea: d105 bne.n 80020f8 + 80020ec: 4b8a ldr r3, [pc, #552] @ (8002318 ) + 80020ee: 681b ldr r3, [r3, #0] + 80020f0: 4a89 ldr r2, [pc, #548] @ (8002318 ) + 80020f2: f043 0304 orr.w r3, r3, #4 + 80020f6: 6013 str r3, [r2, #0] + 80020f8: 4b87 ldr r3, [pc, #540] @ (8002318 ) + 80020fa: 681b ldr r3, [r3, #0] + 80020fc: f023 0201 bic.w r2, r3, #1 + 8002100: 4985 ldr r1, [pc, #532] @ (8002318 ) + 8002102: 683b ldr r3, [r7, #0] + 8002104: 4313 orrs r3, r2 + 8002106: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8002108: 4b83 ldr r3, [pc, #524] @ (8002318 ) + 800210a: 681b ldr r3, [r3, #0] + 800210c: f003 0301 and.w r3, r3, #1 + 8002110: 683a ldr r2, [r7, #0] + 8002112: 429a cmp r2, r3 + 8002114: d001 beq.n 800211a + { + return HAL_ERROR; + 8002116: 2301 movs r3, #1 + 8002118: e0f9 b.n 800230e + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800211a: 687b ldr r3, [r7, #4] + 800211c: 681b ldr r3, [r3, #0] + 800211e: f003 0302 and.w r3, r3, #2 + 8002122: 2b00 cmp r3, #0 + 8002124: d008 beq.n 8002138 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8002126: 4b7d ldr r3, [pc, #500] @ (800231c ) + 8002128: 689b ldr r3, [r3, #8] + 800212a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800212e: 687b ldr r3, [r7, #4] + 8002130: 689b ldr r3, [r3, #8] + 8002132: 497a ldr r1, [pc, #488] @ (800231c ) + 8002134: 4313 orrs r3, r2 + 8002136: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8002138: 687b ldr r3, [r7, #4] + 800213a: 681b ldr r3, [r3, #0] + 800213c: f003 0301 and.w r3, r3, #1 + 8002140: 2b00 cmp r3, #0 + 8002142: f000 808e beq.w 8002262 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8002146: 687b ldr r3, [r7, #4] + 8002148: 685b ldr r3, [r3, #4] + 800214a: 2b02 cmp r3, #2 + 800214c: d107 bne.n 800215e + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800214e: 4b73 ldr r3, [pc, #460] @ (800231c ) + 8002150: 681b ldr r3, [r3, #0] + 8002152: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8002156: 2b00 cmp r3, #0 + 8002158: d121 bne.n 800219e + { + return HAL_ERROR; + 800215a: 2301 movs r3, #1 + 800215c: e0d7 b.n 800230e + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800215e: 687b ldr r3, [r7, #4] + 8002160: 685b ldr r3, [r3, #4] + 8002162: 2b03 cmp r3, #3 + 8002164: d107 bne.n 8002176 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8002166: 4b6d ldr r3, [pc, #436] @ (800231c ) + 8002168: 681b ldr r3, [r3, #0] + 800216a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800216e: 2b00 cmp r3, #0 + 8002170: d115 bne.n 800219e + { + return HAL_ERROR; + 8002172: 2301 movs r3, #1 + 8002174: e0cb b.n 800230e + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8002176: 687b ldr r3, [r7, #4] + 8002178: 685b ldr r3, [r3, #4] + 800217a: 2b01 cmp r3, #1 + 800217c: d107 bne.n 800218e + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800217e: 4b67 ldr r3, [pc, #412] @ (800231c ) + 8002180: 681b ldr r3, [r3, #0] + 8002182: f003 0302 and.w r3, r3, #2 + 8002186: 2b00 cmp r3, #0 + 8002188: d109 bne.n 800219e + { + return HAL_ERROR; + 800218a: 2301 movs r3, #1 + 800218c: e0bf b.n 800230e + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800218e: 4b63 ldr r3, [pc, #396] @ (800231c ) + 8002190: 681b ldr r3, [r3, #0] + 8002192: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002196: 2b00 cmp r3, #0 + 8002198: d101 bne.n 800219e + { + return HAL_ERROR; + 800219a: 2301 movs r3, #1 + 800219c: e0b7 b.n 800230e + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 800219e: 4b5f ldr r3, [pc, #380] @ (800231c ) + 80021a0: 689b ldr r3, [r3, #8] + 80021a2: f023 0203 bic.w r2, r3, #3 + 80021a6: 687b ldr r3, [r7, #4] + 80021a8: 685b ldr r3, [r3, #4] + 80021aa: 495c ldr r1, [pc, #368] @ (800231c ) + 80021ac: 4313 orrs r3, r2 + 80021ae: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80021b0: f7ff f976 bl 80014a0 + 80021b4: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80021b6: 687b ldr r3, [r7, #4] + 80021b8: 685b ldr r3, [r3, #4] + 80021ba: 2b02 cmp r3, #2 + 80021bc: d112 bne.n 80021e4 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 80021be: e00a b.n 80021d6 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80021c0: f7ff f96e bl 80014a0 + 80021c4: 4602 mov r2, r0 + 80021c6: 68fb ldr r3, [r7, #12] + 80021c8: 1ad3 subs r3, r2, r3 + 80021ca: f241 3288 movw r2, #5000 @ 0x1388 + 80021ce: 4293 cmp r3, r2 + 80021d0: d901 bls.n 80021d6 + { + return HAL_TIMEOUT; + 80021d2: 2303 movs r3, #3 + 80021d4: e09b b.n 800230e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 80021d6: 4b51 ldr r3, [pc, #324] @ (800231c ) + 80021d8: 689b ldr r3, [r3, #8] + 80021da: f003 030c and.w r3, r3, #12 + 80021de: 2b08 cmp r3, #8 + 80021e0: d1ee bne.n 80021c0 + 80021e2: e03e b.n 8002262 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80021e4: 687b ldr r3, [r7, #4] + 80021e6: 685b ldr r3, [r3, #4] + 80021e8: 2b03 cmp r3, #3 + 80021ea: d112 bne.n 8002212 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80021ec: e00a b.n 8002204 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80021ee: f7ff f957 bl 80014a0 + 80021f2: 4602 mov r2, r0 + 80021f4: 68fb ldr r3, [r7, #12] + 80021f6: 1ad3 subs r3, r2, r3 + 80021f8: f241 3288 movw r2, #5000 @ 0x1388 + 80021fc: 4293 cmp r3, r2 + 80021fe: d901 bls.n 8002204 + { + return HAL_TIMEOUT; + 8002200: 2303 movs r3, #3 + 8002202: e084 b.n 800230e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8002204: 4b45 ldr r3, [pc, #276] @ (800231c ) + 8002206: 689b ldr r3, [r3, #8] + 8002208: f003 030c and.w r3, r3, #12 + 800220c: 2b0c cmp r3, #12 + 800220e: d1ee bne.n 80021ee + 8002210: e027 b.n 8002262 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8002212: 687b ldr r3, [r7, #4] + 8002214: 685b ldr r3, [r3, #4] + 8002216: 2b01 cmp r3, #1 + 8002218: d11d bne.n 8002256 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 800221a: e00a b.n 8002232 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 800221c: f7ff f940 bl 80014a0 + 8002220: 4602 mov r2, r0 + 8002222: 68fb ldr r3, [r7, #12] + 8002224: 1ad3 subs r3, r2, r3 + 8002226: f241 3288 movw r2, #5000 @ 0x1388 + 800222a: 4293 cmp r3, r2 + 800222c: d901 bls.n 8002232 + { + return HAL_TIMEOUT; + 800222e: 2303 movs r3, #3 + 8002230: e06d b.n 800230e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8002232: 4b3a ldr r3, [pc, #232] @ (800231c ) + 8002234: 689b ldr r3, [r3, #8] + 8002236: f003 030c and.w r3, r3, #12 + 800223a: 2b04 cmp r3, #4 + 800223c: d1ee bne.n 800221c + 800223e: e010 b.n 8002262 + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002240: f7ff f92e bl 80014a0 + 8002244: 4602 mov r2, r0 + 8002246: 68fb ldr r3, [r7, #12] + 8002248: 1ad3 subs r3, r2, r3 + 800224a: f241 3288 movw r2, #5000 @ 0x1388 + 800224e: 4293 cmp r3, r2 + 8002250: d901 bls.n 8002256 + { + return HAL_TIMEOUT; + 8002252: 2303 movs r3, #3 + 8002254: e05b b.n 800230e + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 8002256: 4b31 ldr r3, [pc, #196] @ (800231c ) + 8002258: 689b ldr r3, [r3, #8] + 800225a: f003 030c and.w r3, r3, #12 + 800225e: 2b00 cmp r3, #0 + 8002260: d1ee bne.n 8002240 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8002262: 4b2d ldr r3, [pc, #180] @ (8002318 ) + 8002264: 681b ldr r3, [r3, #0] + 8002266: f003 0301 and.w r3, r3, #1 + 800226a: 683a ldr r2, [r7, #0] + 800226c: 429a cmp r2, r3 + 800226e: d219 bcs.n 80022a4 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8002270: 683b ldr r3, [r7, #0] + 8002272: 2b01 cmp r3, #1 + 8002274: d105 bne.n 8002282 + 8002276: 4b28 ldr r3, [pc, #160] @ (8002318 ) + 8002278: 681b ldr r3, [r3, #0] + 800227a: 4a27 ldr r2, [pc, #156] @ (8002318 ) + 800227c: f043 0304 orr.w r3, r3, #4 + 8002280: 6013 str r3, [r2, #0] + 8002282: 4b25 ldr r3, [pc, #148] @ (8002318 ) + 8002284: 681b ldr r3, [r3, #0] + 8002286: f023 0201 bic.w r2, r3, #1 + 800228a: 4923 ldr r1, [pc, #140] @ (8002318 ) + 800228c: 683b ldr r3, [r7, #0] + 800228e: 4313 orrs r3, r2 + 8002290: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8002292: 4b21 ldr r3, [pc, #132] @ (8002318 ) + 8002294: 681b ldr r3, [r3, #0] + 8002296: f003 0301 and.w r3, r3, #1 + 800229a: 683a ldr r2, [r7, #0] + 800229c: 429a cmp r2, r3 + 800229e: d001 beq.n 80022a4 + { + return HAL_ERROR; + 80022a0: 2301 movs r3, #1 + 80022a2: e034 b.n 800230e + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 80022a4: 687b ldr r3, [r7, #4] + 80022a6: 681b ldr r3, [r3, #0] + 80022a8: f003 0304 and.w r3, r3, #4 + 80022ac: 2b00 cmp r3, #0 + 80022ae: d008 beq.n 80022c2 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 80022b0: 4b1a ldr r3, [pc, #104] @ (800231c ) + 80022b2: 689b ldr r3, [r3, #8] + 80022b4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 80022b8: 687b ldr r3, [r7, #4] + 80022ba: 68db ldr r3, [r3, #12] + 80022bc: 4917 ldr r1, [pc, #92] @ (800231c ) + 80022be: 4313 orrs r3, r2 + 80022c0: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80022c2: 687b ldr r3, [r7, #4] + 80022c4: 681b ldr r3, [r3, #0] + 80022c6: f003 0308 and.w r3, r3, #8 + 80022ca: 2b00 cmp r3, #0 + 80022cc: d009 beq.n 80022e2 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 80022ce: 4b13 ldr r3, [pc, #76] @ (800231c ) + 80022d0: 689b ldr r3, [r3, #8] + 80022d2: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 80022d6: 687b ldr r3, [r7, #4] + 80022d8: 691b ldr r3, [r3, #16] + 80022da: 00db lsls r3, r3, #3 + 80022dc: 490f ldr r1, [pc, #60] @ (800231c ) + 80022de: 4313 orrs r3, r2 + 80022e0: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 80022e2: f000 f823 bl 800232c + 80022e6: 4602 mov r2, r0 + 80022e8: 4b0c ldr r3, [pc, #48] @ (800231c ) + 80022ea: 689b ldr r3, [r3, #8] + 80022ec: 091b lsrs r3, r3, #4 + 80022ee: f003 030f and.w r3, r3, #15 + 80022f2: 490b ldr r1, [pc, #44] @ (8002320 ) + 80022f4: 5ccb ldrb r3, [r1, r3] + 80022f6: fa22 f303 lsr.w r3, r2, r3 + 80022fa: 4a0a ldr r2, [pc, #40] @ (8002324 ) + 80022fc: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 80022fe: 4b0a ldr r3, [pc, #40] @ (8002328 ) + 8002300: 681b ldr r3, [r3, #0] + 8002302: 4618 mov r0, r3 + 8002304: f7ff f880 bl 8001408 + 8002308: 4603 mov r3, r0 + 800230a: 72fb strb r3, [r7, #11] + + return status; + 800230c: 7afb ldrb r3, [r7, #11] +} + 800230e: 4618 mov r0, r3 + 8002310: 3710 adds r7, #16 + 8002312: 46bd mov sp, r7 + 8002314: bd80 pop {r7, pc} + 8002316: bf00 nop + 8002318: 40023c00 .word 0x40023c00 + 800231c: 40023800 .word 0x40023800 + 8002320: 08003814 .word 0x08003814 + 8002324: 20000004 .word 0x20000004 + 8002328: 20000008 .word 0x20000008 + +0800232c : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 800232c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8002330: b08e sub sp, #56 @ 0x38 + 8002332: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 8002334: 4b58 ldr r3, [pc, #352] @ (8002498 ) + 8002336: 689b ldr r3, [r3, #8] + 8002338: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 800233a: 6afb ldr r3, [r7, #44] @ 0x2c + 800233c: f003 030c and.w r3, r3, #12 + 8002340: 2b0c cmp r3, #12 + 8002342: d00d beq.n 8002360 + 8002344: 2b0c cmp r3, #12 + 8002346: f200 8092 bhi.w 800246e + 800234a: 2b04 cmp r3, #4 + 800234c: d002 beq.n 8002354 + 800234e: 2b08 cmp r3, #8 + 8002350: d003 beq.n 800235a + 8002352: e08c b.n 800246e + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8002354: 4b51 ldr r3, [pc, #324] @ (800249c ) + 8002356: 633b str r3, [r7, #48] @ 0x30 + break; + 8002358: e097 b.n 800248a + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 800235a: 4b51 ldr r3, [pc, #324] @ (80024a0 ) + 800235c: 633b str r3, [r7, #48] @ 0x30 + break; + 800235e: e094 b.n 800248a + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8002360: 6afb ldr r3, [r7, #44] @ 0x2c + 8002362: 0c9b lsrs r3, r3, #18 + 8002364: f003 020f and.w r2, r3, #15 + 8002368: 4b4e ldr r3, [pc, #312] @ (80024a4 ) + 800236a: 5c9b ldrb r3, [r3, r2] + 800236c: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 800236e: 6afb ldr r3, [r7, #44] @ 0x2c + 8002370: 0d9b lsrs r3, r3, #22 + 8002372: f003 0303 and.w r3, r3, #3 + 8002376: 3301 adds r3, #1 + 8002378: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 800237a: 4b47 ldr r3, [pc, #284] @ (8002498 ) + 800237c: 689b ldr r3, [r3, #8] + 800237e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8002382: 2b00 cmp r3, #0 + 8002384: d021 beq.n 80023ca + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8002386: 6abb ldr r3, [r7, #40] @ 0x28 + 8002388: 2200 movs r2, #0 + 800238a: 61bb str r3, [r7, #24] + 800238c: 61fa str r2, [r7, #28] + 800238e: 4b44 ldr r3, [pc, #272] @ (80024a0 ) + 8002390: e9d7 8906 ldrd r8, r9, [r7, #24] + 8002394: 464a mov r2, r9 + 8002396: fb03 f202 mul.w r2, r3, r2 + 800239a: 2300 movs r3, #0 + 800239c: 4644 mov r4, r8 + 800239e: fb04 f303 mul.w r3, r4, r3 + 80023a2: 4413 add r3, r2 + 80023a4: 4a3e ldr r2, [pc, #248] @ (80024a0 ) + 80023a6: 4644 mov r4, r8 + 80023a8: fba4 0102 umull r0, r1, r4, r2 + 80023ac: 440b add r3, r1 + 80023ae: 4619 mov r1, r3 + 80023b0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80023b2: 2200 movs r2, #0 + 80023b4: 613b str r3, [r7, #16] + 80023b6: 617a str r2, [r7, #20] + 80023b8: e9d7 2304 ldrd r2, r3, [r7, #16] + 80023bc: f7fe f9e6 bl 800078c <__aeabi_uldivmod> + 80023c0: 4602 mov r2, r0 + 80023c2: 460b mov r3, r1 + 80023c4: 4613 mov r3, r2 + 80023c6: 637b str r3, [r7, #52] @ 0x34 + 80023c8: e04e b.n 8002468 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 80023ca: 6abb ldr r3, [r7, #40] @ 0x28 + 80023cc: 2200 movs r2, #0 + 80023ce: 469a mov sl, r3 + 80023d0: 4693 mov fp, r2 + 80023d2: 4652 mov r2, sl + 80023d4: 465b mov r3, fp + 80023d6: f04f 0000 mov.w r0, #0 + 80023da: f04f 0100 mov.w r1, #0 + 80023de: 0159 lsls r1, r3, #5 + 80023e0: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 80023e4: 0150 lsls r0, r2, #5 + 80023e6: 4602 mov r2, r0 + 80023e8: 460b mov r3, r1 + 80023ea: ebb2 080a subs.w r8, r2, sl + 80023ee: eb63 090b sbc.w r9, r3, fp + 80023f2: f04f 0200 mov.w r2, #0 + 80023f6: f04f 0300 mov.w r3, #0 + 80023fa: ea4f 1389 mov.w r3, r9, lsl #6 + 80023fe: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8002402: ea4f 1288 mov.w r2, r8, lsl #6 + 8002406: ebb2 0408 subs.w r4, r2, r8 + 800240a: eb63 0509 sbc.w r5, r3, r9 + 800240e: f04f 0200 mov.w r2, #0 + 8002412: f04f 0300 mov.w r3, #0 + 8002416: 00eb lsls r3, r5, #3 + 8002418: ea43 7354 orr.w r3, r3, r4, lsr #29 + 800241c: 00e2 lsls r2, r4, #3 + 800241e: 4614 mov r4, r2 + 8002420: 461d mov r5, r3 + 8002422: eb14 030a adds.w r3, r4, sl + 8002426: 603b str r3, [r7, #0] + 8002428: eb45 030b adc.w r3, r5, fp + 800242c: 607b str r3, [r7, #4] + 800242e: f04f 0200 mov.w r2, #0 + 8002432: f04f 0300 mov.w r3, #0 + 8002436: e9d7 4500 ldrd r4, r5, [r7] + 800243a: 4629 mov r1, r5 + 800243c: 028b lsls r3, r1, #10 + 800243e: 4620 mov r0, r4 + 8002440: 4629 mov r1, r5 + 8002442: 4604 mov r4, r0 + 8002444: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8002448: 4601 mov r1, r0 + 800244a: 028a lsls r2, r1, #10 + 800244c: 4610 mov r0, r2 + 800244e: 4619 mov r1, r3 + 8002450: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002452: 2200 movs r2, #0 + 8002454: 60bb str r3, [r7, #8] + 8002456: 60fa str r2, [r7, #12] + 8002458: e9d7 2302 ldrd r2, r3, [r7, #8] + 800245c: f7fe f996 bl 800078c <__aeabi_uldivmod> + 8002460: 4602 mov r2, r0 + 8002462: 460b mov r3, r1 + 8002464: 4613 mov r3, r2 + 8002466: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 8002468: 6b7b ldr r3, [r7, #52] @ 0x34 + 800246a: 633b str r3, [r7, #48] @ 0x30 + break; + 800246c: e00d b.n 800248a + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 800246e: 4b0a ldr r3, [pc, #40] @ (8002498 ) + 8002470: 685b ldr r3, [r3, #4] + 8002472: 0b5b lsrs r3, r3, #13 + 8002474: f003 0307 and.w r3, r3, #7 + 8002478: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 800247a: 6a3b ldr r3, [r7, #32] + 800247c: 3301 adds r3, #1 + 800247e: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8002482: fa02 f303 lsl.w r3, r2, r3 + 8002486: 633b str r3, [r7, #48] @ 0x30 + break; + 8002488: bf00 nop + } + } + return sysclockfreq; + 800248a: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 800248c: 4618 mov r0, r3 + 800248e: 3738 adds r7, #56 @ 0x38 + 8002490: 46bd mov sp, r7 + 8002492: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8002496: bf00 nop + 8002498: 40023800 .word 0x40023800 + 800249c: 00f42400 .word 0x00f42400 + 80024a0: 016e3600 .word 0x016e3600 + 80024a4: 08003808 .word 0x08003808 + +080024a8 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 80024a8: b480 push {r7} + 80024aa: b087 sub sp, #28 + 80024ac: af00 add r7, sp, #0 + 80024ae: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 80024b0: 2300 movs r3, #0 + 80024b2: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 80024b4: 4b29 ldr r3, [pc, #164] @ (800255c ) + 80024b6: 689b ldr r3, [r3, #8] + 80024b8: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 80024bc: 2b00 cmp r3, #0 + 80024be: d12c bne.n 800251a + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 80024c0: 4b26 ldr r3, [pc, #152] @ (800255c ) + 80024c2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024c4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80024c8: 2b00 cmp r3, #0 + 80024ca: d005 beq.n 80024d8 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 80024cc: 4b24 ldr r3, [pc, #144] @ (8002560 ) + 80024ce: 681b ldr r3, [r3, #0] + 80024d0: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 80024d4: 617b str r3, [r7, #20] + 80024d6: e016 b.n 8002506 + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 80024d8: 4b20 ldr r3, [pc, #128] @ (800255c ) + 80024da: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024dc: 4a1f ldr r2, [pc, #124] @ (800255c ) + 80024de: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80024e2: 6253 str r3, [r2, #36] @ 0x24 + 80024e4: 4b1d ldr r3, [pc, #116] @ (800255c ) + 80024e6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024e8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80024ec: 60fb str r3, [r7, #12] + 80024ee: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 80024f0: 4b1b ldr r3, [pc, #108] @ (8002560 ) + 80024f2: 681b ldr r3, [r3, #0] + 80024f4: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 80024f8: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 80024fa: 4b18 ldr r3, [pc, #96] @ (800255c ) + 80024fc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80024fe: 4a17 ldr r2, [pc, #92] @ (800255c ) + 8002500: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8002504: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8002506: 697b ldr r3, [r7, #20] + 8002508: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 800250c: d105 bne.n 800251a + 800250e: 687b ldr r3, [r7, #4] + 8002510: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8002514: d101 bne.n 800251a + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8002516: 2301 movs r3, #1 + 8002518: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 800251a: 693b ldr r3, [r7, #16] + 800251c: 2b01 cmp r3, #1 + 800251e: d105 bne.n 800252c + 8002520: 4b10 ldr r3, [pc, #64] @ (8002564 ) + 8002522: 681b ldr r3, [r3, #0] + 8002524: 4a0f ldr r2, [pc, #60] @ (8002564 ) + 8002526: f043 0304 orr.w r3, r3, #4 + 800252a: 6013 str r3, [r2, #0] + 800252c: 4b0d ldr r3, [pc, #52] @ (8002564 ) + 800252e: 681b ldr r3, [r3, #0] + 8002530: f023 0201 bic.w r2, r3, #1 + 8002534: 490b ldr r1, [pc, #44] @ (8002564 ) + 8002536: 693b ldr r3, [r7, #16] + 8002538: 4313 orrs r3, r2 + 800253a: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 800253c: 4b09 ldr r3, [pc, #36] @ (8002564 ) + 800253e: 681b ldr r3, [r3, #0] + 8002540: f003 0301 and.w r3, r3, #1 + 8002544: 693a ldr r2, [r7, #16] + 8002546: 429a cmp r2, r3 + 8002548: d001 beq.n 800254e + { + return HAL_ERROR; + 800254a: 2301 movs r3, #1 + 800254c: e000 b.n 8002550 + } + + return HAL_OK; + 800254e: 2300 movs r3, #0 +} + 8002550: 4618 mov r0, r3 + 8002552: 371c adds r7, #28 + 8002554: 46bd mov sp, r7 + 8002556: bc80 pop {r7} + 8002558: 4770 bx lr + 800255a: bf00 nop + 800255c: 40023800 .word 0x40023800 + 8002560: 40007000 .word 0x40007000 + 8002564: 40023c00 .word 0x40023c00 + +08002568 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8002568: b580 push {r7, lr} + 800256a: b082 sub sp, #8 + 800256c: af00 add r7, sp, #0 + 800256e: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8002570: 687b ldr r3, [r7, #4] + 8002572: 2b00 cmp r3, #0 + 8002574: d101 bne.n 800257a + { + return HAL_ERROR; + 8002576: 2301 movs r3, #1 + 8002578: e07b b.n 8002672 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 800257a: 687b ldr r3, [r7, #4] + 800257c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800257e: 2b00 cmp r3, #0 + 8002580: d108 bne.n 8002594 + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8002582: 687b ldr r3, [r7, #4] + 8002584: 685b ldr r3, [r3, #4] + 8002586: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 800258a: d009 beq.n 80025a0 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 800258c: 687b ldr r3, [r7, #4] + 800258e: 2200 movs r2, #0 + 8002590: 61da str r2, [r3, #28] + 8002592: e005 b.n 80025a0 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8002594: 687b ldr r3, [r7, #4] + 8002596: 2200 movs r2, #0 + 8002598: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 800259a: 687b ldr r3, [r7, #4] + 800259c: 2200 movs r2, #0 + 800259e: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 80025a0: 687b ldr r3, [r7, #4] + 80025a2: 2200 movs r2, #0 + 80025a4: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 80025a6: 687b ldr r3, [r7, #4] + 80025a8: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 80025ac: b2db uxtb r3, r3 + 80025ae: 2b00 cmp r3, #0 + 80025b0: d106 bne.n 80025c0 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 80025b2: 687b ldr r3, [r7, #4] + 80025b4: 2200 movs r2, #0 + 80025b6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 80025ba: 6878 ldr r0, [r7, #4] + 80025bc: f7fe fd28 bl 8001010 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 80025c0: 687b ldr r3, [r7, #4] + 80025c2: 2202 movs r2, #2 + 80025c4: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 80025c8: 687b ldr r3, [r7, #4] + 80025ca: 681b ldr r3, [r3, #0] + 80025cc: 681a ldr r2, [r3, #0] + 80025ce: 687b ldr r3, [r7, #4] + 80025d0: 681b ldr r3, [r3, #0] + 80025d2: f022 0240 bic.w r2, r2, #64 @ 0x40 + 80025d6: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 80025d8: 687b ldr r3, [r7, #4] + 80025da: 685b ldr r3, [r3, #4] + 80025dc: f403 7282 and.w r2, r3, #260 @ 0x104 + 80025e0: 687b ldr r3, [r7, #4] + 80025e2: 689b ldr r3, [r3, #8] + 80025e4: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 80025e8: 431a orrs r2, r3 + 80025ea: 687b ldr r3, [r7, #4] + 80025ec: 68db ldr r3, [r3, #12] + 80025ee: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80025f2: 431a orrs r2, r3 + 80025f4: 687b ldr r3, [r7, #4] + 80025f6: 691b ldr r3, [r3, #16] + 80025f8: f003 0302 and.w r3, r3, #2 + 80025fc: 431a orrs r2, r3 + 80025fe: 687b ldr r3, [r7, #4] + 8002600: 695b ldr r3, [r3, #20] + 8002602: f003 0301 and.w r3, r3, #1 + 8002606: 431a orrs r2, r3 + 8002608: 687b ldr r3, [r7, #4] + 800260a: 699b ldr r3, [r3, #24] + 800260c: f403 7300 and.w r3, r3, #512 @ 0x200 + 8002610: 431a orrs r2, r3 + 8002612: 687b ldr r3, [r7, #4] + 8002614: 69db ldr r3, [r3, #28] + 8002616: f003 0338 and.w r3, r3, #56 @ 0x38 + 800261a: 431a orrs r2, r3 + 800261c: 687b ldr r3, [r7, #4] + 800261e: 6a1b ldr r3, [r3, #32] + 8002620: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002624: ea42 0103 orr.w r1, r2, r3 + 8002628: 687b ldr r3, [r7, #4] + 800262a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800262c: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8002630: 687b ldr r3, [r7, #4] + 8002632: 681b ldr r3, [r3, #0] + 8002634: 430a orrs r2, r1 + 8002636: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8002638: 687b ldr r3, [r7, #4] + 800263a: 699b ldr r3, [r3, #24] + 800263c: 0c1b lsrs r3, r3, #16 + 800263e: f003 0104 and.w r1, r3, #4 + 8002642: 687b ldr r3, [r7, #4] + 8002644: 6a5b ldr r3, [r3, #36] @ 0x24 + 8002646: f003 0210 and.w r2, r3, #16 + 800264a: 687b ldr r3, [r7, #4] + 800264c: 681b ldr r3, [r3, #0] + 800264e: 430a orrs r2, r1 + 8002650: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8002652: 687b ldr r3, [r7, #4] + 8002654: 681b ldr r3, [r3, #0] + 8002656: 69da ldr r2, [r3, #28] + 8002658: 687b ldr r3, [r7, #4] + 800265a: 681b ldr r3, [r3, #0] + 800265c: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8002660: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8002662: 687b ldr r3, [r7, #4] + 8002664: 2200 movs r2, #0 + 8002666: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8002668: 687b ldr r3, [r7, #4] + 800266a: 2201 movs r2, #1 + 800266c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8002670: 2300 movs r3, #0 +} + 8002672: 4618 mov r0, r3 + 8002674: 3708 adds r7, #8 + 8002676: 46bd mov sp, r7 + 8002678: bd80 pop {r7, pc} + +0800267a : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 800267a: b580 push {r7, lr} + 800267c: b088 sub sp, #32 + 800267e: af00 add r7, sp, #0 + 8002680: 60f8 str r0, [r7, #12] + 8002682: 60b9 str r1, [r7, #8] + 8002684: 603b str r3, [r7, #0] + 8002686: 4613 mov r3, r2 + 8002688: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 800268a: f7fe ff09 bl 80014a0 + 800268e: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8002690: 88fb ldrh r3, [r7, #6] + 8002692: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8002694: 68fb ldr r3, [r7, #12] + 8002696: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 800269a: b2db uxtb r3, r3 + 800269c: 2b01 cmp r3, #1 + 800269e: d001 beq.n 80026a4 + { + return HAL_BUSY; + 80026a0: 2302 movs r3, #2 + 80026a2: e12a b.n 80028fa + } + + if ((pData == NULL) || (Size == 0U)) + 80026a4: 68bb ldr r3, [r7, #8] + 80026a6: 2b00 cmp r3, #0 + 80026a8: d002 beq.n 80026b0 + 80026aa: 88fb ldrh r3, [r7, #6] + 80026ac: 2b00 cmp r3, #0 + 80026ae: d101 bne.n 80026b4 + { + return HAL_ERROR; + 80026b0: 2301 movs r3, #1 + 80026b2: e122 b.n 80028fa + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 80026b4: 68fb ldr r3, [r7, #12] + 80026b6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 80026ba: 2b01 cmp r3, #1 + 80026bc: d101 bne.n 80026c2 + 80026be: 2302 movs r3, #2 + 80026c0: e11b b.n 80028fa + 80026c2: 68fb ldr r3, [r7, #12] + 80026c4: 2201 movs r2, #1 + 80026c6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 80026ca: 68fb ldr r3, [r7, #12] + 80026cc: 2203 movs r2, #3 + 80026ce: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 80026d2: 68fb ldr r3, [r7, #12] + 80026d4: 2200 movs r2, #0 + 80026d6: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 80026d8: 68fb ldr r3, [r7, #12] + 80026da: 68ba ldr r2, [r7, #8] + 80026dc: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 80026de: 68fb ldr r3, [r7, #12] + 80026e0: 88fa ldrh r2, [r7, #6] + 80026e2: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 80026e4: 68fb ldr r3, [r7, #12] + 80026e6: 88fa ldrh r2, [r7, #6] + 80026e8: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 80026ea: 68fb ldr r3, [r7, #12] + 80026ec: 2200 movs r2, #0 + 80026ee: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 80026f0: 68fb ldr r3, [r7, #12] + 80026f2: 2200 movs r2, #0 + 80026f4: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 80026f6: 68fb ldr r3, [r7, #12] + 80026f8: 2200 movs r2, #0 + 80026fa: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 80026fc: 68fb ldr r3, [r7, #12] + 80026fe: 2200 movs r2, #0 + 8002700: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8002702: 68fb ldr r3, [r7, #12] + 8002704: 2200 movs r2, #0 + 8002706: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8002708: 68fb ldr r3, [r7, #12] + 800270a: 689b ldr r3, [r3, #8] + 800270c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8002710: d10f bne.n 8002732 + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8002712: 68fb ldr r3, [r7, #12] + 8002714: 681b ldr r3, [r3, #0] + 8002716: 681a ldr r2, [r3, #0] + 8002718: 68fb ldr r3, [r7, #12] + 800271a: 681b ldr r3, [r3, #0] + 800271c: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8002720: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8002722: 68fb ldr r3, [r7, #12] + 8002724: 681b ldr r3, [r3, #0] + 8002726: 681a ldr r2, [r3, #0] + 8002728: 68fb ldr r3, [r7, #12] + 800272a: 681b ldr r3, [r3, #0] + 800272c: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8002730: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8002732: 68fb ldr r3, [r7, #12] + 8002734: 681b ldr r3, [r3, #0] + 8002736: 681b ldr r3, [r3, #0] + 8002738: f003 0340 and.w r3, r3, #64 @ 0x40 + 800273c: 2b40 cmp r3, #64 @ 0x40 + 800273e: d007 beq.n 8002750 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8002740: 68fb ldr r3, [r7, #12] + 8002742: 681b ldr r3, [r3, #0] + 8002744: 681a ldr r2, [r3, #0] + 8002746: 68fb ldr r3, [r7, #12] + 8002748: 681b ldr r3, [r3, #0] + 800274a: f042 0240 orr.w r2, r2, #64 @ 0x40 + 800274e: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8002750: 68fb ldr r3, [r7, #12] + 8002752: 68db ldr r3, [r3, #12] + 8002754: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8002758: d152 bne.n 8002800 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800275a: 68fb ldr r3, [r7, #12] + 800275c: 685b ldr r3, [r3, #4] + 800275e: 2b00 cmp r3, #0 + 8002760: d002 beq.n 8002768 + 8002762: 8b7b ldrh r3, [r7, #26] + 8002764: 2b01 cmp r3, #1 + 8002766: d145 bne.n 80027f4 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8002768: 68fb ldr r3, [r7, #12] + 800276a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800276c: 881a ldrh r2, [r3, #0] + 800276e: 68fb ldr r3, [r7, #12] + 8002770: 681b ldr r3, [r3, #0] + 8002772: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8002774: 68fb ldr r3, [r7, #12] + 8002776: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002778: 1c9a adds r2, r3, #2 + 800277a: 68fb ldr r3, [r7, #12] + 800277c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 800277e: 68fb ldr r3, [r7, #12] + 8002780: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002782: b29b uxth r3, r3 + 8002784: 3b01 subs r3, #1 + 8002786: b29a uxth r2, r3 + 8002788: 68fb ldr r3, [r7, #12] + 800278a: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 800278c: e032 b.n 80027f4 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 800278e: 68fb ldr r3, [r7, #12] + 8002790: 681b ldr r3, [r3, #0] + 8002792: 689b ldr r3, [r3, #8] + 8002794: f003 0302 and.w r3, r3, #2 + 8002798: 2b02 cmp r3, #2 + 800279a: d112 bne.n 80027c2 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 800279c: 68fb ldr r3, [r7, #12] + 800279e: 6b1b ldr r3, [r3, #48] @ 0x30 + 80027a0: 881a ldrh r2, [r3, #0] + 80027a2: 68fb ldr r3, [r7, #12] + 80027a4: 681b ldr r3, [r3, #0] + 80027a6: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 80027a8: 68fb ldr r3, [r7, #12] + 80027aa: 6b1b ldr r3, [r3, #48] @ 0x30 + 80027ac: 1c9a adds r2, r3, #2 + 80027ae: 68fb ldr r3, [r7, #12] + 80027b0: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 80027b2: 68fb ldr r3, [r7, #12] + 80027b4: 8edb ldrh r3, [r3, #54] @ 0x36 + 80027b6: b29b uxth r3, r3 + 80027b8: 3b01 subs r3, #1 + 80027ba: b29a uxth r2, r3 + 80027bc: 68fb ldr r3, [r7, #12] + 80027be: 86da strh r2, [r3, #54] @ 0x36 + 80027c0: e018 b.n 80027f4 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 80027c2: f7fe fe6d bl 80014a0 + 80027c6: 4602 mov r2, r0 + 80027c8: 69fb ldr r3, [r7, #28] + 80027ca: 1ad3 subs r3, r2, r3 + 80027cc: 683a ldr r2, [r7, #0] + 80027ce: 429a cmp r2, r3 + 80027d0: d803 bhi.n 80027da + 80027d2: 683b ldr r3, [r7, #0] + 80027d4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80027d8: d102 bne.n 80027e0 + 80027da: 683b ldr r3, [r7, #0] + 80027dc: 2b00 cmp r3, #0 + 80027de: d109 bne.n 80027f4 + { + hspi->State = HAL_SPI_STATE_READY; + 80027e0: 68fb ldr r3, [r7, #12] + 80027e2: 2201 movs r2, #1 + 80027e4: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 80027e8: 68fb ldr r3, [r7, #12] + 80027ea: 2200 movs r2, #0 + 80027ec: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 80027f0: 2303 movs r3, #3 + 80027f2: e082 b.n 80028fa + while (hspi->TxXferCount > 0U) + 80027f4: 68fb ldr r3, [r7, #12] + 80027f6: 8edb ldrh r3, [r3, #54] @ 0x36 + 80027f8: b29b uxth r3, r3 + 80027fa: 2b00 cmp r3, #0 + 80027fc: d1c7 bne.n 800278e + 80027fe: e053 b.n 80028a8 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8002800: 68fb ldr r3, [r7, #12] + 8002802: 685b ldr r3, [r3, #4] + 8002804: 2b00 cmp r3, #0 + 8002806: d002 beq.n 800280e + 8002808: 8b7b ldrh r3, [r7, #26] + 800280a: 2b01 cmp r3, #1 + 800280c: d147 bne.n 800289e + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 800280e: 68fb ldr r3, [r7, #12] + 8002810: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002812: 68fb ldr r3, [r7, #12] + 8002814: 681b ldr r3, [r3, #0] + 8002816: 330c adds r3, #12 + 8002818: 7812 ldrb r2, [r2, #0] + 800281a: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 800281c: 68fb ldr r3, [r7, #12] + 800281e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002820: 1c5a adds r2, r3, #1 + 8002822: 68fb ldr r3, [r7, #12] + 8002824: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8002826: 68fb ldr r3, [r7, #12] + 8002828: 8edb ldrh r3, [r3, #54] @ 0x36 + 800282a: b29b uxth r3, r3 + 800282c: 3b01 subs r3, #1 + 800282e: b29a uxth r2, r3 + 8002830: 68fb ldr r3, [r7, #12] + 8002832: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8002834: e033 b.n 800289e + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8002836: 68fb ldr r3, [r7, #12] + 8002838: 681b ldr r3, [r3, #0] + 800283a: 689b ldr r3, [r3, #8] + 800283c: f003 0302 and.w r3, r3, #2 + 8002840: 2b02 cmp r3, #2 + 8002842: d113 bne.n 800286c + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8002844: 68fb ldr r3, [r7, #12] + 8002846: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002848: 68fb ldr r3, [r7, #12] + 800284a: 681b ldr r3, [r3, #0] + 800284c: 330c adds r3, #12 + 800284e: 7812 ldrb r2, [r2, #0] + 8002850: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8002852: 68fb ldr r3, [r7, #12] + 8002854: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002856: 1c5a adds r2, r3, #1 + 8002858: 68fb ldr r3, [r7, #12] + 800285a: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 800285c: 68fb ldr r3, [r7, #12] + 800285e: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002860: b29b uxth r3, r3 + 8002862: 3b01 subs r3, #1 + 8002864: b29a uxth r2, r3 + 8002866: 68fb ldr r3, [r7, #12] + 8002868: 86da strh r2, [r3, #54] @ 0x36 + 800286a: e018 b.n 800289e + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800286c: f7fe fe18 bl 80014a0 + 8002870: 4602 mov r2, r0 + 8002872: 69fb ldr r3, [r7, #28] + 8002874: 1ad3 subs r3, r2, r3 + 8002876: 683a ldr r2, [r7, #0] + 8002878: 429a cmp r2, r3 + 800287a: d803 bhi.n 8002884 + 800287c: 683b ldr r3, [r7, #0] + 800287e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8002882: d102 bne.n 800288a + 8002884: 683b ldr r3, [r7, #0] + 8002886: 2b00 cmp r3, #0 + 8002888: d109 bne.n 800289e + { + hspi->State = HAL_SPI_STATE_READY; + 800288a: 68fb ldr r3, [r7, #12] + 800288c: 2201 movs r2, #1 + 800288e: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8002892: 68fb ldr r3, [r7, #12] + 8002894: 2200 movs r2, #0 + 8002896: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 800289a: 2303 movs r3, #3 + 800289c: e02d b.n 80028fa + while (hspi->TxXferCount > 0U) + 800289e: 68fb ldr r3, [r7, #12] + 80028a0: 8edb ldrh r3, [r3, #54] @ 0x36 + 80028a2: b29b uxth r3, r3 + 80028a4: 2b00 cmp r3, #0 + 80028a6: d1c6 bne.n 8002836 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 80028a8: 69fa ldr r2, [r7, #28] + 80028aa: 6839 ldr r1, [r7, #0] + 80028ac: 68f8 ldr r0, [r7, #12] + 80028ae: f000 f8b1 bl 8002a14 + 80028b2: 4603 mov r3, r0 + 80028b4: 2b00 cmp r3, #0 + 80028b6: d002 beq.n 80028be + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 80028b8: 68fb ldr r3, [r7, #12] + 80028ba: 2220 movs r2, #32 + 80028bc: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 80028be: 68fb ldr r3, [r7, #12] + 80028c0: 689b ldr r3, [r3, #8] + 80028c2: 2b00 cmp r3, #0 + 80028c4: d10a bne.n 80028dc + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 80028c6: 2300 movs r3, #0 + 80028c8: 617b str r3, [r7, #20] + 80028ca: 68fb ldr r3, [r7, #12] + 80028cc: 681b ldr r3, [r3, #0] + 80028ce: 68db ldr r3, [r3, #12] + 80028d0: 617b str r3, [r7, #20] + 80028d2: 68fb ldr r3, [r7, #12] + 80028d4: 681b ldr r3, [r3, #0] + 80028d6: 689b ldr r3, [r3, #8] + 80028d8: 617b str r3, [r7, #20] + 80028da: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 80028dc: 68fb ldr r3, [r7, #12] + 80028de: 2201 movs r2, #1 + 80028e0: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80028e4: 68fb ldr r3, [r7, #12] + 80028e6: 2200 movs r2, #0 + 80028e8: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 80028ec: 68fb ldr r3, [r7, #12] + 80028ee: 6d5b ldr r3, [r3, #84] @ 0x54 + 80028f0: 2b00 cmp r3, #0 + 80028f2: d001 beq.n 80028f8 + { + return HAL_ERROR; + 80028f4: 2301 movs r3, #1 + 80028f6: e000 b.n 80028fa + } + else + { + return HAL_OK; + 80028f8: 2300 movs r3, #0 + } +} + 80028fa: 4618 mov r0, r3 + 80028fc: 3720 adds r7, #32 + 80028fe: 46bd mov sp, r7 + 8002900: bd80 pop {r7, pc} + ... + +08002904 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8002904: b580 push {r7, lr} + 8002906: b088 sub sp, #32 + 8002908: af00 add r7, sp, #0 + 800290a: 60f8 str r0, [r7, #12] + 800290c: 60b9 str r1, [r7, #8] + 800290e: 603b str r3, [r7, #0] + 8002910: 4613 mov r3, r2 + 8002912: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 8002914: f7fe fdc4 bl 80014a0 + 8002918: 4602 mov r2, r0 + 800291a: 6abb ldr r3, [r7, #40] @ 0x28 + 800291c: 1a9b subs r3, r3, r2 + 800291e: 683a ldr r2, [r7, #0] + 8002920: 4413 add r3, r2 + 8002922: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 8002924: f7fe fdbc bl 80014a0 + 8002928: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 800292a: 4b39 ldr r3, [pc, #228] @ (8002a10 ) + 800292c: 681b ldr r3, [r3, #0] + 800292e: 015b lsls r3, r3, #5 + 8002930: 0d1b lsrs r3, r3, #20 + 8002932: 69fa ldr r2, [r7, #28] + 8002934: fb02 f303 mul.w r3, r2, r3 + 8002938: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 800293a: e054 b.n 80029e6 + { + if (Timeout != HAL_MAX_DELAY) + 800293c: 683b ldr r3, [r7, #0] + 800293e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8002942: d050 beq.n 80029e6 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8002944: f7fe fdac bl 80014a0 + 8002948: 4602 mov r2, r0 + 800294a: 69bb ldr r3, [r7, #24] + 800294c: 1ad3 subs r3, r2, r3 + 800294e: 69fa ldr r2, [r7, #28] + 8002950: 429a cmp r2, r3 + 8002952: d902 bls.n 800295a + 8002954: 69fb ldr r3, [r7, #28] + 8002956: 2b00 cmp r3, #0 + 8002958: d13d bne.n 80029d6 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 800295a: 68fb ldr r3, [r7, #12] + 800295c: 681b ldr r3, [r3, #0] + 800295e: 685a ldr r2, [r3, #4] + 8002960: 68fb ldr r3, [r7, #12] + 8002962: 681b ldr r3, [r3, #0] + 8002964: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8002968: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800296a: 68fb ldr r3, [r7, #12] + 800296c: 685b ldr r3, [r3, #4] + 800296e: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002972: d111 bne.n 8002998 + 8002974: 68fb ldr r3, [r7, #12] + 8002976: 689b ldr r3, [r3, #8] + 8002978: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 800297c: d004 beq.n 8002988 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800297e: 68fb ldr r3, [r7, #12] + 8002980: 689b ldr r3, [r3, #8] + 8002982: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8002986: d107 bne.n 8002998 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8002988: 68fb ldr r3, [r7, #12] + 800298a: 681b ldr r3, [r3, #0] + 800298c: 681a ldr r2, [r3, #0] + 800298e: 68fb ldr r3, [r7, #12] + 8002990: 681b ldr r3, [r3, #0] + 8002992: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8002996: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8002998: 68fb ldr r3, [r7, #12] + 800299a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800299c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80029a0: d10f bne.n 80029c2 + { + SPI_RESET_CRC(hspi); + 80029a2: 68fb ldr r3, [r7, #12] + 80029a4: 681b ldr r3, [r3, #0] + 80029a6: 681a ldr r2, [r3, #0] + 80029a8: 68fb ldr r3, [r7, #12] + 80029aa: 681b ldr r3, [r3, #0] + 80029ac: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 80029b0: 601a str r2, [r3, #0] + 80029b2: 68fb ldr r3, [r7, #12] + 80029b4: 681b ldr r3, [r3, #0] + 80029b6: 681a ldr r2, [r3, #0] + 80029b8: 68fb ldr r3, [r7, #12] + 80029ba: 681b ldr r3, [r3, #0] + 80029bc: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 80029c0: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 80029c2: 68fb ldr r3, [r7, #12] + 80029c4: 2201 movs r2, #1 + 80029c6: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80029ca: 68fb ldr r3, [r7, #12] + 80029cc: 2200 movs r2, #0 + 80029ce: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 80029d2: 2303 movs r3, #3 + 80029d4: e017 b.n 8002a06 + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 80029d6: 697b ldr r3, [r7, #20] + 80029d8: 2b00 cmp r3, #0 + 80029da: d101 bne.n 80029e0 + { + tmp_timeout = 0U; + 80029dc: 2300 movs r3, #0 + 80029de: 61fb str r3, [r7, #28] + } + count--; + 80029e0: 697b ldr r3, [r7, #20] + 80029e2: 3b01 subs r3, #1 + 80029e4: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 80029e6: 68fb ldr r3, [r7, #12] + 80029e8: 681b ldr r3, [r3, #0] + 80029ea: 689a ldr r2, [r3, #8] + 80029ec: 68bb ldr r3, [r7, #8] + 80029ee: 4013 ands r3, r2 + 80029f0: 68ba ldr r2, [r7, #8] + 80029f2: 429a cmp r2, r3 + 80029f4: bf0c ite eq + 80029f6: 2301 moveq r3, #1 + 80029f8: 2300 movne r3, #0 + 80029fa: b2db uxtb r3, r3 + 80029fc: 461a mov r2, r3 + 80029fe: 79fb ldrb r3, [r7, #7] + 8002a00: 429a cmp r2, r3 + 8002a02: d19b bne.n 800293c + } + } + + return HAL_OK; + 8002a04: 2300 movs r3, #0 +} + 8002a06: 4618 mov r0, r3 + 8002a08: 3720 adds r7, #32 + 8002a0a: 46bd mov sp, r7 + 8002a0c: bd80 pop {r7, pc} + 8002a0e: bf00 nop + 8002a10: 20000004 .word 0x20000004 + +08002a14 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 8002a14: b580 push {r7, lr} + 8002a16: b088 sub sp, #32 + 8002a18: af02 add r7, sp, #8 + 8002a1a: 60f8 str r0, [r7, #12] + 8002a1c: 60b9 str r1, [r7, #8] + 8002a1e: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 8002a20: 687b ldr r3, [r7, #4] + 8002a22: 9300 str r3, [sp, #0] + 8002a24: 68bb ldr r3, [r7, #8] + 8002a26: 2201 movs r2, #1 + 8002a28: 2102 movs r1, #2 + 8002a2a: 68f8 ldr r0, [r7, #12] + 8002a2c: f7ff ff6a bl 8002904 + 8002a30: 4603 mov r3, r0 + 8002a32: 2b00 cmp r3, #0 + 8002a34: d007 beq.n 8002a46 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002a36: 68fb ldr r3, [r7, #12] + 8002a38: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002a3a: f043 0220 orr.w r2, r3, #32 + 8002a3e: 68fb ldr r3, [r7, #12] + 8002a40: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8002a42: 2303 movs r3, #3 + 8002a44: e032 b.n 8002aac + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 8002a46: 4b1b ldr r3, [pc, #108] @ (8002ab4 ) + 8002a48: 681b ldr r3, [r3, #0] + 8002a4a: 4a1b ldr r2, [pc, #108] @ (8002ab8 ) + 8002a4c: fba2 2303 umull r2, r3, r2, r3 + 8002a50: 0d5b lsrs r3, r3, #21 + 8002a52: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8002a56: fb02 f303 mul.w r3, r2, r3 + 8002a5a: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8002a5c: 68fb ldr r3, [r7, #12] + 8002a5e: 685b ldr r3, [r3, #4] + 8002a60: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002a64: d112 bne.n 8002a8c + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8002a66: 687b ldr r3, [r7, #4] + 8002a68: 9300 str r3, [sp, #0] + 8002a6a: 68bb ldr r3, [r7, #8] + 8002a6c: 2200 movs r2, #0 + 8002a6e: 2180 movs r1, #128 @ 0x80 + 8002a70: 68f8 ldr r0, [r7, #12] + 8002a72: f7ff ff47 bl 8002904 + 8002a76: 4603 mov r3, r0 + 8002a78: 2b00 cmp r3, #0 + 8002a7a: d016 beq.n 8002aaa + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002a7c: 68fb ldr r3, [r7, #12] + 8002a7e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002a80: f043 0220 orr.w r2, r3, #32 + 8002a84: 68fb ldr r3, [r7, #12] + 8002a86: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8002a88: 2303 movs r3, #3 + 8002a8a: e00f b.n 8002aac + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 8002a8c: 697b ldr r3, [r7, #20] + 8002a8e: 2b00 cmp r3, #0 + 8002a90: d00a beq.n 8002aa8 + { + break; + } + count--; + 8002a92: 697b ldr r3, [r7, #20] + 8002a94: 3b01 subs r3, #1 + 8002a96: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 8002a98: 68fb ldr r3, [r7, #12] + 8002a9a: 681b ldr r3, [r3, #0] + 8002a9c: 689b ldr r3, [r3, #8] + 8002a9e: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002aa2: 2b80 cmp r3, #128 @ 0x80 + 8002aa4: d0f2 beq.n 8002a8c + 8002aa6: e000 b.n 8002aaa + break; + 8002aa8: bf00 nop + } + + return HAL_OK; + 8002aaa: 2300 movs r3, #0 +} + 8002aac: 4618 mov r0, r3 + 8002aae: 3718 adds r7, #24 + 8002ab0: 46bd mov sp, r7 + 8002ab2: bd80 pop {r7, pc} + 8002ab4: 20000004 .word 0x20000004 + 8002ab8: 165e9f81 .word 0x165e9f81 + +08002abc : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 8002abc: b580 push {r7, lr} + 8002abe: b082 sub sp, #8 + 8002ac0: af00 add r7, sp, #0 + 8002ac2: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8002ac4: 687b ldr r3, [r7, #4] + 8002ac6: 2b00 cmp r3, #0 + 8002ac8: d101 bne.n 8002ace + { + return HAL_ERROR; + 8002aca: 2301 movs r3, #1 + 8002acc: e031 b.n 8002b32 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8002ace: 687b ldr r3, [r7, #4] + 8002ad0: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 8002ad4: b2db uxtb r3, r3 + 8002ad6: 2b00 cmp r3, #0 + 8002ad8: d106 bne.n 8002ae8 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8002ada: 687b ldr r3, [r7, #4] + 8002adc: 2200 movs r2, #0 + 8002ade: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8002ae2: 6878 ldr r0, [r7, #4] + 8002ae4: f7fe fad8 bl 8001098 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002ae8: 687b ldr r3, [r7, #4] + 8002aea: 2202 movs r2, #2 + 8002aec: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002af0: 687b ldr r3, [r7, #4] + 8002af2: 681a ldr r2, [r3, #0] + 8002af4: 687b ldr r3, [r7, #4] + 8002af6: 3304 adds r3, #4 + 8002af8: 4619 mov r1, r3 + 8002afa: 4610 mov r0, r2 + 8002afc: f000 fbc8 bl 8003290 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002b00: 687b ldr r3, [r7, #4] + 8002b02: 2201 movs r2, #1 + 8002b04: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8002b08: 687b ldr r3, [r7, #4] + 8002b0a: 2201 movs r2, #1 + 8002b0c: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002b10: 687b ldr r3, [r7, #4] + 8002b12: 2201 movs r2, #1 + 8002b14: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002b18: 687b ldr r3, [r7, #4] + 8002b1a: 2201 movs r2, #1 + 8002b1c: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002b20: 687b ldr r3, [r7, #4] + 8002b22: 2201 movs r2, #1 + 8002b24: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8002b28: 687b ldr r3, [r7, #4] + 8002b2a: 2201 movs r2, #1 + 8002b2c: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 8002b30: 2300 movs r3, #0 +} + 8002b32: 4618 mov r0, r3 + 8002b34: 3708 adds r7, #8 + 8002b36: 46bd mov sp, r7 + 8002b38: bd80 pop {r7, pc} + ... + +08002b3c : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 8002b3c: b480 push {r7} + 8002b3e: b085 sub sp, #20 + 8002b40: af00 add r7, sp, #0 + 8002b42: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + 8002b44: 687b ldr r3, [r7, #4] + 8002b46: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 8002b4a: b2db uxtb r3, r3 + 8002b4c: 2b01 cmp r3, #1 + 8002b4e: d001 beq.n 8002b54 + { + return HAL_ERROR; + 8002b50: 2301 movs r3, #1 + 8002b52: e03a b.n 8002bca + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002b54: 687b ldr r3, [r7, #4] + 8002b56: 2202 movs r2, #2 + 8002b58: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 8002b5c: 687b ldr r3, [r7, #4] + 8002b5e: 681b ldr r3, [r3, #0] + 8002b60: 68da ldr r2, [r3, #12] + 8002b62: 687b ldr r3, [r7, #4] + 8002b64: 681b ldr r3, [r3, #0] + 8002b66: f042 0201 orr.w r2, r2, #1 + 8002b6a: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8002b6c: 687b ldr r3, [r7, #4] + 8002b6e: 681b ldr r3, [r3, #0] + 8002b70: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002b74: d00e beq.n 8002b94 + 8002b76: 687b ldr r3, [r7, #4] + 8002b78: 681b ldr r3, [r3, #0] + 8002b7a: 4a16 ldr r2, [pc, #88] @ (8002bd4 ) + 8002b7c: 4293 cmp r3, r2 + 8002b7e: d009 beq.n 8002b94 + 8002b80: 687b ldr r3, [r7, #4] + 8002b82: 681b ldr r3, [r3, #0] + 8002b84: 4a14 ldr r2, [pc, #80] @ (8002bd8 ) + 8002b86: 4293 cmp r3, r2 + 8002b88: d004 beq.n 8002b94 + 8002b8a: 687b ldr r3, [r7, #4] + 8002b8c: 681b ldr r3, [r3, #0] + 8002b8e: 4a13 ldr r2, [pc, #76] @ (8002bdc ) + 8002b90: 4293 cmp r3, r2 + 8002b92: d111 bne.n 8002bb8 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8002b94: 687b ldr r3, [r7, #4] + 8002b96: 681b ldr r3, [r3, #0] + 8002b98: 689b ldr r3, [r3, #8] + 8002b9a: f003 0307 and.w r3, r3, #7 + 8002b9e: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8002ba0: 68fb ldr r3, [r7, #12] + 8002ba2: 2b06 cmp r3, #6 + 8002ba4: d010 beq.n 8002bc8 + { + __HAL_TIM_ENABLE(htim); + 8002ba6: 687b ldr r3, [r7, #4] + 8002ba8: 681b ldr r3, [r3, #0] + 8002baa: 681a ldr r2, [r3, #0] + 8002bac: 687b ldr r3, [r7, #4] + 8002bae: 681b ldr r3, [r3, #0] + 8002bb0: f042 0201 orr.w r2, r2, #1 + 8002bb4: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8002bb6: e007 b.n 8002bc8 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 8002bb8: 687b ldr r3, [r7, #4] + 8002bba: 681b ldr r3, [r3, #0] + 8002bbc: 681a ldr r2, [r3, #0] + 8002bbe: 687b ldr r3, [r7, #4] + 8002bc0: 681b ldr r3, [r3, #0] + 8002bc2: f042 0201 orr.w r2, r2, #1 + 8002bc6: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8002bc8: 2300 movs r3, #0 +} + 8002bca: 4618 mov r0, r3 + 8002bcc: 3714 adds r7, #20 + 8002bce: 46bd mov sp, r7 + 8002bd0: bc80 pop {r7} + 8002bd2: 4770 bx lr + 8002bd4: 40000400 .word 0x40000400 + 8002bd8: 40000800 .word 0x40000800 + 8002bdc: 40010800 .word 0x40010800 + +08002be0 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8002be0: b580 push {r7, lr} + 8002be2: b082 sub sp, #8 + 8002be4: af00 add r7, sp, #0 + 8002be6: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8002be8: 687b ldr r3, [r7, #4] + 8002bea: 2b00 cmp r3, #0 + 8002bec: d101 bne.n 8002bf2 + { + return HAL_ERROR; + 8002bee: 2301 movs r3, #1 + 8002bf0: e031 b.n 8002c56 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8002bf2: 687b ldr r3, [r7, #4] + 8002bf4: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 8002bf8: b2db uxtb r3, r3 + 8002bfa: 2b00 cmp r3, #0 + 8002bfc: d106 bne.n 8002c0c + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8002bfe: 687b ldr r3, [r7, #4] + 8002c00: 2200 movs r2, #0 + 8002c02: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 8002c06: 6878 ldr r0, [r7, #4] + 8002c08: f000 f829 bl 8002c5e +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002c0c: 687b ldr r3, [r7, #4] + 8002c0e: 2202 movs r2, #2 + 8002c10: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002c14: 687b ldr r3, [r7, #4] + 8002c16: 681a ldr r2, [r3, #0] + 8002c18: 687b ldr r3, [r7, #4] + 8002c1a: 3304 adds r3, #4 + 8002c1c: 4619 mov r1, r3 + 8002c1e: 4610 mov r0, r2 + 8002c20: f000 fb36 bl 8003290 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002c24: 687b ldr r3, [r7, #4] + 8002c26: 2201 movs r2, #1 + 8002c28: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8002c2c: 687b ldr r3, [r7, #4] + 8002c2e: 2201 movs r2, #1 + 8002c30: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002c34: 687b ldr r3, [r7, #4] + 8002c36: 2201 movs r2, #1 + 8002c38: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002c3c: 687b ldr r3, [r7, #4] + 8002c3e: 2201 movs r2, #1 + 8002c40: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002c44: 687b ldr r3, [r7, #4] + 8002c46: 2201 movs r2, #1 + 8002c48: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8002c4c: 687b ldr r3, [r7, #4] + 8002c4e: 2201 movs r2, #1 + 8002c50: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 8002c54: 2300 movs r3, #0 +} + 8002c56: 4618 mov r0, r3 + 8002c58: 3708 adds r7, #8 + 8002c5a: 46bd mov sp, r7 + 8002c5c: bd80 pop {r7, pc} + +08002c5e : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 8002c5e: b480 push {r7} + 8002c60: b083 sub sp, #12 + 8002c62: af00 add r7, sp, #0 + 8002c64: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 8002c66: bf00 nop + 8002c68: 370c adds r7, #12 + 8002c6a: 46bd mov sp, r7 + 8002c6c: bc80 pop {r7} + 8002c6e: 4770 bx lr + +08002c70 : + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 8002c70: b580 push {r7, lr} + 8002c72: b084 sub sp, #16 + 8002c74: af00 add r7, sp, #0 + 8002c76: 6078 str r0, [r7, #4] + 8002c78: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 8002c7a: 683b ldr r3, [r7, #0] + 8002c7c: 2b00 cmp r3, #0 + 8002c7e: d109 bne.n 8002c94 + 8002c80: 687b ldr r3, [r7, #4] + 8002c82: f893 303a ldrb.w r3, [r3, #58] @ 0x3a + 8002c86: b2db uxtb r3, r3 + 8002c88: 2b01 cmp r3, #1 + 8002c8a: bf14 ite ne + 8002c8c: 2301 movne r3, #1 + 8002c8e: 2300 moveq r3, #0 + 8002c90: b2db uxtb r3, r3 + 8002c92: e022 b.n 8002cda + 8002c94: 683b ldr r3, [r7, #0] + 8002c96: 2b04 cmp r3, #4 + 8002c98: d109 bne.n 8002cae + 8002c9a: 687b ldr r3, [r7, #4] + 8002c9c: f893 303b ldrb.w r3, [r3, #59] @ 0x3b + 8002ca0: b2db uxtb r3, r3 + 8002ca2: 2b01 cmp r3, #1 + 8002ca4: bf14 ite ne + 8002ca6: 2301 movne r3, #1 + 8002ca8: 2300 moveq r3, #0 + 8002caa: b2db uxtb r3, r3 + 8002cac: e015 b.n 8002cda + 8002cae: 683b ldr r3, [r7, #0] + 8002cb0: 2b08 cmp r3, #8 + 8002cb2: d109 bne.n 8002cc8 + 8002cb4: 687b ldr r3, [r7, #4] + 8002cb6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8002cba: b2db uxtb r3, r3 + 8002cbc: 2b01 cmp r3, #1 + 8002cbe: bf14 ite ne + 8002cc0: 2301 movne r3, #1 + 8002cc2: 2300 moveq r3, #0 + 8002cc4: b2db uxtb r3, r3 + 8002cc6: e008 b.n 8002cda + 8002cc8: 687b ldr r3, [r7, #4] + 8002cca: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8002cce: b2db uxtb r3, r3 + 8002cd0: 2b01 cmp r3, #1 + 8002cd2: bf14 ite ne + 8002cd4: 2301 movne r3, #1 + 8002cd6: 2300 moveq r3, #0 + 8002cd8: b2db uxtb r3, r3 + 8002cda: 2b00 cmp r3, #0 + 8002cdc: d001 beq.n 8002ce2 + { + return HAL_ERROR; + 8002cde: 2301 movs r3, #1 + 8002ce0: e051 b.n 8002d86 + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 8002ce2: 683b ldr r3, [r7, #0] + 8002ce4: 2b00 cmp r3, #0 + 8002ce6: d104 bne.n 8002cf2 + 8002ce8: 687b ldr r3, [r7, #4] + 8002cea: 2202 movs r2, #2 + 8002cec: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002cf0: e013 b.n 8002d1a + 8002cf2: 683b ldr r3, [r7, #0] + 8002cf4: 2b04 cmp r3, #4 + 8002cf6: d104 bne.n 8002d02 + 8002cf8: 687b ldr r3, [r7, #4] + 8002cfa: 2202 movs r2, #2 + 8002cfc: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002d00: e00b b.n 8002d1a + 8002d02: 683b ldr r3, [r7, #0] + 8002d04: 2b08 cmp r3, #8 + 8002d06: d104 bne.n 8002d12 + 8002d08: 687b ldr r3, [r7, #4] + 8002d0a: 2202 movs r2, #2 + 8002d0c: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002d10: e003 b.n 8002d1a + 8002d12: 687b ldr r3, [r7, #4] + 8002d14: 2202 movs r2, #2 + 8002d16: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 8002d1a: 687b ldr r3, [r7, #4] + 8002d1c: 681b ldr r3, [r3, #0] + 8002d1e: 2201 movs r2, #1 + 8002d20: 6839 ldr r1, [r7, #0] + 8002d22: 4618 mov r0, r3 + 8002d24: f000 fcb5 bl 8003692 + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8002d28: 687b ldr r3, [r7, #4] + 8002d2a: 681b ldr r3, [r3, #0] + 8002d2c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002d30: d00e beq.n 8002d50 + 8002d32: 687b ldr r3, [r7, #4] + 8002d34: 681b ldr r3, [r3, #0] + 8002d36: 4a16 ldr r2, [pc, #88] @ (8002d90 ) + 8002d38: 4293 cmp r3, r2 + 8002d3a: d009 beq.n 8002d50 + 8002d3c: 687b ldr r3, [r7, #4] + 8002d3e: 681b ldr r3, [r3, #0] + 8002d40: 4a14 ldr r2, [pc, #80] @ (8002d94 ) + 8002d42: 4293 cmp r3, r2 + 8002d44: d004 beq.n 8002d50 + 8002d46: 687b ldr r3, [r7, #4] + 8002d48: 681b ldr r3, [r3, #0] + 8002d4a: 4a13 ldr r2, [pc, #76] @ (8002d98 ) + 8002d4c: 4293 cmp r3, r2 + 8002d4e: d111 bne.n 8002d74 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8002d50: 687b ldr r3, [r7, #4] + 8002d52: 681b ldr r3, [r3, #0] + 8002d54: 689b ldr r3, [r3, #8] + 8002d56: f003 0307 and.w r3, r3, #7 + 8002d5a: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8002d5c: 68fb ldr r3, [r7, #12] + 8002d5e: 2b06 cmp r3, #6 + 8002d60: d010 beq.n 8002d84 + { + __HAL_TIM_ENABLE(htim); + 8002d62: 687b ldr r3, [r7, #4] + 8002d64: 681b ldr r3, [r3, #0] + 8002d66: 681a ldr r2, [r3, #0] + 8002d68: 687b ldr r3, [r7, #4] + 8002d6a: 681b ldr r3, [r3, #0] + 8002d6c: f042 0201 orr.w r2, r2, #1 + 8002d70: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8002d72: e007 b.n 8002d84 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 8002d74: 687b ldr r3, [r7, #4] + 8002d76: 681b ldr r3, [r3, #0] + 8002d78: 681a ldr r2, [r3, #0] + 8002d7a: 687b ldr r3, [r7, #4] + 8002d7c: 681b ldr r3, [r3, #0] + 8002d7e: f042 0201 orr.w r2, r2, #1 + 8002d82: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8002d84: 2300 movs r3, #0 +} + 8002d86: 4618 mov r0, r3 + 8002d88: 3710 adds r7, #16 + 8002d8a: 46bd mov sp, r7 + 8002d8c: bd80 pop {r7, pc} + 8002d8e: bf00 nop + 8002d90: 40000400 .word 0x40000400 + 8002d94: 40000800 .word 0x40000800 + 8002d98: 40010800 .word 0x40010800 + +08002d9c : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 8002d9c: b580 push {r7, lr} + 8002d9e: b084 sub sp, #16 + 8002da0: af00 add r7, sp, #0 + 8002da2: 6078 str r0, [r7, #4] + uint32_t itsource = htim->Instance->DIER; + 8002da4: 687b ldr r3, [r7, #4] + 8002da6: 681b ldr r3, [r3, #0] + 8002da8: 68db ldr r3, [r3, #12] + 8002daa: 60fb str r3, [r7, #12] + uint32_t itflag = htim->Instance->SR; + 8002dac: 687b ldr r3, [r7, #4] + 8002dae: 681b ldr r3, [r3, #0] + 8002db0: 691b ldr r3, [r3, #16] + 8002db2: 60bb str r3, [r7, #8] + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + 8002db4: 68bb ldr r3, [r7, #8] + 8002db6: f003 0302 and.w r3, r3, #2 + 8002dba: 2b00 cmp r3, #0 + 8002dbc: d020 beq.n 8002e00 + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + 8002dbe: 68fb ldr r3, [r7, #12] + 8002dc0: f003 0302 and.w r3, r3, #2 + 8002dc4: 2b00 cmp r3, #0 + 8002dc6: d01b beq.n 8002e00 + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + 8002dc8: 687b ldr r3, [r7, #4] + 8002dca: 681b ldr r3, [r3, #0] + 8002dcc: f06f 0202 mvn.w r2, #2 + 8002dd0: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 8002dd2: 687b ldr r3, [r7, #4] + 8002dd4: 2201 movs r2, #1 + 8002dd6: 761a strb r2, [r3, #24] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 8002dd8: 687b ldr r3, [r7, #4] + 8002dda: 681b ldr r3, [r3, #0] + 8002ddc: 699b ldr r3, [r3, #24] + 8002dde: f003 0303 and.w r3, r3, #3 + 8002de2: 2b00 cmp r3, #0 + 8002de4: d003 beq.n 8002dee + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002de6: 6878 ldr r0, [r7, #4] + 8002de8: f000 fa36 bl 8003258 + 8002dec: e005 b.n 8002dfa + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002dee: 6878 ldr r0, [r7, #4] + 8002df0: f000 fa29 bl 8003246 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002df4: 6878 ldr r0, [r7, #4] + 8002df6: f000 fa38 bl 800326a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002dfa: 687b ldr r3, [r7, #4] + 8002dfc: 2200 movs r2, #0 + 8002dfe: 761a strb r2, [r3, #24] + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + 8002e00: 68bb ldr r3, [r7, #8] + 8002e02: f003 0304 and.w r3, r3, #4 + 8002e06: 2b00 cmp r3, #0 + 8002e08: d020 beq.n 8002e4c + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + 8002e0a: 68fb ldr r3, [r7, #12] + 8002e0c: f003 0304 and.w r3, r3, #4 + 8002e10: 2b00 cmp r3, #0 + 8002e12: d01b beq.n 8002e4c + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + 8002e14: 687b ldr r3, [r7, #4] + 8002e16: 681b ldr r3, [r3, #0] + 8002e18: f06f 0204 mvn.w r2, #4 + 8002e1c: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8002e1e: 687b ldr r3, [r7, #4] + 8002e20: 2202 movs r2, #2 + 8002e22: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8002e24: 687b ldr r3, [r7, #4] + 8002e26: 681b ldr r3, [r3, #0] + 8002e28: 699b ldr r3, [r3, #24] + 8002e2a: f403 7340 and.w r3, r3, #768 @ 0x300 + 8002e2e: 2b00 cmp r3, #0 + 8002e30: d003 beq.n 8002e3a + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002e32: 6878 ldr r0, [r7, #4] + 8002e34: f000 fa10 bl 8003258 + 8002e38: e005 b.n 8002e46 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002e3a: 6878 ldr r0, [r7, #4] + 8002e3c: f000 fa03 bl 8003246 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002e40: 6878 ldr r0, [r7, #4] + 8002e42: f000 fa12 bl 800326a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002e46: 687b ldr r3, [r7, #4] + 8002e48: 2200 movs r2, #0 + 8002e4a: 761a strb r2, [r3, #24] + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + 8002e4c: 68bb ldr r3, [r7, #8] + 8002e4e: f003 0308 and.w r3, r3, #8 + 8002e52: 2b00 cmp r3, #0 + 8002e54: d020 beq.n 8002e98 + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + 8002e56: 68fb ldr r3, [r7, #12] + 8002e58: f003 0308 and.w r3, r3, #8 + 8002e5c: 2b00 cmp r3, #0 + 8002e5e: d01b beq.n 8002e98 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + 8002e60: 687b ldr r3, [r7, #4] + 8002e62: 681b ldr r3, [r3, #0] + 8002e64: f06f 0208 mvn.w r2, #8 + 8002e68: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8002e6a: 687b ldr r3, [r7, #4] + 8002e6c: 2204 movs r2, #4 + 8002e6e: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 8002e70: 687b ldr r3, [r7, #4] + 8002e72: 681b ldr r3, [r3, #0] + 8002e74: 69db ldr r3, [r3, #28] + 8002e76: f003 0303 and.w r3, r3, #3 + 8002e7a: 2b00 cmp r3, #0 + 8002e7c: d003 beq.n 8002e86 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002e7e: 6878 ldr r0, [r7, #4] + 8002e80: f000 f9ea bl 8003258 + 8002e84: e005 b.n 8002e92 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002e86: 6878 ldr r0, [r7, #4] + 8002e88: f000 f9dd bl 8003246 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002e8c: 6878 ldr r0, [r7, #4] + 8002e8e: f000 f9ec bl 800326a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002e92: 687b ldr r3, [r7, #4] + 8002e94: 2200 movs r2, #0 + 8002e96: 761a strb r2, [r3, #24] + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + 8002e98: 68bb ldr r3, [r7, #8] + 8002e9a: f003 0310 and.w r3, r3, #16 + 8002e9e: 2b00 cmp r3, #0 + 8002ea0: d020 beq.n 8002ee4 + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + 8002ea2: 68fb ldr r3, [r7, #12] + 8002ea4: f003 0310 and.w r3, r3, #16 + 8002ea8: 2b00 cmp r3, #0 + 8002eaa: d01b beq.n 8002ee4 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + 8002eac: 687b ldr r3, [r7, #4] + 8002eae: 681b ldr r3, [r3, #0] + 8002eb0: f06f 0210 mvn.w r2, #16 + 8002eb4: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8002eb6: 687b ldr r3, [r7, #4] + 8002eb8: 2208 movs r2, #8 + 8002eba: 761a strb r2, [r3, #24] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8002ebc: 687b ldr r3, [r7, #4] + 8002ebe: 681b ldr r3, [r3, #0] + 8002ec0: 69db ldr r3, [r3, #28] + 8002ec2: f403 7340 and.w r3, r3, #768 @ 0x300 + 8002ec6: 2b00 cmp r3, #0 + 8002ec8: d003 beq.n 8002ed2 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8002eca: 6878 ldr r0, [r7, #4] + 8002ecc: f000 f9c4 bl 8003258 + 8002ed0: e005 b.n 8002ede + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8002ed2: 6878 ldr r0, [r7, #4] + 8002ed4: f000 f9b7 bl 8003246 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8002ed8: 6878 ldr r0, [r7, #4] + 8002eda: f000 f9c6 bl 800326a +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8002ede: 687b ldr r3, [r7, #4] + 8002ee0: 2200 movs r2, #0 + 8002ee2: 761a strb r2, [r3, #24] + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + 8002ee4: 68bb ldr r3, [r7, #8] + 8002ee6: f003 0301 and.w r3, r3, #1 + 8002eea: 2b00 cmp r3, #0 + 8002eec: d00c beq.n 8002f08 + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + 8002eee: 68fb ldr r3, [r7, #12] + 8002ef0: f003 0301 and.w r3, r3, #1 + 8002ef4: 2b00 cmp r3, #0 + 8002ef6: d007 beq.n 8002f08 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); + 8002ef8: 687b ldr r3, [r7, #4] + 8002efa: 681b ldr r3, [r3, #0] + 8002efc: f06f 0201 mvn.w r2, #1 + 8002f00: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 8002f02: 6878 ldr r0, [r7, #4] + 8002f04: f7fd ffec bl 8000ee0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + 8002f08: 68bb ldr r3, [r7, #8] + 8002f0a: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002f0e: 2b00 cmp r3, #0 + 8002f10: d00c beq.n 8002f2c + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + 8002f12: 68fb ldr r3, [r7, #12] + 8002f14: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002f18: 2b00 cmp r3, #0 + 8002f1a: d007 beq.n 8002f2c + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); + 8002f1c: 687b ldr r3, [r7, #4] + 8002f1e: 681b ldr r3, [r3, #0] + 8002f20: f06f 0240 mvn.w r2, #64 @ 0x40 + 8002f24: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 8002f26: 6878 ldr r0, [r7, #4] + 8002f28: f000 f9a8 bl 800327c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 8002f2c: bf00 nop + 8002f2e: 3710 adds r7, #16 + 8002f30: 46bd mov sp, r7 + 8002f32: bd80 pop {r7, pc} + +08002f34 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8002f34: b580 push {r7, lr} + 8002f36: b086 sub sp, #24 + 8002f38: af00 add r7, sp, #0 + 8002f3a: 60f8 str r0, [r7, #12] + 8002f3c: 60b9 str r1, [r7, #8] + 8002f3e: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002f40: 2300 movs r3, #0 + 8002f42: 75fb strb r3, [r7, #23] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8002f44: 68fb ldr r3, [r7, #12] + 8002f46: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 8002f4a: 2b01 cmp r3, #1 + 8002f4c: d101 bne.n 8002f52 + 8002f4e: 2302 movs r3, #2 + 8002f50: e0ae b.n 80030b0 + 8002f52: 68fb ldr r3, [r7, #12] + 8002f54: 2201 movs r2, #1 + 8002f56: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + switch (Channel) + 8002f5a: 687b ldr r3, [r7, #4] + 8002f5c: 2b0c cmp r3, #12 + 8002f5e: f200 809f bhi.w 80030a0 + 8002f62: a201 add r2, pc, #4 @ (adr r2, 8002f68 ) + 8002f64: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002f68: 08002f9d .word 0x08002f9d + 8002f6c: 080030a1 .word 0x080030a1 + 8002f70: 080030a1 .word 0x080030a1 + 8002f74: 080030a1 .word 0x080030a1 + 8002f78: 08002fdd .word 0x08002fdd + 8002f7c: 080030a1 .word 0x080030a1 + 8002f80: 080030a1 .word 0x080030a1 + 8002f84: 080030a1 .word 0x080030a1 + 8002f88: 0800301f .word 0x0800301f + 8002f8c: 080030a1 .word 0x080030a1 + 8002f90: 080030a1 .word 0x080030a1 + 8002f94: 080030a1 .word 0x080030a1 + 8002f98: 0800305f .word 0x0800305f + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 8002f9c: 68fb ldr r3, [r7, #12] + 8002f9e: 681b ldr r3, [r3, #0] + 8002fa0: 68b9 ldr r1, [r7, #8] + 8002fa2: 4618 mov r0, r3 + 8002fa4: f000 f9ea bl 800337c + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 8002fa8: 68fb ldr r3, [r7, #12] + 8002faa: 681b ldr r3, [r3, #0] + 8002fac: 699a ldr r2, [r3, #24] + 8002fae: 68fb ldr r3, [r7, #12] + 8002fb0: 681b ldr r3, [r3, #0] + 8002fb2: f042 0208 orr.w r2, r2, #8 + 8002fb6: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 8002fb8: 68fb ldr r3, [r7, #12] + 8002fba: 681b ldr r3, [r3, #0] + 8002fbc: 699a ldr r2, [r3, #24] + 8002fbe: 68fb ldr r3, [r7, #12] + 8002fc0: 681b ldr r3, [r3, #0] + 8002fc2: f022 0204 bic.w r2, r2, #4 + 8002fc6: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 8002fc8: 68fb ldr r3, [r7, #12] + 8002fca: 681b ldr r3, [r3, #0] + 8002fcc: 6999 ldr r1, [r3, #24] + 8002fce: 68bb ldr r3, [r7, #8] + 8002fd0: 68da ldr r2, [r3, #12] + 8002fd2: 68fb ldr r3, [r7, #12] + 8002fd4: 681b ldr r3, [r3, #0] + 8002fd6: 430a orrs r2, r1 + 8002fd8: 619a str r2, [r3, #24] + break; + 8002fda: e064 b.n 80030a6 + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 8002fdc: 68fb ldr r3, [r7, #12] + 8002fde: 681b ldr r3, [r3, #0] + 8002fe0: 68b9 ldr r1, [r7, #8] + 8002fe2: 4618 mov r0, r3 + 8002fe4: f000 fa06 bl 80033f4 + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 8002fe8: 68fb ldr r3, [r7, #12] + 8002fea: 681b ldr r3, [r3, #0] + 8002fec: 699a ldr r2, [r3, #24] + 8002fee: 68fb ldr r3, [r7, #12] + 8002ff0: 681b ldr r3, [r3, #0] + 8002ff2: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8002ff6: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 8002ff8: 68fb ldr r3, [r7, #12] + 8002ffa: 681b ldr r3, [r3, #0] + 8002ffc: 699a ldr r2, [r3, #24] + 8002ffe: 68fb ldr r3, [r7, #12] + 8003000: 681b ldr r3, [r3, #0] + 8003002: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8003006: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 8003008: 68fb ldr r3, [r7, #12] + 800300a: 681b ldr r3, [r3, #0] + 800300c: 6999 ldr r1, [r3, #24] + 800300e: 68bb ldr r3, [r7, #8] + 8003010: 68db ldr r3, [r3, #12] + 8003012: 021a lsls r2, r3, #8 + 8003014: 68fb ldr r3, [r7, #12] + 8003016: 681b ldr r3, [r3, #0] + 8003018: 430a orrs r2, r1 + 800301a: 619a str r2, [r3, #24] + break; + 800301c: e043 b.n 80030a6 + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 800301e: 68fb ldr r3, [r7, #12] + 8003020: 681b ldr r3, [r3, #0] + 8003022: 68b9 ldr r1, [r7, #8] + 8003024: 4618 mov r0, r3 + 8003026: f000 fa23 bl 8003470 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 800302a: 68fb ldr r3, [r7, #12] + 800302c: 681b ldr r3, [r3, #0] + 800302e: 69da ldr r2, [r3, #28] + 8003030: 68fb ldr r3, [r7, #12] + 8003032: 681b ldr r3, [r3, #0] + 8003034: f042 0208 orr.w r2, r2, #8 + 8003038: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 800303a: 68fb ldr r3, [r7, #12] + 800303c: 681b ldr r3, [r3, #0] + 800303e: 69da ldr r2, [r3, #28] + 8003040: 68fb ldr r3, [r7, #12] + 8003042: 681b ldr r3, [r3, #0] + 8003044: f022 0204 bic.w r2, r2, #4 + 8003048: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 800304a: 68fb ldr r3, [r7, #12] + 800304c: 681b ldr r3, [r3, #0] + 800304e: 69d9 ldr r1, [r3, #28] + 8003050: 68bb ldr r3, [r7, #8] + 8003052: 68da ldr r2, [r3, #12] + 8003054: 68fb ldr r3, [r7, #12] + 8003056: 681b ldr r3, [r3, #0] + 8003058: 430a orrs r2, r1 + 800305a: 61da str r2, [r3, #28] + break; + 800305c: e023 b.n 80030a6 + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 800305e: 68fb ldr r3, [r7, #12] + 8003060: 681b ldr r3, [r3, #0] + 8003062: 68b9 ldr r1, [r7, #8] + 8003064: 4618 mov r0, r3 + 8003066: f000 fa40 bl 80034ea + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 800306a: 68fb ldr r3, [r7, #12] + 800306c: 681b ldr r3, [r3, #0] + 800306e: 69da ldr r2, [r3, #28] + 8003070: 68fb ldr r3, [r7, #12] + 8003072: 681b ldr r3, [r3, #0] + 8003074: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8003078: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 800307a: 68fb ldr r3, [r7, #12] + 800307c: 681b ldr r3, [r3, #0] + 800307e: 69da ldr r2, [r3, #28] + 8003080: 68fb ldr r3, [r7, #12] + 8003082: 681b ldr r3, [r3, #0] + 8003084: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8003088: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 800308a: 68fb ldr r3, [r7, #12] + 800308c: 681b ldr r3, [r3, #0] + 800308e: 69d9 ldr r1, [r3, #28] + 8003090: 68bb ldr r3, [r7, #8] + 8003092: 68db ldr r3, [r3, #12] + 8003094: 021a lsls r2, r3, #8 + 8003096: 68fb ldr r3, [r7, #12] + 8003098: 681b ldr r3, [r3, #0] + 800309a: 430a orrs r2, r1 + 800309c: 61da str r2, [r3, #28] + break; + 800309e: e002 b.n 80030a6 + } + + default: + status = HAL_ERROR; + 80030a0: 2301 movs r3, #1 + 80030a2: 75fb strb r3, [r7, #23] + break; + 80030a4: bf00 nop + } + + __HAL_UNLOCK(htim); + 80030a6: 68fb ldr r3, [r7, #12] + 80030a8: 2200 movs r2, #0 + 80030aa: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 80030ae: 7dfb ldrb r3, [r7, #23] +} + 80030b0: 4618 mov r0, r3 + 80030b2: 3718 adds r7, #24 + 80030b4: 46bd mov sp, r7 + 80030b6: bd80 pop {r7, pc} + +080030b8 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 80030b8: b580 push {r7, lr} + 80030ba: b084 sub sp, #16 + 80030bc: af00 add r7, sp, #0 + 80030be: 6078 str r0, [r7, #4] + 80030c0: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 80030c2: 2300 movs r3, #0 + 80030c4: 73fb strb r3, [r7, #15] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 80030c6: 687b ldr r3, [r7, #4] + 80030c8: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 80030cc: 2b01 cmp r3, #1 + 80030ce: d101 bne.n 80030d4 + 80030d0: 2302 movs r3, #2 + 80030d2: e0b4 b.n 800323e + 80030d4: 687b ldr r3, [r7, #4] + 80030d6: 2201 movs r2, #1 + 80030d8: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + htim->State = HAL_TIM_STATE_BUSY; + 80030dc: 687b ldr r3, [r7, #4] + 80030de: 2202 movs r2, #2 + 80030e0: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 80030e4: 687b ldr r3, [r7, #4] + 80030e6: 681b ldr r3, [r3, #0] + 80030e8: 689b ldr r3, [r3, #8] + 80030ea: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 80030ec: 68bb ldr r3, [r7, #8] + 80030ee: f023 0377 bic.w r3, r3, #119 @ 0x77 + 80030f2: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 80030f4: 68bb ldr r3, [r7, #8] + 80030f6: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 80030fa: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 80030fc: 687b ldr r3, [r7, #4] + 80030fe: 681b ldr r3, [r3, #0] + 8003100: 68ba ldr r2, [r7, #8] + 8003102: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8003104: 683b ldr r3, [r7, #0] + 8003106: 681b ldr r3, [r3, #0] + 8003108: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 800310c: d03e beq.n 800318c + 800310e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8003112: f200 8087 bhi.w 8003224 + 8003116: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800311a: f000 8086 beq.w 800322a + 800311e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8003122: d87f bhi.n 8003224 + 8003124: 2b70 cmp r3, #112 @ 0x70 + 8003126: d01a beq.n 800315e + 8003128: 2b70 cmp r3, #112 @ 0x70 + 800312a: d87b bhi.n 8003224 + 800312c: 2b60 cmp r3, #96 @ 0x60 + 800312e: d050 beq.n 80031d2 + 8003130: 2b60 cmp r3, #96 @ 0x60 + 8003132: d877 bhi.n 8003224 + 8003134: 2b50 cmp r3, #80 @ 0x50 + 8003136: d03c beq.n 80031b2 + 8003138: 2b50 cmp r3, #80 @ 0x50 + 800313a: d873 bhi.n 8003224 + 800313c: 2b40 cmp r3, #64 @ 0x40 + 800313e: d058 beq.n 80031f2 + 8003140: 2b40 cmp r3, #64 @ 0x40 + 8003142: d86f bhi.n 8003224 + 8003144: 2b30 cmp r3, #48 @ 0x30 + 8003146: d064 beq.n 8003212 + 8003148: 2b30 cmp r3, #48 @ 0x30 + 800314a: d86b bhi.n 8003224 + 800314c: 2b20 cmp r3, #32 + 800314e: d060 beq.n 8003212 + 8003150: 2b20 cmp r3, #32 + 8003152: d867 bhi.n 8003224 + 8003154: 2b00 cmp r3, #0 + 8003156: d05c beq.n 8003212 + 8003158: 2b10 cmp r3, #16 + 800315a: d05a beq.n 8003212 + 800315c: e062 b.n 8003224 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 800315e: 687b ldr r3, [r7, #4] + 8003160: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8003162: 683b ldr r3, [r7, #0] + 8003164: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8003166: 683b ldr r3, [r7, #0] + 8003168: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 800316a: 683b ldr r3, [r7, #0] + 800316c: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 800316e: f000 fa71 bl 8003654 + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 8003172: 687b ldr r3, [r7, #4] + 8003174: 681b ldr r3, [r3, #0] + 8003176: 689b ldr r3, [r3, #8] + 8003178: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 800317a: 68bb ldr r3, [r7, #8] + 800317c: f043 0377 orr.w r3, r3, #119 @ 0x77 + 8003180: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8003182: 687b ldr r3, [r7, #4] + 8003184: 681b ldr r3, [r3, #0] + 8003186: 68ba ldr r2, [r7, #8] + 8003188: 609a str r2, [r3, #8] + break; + 800318a: e04f b.n 800322c + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 800318c: 687b ldr r3, [r7, #4] + 800318e: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8003190: 683b ldr r3, [r7, #0] + 8003192: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8003194: 683b ldr r3, [r7, #0] + 8003196: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 8003198: 683b ldr r3, [r7, #0] + 800319a: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 800319c: f000 fa5a bl 8003654 + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 80031a0: 687b ldr r3, [r7, #4] + 80031a2: 681b ldr r3, [r3, #0] + 80031a4: 689a ldr r2, [r3, #8] + 80031a6: 687b ldr r3, [r7, #4] + 80031a8: 681b ldr r3, [r3, #0] + 80031aa: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 80031ae: 609a str r2, [r3, #8] + break; + 80031b0: e03c b.n 800322c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 80031b2: 687b ldr r3, [r7, #4] + 80031b4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80031b6: 683b ldr r3, [r7, #0] + 80031b8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80031ba: 683b ldr r3, [r7, #0] + 80031bc: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 80031be: 461a mov r2, r3 + 80031c0: f000 f9d1 bl 8003566 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 80031c4: 687b ldr r3, [r7, #4] + 80031c6: 681b ldr r3, [r3, #0] + 80031c8: 2150 movs r1, #80 @ 0x50 + 80031ca: 4618 mov r0, r3 + 80031cc: f000 fa28 bl 8003620 + break; + 80031d0: e02c b.n 800322c + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 80031d2: 687b ldr r3, [r7, #4] + 80031d4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80031d6: 683b ldr r3, [r7, #0] + 80031d8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80031da: 683b ldr r3, [r7, #0] + 80031dc: 68db ldr r3, [r3, #12] + TIM_TI2_ConfigInputStage(htim->Instance, + 80031de: 461a mov r2, r3 + 80031e0: f000 f9ef bl 80035c2 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 80031e4: 687b ldr r3, [r7, #4] + 80031e6: 681b ldr r3, [r3, #0] + 80031e8: 2160 movs r1, #96 @ 0x60 + 80031ea: 4618 mov r0, r3 + 80031ec: f000 fa18 bl 8003620 + break; + 80031f0: e01c b.n 800322c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 80031f2: 687b ldr r3, [r7, #4] + 80031f4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80031f6: 683b ldr r3, [r7, #0] + 80031f8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80031fa: 683b ldr r3, [r7, #0] + 80031fc: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 80031fe: 461a mov r2, r3 + 8003200: f000 f9b1 bl 8003566 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 8003204: 687b ldr r3, [r7, #4] + 8003206: 681b ldr r3, [r3, #0] + 8003208: 2140 movs r1, #64 @ 0x40 + 800320a: 4618 mov r0, r3 + 800320c: f000 fa08 bl 8003620 + break; + 8003210: e00c b.n 800322c + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 8003212: 687b ldr r3, [r7, #4] + 8003214: 681a ldr r2, [r3, #0] + 8003216: 683b ldr r3, [r7, #0] + 8003218: 681b ldr r3, [r3, #0] + 800321a: 4619 mov r1, r3 + 800321c: 4610 mov r0, r2 + 800321e: f000 f9ff bl 8003620 + break; + 8003222: e003 b.n 800322c + } + + default: + status = HAL_ERROR; + 8003224: 2301 movs r3, #1 + 8003226: 73fb strb r3, [r7, #15] + break; + 8003228: e000 b.n 800322c + break; + 800322a: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 800322c: 687b ldr r3, [r7, #4] + 800322e: 2201 movs r2, #1 + 8003230: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8003234: 687b ldr r3, [r7, #4] + 8003236: 2200 movs r2, #0 + 8003238: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 800323c: 7bfb ldrb r3, [r7, #15] +} + 800323e: 4618 mov r0, r3 + 8003240: 3710 adds r7, #16 + 8003242: 46bd mov sp, r7 + 8003244: bd80 pop {r7, pc} + +08003246 : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8003246: b480 push {r7} + 8003248: b083 sub sp, #12 + 800324a: af00 add r7, sp, #0 + 800324c: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 800324e: bf00 nop + 8003250: 370c adds r7, #12 + 8003252: 46bd mov sp, r7 + 8003254: bc80 pop {r7} + 8003256: 4770 bx lr + +08003258 : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 8003258: b480 push {r7} + 800325a: b083 sub sp, #12 + 800325c: af00 add r7, sp, #0 + 800325e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8003260: bf00 nop + 8003262: 370c adds r7, #12 + 8003264: 46bd mov sp, r7 + 8003266: bc80 pop {r7} + 8003268: 4770 bx lr + +0800326a : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 800326a: b480 push {r7} + 800326c: b083 sub sp, #12 + 800326e: af00 add r7, sp, #0 + 8003270: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 8003272: bf00 nop + 8003274: 370c adds r7, #12 + 8003276: 46bd mov sp, r7 + 8003278: bc80 pop {r7} + 800327a: 4770 bx lr + +0800327c : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 800327c: b480 push {r7} + 800327e: b083 sub sp, #12 + 8003280: af00 add r7, sp, #0 + 8003282: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 8003284: bf00 nop + 8003286: 370c adds r7, #12 + 8003288: 46bd mov sp, r7 + 800328a: bc80 pop {r7} + 800328c: 4770 bx lr + ... + +08003290 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 8003290: b480 push {r7} + 8003292: b085 sub sp, #20 + 8003294: af00 add r7, sp, #0 + 8003296: 6078 str r0, [r7, #4] + 8003298: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 800329a: 687b ldr r3, [r7, #4] + 800329c: 681b ldr r3, [r3, #0] + 800329e: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 80032a0: 687b ldr r3, [r7, #4] + 80032a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80032a6: d00f beq.n 80032c8 + 80032a8: 687b ldr r3, [r7, #4] + 80032aa: 4a2e ldr r2, [pc, #184] @ (8003364 ) + 80032ac: 4293 cmp r3, r2 + 80032ae: d00b beq.n 80032c8 + 80032b0: 687b ldr r3, [r7, #4] + 80032b2: 4a2d ldr r2, [pc, #180] @ (8003368 ) + 80032b4: 4293 cmp r3, r2 + 80032b6: d007 beq.n 80032c8 + 80032b8: 687b ldr r3, [r7, #4] + 80032ba: 4a2c ldr r2, [pc, #176] @ (800336c ) + 80032bc: 4293 cmp r3, r2 + 80032be: d003 beq.n 80032c8 + 80032c0: 687b ldr r3, [r7, #4] + 80032c2: 4a2b ldr r2, [pc, #172] @ (8003370 ) + 80032c4: 4293 cmp r3, r2 + 80032c6: d108 bne.n 80032da + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 80032c8: 68fb ldr r3, [r7, #12] + 80032ca: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80032ce: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 80032d0: 683b ldr r3, [r7, #0] + 80032d2: 685b ldr r3, [r3, #4] + 80032d4: 68fa ldr r2, [r7, #12] + 80032d6: 4313 orrs r3, r2 + 80032d8: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 80032da: 687b ldr r3, [r7, #4] + 80032dc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80032e0: d017 beq.n 8003312 + 80032e2: 687b ldr r3, [r7, #4] + 80032e4: 4a1f ldr r2, [pc, #124] @ (8003364 ) + 80032e6: 4293 cmp r3, r2 + 80032e8: d013 beq.n 8003312 + 80032ea: 687b ldr r3, [r7, #4] + 80032ec: 4a1e ldr r2, [pc, #120] @ (8003368 ) + 80032ee: 4293 cmp r3, r2 + 80032f0: d00f beq.n 8003312 + 80032f2: 687b ldr r3, [r7, #4] + 80032f4: 4a1d ldr r2, [pc, #116] @ (800336c ) + 80032f6: 4293 cmp r3, r2 + 80032f8: d00b beq.n 8003312 + 80032fa: 687b ldr r3, [r7, #4] + 80032fc: 4a1c ldr r2, [pc, #112] @ (8003370 ) + 80032fe: 4293 cmp r3, r2 + 8003300: d007 beq.n 8003312 + 8003302: 687b ldr r3, [r7, #4] + 8003304: 4a1b ldr r2, [pc, #108] @ (8003374 ) + 8003306: 4293 cmp r3, r2 + 8003308: d003 beq.n 8003312 + 800330a: 687b ldr r3, [r7, #4] + 800330c: 4a1a ldr r2, [pc, #104] @ (8003378 ) + 800330e: 4293 cmp r3, r2 + 8003310: d108 bne.n 8003324 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 8003312: 68fb ldr r3, [r7, #12] + 8003314: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8003318: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 800331a: 683b ldr r3, [r7, #0] + 800331c: 68db ldr r3, [r3, #12] + 800331e: 68fa ldr r2, [r7, #12] + 8003320: 4313 orrs r3, r2 + 8003322: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 8003324: 68fb ldr r3, [r7, #12] + 8003326: f023 0280 bic.w r2, r3, #128 @ 0x80 + 800332a: 683b ldr r3, [r7, #0] + 800332c: 691b ldr r3, [r3, #16] + 800332e: 4313 orrs r3, r2 + 8003330: 60fb str r3, [r7, #12] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8003332: 683b ldr r3, [r7, #0] + 8003334: 689a ldr r2, [r3, #8] + 8003336: 687b ldr r3, [r7, #4] + 8003338: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 800333a: 683b ldr r3, [r7, #0] + 800333c: 681a ldr r2, [r3, #0] + 800333e: 687b ldr r3, [r7, #4] + 8003340: 629a str r2, [r3, #40] @ 0x28 + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + 8003342: 687b ldr r3, [r7, #4] + 8003344: 681b ldr r3, [r3, #0] + 8003346: f043 0204 orr.w r2, r3, #4 + 800334a: 687b ldr r3, [r7, #4] + 800334c: 601a str r2, [r3, #0] + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 800334e: 687b ldr r3, [r7, #4] + 8003350: 2201 movs r2, #1 + 8003352: 615a str r2, [r3, #20] + + TIMx->CR1 = tmpcr1; + 8003354: 687b ldr r3, [r7, #4] + 8003356: 68fa ldr r2, [r7, #12] + 8003358: 601a str r2, [r3, #0] +} + 800335a: bf00 nop + 800335c: 3714 adds r7, #20 + 800335e: 46bd mov sp, r7 + 8003360: bc80 pop {r7} + 8003362: 4770 bx lr + 8003364: 40000400 .word 0x40000400 + 8003368: 40000800 .word 0x40000800 + 800336c: 40000c00 .word 0x40000c00 + 8003370: 40010800 .word 0x40010800 + 8003374: 40010c00 .word 0x40010c00 + 8003378: 40011000 .word 0x40011000 + +0800337c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 800337c: b480 push {r7} + 800337e: b087 sub sp, #28 + 8003380: af00 add r7, sp, #0 + 8003382: 6078 str r0, [r7, #4] + 8003384: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8003386: 687b ldr r3, [r7, #4] + 8003388: 6a1b ldr r3, [r3, #32] + 800338a: 617b str r3, [r7, #20] + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 800338c: 687b ldr r3, [r7, #4] + 800338e: 6a1b ldr r3, [r3, #32] + 8003390: f023 0201 bic.w r2, r3, #1 + 8003394: 687b ldr r3, [r7, #4] + 8003396: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003398: 687b ldr r3, [r7, #4] + 800339a: 685b ldr r3, [r3, #4] + 800339c: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 800339e: 687b ldr r3, [r7, #4] + 80033a0: 699b ldr r3, [r3, #24] + 80033a2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 80033a4: 68fb ldr r3, [r7, #12] + 80033a6: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80033aa: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 80033ac: 68fb ldr r3, [r7, #12] + 80033ae: f023 0303 bic.w r3, r3, #3 + 80033b2: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 80033b4: 683b ldr r3, [r7, #0] + 80033b6: 681b ldr r3, [r3, #0] + 80033b8: 68fa ldr r2, [r7, #12] + 80033ba: 4313 orrs r3, r2 + 80033bc: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 80033be: 697b ldr r3, [r7, #20] + 80033c0: f023 0302 bic.w r3, r3, #2 + 80033c4: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 80033c6: 683b ldr r3, [r7, #0] + 80033c8: 689b ldr r3, [r3, #8] + 80033ca: 697a ldr r2, [r7, #20] + 80033cc: 4313 orrs r3, r2 + 80033ce: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80033d0: 687b ldr r3, [r7, #4] + 80033d2: 693a ldr r2, [r7, #16] + 80033d4: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 80033d6: 687b ldr r3, [r7, #4] + 80033d8: 68fa ldr r2, [r7, #12] + 80033da: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 80033dc: 683b ldr r3, [r7, #0] + 80033de: 685a ldr r2, [r3, #4] + 80033e0: 687b ldr r3, [r7, #4] + 80033e2: 635a str r2, [r3, #52] @ 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80033e4: 687b ldr r3, [r7, #4] + 80033e6: 697a ldr r2, [r7, #20] + 80033e8: 621a str r2, [r3, #32] +} + 80033ea: bf00 nop + 80033ec: 371c adds r7, #28 + 80033ee: 46bd mov sp, r7 + 80033f0: bc80 pop {r7} + 80033f2: 4770 bx lr + +080033f4 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 80033f4: b480 push {r7} + 80033f6: b087 sub sp, #28 + 80033f8: af00 add r7, sp, #0 + 80033fa: 6078 str r0, [r7, #4] + 80033fc: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80033fe: 687b ldr r3, [r7, #4] + 8003400: 6a1b ldr r3, [r3, #32] + 8003402: 617b str r3, [r7, #20] + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8003404: 687b ldr r3, [r7, #4] + 8003406: 6a1b ldr r3, [r3, #32] + 8003408: f023 0210 bic.w r2, r3, #16 + 800340c: 687b ldr r3, [r7, #4] + 800340e: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003410: 687b ldr r3, [r7, #4] + 8003412: 685b ldr r3, [r3, #4] + 8003414: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8003416: 687b ldr r3, [r7, #4] + 8003418: 699b ldr r3, [r3, #24] + 800341a: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 800341c: 68fb ldr r3, [r7, #12] + 800341e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8003422: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8003424: 68fb ldr r3, [r7, #12] + 8003426: f423 7340 bic.w r3, r3, #768 @ 0x300 + 800342a: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 800342c: 683b ldr r3, [r7, #0] + 800342e: 681b ldr r3, [r3, #0] + 8003430: 021b lsls r3, r3, #8 + 8003432: 68fa ldr r2, [r7, #12] + 8003434: 4313 orrs r3, r2 + 8003436: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8003438: 697b ldr r3, [r7, #20] + 800343a: f023 0320 bic.w r3, r3, #32 + 800343e: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 8003440: 683b ldr r3, [r7, #0] + 8003442: 689b ldr r3, [r3, #8] + 8003444: 011b lsls r3, r3, #4 + 8003446: 697a ldr r2, [r7, #20] + 8003448: 4313 orrs r3, r2 + 800344a: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800344c: 687b ldr r3, [r7, #4] + 800344e: 693a ldr r2, [r7, #16] + 8003450: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8003452: 687b ldr r3, [r7, #4] + 8003454: 68fa ldr r2, [r7, #12] + 8003456: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8003458: 683b ldr r3, [r7, #0] + 800345a: 685a ldr r2, [r3, #4] + 800345c: 687b ldr r3, [r7, #4] + 800345e: 639a str r2, [r3, #56] @ 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003460: 687b ldr r3, [r7, #4] + 8003462: 697a ldr r2, [r7, #20] + 8003464: 621a str r2, [r3, #32] +} + 8003466: bf00 nop + 8003468: 371c adds r7, #28 + 800346a: 46bd mov sp, r7 + 800346c: bc80 pop {r7} + 800346e: 4770 bx lr + +08003470 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8003470: b480 push {r7} + 8003472: b087 sub sp, #28 + 8003474: af00 add r7, sp, #0 + 8003476: 6078 str r0, [r7, #4] + 8003478: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 800347a: 687b ldr r3, [r7, #4] + 800347c: 6a1b ldr r3, [r3, #32] + 800347e: 617b str r3, [r7, #20] + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8003480: 687b ldr r3, [r7, #4] + 8003482: 6a1b ldr r3, [r3, #32] + 8003484: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8003488: 687b ldr r3, [r7, #4] + 800348a: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 800348c: 687b ldr r3, [r7, #4] + 800348e: 685b ldr r3, [r3, #4] + 8003490: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8003492: 687b ldr r3, [r7, #4] + 8003494: 69db ldr r3, [r3, #28] + 8003496: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8003498: 68fb ldr r3, [r7, #12] + 800349a: f023 0370 bic.w r3, r3, #112 @ 0x70 + 800349e: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 80034a0: 68fb ldr r3, [r7, #12] + 80034a2: f023 0303 bic.w r3, r3, #3 + 80034a6: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 80034a8: 683b ldr r3, [r7, #0] + 80034aa: 681b ldr r3, [r3, #0] + 80034ac: 68fa ldr r2, [r7, #12] + 80034ae: 4313 orrs r3, r2 + 80034b0: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 80034b2: 697b ldr r3, [r7, #20] + 80034b4: f423 7300 bic.w r3, r3, #512 @ 0x200 + 80034b8: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 80034ba: 683b ldr r3, [r7, #0] + 80034bc: 689b ldr r3, [r3, #8] + 80034be: 021b lsls r3, r3, #8 + 80034c0: 697a ldr r2, [r7, #20] + 80034c2: 4313 orrs r3, r2 + 80034c4: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80034c6: 687b ldr r3, [r7, #4] + 80034c8: 693a ldr r2, [r7, #16] + 80034ca: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 80034cc: 687b ldr r3, [r7, #4] + 80034ce: 68fa ldr r2, [r7, #12] + 80034d0: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 80034d2: 683b ldr r3, [r7, #0] + 80034d4: 685a ldr r2, [r3, #4] + 80034d6: 687b ldr r3, [r7, #4] + 80034d8: 63da str r2, [r3, #60] @ 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80034da: 687b ldr r3, [r7, #4] + 80034dc: 697a ldr r2, [r7, #20] + 80034de: 621a str r2, [r3, #32] +} + 80034e0: bf00 nop + 80034e2: 371c adds r7, #28 + 80034e4: 46bd mov sp, r7 + 80034e6: bc80 pop {r7} + 80034e8: 4770 bx lr + +080034ea : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 80034ea: b480 push {r7} + 80034ec: b087 sub sp, #28 + 80034ee: af00 add r7, sp, #0 + 80034f0: 6078 str r0, [r7, #4] + 80034f2: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80034f4: 687b ldr r3, [r7, #4] + 80034f6: 6a1b ldr r3, [r3, #32] + 80034f8: 617b str r3, [r7, #20] + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 80034fa: 687b ldr r3, [r7, #4] + 80034fc: 6a1b ldr r3, [r3, #32] + 80034fe: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8003502: 687b ldr r3, [r7, #4] + 8003504: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8003506: 687b ldr r3, [r7, #4] + 8003508: 685b ldr r3, [r3, #4] + 800350a: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 800350c: 687b ldr r3, [r7, #4] + 800350e: 69db ldr r3, [r3, #28] + 8003510: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8003512: 68fb ldr r3, [r7, #12] + 8003514: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8003518: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 800351a: 68fb ldr r3, [r7, #12] + 800351c: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8003520: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8003522: 683b ldr r3, [r7, #0] + 8003524: 681b ldr r3, [r3, #0] + 8003526: 021b lsls r3, r3, #8 + 8003528: 68fa ldr r2, [r7, #12] + 800352a: 4313 orrs r3, r2 + 800352c: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 800352e: 697b ldr r3, [r7, #20] + 8003530: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 8003534: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8003536: 683b ldr r3, [r7, #0] + 8003538: 689b ldr r3, [r3, #8] + 800353a: 031b lsls r3, r3, #12 + 800353c: 697a ldr r2, [r7, #20] + 800353e: 4313 orrs r3, r2 + 8003540: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8003542: 687b ldr r3, [r7, #4] + 8003544: 693a ldr r2, [r7, #16] + 8003546: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8003548: 687b ldr r3, [r7, #4] + 800354a: 68fa ldr r2, [r7, #12] + 800354c: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 800354e: 683b ldr r3, [r7, #0] + 8003550: 685a ldr r2, [r3, #4] + 8003552: 687b ldr r3, [r7, #4] + 8003554: 641a str r2, [r3, #64] @ 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8003556: 687b ldr r3, [r7, #4] + 8003558: 697a ldr r2, [r7, #20] + 800355a: 621a str r2, [r3, #32] +} + 800355c: bf00 nop + 800355e: 371c adds r7, #28 + 8003560: 46bd mov sp, r7 + 8003562: bc80 pop {r7} + 8003564: 4770 bx lr + +08003566 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8003566: b480 push {r7} + 8003568: b087 sub sp, #28 + 800356a: af00 add r7, sp, #0 + 800356c: 60f8 str r0, [r7, #12] + 800356e: 60b9 str r1, [r7, #8] + 8003570: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8003572: 68fb ldr r3, [r7, #12] + 8003574: 6a1b ldr r3, [r3, #32] + 8003576: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 8003578: 68fb ldr r3, [r7, #12] + 800357a: 6a1b ldr r3, [r3, #32] + 800357c: f023 0201 bic.w r2, r3, #1 + 8003580: 68fb ldr r3, [r7, #12] + 8003582: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8003584: 68fb ldr r3, [r7, #12] + 8003586: 699b ldr r3, [r3, #24] + 8003588: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 800358a: 693b ldr r3, [r7, #16] + 800358c: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8003590: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8003592: 687b ldr r3, [r7, #4] + 8003594: 011b lsls r3, r3, #4 + 8003596: 693a ldr r2, [r7, #16] + 8003598: 4313 orrs r3, r2 + 800359a: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 800359c: 697b ldr r3, [r7, #20] + 800359e: f023 030a bic.w r3, r3, #10 + 80035a2: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 80035a4: 697a ldr r2, [r7, #20] + 80035a6: 68bb ldr r3, [r7, #8] + 80035a8: 4313 orrs r3, r2 + 80035aa: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 80035ac: 68fb ldr r3, [r7, #12] + 80035ae: 693a ldr r2, [r7, #16] + 80035b0: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 80035b2: 68fb ldr r3, [r7, #12] + 80035b4: 697a ldr r2, [r7, #20] + 80035b6: 621a str r2, [r3, #32] +} + 80035b8: bf00 nop + 80035ba: 371c adds r7, #28 + 80035bc: 46bd mov sp, r7 + 80035be: bc80 pop {r7} + 80035c0: 4770 bx lr + +080035c2 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 80035c2: b480 push {r7} + 80035c4: b087 sub sp, #28 + 80035c6: af00 add r7, sp, #0 + 80035c8: 60f8 str r0, [r7, #12] + 80035ca: 60b9 str r1, [r7, #8] + 80035cc: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + 80035ce: 68fb ldr r3, [r7, #12] + 80035d0: 6a1b ldr r3, [r3, #32] + 80035d2: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC2E; + 80035d4: 68fb ldr r3, [r7, #12] + 80035d6: 6a1b ldr r3, [r3, #32] + 80035d8: f023 0210 bic.w r2, r3, #16 + 80035dc: 68fb ldr r3, [r7, #12] + 80035de: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 80035e0: 68fb ldr r3, [r7, #12] + 80035e2: 699b ldr r3, [r3, #24] + 80035e4: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 80035e6: 693b ldr r3, [r7, #16] + 80035e8: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 80035ec: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 12U); + 80035ee: 687b ldr r3, [r7, #4] + 80035f0: 031b lsls r3, r3, #12 + 80035f2: 693a ldr r2, [r7, #16] + 80035f4: 4313 orrs r3, r2 + 80035f6: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 80035f8: 697b ldr r3, [r7, #20] + 80035fa: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 80035fe: 617b str r3, [r7, #20] + tmpccer |= (TIM_ICPolarity << 4U); + 8003600: 68bb ldr r3, [r7, #8] + 8003602: 011b lsls r3, r3, #4 + 8003604: 697a ldr r2, [r7, #20] + 8003606: 4313 orrs r3, r2 + 8003608: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 800360a: 68fb ldr r3, [r7, #12] + 800360c: 693a ldr r2, [r7, #16] + 800360e: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8003610: 68fb ldr r3, [r7, #12] + 8003612: 697a ldr r2, [r7, #20] + 8003614: 621a str r2, [r3, #32] +} + 8003616: bf00 nop + 8003618: 371c adds r7, #28 + 800361a: 46bd mov sp, r7 + 800361c: bc80 pop {r7} + 800361e: 4770 bx lr + +08003620 : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 8003620: b480 push {r7} + 8003622: b085 sub sp, #20 + 8003624: af00 add r7, sp, #0 + 8003626: 6078 str r0, [r7, #4] + 8003628: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 800362a: 687b ldr r3, [r7, #4] + 800362c: 689b ldr r3, [r3, #8] + 800362e: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8003630: 68fb ldr r3, [r7, #12] + 8003632: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8003636: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8003638: 683a ldr r2, [r7, #0] + 800363a: 68fb ldr r3, [r7, #12] + 800363c: 4313 orrs r3, r2 + 800363e: f043 0307 orr.w r3, r3, #7 + 8003642: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8003644: 687b ldr r3, [r7, #4] + 8003646: 68fa ldr r2, [r7, #12] + 8003648: 609a str r2, [r3, #8] +} + 800364a: bf00 nop + 800364c: 3714 adds r7, #20 + 800364e: 46bd mov sp, r7 + 8003650: bc80 pop {r7} + 8003652: 4770 bx lr + +08003654 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8003654: b480 push {r7} + 8003656: b087 sub sp, #28 + 8003658: af00 add r7, sp, #0 + 800365a: 60f8 str r0, [r7, #12] + 800365c: 60b9 str r1, [r7, #8] + 800365e: 607a str r2, [r7, #4] + 8003660: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 8003662: 68fb ldr r3, [r7, #12] + 8003664: 689b ldr r3, [r3, #8] + 8003666: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8003668: 697b ldr r3, [r7, #20] + 800366a: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 800366e: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8003670: 683b ldr r3, [r7, #0] + 8003672: 021a lsls r2, r3, #8 + 8003674: 687b ldr r3, [r7, #4] + 8003676: 431a orrs r2, r3 + 8003678: 68bb ldr r3, [r7, #8] + 800367a: 4313 orrs r3, r2 + 800367c: 697a ldr r2, [r7, #20] + 800367e: 4313 orrs r3, r2 + 8003680: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8003682: 68fb ldr r3, [r7, #12] + 8003684: 697a ldr r2, [r7, #20] + 8003686: 609a str r2, [r3, #8] +} + 8003688: bf00 nop + 800368a: 371c adds r7, #28 + 800368c: 46bd mov sp, r7 + 800368e: bc80 pop {r7} + 8003690: 4770 bx lr + +08003692 : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 8003692: b480 push {r7} + 8003694: b087 sub sp, #28 + 8003696: af00 add r7, sp, #0 + 8003698: 60f8 str r0, [r7, #12] + 800369a: 60b9 str r1, [r7, #8] + 800369c: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 800369e: 68bb ldr r3, [r7, #8] + 80036a0: f003 031f and.w r3, r3, #31 + 80036a4: 2201 movs r2, #1 + 80036a6: fa02 f303 lsl.w r3, r2, r3 + 80036aa: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 80036ac: 68fb ldr r3, [r7, #12] + 80036ae: 6a1a ldr r2, [r3, #32] + 80036b0: 697b ldr r3, [r7, #20] + 80036b2: 43db mvns r3, r3 + 80036b4: 401a ands r2, r3 + 80036b6: 68fb ldr r3, [r7, #12] + 80036b8: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 80036ba: 68fb ldr r3, [r7, #12] + 80036bc: 6a1a ldr r2, [r3, #32] + 80036be: 68bb ldr r3, [r7, #8] + 80036c0: f003 031f and.w r3, r3, #31 + 80036c4: 6879 ldr r1, [r7, #4] + 80036c6: fa01 f303 lsl.w r3, r1, r3 + 80036ca: 431a orrs r2, r3 + 80036cc: 68fb ldr r3, [r7, #12] + 80036ce: 621a str r2, [r3, #32] +} + 80036d0: bf00 nop + 80036d2: 371c adds r7, #28 + 80036d4: 46bd mov sp, r7 + 80036d6: bc80 pop {r7} + 80036d8: 4770 bx lr + ... + +080036dc : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + 80036dc: b480 push {r7} + 80036de: b085 sub sp, #20 + 80036e0: af00 add r7, sp, #0 + 80036e2: 6078 str r0, [r7, #4] + 80036e4: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 80036e6: 687b ldr r3, [r7, #4] + 80036e8: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 80036ec: 2b01 cmp r3, #1 + 80036ee: d101 bne.n 80036f4 + 80036f0: 2302 movs r3, #2 + 80036f2: e046 b.n 8003782 + 80036f4: 687b ldr r3, [r7, #4] + 80036f6: 2201 movs r2, #1 + 80036f8: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 80036fc: 687b ldr r3, [r7, #4] + 80036fe: 2202 movs r2, #2 + 8003700: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8003704: 687b ldr r3, [r7, #4] + 8003706: 681b ldr r3, [r3, #0] + 8003708: 685b ldr r3, [r3, #4] + 800370a: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 800370c: 687b ldr r3, [r7, #4] + 800370e: 681b ldr r3, [r3, #0] + 8003710: 689b ldr r3, [r3, #8] + 8003712: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8003714: 68fb ldr r3, [r7, #12] + 8003716: f023 0370 bic.w r3, r3, #112 @ 0x70 + 800371a: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 800371c: 683b ldr r3, [r7, #0] + 800371e: 681b ldr r3, [r3, #0] + 8003720: 68fa ldr r2, [r7, #12] + 8003722: 4313 orrs r3, r2 + 8003724: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8003726: 687b ldr r3, [r7, #4] + 8003728: 681b ldr r3, [r3, #0] + 800372a: 68fa ldr r2, [r7, #12] + 800372c: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 800372e: 687b ldr r3, [r7, #4] + 8003730: 681b ldr r3, [r3, #0] + 8003732: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8003736: d00e beq.n 8003756 + 8003738: 687b ldr r3, [r7, #4] + 800373a: 681b ldr r3, [r3, #0] + 800373c: 4a13 ldr r2, [pc, #76] @ (800378c ) + 800373e: 4293 cmp r3, r2 + 8003740: d009 beq.n 8003756 + 8003742: 687b ldr r3, [r7, #4] + 8003744: 681b ldr r3, [r3, #0] + 8003746: 4a12 ldr r2, [pc, #72] @ (8003790 ) + 8003748: 4293 cmp r3, r2 + 800374a: d004 beq.n 8003756 + 800374c: 687b ldr r3, [r7, #4] + 800374e: 681b ldr r3, [r3, #0] + 8003750: 4a10 ldr r2, [pc, #64] @ (8003794 ) + 8003752: 4293 cmp r3, r2 + 8003754: d10c bne.n 8003770 + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8003756: 68bb ldr r3, [r7, #8] + 8003758: f023 0380 bic.w r3, r3, #128 @ 0x80 + 800375c: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 800375e: 683b ldr r3, [r7, #0] + 8003760: 685b ldr r3, [r3, #4] + 8003762: 68ba ldr r2, [r7, #8] + 8003764: 4313 orrs r3, r2 + 8003766: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8003768: 687b ldr r3, [r7, #4] + 800376a: 681b ldr r3, [r3, #0] + 800376c: 68ba ldr r2, [r7, #8] + 800376e: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8003770: 687b ldr r3, [r7, #4] + 8003772: 2201 movs r2, #1 + 8003774: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8003778: 687b ldr r3, [r7, #4] + 800377a: 2200 movs r2, #0 + 800377c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return HAL_OK; + 8003780: 2300 movs r3, #0 +} + 8003782: 4618 mov r0, r3 + 8003784: 3714 adds r7, #20 + 8003786: 46bd mov sp, r7 + 8003788: bc80 pop {r7} + 800378a: 4770 bx lr + 800378c: 40000400 .word 0x40000400 + 8003790: 40000800 .word 0x40000800 + 8003794: 40010800 .word 0x40010800 + +08003798 : + 8003798: 4603 mov r3, r0 + 800379a: 4402 add r2, r0 + 800379c: 4293 cmp r3, r2 + 800379e: d100 bne.n 80037a2 + 80037a0: 4770 bx lr + 80037a2: f803 1b01 strb.w r1, [r3], #1 + 80037a6: e7f9 b.n 800379c + +080037a8 <__libc_init_array>: + 80037a8: b570 push {r4, r5, r6, lr} + 80037aa: 2600 movs r6, #0 + 80037ac: 4d0c ldr r5, [pc, #48] @ (80037e0 <__libc_init_array+0x38>) + 80037ae: 4c0d ldr r4, [pc, #52] @ (80037e4 <__libc_init_array+0x3c>) + 80037b0: 1b64 subs r4, r4, r5 + 80037b2: 10a4 asrs r4, r4, #2 + 80037b4: 42a6 cmp r6, r4 + 80037b6: d109 bne.n 80037cc <__libc_init_array+0x24> + 80037b8: f000 f81a bl 80037f0 <_init> + 80037bc: 2600 movs r6, #0 + 80037be: 4d0a ldr r5, [pc, #40] @ (80037e8 <__libc_init_array+0x40>) + 80037c0: 4c0a ldr r4, [pc, #40] @ (80037ec <__libc_init_array+0x44>) + 80037c2: 1b64 subs r4, r4, r5 + 80037c4: 10a4 asrs r4, r4, #2 + 80037c6: 42a6 cmp r6, r4 + 80037c8: d105 bne.n 80037d6 <__libc_init_array+0x2e> + 80037ca: bd70 pop {r4, r5, r6, pc} + 80037cc: f855 3b04 ldr.w r3, [r5], #4 + 80037d0: 4798 blx r3 + 80037d2: 3601 adds r6, #1 + 80037d4: e7ee b.n 80037b4 <__libc_init_array+0xc> + 80037d6: f855 3b04 ldr.w r3, [r5], #4 + 80037da: 4798 blx r3 + 80037dc: 3601 adds r6, #1 + 80037de: e7f2 b.n 80037c6 <__libc_init_array+0x1e> + 80037e0: 0800383c .word 0x0800383c + 80037e4: 0800383c .word 0x0800383c + 80037e8: 0800383c .word 0x0800383c + 80037ec: 08003840 .word 0x08003840 + +080037f0 <_init>: + 80037f0: b5f8 push {r3, r4, r5, r6, r7, lr} + 80037f2: bf00 nop + 80037f4: bcf8 pop {r3, r4, r5, r6, r7} + 80037f6: bc08 pop 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o +START GROUP +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a +LOAD 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08001a20 HAL_GPIO_EXTI_IRQHandler + .text.HAL_GPIO_EXTI_Callback + 0x08001a50 0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08001a50 HAL_GPIO_EXTI_Callback + .text.HAL_RCC_OscConfig + 0x08001a64 0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08001a64 HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x080020c4 0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x080020c4 HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x0800232c 0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0800232c HAL_RCC_GetSysClockFreq + .text.RCC_SetFlashLatencyFromMSIRange + 0x080024a8 0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .text.HAL_SPI_Init + 0x08002568 0x112 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08002568 HAL_SPI_Init + .text.HAL_SPI_Transmit + 0x0800267a 0x288 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x0800267a HAL_SPI_Transmit + *fill* 0x08002902 0x2 + .text.SPI_WaitFlagStateUntilTimeout + 0x08002904 0x110 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .text.SPI_EndRxTxTransaction + 0x08002a14 0xa8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .text.HAL_TIM_Base_Init + 0x08002abc 0x7e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08002abc HAL_TIM_Base_Init + *fill* 0x08002b3a 0x2 + .text.HAL_TIM_Base_Start_IT + 0x08002b3c 0xa4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08002b3c HAL_TIM_Base_Start_IT + .text.HAL_TIM_PWM_Init + 0x08002be0 0x7e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08002be0 HAL_TIM_PWM_Init + .text.HAL_TIM_PWM_MspInit + 0x08002c5e 0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08002c5e HAL_TIM_PWM_MspInit + .text.HAL_TIM_PWM_Start + 0x08002c70 0x12c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08002c70 HAL_TIM_PWM_Start + .text.HAL_TIM_IRQHandler + 0x08002d9c 0x198 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08002d9c HAL_TIM_IRQHandler + .text.HAL_TIM_PWM_ConfigChannel + 0x08002f34 0x184 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08002f34 HAL_TIM_PWM_ConfigChannel + .text.HAL_TIM_ConfigClockSource + 0x080030b8 0x18e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x080030b8 HAL_TIM_ConfigClockSource + .text.HAL_TIM_OC_DelayElapsedCallback + 0x08003246 0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08003246 HAL_TIM_OC_DelayElapsedCallback + .text.HAL_TIM_IC_CaptureCallback + 0x08003258 0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x08003258 HAL_TIM_IC_CaptureCallback + .text.HAL_TIM_PWM_PulseFinishedCallback + 0x0800326a 0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x0800326a HAL_TIM_PWM_PulseFinishedCallback + .text.HAL_TIM_TriggerCallback + 0x0800327c 0x12 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x0800327c HAL_TIM_TriggerCallback + *fill* 0x0800328e 0x2 + .text.TIM_Base_SetConfig + 0x08003290 0xec ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_OC1_SetConfig + 0x0800337c 0x78 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_OC2_SetConfig + 0x080033f4 0x7c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_OC3_SetConfig + 0x08003470 0x7a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x080034ea 0x7c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_TI1_ConfigInputStage + 0x08003566 0x5c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_TI2_ConfigInputStage + 0x080035c2 0x5e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_ITRx_SetConfig + 0x08003620 0x34 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_ETR_SetConfig + 0x08003654 0x3e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .text.TIM_CCxChannelCmd + 0x08003692 0x48 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + *fill* 0x080036da 0x2 + .text.HAL_TIMEx_MasterConfigSynchronization + 0x080036dc 0xbc ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + 0x080036dc HAL_TIMEx_MasterConfigSynchronization + .text.memset 0x08003798 0x10 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + 0x08003798 memset + .text.__libc_init_array + 0x080037a8 0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + 0x080037a8 __libc_init_array + *(.glue_7) + .glue_7 0x080037f0 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x080037f0 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/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x000002e1 0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_arm_muldf3.o) + .ARM.attributes + 0x000002fe 0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_arm_addsubdf3.o) + .ARM.attributes + 0x0000031b 0x1d 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0000000..512837e --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP4_GAMME.list @@ -0,0 +1,8029 @@ + +TP4_GAMME.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00002d68 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000002c 08002ea4 08002ea4 00003ea4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08002ed0 08002ed0 0000400c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08002ed0 08002ed0 00003ed0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08002ed8 08002ed8 0000400c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08002ed8 08002ed8 00003ed8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 08002edc 08002edc 00003edc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000000c 20000000 08002ee0 00004000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000000b8 2000000c 08002eec 0000400c 2**2 + ALLOC + 10 ._user_heap_stack 00000604 200000c4 08002eec 000040c4 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0 + CONTENTS, READONLY + 12 .debug_info 000090ef 00000000 00000000 00004035 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 000018df 00000000 00000000 0000d124 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000ab0 00000000 00000000 0000ea08 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 0000081a 00000000 00000000 0000f4b8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000155f9 00000000 00000000 0000fcd2 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0000aad6 00000000 00000000 000252cb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 0008863a 00000000 00000000 0002fda1 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000b83db 2**0 + CONTENTS, READONLY + 20 .debug_frame 00002c14 00000000 00000000 000b8420 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000bb034 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 2000000c .word 0x2000000c + 8000158: 00000000 .word 0x00000000 + 800015c: 08002e8c .word 0x08002e8c + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000010 .word 0x20000010 + 8000178: 08002e8c .word 0x08002e8c + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0 : + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void DO() { + 80004b0: b580 push {r7, lr} + 80004b2: af00 add r7, sp, #0 + MAX7219_DisplayChar(4, 0); + 80004b4: 2100 movs r1, #0 + 80004b6: 2004 movs r0, #4 + 80004b8: f000 fbb6 bl 8000c28 + TIM3->PSC = ((16000000/524)/1600) - 1; + 80004bc: 4b02 ldr r3, [pc, #8] @ (80004c8 ) + 80004be: 2212 movs r2, #18 + 80004c0: 629a str r2, [r3, #40] @ 0x28 +} + 80004c2: bf00 nop + 80004c4: bd80 pop {r7, pc} + 80004c6: bf00 nop + 80004c8: 40000400 .word 0x40000400 + +080004cc : + +void RE() { + 80004cc: b580 push {r7, lr} + 80004ce: af00 add r7, sp, #0 + MAX7219_DisplayChar(4, 1); + 80004d0: 2101 movs r1, #1 + 80004d2: 2004 movs r0, #4 + 80004d4: f000 fba8 bl 8000c28 + TIM3->PSC = ((16000000/587)/1600) - 1; + 80004d8: 4b02 ldr r3, [pc, #8] @ (80004e4 ) + 80004da: 2210 movs r2, #16 + 80004dc: 629a str r2, [r3, #40] @ 0x28 +} + 80004de: bf00 nop + 80004e0: bd80 pop {r7, pc} + 80004e2: bf00 nop + 80004e4: 40000400 .word 0x40000400 + +080004e8 : + +void MI() { + 80004e8: b580 push {r7, lr} + 80004ea: af00 add r7, sp, #0 + MAX7219_DisplayChar(4, 2); + 80004ec: 2102 movs r1, #2 + 80004ee: 2004 movs r0, #4 + 80004f0: f000 fb9a bl 8000c28 + TIM3->PSC = ((16000000/662)/1600) - 1; + 80004f4: 4b02 ldr r3, [pc, #8] @ (8000500 ) + 80004f6: 220e movs r2, #14 + 80004f8: 629a str r2, [r3, #40] @ 0x28 +} + 80004fa: bf00 nop + 80004fc: bd80 pop {r7, pc} + 80004fe: bf00 nop + 8000500: 40000400 .word 0x40000400 + +08000504 : + +void FA() { + 8000504: b580 push {r7, lr} + 8000506: af00 add r7, sp, #0 + MAX7219_DisplayChar(4, 3); + 8000508: 2103 movs r1, #3 + 800050a: 2004 movs r0, #4 + 800050c: f000 fb8c bl 8000c28 + TIM3->PSC = ((16000000/701)/1600) - 1; + 8000510: 4b02 ldr r3, [pc, #8] @ (800051c ) + 8000512: 220d movs r2, #13 + 8000514: 629a str r2, [r3, #40] @ 0x28 +} + 8000516: bf00 nop + 8000518: bd80 pop {r7, pc} + 800051a: bf00 nop + 800051c: 40000400 .word 0x40000400 + +08000520 : + +void SOL() { + 8000520: b580 push {r7, lr} + 8000522: af00 add r7, sp, #0 + MAX7219_DisplayChar(4, 4); + 8000524: 2104 movs r1, #4 + 8000526: 2004 movs r0, #4 + 8000528: f000 fb7e bl 8000c28 + TIM3->PSC = ((16000000/787)/1600) - 1; + 800052c: 4b02 ldr r3, [pc, #8] @ (8000538 ) + 800052e: 220b movs r2, #11 + 8000530: 629a str r2, [r3, #40] @ 0x28 +} + 8000532: bf00 nop + 8000534: bd80 pop {r7, pc} + 8000536: bf00 nop + 8000538: 40000400 .word 0x40000400 + +0800053c : + +void LA() { + 800053c: b580 push {r7, lr} + 800053e: af00 add r7, sp, #0 + MAX7219_DisplayChar(4, 5); + 8000540: 2105 movs r1, #5 + 8000542: 2004 movs r0, #4 + 8000544: f000 fb70 bl 8000c28 + TIM3->PSC = ((16000000/878)/1600) - 1; + 8000548: 4b02 ldr r3, [pc, #8] @ (8000554 ) + 800054a: 220a movs r2, #10 + 800054c: 629a str r2, [r3, #40] @ 0x28 +} + 800054e: bf00 nop + 8000550: bd80 pop {r7, pc} + 8000552: bf00 nop + 8000554: 40000400 .word 0x40000400 + +08000558 : + +void SI() { + 8000558: b580 push {r7, lr} + 800055a: af00 add r7, sp, #0 + MAX7219_DisplayChar(4, 6); + 800055c: 2106 movs r1, #6 + 800055e: 2004 movs r0, #4 + 8000560: f000 fb62 bl 8000c28 + TIM3->PSC = ((16000000/1004)/1600) - 1; + 8000564: 4b02 ldr r3, [pc, #8] @ (8000570 ) + 8000566: 2208 movs r2, #8 + 8000568: 629a str r2, [r3, #40] @ 0x28 +} + 800056a: bf00 nop + 800056c: bd80 pop {r7, pc} + 800056e: bf00 nop + 8000570: 40000400 .word 0x40000400 + +08000574
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000574: b580 push {r7, lr} + 8000576: b082 sub sp, #8 + 8000578: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 800057a: f000 fb9b bl 8000cb4 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 800057e: f000 f85f bl 8000640 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000582: f000 f94d bl 8000820 + MX_SPI1_Init(); + 8000586: f000 f8a1 bl 80006cc + MX_TIM3_Init(); + 800058a: f000 f8d5 bl 8000738 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 800058e: f000 fafe bl 8000b8e + HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1); + 8000592: 2100 movs r1, #0 + 8000594: 4829 ldr r0, [pc, #164] @ (800063c ) + 8000596: f001 ffa9 bl 80024ec + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 800059a: f000 fb2f bl 8000bfc + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + for (int i = 0; i < 7; i++) { + 800059e: 2300 movs r3, #0 + 80005a0: 607b str r3, [r7, #4] + 80005a2: e047 b.n 8000634 + if (i == 0) { // DO + 80005a4: 687b ldr r3, [r7, #4] + 80005a6: 2b00 cmp r3, #0 + 80005a8: d106 bne.n 80005b8 + DO(); + 80005aa: f7ff ff81 bl 80004b0 + HAL_Delay(500); + 80005ae: f44f 70fa mov.w r0, #500 @ 0x1f4 + 80005b2: f000 fbed bl 8000d90 + 80005b6: e03a b.n 800062e + } else if (i == 1) { // RE + 80005b8: 687b ldr r3, [r7, #4] + 80005ba: 2b01 cmp r3, #1 + 80005bc: d106 bne.n 80005cc + RE(); + 80005be: f7ff ff85 bl 80004cc + HAL_Delay(500); + 80005c2: f44f 70fa mov.w r0, #500 @ 0x1f4 + 80005c6: f000 fbe3 bl 8000d90 + 80005ca: e030 b.n 800062e + } else if (i == 2) { // MI + 80005cc: 687b ldr r3, [r7, #4] + 80005ce: 2b02 cmp r3, #2 + 80005d0: d106 bne.n 80005e0 + MI(); + 80005d2: f7ff ff89 bl 80004e8 + HAL_Delay(500); + 80005d6: f44f 70fa mov.w r0, #500 @ 0x1f4 + 80005da: f000 fbd9 bl 8000d90 + 80005de: e026 b.n 800062e + } else if (i == 3) { // FA + 80005e0: 687b ldr r3, [r7, #4] + 80005e2: 2b03 cmp r3, #3 + 80005e4: d106 bne.n 80005f4 + FA(); + 80005e6: f7ff ff8d bl 8000504 + HAL_Delay(500); + 80005ea: f44f 70fa mov.w r0, #500 @ 0x1f4 + 80005ee: f000 fbcf bl 8000d90 + 80005f2: e01c b.n 800062e + } else if (i == 4) { // SOL + 80005f4: 687b ldr r3, [r7, #4] + 80005f6: 2b04 cmp r3, #4 + 80005f8: d106 bne.n 8000608 + SOL(); + 80005fa: f7ff ff91 bl 8000520 + HAL_Delay(500); + 80005fe: f44f 70fa mov.w r0, #500 @ 0x1f4 + 8000602: f000 fbc5 bl 8000d90 + 8000606: e012 b.n 800062e + } else if (i == 5) { // LA + 8000608: 687b ldr r3, [r7, #4] + 800060a: 2b05 cmp r3, #5 + 800060c: d106 bne.n 800061c + LA(); + 800060e: f7ff ff95 bl 800053c + HAL_Delay(500); + 8000612: f44f 70fa mov.w r0, #500 @ 0x1f4 + 8000616: f000 fbbb bl 8000d90 + 800061a: e008 b.n 800062e + } else if (i == 6) { // SI + 800061c: 687b ldr r3, [r7, #4] + 800061e: 2b06 cmp r3, #6 + 8000620: d105 bne.n 800062e + SI(); + 8000622: f7ff ff99 bl 8000558 + HAL_Delay(500); + 8000626: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800062a: f000 fbb1 bl 8000d90 + for (int i = 0; i < 7; i++) { + 800062e: 687b ldr r3, [r7, #4] + 8000630: 3301 adds r3, #1 + 8000632: 607b str r3, [r7, #4] + 8000634: 687b ldr r3, [r7, #4] + 8000636: 2b06 cmp r3, #6 + 8000638: ddb4 ble.n 80005a4 + 800063a: e7b0 b.n 800059e + 800063c: 20000080 .word 0x20000080 + +08000640 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000640: b580 push {r7, lr} + 8000642: b092 sub sp, #72 @ 0x48 + 8000644: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000646: f107 0314 add.w r3, r7, #20 + 800064a: 2234 movs r2, #52 @ 0x34 + 800064c: 2100 movs r1, #0 + 800064e: 4618 mov r0, r3 + 8000650: f002 fbf0 bl 8002e34 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000654: 463b mov r3, r7 + 8000656: 2200 movs r2, #0 + 8000658: 601a str r2, [r3, #0] + 800065a: 605a str r2, [r3, #4] + 800065c: 609a str r2, [r3, #8] + 800065e: 60da str r2, [r3, #12] + 8000660: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000662: 4b19 ldr r3, [pc, #100] @ (80006c8 ) + 8000664: 681b ldr r3, [r3, #0] + 8000666: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 800066a: 4a17 ldr r2, [pc, #92] @ (80006c8 ) + 800066c: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000670: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000672: 2302 movs r3, #2 + 8000674: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000676: 2301 movs r3, #1 + 8000678: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 800067a: 2310 movs r3, #16 + 800067c: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 800067e: 2300 movs r3, #0 + 8000680: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000682: f107 0314 add.w r3, r7, #20 + 8000686: 4618 mov r0, r3 + 8000688: f000 fe7c bl 8001384 + 800068c: 4603 mov r3, r0 + 800068e: 2b00 cmp r3, #0 + 8000690: d001 beq.n 8000696 + { + Error_Handler(); + 8000692: f000 f94b bl 800092c + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000696: 230f movs r3, #15 + 8000698: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 800069a: 2301 movs r3, #1 + 800069c: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 800069e: 2300 movs r3, #0 + 80006a0: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80006a2: 2300 movs r3, #0 + 80006a4: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80006a6: 2300 movs r3, #0 + 80006a8: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 80006aa: 463b mov r3, r7 + 80006ac: 2100 movs r1, #0 + 80006ae: 4618 mov r0, r3 + 80006b0: f001 f998 bl 80019e4 + 80006b4: 4603 mov r3, r0 + 80006b6: 2b00 cmp r3, #0 + 80006b8: d001 beq.n 80006be + { + Error_Handler(); + 80006ba: f000 f937 bl 800092c + } +} + 80006be: bf00 nop + 80006c0: 3748 adds r7, #72 @ 0x48 + 80006c2: 46bd mov sp, r7 + 80006c4: bd80 pop {r7, pc} + 80006c6: bf00 nop + 80006c8: 40007000 .word 0x40007000 + +080006cc : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 80006cc: b580 push {r7, lr} + 80006ce: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 80006d0: 4b17 ldr r3, [pc, #92] @ (8000730 ) + 80006d2: 4a18 ldr r2, [pc, #96] @ (8000734 ) + 80006d4: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 80006d6: 4b16 ldr r3, [pc, #88] @ (8000730 ) + 80006d8: f44f 7282 mov.w r2, #260 @ 0x104 + 80006dc: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 80006de: 4b14 ldr r3, [pc, #80] @ (8000730 ) + 80006e0: 2200 movs r2, #0 + 80006e2: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 80006e4: 4b12 ldr r3, [pc, #72] @ (8000730 ) + 80006e6: 2200 movs r2, #0 + 80006e8: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 80006ea: 4b11 ldr r3, [pc, #68] @ (8000730 ) + 80006ec: 2200 movs r2, #0 + 80006ee: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 80006f0: 4b0f ldr r3, [pc, #60] @ (8000730 ) + 80006f2: 2200 movs r2, #0 + 80006f4: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 80006f6: 4b0e ldr r3, [pc, #56] @ (8000730 ) + 80006f8: f44f 7200 mov.w r2, #512 @ 0x200 + 80006fc: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 80006fe: 4b0c ldr r3, [pc, #48] @ (8000730 ) + 8000700: 2200 movs r2, #0 + 8000702: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 8000704: 4b0a ldr r3, [pc, #40] @ (8000730 ) + 8000706: 2200 movs r2, #0 + 8000708: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 800070a: 4b09 ldr r3, [pc, #36] @ (8000730 ) + 800070c: 2200 movs r2, #0 + 800070e: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8000710: 4b07 ldr r3, [pc, #28] @ (8000730 ) + 8000712: 2200 movs r2, #0 + 8000714: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 8000716: 4b06 ldr r3, [pc, #24] @ (8000730 ) + 8000718: 220a movs r2, #10 + 800071a: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 800071c: 4804 ldr r0, [pc, #16] @ (8000730 ) + 800071e: f001 fbb3 bl 8001e88 + 8000722: 4603 mov r3, r0 + 8000724: 2b00 cmp r3, #0 + 8000726: d001 beq.n 800072c + { + Error_Handler(); + 8000728: f000 f900 bl 800092c + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 800072c: bf00 nop + 800072e: bd80 pop {r7, pc} + 8000730: 20000028 .word 0x20000028 + 8000734: 40013000 .word 0x40013000 + +08000738 : + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + 8000738: b580 push {r7, lr} + 800073a: b08a sub sp, #40 @ 0x28 + 800073c: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800073e: f107 0318 add.w r3, r7, #24 + 8000742: 2200 movs r2, #0 + 8000744: 601a str r2, [r3, #0] + 8000746: 605a str r2, [r3, #4] + 8000748: 609a str r2, [r3, #8] + 800074a: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 800074c: f107 0310 add.w r3, r7, #16 + 8000750: 2200 movs r2, #0 + 8000752: 601a str r2, [r3, #0] + 8000754: 605a str r2, [r3, #4] + TIM_OC_InitTypeDef sConfigOC = {0}; + 8000756: 463b mov r3, r7 + 8000758: 2200 movs r2, #0 + 800075a: 601a str r2, [r3, #0] + 800075c: 605a str r2, [r3, #4] + 800075e: 609a str r2, [r3, #8] + 8000760: 60da str r2, [r3, #12] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 8000762: 4b2d ldr r3, [pc, #180] @ (8000818 ) + 8000764: 4a2d ldr r2, [pc, #180] @ (800081c ) + 8000766: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 19-1; + 8000768: 4b2b ldr r3, [pc, #172] @ (8000818 ) + 800076a: 2212 movs r2, #18 + 800076c: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 800076e: 4b2a ldr r3, [pc, #168] @ (8000818 ) + 8000770: 2200 movs r2, #0 + 8000772: 609a str r2, [r3, #8] + htim3.Init.Period = 1600-1; + 8000774: 4b28 ldr r3, [pc, #160] @ (8000818 ) + 8000776: f240 623f movw r2, #1599 @ 0x63f + 800077a: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 800077c: 4b26 ldr r3, [pc, #152] @ (8000818 ) + 800077e: 2200 movs r2, #0 + 8000780: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 8000782: 4b25 ldr r3, [pc, #148] @ (8000818 ) + 8000784: 2280 movs r2, #128 @ 0x80 + 8000786: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + 8000788: 4823 ldr r0, [pc, #140] @ (8000818 ) + 800078a: f001 fe27 bl 80023dc + 800078e: 4603 mov r3, r0 + 8000790: 2b00 cmp r3, #0 + 8000792: d001 beq.n 8000798 + { + Error_Handler(); + 8000794: f000 f8ca bl 800092c + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8000798: f44f 5380 mov.w r3, #4096 @ 0x1000 + 800079c: 61bb str r3, [r7, #24] + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + 800079e: f107 0318 add.w r3, r7, #24 + 80007a2: 4619 mov r1, r3 + 80007a4: 481c ldr r0, [pc, #112] @ (8000818 ) + 80007a6: f001 fff9 bl 800279c + 80007aa: 4603 mov r3, r0 + 80007ac: 2b00 cmp r3, #0 + 80007ae: d001 beq.n 80007b4 + { + Error_Handler(); + 80007b0: f000 f8bc bl 800092c + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + 80007b4: 4818 ldr r0, [pc, #96] @ (8000818 ) + 80007b6: f001 fe50 bl 800245a + 80007ba: 4603 mov r3, r0 + 80007bc: 2b00 cmp r3, #0 + 80007be: d001 beq.n 80007c4 + { + Error_Handler(); + 80007c0: f000 f8b4 bl 800092c + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80007c4: 2300 movs r3, #0 + 80007c6: 613b str r3, [r7, #16] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80007c8: 2300 movs r3, #0 + 80007ca: 617b str r3, [r7, #20] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 80007cc: f107 0310 add.w r3, r7, #16 + 80007d0: 4619 mov r1, r3 + 80007d2: 4811 ldr r0, [pc, #68] @ (8000818 ) + 80007d4: f002 fad0 bl 8002d78 + 80007d8: 4603 mov r3, r0 + 80007da: 2b00 cmp r3, #0 + 80007dc: d001 beq.n 80007e2 + { + Error_Handler(); + 80007de: f000 f8a5 bl 800092c + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 80007e2: 2360 movs r3, #96 @ 0x60 + 80007e4: 603b str r3, [r7, #0] + sConfigOC.Pulse = 800-1; + 80007e6: f240 331f movw r3, #799 @ 0x31f + 80007ea: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 80007ec: 2300 movs r3, #0 + 80007ee: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 80007f0: 2300 movs r3, #0 + 80007f2: 60fb str r3, [r7, #12] + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 80007f4: 463b mov r3, r7 + 80007f6: 2200 movs r2, #0 + 80007f8: 4619 mov r1, r3 + 80007fa: 4807 ldr r0, [pc, #28] @ (8000818 ) + 80007fc: f001 ff0c bl 8002618 + 8000800: 4603 mov r3, r0 + 8000802: 2b00 cmp r3, #0 + 8000804: d001 beq.n 800080a + { + Error_Handler(); + 8000806: f000 f891 bl 800092c + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + 800080a: 4803 ldr r0, [pc, #12] @ (8000818 ) + 800080c: f000 f924 bl 8000a58 + +} + 8000810: bf00 nop + 8000812: 3728 adds r7, #40 @ 0x28 + 8000814: 46bd mov sp, r7 + 8000816: bd80 pop {r7, pc} + 8000818: 20000080 .word 0x20000080 + 800081c: 40000400 .word 0x40000400 + +08000820 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000820: b580 push {r7, lr} + 8000822: b088 sub sp, #32 + 8000824: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000826: f107 030c add.w r3, r7, #12 + 800082a: 2200 movs r2, #0 + 800082c: 601a str r2, [r3, #0] + 800082e: 605a str r2, [r3, #4] + 8000830: 609a str r2, [r3, #8] + 8000832: 60da str r2, [r3, #12] + 8000834: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000836: 4b39 ldr r3, [pc, #228] @ (800091c ) + 8000838: 69db ldr r3, [r3, #28] + 800083a: 4a38 ldr r2, [pc, #224] @ (800091c ) + 800083c: f043 0304 orr.w r3, r3, #4 + 8000840: 61d3 str r3, [r2, #28] + 8000842: 4b36 ldr r3, [pc, #216] @ (800091c ) + 8000844: 69db ldr r3, [r3, #28] + 8000846: f003 0304 and.w r3, r3, #4 + 800084a: 60bb str r3, [r7, #8] + 800084c: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800084e: 4b33 ldr r3, [pc, #204] @ (800091c ) + 8000850: 69db ldr r3, [r3, #28] + 8000852: 4a32 ldr r2, [pc, #200] @ (800091c ) + 8000854: f043 0301 orr.w r3, r3, #1 + 8000858: 61d3 str r3, [r2, #28] + 800085a: 4b30 ldr r3, [pc, #192] @ (800091c ) + 800085c: 69db ldr r3, [r3, #28] + 800085e: f003 0301 and.w r3, r3, #1 + 8000862: 607b str r3, [r7, #4] + 8000864: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000866: 4b2d ldr r3, [pc, #180] @ (800091c ) + 8000868: 69db ldr r3, [r3, #28] + 800086a: 4a2c ldr r2, [pc, #176] @ (800091c ) + 800086c: f043 0302 orr.w r3, r3, #2 + 8000870: 61d3 str r3, [r2, #28] + 8000872: 4b2a ldr r3, [pc, #168] @ (800091c ) + 8000874: 69db ldr r3, [r3, #28] + 8000876: f003 0302 and.w r3, r3, #2 + 800087a: 603b str r3, [r7, #0] + 800087c: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 800087e: 2200 movs r2, #0 + 8000880: 2101 movs r1, #1 + 8000882: 4827 ldr r0, [pc, #156] @ (8000920 ) + 8000884: f000 fd44 bl 8001310 + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 8000888: 2301 movs r3, #1 + 800088a: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800088c: 2301 movs r3, #1 + 800088e: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000890: 2300 movs r3, #0 + 8000892: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000894: 2300 movs r3, #0 + 8000896: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8000898: f107 030c add.w r3, r7, #12 + 800089c: 4619 mov r1, r3 + 800089e: 4820 ldr r0, [pc, #128] @ (8000920 ) + 80008a0: f000 fba6 bl 8000ff0 + + /*Configure GPIO pin : PB15 */ + GPIO_InitStruct.Pin = GPIO_PIN_15; + 80008a4: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80008a8: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80008aa: 2302 movs r3, #2 + 80008ac: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008ae: 2300 movs r3, #0 + 80008b0: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80008b2: 2300 movs r3, #0 + 80008b4: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + 80008b6: 2303 movs r3, #3 + 80008b8: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80008ba: f107 030c add.w r3, r7, #12 + 80008be: 4619 mov r1, r3 + 80008c0: 4818 ldr r0, [pc, #96] @ (8000924 ) + 80008c2: f000 fb95 bl 8000ff0 + + /*Configure GPIO pins : PA11 PA12 */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 80008c6: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 80008ca: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 80008cc: f44f 1388 mov.w r3, #1114112 @ 0x110000 + 80008d0: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008d2: 2300 movs r3, #0 + 80008d4: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80008d6: f107 030c add.w r3, r7, #12 + 80008da: 4619 mov r1, r3 + 80008dc: 4812 ldr r0, [pc, #72] @ (8000928 ) + 80008de: f000 fb87 bl 8000ff0 + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + 80008e2: 2380 movs r3, #128 @ 0x80 + 80008e4: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80008e6: 2302 movs r3, #2 + 80008e8: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008ea: 2300 movs r3, #0 + 80008ec: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80008ee: 2300 movs r3, #0 + 80008f0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 80008f2: 2302 movs r3, #2 + 80008f4: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80008f6: f107 030c add.w r3, r7, #12 + 80008fa: 4619 mov r1, r3 + 80008fc: 4809 ldr r0, [pc, #36] @ (8000924 ) + 80008fe: f000 fb77 bl 8000ff0 + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 8000902: 2200 movs r2, #0 + 8000904: 2100 movs r1, #0 + 8000906: 2028 movs r0, #40 @ 0x28 + 8000908: f000 fb3b bl 8000f82 + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 800090c: 2028 movs r0, #40 @ 0x28 + 800090e: f000 fb54 bl 8000fba + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 8000912: bf00 nop + 8000914: 3720 adds r7, #32 + 8000916: 46bd mov sp, r7 + 8000918: bd80 pop {r7, pc} + 800091a: bf00 nop + 800091c: 40023800 .word 0x40023800 + 8000920: 40020800 .word 0x40020800 + 8000924: 40020400 .word 0x40020400 + 8000928: 40020000 .word 0x40020000 + +0800092c : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 800092c: b480 push {r7} + 800092e: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000930: b672 cpsid i +} + 8000932: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000934: bf00 nop + 8000936: e7fd b.n 8000934 + +08000938 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000938: b480 push {r7} + 800093a: b085 sub sp, #20 + 800093c: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 800093e: 4b14 ldr r3, [pc, #80] @ (8000990 ) + 8000940: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000942: 4a13 ldr r2, [pc, #76] @ (8000990 ) + 8000944: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 8000948: 6253 str r3, [r2, #36] @ 0x24 + 800094a: 4b11 ldr r3, [pc, #68] @ (8000990 ) + 800094c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800094e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8000952: 60fb str r3, [r7, #12] + 8000954: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000956: 4b0e ldr r3, [pc, #56] @ (8000990 ) + 8000958: 6a1b ldr r3, [r3, #32] + 800095a: 4a0d ldr r2, [pc, #52] @ (8000990 ) + 800095c: f043 0301 orr.w r3, r3, #1 + 8000960: 6213 str r3, [r2, #32] + 8000962: 4b0b ldr r3, [pc, #44] @ (8000990 ) + 8000964: 6a1b ldr r3, [r3, #32] + 8000966: f003 0301 and.w r3, r3, #1 + 800096a: 60bb str r3, [r7, #8] + 800096c: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800096e: 4b08 ldr r3, [pc, #32] @ (8000990 ) + 8000970: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000972: 4a07 ldr r2, [pc, #28] @ (8000990 ) + 8000974: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000978: 6253 str r3, [r2, #36] @ 0x24 + 800097a: 4b05 ldr r3, [pc, #20] @ (8000990 ) + 800097c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800097e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8000982: 607b str r3, [r7, #4] + 8000984: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000986: bf00 nop + 8000988: 3714 adds r7, #20 + 800098a: 46bd mov sp, r7 + 800098c: bc80 pop {r7} + 800098e: 4770 bx lr + 8000990: 40023800 .word 0x40023800 + +08000994 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8000994: b580 push {r7, lr} + 8000996: b08a sub sp, #40 @ 0x28 + 8000998: af00 add r7, sp, #0 + 800099a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800099c: f107 0314 add.w r3, r7, #20 + 80009a0: 2200 movs r2, #0 + 80009a2: 601a str r2, [r3, #0] + 80009a4: 605a str r2, [r3, #4] + 80009a6: 609a str r2, [r3, #8] + 80009a8: 60da str r2, [r3, #12] + 80009aa: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 80009ac: 687b ldr r3, [r7, #4] + 80009ae: 681b ldr r3, [r3, #0] + 80009b0: 4a17 ldr r2, [pc, #92] @ (8000a10 ) + 80009b2: 4293 cmp r3, r2 + 80009b4: d127 bne.n 8000a06 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 80009b6: 4b17 ldr r3, [pc, #92] @ (8000a14 ) + 80009b8: 6a1b ldr r3, [r3, #32] + 80009ba: 4a16 ldr r2, [pc, #88] @ (8000a14 ) + 80009bc: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 80009c0: 6213 str r3, [r2, #32] + 80009c2: 4b14 ldr r3, [pc, #80] @ (8000a14 ) + 80009c4: 6a1b ldr r3, [r3, #32] + 80009c6: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80009ca: 613b str r3, [r7, #16] + 80009cc: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80009ce: 4b11 ldr r3, [pc, #68] @ (8000a14 ) + 80009d0: 69db ldr r3, [r3, #28] + 80009d2: 4a10 ldr r2, [pc, #64] @ (8000a14 ) + 80009d4: f043 0301 orr.w r3, r3, #1 + 80009d8: 61d3 str r3, [r2, #28] + 80009da: 4b0e ldr r3, [pc, #56] @ (8000a14 ) + 80009dc: 69db ldr r3, [r3, #28] + 80009de: f003 0301 and.w r3, r3, #1 + 80009e2: 60fb str r3, [r7, #12] + 80009e4: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 80009e6: 23e0 movs r3, #224 @ 0xe0 + 80009e8: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80009ea: 2302 movs r3, #2 + 80009ec: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80009ee: 2300 movs r3, #0 + 80009f0: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80009f2: 2303 movs r3, #3 + 80009f4: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 80009f6: 2305 movs r3, #5 + 80009f8: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80009fa: f107 0314 add.w r3, r7, #20 + 80009fe: 4619 mov r1, r3 + 8000a00: 4805 ldr r0, [pc, #20] @ (8000a18 ) + 8000a02: f000 faf5 bl 8000ff0 + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 8000a06: bf00 nop + 8000a08: 3728 adds r7, #40 @ 0x28 + 8000a0a: 46bd mov sp, r7 + 8000a0c: bd80 pop {r7, pc} + 8000a0e: bf00 nop + 8000a10: 40013000 .word 0x40013000 + 8000a14: 40023800 .word 0x40023800 + 8000a18: 40020000 .word 0x40020000 + +08000a1c : + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8000a1c: b480 push {r7} + 8000a1e: b085 sub sp, #20 + 8000a20: af00 add r7, sp, #0 + 8000a22: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM3) + 8000a24: 687b ldr r3, [r7, #4] + 8000a26: 681b ldr r3, [r3, #0] + 8000a28: 4a09 ldr r2, [pc, #36] @ (8000a50 ) + 8000a2a: 4293 cmp r3, r2 + 8000a2c: d10b bne.n 8000a46 + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + 8000a2e: 4b09 ldr r3, [pc, #36] @ (8000a54 ) + 8000a30: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000a32: 4a08 ldr r2, [pc, #32] @ (8000a54 ) + 8000a34: f043 0302 orr.w r3, r3, #2 + 8000a38: 6253 str r3, [r2, #36] @ 0x24 + 8000a3a: 4b06 ldr r3, [pc, #24] @ (8000a54 ) + 8000a3c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000a3e: f003 0302 and.w r3, r3, #2 + 8000a42: 60fb str r3, [r7, #12] + 8000a44: 68fb ldr r3, [r7, #12] + + /* USER CODE END TIM3_MspInit 1 */ + + } + +} + 8000a46: bf00 nop + 8000a48: 3714 adds r7, #20 + 8000a4a: 46bd mov sp, r7 + 8000a4c: bc80 pop {r7} + 8000a4e: 4770 bx lr + 8000a50: 40000400 .word 0x40000400 + 8000a54: 40023800 .word 0x40023800 + +08000a58 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8000a58: b580 push {r7, lr} + 8000a5a: b088 sub sp, #32 + 8000a5c: af00 add r7, sp, #0 + 8000a5e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000a60: f107 030c add.w r3, r7, #12 + 8000a64: 2200 movs r2, #0 + 8000a66: 601a str r2, [r3, #0] + 8000a68: 605a str r2, [r3, #4] + 8000a6a: 609a str r2, [r3, #8] + 8000a6c: 60da str r2, [r3, #12] + 8000a6e: 611a str r2, [r3, #16] + if(htim->Instance==TIM3) + 8000a70: 687b ldr r3, [r7, #4] + 8000a72: 681b ldr r3, [r3, #0] + 8000a74: 4a11 ldr r2, [pc, #68] @ (8000abc ) + 8000a76: 4293 cmp r3, r2 + 8000a78: d11b bne.n 8000ab2 + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000a7a: 4b11 ldr r3, [pc, #68] @ (8000ac0 ) + 8000a7c: 69db ldr r3, [r3, #28] + 8000a7e: 4a10 ldr r2, [pc, #64] @ (8000ac0 ) + 8000a80: f043 0304 orr.w r3, r3, #4 + 8000a84: 61d3 str r3, [r2, #28] + 8000a86: 4b0e ldr r3, [pc, #56] @ (8000ac0 ) + 8000a88: 69db ldr r3, [r3, #28] + 8000a8a: f003 0304 and.w r3, r3, #4 + 8000a8e: 60bb str r3, [r7, #8] + 8000a90: 68bb ldr r3, [r7, #8] + /**TIM3 GPIO Configuration + PC6 ------> TIM3_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + 8000a92: 2340 movs r3, #64 @ 0x40 + 8000a94: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000a96: 2302 movs r3, #2 + 8000a98: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000a9a: 2300 movs r3, #0 + 8000a9c: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000a9e: 2300 movs r3, #0 + 8000aa0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 8000aa2: 2302 movs r3, #2 + 8000aa4: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8000aa6: f107 030c add.w r3, r7, #12 + 8000aaa: 4619 mov r1, r3 + 8000aac: 4805 ldr r0, [pc, #20] @ (8000ac4 ) + 8000aae: f000 fa9f bl 8000ff0 + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + +} + 8000ab2: bf00 nop + 8000ab4: 3720 adds r7, #32 + 8000ab6: 46bd mov sp, r7 + 8000ab8: bd80 pop {r7, pc} + 8000aba: bf00 nop + 8000abc: 40000400 .word 0x40000400 + 8000ac0: 40023800 .word 0x40023800 + 8000ac4: 40020800 .word 0x40020800 + +08000ac8 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000ac8: b480 push {r7} + 8000aca: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000acc: bf00 nop + 8000ace: e7fd b.n 8000acc + +08000ad0 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000ad0: b480 push {r7} + 8000ad2: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000ad4: bf00 nop + 8000ad6: e7fd b.n 8000ad4 + +08000ad8 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000ad8: b480 push {r7} + 8000ada: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000adc: bf00 nop + 8000ade: e7fd b.n 8000adc + +08000ae0 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000ae0: b480 push {r7} + 8000ae2: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000ae4: bf00 nop + 8000ae6: e7fd b.n 8000ae4 + +08000ae8 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000ae8: b480 push {r7} + 8000aea: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000aec: bf00 nop + 8000aee: e7fd b.n 8000aec + +08000af0 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000af0: b480 push {r7} + 8000af2: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000af4: bf00 nop + 8000af6: 46bd mov sp, r7 + 8000af8: bc80 pop {r7} + 8000afa: 4770 bx lr + +08000afc : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000afc: b480 push {r7} + 8000afe: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000b00: bf00 nop + 8000b02: 46bd mov sp, r7 + 8000b04: bc80 pop {r7} + 8000b06: 4770 bx lr + +08000b08 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000b08: b480 push {r7} + 8000b0a: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000b0c: bf00 nop + 8000b0e: 46bd mov sp, r7 + 8000b10: bc80 pop {r7} + 8000b12: 4770 bx lr + +08000b14 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000b14: b580 push {r7, lr} + 8000b16: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000b18: f000 f91e bl 8000d58 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000b1c: bf00 nop + 8000b1e: bd80 pop {r7, pc} + +08000b20 : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 8000b20: b580 push {r7, lr} + 8000b22: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + 8000b24: f44f 6000 mov.w r0, #2048 @ 0x800 + 8000b28: f000 fc0a bl 8001340 + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + 8000b2c: f44f 5080 mov.w r0, #4096 @ 0x1000 + 8000b30: f000 fc06 bl 8001340 + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8000b34: bf00 nop + 8000b36: bd80 pop {r7, pc} + +08000b38 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000b38: b480 push {r7} + 8000b3a: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000b3c: bf00 nop + 8000b3e: 46bd mov sp, r7 + 8000b40: bc80 pop {r7} + 8000b42: 4770 bx lr + +08000b44 : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000b44: f7ff fff8 bl 8000b38 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000b48: 480b ldr r0, [pc, #44] @ (8000b78 ) + ldr r1, =_edata + 8000b4a: 490c ldr r1, [pc, #48] @ (8000b7c ) + ldr r2, =_sidata + 8000b4c: 4a0c ldr r2, [pc, #48] @ (8000b80 ) + movs r3, #0 + 8000b4e: 2300 movs r3, #0 + b LoopCopyDataInit + 8000b50: e002 b.n 8000b58 + +08000b52 : + +CopyDataInit: + ldr r4, [r2, r3] + 8000b52: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000b54: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000b56: 3304 adds r3, #4 + +08000b58 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000b58: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000b5a: 428c cmp r4, r1 + bcc CopyDataInit + 8000b5c: d3f9 bcc.n 8000b52 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000b5e: 4a09 ldr r2, [pc, #36] @ (8000b84 ) + ldr r4, =_ebss + 8000b60: 4c09 ldr r4, [pc, #36] @ (8000b88 ) + movs r3, #0 + 8000b62: 2300 movs r3, #0 + b LoopFillZerobss + 8000b64: e001 b.n 8000b6a + +08000b66 : + +FillZerobss: + str r3, [r2] + 8000b66: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000b68: 3204 adds r2, #4 + +08000b6a : + +LoopFillZerobss: + cmp r2, r4 + 8000b6a: 42a2 cmp r2, r4 + bcc FillZerobss + 8000b6c: d3fb bcc.n 8000b66 + +/* Call static constructors */ + bl __libc_init_array + 8000b6e: f002 f969 bl 8002e44 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8000b72: f7ff fcff bl 8000574
+ bx lr + 8000b76: 4770 bx lr + ldr r0, =_sdata + 8000b78: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000b7c: 2000000c .word 0x2000000c + ldr r2, =_sidata + 8000b80: 08002ee0 .word 0x08002ee0 + ldr r2, =_sbss + 8000b84: 2000000c .word 0x2000000c + ldr r4, =_ebss + 8000b88: 200000c4 .word 0x200000c4 + +08000b8c : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000b8c: e7fe b.n 8000b8c + +08000b8e : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 8000b8e: b580 push {r7, lr} + 8000b90: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 8000b92: 2107 movs r1, #7 + 8000b94: 200b movs r0, #11 + 8000b96: f000 f85d bl 8000c54 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 8000b9a: 2100 movs r1, #0 + 8000b9c: 2009 movs r0, #9 + 8000b9e: f000 f859 bl 8000c54 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 8000ba2: f000 f809 bl 8000bb8 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 8000ba6: f000 f80f bl 8000bc8 + MAX7219_Clear(); // clear all digits + 8000baa: f000 f827 bl 8000bfc + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 8000bae: 200f movs r0, #15 + 8000bb0: f000 f812 bl 8000bd8 +} + 8000bb4: bf00 nop + 8000bb6: bd80 pop {r7, pc} + +08000bb8 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000bb8: b580 push {r7, lr} + 8000bba: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000bbc: 2101 movs r1, #1 + 8000bbe: 200c movs r0, #12 + 8000bc0: f000 f848 bl 8000c54 +} + 8000bc4: bf00 nop + 8000bc6: bd80 pop {r7, pc} + +08000bc8 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 8000bc8: b580 push {r7, lr} + 8000bca: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 8000bcc: 2100 movs r1, #0 + 8000bce: 200f movs r0, #15 + 8000bd0: f000 f840 bl 8000c54 +} + 8000bd4: bf00 nop + 8000bd6: bd80 pop {r7, pc} + +08000bd8 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 8000bd8: b580 push {r7, lr} + 8000bda: b082 sub sp, #8 + 8000bdc: af00 add r7, sp, #0 + 8000bde: 4603 mov r3, r0 + 8000be0: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 8000be2: 79fb ldrb r3, [r7, #7] + 8000be4: f003 030f and.w r3, r3, #15 + 8000be8: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 8000bea: 79fb ldrb r3, [r7, #7] + 8000bec: 4619 mov r1, r3 + 8000bee: 200a movs r0, #10 + 8000bf0: f000 f830 bl 8000c54 +} + 8000bf4: bf00 nop + 8000bf6: 3708 adds r7, #8 + 8000bf8: 46bd mov sp, r7 + 8000bfa: bd80 pop {r7, pc} + +08000bfc : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 8000bfc: b580 push {r7, lr} + 8000bfe: b082 sub sp, #8 + 8000c00: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 8000c02: 2300 movs r3, #0 + 8000c04: 71fb strb r3, [r7, #7] + 8000c06: e007 b.n 8000c18 + MAX7219_Write(i, 0x00); // turn all segments off + 8000c08: 79fb ldrb r3, [r7, #7] + 8000c0a: 2100 movs r1, #0 + 8000c0c: 4618 mov r0, r3 + 8000c0e: f000 f821 bl 8000c54 + for (i=0; i < 8; i++) + 8000c12: 79fb ldrb r3, [r7, #7] + 8000c14: 3301 adds r3, #1 + 8000c16: 71fb strb r3, [r7, #7] + 8000c18: 79fb ldrb r3, [r7, #7] + 8000c1a: 2b07 cmp r3, #7 + 8000c1c: d9f4 bls.n 8000c08 +} + 8000c1e: bf00 nop + 8000c20: bf00 nop + 8000c22: 3708 adds r7, #8 + 8000c24: 46bd mov sp, r7 + 8000c26: bd80 pop {r7, pc} + +08000c28 : +* character = character to display (0-9, A-Z) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayChar(char digit, char character) +{ + 8000c28: b580 push {r7, lr} + 8000c2a: b082 sub sp, #8 + 8000c2c: af00 add r7, sp, #0 + 8000c2e: 4603 mov r3, r0 + 8000c30: 460a mov r2, r1 + 8000c32: 71fb strb r3, [r7, #7] + 8000c34: 4613 mov r3, r2 + 8000c36: 71bb strb r3, [r7, #6] + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]); + 8000c38: 79bb ldrb r3, [r7, #6] + 8000c3a: 4a05 ldr r2, [pc, #20] @ (8000c50 ) + 8000c3c: 5cd2 ldrb r2, [r2, r3] + 8000c3e: 79fb ldrb r3, [r7, #7] + 8000c40: 4611 mov r1, r2 + 8000c42: 4618 mov r0, r3 + 8000c44: f000 f806 bl 8000c54 +} + 8000c48: bf00 nop + 8000c4a: 3708 adds r7, #8 + 8000c4c: 46bd mov sp, r7 + 8000c4e: bd80 pop {r7, pc} + 8000c50: 08002ec0 .word 0x08002ec0 + +08000c54 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8000c54: b580 push {r7, lr} + 8000c56: b082 sub sp, #8 + 8000c58: af00 add r7, sp, #0 + 8000c5a: 4603 mov r3, r0 + 8000c5c: 460a mov r2, r1 + 8000c5e: 71fb strb r3, [r7, #7] + 8000c60: 4613 mov r3, r2 + 8000c62: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8000c64: 4b09 ldr r3, [pc, #36] @ (8000c8c ) + 8000c66: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000c6a: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8000c6c: 79fb ldrb r3, [r7, #7] + 8000c6e: 4618 mov r0, r3 + 8000c70: f000 f80e bl 8000c90 + MAX7219_SendByte(dataout); // write data to MAX7219 + 8000c74: 79bb ldrb r3, [r7, #6] + 8000c76: 4618 mov r0, r3 + 8000c78: f000 f80a bl 8000c90 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 8000c7c: 4b03 ldr r3, [pc, #12] @ (8000c8c ) + 8000c7e: 2201 movs r2, #1 + 8000c80: 619a str r2, [r3, #24] + } + 8000c82: bf00 nop + 8000c84: 3708 adds r7, #8 + 8000c86: 46bd mov sp, r7 + 8000c88: bd80 pop {r7, pc} + 8000c8a: bf00 nop + 8000c8c: 40020800 .word 0x40020800 + +08000c90 : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000c90: b580 push {r7, lr} + 8000c92: b082 sub sp, #8 + 8000c94: af00 add r7, sp, #0 + 8000c96: 4603 mov r3, r0 + 8000c98: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 8000c9a: 1df9 adds r1, r7, #7 + 8000c9c: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000ca0: 2201 movs r2, #1 + 8000ca2: 4803 ldr r0, [pc, #12] @ (8000cb0 ) + 8000ca4: f001 f979 bl 8001f9a + +} + 8000ca8: bf00 nop + 8000caa: 3708 adds r7, #8 + 8000cac: 46bd mov sp, r7 + 8000cae: bd80 pop {r7, pc} + 8000cb0: 20000028 .word 0x20000028 + +08000cb4 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000cb4: b580 push {r7, lr} + 8000cb6: b082 sub sp, #8 + 8000cb8: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000cba: 2300 movs r3, #0 + 8000cbc: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000cbe: 2003 movs r0, #3 + 8000cc0: f000 f954 bl 8000f6c + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000cc4: 200f movs r0, #15 + 8000cc6: f000 f80d bl 8000ce4 + 8000cca: 4603 mov r3, r0 + 8000ccc: 2b00 cmp r3, #0 + 8000cce: d002 beq.n 8000cd6 + { + status = HAL_ERROR; + 8000cd0: 2301 movs r3, #1 + 8000cd2: 71fb strb r3, [r7, #7] + 8000cd4: e001 b.n 8000cda + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000cd6: f7ff fe2f bl 8000938 + } + + /* Return function status */ + return status; + 8000cda: 79fb ldrb r3, [r7, #7] +} + 8000cdc: 4618 mov r0, r3 + 8000cde: 3708 adds r7, #8 + 8000ce0: 46bd mov sp, r7 + 8000ce2: bd80 pop {r7, pc} + +08000ce4 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000ce4: b580 push {r7, lr} + 8000ce6: b084 sub sp, #16 + 8000ce8: af00 add r7, sp, #0 + 8000cea: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000cec: 2300 movs r3, #0 + 8000cee: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 8000cf0: 4b16 ldr r3, [pc, #88] @ (8000d4c ) + 8000cf2: 681b ldr r3, [r3, #0] + 8000cf4: 2b00 cmp r3, #0 + 8000cf6: d022 beq.n 8000d3e + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 8000cf8: 4b15 ldr r3, [pc, #84] @ (8000d50 ) + 8000cfa: 681a ldr r2, [r3, #0] + 8000cfc: 4b13 ldr r3, [pc, #76] @ (8000d4c ) + 8000cfe: 681b ldr r3, [r3, #0] + 8000d00: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8000d04: fbb1 f3f3 udiv r3, r1, r3 + 8000d08: fbb2 f3f3 udiv r3, r2, r3 + 8000d0c: 4618 mov r0, r3 + 8000d0e: f000 f962 bl 8000fd6 + 8000d12: 4603 mov r3, r0 + 8000d14: 2b00 cmp r3, #0 + 8000d16: d10f bne.n 8000d38 + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000d18: 687b ldr r3, [r7, #4] + 8000d1a: 2b0f cmp r3, #15 + 8000d1c: d809 bhi.n 8000d32 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000d1e: 2200 movs r2, #0 + 8000d20: 6879 ldr r1, [r7, #4] + 8000d22: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000d26: f000 f92c bl 8000f82 + uwTickPrio = TickPriority; + 8000d2a: 4a0a ldr r2, [pc, #40] @ (8000d54 ) + 8000d2c: 687b ldr r3, [r7, #4] + 8000d2e: 6013 str r3, [r2, #0] + 8000d30: e007 b.n 8000d42 + } + else + { + status = HAL_ERROR; + 8000d32: 2301 movs r3, #1 + 8000d34: 73fb strb r3, [r7, #15] + 8000d36: e004 b.n 8000d42 + } + } + else + { + status = HAL_ERROR; + 8000d38: 2301 movs r3, #1 + 8000d3a: 73fb strb r3, [r7, #15] + 8000d3c: e001 b.n 8000d42 + } + } + else + { + status = HAL_ERROR; + 8000d3e: 2301 movs r3, #1 + 8000d40: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8000d42: 7bfb ldrb r3, [r7, #15] +} + 8000d44: 4618 mov r0, r3 + 8000d46: 3710 adds r7, #16 + 8000d48: 46bd mov sp, r7 + 8000d4a: bd80 pop {r7, pc} + 8000d4c: 20000008 .word 0x20000008 + 8000d50: 20000000 .word 0x20000000 + 8000d54: 20000004 .word 0x20000004 + +08000d58 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000d58: b480 push {r7} + 8000d5a: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000d5c: 4b05 ldr r3, [pc, #20] @ (8000d74 ) + 8000d5e: 681a ldr r2, [r3, #0] + 8000d60: 4b05 ldr r3, [pc, #20] @ (8000d78 ) + 8000d62: 681b ldr r3, [r3, #0] + 8000d64: 4413 add r3, r2 + 8000d66: 4a03 ldr r2, [pc, #12] @ (8000d74 ) + 8000d68: 6013 str r3, [r2, #0] +} + 8000d6a: bf00 nop + 8000d6c: 46bd mov sp, r7 + 8000d6e: bc80 pop {r7} + 8000d70: 4770 bx lr + 8000d72: bf00 nop + 8000d74: 200000c0 .word 0x200000c0 + 8000d78: 20000008 .word 0x20000008 + +08000d7c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000d7c: b480 push {r7} + 8000d7e: af00 add r7, sp, #0 + return uwTick; + 8000d80: 4b02 ldr r3, [pc, #8] @ (8000d8c ) + 8000d82: 681b ldr r3, [r3, #0] +} + 8000d84: 4618 mov r0, r3 + 8000d86: 46bd mov sp, r7 + 8000d88: bc80 pop {r7} + 8000d8a: 4770 bx lr + 8000d8c: 200000c0 .word 0x200000c0 + +08000d90 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000d90: b580 push {r7, lr} + 8000d92: b084 sub sp, #16 + 8000d94: af00 add r7, sp, #0 + 8000d96: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8000d98: f7ff fff0 bl 8000d7c + 8000d9c: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8000d9e: 687b ldr r3, [r7, #4] + 8000da0: 60fb str r3, [r7, #12] + + /* Add a period to guaranty minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000da2: 68fb ldr r3, [r7, #12] + 8000da4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8000da8: d004 beq.n 8000db4 + { + wait += (uint32_t)(uwTickFreq); + 8000daa: 4b09 ldr r3, [pc, #36] @ (8000dd0 ) + 8000dac: 681b ldr r3, [r3, #0] + 8000dae: 68fa ldr r2, [r7, #12] + 8000db0: 4413 add r3, r2 + 8000db2: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 8000db4: bf00 nop + 8000db6: f7ff ffe1 bl 8000d7c + 8000dba: 4602 mov r2, r0 + 8000dbc: 68bb ldr r3, [r7, #8] + 8000dbe: 1ad3 subs r3, r2, r3 + 8000dc0: 68fa ldr r2, [r7, #12] + 8000dc2: 429a cmp r2, r3 + 8000dc4: d8f7 bhi.n 8000db6 + { + } +} + 8000dc6: bf00 nop + 8000dc8: bf00 nop + 8000dca: 3710 adds r7, #16 + 8000dcc: 46bd mov sp, r7 + 8000dce: bd80 pop {r7, pc} + 8000dd0: 20000008 .word 0x20000008 + +08000dd4 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000dd4: b480 push {r7} + 8000dd6: b085 sub sp, #20 + 8000dd8: af00 add r7, sp, #0 + 8000dda: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000ddc: 687b ldr r3, [r7, #4] + 8000dde: f003 0307 and.w r3, r3, #7 + 8000de2: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000de4: 4b0c ldr r3, [pc, #48] @ (8000e18 <__NVIC_SetPriorityGrouping+0x44>) + 8000de6: 68db ldr r3, [r3, #12] + 8000de8: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000dea: 68ba ldr r2, [r7, #8] + 8000dec: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000df0: 4013 ands r3, r2 + 8000df2: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000df4: 68fb ldr r3, [r7, #12] + 8000df6: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000df8: 68bb ldr r3, [r7, #8] + 8000dfa: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000dfc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000e00: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000e04: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000e06: 4a04 ldr r2, [pc, #16] @ (8000e18 <__NVIC_SetPriorityGrouping+0x44>) + 8000e08: 68bb ldr r3, [r7, #8] + 8000e0a: 60d3 str r3, [r2, #12] +} + 8000e0c: bf00 nop + 8000e0e: 3714 adds r7, #20 + 8000e10: 46bd mov sp, r7 + 8000e12: bc80 pop {r7} + 8000e14: 4770 bx lr + 8000e16: bf00 nop + 8000e18: e000ed00 .word 0xe000ed00 + +08000e1c <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000e1c: b480 push {r7} + 8000e1e: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000e20: 4b04 ldr r3, [pc, #16] @ (8000e34 <__NVIC_GetPriorityGrouping+0x18>) + 8000e22: 68db ldr r3, [r3, #12] + 8000e24: 0a1b lsrs r3, r3, #8 + 8000e26: f003 0307 and.w r3, r3, #7 +} + 8000e2a: 4618 mov r0, r3 + 8000e2c: 46bd mov sp, r7 + 8000e2e: bc80 pop {r7} + 8000e30: 4770 bx lr + 8000e32: bf00 nop + 8000e34: e000ed00 .word 0xe000ed00 + +08000e38 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000e38: b480 push {r7} + 8000e3a: b083 sub sp, #12 + 8000e3c: af00 add r7, sp, #0 + 8000e3e: 4603 mov r3, r0 + 8000e40: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000e42: f997 3007 ldrsb.w r3, [r7, #7] + 8000e46: 2b00 cmp r3, #0 + 8000e48: db0b blt.n 8000e62 <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8000e4a: 79fb ldrb r3, [r7, #7] + 8000e4c: f003 021f and.w r2, r3, #31 + 8000e50: 4906 ldr r1, [pc, #24] @ (8000e6c <__NVIC_EnableIRQ+0x34>) + 8000e52: f997 3007 ldrsb.w r3, [r7, #7] + 8000e56: 095b lsrs r3, r3, #5 + 8000e58: 2001 movs r0, #1 + 8000e5a: fa00 f202 lsl.w r2, r0, r2 + 8000e5e: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8000e62: bf00 nop + 8000e64: 370c adds r7, #12 + 8000e66: 46bd mov sp, r7 + 8000e68: bc80 pop {r7} + 8000e6a: 4770 bx lr + 8000e6c: e000e100 .word 0xe000e100 + +08000e70 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000e70: b480 push {r7} + 8000e72: b083 sub sp, #12 + 8000e74: af00 add r7, sp, #0 + 8000e76: 4603 mov r3, r0 + 8000e78: 6039 str r1, [r7, #0] + 8000e7a: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000e7c: f997 3007 ldrsb.w r3, [r7, #7] + 8000e80: 2b00 cmp r3, #0 + 8000e82: db0a blt.n 8000e9a <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000e84: 683b ldr r3, [r7, #0] + 8000e86: b2da uxtb r2, r3 + 8000e88: 490c ldr r1, [pc, #48] @ (8000ebc <__NVIC_SetPriority+0x4c>) + 8000e8a: f997 3007 ldrsb.w r3, [r7, #7] + 8000e8e: 0112 lsls r2, r2, #4 + 8000e90: b2d2 uxtb r2, r2 + 8000e92: 440b add r3, r1 + 8000e94: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000e98: e00a b.n 8000eb0 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000e9a: 683b ldr r3, [r7, #0] + 8000e9c: b2da uxtb r2, r3 + 8000e9e: 4908 ldr r1, [pc, #32] @ (8000ec0 <__NVIC_SetPriority+0x50>) + 8000ea0: 79fb ldrb r3, [r7, #7] + 8000ea2: f003 030f and.w r3, r3, #15 + 8000ea6: 3b04 subs r3, #4 + 8000ea8: 0112 lsls r2, r2, #4 + 8000eaa: b2d2 uxtb r2, r2 + 8000eac: 440b add r3, r1 + 8000eae: 761a strb r2, [r3, #24] +} + 8000eb0: bf00 nop + 8000eb2: 370c adds r7, #12 + 8000eb4: 46bd mov sp, r7 + 8000eb6: bc80 pop {r7} + 8000eb8: 4770 bx lr + 8000eba: bf00 nop + 8000ebc: e000e100 .word 0xe000e100 + 8000ec0: e000ed00 .word 0xe000ed00 + +08000ec4 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000ec4: b480 push {r7} + 8000ec6: b089 sub sp, #36 @ 0x24 + 8000ec8: af00 add r7, sp, #0 + 8000eca: 60f8 str r0, [r7, #12] + 8000ecc: 60b9 str r1, [r7, #8] + 8000ece: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000ed0: 68fb ldr r3, [r7, #12] + 8000ed2: f003 0307 and.w r3, r3, #7 + 8000ed6: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000ed8: 69fb ldr r3, [r7, #28] + 8000eda: f1c3 0307 rsb r3, r3, #7 + 8000ede: 2b04 cmp r3, #4 + 8000ee0: bf28 it cs + 8000ee2: 2304 movcs r3, #4 + 8000ee4: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000ee6: 69fb ldr r3, [r7, #28] + 8000ee8: 3304 adds r3, #4 + 8000eea: 2b06 cmp r3, #6 + 8000eec: d902 bls.n 8000ef4 + 8000eee: 69fb ldr r3, [r7, #28] + 8000ef0: 3b03 subs r3, #3 + 8000ef2: e000 b.n 8000ef6 + 8000ef4: 2300 movs r3, #0 + 8000ef6: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000ef8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000efc: 69bb ldr r3, [r7, #24] + 8000efe: fa02 f303 lsl.w r3, r2, r3 + 8000f02: 43da mvns r2, r3 + 8000f04: 68bb ldr r3, [r7, #8] + 8000f06: 401a ands r2, r3 + 8000f08: 697b ldr r3, [r7, #20] + 8000f0a: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000f0c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000f10: 697b ldr r3, [r7, #20] + 8000f12: fa01 f303 lsl.w r3, r1, r3 + 8000f16: 43d9 mvns r1, r3 + 8000f18: 687b ldr r3, [r7, #4] + 8000f1a: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000f1c: 4313 orrs r3, r2 + ); +} + 8000f1e: 4618 mov r0, r3 + 8000f20: 3724 adds r7, #36 @ 0x24 + 8000f22: 46bd mov sp, r7 + 8000f24: bc80 pop {r7} + 8000f26: 4770 bx lr + +08000f28 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000f28: b580 push {r7, lr} + 8000f2a: b082 sub sp, #8 + 8000f2c: af00 add r7, sp, #0 + 8000f2e: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000f30: 687b ldr r3, [r7, #4] + 8000f32: 3b01 subs r3, #1 + 8000f34: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000f38: d301 bcc.n 8000f3e + { + return (1UL); /* Reload value impossible */ + 8000f3a: 2301 movs r3, #1 + 8000f3c: e00f b.n 8000f5e + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000f3e: 4a0a ldr r2, [pc, #40] @ (8000f68 ) + 8000f40: 687b ldr r3, [r7, #4] + 8000f42: 3b01 subs r3, #1 + 8000f44: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000f46: 210f movs r1, #15 + 8000f48: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000f4c: f7ff ff90 bl 8000e70 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000f50: 4b05 ldr r3, [pc, #20] @ (8000f68 ) + 8000f52: 2200 movs r2, #0 + 8000f54: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000f56: 4b04 ldr r3, [pc, #16] @ (8000f68 ) + 8000f58: 2207 movs r2, #7 + 8000f5a: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000f5c: 2300 movs r3, #0 +} + 8000f5e: 4618 mov r0, r3 + 8000f60: 3708 adds r7, #8 + 8000f62: 46bd mov sp, r7 + 8000f64: bd80 pop {r7, pc} + 8000f66: bf00 nop + 8000f68: e000e010 .word 0xe000e010 + +08000f6c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000f6c: b580 push {r7, lr} + 8000f6e: b082 sub sp, #8 + 8000f70: af00 add r7, sp, #0 + 8000f72: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8000f74: 6878 ldr r0, [r7, #4] + 8000f76: f7ff ff2d bl 8000dd4 <__NVIC_SetPriorityGrouping> +} + 8000f7a: bf00 nop + 8000f7c: 3708 adds r7, #8 + 8000f7e: 46bd mov sp, r7 + 8000f80: bd80 pop {r7, pc} + +08000f82 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000f82: b580 push {r7, lr} + 8000f84: b086 sub sp, #24 + 8000f86: af00 add r7, sp, #0 + 8000f88: 4603 mov r3, r0 + 8000f8a: 60b9 str r1, [r7, #8] + 8000f8c: 607a str r2, [r7, #4] + 8000f8e: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8000f90: 2300 movs r3, #0 + 8000f92: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8000f94: f7ff ff42 bl 8000e1c <__NVIC_GetPriorityGrouping> + 8000f98: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8000f9a: 687a ldr r2, [r7, #4] + 8000f9c: 68b9 ldr r1, [r7, #8] + 8000f9e: 6978 ldr r0, [r7, #20] + 8000fa0: f7ff ff90 bl 8000ec4 + 8000fa4: 4602 mov r2, r0 + 8000fa6: f997 300f ldrsb.w r3, [r7, #15] + 8000faa: 4611 mov r1, r2 + 8000fac: 4618 mov r0, r3 + 8000fae: f7ff ff5f bl 8000e70 <__NVIC_SetPriority> +} + 8000fb2: bf00 nop + 8000fb4: 3718 adds r7, #24 + 8000fb6: 46bd mov sp, r7 + 8000fb8: bd80 pop {r7, pc} + +08000fba : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000fba: b580 push {r7, lr} + 8000fbc: b082 sub sp, #8 + 8000fbe: af00 add r7, sp, #0 + 8000fc0: 4603 mov r3, r0 + 8000fc2: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8000fc4: f997 3007 ldrsb.w r3, [r7, #7] + 8000fc8: 4618 mov r0, r3 + 8000fca: f7ff ff35 bl 8000e38 <__NVIC_EnableIRQ> +} + 8000fce: bf00 nop + 8000fd0: 3708 adds r7, #8 + 8000fd2: 46bd mov sp, r7 + 8000fd4: bd80 pop {r7, pc} + +08000fd6 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000fd6: b580 push {r7, lr} + 8000fd8: b082 sub sp, #8 + 8000fda: af00 add r7, sp, #0 + 8000fdc: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000fde: 6878 ldr r0, [r7, #4] + 8000fe0: f7ff ffa2 bl 8000f28 + 8000fe4: 4603 mov r3, r0 +} + 8000fe6: 4618 mov r0, r3 + 8000fe8: 3708 adds r7, #8 + 8000fea: 46bd mov sp, r7 + 8000fec: bd80 pop {r7, pc} + ... + +08000ff0 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000ff0: b480 push {r7} + 8000ff2: b087 sub sp, #28 + 8000ff4: af00 add r7, sp, #0 + 8000ff6: 6078 str r0, [r7, #4] + 8000ff8: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8000ffa: 2300 movs r3, #0 + 8000ffc: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8000ffe: 2300 movs r3, #0 + 8001000: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 8001002: 2300 movs r3, #0 + 8001004: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8001006: e160 b.n 80012ca + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8001008: 683b ldr r3, [r7, #0] + 800100a: 681a ldr r2, [r3, #0] + 800100c: 2101 movs r1, #1 + 800100e: 697b ldr r3, [r7, #20] + 8001010: fa01 f303 lsl.w r3, r1, r3 + 8001014: 4013 ands r3, r2 + 8001016: 60fb str r3, [r7, #12] + + if (iocurrent) + 8001018: 68fb ldr r3, [r7, #12] + 800101a: 2b00 cmp r3, #0 + 800101c: f000 8152 beq.w 80012c4 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8001020: 683b ldr r3, [r7, #0] + 8001022: 685b ldr r3, [r3, #4] + 8001024: f003 0303 and.w r3, r3, #3 + 8001028: 2b01 cmp r3, #1 + 800102a: d005 beq.n 8001038 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 800102c: 683b ldr r3, [r7, #0] + 800102e: 685b ldr r3, [r3, #4] + 8001030: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8001034: 2b02 cmp r3, #2 + 8001036: d130 bne.n 800109a + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001038: 687b ldr r3, [r7, #4] + 800103a: 689b ldr r3, [r3, #8] + 800103c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 800103e: 697b ldr r3, [r7, #20] + 8001040: 005b lsls r3, r3, #1 + 8001042: 2203 movs r2, #3 + 8001044: fa02 f303 lsl.w r3, r2, r3 + 8001048: 43db mvns r3, r3 + 800104a: 693a ldr r2, [r7, #16] + 800104c: 4013 ands r3, r2 + 800104e: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8001050: 683b ldr r3, [r7, #0] + 8001052: 68da ldr r2, [r3, #12] + 8001054: 697b ldr r3, [r7, #20] + 8001056: 005b lsls r3, r3, #1 + 8001058: fa02 f303 lsl.w r3, r2, r3 + 800105c: 693a ldr r2, [r7, #16] + 800105e: 4313 orrs r3, r2 + 8001060: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8001062: 687b ldr r3, [r7, #4] + 8001064: 693a ldr r2, [r7, #16] + 8001066: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8001068: 687b ldr r3, [r7, #4] + 800106a: 685b ldr r3, [r3, #4] + 800106c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 800106e: 2201 movs r2, #1 + 8001070: 697b ldr r3, [r7, #20] + 8001072: fa02 f303 lsl.w r3, r2, r3 + 8001076: 43db mvns r3, r3 + 8001078: 693a ldr r2, [r7, #16] + 800107a: 4013 ands r3, r2 + 800107c: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 800107e: 683b ldr r3, [r7, #0] + 8001080: 685b ldr r3, [r3, #4] + 8001082: 091b lsrs r3, r3, #4 + 8001084: f003 0201 and.w r2, r3, #1 + 8001088: 697b ldr r3, [r7, #20] + 800108a: fa02 f303 lsl.w r3, r2, r3 + 800108e: 693a ldr r2, [r7, #16] + 8001090: 4313 orrs r3, r2 + 8001092: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8001094: 687b ldr r3, [r7, #4] + 8001096: 693a ldr r2, [r7, #16] + 8001098: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 800109a: 683b ldr r3, [r7, #0] + 800109c: 685b ldr r3, [r3, #4] + 800109e: f003 0303 and.w r3, r3, #3 + 80010a2: 2b03 cmp r3, #3 + 80010a4: d017 beq.n 80010d6 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 80010a6: 687b ldr r3, [r7, #4] + 80010a8: 68db ldr r3, [r3, #12] + 80010aa: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 80010ac: 697b ldr r3, [r7, #20] + 80010ae: 005b lsls r3, r3, #1 + 80010b0: 2203 movs r2, #3 + 80010b2: fa02 f303 lsl.w r3, r2, r3 + 80010b6: 43db mvns r3, r3 + 80010b8: 693a ldr r2, [r7, #16] + 80010ba: 4013 ands r3, r2 + 80010bc: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 80010be: 683b ldr r3, [r7, #0] + 80010c0: 689a ldr r2, [r3, #8] + 80010c2: 697b ldr r3, [r7, #20] + 80010c4: 005b lsls r3, r3, #1 + 80010c6: fa02 f303 lsl.w r3, r2, r3 + 80010ca: 693a ldr r2, [r7, #16] + 80010cc: 4313 orrs r3, r2 + 80010ce: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 80010d0: 687b ldr r3, [r7, #4] + 80010d2: 693a ldr r2, [r7, #16] + 80010d4: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 80010d6: 683b ldr r3, [r7, #0] + 80010d8: 685b ldr r3, [r3, #4] + 80010da: f003 0303 and.w r3, r3, #3 + 80010de: 2b02 cmp r3, #2 + 80010e0: d123 bne.n 800112a + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 80010e2: 697b ldr r3, [r7, #20] + 80010e4: 08da lsrs r2, r3, #3 + 80010e6: 687b ldr r3, [r7, #4] + 80010e8: 3208 adds r2, #8 + 80010ea: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80010ee: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 80010f0: 697b ldr r3, [r7, #20] + 80010f2: f003 0307 and.w r3, r3, #7 + 80010f6: 009b lsls r3, r3, #2 + 80010f8: 220f movs r2, #15 + 80010fa: fa02 f303 lsl.w r3, r2, r3 + 80010fe: 43db mvns r3, r3 + 8001100: 693a ldr r2, [r7, #16] + 8001102: 4013 ands r3, r2 + 8001104: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8001106: 683b ldr r3, [r7, #0] + 8001108: 691a ldr r2, [r3, #16] + 800110a: 697b ldr r3, [r7, #20] + 800110c: f003 0307 and.w r3, r3, #7 + 8001110: 009b lsls r3, r3, #2 + 8001112: fa02 f303 lsl.w r3, r2, r3 + 8001116: 693a ldr r2, [r7, #16] + 8001118: 4313 orrs r3, r2 + 800111a: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 800111c: 697b ldr r3, [r7, #20] + 800111e: 08da lsrs r2, r3, #3 + 8001120: 687b ldr r3, [r7, #4] + 8001122: 3208 adds r2, #8 + 8001124: 6939 ldr r1, [r7, #16] + 8001126: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 800112a: 687b ldr r3, [r7, #4] + 800112c: 681b ldr r3, [r3, #0] + 800112e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8001130: 697b ldr r3, [r7, #20] + 8001132: 005b lsls r3, r3, #1 + 8001134: 2203 movs r2, #3 + 8001136: fa02 f303 lsl.w r3, r2, r3 + 800113a: 43db mvns r3, r3 + 800113c: 693a ldr r2, [r7, #16] + 800113e: 4013 ands r3, r2 + 8001140: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8001142: 683b ldr r3, [r7, #0] + 8001144: 685b ldr r3, [r3, #4] + 8001146: f003 0203 and.w r2, r3, #3 + 800114a: 697b ldr r3, [r7, #20] + 800114c: 005b lsls r3, r3, #1 + 800114e: fa02 f303 lsl.w r3, r2, r3 + 8001152: 693a ldr r2, [r7, #16] + 8001154: 4313 orrs r3, r2 + 8001156: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8001158: 687b ldr r3, [r7, #4] + 800115a: 693a ldr r2, [r7, #16] + 800115c: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 800115e: 683b ldr r3, [r7, #0] + 8001160: 685b ldr r3, [r3, #4] + 8001162: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001166: 2b00 cmp r3, #0 + 8001168: f000 80ac beq.w 80012c4 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800116c: 4b5e ldr r3, [pc, #376] @ (80012e8 ) + 800116e: 6a1b ldr r3, [r3, #32] + 8001170: 4a5d ldr r2, [pc, #372] @ (80012e8 ) + 8001172: f043 0301 orr.w r3, r3, #1 + 8001176: 6213 str r3, [r2, #32] + 8001178: 4b5b ldr r3, [pc, #364] @ (80012e8 ) + 800117a: 6a1b ldr r3, [r3, #32] + 800117c: f003 0301 and.w r3, r3, #1 + 8001180: 60bb str r3, [r7, #8] + 8001182: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8001184: 4a59 ldr r2, [pc, #356] @ (80012ec ) + 8001186: 697b ldr r3, [r7, #20] + 8001188: 089b lsrs r3, r3, #2 + 800118a: 3302 adds r3, #2 + 800118c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001190: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 8001192: 697b ldr r3, [r7, #20] + 8001194: f003 0303 and.w r3, r3, #3 + 8001198: 009b lsls r3, r3, #2 + 800119a: 220f movs r2, #15 + 800119c: fa02 f303 lsl.w r3, r2, r3 + 80011a0: 43db mvns r3, r3 + 80011a2: 693a ldr r2, [r7, #16] + 80011a4: 4013 ands r3, r2 + 80011a6: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 80011a8: 687b ldr r3, [r7, #4] + 80011aa: 4a51 ldr r2, [pc, #324] @ (80012f0 ) + 80011ac: 4293 cmp r3, r2 + 80011ae: d025 beq.n 80011fc + 80011b0: 687b ldr r3, [r7, #4] + 80011b2: 4a50 ldr r2, [pc, #320] @ (80012f4 ) + 80011b4: 4293 cmp r3, r2 + 80011b6: d01f beq.n 80011f8 + 80011b8: 687b ldr r3, [r7, #4] + 80011ba: 4a4f ldr r2, [pc, #316] @ (80012f8 ) + 80011bc: 4293 cmp r3, r2 + 80011be: d019 beq.n 80011f4 + 80011c0: 687b ldr r3, [r7, #4] + 80011c2: 4a4e ldr r2, [pc, #312] @ (80012fc ) + 80011c4: 4293 cmp r3, r2 + 80011c6: d013 beq.n 80011f0 + 80011c8: 687b ldr r3, [r7, #4] + 80011ca: 4a4d ldr r2, [pc, #308] @ (8001300 ) + 80011cc: 4293 cmp r3, r2 + 80011ce: d00d beq.n 80011ec + 80011d0: 687b ldr r3, [r7, #4] + 80011d2: 4a4c ldr r2, [pc, #304] @ (8001304 ) + 80011d4: 4293 cmp r3, r2 + 80011d6: d007 beq.n 80011e8 + 80011d8: 687b ldr r3, [r7, #4] + 80011da: 4a4b ldr r2, [pc, #300] @ (8001308 ) + 80011dc: 4293 cmp r3, r2 + 80011de: d101 bne.n 80011e4 + 80011e0: 2306 movs r3, #6 + 80011e2: e00c b.n 80011fe + 80011e4: 2307 movs r3, #7 + 80011e6: e00a b.n 80011fe + 80011e8: 2305 movs r3, #5 + 80011ea: e008 b.n 80011fe + 80011ec: 2304 movs r3, #4 + 80011ee: e006 b.n 80011fe + 80011f0: 2303 movs r3, #3 + 80011f2: e004 b.n 80011fe + 80011f4: 2302 movs r3, #2 + 80011f6: e002 b.n 80011fe + 80011f8: 2301 movs r3, #1 + 80011fa: e000 b.n 80011fe + 80011fc: 2300 movs r3, #0 + 80011fe: 697a ldr r2, [r7, #20] + 8001200: f002 0203 and.w r2, r2, #3 + 8001204: 0092 lsls r2, r2, #2 + 8001206: 4093 lsls r3, r2 + 8001208: 693a ldr r2, [r7, #16] + 800120a: 4313 orrs r3, r2 + 800120c: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 800120e: 4937 ldr r1, [pc, #220] @ (80012ec ) + 8001210: 697b ldr r3, [r7, #20] + 8001212: 089b lsrs r3, r3, #2 + 8001214: 3302 adds r3, #2 + 8001216: 693a ldr r2, [r7, #16] + 8001218: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 800121c: 4b3b ldr r3, [pc, #236] @ (800130c ) + 800121e: 689b ldr r3, [r3, #8] + 8001220: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001222: 68fb ldr r3, [r7, #12] + 8001224: 43db mvns r3, r3 + 8001226: 693a ldr r2, [r7, #16] + 8001228: 4013 ands r3, r2 + 800122a: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 800122c: 683b ldr r3, [r7, #0] + 800122e: 685b ldr r3, [r3, #4] + 8001230: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001234: 2b00 cmp r3, #0 + 8001236: d003 beq.n 8001240 + { + SET_BIT(temp, iocurrent); + 8001238: 693a ldr r2, [r7, #16] + 800123a: 68fb ldr r3, [r7, #12] + 800123c: 4313 orrs r3, r2 + 800123e: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 8001240: 4a32 ldr r2, [pc, #200] @ (800130c ) + 8001242: 693b ldr r3, [r7, #16] + 8001244: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8001246: 4b31 ldr r3, [pc, #196] @ (800130c ) + 8001248: 68db ldr r3, [r3, #12] + 800124a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 800124c: 68fb ldr r3, [r7, #12] + 800124e: 43db mvns r3, r3 + 8001250: 693a ldr r2, [r7, #16] + 8001252: 4013 ands r3, r2 + 8001254: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8001256: 683b ldr r3, [r7, #0] + 8001258: 685b ldr r3, [r3, #4] + 800125a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800125e: 2b00 cmp r3, #0 + 8001260: d003 beq.n 800126a + { + SET_BIT(temp, iocurrent); + 8001262: 693a ldr r2, [r7, #16] + 8001264: 68fb ldr r3, [r7, #12] + 8001266: 4313 orrs r3, r2 + 8001268: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 800126a: 4a28 ldr r2, [pc, #160] @ (800130c ) + 800126c: 693b ldr r3, [r7, #16] + 800126e: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8001270: 4b26 ldr r3, [pc, #152] @ (800130c ) + 8001272: 685b ldr r3, [r3, #4] + 8001274: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001276: 68fb ldr r3, [r7, #12] + 8001278: 43db mvns r3, r3 + 800127a: 693a ldr r2, [r7, #16] + 800127c: 4013 ands r3, r2 + 800127e: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8001280: 683b ldr r3, [r7, #0] + 8001282: 685b ldr r3, [r3, #4] + 8001284: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001288: 2b00 cmp r3, #0 + 800128a: d003 beq.n 8001294 + { + SET_BIT(temp, iocurrent); + 800128c: 693a ldr r2, [r7, #16] + 800128e: 68fb ldr r3, [r7, #12] + 8001290: 4313 orrs r3, r2 + 8001292: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8001294: 4a1d ldr r2, [pc, #116] @ (800130c ) + 8001296: 693b ldr r3, [r7, #16] + 8001298: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 800129a: 4b1c ldr r3, [pc, #112] @ (800130c ) + 800129c: 681b ldr r3, [r3, #0] + 800129e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 80012a0: 68fb ldr r3, [r7, #12] + 80012a2: 43db mvns r3, r3 + 80012a4: 693a ldr r2, [r7, #16] + 80012a6: 4013 ands r3, r2 + 80012a8: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 80012aa: 683b ldr r3, [r7, #0] + 80012ac: 685b ldr r3, [r3, #4] + 80012ae: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80012b2: 2b00 cmp r3, #0 + 80012b4: d003 beq.n 80012be + { + SET_BIT(temp, iocurrent); + 80012b6: 693a ldr r2, [r7, #16] + 80012b8: 68fb ldr r3, [r7, #12] + 80012ba: 4313 orrs r3, r2 + 80012bc: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 80012be: 4a13 ldr r2, [pc, #76] @ (800130c ) + 80012c0: 693b ldr r3, [r7, #16] + 80012c2: 6013 str r3, [r2, #0] + } + } + + position++; + 80012c4: 697b ldr r3, [r7, #20] + 80012c6: 3301 adds r3, #1 + 80012c8: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 80012ca: 683b ldr r3, [r7, #0] + 80012cc: 681a ldr r2, [r3, #0] + 80012ce: 697b ldr r3, [r7, #20] + 80012d0: fa22 f303 lsr.w r3, r2, r3 + 80012d4: 2b00 cmp r3, #0 + 80012d6: f47f ae97 bne.w 8001008 + } +} + 80012da: bf00 nop + 80012dc: bf00 nop + 80012de: 371c adds r7, #28 + 80012e0: 46bd mov sp, r7 + 80012e2: bc80 pop {r7} + 80012e4: 4770 bx lr + 80012e6: bf00 nop + 80012e8: 40023800 .word 0x40023800 + 80012ec: 40010000 .word 0x40010000 + 80012f0: 40020000 .word 0x40020000 + 80012f4: 40020400 .word 0x40020400 + 80012f8: 40020800 .word 0x40020800 + 80012fc: 40020c00 .word 0x40020c00 + 8001300: 40021000 .word 0x40021000 + 8001304: 40021400 .word 0x40021400 + 8001308: 40021800 .word 0x40021800 + 800130c: 40010400 .word 0x40010400 + +08001310 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8001310: b480 push {r7} + 8001312: b083 sub sp, #12 + 8001314: af00 add r7, sp, #0 + 8001316: 6078 str r0, [r7, #4] + 8001318: 460b mov r3, r1 + 800131a: 807b strh r3, [r7, #2] + 800131c: 4613 mov r3, r2 + 800131e: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8001320: 787b ldrb r3, [r7, #1] + 8001322: 2b00 cmp r3, #0 + 8001324: d003 beq.n 800132e + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8001326: 887a ldrh r2, [r7, #2] + 8001328: 687b ldr r3, [r7, #4] + 800132a: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 800132c: e003 b.n 8001336 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 800132e: 887b ldrh r3, [r7, #2] + 8001330: 041a lsls r2, r3, #16 + 8001332: 687b ldr r3, [r7, #4] + 8001334: 619a str r2, [r3, #24] +} + 8001336: bf00 nop + 8001338: 370c adds r7, #12 + 800133a: 46bd mov sp, r7 + 800133c: bc80 pop {r7} + 800133e: 4770 bx lr + +08001340 : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 8001340: b580 push {r7, lr} + 8001342: b082 sub sp, #8 + 8001344: af00 add r7, sp, #0 + 8001346: 4603 mov r3, r0 + 8001348: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 800134a: 4b08 ldr r3, [pc, #32] @ (800136c ) + 800134c: 695a ldr r2, [r3, #20] + 800134e: 88fb ldrh r3, [r7, #6] + 8001350: 4013 ands r3, r2 + 8001352: 2b00 cmp r3, #0 + 8001354: d006 beq.n 8001364 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 8001356: 4a05 ldr r2, [pc, #20] @ (800136c ) + 8001358: 88fb ldrh r3, [r7, #6] + 800135a: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 800135c: 88fb ldrh r3, [r7, #6] + 800135e: 4618 mov r0, r3 + 8001360: f000 f806 bl 8001370 + } +} + 8001364: bf00 nop + 8001366: 3708 adds r7, #8 + 8001368: 46bd mov sp, r7 + 800136a: bd80 pop {r7, pc} + 800136c: 40010400 .word 0x40010400 + +08001370 : + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 8001370: b480 push {r7} + 8001372: b083 sub sp, #12 + 8001374: af00 add r7, sp, #0 + 8001376: 4603 mov r3, r0 + 8001378: 80fb strh r3, [r7, #6] + UNUSED(GPIO_Pin); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + 800137a: bf00 nop + 800137c: 370c adds r7, #12 + 800137e: 46bd mov sp, r7 + 8001380: bc80 pop {r7} + 8001382: 4770 bx lr + +08001384 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8001384: b580 push {r7, lr} + 8001386: b088 sub sp, #32 + 8001388: af00 add r7, sp, #0 + 800138a: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 800138c: 687b ldr r3, [r7, #4] + 800138e: 2b00 cmp r3, #0 + 8001390: d101 bne.n 8001396 + { + return HAL_ERROR; + 8001392: 2301 movs r3, #1 + 8001394: e31d b.n 80019d2 + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8001396: 4b94 ldr r3, [pc, #592] @ (80015e8 ) + 8001398: 689b ldr r3, [r3, #8] + 800139a: f003 030c and.w r3, r3, #12 + 800139e: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80013a0: 4b91 ldr r3, [pc, #580] @ (80015e8 ) + 80013a2: 689b ldr r3, [r3, #8] + 80013a4: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80013a8: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80013aa: 687b ldr r3, [r7, #4] + 80013ac: 681b ldr r3, [r3, #0] + 80013ae: f003 0301 and.w r3, r3, #1 + 80013b2: 2b00 cmp r3, #0 + 80013b4: d07b beq.n 80014ae + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 80013b6: 69bb ldr r3, [r7, #24] + 80013b8: 2b08 cmp r3, #8 + 80013ba: d006 beq.n 80013ca + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 80013bc: 69bb ldr r3, [r7, #24] + 80013be: 2b0c cmp r3, #12 + 80013c0: d10f bne.n 80013e2 + 80013c2: 697b ldr r3, [r7, #20] + 80013c4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80013c8: d10b bne.n 80013e2 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80013ca: 4b87 ldr r3, [pc, #540] @ (80015e8 ) + 80013cc: 681b ldr r3, [r3, #0] + 80013ce: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80013d2: 2b00 cmp r3, #0 + 80013d4: d06a beq.n 80014ac + 80013d6: 687b ldr r3, [r7, #4] + 80013d8: 685b ldr r3, [r3, #4] + 80013da: 2b00 cmp r3, #0 + 80013dc: d166 bne.n 80014ac + { + return HAL_ERROR; + 80013de: 2301 movs r3, #1 + 80013e0: e2f7 b.n 80019d2 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80013e2: 687b ldr r3, [r7, #4] + 80013e4: 685b ldr r3, [r3, #4] + 80013e6: 2b01 cmp r3, #1 + 80013e8: d106 bne.n 80013f8 + 80013ea: 4b7f ldr r3, [pc, #508] @ (80015e8 ) + 80013ec: 681b ldr r3, [r3, #0] + 80013ee: 4a7e ldr r2, [pc, #504] @ (80015e8 ) + 80013f0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80013f4: 6013 str r3, [r2, #0] + 80013f6: e02d b.n 8001454 + 80013f8: 687b ldr r3, [r7, #4] + 80013fa: 685b ldr r3, [r3, #4] + 80013fc: 2b00 cmp r3, #0 + 80013fe: d10c bne.n 800141a + 8001400: 4b79 ldr r3, [pc, #484] @ (80015e8 ) + 8001402: 681b ldr r3, [r3, #0] + 8001404: 4a78 ldr r2, [pc, #480] @ (80015e8 ) + 8001406: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800140a: 6013 str r3, [r2, #0] + 800140c: 4b76 ldr r3, [pc, #472] @ (80015e8 ) + 800140e: 681b ldr r3, [r3, #0] + 8001410: 4a75 ldr r2, [pc, #468] @ (80015e8 ) + 8001412: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001416: 6013 str r3, [r2, #0] + 8001418: e01c b.n 8001454 + 800141a: 687b ldr r3, [r7, #4] + 800141c: 685b ldr r3, [r3, #4] + 800141e: 2b05 cmp r3, #5 + 8001420: d10c bne.n 800143c + 8001422: 4b71 ldr r3, [pc, #452] @ (80015e8 ) + 8001424: 681b ldr r3, [r3, #0] + 8001426: 4a70 ldr r2, [pc, #448] @ (80015e8 ) + 8001428: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 800142c: 6013 str r3, [r2, #0] + 800142e: 4b6e ldr r3, [pc, #440] @ (80015e8 ) + 8001430: 681b ldr r3, [r3, #0] + 8001432: 4a6d ldr r2, [pc, #436] @ (80015e8 ) + 8001434: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001438: 6013 str r3, [r2, #0] + 800143a: e00b b.n 8001454 + 800143c: 4b6a ldr r3, [pc, #424] @ (80015e8 ) + 800143e: 681b ldr r3, [r3, #0] + 8001440: 4a69 ldr r2, [pc, #420] @ (80015e8 ) + 8001442: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001446: 6013 str r3, [r2, #0] + 8001448: 4b67 ldr r3, [pc, #412] @ (80015e8 ) + 800144a: 681b ldr r3, [r3, #0] + 800144c: 4a66 ldr r2, [pc, #408] @ (80015e8 ) + 800144e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001452: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8001454: 687b ldr r3, [r7, #4] + 8001456: 685b ldr r3, [r3, #4] + 8001458: 2b00 cmp r3, #0 + 800145a: d013 beq.n 8001484 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800145c: f7ff fc8e bl 8000d7c + 8001460: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001462: e008 b.n 8001476 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001464: f7ff fc8a bl 8000d7c + 8001468: 4602 mov r2, r0 + 800146a: 693b ldr r3, [r7, #16] + 800146c: 1ad3 subs r3, r2, r3 + 800146e: 2b64 cmp r3, #100 @ 0x64 + 8001470: d901 bls.n 8001476 + { + return HAL_TIMEOUT; + 8001472: 2303 movs r3, #3 + 8001474: e2ad b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001476: 4b5c ldr r3, [pc, #368] @ (80015e8 ) + 8001478: 681b ldr r3, [r3, #0] + 800147a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800147e: 2b00 cmp r3, #0 + 8001480: d0f0 beq.n 8001464 + 8001482: e014 b.n 80014ae + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001484: f7ff fc7a bl 8000d7c + 8001488: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 800148a: e008 b.n 800149e + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 800148c: f7ff fc76 bl 8000d7c + 8001490: 4602 mov r2, r0 + 8001492: 693b ldr r3, [r7, #16] + 8001494: 1ad3 subs r3, r2, r3 + 8001496: 2b64 cmp r3, #100 @ 0x64 + 8001498: d901 bls.n 800149e + { + return HAL_TIMEOUT; + 800149a: 2303 movs r3, #3 + 800149c: e299 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 800149e: 4b52 ldr r3, [pc, #328] @ (80015e8 ) + 80014a0: 681b ldr r3, [r3, #0] + 80014a2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80014a6: 2b00 cmp r3, #0 + 80014a8: d1f0 bne.n 800148c + 80014aa: e000 b.n 80014ae + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80014ac: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80014ae: 687b ldr r3, [r7, #4] + 80014b0: 681b ldr r3, [r3, #0] + 80014b2: f003 0302 and.w r3, r3, #2 + 80014b6: 2b00 cmp r3, #0 + 80014b8: d05a beq.n 8001570 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 80014ba: 69bb ldr r3, [r7, #24] + 80014bc: 2b04 cmp r3, #4 + 80014be: d005 beq.n 80014cc + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 80014c0: 69bb ldr r3, [r7, #24] + 80014c2: 2b0c cmp r3, #12 + 80014c4: d119 bne.n 80014fa + 80014c6: 697b ldr r3, [r7, #20] + 80014c8: 2b00 cmp r3, #0 + 80014ca: d116 bne.n 80014fa + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80014cc: 4b46 ldr r3, [pc, #280] @ (80015e8 ) + 80014ce: 681b ldr r3, [r3, #0] + 80014d0: f003 0302 and.w r3, r3, #2 + 80014d4: 2b00 cmp r3, #0 + 80014d6: d005 beq.n 80014e4 + 80014d8: 687b ldr r3, [r7, #4] + 80014da: 68db ldr r3, [r3, #12] + 80014dc: 2b01 cmp r3, #1 + 80014de: d001 beq.n 80014e4 + { + return HAL_ERROR; + 80014e0: 2301 movs r3, #1 + 80014e2: e276 b.n 80019d2 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80014e4: 4b40 ldr r3, [pc, #256] @ (80015e8 ) + 80014e6: 685b ldr r3, [r3, #4] + 80014e8: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 80014ec: 687b ldr r3, [r7, #4] + 80014ee: 691b ldr r3, [r3, #16] + 80014f0: 021b lsls r3, r3, #8 + 80014f2: 493d ldr r1, [pc, #244] @ (80015e8 ) + 80014f4: 4313 orrs r3, r2 + 80014f6: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80014f8: e03a b.n 8001570 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 80014fa: 687b ldr r3, [r7, #4] + 80014fc: 68db ldr r3, [r3, #12] + 80014fe: 2b00 cmp r3, #0 + 8001500: d020 beq.n 8001544 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8001502: 4b3a ldr r3, [pc, #232] @ (80015ec ) + 8001504: 2201 movs r2, #1 + 8001506: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001508: f7ff fc38 bl 8000d7c + 800150c: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800150e: e008 b.n 8001522 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001510: f7ff fc34 bl 8000d7c + 8001514: 4602 mov r2, r0 + 8001516: 693b ldr r3, [r7, #16] + 8001518: 1ad3 subs r3, r2, r3 + 800151a: 2b02 cmp r3, #2 + 800151c: d901 bls.n 8001522 + { + return HAL_TIMEOUT; + 800151e: 2303 movs r3, #3 + 8001520: e257 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001522: 4b31 ldr r3, [pc, #196] @ (80015e8 ) + 8001524: 681b ldr r3, [r3, #0] + 8001526: f003 0302 and.w r3, r3, #2 + 800152a: 2b00 cmp r3, #0 + 800152c: d0f0 beq.n 8001510 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800152e: 4b2e ldr r3, [pc, #184] @ (80015e8 ) + 8001530: 685b ldr r3, [r3, #4] + 8001532: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001536: 687b ldr r3, [r7, #4] + 8001538: 691b ldr r3, [r3, #16] + 800153a: 021b lsls r3, r3, #8 + 800153c: 492a ldr r1, [pc, #168] @ (80015e8 ) + 800153e: 4313 orrs r3, r2 + 8001540: 604b str r3, [r1, #4] + 8001542: e015 b.n 8001570 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8001544: 4b29 ldr r3, [pc, #164] @ (80015ec ) + 8001546: 2200 movs r2, #0 + 8001548: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800154a: f7ff fc17 bl 8000d7c + 800154e: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001550: e008 b.n 8001564 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8001552: f7ff fc13 bl 8000d7c + 8001556: 4602 mov r2, r0 + 8001558: 693b ldr r3, [r7, #16] + 800155a: 1ad3 subs r3, r2, r3 + 800155c: 2b02 cmp r3, #2 + 800155e: d901 bls.n 8001564 + { + return HAL_TIMEOUT; + 8001560: 2303 movs r3, #3 + 8001562: e236 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001564: 4b20 ldr r3, [pc, #128] @ (80015e8 ) + 8001566: 681b ldr r3, [r3, #0] + 8001568: f003 0302 and.w r3, r3, #2 + 800156c: 2b00 cmp r3, #0 + 800156e: d1f0 bne.n 8001552 + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8001570: 687b ldr r3, [r7, #4] + 8001572: 681b ldr r3, [r3, #0] + 8001574: f003 0310 and.w r3, r3, #16 + 8001578: 2b00 cmp r3, #0 + 800157a: f000 80b8 beq.w 80016ee + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 800157e: 69bb ldr r3, [r7, #24] + 8001580: 2b00 cmp r3, #0 + 8001582: d170 bne.n 8001666 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8001584: 4b18 ldr r3, [pc, #96] @ (80015e8 ) + 8001586: 681b ldr r3, [r3, #0] + 8001588: f403 7300 and.w r3, r3, #512 @ 0x200 + 800158c: 2b00 cmp r3, #0 + 800158e: d005 beq.n 800159c + 8001590: 687b ldr r3, [r7, #4] + 8001592: 699b ldr r3, [r3, #24] + 8001594: 2b00 cmp r3, #0 + 8001596: d101 bne.n 800159c + { + return HAL_ERROR; + 8001598: 2301 movs r3, #1 + 800159a: e21a b.n 80019d2 + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 800159c: 687b ldr r3, [r7, #4] + 800159e: 6a1a ldr r2, [r3, #32] + 80015a0: 4b11 ldr r3, [pc, #68] @ (80015e8 ) + 80015a2: 685b ldr r3, [r3, #4] + 80015a4: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 80015a8: 429a cmp r2, r3 + 80015aa: d921 bls.n 80015f0 + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80015ac: 687b ldr r3, [r7, #4] + 80015ae: 6a1b ldr r3, [r3, #32] + 80015b0: 4618 mov r0, r3 + 80015b2: f000 fc09 bl 8001dc8 + 80015b6: 4603 mov r3, r0 + 80015b8: 2b00 cmp r3, #0 + 80015ba: d001 beq.n 80015c0 + { + return HAL_ERROR; + 80015bc: 2301 movs r3, #1 + 80015be: e208 b.n 80019d2 + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80015c0: 4b09 ldr r3, [pc, #36] @ (80015e8 ) + 80015c2: 685b ldr r3, [r3, #4] + 80015c4: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80015c8: 687b ldr r3, [r7, #4] + 80015ca: 6a1b ldr r3, [r3, #32] + 80015cc: 4906 ldr r1, [pc, #24] @ (80015e8 ) + 80015ce: 4313 orrs r3, r2 + 80015d0: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80015d2: 4b05 ldr r3, [pc, #20] @ (80015e8 ) + 80015d4: 685b ldr r3, [r3, #4] + 80015d6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80015da: 687b ldr r3, [r7, #4] + 80015dc: 69db ldr r3, [r3, #28] + 80015de: 061b lsls r3, r3, #24 + 80015e0: 4901 ldr r1, [pc, #4] @ (80015e8 ) + 80015e2: 4313 orrs r3, r2 + 80015e4: 604b str r3, [r1, #4] + 80015e6: e020 b.n 800162a + 80015e8: 40023800 .word 0x40023800 + 80015ec: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80015f0: 4b99 ldr r3, [pc, #612] @ (8001858 ) + 80015f2: 685b ldr r3, [r3, #4] + 80015f4: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80015f8: 687b ldr r3, [r7, #4] + 80015fa: 6a1b ldr r3, [r3, #32] + 80015fc: 4996 ldr r1, [pc, #600] @ (8001858 ) + 80015fe: 4313 orrs r3, r2 + 8001600: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001602: 4b95 ldr r3, [pc, #596] @ (8001858 ) + 8001604: 685b ldr r3, [r3, #4] + 8001606: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 800160a: 687b ldr r3, [r7, #4] + 800160c: 69db ldr r3, [r3, #28] + 800160e: 061b lsls r3, r3, #24 + 8001610: 4991 ldr r1, [pc, #580] @ (8001858 ) + 8001612: 4313 orrs r3, r2 + 8001614: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001616: 687b ldr r3, [r7, #4] + 8001618: 6a1b ldr r3, [r3, #32] + 800161a: 4618 mov r0, r3 + 800161c: f000 fbd4 bl 8001dc8 + 8001620: 4603 mov r3, r0 + 8001622: 2b00 cmp r3, #0 + 8001624: d001 beq.n 800162a + { + return HAL_ERROR; + 8001626: 2301 movs r3, #1 + 8001628: e1d3 b.n 80019d2 + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 800162a: 687b ldr r3, [r7, #4] + 800162c: 6a1b ldr r3, [r3, #32] + 800162e: 0b5b lsrs r3, r3, #13 + 8001630: 3301 adds r3, #1 + 8001632: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001636: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 800163a: 4a87 ldr r2, [pc, #540] @ (8001858 ) + 800163c: 6892 ldr r2, [r2, #8] + 800163e: 0912 lsrs r2, r2, #4 + 8001640: f002 020f and.w r2, r2, #15 + 8001644: 4985 ldr r1, [pc, #532] @ (800185c ) + 8001646: 5c8a ldrb r2, [r1, r2] + 8001648: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 800164a: 4a85 ldr r2, [pc, #532] @ (8001860 ) + 800164c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 800164e: 4b85 ldr r3, [pc, #532] @ (8001864 ) + 8001650: 681b ldr r3, [r3, #0] + 8001652: 4618 mov r0, r3 + 8001654: f7ff fb46 bl 8000ce4 + 8001658: 4603 mov r3, r0 + 800165a: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 800165c: 7bfb ldrb r3, [r7, #15] + 800165e: 2b00 cmp r3, #0 + 8001660: d045 beq.n 80016ee + { + return status; + 8001662: 7bfb ldrb r3, [r7, #15] + 8001664: e1b5 b.n 80019d2 + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8001666: 687b ldr r3, [r7, #4] + 8001668: 699b ldr r3, [r3, #24] + 800166a: 2b00 cmp r3, #0 + 800166c: d029 beq.n 80016c2 + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 800166e: 4b7e ldr r3, [pc, #504] @ (8001868 ) + 8001670: 2201 movs r2, #1 + 8001672: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001674: f7ff fb82 bl 8000d7c + 8001678: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800167a: e008 b.n 800168e + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 800167c: f7ff fb7e bl 8000d7c + 8001680: 4602 mov r2, r0 + 8001682: 693b ldr r3, [r7, #16] + 8001684: 1ad3 subs r3, r2, r3 + 8001686: 2b02 cmp r3, #2 + 8001688: d901 bls.n 800168e + { + return HAL_TIMEOUT; + 800168a: 2303 movs r3, #3 + 800168c: e1a1 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800168e: 4b72 ldr r3, [pc, #456] @ (8001858 ) + 8001690: 681b ldr r3, [r3, #0] + 8001692: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001696: 2b00 cmp r3, #0 + 8001698: d0f0 beq.n 800167c + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800169a: 4b6f ldr r3, [pc, #444] @ (8001858 ) + 800169c: 685b ldr r3, [r3, #4] + 800169e: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80016a2: 687b ldr r3, [r7, #4] + 80016a4: 6a1b ldr r3, [r3, #32] + 80016a6: 496c ldr r1, [pc, #432] @ (8001858 ) + 80016a8: 4313 orrs r3, r2 + 80016aa: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80016ac: 4b6a ldr r3, [pc, #424] @ (8001858 ) + 80016ae: 685b ldr r3, [r3, #4] + 80016b0: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80016b4: 687b ldr r3, [r7, #4] + 80016b6: 69db ldr r3, [r3, #28] + 80016b8: 061b lsls r3, r3, #24 + 80016ba: 4967 ldr r1, [pc, #412] @ (8001858 ) + 80016bc: 4313 orrs r3, r2 + 80016be: 604b str r3, [r1, #4] + 80016c0: e015 b.n 80016ee + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 80016c2: 4b69 ldr r3, [pc, #420] @ (8001868 ) + 80016c4: 2200 movs r2, #0 + 80016c6: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80016c8: f7ff fb58 bl 8000d7c + 80016cc: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80016ce: e008 b.n 80016e2 + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80016d0: f7ff fb54 bl 8000d7c + 80016d4: 4602 mov r2, r0 + 80016d6: 693b ldr r3, [r7, #16] + 80016d8: 1ad3 subs r3, r2, r3 + 80016da: 2b02 cmp r3, #2 + 80016dc: d901 bls.n 80016e2 + { + return HAL_TIMEOUT; + 80016de: 2303 movs r3, #3 + 80016e0: e177 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80016e2: 4b5d ldr r3, [pc, #372] @ (8001858 ) + 80016e4: 681b ldr r3, [r3, #0] + 80016e6: f403 7300 and.w r3, r3, #512 @ 0x200 + 80016ea: 2b00 cmp r3, #0 + 80016ec: d1f0 bne.n 80016d0 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80016ee: 687b ldr r3, [r7, #4] + 80016f0: 681b ldr r3, [r3, #0] + 80016f2: f003 0308 and.w r3, r3, #8 + 80016f6: 2b00 cmp r3, #0 + 80016f8: d030 beq.n 800175c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 80016fa: 687b ldr r3, [r7, #4] + 80016fc: 695b ldr r3, [r3, #20] + 80016fe: 2b00 cmp r3, #0 + 8001700: d016 beq.n 8001730 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8001702: 4b5a ldr r3, [pc, #360] @ (800186c ) + 8001704: 2201 movs r2, #1 + 8001706: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001708: f7ff fb38 bl 8000d7c + 800170c: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800170e: e008 b.n 8001722 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8001710: f7ff fb34 bl 8000d7c + 8001714: 4602 mov r2, r0 + 8001716: 693b ldr r3, [r7, #16] + 8001718: 1ad3 subs r3, r2, r3 + 800171a: 2b02 cmp r3, #2 + 800171c: d901 bls.n 8001722 + { + return HAL_TIMEOUT; + 800171e: 2303 movs r3, #3 + 8001720: e157 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8001722: 4b4d ldr r3, [pc, #308] @ (8001858 ) + 8001724: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001726: f003 0302 and.w r3, r3, #2 + 800172a: 2b00 cmp r3, #0 + 800172c: d0f0 beq.n 8001710 + 800172e: e015 b.n 800175c + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8001730: 4b4e ldr r3, [pc, #312] @ (800186c ) + 8001732: 2200 movs r2, #0 + 8001734: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001736: f7ff fb21 bl 8000d7c + 800173a: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 800173c: e008 b.n 8001750 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800173e: f7ff fb1d bl 8000d7c + 8001742: 4602 mov r2, r0 + 8001744: 693b ldr r3, [r7, #16] + 8001746: 1ad3 subs r3, r2, r3 + 8001748: 2b02 cmp r3, #2 + 800174a: d901 bls.n 8001750 + { + return HAL_TIMEOUT; + 800174c: 2303 movs r3, #3 + 800174e: e140 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001750: 4b41 ldr r3, [pc, #260] @ (8001858 ) + 8001752: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001754: f003 0302 and.w r3, r3, #2 + 8001758: 2b00 cmp r3, #0 + 800175a: d1f0 bne.n 800173e + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800175c: 687b ldr r3, [r7, #4] + 800175e: 681b ldr r3, [r3, #0] + 8001760: f003 0304 and.w r3, r3, #4 + 8001764: 2b00 cmp r3, #0 + 8001766: f000 80b5 beq.w 80018d4 + { + FlagStatus pwrclkchanged = RESET; + 800176a: 2300 movs r3, #0 + 800176c: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800176e: 4b3a ldr r3, [pc, #232] @ (8001858 ) + 8001770: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001772: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001776: 2b00 cmp r3, #0 + 8001778: d10d bne.n 8001796 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 800177a: 4b37 ldr r3, [pc, #220] @ (8001858 ) + 800177c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800177e: 4a36 ldr r2, [pc, #216] @ (8001858 ) + 8001780: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001784: 6253 str r3, [r2, #36] @ 0x24 + 8001786: 4b34 ldr r3, [pc, #208] @ (8001858 ) + 8001788: 6a5b ldr r3, [r3, #36] @ 0x24 + 800178a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800178e: 60bb str r3, [r7, #8] + 8001790: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8001792: 2301 movs r3, #1 + 8001794: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001796: 4b36 ldr r3, [pc, #216] @ (8001870 ) + 8001798: 681b ldr r3, [r3, #0] + 800179a: f403 7380 and.w r3, r3, #256 @ 0x100 + 800179e: 2b00 cmp r3, #0 + 80017a0: d118 bne.n 80017d4 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80017a2: 4b33 ldr r3, [pc, #204] @ (8001870 ) + 80017a4: 681b ldr r3, [r3, #0] + 80017a6: 4a32 ldr r2, [pc, #200] @ (8001870 ) + 80017a8: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80017ac: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80017ae: f7ff fae5 bl 8000d7c + 80017b2: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80017b4: e008 b.n 80017c8 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80017b6: f7ff fae1 bl 8000d7c + 80017ba: 4602 mov r2, r0 + 80017bc: 693b ldr r3, [r7, #16] + 80017be: 1ad3 subs r3, r2, r3 + 80017c0: 2b64 cmp r3, #100 @ 0x64 + 80017c2: d901 bls.n 80017c8 + { + return HAL_TIMEOUT; + 80017c4: 2303 movs r3, #3 + 80017c6: e104 b.n 80019d2 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80017c8: 4b29 ldr r3, [pc, #164] @ (8001870 ) + 80017ca: 681b ldr r3, [r3, #0] + 80017cc: f403 7380 and.w r3, r3, #256 @ 0x100 + 80017d0: 2b00 cmp r3, #0 + 80017d2: d0f0 beq.n 80017b6 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80017d4: 687b ldr r3, [r7, #4] + 80017d6: 689b ldr r3, [r3, #8] + 80017d8: 2b01 cmp r3, #1 + 80017da: d106 bne.n 80017ea + 80017dc: 4b1e ldr r3, [pc, #120] @ (8001858 ) + 80017de: 6b5b ldr r3, [r3, #52] @ 0x34 + 80017e0: 4a1d ldr r2, [pc, #116] @ (8001858 ) + 80017e2: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80017e6: 6353 str r3, [r2, #52] @ 0x34 + 80017e8: e02d b.n 8001846 + 80017ea: 687b ldr r3, [r7, #4] + 80017ec: 689b ldr r3, [r3, #8] + 80017ee: 2b00 cmp r3, #0 + 80017f0: d10c bne.n 800180c + 80017f2: 4b19 ldr r3, [pc, #100] @ (8001858 ) + 80017f4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80017f6: 4a18 ldr r2, [pc, #96] @ (8001858 ) + 80017f8: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80017fc: 6353 str r3, [r2, #52] @ 0x34 + 80017fe: 4b16 ldr r3, [pc, #88] @ (8001858 ) + 8001800: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001802: 4a15 ldr r2, [pc, #84] @ (8001858 ) + 8001804: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001808: 6353 str r3, [r2, #52] @ 0x34 + 800180a: e01c b.n 8001846 + 800180c: 687b ldr r3, [r7, #4] + 800180e: 689b ldr r3, [r3, #8] + 8001810: 2b05 cmp r3, #5 + 8001812: d10c bne.n 800182e + 8001814: 4b10 ldr r3, [pc, #64] @ (8001858 ) + 8001816: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001818: 4a0f ldr r2, [pc, #60] @ (8001858 ) + 800181a: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 800181e: 6353 str r3, [r2, #52] @ 0x34 + 8001820: 4b0d ldr r3, [pc, #52] @ (8001858 ) + 8001822: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001824: 4a0c ldr r2, [pc, #48] @ (8001858 ) + 8001826: f443 7380 orr.w r3, r3, #256 @ 0x100 + 800182a: 6353 str r3, [r2, #52] @ 0x34 + 800182c: e00b b.n 8001846 + 800182e: 4b0a ldr r3, [pc, #40] @ (8001858 ) + 8001830: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001832: 4a09 ldr r2, [pc, #36] @ (8001858 ) + 8001834: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001838: 6353 str r3, [r2, #52] @ 0x34 + 800183a: 4b07 ldr r3, [pc, #28] @ (8001858 ) + 800183c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800183e: 4a06 ldr r2, [pc, #24] @ (8001858 ) + 8001840: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001844: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8001846: 687b ldr r3, [r7, #4] + 8001848: 689b ldr r3, [r3, #8] + 800184a: 2b00 cmp r3, #0 + 800184c: d024 beq.n 8001898 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800184e: f7ff fa95 bl 8000d7c + 8001852: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001854: e019 b.n 800188a + 8001856: bf00 nop + 8001858: 40023800 .word 0x40023800 + 800185c: 08002eb0 .word 0x08002eb0 + 8001860: 20000000 .word 0x20000000 + 8001864: 20000004 .word 0x20000004 + 8001868: 42470020 .word 0x42470020 + 800186c: 42470680 .word 0x42470680 + 8001870: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001874: f7ff fa82 bl 8000d7c + 8001878: 4602 mov r2, r0 + 800187a: 693b ldr r3, [r7, #16] + 800187c: 1ad3 subs r3, r2, r3 + 800187e: f241 3288 movw r2, #5000 @ 0x1388 + 8001882: 4293 cmp r3, r2 + 8001884: d901 bls.n 800188a + { + return HAL_TIMEOUT; + 8001886: 2303 movs r3, #3 + 8001888: e0a3 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800188a: 4b54 ldr r3, [pc, #336] @ (80019dc ) + 800188c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800188e: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001892: 2b00 cmp r3, #0 + 8001894: d0ee beq.n 8001874 + 8001896: e014 b.n 80018c2 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001898: f7ff fa70 bl 8000d7c + 800189c: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 800189e: e00a b.n 80018b6 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80018a0: f7ff fa6c bl 8000d7c + 80018a4: 4602 mov r2, r0 + 80018a6: 693b ldr r3, [r7, #16] + 80018a8: 1ad3 subs r3, r2, r3 + 80018aa: f241 3288 movw r2, #5000 @ 0x1388 + 80018ae: 4293 cmp r3, r2 + 80018b0: d901 bls.n 80018b6 + { + return HAL_TIMEOUT; + 80018b2: 2303 movs r3, #3 + 80018b4: e08d b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80018b6: 4b49 ldr r3, [pc, #292] @ (80019dc ) + 80018b8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80018ba: f403 7300 and.w r3, r3, #512 @ 0x200 + 80018be: 2b00 cmp r3, #0 + 80018c0: d1ee bne.n 80018a0 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 80018c2: 7ffb ldrb r3, [r7, #31] + 80018c4: 2b01 cmp r3, #1 + 80018c6: d105 bne.n 80018d4 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80018c8: 4b44 ldr r3, [pc, #272] @ (80019dc ) + 80018ca: 6a5b ldr r3, [r3, #36] @ 0x24 + 80018cc: 4a43 ldr r2, [pc, #268] @ (80019dc ) + 80018ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80018d2: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80018d4: 687b ldr r3, [r7, #4] + 80018d6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80018d8: 2b00 cmp r3, #0 + 80018da: d079 beq.n 80019d0 + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80018dc: 69bb ldr r3, [r7, #24] + 80018de: 2b0c cmp r3, #12 + 80018e0: d056 beq.n 8001990 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80018e2: 687b ldr r3, [r7, #4] + 80018e4: 6a5b ldr r3, [r3, #36] @ 0x24 + 80018e6: 2b02 cmp r3, #2 + 80018e8: d13b bne.n 8001962 + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80018ea: 4b3d ldr r3, [pc, #244] @ (80019e0 ) + 80018ec: 2200 movs r2, #0 + 80018ee: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80018f0: f7ff fa44 bl 8000d7c + 80018f4: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80018f6: e008 b.n 800190a + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80018f8: f7ff fa40 bl 8000d7c + 80018fc: 4602 mov r2, r0 + 80018fe: 693b ldr r3, [r7, #16] + 8001900: 1ad3 subs r3, r2, r3 + 8001902: 2b02 cmp r3, #2 + 8001904: d901 bls.n 800190a + { + return HAL_TIMEOUT; + 8001906: 2303 movs r3, #3 + 8001908: e063 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800190a: 4b34 ldr r3, [pc, #208] @ (80019dc ) + 800190c: 681b ldr r3, [r3, #0] + 800190e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001912: 2b00 cmp r3, #0 + 8001914: d1f0 bne.n 80018f8 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8001916: 4b31 ldr r3, [pc, #196] @ (80019dc ) + 8001918: 689b ldr r3, [r3, #8] + 800191a: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 800191e: 687b ldr r3, [r7, #4] + 8001920: 6a99 ldr r1, [r3, #40] @ 0x28 + 8001922: 687b ldr r3, [r7, #4] + 8001924: 6adb ldr r3, [r3, #44] @ 0x2c + 8001926: 4319 orrs r1, r3 + 8001928: 687b ldr r3, [r7, #4] + 800192a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800192c: 430b orrs r3, r1 + 800192e: 492b ldr r1, [pc, #172] @ (80019dc ) + 8001930: 4313 orrs r3, r2 + 8001932: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8001934: 4b2a ldr r3, [pc, #168] @ (80019e0 ) + 8001936: 2201 movs r2, #1 + 8001938: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800193a: f7ff fa1f bl 8000d7c + 800193e: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001940: e008 b.n 8001954 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001942: f7ff fa1b bl 8000d7c + 8001946: 4602 mov r2, r0 + 8001948: 693b ldr r3, [r7, #16] + 800194a: 1ad3 subs r3, r2, r3 + 800194c: 2b02 cmp r3, #2 + 800194e: d901 bls.n 8001954 + { + return HAL_TIMEOUT; + 8001950: 2303 movs r3, #3 + 8001952: e03e b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001954: 4b21 ldr r3, [pc, #132] @ (80019dc ) + 8001956: 681b ldr r3, [r3, #0] + 8001958: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800195c: 2b00 cmp r3, #0 + 800195e: d0f0 beq.n 8001942 + 8001960: e036 b.n 80019d0 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001962: 4b1f ldr r3, [pc, #124] @ (80019e0 ) + 8001964: 2200 movs r2, #0 + 8001966: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001968: f7ff fa08 bl 8000d7c + 800196c: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800196e: e008 b.n 8001982 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001970: f7ff fa04 bl 8000d7c + 8001974: 4602 mov r2, r0 + 8001976: 693b ldr r3, [r7, #16] + 8001978: 1ad3 subs r3, r2, r3 + 800197a: 2b02 cmp r3, #2 + 800197c: d901 bls.n 8001982 + { + return HAL_TIMEOUT; + 800197e: 2303 movs r3, #3 + 8001980: e027 b.n 80019d2 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001982: 4b16 ldr r3, [pc, #88] @ (80019dc ) + 8001984: 681b ldr r3, [r3, #0] + 8001986: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800198a: 2b00 cmp r3, #0 + 800198c: d1f0 bne.n 8001970 + 800198e: e01f b.n 80019d0 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8001990: 687b ldr r3, [r7, #4] + 8001992: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001994: 2b01 cmp r3, #1 + 8001996: d101 bne.n 800199c + { + return HAL_ERROR; + 8001998: 2301 movs r3, #1 + 800199a: e01a b.n 80019d2 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 800199c: 4b0f ldr r3, [pc, #60] @ (80019dc ) + 800199e: 689b ldr r3, [r3, #8] + 80019a0: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80019a2: 697b ldr r3, [r7, #20] + 80019a4: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 80019a8: 687b ldr r3, [r7, #4] + 80019aa: 6a9b ldr r3, [r3, #40] @ 0x28 + 80019ac: 429a cmp r2, r3 + 80019ae: d10d bne.n 80019cc + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80019b0: 697b ldr r3, [r7, #20] + 80019b2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 80019b6: 687b ldr r3, [r7, #4] + 80019b8: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80019ba: 429a cmp r2, r3 + 80019bc: d106 bne.n 80019cc + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 80019be: 697b ldr r3, [r7, #20] + 80019c0: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 80019c4: 687b ldr r3, [r7, #4] + 80019c6: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80019c8: 429a cmp r2, r3 + 80019ca: d001 beq.n 80019d0 + { + return HAL_ERROR; + 80019cc: 2301 movs r3, #1 + 80019ce: e000 b.n 80019d2 + } + } + } + } + + return HAL_OK; + 80019d0: 2300 movs r3, #0 +} + 80019d2: 4618 mov r0, r3 + 80019d4: 3720 adds r7, #32 + 80019d6: 46bd mov sp, r7 + 80019d8: bd80 pop {r7, pc} + 80019da: bf00 nop + 80019dc: 40023800 .word 0x40023800 + 80019e0: 42470060 .word 0x42470060 + +080019e4 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80019e4: b580 push {r7, lr} + 80019e6: b084 sub sp, #16 + 80019e8: af00 add r7, sp, #0 + 80019ea: 6078 str r0, [r7, #4] + 80019ec: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 80019ee: 687b ldr r3, [r7, #4] + 80019f0: 2b00 cmp r3, #0 + 80019f2: d101 bne.n 80019f8 + { + return HAL_ERROR; + 80019f4: 2301 movs r3, #1 + 80019f6: e11a b.n 8001c2e + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 80019f8: 4b8f ldr r3, [pc, #572] @ (8001c38 ) + 80019fa: 681b ldr r3, [r3, #0] + 80019fc: f003 0301 and.w r3, r3, #1 + 8001a00: 683a ldr r2, [r7, #0] + 8001a02: 429a cmp r2, r3 + 8001a04: d919 bls.n 8001a3a + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001a06: 683b ldr r3, [r7, #0] + 8001a08: 2b01 cmp r3, #1 + 8001a0a: d105 bne.n 8001a18 + 8001a0c: 4b8a ldr r3, [pc, #552] @ (8001c38 ) + 8001a0e: 681b ldr r3, [r3, #0] + 8001a10: 4a89 ldr r2, [pc, #548] @ (8001c38 ) + 8001a12: f043 0304 orr.w r3, r3, #4 + 8001a16: 6013 str r3, [r2, #0] + 8001a18: 4b87 ldr r3, [pc, #540] @ (8001c38 ) + 8001a1a: 681b ldr r3, [r3, #0] + 8001a1c: f023 0201 bic.w r2, r3, #1 + 8001a20: 4985 ldr r1, [pc, #532] @ (8001c38 ) + 8001a22: 683b ldr r3, [r7, #0] + 8001a24: 4313 orrs r3, r2 + 8001a26: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001a28: 4b83 ldr r3, [pc, #524] @ (8001c38 ) + 8001a2a: 681b ldr r3, [r3, #0] + 8001a2c: f003 0301 and.w r3, r3, #1 + 8001a30: 683a ldr r2, [r7, #0] + 8001a32: 429a cmp r2, r3 + 8001a34: d001 beq.n 8001a3a + { + return HAL_ERROR; + 8001a36: 2301 movs r3, #1 + 8001a38: e0f9 b.n 8001c2e + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8001a3a: 687b ldr r3, [r7, #4] + 8001a3c: 681b ldr r3, [r3, #0] + 8001a3e: f003 0302 and.w r3, r3, #2 + 8001a42: 2b00 cmp r3, #0 + 8001a44: d008 beq.n 8001a58 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8001a46: 4b7d ldr r3, [pc, #500] @ (8001c3c ) + 8001a48: 689b ldr r3, [r3, #8] + 8001a4a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8001a4e: 687b ldr r3, [r7, #4] + 8001a50: 689b ldr r3, [r3, #8] + 8001a52: 497a ldr r1, [pc, #488] @ (8001c3c ) + 8001a54: 4313 orrs r3, r2 + 8001a56: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8001a58: 687b ldr r3, [r7, #4] + 8001a5a: 681b ldr r3, [r3, #0] + 8001a5c: f003 0301 and.w r3, r3, #1 + 8001a60: 2b00 cmp r3, #0 + 8001a62: f000 808e beq.w 8001b82 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001a66: 687b ldr r3, [r7, #4] + 8001a68: 685b ldr r3, [r3, #4] + 8001a6a: 2b02 cmp r3, #2 + 8001a6c: d107 bne.n 8001a7e + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001a6e: 4b73 ldr r3, [pc, #460] @ (8001c3c ) + 8001a70: 681b ldr r3, [r3, #0] + 8001a72: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001a76: 2b00 cmp r3, #0 + 8001a78: d121 bne.n 8001abe + { + return HAL_ERROR; + 8001a7a: 2301 movs r3, #1 + 8001a7c: e0d7 b.n 8001c2e + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001a7e: 687b ldr r3, [r7, #4] + 8001a80: 685b ldr r3, [r3, #4] + 8001a82: 2b03 cmp r3, #3 + 8001a84: d107 bne.n 8001a96 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001a86: 4b6d ldr r3, [pc, #436] @ (8001c3c ) + 8001a88: 681b ldr r3, [r3, #0] + 8001a8a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001a8e: 2b00 cmp r3, #0 + 8001a90: d115 bne.n 8001abe + { + return HAL_ERROR; + 8001a92: 2301 movs r3, #1 + 8001a94: e0cb b.n 8001c2e + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001a96: 687b ldr r3, [r7, #4] + 8001a98: 685b ldr r3, [r3, #4] + 8001a9a: 2b01 cmp r3, #1 + 8001a9c: d107 bne.n 8001aae + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001a9e: 4b67 ldr r3, [pc, #412] @ (8001c3c ) + 8001aa0: 681b ldr r3, [r3, #0] + 8001aa2: f003 0302 and.w r3, r3, #2 + 8001aa6: 2b00 cmp r3, #0 + 8001aa8: d109 bne.n 8001abe + { + return HAL_ERROR; + 8001aaa: 2301 movs r3, #1 + 8001aac: e0bf b.n 8001c2e + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001aae: 4b63 ldr r3, [pc, #396] @ (8001c3c ) + 8001ab0: 681b ldr r3, [r3, #0] + 8001ab2: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001ab6: 2b00 cmp r3, #0 + 8001ab8: d101 bne.n 8001abe + { + return HAL_ERROR; + 8001aba: 2301 movs r3, #1 + 8001abc: e0b7 b.n 8001c2e + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8001abe: 4b5f ldr r3, [pc, #380] @ (8001c3c ) + 8001ac0: 689b ldr r3, [r3, #8] + 8001ac2: f023 0203 bic.w r2, r3, #3 + 8001ac6: 687b ldr r3, [r7, #4] + 8001ac8: 685b ldr r3, [r3, #4] + 8001aca: 495c ldr r1, [pc, #368] @ (8001c3c ) + 8001acc: 4313 orrs r3, r2 + 8001ace: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001ad0: f7ff f954 bl 8000d7c + 8001ad4: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001ad6: 687b ldr r3, [r7, #4] + 8001ad8: 685b ldr r3, [r3, #4] + 8001ada: 2b02 cmp r3, #2 + 8001adc: d112 bne.n 8001b04 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001ade: e00a b.n 8001af6 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001ae0: f7ff f94c bl 8000d7c + 8001ae4: 4602 mov r2, r0 + 8001ae6: 68fb ldr r3, [r7, #12] + 8001ae8: 1ad3 subs r3, r2, r3 + 8001aea: f241 3288 movw r2, #5000 @ 0x1388 + 8001aee: 4293 cmp r3, r2 + 8001af0: d901 bls.n 8001af6 + { + return HAL_TIMEOUT; + 8001af2: 2303 movs r3, #3 + 8001af4: e09b b.n 8001c2e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001af6: 4b51 ldr r3, [pc, #324] @ (8001c3c ) + 8001af8: 689b ldr r3, [r3, #8] + 8001afa: f003 030c and.w r3, r3, #12 + 8001afe: 2b08 cmp r3, #8 + 8001b00: d1ee bne.n 8001ae0 + 8001b02: e03e b.n 8001b82 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001b04: 687b ldr r3, [r7, #4] + 8001b06: 685b ldr r3, [r3, #4] + 8001b08: 2b03 cmp r3, #3 + 8001b0a: d112 bne.n 8001b32 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001b0c: e00a b.n 8001b24 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001b0e: f7ff f935 bl 8000d7c + 8001b12: 4602 mov r2, r0 + 8001b14: 68fb ldr r3, [r7, #12] + 8001b16: 1ad3 subs r3, r2, r3 + 8001b18: f241 3288 movw r2, #5000 @ 0x1388 + 8001b1c: 4293 cmp r3, r2 + 8001b1e: d901 bls.n 8001b24 + { + return HAL_TIMEOUT; + 8001b20: 2303 movs r3, #3 + 8001b22: e084 b.n 8001c2e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001b24: 4b45 ldr r3, [pc, #276] @ (8001c3c ) + 8001b26: 689b ldr r3, [r3, #8] + 8001b28: f003 030c and.w r3, r3, #12 + 8001b2c: 2b0c cmp r3, #12 + 8001b2e: d1ee bne.n 8001b0e + 8001b30: e027 b.n 8001b82 + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001b32: 687b ldr r3, [r7, #4] + 8001b34: 685b ldr r3, [r3, #4] + 8001b36: 2b01 cmp r3, #1 + 8001b38: d11d bne.n 8001b76 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001b3a: e00a b.n 8001b52 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001b3c: f7ff f91e bl 8000d7c + 8001b40: 4602 mov r2, r0 + 8001b42: 68fb ldr r3, [r7, #12] + 8001b44: 1ad3 subs r3, r2, r3 + 8001b46: f241 3288 movw r2, #5000 @ 0x1388 + 8001b4a: 4293 cmp r3, r2 + 8001b4c: d901 bls.n 8001b52 + { + return HAL_TIMEOUT; + 8001b4e: 2303 movs r3, #3 + 8001b50: e06d b.n 8001c2e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001b52: 4b3a ldr r3, [pc, #232] @ (8001c3c ) + 8001b54: 689b ldr r3, [r3, #8] + 8001b56: f003 030c and.w r3, r3, #12 + 8001b5a: 2b04 cmp r3, #4 + 8001b5c: d1ee bne.n 8001b3c + 8001b5e: e010 b.n 8001b82 + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001b60: f7ff f90c bl 8000d7c + 8001b64: 4602 mov r2, r0 + 8001b66: 68fb ldr r3, [r7, #12] + 8001b68: 1ad3 subs r3, r2, r3 + 8001b6a: f241 3288 movw r2, #5000 @ 0x1388 + 8001b6e: 4293 cmp r3, r2 + 8001b70: d901 bls.n 8001b76 + { + return HAL_TIMEOUT; + 8001b72: 2303 movs r3, #3 + 8001b74: e05b b.n 8001c2e + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 8001b76: 4b31 ldr r3, [pc, #196] @ (8001c3c ) + 8001b78: 689b ldr r3, [r3, #8] + 8001b7a: f003 030c and.w r3, r3, #12 + 8001b7e: 2b00 cmp r3, #0 + 8001b80: d1ee bne.n 8001b60 + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8001b82: 4b2d ldr r3, [pc, #180] @ (8001c38 ) + 8001b84: 681b ldr r3, [r3, #0] + 8001b86: f003 0301 and.w r3, r3, #1 + 8001b8a: 683a ldr r2, [r7, #0] + 8001b8c: 429a cmp r2, r3 + 8001b8e: d219 bcs.n 8001bc4 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001b90: 683b ldr r3, [r7, #0] + 8001b92: 2b01 cmp r3, #1 + 8001b94: d105 bne.n 8001ba2 + 8001b96: 4b28 ldr r3, [pc, #160] @ (8001c38 ) + 8001b98: 681b ldr r3, [r3, #0] + 8001b9a: 4a27 ldr r2, [pc, #156] @ (8001c38 ) + 8001b9c: f043 0304 orr.w r3, r3, #4 + 8001ba0: 6013 str r3, [r2, #0] + 8001ba2: 4b25 ldr r3, [pc, #148] @ (8001c38 ) + 8001ba4: 681b ldr r3, [r3, #0] + 8001ba6: f023 0201 bic.w r2, r3, #1 + 8001baa: 4923 ldr r1, [pc, #140] @ (8001c38 ) + 8001bac: 683b ldr r3, [r7, #0] + 8001bae: 4313 orrs r3, r2 + 8001bb0: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001bb2: 4b21 ldr r3, [pc, #132] @ (8001c38 ) + 8001bb4: 681b ldr r3, [r3, #0] + 8001bb6: f003 0301 and.w r3, r3, #1 + 8001bba: 683a ldr r2, [r7, #0] + 8001bbc: 429a cmp r2, r3 + 8001bbe: d001 beq.n 8001bc4 + { + return HAL_ERROR; + 8001bc0: 2301 movs r3, #1 + 8001bc2: e034 b.n 8001c2e + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001bc4: 687b ldr r3, [r7, #4] + 8001bc6: 681b ldr r3, [r3, #0] + 8001bc8: f003 0304 and.w r3, r3, #4 + 8001bcc: 2b00 cmp r3, #0 + 8001bce: d008 beq.n 8001be2 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8001bd0: 4b1a ldr r3, [pc, #104] @ (8001c3c ) + 8001bd2: 689b ldr r3, [r3, #8] + 8001bd4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001bd8: 687b ldr r3, [r7, #4] + 8001bda: 68db ldr r3, [r3, #12] + 8001bdc: 4917 ldr r1, [pc, #92] @ (8001c3c ) + 8001bde: 4313 orrs r3, r2 + 8001be0: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001be2: 687b ldr r3, [r7, #4] + 8001be4: 681b ldr r3, [r3, #0] + 8001be6: f003 0308 and.w r3, r3, #8 + 8001bea: 2b00 cmp r3, #0 + 8001bec: d009 beq.n 8001c02 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8001bee: 4b13 ldr r3, [pc, #76] @ (8001c3c ) + 8001bf0: 689b ldr r3, [r3, #8] + 8001bf2: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001bf6: 687b ldr r3, [r7, #4] + 8001bf8: 691b ldr r3, [r3, #16] + 8001bfa: 00db lsls r3, r3, #3 + 8001bfc: 490f ldr r1, [pc, #60] @ (8001c3c ) + 8001bfe: 4313 orrs r3, r2 + 8001c00: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8001c02: f000 f823 bl 8001c4c + 8001c06: 4602 mov r2, r0 + 8001c08: 4b0c ldr r3, [pc, #48] @ (8001c3c ) + 8001c0a: 689b ldr r3, [r3, #8] + 8001c0c: 091b lsrs r3, r3, #4 + 8001c0e: f003 030f and.w r3, r3, #15 + 8001c12: 490b ldr r1, [pc, #44] @ (8001c40 ) + 8001c14: 5ccb ldrb r3, [r1, r3] + 8001c16: fa22 f303 lsr.w r3, r2, r3 + 8001c1a: 4a0a ldr r2, [pc, #40] @ (8001c44 ) + 8001c1c: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001c1e: 4b0a ldr r3, [pc, #40] @ (8001c48 ) + 8001c20: 681b ldr r3, [r3, #0] + 8001c22: 4618 mov r0, r3 + 8001c24: f7ff f85e bl 8000ce4 + 8001c28: 4603 mov r3, r0 + 8001c2a: 72fb strb r3, [r7, #11] + + return status; + 8001c2c: 7afb ldrb r3, [r7, #11] +} + 8001c2e: 4618 mov r0, r3 + 8001c30: 3710 adds r7, #16 + 8001c32: 46bd mov sp, r7 + 8001c34: bd80 pop {r7, pc} + 8001c36: bf00 nop + 8001c38: 40023c00 .word 0x40023c00 + 8001c3c: 40023800 .word 0x40023800 + 8001c40: 08002eb0 .word 0x08002eb0 + 8001c44: 20000000 .word 0x20000000 + 8001c48: 20000004 .word 0x20000004 + +08001c4c : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8001c4c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001c50: b08e sub sp, #56 @ 0x38 + 8001c52: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 8001c54: 4b58 ldr r3, [pc, #352] @ (8001db8 ) + 8001c56: 689b ldr r3, [r3, #8] + 8001c58: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8001c5a: 6afb ldr r3, [r7, #44] @ 0x2c + 8001c5c: f003 030c and.w r3, r3, #12 + 8001c60: 2b0c cmp r3, #12 + 8001c62: d00d beq.n 8001c80 + 8001c64: 2b0c cmp r3, #12 + 8001c66: f200 8092 bhi.w 8001d8e + 8001c6a: 2b04 cmp r3, #4 + 8001c6c: d002 beq.n 8001c74 + 8001c6e: 2b08 cmp r3, #8 + 8001c70: d003 beq.n 8001c7a + 8001c72: e08c b.n 8001d8e + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8001c74: 4b51 ldr r3, [pc, #324] @ (8001dbc ) + 8001c76: 633b str r3, [r7, #48] @ 0x30 + break; + 8001c78: e097 b.n 8001daa + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001c7a: 4b51 ldr r3, [pc, #324] @ (8001dc0 ) + 8001c7c: 633b str r3, [r7, #48] @ 0x30 + break; + 8001c7e: e094 b.n 8001daa + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8001c80: 6afb ldr r3, [r7, #44] @ 0x2c + 8001c82: 0c9b lsrs r3, r3, #18 + 8001c84: f003 020f and.w r2, r3, #15 + 8001c88: 4b4e ldr r3, [pc, #312] @ (8001dc4 ) + 8001c8a: 5c9b ldrb r3, [r3, r2] + 8001c8c: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8001c8e: 6afb ldr r3, [r7, #44] @ 0x2c + 8001c90: 0d9b lsrs r3, r3, #22 + 8001c92: f003 0303 and.w r3, r3, #3 + 8001c96: 3301 adds r3, #1 + 8001c98: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8001c9a: 4b47 ldr r3, [pc, #284] @ (8001db8 ) + 8001c9c: 689b ldr r3, [r3, #8] + 8001c9e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001ca2: 2b00 cmp r3, #0 + 8001ca4: d021 beq.n 8001cea + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001ca6: 6abb ldr r3, [r7, #40] @ 0x28 + 8001ca8: 2200 movs r2, #0 + 8001caa: 61bb str r3, [r7, #24] + 8001cac: 61fa str r2, [r7, #28] + 8001cae: 4b44 ldr r3, [pc, #272] @ (8001dc0 ) + 8001cb0: e9d7 8906 ldrd r8, r9, [r7, #24] + 8001cb4: 464a mov r2, r9 + 8001cb6: fb03 f202 mul.w r2, r3, r2 + 8001cba: 2300 movs r3, #0 + 8001cbc: 4644 mov r4, r8 + 8001cbe: fb04 f303 mul.w r3, r4, r3 + 8001cc2: 4413 add r3, r2 + 8001cc4: 4a3e ldr r2, [pc, #248] @ (8001dc0 ) + 8001cc6: 4644 mov r4, r8 + 8001cc8: fba4 0102 umull r0, r1, r4, r2 + 8001ccc: 440b add r3, r1 + 8001cce: 4619 mov r1, r3 + 8001cd0: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001cd2: 2200 movs r2, #0 + 8001cd4: 613b str r3, [r7, #16] + 8001cd6: 617a str r2, [r7, #20] + 8001cd8: e9d7 2304 ldrd r2, r3, [r7, #16] + 8001cdc: f7fe fa4e bl 800017c <__aeabi_uldivmod> + 8001ce0: 4602 mov r2, r0 + 8001ce2: 460b mov r3, r1 + 8001ce4: 4613 mov r3, r2 + 8001ce6: 637b str r3, [r7, #52] @ 0x34 + 8001ce8: e04e b.n 8001d88 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001cea: 6abb ldr r3, [r7, #40] @ 0x28 + 8001cec: 2200 movs r2, #0 + 8001cee: 469a mov sl, r3 + 8001cf0: 4693 mov fp, r2 + 8001cf2: 4652 mov r2, sl + 8001cf4: 465b mov r3, fp + 8001cf6: f04f 0000 mov.w r0, #0 + 8001cfa: f04f 0100 mov.w r1, #0 + 8001cfe: 0159 lsls r1, r3, #5 + 8001d00: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001d04: 0150 lsls r0, r2, #5 + 8001d06: 4602 mov r2, r0 + 8001d08: 460b mov r3, r1 + 8001d0a: ebb2 080a subs.w r8, r2, sl + 8001d0e: eb63 090b sbc.w r9, r3, fp + 8001d12: f04f 0200 mov.w r2, #0 + 8001d16: f04f 0300 mov.w r3, #0 + 8001d1a: ea4f 1389 mov.w r3, r9, lsl #6 + 8001d1e: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001d22: ea4f 1288 mov.w r2, r8, lsl #6 + 8001d26: ebb2 0408 subs.w r4, r2, r8 + 8001d2a: eb63 0509 sbc.w r5, r3, r9 + 8001d2e: f04f 0200 mov.w r2, #0 + 8001d32: f04f 0300 mov.w r3, #0 + 8001d36: 00eb lsls r3, r5, #3 + 8001d38: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8001d3c: 00e2 lsls r2, r4, #3 + 8001d3e: 4614 mov r4, r2 + 8001d40: 461d mov r5, r3 + 8001d42: eb14 030a adds.w r3, r4, sl + 8001d46: 603b str r3, [r7, #0] + 8001d48: eb45 030b adc.w r3, r5, fp + 8001d4c: 607b str r3, [r7, #4] + 8001d4e: f04f 0200 mov.w r2, #0 + 8001d52: f04f 0300 mov.w r3, #0 + 8001d56: e9d7 4500 ldrd r4, r5, [r7] + 8001d5a: 4629 mov r1, r5 + 8001d5c: 028b lsls r3, r1, #10 + 8001d5e: 4620 mov r0, r4 + 8001d60: 4629 mov r1, r5 + 8001d62: 4604 mov r4, r0 + 8001d64: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8001d68: 4601 mov r1, r0 + 8001d6a: 028a lsls r2, r1, #10 + 8001d6c: 4610 mov r0, r2 + 8001d6e: 4619 mov r1, r3 + 8001d70: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001d72: 2200 movs r2, #0 + 8001d74: 60bb str r3, [r7, #8] + 8001d76: 60fa str r2, [r7, #12] + 8001d78: e9d7 2302 ldrd r2, r3, [r7, #8] + 8001d7c: f7fe f9fe bl 800017c <__aeabi_uldivmod> + 8001d80: 4602 mov r2, r0 + 8001d82: 460b mov r3, r1 + 8001d84: 4613 mov r3, r2 + 8001d86: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 8001d88: 6b7b ldr r3, [r7, #52] @ 0x34 + 8001d8a: 633b str r3, [r7, #48] @ 0x30 + break; + 8001d8c: e00d b.n 8001daa + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8001d8e: 4b0a ldr r3, [pc, #40] @ (8001db8 ) + 8001d90: 685b ldr r3, [r3, #4] + 8001d92: 0b5b lsrs r3, r3, #13 + 8001d94: f003 0307 and.w r3, r3, #7 + 8001d98: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8001d9a: 6a3b ldr r3, [r7, #32] + 8001d9c: 3301 adds r3, #1 + 8001d9e: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001da2: fa02 f303 lsl.w r3, r2, r3 + 8001da6: 633b str r3, [r7, #48] @ 0x30 + break; + 8001da8: bf00 nop + } + } + return sysclockfreq; + 8001daa: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 8001dac: 4618 mov r0, r3 + 8001dae: 3738 adds r7, #56 @ 0x38 + 8001db0: 46bd mov sp, r7 + 8001db2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8001db6: bf00 nop + 8001db8: 40023800 .word 0x40023800 + 8001dbc: 00f42400 .word 0x00f42400 + 8001dc0: 016e3600 .word 0x016e3600 + 8001dc4: 08002ea4 .word 0x08002ea4 + +08001dc8 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 8001dc8: b480 push {r7} + 8001dca: b087 sub sp, #28 + 8001dcc: af00 add r7, sp, #0 + 8001dce: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8001dd0: 2300 movs r3, #0 + 8001dd2: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 8001dd4: 4b29 ldr r3, [pc, #164] @ (8001e7c ) + 8001dd6: 689b ldr r3, [r3, #8] + 8001dd8: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001ddc: 2b00 cmp r3, #0 + 8001dde: d12c bne.n 8001e3a + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 8001de0: 4b26 ldr r3, [pc, #152] @ (8001e7c ) + 8001de2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001de4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001de8: 2b00 cmp r3, #0 + 8001dea: d005 beq.n 8001df8 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001dec: 4b24 ldr r3, [pc, #144] @ (8001e80 ) + 8001dee: 681b ldr r3, [r3, #0] + 8001df0: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001df4: 617b str r3, [r7, #20] + 8001df6: e016 b.n 8001e26 + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001df8: 4b20 ldr r3, [pc, #128] @ (8001e7c ) + 8001dfa: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001dfc: 4a1f ldr r2, [pc, #124] @ (8001e7c ) + 8001dfe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001e02: 6253 str r3, [r2, #36] @ 0x24 + 8001e04: 4b1d ldr r3, [pc, #116] @ (8001e7c ) + 8001e06: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e08: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001e0c: 60fb str r3, [r7, #12] + 8001e0e: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001e10: 4b1b ldr r3, [pc, #108] @ (8001e80 ) + 8001e12: 681b ldr r3, [r3, #0] + 8001e14: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001e18: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001e1a: 4b18 ldr r3, [pc, #96] @ (8001e7c ) + 8001e1c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e1e: 4a17 ldr r2, [pc, #92] @ (8001e7c ) + 8001e20: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001e24: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001e26: 697b ldr r3, [r7, #20] + 8001e28: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001e2c: d105 bne.n 8001e3a + 8001e2e: 687b ldr r3, [r7, #4] + 8001e30: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001e34: d101 bne.n 8001e3a + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001e36: 2301 movs r3, #1 + 8001e38: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001e3a: 693b ldr r3, [r7, #16] + 8001e3c: 2b01 cmp r3, #1 + 8001e3e: d105 bne.n 8001e4c + 8001e40: 4b10 ldr r3, [pc, #64] @ (8001e84 ) + 8001e42: 681b ldr r3, [r3, #0] + 8001e44: 4a0f ldr r2, [pc, #60] @ (8001e84 ) + 8001e46: f043 0304 orr.w r3, r3, #4 + 8001e4a: 6013 str r3, [r2, #0] + 8001e4c: 4b0d ldr r3, [pc, #52] @ (8001e84 ) + 8001e4e: 681b ldr r3, [r3, #0] + 8001e50: f023 0201 bic.w r2, r3, #1 + 8001e54: 490b ldr r1, [pc, #44] @ (8001e84 ) + 8001e56: 693b ldr r3, [r7, #16] + 8001e58: 4313 orrs r3, r2 + 8001e5a: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001e5c: 4b09 ldr r3, [pc, #36] @ (8001e84 ) + 8001e5e: 681b ldr r3, [r3, #0] + 8001e60: f003 0301 and.w r3, r3, #1 + 8001e64: 693a ldr r2, [r7, #16] + 8001e66: 429a cmp r2, r3 + 8001e68: d001 beq.n 8001e6e + { + return HAL_ERROR; + 8001e6a: 2301 movs r3, #1 + 8001e6c: e000 b.n 8001e70 + } + + return HAL_OK; + 8001e6e: 2300 movs r3, #0 +} + 8001e70: 4618 mov r0, r3 + 8001e72: 371c adds r7, #28 + 8001e74: 46bd mov sp, r7 + 8001e76: bc80 pop {r7} + 8001e78: 4770 bx lr + 8001e7a: bf00 nop + 8001e7c: 40023800 .word 0x40023800 + 8001e80: 40007000 .word 0x40007000 + 8001e84: 40023c00 .word 0x40023c00 + +08001e88 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001e88: b580 push {r7, lr} + 8001e8a: b082 sub sp, #8 + 8001e8c: af00 add r7, sp, #0 + 8001e8e: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001e90: 687b ldr r3, [r7, #4] + 8001e92: 2b00 cmp r3, #0 + 8001e94: d101 bne.n 8001e9a + { + return HAL_ERROR; + 8001e96: 2301 movs r3, #1 + 8001e98: e07b b.n 8001f92 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001e9a: 687b ldr r3, [r7, #4] + 8001e9c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e9e: 2b00 cmp r3, #0 + 8001ea0: d108 bne.n 8001eb4 + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001ea2: 687b ldr r3, [r7, #4] + 8001ea4: 685b ldr r3, [r3, #4] + 8001ea6: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001eaa: d009 beq.n 8001ec0 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001eac: 687b ldr r3, [r7, #4] + 8001eae: 2200 movs r2, #0 + 8001eb0: 61da str r2, [r3, #28] + 8001eb2: e005 b.n 8001ec0 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001eb4: 687b ldr r3, [r7, #4] + 8001eb6: 2200 movs r2, #0 + 8001eb8: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001eba: 687b ldr r3, [r7, #4] + 8001ebc: 2200 movs r2, #0 + 8001ebe: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001ec0: 687b ldr r3, [r7, #4] + 8001ec2: 2200 movs r2, #0 + 8001ec4: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001ec6: 687b ldr r3, [r7, #4] + 8001ec8: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001ecc: b2db uxtb r3, r3 + 8001ece: 2b00 cmp r3, #0 + 8001ed0: d106 bne.n 8001ee0 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001ed2: 687b ldr r3, [r7, #4] + 8001ed4: 2200 movs r2, #0 + 8001ed6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001eda: 6878 ldr r0, [r7, #4] + 8001edc: f7fe fd5a bl 8000994 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001ee0: 687b ldr r3, [r7, #4] + 8001ee2: 2202 movs r2, #2 + 8001ee4: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001ee8: 687b ldr r3, [r7, #4] + 8001eea: 681b ldr r3, [r3, #0] + 8001eec: 681a ldr r2, [r3, #0] + 8001eee: 687b ldr r3, [r7, #4] + 8001ef0: 681b ldr r3, [r3, #0] + 8001ef2: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001ef6: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001ef8: 687b ldr r3, [r7, #4] + 8001efa: 685b ldr r3, [r3, #4] + 8001efc: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001f00: 687b ldr r3, [r7, #4] + 8001f02: 689b ldr r3, [r3, #8] + 8001f04: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001f08: 431a orrs r2, r3 + 8001f0a: 687b ldr r3, [r7, #4] + 8001f0c: 68db ldr r3, [r3, #12] + 8001f0e: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001f12: 431a orrs r2, r3 + 8001f14: 687b ldr r3, [r7, #4] + 8001f16: 691b ldr r3, [r3, #16] + 8001f18: f003 0302 and.w r3, r3, #2 + 8001f1c: 431a orrs r2, r3 + 8001f1e: 687b ldr r3, [r7, #4] + 8001f20: 695b ldr r3, [r3, #20] + 8001f22: f003 0301 and.w r3, r3, #1 + 8001f26: 431a orrs r2, r3 + 8001f28: 687b ldr r3, [r7, #4] + 8001f2a: 699b ldr r3, [r3, #24] + 8001f2c: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001f30: 431a orrs r2, r3 + 8001f32: 687b ldr r3, [r7, #4] + 8001f34: 69db ldr r3, [r3, #28] + 8001f36: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001f3a: 431a orrs r2, r3 + 8001f3c: 687b ldr r3, [r7, #4] + 8001f3e: 6a1b ldr r3, [r3, #32] + 8001f40: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001f44: ea42 0103 orr.w r1, r2, r3 + 8001f48: 687b ldr r3, [r7, #4] + 8001f4a: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001f4c: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001f50: 687b ldr r3, [r7, #4] + 8001f52: 681b ldr r3, [r3, #0] + 8001f54: 430a orrs r2, r1 + 8001f56: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8001f58: 687b ldr r3, [r7, #4] + 8001f5a: 699b ldr r3, [r3, #24] + 8001f5c: 0c1b lsrs r3, r3, #16 + 8001f5e: f003 0104 and.w r1, r3, #4 + 8001f62: 687b ldr r3, [r7, #4] + 8001f64: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001f66: f003 0210 and.w r2, r3, #16 + 8001f6a: 687b ldr r3, [r7, #4] + 8001f6c: 681b ldr r3, [r3, #0] + 8001f6e: 430a orrs r2, r1 + 8001f70: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8001f72: 687b ldr r3, [r7, #4] + 8001f74: 681b ldr r3, [r3, #0] + 8001f76: 69da ldr r2, [r3, #28] + 8001f78: 687b ldr r3, [r7, #4] + 8001f7a: 681b ldr r3, [r3, #0] + 8001f7c: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001f80: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001f82: 687b ldr r3, [r7, #4] + 8001f84: 2200 movs r2, #0 + 8001f86: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8001f88: 687b ldr r3, [r7, #4] + 8001f8a: 2201 movs r2, #1 + 8001f8c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8001f90: 2300 movs r3, #0 +} + 8001f92: 4618 mov r0, r3 + 8001f94: 3708 adds r7, #8 + 8001f96: 46bd mov sp, r7 + 8001f98: bd80 pop {r7, pc} + +08001f9a : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8001f9a: b580 push {r7, lr} + 8001f9c: b088 sub sp, #32 + 8001f9e: af00 add r7, sp, #0 + 8001fa0: 60f8 str r0, [r7, #12] + 8001fa2: 60b9 str r1, [r7, #8] + 8001fa4: 603b str r3, [r7, #0] + 8001fa6: 4613 mov r3, r2 + 8001fa8: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001faa: f7fe fee7 bl 8000d7c + 8001fae: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8001fb0: 88fb ldrh r3, [r7, #6] + 8001fb2: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8001fb4: 68fb ldr r3, [r7, #12] + 8001fb6: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001fba: b2db uxtb r3, r3 + 8001fbc: 2b01 cmp r3, #1 + 8001fbe: d001 beq.n 8001fc4 + { + return HAL_BUSY; + 8001fc0: 2302 movs r3, #2 + 8001fc2: e12a b.n 800221a + } + + if ((pData == NULL) || (Size == 0U)) + 8001fc4: 68bb ldr r3, [r7, #8] + 8001fc6: 2b00 cmp r3, #0 + 8001fc8: d002 beq.n 8001fd0 + 8001fca: 88fb ldrh r3, [r7, #6] + 8001fcc: 2b00 cmp r3, #0 + 8001fce: d101 bne.n 8001fd4 + { + return HAL_ERROR; + 8001fd0: 2301 movs r3, #1 + 8001fd2: e122 b.n 800221a + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 8001fd4: 68fb ldr r3, [r7, #12] + 8001fd6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001fda: 2b01 cmp r3, #1 + 8001fdc: d101 bne.n 8001fe2 + 8001fde: 2302 movs r3, #2 + 8001fe0: e11b b.n 800221a + 8001fe2: 68fb ldr r3, [r7, #12] + 8001fe4: 2201 movs r2, #1 + 8001fe6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8001fea: 68fb ldr r3, [r7, #12] + 8001fec: 2203 movs r2, #3 + 8001fee: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001ff2: 68fb ldr r3, [r7, #12] + 8001ff4: 2200 movs r2, #0 + 8001ff6: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8001ff8: 68fb ldr r3, [r7, #12] + 8001ffa: 68ba ldr r2, [r7, #8] + 8001ffc: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 8001ffe: 68fb ldr r3, [r7, #12] + 8002000: 88fa ldrh r2, [r7, #6] + 8002002: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8002004: 68fb ldr r3, [r7, #12] + 8002006: 88fa ldrh r2, [r7, #6] + 8002008: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 800200a: 68fb ldr r3, [r7, #12] + 800200c: 2200 movs r2, #0 + 800200e: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 8002010: 68fb ldr r3, [r7, #12] + 8002012: 2200 movs r2, #0 + 8002014: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8002016: 68fb ldr r3, [r7, #12] + 8002018: 2200 movs r2, #0 + 800201a: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 800201c: 68fb ldr r3, [r7, #12] + 800201e: 2200 movs r2, #0 + 8002020: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8002022: 68fb ldr r3, [r7, #12] + 8002024: 2200 movs r2, #0 + 8002026: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8002028: 68fb ldr r3, [r7, #12] + 800202a: 689b ldr r3, [r3, #8] + 800202c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8002030: d10f bne.n 8002052 + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8002032: 68fb ldr r3, [r7, #12] + 8002034: 681b ldr r3, [r3, #0] + 8002036: 681a ldr r2, [r3, #0] + 8002038: 68fb ldr r3, [r7, #12] + 800203a: 681b ldr r3, [r3, #0] + 800203c: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8002040: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8002042: 68fb ldr r3, [r7, #12] + 8002044: 681b ldr r3, [r3, #0] + 8002046: 681a ldr r2, [r3, #0] + 8002048: 68fb ldr r3, [r7, #12] + 800204a: 681b ldr r3, [r3, #0] + 800204c: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8002050: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8002052: 68fb ldr r3, [r7, #12] + 8002054: 681b ldr r3, [r3, #0] + 8002056: 681b ldr r3, [r3, #0] + 8002058: f003 0340 and.w r3, r3, #64 @ 0x40 + 800205c: 2b40 cmp r3, #64 @ 0x40 + 800205e: d007 beq.n 8002070 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8002060: 68fb ldr r3, [r7, #12] + 8002062: 681b ldr r3, [r3, #0] + 8002064: 681a ldr r2, [r3, #0] + 8002066: 68fb ldr r3, [r7, #12] + 8002068: 681b ldr r3, [r3, #0] + 800206a: f042 0240 orr.w r2, r2, #64 @ 0x40 + 800206e: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8002070: 68fb ldr r3, [r7, #12] + 8002072: 68db ldr r3, [r3, #12] + 8002074: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8002078: d152 bne.n 8002120 + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800207a: 68fb ldr r3, [r7, #12] + 800207c: 685b ldr r3, [r3, #4] + 800207e: 2b00 cmp r3, #0 + 8002080: d002 beq.n 8002088 + 8002082: 8b7b ldrh r3, [r7, #26] + 8002084: 2b01 cmp r3, #1 + 8002086: d145 bne.n 8002114 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8002088: 68fb ldr r3, [r7, #12] + 800208a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800208c: 881a ldrh r2, [r3, #0] + 800208e: 68fb ldr r3, [r7, #12] + 8002090: 681b ldr r3, [r3, #0] + 8002092: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8002094: 68fb ldr r3, [r7, #12] + 8002096: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002098: 1c9a adds r2, r3, #2 + 800209a: 68fb ldr r3, [r7, #12] + 800209c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 800209e: 68fb ldr r3, [r7, #12] + 80020a0: 8edb ldrh r3, [r3, #54] @ 0x36 + 80020a2: b29b uxth r3, r3 + 80020a4: 3b01 subs r3, #1 + 80020a6: b29a uxth r2, r3 + 80020a8: 68fb ldr r3, [r7, #12] + 80020aa: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 80020ac: e032 b.n 8002114 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 80020ae: 68fb ldr r3, [r7, #12] + 80020b0: 681b ldr r3, [r3, #0] + 80020b2: 689b ldr r3, [r3, #8] + 80020b4: f003 0302 and.w r3, r3, #2 + 80020b8: 2b02 cmp r3, #2 + 80020ba: d112 bne.n 80020e2 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 80020bc: 68fb ldr r3, [r7, #12] + 80020be: 6b1b ldr r3, [r3, #48] @ 0x30 + 80020c0: 881a ldrh r2, [r3, #0] + 80020c2: 68fb ldr r3, [r7, #12] + 80020c4: 681b ldr r3, [r3, #0] + 80020c6: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 80020c8: 68fb ldr r3, [r7, #12] + 80020ca: 6b1b ldr r3, [r3, #48] @ 0x30 + 80020cc: 1c9a adds r2, r3, #2 + 80020ce: 68fb ldr r3, [r7, #12] + 80020d0: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 80020d2: 68fb ldr r3, [r7, #12] + 80020d4: 8edb ldrh r3, [r3, #54] @ 0x36 + 80020d6: b29b uxth r3, r3 + 80020d8: 3b01 subs r3, #1 + 80020da: b29a uxth r2, r3 + 80020dc: 68fb ldr r3, [r7, #12] + 80020de: 86da strh r2, [r3, #54] @ 0x36 + 80020e0: e018 b.n 8002114 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 80020e2: f7fe fe4b bl 8000d7c + 80020e6: 4602 mov r2, r0 + 80020e8: 69fb ldr r3, [r7, #28] + 80020ea: 1ad3 subs r3, r2, r3 + 80020ec: 683a ldr r2, [r7, #0] + 80020ee: 429a cmp r2, r3 + 80020f0: d803 bhi.n 80020fa + 80020f2: 683b ldr r3, [r7, #0] + 80020f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80020f8: d102 bne.n 8002100 + 80020fa: 683b ldr r3, [r7, #0] + 80020fc: 2b00 cmp r3, #0 + 80020fe: d109 bne.n 8002114 + { + hspi->State = HAL_SPI_STATE_READY; + 8002100: 68fb ldr r3, [r7, #12] + 8002102: 2201 movs r2, #1 + 8002104: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8002108: 68fb ldr r3, [r7, #12] + 800210a: 2200 movs r2, #0 + 800210c: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8002110: 2303 movs r3, #3 + 8002112: e082 b.n 800221a + while (hspi->TxXferCount > 0U) + 8002114: 68fb ldr r3, [r7, #12] + 8002116: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002118: b29b uxth r3, r3 + 800211a: 2b00 cmp r3, #0 + 800211c: d1c7 bne.n 80020ae + 800211e: e053 b.n 80021c8 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8002120: 68fb ldr r3, [r7, #12] + 8002122: 685b ldr r3, [r3, #4] + 8002124: 2b00 cmp r3, #0 + 8002126: d002 beq.n 800212e + 8002128: 8b7b ldrh r3, [r7, #26] + 800212a: 2b01 cmp r3, #1 + 800212c: d147 bne.n 80021be + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 800212e: 68fb ldr r3, [r7, #12] + 8002130: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002132: 68fb ldr r3, [r7, #12] + 8002134: 681b ldr r3, [r3, #0] + 8002136: 330c adds r3, #12 + 8002138: 7812 ldrb r2, [r2, #0] + 800213a: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 800213c: 68fb ldr r3, [r7, #12] + 800213e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002140: 1c5a adds r2, r3, #1 + 8002142: 68fb ldr r3, [r7, #12] + 8002144: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8002146: 68fb ldr r3, [r7, #12] + 8002148: 8edb ldrh r3, [r3, #54] @ 0x36 + 800214a: b29b uxth r3, r3 + 800214c: 3b01 subs r3, #1 + 800214e: b29a uxth r2, r3 + 8002150: 68fb ldr r3, [r7, #12] + 8002152: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8002154: e033 b.n 80021be + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8002156: 68fb ldr r3, [r7, #12] + 8002158: 681b ldr r3, [r3, #0] + 800215a: 689b ldr r3, [r3, #8] + 800215c: f003 0302 and.w r3, r3, #2 + 8002160: 2b02 cmp r3, #2 + 8002162: d113 bne.n 800218c + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8002164: 68fb ldr r3, [r7, #12] + 8002166: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002168: 68fb ldr r3, [r7, #12] + 800216a: 681b ldr r3, [r3, #0] + 800216c: 330c adds r3, #12 + 800216e: 7812 ldrb r2, [r2, #0] + 8002170: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8002172: 68fb ldr r3, [r7, #12] + 8002174: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002176: 1c5a adds r2, r3, #1 + 8002178: 68fb ldr r3, [r7, #12] + 800217a: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 800217c: 68fb ldr r3, [r7, #12] + 800217e: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002180: b29b uxth r3, r3 + 8002182: 3b01 subs r3, #1 + 8002184: b29a uxth r2, r3 + 8002186: 68fb ldr r3, [r7, #12] + 8002188: 86da strh r2, [r3, #54] @ 0x36 + 800218a: e018 b.n 80021be + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 800218c: f7fe fdf6 bl 8000d7c + 8002190: 4602 mov r2, r0 + 8002192: 69fb ldr r3, [r7, #28] + 8002194: 1ad3 subs r3, r2, r3 + 8002196: 683a ldr r2, [r7, #0] + 8002198: 429a cmp r2, r3 + 800219a: d803 bhi.n 80021a4 + 800219c: 683b ldr r3, [r7, #0] + 800219e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80021a2: d102 bne.n 80021aa + 80021a4: 683b ldr r3, [r7, #0] + 80021a6: 2b00 cmp r3, #0 + 80021a8: d109 bne.n 80021be + { + hspi->State = HAL_SPI_STATE_READY; + 80021aa: 68fb ldr r3, [r7, #12] + 80021ac: 2201 movs r2, #1 + 80021ae: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 80021b2: 68fb ldr r3, [r7, #12] + 80021b4: 2200 movs r2, #0 + 80021b6: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 80021ba: 2303 movs r3, #3 + 80021bc: e02d b.n 800221a + while (hspi->TxXferCount > 0U) + 80021be: 68fb ldr r3, [r7, #12] + 80021c0: 8edb ldrh r3, [r3, #54] @ 0x36 + 80021c2: b29b uxth r3, r3 + 80021c4: 2b00 cmp r3, #0 + 80021c6: d1c6 bne.n 8002156 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 80021c8: 69fa ldr r2, [r7, #28] + 80021ca: 6839 ldr r1, [r7, #0] + 80021cc: 68f8 ldr r0, [r7, #12] + 80021ce: f000 f8b1 bl 8002334 + 80021d2: 4603 mov r3, r0 + 80021d4: 2b00 cmp r3, #0 + 80021d6: d002 beq.n 80021de + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 80021d8: 68fb ldr r3, [r7, #12] + 80021da: 2220 movs r2, #32 + 80021dc: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 80021de: 68fb ldr r3, [r7, #12] + 80021e0: 689b ldr r3, [r3, #8] + 80021e2: 2b00 cmp r3, #0 + 80021e4: d10a bne.n 80021fc + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 80021e6: 2300 movs r3, #0 + 80021e8: 617b str r3, [r7, #20] + 80021ea: 68fb ldr r3, [r7, #12] + 80021ec: 681b ldr r3, [r3, #0] + 80021ee: 68db ldr r3, [r3, #12] + 80021f0: 617b str r3, [r7, #20] + 80021f2: 68fb ldr r3, [r7, #12] + 80021f4: 681b ldr r3, [r3, #0] + 80021f6: 689b ldr r3, [r3, #8] + 80021f8: 617b str r3, [r7, #20] + 80021fa: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 80021fc: 68fb ldr r3, [r7, #12] + 80021fe: 2201 movs r2, #1 + 8002200: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8002204: 68fb ldr r3, [r7, #12] + 8002206: 2200 movs r2, #0 + 8002208: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 800220c: 68fb ldr r3, [r7, #12] + 800220e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002210: 2b00 cmp r3, #0 + 8002212: d001 beq.n 8002218 + { + return HAL_ERROR; + 8002214: 2301 movs r3, #1 + 8002216: e000 b.n 800221a + } + else + { + return HAL_OK; + 8002218: 2300 movs r3, #0 + } +} + 800221a: 4618 mov r0, r3 + 800221c: 3720 adds r7, #32 + 800221e: 46bd mov sp, r7 + 8002220: bd80 pop {r7, pc} + ... + +08002224 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8002224: b580 push {r7, lr} + 8002226: b088 sub sp, #32 + 8002228: af00 add r7, sp, #0 + 800222a: 60f8 str r0, [r7, #12] + 800222c: 60b9 str r1, [r7, #8] + 800222e: 603b str r3, [r7, #0] + 8002230: 4613 mov r3, r2 + 8002232: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 8002234: f7fe fda2 bl 8000d7c + 8002238: 4602 mov r2, r0 + 800223a: 6abb ldr r3, [r7, #40] @ 0x28 + 800223c: 1a9b subs r3, r3, r2 + 800223e: 683a ldr r2, [r7, #0] + 8002240: 4413 add r3, r2 + 8002242: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 8002244: f7fe fd9a bl 8000d7c + 8002248: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 800224a: 4b39 ldr r3, [pc, #228] @ (8002330 ) + 800224c: 681b ldr r3, [r3, #0] + 800224e: 015b lsls r3, r3, #5 + 8002250: 0d1b lsrs r3, r3, #20 + 8002252: 69fa ldr r2, [r7, #28] + 8002254: fb02 f303 mul.w r3, r2, r3 + 8002258: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 800225a: e054 b.n 8002306 + { + if (Timeout != HAL_MAX_DELAY) + 800225c: 683b ldr r3, [r7, #0] + 800225e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8002262: d050 beq.n 8002306 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8002264: f7fe fd8a bl 8000d7c + 8002268: 4602 mov r2, r0 + 800226a: 69bb ldr r3, [r7, #24] + 800226c: 1ad3 subs r3, r2, r3 + 800226e: 69fa ldr r2, [r7, #28] + 8002270: 429a cmp r2, r3 + 8002272: d902 bls.n 800227a + 8002274: 69fb ldr r3, [r7, #28] + 8002276: 2b00 cmp r3, #0 + 8002278: d13d bne.n 80022f6 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 800227a: 68fb ldr r3, [r7, #12] + 800227c: 681b ldr r3, [r3, #0] + 800227e: 685a ldr r2, [r3, #4] + 8002280: 68fb ldr r3, [r7, #12] + 8002282: 681b ldr r3, [r3, #0] + 8002284: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8002288: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800228a: 68fb ldr r3, [r7, #12] + 800228c: 685b ldr r3, [r3, #4] + 800228e: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002292: d111 bne.n 80022b8 + 8002294: 68fb ldr r3, [r7, #12] + 8002296: 689b ldr r3, [r3, #8] + 8002298: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 800229c: d004 beq.n 80022a8 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800229e: 68fb ldr r3, [r7, #12] + 80022a0: 689b ldr r3, [r3, #8] + 80022a2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 80022a6: d107 bne.n 80022b8 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 80022a8: 68fb ldr r3, [r7, #12] + 80022aa: 681b ldr r3, [r3, #0] + 80022ac: 681a ldr r2, [r3, #0] + 80022ae: 68fb ldr r3, [r7, #12] + 80022b0: 681b ldr r3, [r3, #0] + 80022b2: f022 0240 bic.w r2, r2, #64 @ 0x40 + 80022b6: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 80022b8: 68fb ldr r3, [r7, #12] + 80022ba: 6a9b ldr r3, [r3, #40] @ 0x28 + 80022bc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80022c0: d10f bne.n 80022e2 + { + SPI_RESET_CRC(hspi); + 80022c2: 68fb ldr r3, [r7, #12] + 80022c4: 681b ldr r3, [r3, #0] + 80022c6: 681a ldr r2, [r3, #0] + 80022c8: 68fb ldr r3, [r7, #12] + 80022ca: 681b ldr r3, [r3, #0] + 80022cc: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 80022d0: 601a str r2, [r3, #0] + 80022d2: 68fb ldr r3, [r7, #12] + 80022d4: 681b ldr r3, [r3, #0] + 80022d6: 681a ldr r2, [r3, #0] + 80022d8: 68fb ldr r3, [r7, #12] + 80022da: 681b ldr r3, [r3, #0] + 80022dc: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 80022e0: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 80022e2: 68fb ldr r3, [r7, #12] + 80022e4: 2201 movs r2, #1 + 80022e6: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80022ea: 68fb ldr r3, [r7, #12] + 80022ec: 2200 movs r2, #0 + 80022ee: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 80022f2: 2303 movs r3, #3 + 80022f4: e017 b.n 8002326 + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 80022f6: 697b ldr r3, [r7, #20] + 80022f8: 2b00 cmp r3, #0 + 80022fa: d101 bne.n 8002300 + { + tmp_timeout = 0U; + 80022fc: 2300 movs r3, #0 + 80022fe: 61fb str r3, [r7, #28] + } + count--; + 8002300: 697b ldr r3, [r7, #20] + 8002302: 3b01 subs r3, #1 + 8002304: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8002306: 68fb ldr r3, [r7, #12] + 8002308: 681b ldr r3, [r3, #0] + 800230a: 689a ldr r2, [r3, #8] + 800230c: 68bb ldr r3, [r7, #8] + 800230e: 4013 ands r3, r2 + 8002310: 68ba ldr r2, [r7, #8] + 8002312: 429a cmp r2, r3 + 8002314: bf0c ite eq + 8002316: 2301 moveq r3, #1 + 8002318: 2300 movne r3, #0 + 800231a: b2db uxtb r3, r3 + 800231c: 461a mov r2, r3 + 800231e: 79fb ldrb r3, [r7, #7] + 8002320: 429a cmp r2, r3 + 8002322: d19b bne.n 800225c + } + } + + return HAL_OK; + 8002324: 2300 movs r3, #0 +} + 8002326: 4618 mov r0, r3 + 8002328: 3720 adds r7, #32 + 800232a: 46bd mov sp, r7 + 800232c: bd80 pop {r7, pc} + 800232e: bf00 nop + 8002330: 20000000 .word 0x20000000 + +08002334 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 8002334: b580 push {r7, lr} + 8002336: b088 sub sp, #32 + 8002338: af02 add r7, sp, #8 + 800233a: 60f8 str r0, [r7, #12] + 800233c: 60b9 str r1, [r7, #8] + 800233e: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 8002340: 687b ldr r3, [r7, #4] + 8002342: 9300 str r3, [sp, #0] + 8002344: 68bb ldr r3, [r7, #8] + 8002346: 2201 movs r2, #1 + 8002348: 2102 movs r1, #2 + 800234a: 68f8 ldr r0, [r7, #12] + 800234c: f7ff ff6a bl 8002224 + 8002350: 4603 mov r3, r0 + 8002352: 2b00 cmp r3, #0 + 8002354: d007 beq.n 8002366 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002356: 68fb ldr r3, [r7, #12] + 8002358: 6d5b ldr r3, [r3, #84] @ 0x54 + 800235a: f043 0220 orr.w r2, r3, #32 + 800235e: 68fb ldr r3, [r7, #12] + 8002360: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8002362: 2303 movs r3, #3 + 8002364: e032 b.n 80023cc + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 8002366: 4b1b ldr r3, [pc, #108] @ (80023d4 ) + 8002368: 681b ldr r3, [r3, #0] + 800236a: 4a1b ldr r2, [pc, #108] @ (80023d8 ) + 800236c: fba2 2303 umull r2, r3, r2, r3 + 8002370: 0d5b lsrs r3, r3, #21 + 8002372: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8002376: fb02 f303 mul.w r3, r2, r3 + 800237a: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 800237c: 68fb ldr r3, [r7, #12] + 800237e: 685b ldr r3, [r3, #4] + 8002380: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002384: d112 bne.n 80023ac + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8002386: 687b ldr r3, [r7, #4] + 8002388: 9300 str r3, [sp, #0] + 800238a: 68bb ldr r3, [r7, #8] + 800238c: 2200 movs r2, #0 + 800238e: 2180 movs r1, #128 @ 0x80 + 8002390: 68f8 ldr r0, [r7, #12] + 8002392: f7ff ff47 bl 8002224 + 8002396: 4603 mov r3, r0 + 8002398: 2b00 cmp r3, #0 + 800239a: d016 beq.n 80023ca + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800239c: 68fb ldr r3, [r7, #12] + 800239e: 6d5b ldr r3, [r3, #84] @ 0x54 + 80023a0: f043 0220 orr.w r2, r3, #32 + 80023a4: 68fb ldr r3, [r7, #12] + 80023a6: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 80023a8: 2303 movs r3, #3 + 80023aa: e00f b.n 80023cc + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 80023ac: 697b ldr r3, [r7, #20] + 80023ae: 2b00 cmp r3, #0 + 80023b0: d00a beq.n 80023c8 + { + break; + } + count--; + 80023b2: 697b ldr r3, [r7, #20] + 80023b4: 3b01 subs r3, #1 + 80023b6: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 80023b8: 68fb ldr r3, [r7, #12] + 80023ba: 681b ldr r3, [r3, #0] + 80023bc: 689b ldr r3, [r3, #8] + 80023be: f003 0380 and.w r3, r3, #128 @ 0x80 + 80023c2: 2b80 cmp r3, #128 @ 0x80 + 80023c4: d0f2 beq.n 80023ac + 80023c6: e000 b.n 80023ca + break; + 80023c8: bf00 nop + } + + return HAL_OK; + 80023ca: 2300 movs r3, #0 +} + 80023cc: 4618 mov r0, r3 + 80023ce: 3718 adds r7, #24 + 80023d0: 46bd mov sp, r7 + 80023d2: bd80 pop {r7, pc} + 80023d4: 20000000 .word 0x20000000 + 80023d8: 165e9f81 .word 0x165e9f81 + +080023dc : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 80023dc: b580 push {r7, lr} + 80023de: b082 sub sp, #8 + 80023e0: af00 add r7, sp, #0 + 80023e2: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80023e4: 687b ldr r3, [r7, #4] + 80023e6: 2b00 cmp r3, #0 + 80023e8: d101 bne.n 80023ee + { + return HAL_ERROR; + 80023ea: 2301 movs r3, #1 + 80023ec: e031 b.n 8002452 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80023ee: 687b ldr r3, [r7, #4] + 80023f0: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 80023f4: b2db uxtb r3, r3 + 80023f6: 2b00 cmp r3, #0 + 80023f8: d106 bne.n 8002408 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 80023fa: 687b ldr r3, [r7, #4] + 80023fc: 2200 movs r2, #0 + 80023fe: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8002402: 6878 ldr r0, [r7, #4] + 8002404: f7fe fb0a bl 8000a1c +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002408: 687b ldr r3, [r7, #4] + 800240a: 2202 movs r2, #2 + 800240c: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8002410: 687b ldr r3, [r7, #4] + 8002412: 681a ldr r2, [r3, #0] + 8002414: 687b ldr r3, [r7, #4] + 8002416: 3304 adds r3, #4 + 8002418: 4619 mov r1, r3 + 800241a: 4610 mov r0, r2 + 800241c: f000 fa86 bl 800292c + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8002420: 687b ldr r3, [r7, #4] + 8002422: 2201 movs r2, #1 + 8002424: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8002428: 687b ldr r3, [r7, #4] + 800242a: 2201 movs r2, #1 + 800242c: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002430: 687b ldr r3, [r7, #4] + 8002432: 2201 movs r2, #1 + 8002434: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002438: 687b ldr r3, [r7, #4] + 800243a: 2201 movs r2, #1 + 800243c: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002440: 687b ldr r3, [r7, #4] + 8002442: 2201 movs r2, #1 + 8002444: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8002448: 687b ldr r3, [r7, #4] + 800244a: 2201 movs r2, #1 + 800244c: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 8002450: 2300 movs r3, #0 +} + 8002452: 4618 mov r0, r3 + 8002454: 3708 adds r7, #8 + 8002456: 46bd mov sp, r7 + 8002458: bd80 pop {r7, pc} + +0800245a : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 800245a: b580 push {r7, lr} + 800245c: b082 sub sp, #8 + 800245e: af00 add r7, sp, #0 + 8002460: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8002462: 687b ldr r3, [r7, #4] + 8002464: 2b00 cmp r3, #0 + 8002466: d101 bne.n 800246c + { + return HAL_ERROR; + 8002468: 2301 movs r3, #1 + 800246a: e031 b.n 80024d0 + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 800246c: 687b ldr r3, [r7, #4] + 800246e: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 8002472: b2db uxtb r3, r3 + 8002474: 2b00 cmp r3, #0 + 8002476: d106 bne.n 8002486 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8002478: 687b ldr r3, [r7, #4] + 800247a: 2200 movs r2, #0 + 800247c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 8002480: 6878 ldr r0, [r7, #4] + 8002482: f000 f829 bl 80024d8 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002486: 687b ldr r3, [r7, #4] + 8002488: 2202 movs r2, #2 + 800248a: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 800248e: 687b ldr r3, [r7, #4] + 8002490: 681a ldr r2, [r3, #0] + 8002492: 687b ldr r3, [r7, #4] + 8002494: 3304 adds r3, #4 + 8002496: 4619 mov r1, r3 + 8002498: 4610 mov r0, r2 + 800249a: f000 fa47 bl 800292c + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 800249e: 687b ldr r3, [r7, #4] + 80024a0: 2201 movs r2, #1 + 80024a2: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 80024a6: 687b ldr r3, [r7, #4] + 80024a8: 2201 movs r2, #1 + 80024aa: f883 203a strb.w r2, [r3, #58] @ 0x3a + 80024ae: 687b ldr r3, [r7, #4] + 80024b0: 2201 movs r2, #1 + 80024b2: f883 203b strb.w r2, [r3, #59] @ 0x3b + 80024b6: 687b ldr r3, [r7, #4] + 80024b8: 2201 movs r2, #1 + 80024ba: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80024be: 687b ldr r3, [r7, #4] + 80024c0: 2201 movs r2, #1 + 80024c2: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 80024c6: 687b ldr r3, [r7, #4] + 80024c8: 2201 movs r2, #1 + 80024ca: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 80024ce: 2300 movs r3, #0 +} + 80024d0: 4618 mov r0, r3 + 80024d2: 3708 adds r7, #8 + 80024d4: 46bd mov sp, r7 + 80024d6: bd80 pop {r7, pc} + +080024d8 : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 80024d8: b480 push {r7} + 80024da: b083 sub sp, #12 + 80024dc: af00 add r7, sp, #0 + 80024de: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 80024e0: bf00 nop + 80024e2: 370c adds r7, #12 + 80024e4: 46bd mov sp, r7 + 80024e6: bc80 pop {r7} + 80024e8: 4770 bx lr + ... + +080024ec : + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 80024ec: b580 push {r7, lr} + 80024ee: b084 sub sp, #16 + 80024f0: af00 add r7, sp, #0 + 80024f2: 6078 str r0, [r7, #4] + 80024f4: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 80024f6: 683b ldr r3, [r7, #0] + 80024f8: 2b00 cmp r3, #0 + 80024fa: d109 bne.n 8002510 + 80024fc: 687b ldr r3, [r7, #4] + 80024fe: f893 303a ldrb.w r3, [r3, #58] @ 0x3a + 8002502: b2db uxtb r3, r3 + 8002504: 2b01 cmp r3, #1 + 8002506: bf14 ite ne + 8002508: 2301 movne r3, #1 + 800250a: 2300 moveq r3, #0 + 800250c: b2db uxtb r3, r3 + 800250e: e022 b.n 8002556 + 8002510: 683b ldr r3, [r7, #0] + 8002512: 2b04 cmp r3, #4 + 8002514: d109 bne.n 800252a + 8002516: 687b ldr r3, [r7, #4] + 8002518: f893 303b ldrb.w r3, [r3, #59] @ 0x3b + 800251c: b2db uxtb r3, r3 + 800251e: 2b01 cmp r3, #1 + 8002520: bf14 ite ne + 8002522: 2301 movne r3, #1 + 8002524: 2300 moveq r3, #0 + 8002526: b2db uxtb r3, r3 + 8002528: e015 b.n 8002556 + 800252a: 683b ldr r3, [r7, #0] + 800252c: 2b08 cmp r3, #8 + 800252e: d109 bne.n 8002544 + 8002530: 687b ldr r3, [r7, #4] + 8002532: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8002536: b2db uxtb r3, r3 + 8002538: 2b01 cmp r3, #1 + 800253a: bf14 ite ne + 800253c: 2301 movne r3, #1 + 800253e: 2300 moveq r3, #0 + 8002540: b2db uxtb r3, r3 + 8002542: e008 b.n 8002556 + 8002544: 687b ldr r3, [r7, #4] + 8002546: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 800254a: b2db uxtb r3, r3 + 800254c: 2b01 cmp r3, #1 + 800254e: bf14 ite ne + 8002550: 2301 movne r3, #1 + 8002552: 2300 moveq r3, #0 + 8002554: b2db uxtb r3, r3 + 8002556: 2b00 cmp r3, #0 + 8002558: d001 beq.n 800255e + { + return HAL_ERROR; + 800255a: 2301 movs r3, #1 + 800255c: e051 b.n 8002602 + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 800255e: 683b ldr r3, [r7, #0] + 8002560: 2b00 cmp r3, #0 + 8002562: d104 bne.n 800256e + 8002564: 687b ldr r3, [r7, #4] + 8002566: 2202 movs r2, #2 + 8002568: f883 203a strb.w r2, [r3, #58] @ 0x3a + 800256c: e013 b.n 8002596 + 800256e: 683b ldr r3, [r7, #0] + 8002570: 2b04 cmp r3, #4 + 8002572: d104 bne.n 800257e + 8002574: 687b ldr r3, [r7, #4] + 8002576: 2202 movs r2, #2 + 8002578: f883 203b strb.w r2, [r3, #59] @ 0x3b + 800257c: e00b b.n 8002596 + 800257e: 683b ldr r3, [r7, #0] + 8002580: 2b08 cmp r3, #8 + 8002582: d104 bne.n 800258e + 8002584: 687b ldr r3, [r7, #4] + 8002586: 2202 movs r2, #2 + 8002588: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800258c: e003 b.n 8002596 + 800258e: 687b ldr r3, [r7, #4] + 8002590: 2202 movs r2, #2 + 8002592: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 8002596: 687b ldr r3, [r7, #4] + 8002598: 681b ldr r3, [r3, #0] + 800259a: 2201 movs r2, #1 + 800259c: 6839 ldr r1, [r7, #0] + 800259e: 4618 mov r0, r3 + 80025a0: f000 fbc5 bl 8002d2e + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 80025a4: 687b ldr r3, [r7, #4] + 80025a6: 681b ldr r3, [r3, #0] + 80025a8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80025ac: d00e beq.n 80025cc + 80025ae: 687b ldr r3, [r7, #4] + 80025b0: 681b ldr r3, [r3, #0] + 80025b2: 4a16 ldr r2, [pc, #88] @ (800260c ) + 80025b4: 4293 cmp r3, r2 + 80025b6: d009 beq.n 80025cc + 80025b8: 687b ldr r3, [r7, #4] + 80025ba: 681b ldr r3, [r3, #0] + 80025bc: 4a14 ldr r2, [pc, #80] @ (8002610 ) + 80025be: 4293 cmp r3, r2 + 80025c0: d004 beq.n 80025cc + 80025c2: 687b ldr r3, [r7, #4] + 80025c4: 681b ldr r3, [r3, #0] + 80025c6: 4a13 ldr r2, [pc, #76] @ (8002614 ) + 80025c8: 4293 cmp r3, r2 + 80025ca: d111 bne.n 80025f0 + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 80025cc: 687b ldr r3, [r7, #4] + 80025ce: 681b ldr r3, [r3, #0] + 80025d0: 689b ldr r3, [r3, #8] + 80025d2: f003 0307 and.w r3, r3, #7 + 80025d6: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80025d8: 68fb ldr r3, [r7, #12] + 80025da: 2b06 cmp r3, #6 + 80025dc: d010 beq.n 8002600 + { + __HAL_TIM_ENABLE(htim); + 80025de: 687b ldr r3, [r7, #4] + 80025e0: 681b ldr r3, [r3, #0] + 80025e2: 681a ldr r2, [r3, #0] + 80025e4: 687b ldr r3, [r7, #4] + 80025e6: 681b ldr r3, [r3, #0] + 80025e8: f042 0201 orr.w r2, r2, #1 + 80025ec: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80025ee: e007 b.n 8002600 + } + } + else + { + __HAL_TIM_ENABLE(htim); + 80025f0: 687b ldr r3, [r7, #4] + 80025f2: 681b ldr r3, [r3, #0] + 80025f4: 681a ldr r2, [r3, #0] + 80025f6: 687b ldr r3, [r7, #4] + 80025f8: 681b ldr r3, [r3, #0] + 80025fa: f042 0201 orr.w r2, r2, #1 + 80025fe: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8002600: 2300 movs r3, #0 +} + 8002602: 4618 mov r0, r3 + 8002604: 3710 adds r7, #16 + 8002606: 46bd mov sp, r7 + 8002608: bd80 pop {r7, pc} + 800260a: bf00 nop + 800260c: 40000400 .word 0x40000400 + 8002610: 40000800 .word 0x40000800 + 8002614: 40010800 .word 0x40010800 + +08002618 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8002618: b580 push {r7, lr} + 800261a: b086 sub sp, #24 + 800261c: af00 add r7, sp, #0 + 800261e: 60f8 str r0, [r7, #12] + 8002620: 60b9 str r1, [r7, #8] + 8002622: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002624: 2300 movs r3, #0 + 8002626: 75fb strb r3, [r7, #23] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8002628: 68fb ldr r3, [r7, #12] + 800262a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 800262e: 2b01 cmp r3, #1 + 8002630: d101 bne.n 8002636 + 8002632: 2302 movs r3, #2 + 8002634: e0ae b.n 8002794 + 8002636: 68fb ldr r3, [r7, #12] + 8002638: 2201 movs r2, #1 + 800263a: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + switch (Channel) + 800263e: 687b ldr r3, [r7, #4] + 8002640: 2b0c cmp r3, #12 + 8002642: f200 809f bhi.w 8002784 + 8002646: a201 add r2, pc, #4 @ (adr r2, 800264c ) + 8002648: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800264c: 08002681 .word 0x08002681 + 8002650: 08002785 .word 0x08002785 + 8002654: 08002785 .word 0x08002785 + 8002658: 08002785 .word 0x08002785 + 800265c: 080026c1 .word 0x080026c1 + 8002660: 08002785 .word 0x08002785 + 8002664: 08002785 .word 0x08002785 + 8002668: 08002785 .word 0x08002785 + 800266c: 08002703 .word 0x08002703 + 8002670: 08002785 .word 0x08002785 + 8002674: 08002785 .word 0x08002785 + 8002678: 08002785 .word 0x08002785 + 800267c: 08002743 .word 0x08002743 + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 8002680: 68fb ldr r3, [r7, #12] + 8002682: 681b ldr r3, [r3, #0] + 8002684: 68b9 ldr r1, [r7, #8] + 8002686: 4618 mov r0, r3 + 8002688: f000 f9c6 bl 8002a18 + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 800268c: 68fb ldr r3, [r7, #12] + 800268e: 681b ldr r3, [r3, #0] + 8002690: 699a ldr r2, [r3, #24] + 8002692: 68fb ldr r3, [r7, #12] + 8002694: 681b ldr r3, [r3, #0] + 8002696: f042 0208 orr.w r2, r2, #8 + 800269a: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 800269c: 68fb ldr r3, [r7, #12] + 800269e: 681b ldr r3, [r3, #0] + 80026a0: 699a ldr r2, [r3, #24] + 80026a2: 68fb ldr r3, [r7, #12] + 80026a4: 681b ldr r3, [r3, #0] + 80026a6: f022 0204 bic.w r2, r2, #4 + 80026aa: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 80026ac: 68fb ldr r3, [r7, #12] + 80026ae: 681b ldr r3, [r3, #0] + 80026b0: 6999 ldr r1, [r3, #24] + 80026b2: 68bb ldr r3, [r7, #8] + 80026b4: 68da ldr r2, [r3, #12] + 80026b6: 68fb ldr r3, [r7, #12] + 80026b8: 681b ldr r3, [r3, #0] + 80026ba: 430a orrs r2, r1 + 80026bc: 619a str r2, [r3, #24] + break; + 80026be: e064 b.n 800278a + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 80026c0: 68fb ldr r3, [r7, #12] + 80026c2: 681b ldr r3, [r3, #0] + 80026c4: 68b9 ldr r1, [r7, #8] + 80026c6: 4618 mov r0, r3 + 80026c8: f000 f9e2 bl 8002a90 + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 80026cc: 68fb ldr r3, [r7, #12] + 80026ce: 681b ldr r3, [r3, #0] + 80026d0: 699a ldr r2, [r3, #24] + 80026d2: 68fb ldr r3, [r7, #12] + 80026d4: 681b ldr r3, [r3, #0] + 80026d6: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 80026da: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 80026dc: 68fb ldr r3, [r7, #12] + 80026de: 681b ldr r3, [r3, #0] + 80026e0: 699a ldr r2, [r3, #24] + 80026e2: 68fb ldr r3, [r7, #12] + 80026e4: 681b ldr r3, [r3, #0] + 80026e6: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 80026ea: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 80026ec: 68fb ldr r3, [r7, #12] + 80026ee: 681b ldr r3, [r3, #0] + 80026f0: 6999 ldr r1, [r3, #24] + 80026f2: 68bb ldr r3, [r7, #8] + 80026f4: 68db ldr r3, [r3, #12] + 80026f6: 021a lsls r2, r3, #8 + 80026f8: 68fb ldr r3, [r7, #12] + 80026fa: 681b ldr r3, [r3, #0] + 80026fc: 430a orrs r2, r1 + 80026fe: 619a str r2, [r3, #24] + break; + 8002700: e043 b.n 800278a + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 8002702: 68fb ldr r3, [r7, #12] + 8002704: 681b ldr r3, [r3, #0] + 8002706: 68b9 ldr r1, [r7, #8] + 8002708: 4618 mov r0, r3 + 800270a: f000 f9ff bl 8002b0c + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 800270e: 68fb ldr r3, [r7, #12] + 8002710: 681b ldr r3, [r3, #0] + 8002712: 69da ldr r2, [r3, #28] + 8002714: 68fb ldr r3, [r7, #12] + 8002716: 681b ldr r3, [r3, #0] + 8002718: f042 0208 orr.w r2, r2, #8 + 800271c: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 800271e: 68fb ldr r3, [r7, #12] + 8002720: 681b ldr r3, [r3, #0] + 8002722: 69da ldr r2, [r3, #28] + 8002724: 68fb ldr r3, [r7, #12] + 8002726: 681b ldr r3, [r3, #0] + 8002728: f022 0204 bic.w r2, r2, #4 + 800272c: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 800272e: 68fb ldr r3, [r7, #12] + 8002730: 681b ldr r3, [r3, #0] + 8002732: 69d9 ldr r1, [r3, #28] + 8002734: 68bb ldr r3, [r7, #8] + 8002736: 68da ldr r2, [r3, #12] + 8002738: 68fb ldr r3, [r7, #12] + 800273a: 681b ldr r3, [r3, #0] + 800273c: 430a orrs r2, r1 + 800273e: 61da str r2, [r3, #28] + break; + 8002740: e023 b.n 800278a + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 8002742: 68fb ldr r3, [r7, #12] + 8002744: 681b ldr r3, [r3, #0] + 8002746: 68b9 ldr r1, [r7, #8] + 8002748: 4618 mov r0, r3 + 800274a: f000 fa1c bl 8002b86 + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 800274e: 68fb ldr r3, [r7, #12] + 8002750: 681b ldr r3, [r3, #0] + 8002752: 69da ldr r2, [r3, #28] + 8002754: 68fb ldr r3, [r7, #12] + 8002756: 681b ldr r3, [r3, #0] + 8002758: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 800275c: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 800275e: 68fb ldr r3, [r7, #12] + 8002760: 681b ldr r3, [r3, #0] + 8002762: 69da ldr r2, [r3, #28] + 8002764: 68fb ldr r3, [r7, #12] + 8002766: 681b ldr r3, [r3, #0] + 8002768: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 800276c: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 800276e: 68fb ldr r3, [r7, #12] + 8002770: 681b ldr r3, [r3, #0] + 8002772: 69d9 ldr r1, [r3, #28] + 8002774: 68bb ldr r3, [r7, #8] + 8002776: 68db ldr r3, [r3, #12] + 8002778: 021a lsls r2, r3, #8 + 800277a: 68fb ldr r3, [r7, #12] + 800277c: 681b ldr r3, [r3, #0] + 800277e: 430a orrs r2, r1 + 8002780: 61da str r2, [r3, #28] + break; + 8002782: e002 b.n 800278a + } + + default: + status = HAL_ERROR; + 8002784: 2301 movs r3, #1 + 8002786: 75fb strb r3, [r7, #23] + break; + 8002788: bf00 nop + } + + __HAL_UNLOCK(htim); + 800278a: 68fb ldr r3, [r7, #12] + 800278c: 2200 movs r2, #0 + 800278e: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 8002792: 7dfb ldrb r3, [r7, #23] +} + 8002794: 4618 mov r0, r3 + 8002796: 3718 adds r7, #24 + 8002798: 46bd mov sp, r7 + 800279a: bd80 pop {r7, pc} + +0800279c : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 800279c: b580 push {r7, lr} + 800279e: b084 sub sp, #16 + 80027a0: af00 add r7, sp, #0 + 80027a2: 6078 str r0, [r7, #4] + 80027a4: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 80027a6: 2300 movs r3, #0 + 80027a8: 73fb strb r3, [r7, #15] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 80027aa: 687b ldr r3, [r7, #4] + 80027ac: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 80027b0: 2b01 cmp r3, #1 + 80027b2: d101 bne.n 80027b8 + 80027b4: 2302 movs r3, #2 + 80027b6: e0b4 b.n 8002922 + 80027b8: 687b ldr r3, [r7, #4] + 80027ba: 2201 movs r2, #1 + 80027bc: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + htim->State = HAL_TIM_STATE_BUSY; + 80027c0: 687b ldr r3, [r7, #4] + 80027c2: 2202 movs r2, #2 + 80027c4: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 80027c8: 687b ldr r3, [r7, #4] + 80027ca: 681b ldr r3, [r3, #0] + 80027cc: 689b ldr r3, [r3, #8] + 80027ce: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 80027d0: 68bb ldr r3, [r7, #8] + 80027d2: f023 0377 bic.w r3, r3, #119 @ 0x77 + 80027d6: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 80027d8: 68bb ldr r3, [r7, #8] + 80027da: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 80027de: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 80027e0: 687b ldr r3, [r7, #4] + 80027e2: 681b ldr r3, [r3, #0] + 80027e4: 68ba ldr r2, [r7, #8] + 80027e6: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 80027e8: 683b ldr r3, [r7, #0] + 80027ea: 681b ldr r3, [r3, #0] + 80027ec: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80027f0: d03e beq.n 8002870 + 80027f2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80027f6: f200 8087 bhi.w 8002908 + 80027fa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80027fe: f000 8086 beq.w 800290e + 8002802: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002806: d87f bhi.n 8002908 + 8002808: 2b70 cmp r3, #112 @ 0x70 + 800280a: d01a beq.n 8002842 + 800280c: 2b70 cmp r3, #112 @ 0x70 + 800280e: d87b bhi.n 8002908 + 8002810: 2b60 cmp r3, #96 @ 0x60 + 8002812: d050 beq.n 80028b6 + 8002814: 2b60 cmp r3, #96 @ 0x60 + 8002816: d877 bhi.n 8002908 + 8002818: 2b50 cmp r3, #80 @ 0x50 + 800281a: d03c beq.n 8002896 + 800281c: 2b50 cmp r3, #80 @ 0x50 + 800281e: d873 bhi.n 8002908 + 8002820: 2b40 cmp r3, #64 @ 0x40 + 8002822: d058 beq.n 80028d6 + 8002824: 2b40 cmp r3, #64 @ 0x40 + 8002826: d86f bhi.n 8002908 + 8002828: 2b30 cmp r3, #48 @ 0x30 + 800282a: d064 beq.n 80028f6 + 800282c: 2b30 cmp r3, #48 @ 0x30 + 800282e: d86b bhi.n 8002908 + 8002830: 2b20 cmp r3, #32 + 8002832: d060 beq.n 80028f6 + 8002834: 2b20 cmp r3, #32 + 8002836: d867 bhi.n 8002908 + 8002838: 2b00 cmp r3, #0 + 800283a: d05c beq.n 80028f6 + 800283c: 2b10 cmp r3, #16 + 800283e: d05a beq.n 80028f6 + 8002840: e062 b.n 8002908 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 8002842: 687b ldr r3, [r7, #4] + 8002844: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8002846: 683b ldr r3, [r7, #0] + 8002848: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 800284a: 683b ldr r3, [r7, #0] + 800284c: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 800284e: 683b ldr r3, [r7, #0] + 8002850: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 8002852: f000 fa4d bl 8002cf0 + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 8002856: 687b ldr r3, [r7, #4] + 8002858: 681b ldr r3, [r3, #0] + 800285a: 689b ldr r3, [r3, #8] + 800285c: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 800285e: 68bb ldr r3, [r7, #8] + 8002860: f043 0377 orr.w r3, r3, #119 @ 0x77 + 8002864: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8002866: 687b ldr r3, [r7, #4] + 8002868: 681b ldr r3, [r3, #0] + 800286a: 68ba ldr r2, [r7, #8] + 800286c: 609a str r2, [r3, #8] + break; + 800286e: e04f b.n 8002910 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 8002870: 687b ldr r3, [r7, #4] + 8002872: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8002874: 683b ldr r3, [r7, #0] + 8002876: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8002878: 683b ldr r3, [r7, #0] + 800287a: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 800287c: 683b ldr r3, [r7, #0] + 800287e: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 8002880: f000 fa36 bl 8002cf0 + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 8002884: 687b ldr r3, [r7, #4] + 8002886: 681b ldr r3, [r3, #0] + 8002888: 689a ldr r2, [r3, #8] + 800288a: 687b ldr r3, [r7, #4] + 800288c: 681b ldr r3, [r3, #0] + 800288e: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8002892: 609a str r2, [r3, #8] + break; + 8002894: e03c b.n 8002910 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 8002896: 687b ldr r3, [r7, #4] + 8002898: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 800289a: 683b ldr r3, [r7, #0] + 800289c: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 800289e: 683b ldr r3, [r7, #0] + 80028a0: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 80028a2: 461a mov r2, r3 + 80028a4: f000 f9ad bl 8002c02 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 80028a8: 687b ldr r3, [r7, #4] + 80028aa: 681b ldr r3, [r3, #0] + 80028ac: 2150 movs r1, #80 @ 0x50 + 80028ae: 4618 mov r0, r3 + 80028b0: f000 fa04 bl 8002cbc + break; + 80028b4: e02c b.n 8002910 + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 80028b6: 687b ldr r3, [r7, #4] + 80028b8: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80028ba: 683b ldr r3, [r7, #0] + 80028bc: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80028be: 683b ldr r3, [r7, #0] + 80028c0: 68db ldr r3, [r3, #12] + TIM_TI2_ConfigInputStage(htim->Instance, + 80028c2: 461a mov r2, r3 + 80028c4: f000 f9cb bl 8002c5e + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 80028c8: 687b ldr r3, [r7, #4] + 80028ca: 681b ldr r3, [r3, #0] + 80028cc: 2160 movs r1, #96 @ 0x60 + 80028ce: 4618 mov r0, r3 + 80028d0: f000 f9f4 bl 8002cbc + break; + 80028d4: e01c b.n 8002910 + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 80028d6: 687b ldr r3, [r7, #4] + 80028d8: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80028da: 683b ldr r3, [r7, #0] + 80028dc: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80028de: 683b ldr r3, [r7, #0] + 80028e0: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 80028e2: 461a mov r2, r3 + 80028e4: f000 f98d bl 8002c02 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 80028e8: 687b ldr r3, [r7, #4] + 80028ea: 681b ldr r3, [r3, #0] + 80028ec: 2140 movs r1, #64 @ 0x40 + 80028ee: 4618 mov r0, r3 + 80028f0: f000 f9e4 bl 8002cbc + break; + 80028f4: e00c b.n 8002910 + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 80028f6: 687b ldr r3, [r7, #4] + 80028f8: 681a ldr r2, [r3, #0] + 80028fa: 683b ldr r3, [r7, #0] + 80028fc: 681b ldr r3, [r3, #0] + 80028fe: 4619 mov r1, r3 + 8002900: 4610 mov r0, r2 + 8002902: f000 f9db bl 8002cbc + break; + 8002906: e003 b.n 8002910 + } + + default: + status = HAL_ERROR; + 8002908: 2301 movs r3, #1 + 800290a: 73fb strb r3, [r7, #15] + break; + 800290c: e000 b.n 8002910 + break; + 800290e: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8002910: 687b ldr r3, [r7, #4] + 8002912: 2201 movs r2, #1 + 8002914: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8002918: 687b ldr r3, [r7, #4] + 800291a: 2200 movs r2, #0 + 800291c: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 8002920: 7bfb ldrb r3, [r7, #15] +} + 8002922: 4618 mov r0, r3 + 8002924: 3710 adds r7, #16 + 8002926: 46bd mov sp, r7 + 8002928: bd80 pop {r7, pc} + ... + +0800292c : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 800292c: b480 push {r7} + 800292e: b085 sub sp, #20 + 8002930: af00 add r7, sp, #0 + 8002932: 6078 str r0, [r7, #4] + 8002934: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8002936: 687b ldr r3, [r7, #4] + 8002938: 681b ldr r3, [r3, #0] + 800293a: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 800293c: 687b ldr r3, [r7, #4] + 800293e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002942: d00f beq.n 8002964 + 8002944: 687b ldr r3, [r7, #4] + 8002946: 4a2e ldr r2, [pc, #184] @ (8002a00 ) + 8002948: 4293 cmp r3, r2 + 800294a: d00b beq.n 8002964 + 800294c: 687b ldr r3, [r7, #4] + 800294e: 4a2d ldr r2, [pc, #180] @ (8002a04 ) + 8002950: 4293 cmp r3, r2 + 8002952: d007 beq.n 8002964 + 8002954: 687b ldr r3, [r7, #4] + 8002956: 4a2c ldr r2, [pc, #176] @ (8002a08 ) + 8002958: 4293 cmp r3, r2 + 800295a: d003 beq.n 8002964 + 800295c: 687b ldr r3, [r7, #4] + 800295e: 4a2b ldr r2, [pc, #172] @ (8002a0c ) + 8002960: 4293 cmp r3, r2 + 8002962: d108 bne.n 8002976 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8002964: 68fb ldr r3, [r7, #12] + 8002966: f023 0370 bic.w r3, r3, #112 @ 0x70 + 800296a: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 800296c: 683b ldr r3, [r7, #0] + 800296e: 685b ldr r3, [r3, #4] + 8002970: 68fa ldr r2, [r7, #12] + 8002972: 4313 orrs r3, r2 + 8002974: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8002976: 687b ldr r3, [r7, #4] + 8002978: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 800297c: d017 beq.n 80029ae + 800297e: 687b ldr r3, [r7, #4] + 8002980: 4a1f ldr r2, [pc, #124] @ (8002a00 ) + 8002982: 4293 cmp r3, r2 + 8002984: d013 beq.n 80029ae + 8002986: 687b ldr r3, [r7, #4] + 8002988: 4a1e ldr r2, [pc, #120] @ (8002a04 ) + 800298a: 4293 cmp r3, r2 + 800298c: d00f beq.n 80029ae + 800298e: 687b ldr r3, [r7, #4] + 8002990: 4a1d ldr r2, [pc, #116] @ (8002a08 ) + 8002992: 4293 cmp r3, r2 + 8002994: d00b beq.n 80029ae + 8002996: 687b ldr r3, [r7, #4] + 8002998: 4a1c ldr r2, [pc, #112] @ (8002a0c ) + 800299a: 4293 cmp r3, r2 + 800299c: d007 beq.n 80029ae + 800299e: 687b ldr r3, [r7, #4] + 80029a0: 4a1b ldr r2, [pc, #108] @ (8002a10 ) + 80029a2: 4293 cmp r3, r2 + 80029a4: d003 beq.n 80029ae + 80029a6: 687b ldr r3, [r7, #4] + 80029a8: 4a1a ldr r2, [pc, #104] @ (8002a14 ) + 80029aa: 4293 cmp r3, r2 + 80029ac: d108 bne.n 80029c0 + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 80029ae: 68fb ldr r3, [r7, #12] + 80029b0: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80029b4: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 80029b6: 683b ldr r3, [r7, #0] + 80029b8: 68db ldr r3, [r3, #12] + 80029ba: 68fa ldr r2, [r7, #12] + 80029bc: 4313 orrs r3, r2 + 80029be: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 80029c0: 68fb ldr r3, [r7, #12] + 80029c2: f023 0280 bic.w r2, r3, #128 @ 0x80 + 80029c6: 683b ldr r3, [r7, #0] + 80029c8: 691b ldr r3, [r3, #16] + 80029ca: 4313 orrs r3, r2 + 80029cc: 60fb str r3, [r7, #12] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 80029ce: 683b ldr r3, [r7, #0] + 80029d0: 689a ldr r2, [r3, #8] + 80029d2: 687b ldr r3, [r7, #4] + 80029d4: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 80029d6: 683b ldr r3, [r7, #0] + 80029d8: 681a ldr r2, [r3, #0] + 80029da: 687b ldr r3, [r7, #4] + 80029dc: 629a str r2, [r3, #40] @ 0x28 + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + 80029de: 687b ldr r3, [r7, #4] + 80029e0: 681b ldr r3, [r3, #0] + 80029e2: f043 0204 orr.w r2, r3, #4 + 80029e6: 687b ldr r3, [r7, #4] + 80029e8: 601a str r2, [r3, #0] + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 80029ea: 687b ldr r3, [r7, #4] + 80029ec: 2201 movs r2, #1 + 80029ee: 615a str r2, [r3, #20] + + TIMx->CR1 = tmpcr1; + 80029f0: 687b ldr r3, [r7, #4] + 80029f2: 68fa ldr r2, [r7, #12] + 80029f4: 601a str r2, [r3, #0] +} + 80029f6: bf00 nop + 80029f8: 3714 adds r7, #20 + 80029fa: 46bd mov sp, r7 + 80029fc: bc80 pop {r7} + 80029fe: 4770 bx lr + 8002a00: 40000400 .word 0x40000400 + 8002a04: 40000800 .word 0x40000800 + 8002a08: 40000c00 .word 0x40000c00 + 8002a0c: 40010800 .word 0x40010800 + 8002a10: 40010c00 .word 0x40010c00 + 8002a14: 40011000 .word 0x40011000 + +08002a18 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002a18: b480 push {r7} + 8002a1a: b087 sub sp, #28 + 8002a1c: af00 add r7, sp, #0 + 8002a1e: 6078 str r0, [r7, #4] + 8002a20: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002a22: 687b ldr r3, [r7, #4] + 8002a24: 6a1b ldr r3, [r3, #32] + 8002a26: 617b str r3, [r7, #20] + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002a28: 687b ldr r3, [r7, #4] + 8002a2a: 6a1b ldr r3, [r3, #32] + 8002a2c: f023 0201 bic.w r2, r3, #1 + 8002a30: 687b ldr r3, [r7, #4] + 8002a32: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002a34: 687b ldr r3, [r7, #4] + 8002a36: 685b ldr r3, [r3, #4] + 8002a38: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002a3a: 687b ldr r3, [r7, #4] + 8002a3c: 699b ldr r3, [r3, #24] + 8002a3e: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 8002a40: 68fb ldr r3, [r7, #12] + 8002a42: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002a46: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 8002a48: 68fb ldr r3, [r7, #12] + 8002a4a: f023 0303 bic.w r3, r3, #3 + 8002a4e: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002a50: 683b ldr r3, [r7, #0] + 8002a52: 681b ldr r3, [r3, #0] + 8002a54: 68fa ldr r2, [r7, #12] + 8002a56: 4313 orrs r3, r2 + 8002a58: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 8002a5a: 697b ldr r3, [r7, #20] + 8002a5c: f023 0302 bic.w r3, r3, #2 + 8002a60: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 8002a62: 683b ldr r3, [r7, #0] + 8002a64: 689b ldr r3, [r3, #8] + 8002a66: 697a ldr r2, [r7, #20] + 8002a68: 4313 orrs r3, r2 + 8002a6a: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002a6c: 687b ldr r3, [r7, #4] + 8002a6e: 693a ldr r2, [r7, #16] + 8002a70: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002a72: 687b ldr r3, [r7, #4] + 8002a74: 68fa ldr r2, [r7, #12] + 8002a76: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 8002a78: 683b ldr r3, [r7, #0] + 8002a7a: 685a ldr r2, [r3, #4] + 8002a7c: 687b ldr r3, [r7, #4] + 8002a7e: 635a str r2, [r3, #52] @ 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002a80: 687b ldr r3, [r7, #4] + 8002a82: 697a ldr r2, [r7, #20] + 8002a84: 621a str r2, [r3, #32] +} + 8002a86: bf00 nop + 8002a88: 371c adds r7, #28 + 8002a8a: 46bd mov sp, r7 + 8002a8c: bc80 pop {r7} + 8002a8e: 4770 bx lr + +08002a90 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002a90: b480 push {r7} + 8002a92: b087 sub sp, #28 + 8002a94: af00 add r7, sp, #0 + 8002a96: 6078 str r0, [r7, #4] + 8002a98: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002a9a: 687b ldr r3, [r7, #4] + 8002a9c: 6a1b ldr r3, [r3, #32] + 8002a9e: 617b str r3, [r7, #20] + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002aa0: 687b ldr r3, [r7, #4] + 8002aa2: 6a1b ldr r3, [r3, #32] + 8002aa4: f023 0210 bic.w r2, r3, #16 + 8002aa8: 687b ldr r3, [r7, #4] + 8002aaa: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002aac: 687b ldr r3, [r7, #4] + 8002aae: 685b ldr r3, [r3, #4] + 8002ab0: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002ab2: 687b ldr r3, [r7, #4] + 8002ab4: 699b ldr r3, [r3, #24] + 8002ab6: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8002ab8: 68fb ldr r3, [r7, #12] + 8002aba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002abe: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8002ac0: 68fb ldr r3, [r7, #12] + 8002ac2: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002ac6: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002ac8: 683b ldr r3, [r7, #0] + 8002aca: 681b ldr r3, [r3, #0] + 8002acc: 021b lsls r3, r3, #8 + 8002ace: 68fa ldr r2, [r7, #12] + 8002ad0: 4313 orrs r3, r2 + 8002ad2: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8002ad4: 697b ldr r3, [r7, #20] + 8002ad6: f023 0320 bic.w r3, r3, #32 + 8002ada: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 8002adc: 683b ldr r3, [r7, #0] + 8002ade: 689b ldr r3, [r3, #8] + 8002ae0: 011b lsls r3, r3, #4 + 8002ae2: 697a ldr r2, [r7, #20] + 8002ae4: 4313 orrs r3, r2 + 8002ae6: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002ae8: 687b ldr r3, [r7, #4] + 8002aea: 693a ldr r2, [r7, #16] + 8002aec: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002aee: 687b ldr r3, [r7, #4] + 8002af0: 68fa ldr r2, [r7, #12] + 8002af2: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8002af4: 683b ldr r3, [r7, #0] + 8002af6: 685a ldr r2, [r3, #4] + 8002af8: 687b ldr r3, [r7, #4] + 8002afa: 639a str r2, [r3, #56] @ 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002afc: 687b ldr r3, [r7, #4] + 8002afe: 697a ldr r2, [r7, #20] + 8002b00: 621a str r2, [r3, #32] +} + 8002b02: bf00 nop + 8002b04: 371c adds r7, #28 + 8002b06: 46bd mov sp, r7 + 8002b08: bc80 pop {r7} + 8002b0a: 4770 bx lr + +08002b0c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002b0c: b480 push {r7} + 8002b0e: b087 sub sp, #28 + 8002b10: af00 add r7, sp, #0 + 8002b12: 6078 str r0, [r7, #4] + 8002b14: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002b16: 687b ldr r3, [r7, #4] + 8002b18: 6a1b ldr r3, [r3, #32] + 8002b1a: 617b str r3, [r7, #20] + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8002b1c: 687b ldr r3, [r7, #4] + 8002b1e: 6a1b ldr r3, [r3, #32] + 8002b20: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8002b24: 687b ldr r3, [r7, #4] + 8002b26: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002b28: 687b ldr r3, [r7, #4] + 8002b2a: 685b ldr r3, [r3, #4] + 8002b2c: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002b2e: 687b ldr r3, [r7, #4] + 8002b30: 69db ldr r3, [r3, #28] + 8002b32: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8002b34: 68fb ldr r3, [r7, #12] + 8002b36: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002b3a: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8002b3c: 68fb ldr r3, [r7, #12] + 8002b3e: f023 0303 bic.w r3, r3, #3 + 8002b42: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002b44: 683b ldr r3, [r7, #0] + 8002b46: 681b ldr r3, [r3, #0] + 8002b48: 68fa ldr r2, [r7, #12] + 8002b4a: 4313 orrs r3, r2 + 8002b4c: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8002b4e: 697b ldr r3, [r7, #20] + 8002b50: f423 7300 bic.w r3, r3, #512 @ 0x200 + 8002b54: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 8002b56: 683b ldr r3, [r7, #0] + 8002b58: 689b ldr r3, [r3, #8] + 8002b5a: 021b lsls r3, r3, #8 + 8002b5c: 697a ldr r2, [r7, #20] + 8002b5e: 4313 orrs r3, r2 + 8002b60: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002b62: 687b ldr r3, [r7, #4] + 8002b64: 693a ldr r2, [r7, #16] + 8002b66: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002b68: 687b ldr r3, [r7, #4] + 8002b6a: 68fa ldr r2, [r7, #12] + 8002b6c: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 8002b6e: 683b ldr r3, [r7, #0] + 8002b70: 685a ldr r2, [r3, #4] + 8002b72: 687b ldr r3, [r7, #4] + 8002b74: 63da str r2, [r3, #60] @ 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002b76: 687b ldr r3, [r7, #4] + 8002b78: 697a ldr r2, [r7, #20] + 8002b7a: 621a str r2, [r3, #32] +} + 8002b7c: bf00 nop + 8002b7e: 371c adds r7, #28 + 8002b80: 46bd mov sp, r7 + 8002b82: bc80 pop {r7} + 8002b84: 4770 bx lr + +08002b86 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002b86: b480 push {r7} + 8002b88: b087 sub sp, #28 + 8002b8a: af00 add r7, sp, #0 + 8002b8c: 6078 str r0, [r7, #4] + 8002b8e: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002b90: 687b ldr r3, [r7, #4] + 8002b92: 6a1b ldr r3, [r3, #32] + 8002b94: 617b str r3, [r7, #20] + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8002b96: 687b ldr r3, [r7, #4] + 8002b98: 6a1b ldr r3, [r3, #32] + 8002b9a: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8002b9e: 687b ldr r3, [r7, #4] + 8002ba0: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002ba2: 687b ldr r3, [r7, #4] + 8002ba4: 685b ldr r3, [r3, #4] + 8002ba6: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002ba8: 687b ldr r3, [r7, #4] + 8002baa: 69db ldr r3, [r3, #28] + 8002bac: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8002bae: 68fb ldr r3, [r7, #12] + 8002bb0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002bb4: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8002bb6: 68fb ldr r3, [r7, #12] + 8002bb8: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002bbc: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002bbe: 683b ldr r3, [r7, #0] + 8002bc0: 681b ldr r3, [r3, #0] + 8002bc2: 021b lsls r3, r3, #8 + 8002bc4: 68fa ldr r2, [r7, #12] + 8002bc6: 4313 orrs r3, r2 + 8002bc8: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8002bca: 697b ldr r3, [r7, #20] + 8002bcc: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 8002bd0: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8002bd2: 683b ldr r3, [r7, #0] + 8002bd4: 689b ldr r3, [r3, #8] + 8002bd6: 031b lsls r3, r3, #12 + 8002bd8: 697a ldr r2, [r7, #20] + 8002bda: 4313 orrs r3, r2 + 8002bdc: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002bde: 687b ldr r3, [r7, #4] + 8002be0: 693a ldr r2, [r7, #16] + 8002be2: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002be4: 687b ldr r3, [r7, #4] + 8002be6: 68fa ldr r2, [r7, #12] + 8002be8: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 8002bea: 683b ldr r3, [r7, #0] + 8002bec: 685a ldr r2, [r3, #4] + 8002bee: 687b ldr r3, [r7, #4] + 8002bf0: 641a str r2, [r3, #64] @ 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002bf2: 687b ldr r3, [r7, #4] + 8002bf4: 697a ldr r2, [r7, #20] + 8002bf6: 621a str r2, [r3, #32] +} + 8002bf8: bf00 nop + 8002bfa: 371c adds r7, #28 + 8002bfc: 46bd mov sp, r7 + 8002bfe: bc80 pop {r7} + 8002c00: 4770 bx lr + +08002c02 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002c02: b480 push {r7} + 8002c04: b087 sub sp, #28 + 8002c06: af00 add r7, sp, #0 + 8002c08: 60f8 str r0, [r7, #12] + 8002c0a: 60b9 str r1, [r7, #8] + 8002c0c: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8002c0e: 68fb ldr r3, [r7, #12] + 8002c10: 6a1b ldr r3, [r3, #32] + 8002c12: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002c14: 68fb ldr r3, [r7, #12] + 8002c16: 6a1b ldr r3, [r3, #32] + 8002c18: f023 0201 bic.w r2, r3, #1 + 8002c1c: 68fb ldr r3, [r7, #12] + 8002c1e: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8002c20: 68fb ldr r3, [r7, #12] + 8002c22: 699b ldr r3, [r3, #24] + 8002c24: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8002c26: 693b ldr r3, [r7, #16] + 8002c28: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8002c2c: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8002c2e: 687b ldr r3, [r7, #4] + 8002c30: 011b lsls r3, r3, #4 + 8002c32: 693a ldr r2, [r7, #16] + 8002c34: 4313 orrs r3, r2 + 8002c36: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 8002c38: 697b ldr r3, [r7, #20] + 8002c3a: f023 030a bic.w r3, r3, #10 + 8002c3e: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8002c40: 697a ldr r2, [r7, #20] + 8002c42: 68bb ldr r3, [r7, #8] + 8002c44: 4313 orrs r3, r2 + 8002c46: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 8002c48: 68fb ldr r3, [r7, #12] + 8002c4a: 693a ldr r2, [r7, #16] + 8002c4c: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8002c4e: 68fb ldr r3, [r7, #12] + 8002c50: 697a ldr r2, [r7, #20] + 8002c52: 621a str r2, [r3, #32] +} + 8002c54: bf00 nop + 8002c56: 371c adds r7, #28 + 8002c58: 46bd mov sp, r7 + 8002c5a: bc80 pop {r7} + 8002c5c: 4770 bx lr + +08002c5e : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002c5e: b480 push {r7} + 8002c60: b087 sub sp, #28 + 8002c62: af00 add r7, sp, #0 + 8002c64: 60f8 str r0, [r7, #12] + 8002c66: 60b9 str r1, [r7, #8] + 8002c68: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + 8002c6a: 68fb ldr r3, [r7, #12] + 8002c6c: 6a1b ldr r3, [r3, #32] + 8002c6e: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002c70: 68fb ldr r3, [r7, #12] + 8002c72: 6a1b ldr r3, [r3, #32] + 8002c74: f023 0210 bic.w r2, r3, #16 + 8002c78: 68fb ldr r3, [r7, #12] + 8002c7a: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8002c7c: 68fb ldr r3, [r7, #12] + 8002c7e: 699b ldr r3, [r3, #24] + 8002c80: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8002c82: 693b ldr r3, [r7, #16] + 8002c84: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 8002c88: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 12U); + 8002c8a: 687b ldr r3, [r7, #4] + 8002c8c: 031b lsls r3, r3, #12 + 8002c8e: 693a ldr r2, [r7, #16] + 8002c90: 4313 orrs r3, r2 + 8002c92: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8002c94: 697b ldr r3, [r7, #20] + 8002c96: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 8002c9a: 617b str r3, [r7, #20] + tmpccer |= (TIM_ICPolarity << 4U); + 8002c9c: 68bb ldr r3, [r7, #8] + 8002c9e: 011b lsls r3, r3, #4 + 8002ca0: 697a ldr r2, [r7, #20] + 8002ca2: 4313 orrs r3, r2 + 8002ca4: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 8002ca6: 68fb ldr r3, [r7, #12] + 8002ca8: 693a ldr r2, [r7, #16] + 8002caa: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8002cac: 68fb ldr r3, [r7, #12] + 8002cae: 697a ldr r2, [r7, #20] + 8002cb0: 621a str r2, [r3, #32] +} + 8002cb2: bf00 nop + 8002cb4: 371c adds r7, #28 + 8002cb6: 46bd mov sp, r7 + 8002cb8: bc80 pop {r7} + 8002cba: 4770 bx lr + +08002cbc : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 8002cbc: b480 push {r7} + 8002cbe: b085 sub sp, #20 + 8002cc0: af00 add r7, sp, #0 + 8002cc2: 6078 str r0, [r7, #4] + 8002cc4: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8002cc6: 687b ldr r3, [r7, #4] + 8002cc8: 689b ldr r3, [r3, #8] + 8002cca: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8002ccc: 68fb ldr r3, [r7, #12] + 8002cce: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002cd2: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8002cd4: 683a ldr r2, [r7, #0] + 8002cd6: 68fb ldr r3, [r7, #12] + 8002cd8: 4313 orrs r3, r2 + 8002cda: f043 0307 orr.w r3, r3, #7 + 8002cde: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8002ce0: 687b ldr r3, [r7, #4] + 8002ce2: 68fa ldr r2, [r7, #12] + 8002ce4: 609a str r2, [r3, #8] +} + 8002ce6: bf00 nop + 8002ce8: 3714 adds r7, #20 + 8002cea: 46bd mov sp, r7 + 8002cec: bc80 pop {r7} + 8002cee: 4770 bx lr + +08002cf0 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8002cf0: b480 push {r7} + 8002cf2: b087 sub sp, #28 + 8002cf4: af00 add r7, sp, #0 + 8002cf6: 60f8 str r0, [r7, #12] + 8002cf8: 60b9 str r1, [r7, #8] + 8002cfa: 607a str r2, [r7, #4] + 8002cfc: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 8002cfe: 68fb ldr r3, [r7, #12] + 8002d00: 689b ldr r3, [r3, #8] + 8002d02: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8002d04: 697b ldr r3, [r7, #20] + 8002d06: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 8002d0a: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8002d0c: 683b ldr r3, [r7, #0] + 8002d0e: 021a lsls r2, r3, #8 + 8002d10: 687b ldr r3, [r7, #4] + 8002d12: 431a orrs r2, r3 + 8002d14: 68bb ldr r3, [r7, #8] + 8002d16: 4313 orrs r3, r2 + 8002d18: 697a ldr r2, [r7, #20] + 8002d1a: 4313 orrs r3, r2 + 8002d1c: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8002d1e: 68fb ldr r3, [r7, #12] + 8002d20: 697a ldr r2, [r7, #20] + 8002d22: 609a str r2, [r3, #8] +} + 8002d24: bf00 nop + 8002d26: 371c adds r7, #28 + 8002d28: 46bd mov sp, r7 + 8002d2a: bc80 pop {r7} + 8002d2c: 4770 bx lr + +08002d2e : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 8002d2e: b480 push {r7} + 8002d30: b087 sub sp, #28 + 8002d32: af00 add r7, sp, #0 + 8002d34: 60f8 str r0, [r7, #12] + 8002d36: 60b9 str r1, [r7, #8] + 8002d38: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 8002d3a: 68bb ldr r3, [r7, #8] + 8002d3c: f003 031f and.w r3, r3, #31 + 8002d40: 2201 movs r2, #1 + 8002d42: fa02 f303 lsl.w r3, r2, r3 + 8002d46: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 8002d48: 68fb ldr r3, [r7, #12] + 8002d4a: 6a1a ldr r2, [r3, #32] + 8002d4c: 697b ldr r3, [r7, #20] + 8002d4e: 43db mvns r3, r3 + 8002d50: 401a ands r2, r3 + 8002d52: 68fb ldr r3, [r7, #12] + 8002d54: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8002d56: 68fb ldr r3, [r7, #12] + 8002d58: 6a1a ldr r2, [r3, #32] + 8002d5a: 68bb ldr r3, [r7, #8] + 8002d5c: f003 031f and.w r3, r3, #31 + 8002d60: 6879 ldr r1, [r7, #4] + 8002d62: fa01 f303 lsl.w r3, r1, r3 + 8002d66: 431a orrs r2, r3 + 8002d68: 68fb ldr r3, [r7, #12] + 8002d6a: 621a str r2, [r3, #32] +} + 8002d6c: bf00 nop + 8002d6e: 371c adds r7, #28 + 8002d70: 46bd mov sp, r7 + 8002d72: bc80 pop {r7} + 8002d74: 4770 bx lr + ... + +08002d78 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8002d78: b480 push {r7} + 8002d7a: b085 sub sp, #20 + 8002d7c: af00 add r7, sp, #0 + 8002d7e: 6078 str r0, [r7, #4] + 8002d80: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 8002d82: 687b ldr r3, [r7, #4] + 8002d84: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 8002d88: 2b01 cmp r3, #1 + 8002d8a: d101 bne.n 8002d90 + 8002d8c: 2302 movs r3, #2 + 8002d8e: e046 b.n 8002e1e + 8002d90: 687b ldr r3, [r7, #4] + 8002d92: 2201 movs r2, #1 + 8002d94: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002d98: 687b ldr r3, [r7, #4] + 8002d9a: 2202 movs r2, #2 + 8002d9c: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8002da0: 687b ldr r3, [r7, #4] + 8002da2: 681b ldr r3, [r3, #0] + 8002da4: 685b ldr r3, [r3, #4] + 8002da6: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8002da8: 687b ldr r3, [r7, #4] + 8002daa: 681b ldr r3, [r3, #0] + 8002dac: 689b ldr r3, [r3, #8] + 8002dae: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8002db0: 68fb ldr r3, [r7, #12] + 8002db2: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002db6: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8002db8: 683b ldr r3, [r7, #0] + 8002dba: 681b ldr r3, [r3, #0] + 8002dbc: 68fa ldr r2, [r7, #12] + 8002dbe: 4313 orrs r3, r2 + 8002dc0: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8002dc2: 687b ldr r3, [r7, #4] + 8002dc4: 681b ldr r3, [r3, #0] + 8002dc6: 68fa ldr r2, [r7, #12] + 8002dc8: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8002dca: 687b ldr r3, [r7, #4] + 8002dcc: 681b ldr r3, [r3, #0] + 8002dce: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002dd2: d00e beq.n 8002df2 + 8002dd4: 687b ldr r3, [r7, #4] + 8002dd6: 681b ldr r3, [r3, #0] + 8002dd8: 4a13 ldr r2, [pc, #76] @ (8002e28 ) + 8002dda: 4293 cmp r3, r2 + 8002ddc: d009 beq.n 8002df2 + 8002dde: 687b ldr r3, [r7, #4] + 8002de0: 681b ldr r3, [r3, #0] + 8002de2: 4a12 ldr r2, [pc, #72] @ (8002e2c ) + 8002de4: 4293 cmp r3, r2 + 8002de6: d004 beq.n 8002df2 + 8002de8: 687b ldr r3, [r7, #4] + 8002dea: 681b ldr r3, [r3, #0] + 8002dec: 4a10 ldr r2, [pc, #64] @ (8002e30 ) + 8002dee: 4293 cmp r3, r2 + 8002df0: d10c bne.n 8002e0c + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8002df2: 68bb ldr r3, [r7, #8] + 8002df4: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8002df8: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8002dfa: 683b ldr r3, [r7, #0] + 8002dfc: 685b ldr r3, [r3, #4] + 8002dfe: 68ba ldr r2, [r7, #8] + 8002e00: 4313 orrs r3, r2 + 8002e02: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8002e04: 687b ldr r3, [r7, #4] + 8002e06: 681b ldr r3, [r3, #0] + 8002e08: 68ba ldr r2, [r7, #8] + 8002e0a: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8002e0c: 687b ldr r3, [r7, #4] + 8002e0e: 2201 movs r2, #1 + 8002e10: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8002e14: 687b ldr r3, [r7, #4] + 8002e16: 2200 movs r2, #0 + 8002e18: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return HAL_OK; + 8002e1c: 2300 movs r3, #0 +} + 8002e1e: 4618 mov r0, r3 + 8002e20: 3714 adds r7, #20 + 8002e22: 46bd mov sp, r7 + 8002e24: bc80 pop {r7} + 8002e26: 4770 bx lr + 8002e28: 40000400 .word 0x40000400 + 8002e2c: 40000800 .word 0x40000800 + 8002e30: 40010800 .word 0x40010800 + +08002e34 : + 8002e34: 4603 mov r3, r0 + 8002e36: 4402 add r2, r0 + 8002e38: 4293 cmp r3, r2 + 8002e3a: d100 bne.n 8002e3e + 8002e3c: 4770 bx lr + 8002e3e: f803 1b01 strb.w r1, [r3], #1 + 8002e42: e7f9 b.n 8002e38 + +08002e44 <__libc_init_array>: + 8002e44: b570 push {r4, r5, r6, lr} + 8002e46: 2600 movs r6, #0 + 8002e48: 4d0c ldr r5, [pc, #48] @ (8002e7c <__libc_init_array+0x38>) + 8002e4a: 4c0d ldr r4, [pc, #52] @ (8002e80 <__libc_init_array+0x3c>) + 8002e4c: 1b64 subs r4, r4, r5 + 8002e4e: 10a4 asrs r4, r4, #2 + 8002e50: 42a6 cmp r6, r4 + 8002e52: d109 bne.n 8002e68 <__libc_init_array+0x24> + 8002e54: f000 f81a bl 8002e8c <_init> + 8002e58: 2600 movs r6, #0 + 8002e5a: 4d0a ldr r5, [pc, #40] @ (8002e84 <__libc_init_array+0x40>) + 8002e5c: 4c0a ldr r4, [pc, #40] @ (8002e88 <__libc_init_array+0x44>) + 8002e5e: 1b64 subs r4, r4, r5 + 8002e60: 10a4 asrs r4, r4, #2 + 8002e62: 42a6 cmp r6, r4 + 8002e64: d105 bne.n 8002e72 <__libc_init_array+0x2e> + 8002e66: bd70 pop {r4, r5, r6, pc} + 8002e68: f855 3b04 ldr.w r3, [r5], #4 + 8002e6c: 4798 blx r3 + 8002e6e: 3601 adds r6, #1 + 8002e70: e7ee b.n 8002e50 <__libc_init_array+0xc> + 8002e72: f855 3b04 ldr.w r3, [r5], #4 + 8002e76: 4798 blx r3 + 8002e78: 3601 adds r6, #1 + 8002e7a: e7f2 b.n 8002e62 <__libc_init_array+0x1e> + 8002e7c: 08002ed8 .word 0x08002ed8 + 8002e80: 08002ed8 .word 0x08002ed8 + 8002e84: 08002ed8 .word 0x08002ed8 + 8002e88: 08002edc .word 0x08002edc + +08002e8c <_init>: + 8002e8c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002e8e: bf00 nop + 8002e90: bcf8 pop {r3, r4, r5, r6, r7} + 8002e92: bc08 pop {r3} + 8002e94: 469e mov lr, r3 + 8002e96: 4770 bx lr + +08002e98 <_fini>: + 8002e98: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002e9a: bf00 nop + 8002e9c: bcf8 pop {r3, r4, r5, r6, r7} + 8002e9e: bc08 pop {r3} + 8002ea0: 469e mov lr, r3 + 8002ea2: 4770 bx lr diff --git a/TP4_INIT_TFT/Debug/TP4_GAMME.map b/TP4_INIT_TFT/Debug/TP4_GAMME.map new file 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o +START GROUP +LOAD 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*(.init) + .init 0x08002e8c 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x08002e8c _init + .init 0x08002e90 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + *(.fini) + .fini 0x08002e98 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x08002e98 _fini + .fini 0x08002e9c 0x8 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0x08002ec0 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x08002ec0 conv_7seg + 0x08002ed0 . = ALIGN (0x4) + +.ARM.extab 0x08002ed0 0x0 + 0x08002ed0 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x08002ed0 . = ALIGN (0x4) + +.ARM 0x08002ed0 0x8 + 0x08002ed0 . = ALIGN (0x4) + 0x08002ed0 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x08002ed0 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + 0x08002ed8 __exidx_end = . + 0x08002ed8 . = ALIGN (0x4) + +.preinit_array 0x08002ed8 0x0 + 0x08002ed8 . = ALIGN (0x4) + 0x08002ed8 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x08002ed8 PROVIDE (__preinit_array_end = .) + 0x08002ed8 . = ALIGN (0x4) + +.init_array 0x08002ed8 0x4 + 0x08002ed8 . = ALIGN (0x4) + 0x08002ed8 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x08002ed8 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + 0x08002edc PROVIDE (__init_array_end = .) + 0x08002edc . = ALIGN (0x4) + +.fini_array 0x08002edc 0x4 + 0x08002edc . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x08002edc 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08002ee0 . = ALIGN (0x4) + 0x08002ee0 _sidata = LOADADDR (.data) + +.rel.dyn 0x08002ee0 0x0 + .rel.iplt 0x08002ee0 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + +.data 0x20000000 0xc load address 0x08002ee0 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x20000000 0x4 ./Core/Src/system_stm32l1xx.o + 0x20000000 SystemCoreClock + .data.uwTickPrio + 0x20000004 0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x20000004 uwTickPrio + .data.uwTickFreq + 0x20000008 0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x20000008 uwTickFreq + *(.RamFunc) + *(.RamFunc*) + 0x2000000c . = ALIGN (0x4) + 0x2000000c _edata = . + +.igot.plt 0x2000000c 0x0 load address 0x08002eec + .igot.plt 0x2000000c 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + 0x2000000c . = ALIGN (0x4) + +.bss 0x2000000c 0xb8 load address 0x08002eec + 0x2000000c _sbss = . + 0x2000000c __bss_start__ = _sbss + *(.bss) + .bss 0x2000000c 0x1c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + *(.bss*) + .bss.hspi1 0x20000028 0x58 ./Core/Src/main.o + 0x20000028 hspi1 + .bss.htim3 0x20000080 0x40 ./Core/Src/main.o + 0x20000080 htim3 + .bss.uwTick 0x200000c0 0x4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x200000c0 uwTick + *(COMMON) + 0x200000c4 . = ALIGN (0x4) + 0x200000c4 _ebss = . + 0x200000c4 __bss_end__ = _ebss + +._user_heap_stack + 0x200000c4 0x604 load address 0x08002eec + 0x200000c8 . = ALIGN (0x8) + *fill* 0x200000c4 0x4 + [!provide] PROVIDE (end = .) + 0x200000c8 PROVIDE (_end = .) + 0x200002c8 . = (. + _Min_Heap_Size) + *fill* 0x200000c8 0x200 + 0x200006c8 . = (. + _Min_Stack_Size) + *fill* 0x200002c8 0x400 + 0x200006c8 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x29 + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + .ARM.attributes + 0x0000001d 0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + .ARM.attributes + 0x0000004a 0x2d ./Core/Src/main.o + .ARM.attributes + 0x00000077 0x2d ./Core/Src/stm32l1xx_hal_msp.o + .ARM.attributes + 0x000000a4 0x2d ./Core/Src/stm32l1xx_it.o + .ARM.attributes + 0x000000d1 0x2d ./Core/Src/system_stm32l1xx.o + .ARM.attributes + 0x000000fe 0x21 ./Core/Startup/startup_stm32l152retx.o + .ARM.attributes + 0x0000011f 0x2d ./Drivers/7Seg_MAX7219/max7219.o + .ARM.attributes + 0x0000014c 0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .ARM.attributes + 0x00000179 0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .ARM.attributes + 0x000001a6 0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .ARM.attributes + 0x000001d3 0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .ARM.attributes + 0x00000200 0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .ARM.attributes + 0x0000022d 0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .ARM.attributes + 0x0000025a 0x2d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + .ARM.attributes + 0x00000287 0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x000002b4 0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x000002e1 0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x000002fe 0x2d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x0000032b 0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x00000348 0x1d /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o +OUTPUT(TP4_GAMME.elf elf32-littlearm) +LOAD linker stubs +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libm.a +LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a + +.debug_info 0x00000000 0x90ef + .debug_info 0x00000000 0x1268 ./Core/Src/main.o + .debug_info 0x00001268 0xc12 ./Core/Src/stm32l1xx_hal_msp.o + .debug_info 0x00001e7a 0x14c ./Core/Src/stm32l1xx_it.o + .debug_info 0x00001fc6 0x27c ./Core/Src/system_stm32l1xx.o + .debug_info 0x00002242 0x30 ./Core/Startup/startup_stm32l152retx.o + .debug_info 0x00002272 0x80e ./Drivers/7Seg_MAX7219/max7219.o + .debug_info 0x00002a80 0x6ef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_info 0x0000316f 0xce5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_info 0x00003e54 0x5b2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_info 0x00004406 0x99b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_info 0x00004da1 0x14d9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_info 0x0000627a 0x27cd ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_info 0x00008a47 0x6a8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_abbrev 0x00000000 0x18df + .debug_abbrev 0x00000000 0x2e0 ./Core/Src/main.o + .debug_abbrev 0x000002e0 0x1d9 ./Core/Src/stm32l1xx_hal_msp.o + .debug_abbrev 0x000004b9 0xa0 ./Core/Src/stm32l1xx_it.o + .debug_abbrev 0x00000559 0x11c ./Core/Src/system_stm32l1xx.o + .debug_abbrev 0x00000675 0x24 ./Core/Startup/startup_stm32l152retx.o + .debug_abbrev 0x00000699 0x1e9 ./Drivers/7Seg_MAX7219/max7219.o + .debug_abbrev 0x00000882 0x275 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_abbrev 0x00000af7 0x31c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_abbrev 0x00000e13 0x1d4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_abbrev 0x00000fe7 0x2b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_abbrev 0x0000129f 0x27a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_abbrev 0x00001519 0x25e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_abbrev 0x00001777 0x168 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_aranges 0x00000000 0xab0 + .debug_aranges + 0x00000000 0x80 ./Core/Src/main.o + .debug_aranges + 0x00000080 0x48 ./Core/Src/stm32l1xx_hal_msp.o + .debug_aranges + 0x000000c8 0x68 ./Core/Src/stm32l1xx_it.o + .debug_aranges + 0x00000130 0x28 ./Core/Src/system_stm32l1xx.o + .debug_aranges + 0x00000158 0x28 ./Core/Startup/startup_stm32l152retx.o + .debug_aranges + 0x00000180 0x78 ./Drivers/7Seg_MAX7219/max7219.o + .debug_aranges + 0x000001f8 0xe0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_aranges + 0x000002d8 0x128 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_aranges + 0x00000400 0x58 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_aranges + 0x00000458 0x90 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_aranges + 0x000004e8 0x1d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_aranges + 0x000006b8 0x3d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_aranges + 0x00000a88 0x28 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_rnglists + 0x00000000 0x81a + .debug_rnglists + 0x00000000 0x5f ./Core/Src/main.o + .debug_rnglists + 0x0000005f 0x32 ./Core/Src/stm32l1xx_hal_msp.o + .debug_rnglists + 0x00000091 0x49 ./Core/Src/stm32l1xx_it.o + .debug_rnglists + 0x000000da 0x1a ./Core/Src/system_stm32l1xx.o + .debug_rnglists + 0x000000f4 0x19 ./Core/Startup/startup_stm32l152retx.o + .debug_rnglists + 0x0000010d 0x55 ./Drivers/7Seg_MAX7219/max7219.o + .debug_rnglists + 0x00000162 0xa3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_rnglists + 0x00000205 0xd9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_rnglists + 0x000002de 0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_rnglists + 0x0000031d 0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_rnglists + 0x0000038a 0x16f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_rnglists + 0x000004f9 0x307 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + .debug_rnglists + 0x00000800 0x1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o + +.debug_macro 0x00000000 0x155f9 + .debug_macro 0x00000000 0x1c2 ./Core/Src/main.o + .debug_macro 0x000001c2 0xacc ./Core/Src/main.o + .debug_macro 0x00000c8e 0x10f ./Core/Src/main.o + .debug_macro 0x00000d9d 0x2e ./Core/Src/main.o + .debug_macro 0x00000dcb 0x22 ./Core/Src/main.o + .debug_macro 0x00000ded 0x22 ./Core/Src/main.o + .debug_macro 0x00000e0f 0x8e ./Core/Src/main.o + .debug_macro 0x00000e9d 0x51 ./Core/Src/main.o + .debug_macro 0x00000eee 0x103 ./Core/Src/main.o + .debug_macro 0x00000ff1 0x6a ./Core/Src/main.o + .debug_macro 0x0000105b 0x1df ./Core/Src/main.o + .debug_macro 0x0000123a 0x1c ./Core/Src/main.o + .debug_macro 0x00001256 0x22 ./Core/Src/main.o + .debug_macro 0x00001278 0xbd ./Core/Src/main.o + .debug_macro 0x00001335 0xe49 ./Core/Src/main.o + .debug_macro 0x0000217e 0x11f ./Core/Src/main.o + .debug_macro 0x0000229d 0xb7a1 ./Core/Src/main.o + .debug_macro 0x0000da3e 0x6d ./Core/Src/main.o + .debug_macro 0x0000daab 0x34e1 ./Core/Src/main.o + .debug_macro 0x00010f8c 0x190 ./Core/Src/main.o + .debug_macro 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file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00002850 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000964 0800298c 0800298c 0000398c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 080032f0 080032f0 0000505c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 080032f0 080032f0 000042f0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 080032f8 080032f8 0000505c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 080032f8 080032f8 000042f8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 080032fc 080032fc 000042fc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000005c 20000000 08003300 00005000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000001b0 2000005c 0800335c 0000505c 2**2 + ALLOC + 10 ._user_heap_stack 00000604 2000020c 0800335c 0000520c 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 0000505c 2**0 + CONTENTS, READONLY + 12 .debug_info 0000629e 00000000 00000000 00005085 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 000016c7 00000000 00000000 0000b323 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 000006d8 00000000 00000000 0000c9f0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 00000512 00000000 00000000 0000d0c8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000155d9 00000000 00000000 0000d5da 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 00007c47 00000000 00000000 00022bb3 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 00084a13 00000000 00000000 0002a7fa 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000af20d 2**0 + CONTENTS, READONLY + 20 .debug_frame 00001c78 00000000 00000000 000af250 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000b0ec8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 2000005c .word 0x2000005c + 8000158: 00000000 .word 0x00000000 + 800015c: 08002974 .word 0x08002974 + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000060 .word 0x20000060 + 8000178: 08002974 .word 0x08002974 + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0 : + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void affiche_nombre(char nombre[], uint8_t col, uint8_t ligne) { + 80004b0: b580 push {r7, lr} + 80004b2: b086 sub sp, #24 + 80004b4: af02 add r7, sp, #8 + 80004b6: 6078 str r0, [r7, #4] + 80004b8: 460b mov r3, r1 + 80004ba: 70fb strb r3, [r7, #3] + 80004bc: 4613 mov r3, r2 + 80004be: 70bb strb r3, [r7, #2] + int nombre_int = atoi(nombre); + 80004c0: 6878 ldr r0, [r7, #4] + 80004c2: f002 f99d bl 8002800 + 80004c6: 60f8 str r0, [r7, #12] + + if (nombre_int < 0 || nombre_int > 9999) { + 80004c8: 68fb ldr r3, [r7, #12] + 80004ca: 2b00 cmp r3, #0 + 80004cc: f2c0 8087 blt.w 80005de + 80004d0: 68fb ldr r3, [r7, #12] + 80004d2: f242 720f movw r2, #9999 @ 0x270f + 80004d6: 4293 cmp r3, r2 + 80004d8: f300 8081 bgt.w 80005de + return; + } + + uint8_t mil = nombre_int / 1000; + 80004dc: 68fb ldr r3, [r7, #12] + 80004de: 4a42 ldr r2, [pc, #264] @ (80005e8 ) + 80004e0: fb82 1203 smull r1, r2, r2, r3 + 80004e4: 1192 asrs r2, r2, #6 + 80004e6: 17db asrs r3, r3, #31 + 80004e8: 1ad3 subs r3, r2, r3 + 80004ea: 72fb strb r3, [r7, #11] + uint8_t cen = (nombre_int / 100) % 10; + 80004ec: 68fb ldr r3, [r7, #12] + 80004ee: 4a3f ldr r2, [pc, #252] @ (80005ec ) + 80004f0: fb82 1203 smull r1, r2, r2, r3 + 80004f4: 1152 asrs r2, r2, #5 + 80004f6: 17db asrs r3, r3, #31 + 80004f8: 1ad2 subs r2, r2, r3 + 80004fa: 4b3d ldr r3, [pc, #244] @ (80005f0 ) + 80004fc: fb83 1302 smull r1, r3, r3, r2 + 8000500: 1099 asrs r1, r3, #2 + 8000502: 17d3 asrs r3, r2, #31 + 8000504: 1ac9 subs r1, r1, r3 + 8000506: 460b mov r3, r1 + 8000508: 009b lsls r3, r3, #2 + 800050a: 440b add r3, r1 + 800050c: 005b lsls r3, r3, #1 + 800050e: 1ad1 subs r1, r2, r3 + 8000510: 460b mov r3, r1 + 8000512: 72bb strb r3, [r7, #10] + uint8_t diz = (nombre_int / 10) % 10; + 8000514: 68fb ldr r3, [r7, #12] + 8000516: 4a36 ldr r2, [pc, #216] @ (80005f0 ) + 8000518: fb82 1203 smull r1, r2, r2, r3 + 800051c: 1092 asrs r2, r2, #2 + 800051e: 17db asrs r3, r3, #31 + 8000520: 1ad2 subs r2, r2, r3 + 8000522: 4b33 ldr r3, [pc, #204] @ (80005f0 ) + 8000524: fb83 1302 smull r1, r3, r3, r2 + 8000528: 1099 asrs r1, r3, #2 + 800052a: 17d3 asrs r3, r2, #31 + 800052c: 1ac9 subs r1, r1, r3 + 800052e: 460b mov r3, r1 + 8000530: 009b lsls r3, r3, #2 + 8000532: 440b add r3, r1 + 8000534: 005b lsls r3, r3, #1 + 8000536: 1ad1 subs r1, r2, r3 + 8000538: 460b mov r3, r1 + 800053a: 727b strb r3, [r7, #9] + uint8_t uni = nombre_int % 10; + 800053c: 68fa ldr r2, [r7, #12] + 800053e: 4b2c ldr r3, [pc, #176] @ (80005f0 ) + 8000540: fb83 1302 smull r1, r3, r3, r2 + 8000544: 1099 asrs r1, r3, #2 + 8000546: 17d3 asrs r3, r2, #31 + 8000548: 1ac9 subs r1, r1, r3 + 800054a: 460b mov r3, r1 + 800054c: 009b lsls r3, r3, #2 + 800054e: 440b add r3, r1 + 8000550: 005b lsls r3, r3, #1 + 8000552: 1ad1 subs r1, r2, r3 + 8000554: 460b mov r3, r1 + 8000556: 723b strb r3, [r7, #8] + + displayChar_TFT(col, ligne, mil + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); + 8000558: 78fb ldrb r3, [r7, #3] + 800055a: b298 uxth r0, r3 + 800055c: 78bb ldrb r3, [r7, #2] + 800055e: b299 uxth r1, r3 + 8000560: 7afb ldrb r3, [r7, #11] + 8000562: 3330 adds r3, #48 @ 0x30 + 8000564: b2da uxtb r2, r3 + 8000566: 2302 movs r3, #2 + 8000568: 9301 str r3, [sp, #4] + 800056a: 2300 movs r3, #0 + 800056c: 9300 str r3, [sp, #0] + 800056e: f64f 73e0 movw r3, #65504 @ 0xffe0 + 8000572: f001 ffc7 bl 8002504 + displayChar_TFT(col + 12, ligne, cen + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); + 8000576: 78fb ldrb r3, [r7, #3] + 8000578: b29b uxth r3, r3 + 800057a: 330c adds r3, #12 + 800057c: b298 uxth r0, r3 + 800057e: 78bb ldrb r3, [r7, #2] + 8000580: b299 uxth r1, r3 + 8000582: 7abb ldrb r3, [r7, #10] + 8000584: 3330 adds r3, #48 @ 0x30 + 8000586: b2da uxtb r2, r3 + 8000588: 2302 movs r3, #2 + 800058a: 9301 str r3, [sp, #4] + 800058c: 2300 movs r3, #0 + 800058e: 9300 str r3, [sp, #0] + 8000590: f64f 73e0 movw r3, #65504 @ 0xffe0 + 8000594: f001 ffb6 bl 8002504 + displayChar_TFT(col + 24, ligne, diz + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); + 8000598: 78fb ldrb r3, [r7, #3] + 800059a: b29b uxth r3, r3 + 800059c: 3318 adds r3, #24 + 800059e: b298 uxth r0, r3 + 80005a0: 78bb ldrb r3, [r7, #2] + 80005a2: b299 uxth r1, r3 + 80005a4: 7a7b ldrb r3, [r7, #9] + 80005a6: 3330 adds r3, #48 @ 0x30 + 80005a8: b2da uxtb r2, r3 + 80005aa: 2302 movs r3, #2 + 80005ac: 9301 str r3, [sp, #4] + 80005ae: 2300 movs r3, #0 + 80005b0: 9300 str r3, [sp, #0] + 80005b2: f64f 73e0 movw r3, #65504 @ 0xffe0 + 80005b6: f001 ffa5 bl 8002504 + displayChar_TFT(col + 36, ligne, uni + 0x30, ST7735_YELLOW, ST7735_BLACK, 2); + 80005ba: 78fb ldrb r3, [r7, #3] + 80005bc: b29b uxth r3, r3 + 80005be: 3324 adds r3, #36 @ 0x24 + 80005c0: b298 uxth r0, r3 + 80005c2: 78bb ldrb r3, [r7, #2] + 80005c4: b299 uxth r1, r3 + 80005c6: 7a3b ldrb r3, [r7, #8] + 80005c8: 3330 adds r3, #48 @ 0x30 + 80005ca: b2da uxtb r2, r3 + 80005cc: 2302 movs r3, #2 + 80005ce: 9301 str r3, [sp, #4] + 80005d0: 2300 movs r3, #0 + 80005d2: 9300 str r3, [sp, #0] + 80005d4: f64f 73e0 movw r3, #65504 @ 0xffe0 + 80005d8: f001 ff94 bl 8002504 + 80005dc: e000 b.n 80005e0 + return; + 80005de: bf00 nop +} + 80005e0: 3710 adds r7, #16 + 80005e2: 46bd mov sp, r7 + 80005e4: bd80 pop {r7, pc} + 80005e6: bf00 nop + 80005e8: 10624dd3 .word 0x10624dd3 + 80005ec: 51eb851f .word 0x51eb851f + 80005f0: 66666667 .word 0x66666667 + +080005f4
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80005f4: b580 push {r7, lr} + 80005f6: b082 sub sp, #8 + 80005f8: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80005fa: f000 fa75 bl 8000ae8 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80005fe: f000 f817 bl 8000630 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000602: f000 f891 bl 8000728 + MX_SPI1_Init(); + 8000606: f000 f859 bl 80006bc + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 800060a: f000 f9f0 bl 80009ee + init_TFT(); + 800060e: f001 fe6f bl 80022f0 + MAX7219_Clear(); + 8000612: f000 fa23 bl 8000a5c + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + char nombre[] = "4090"; + 8000616: 4b05 ldr r3, [pc, #20] @ (800062c ) + 8000618: 603b str r3, [r7, #0] + 800061a: 2300 movs r3, #0 + 800061c: 713b strb r3, [r7, #4] + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + affiche_nombre(nombre, 10, 80); + 800061e: 463b mov r3, r7 + 8000620: 2250 movs r2, #80 @ 0x50 + 8000622: 210a movs r1, #10 + 8000624: 4618 mov r0, r3 + 8000626: f7ff ff43 bl 80004b0 + 800062a: e7f8 b.n 800061e + 800062c: 30393034 .word 0x30393034 + +08000630 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000630: b580 push {r7, lr} + 8000632: b092 sub sp, #72 @ 0x48 + 8000634: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000636: f107 0314 add.w r3, r7, #20 + 800063a: 2234 movs r2, #52 @ 0x34 + 800063c: 2100 movs r1, #0 + 800063e: 4618 mov r0, r3 + 8000640: f002 f966 bl 8002910 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000644: 463b mov r3, r7 + 8000646: 2200 movs r2, #0 + 8000648: 601a str r2, [r3, #0] + 800064a: 605a str r2, [r3, #4] + 800064c: 609a str r2, [r3, #8] + 800064e: 60da str r2, [r3, #12] + 8000650: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000652: 4b19 ldr r3, [pc, #100] @ (80006b8 ) + 8000654: 681b ldr r3, [r3, #0] + 8000656: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 800065a: 4a17 ldr r2, [pc, #92] @ (80006b8 ) + 800065c: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000660: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000662: 2302 movs r3, #2 + 8000664: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000666: 2301 movs r3, #1 + 8000668: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 800066a: 2310 movs r3, #16 + 800066c: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 800066e: 2300 movs r3, #0 + 8000670: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000672: f107 0314 add.w r3, r7, #20 + 8000676: 4618 mov r0, r3 + 8000678: f000 fd52 bl 8001120 + 800067c: 4603 mov r3, r0 + 800067e: 2b00 cmp r3, #0 + 8000680: d001 beq.n 8000686 + { + Error_Handler(); + 8000682: f000 f8e5 bl 8000850 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000686: 230f movs r3, #15 + 8000688: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 800068a: 2301 movs r3, #1 + 800068c: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 800068e: 2300 movs r3, #0 + 8000690: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000692: 2300 movs r3, #0 + 8000694: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000696: 2300 movs r3, #0 + 8000698: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 800069a: 463b mov r3, r7 + 800069c: 2100 movs r1, #0 + 800069e: 4618 mov r0, r3 + 80006a0: f001 f86e bl 8001780 + 80006a4: 4603 mov r3, r0 + 80006a6: 2b00 cmp r3, #0 + 80006a8: d001 beq.n 80006ae + { + Error_Handler(); + 80006aa: f000 f8d1 bl 8000850 + } +} + 80006ae: bf00 nop + 80006b0: 3748 adds r7, #72 @ 0x48 + 80006b2: 46bd mov sp, r7 + 80006b4: bd80 pop {r7, pc} + 80006b6: bf00 nop + 80006b8: 40007000 .word 0x40007000 + +080006bc : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 80006bc: b580 push {r7, lr} + 80006be: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 80006c0: 4b17 ldr r3, [pc, #92] @ (8000720 ) + 80006c2: 4a18 ldr r2, [pc, #96] @ (8000724 ) + 80006c4: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 80006c6: 4b16 ldr r3, [pc, #88] @ (8000720 ) + 80006c8: f44f 7282 mov.w r2, #260 @ 0x104 + 80006cc: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 80006ce: 4b14 ldr r3, [pc, #80] @ (8000720 ) + 80006d0: 2200 movs r2, #0 + 80006d2: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 80006d4: 4b12 ldr r3, [pc, #72] @ (8000720 ) + 80006d6: 2200 movs r2, #0 + 80006d8: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 80006da: 4b11 ldr r3, [pc, #68] @ (8000720 ) + 80006dc: 2200 movs r2, #0 + 80006de: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 80006e0: 4b0f ldr r3, [pc, #60] @ (8000720 ) + 80006e2: 2200 movs r2, #0 + 80006e4: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 80006e6: 4b0e ldr r3, [pc, #56] @ (8000720 ) + 80006e8: f44f 7200 mov.w r2, #512 @ 0x200 + 80006ec: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 80006ee: 4b0c ldr r3, [pc, #48] @ (8000720 ) + 80006f0: 2200 movs r2, #0 + 80006f2: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 80006f4: 4b0a ldr r3, [pc, #40] @ (8000720 ) + 80006f6: 2200 movs r2, #0 + 80006f8: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 80006fa: 4b09 ldr r3, [pc, #36] @ (8000720 ) + 80006fc: 2200 movs r2, #0 + 80006fe: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8000700: 4b07 ldr r3, [pc, #28] @ (8000720 ) + 8000702: 2200 movs r2, #0 + 8000704: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 8000706: 4b06 ldr r3, [pc, #24] @ (8000720 ) + 8000708: 220a movs r2, #10 + 800070a: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 800070c: 4804 ldr r0, [pc, #16] @ (8000720 ) + 800070e: f001 fa89 bl 8001c24 + 8000712: 4603 mov r3, r0 + 8000714: 2b00 cmp r3, #0 + 8000716: d001 beq.n 800071c + { + Error_Handler(); + 8000718: f000 f89a bl 8000850 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 800071c: bf00 nop + 800071e: bd80 pop {r7, pc} + 8000720: 20000078 .word 0x20000078 + 8000724: 40013000 .word 0x40013000 + +08000728 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000728: b580 push {r7, lr} + 800072a: b08a sub sp, #40 @ 0x28 + 800072c: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800072e: f107 0314 add.w r3, r7, #20 + 8000732: 2200 movs r2, #0 + 8000734: 601a str r2, [r3, #0] + 8000736: 605a str r2, [r3, #4] + 8000738: 609a str r2, [r3, #8] + 800073a: 60da str r2, [r3, #12] + 800073c: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800073e: 4b40 ldr r3, [pc, #256] @ (8000840 ) + 8000740: 69db ldr r3, [r3, #28] + 8000742: 4a3f ldr r2, [pc, #252] @ (8000840 ) + 8000744: f043 0304 orr.w r3, r3, #4 + 8000748: 61d3 str r3, [r2, #28] + 800074a: 4b3d ldr r3, [pc, #244] @ (8000840 ) + 800074c: 69db ldr r3, [r3, #28] + 800074e: f003 0304 and.w r3, r3, #4 + 8000752: 613b str r3, [r7, #16] + 8000754: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000756: 4b3a ldr r3, [pc, #232] @ (8000840 ) + 8000758: 69db ldr r3, [r3, #28] + 800075a: 4a39 ldr r2, [pc, #228] @ (8000840 ) + 800075c: f043 0301 orr.w r3, r3, #1 + 8000760: 61d3 str r3, [r2, #28] + 8000762: 4b37 ldr r3, [pc, #220] @ (8000840 ) + 8000764: 69db ldr r3, [r3, #28] + 8000766: f003 0301 and.w r3, r3, #1 + 800076a: 60fb str r3, [r7, #12] + 800076c: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800076e: 4b34 ldr r3, [pc, #208] @ (8000840 ) + 8000770: 69db ldr r3, [r3, #28] + 8000772: 4a33 ldr r2, [pc, #204] @ (8000840 ) + 8000774: f043 0302 orr.w r3, r3, #2 + 8000778: 61d3 str r3, [r2, #28] + 800077a: 4b31 ldr r3, [pc, #196] @ (8000840 ) + 800077c: 69db ldr r3, [r3, #28] + 800077e: f003 0302 and.w r3, r3, #2 + 8000782: 60bb str r3, [r7, #8] + 8000784: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8000786: 4b2e ldr r3, [pc, #184] @ (8000840 ) + 8000788: 69db ldr r3, [r3, #28] + 800078a: 4a2d ldr r2, [pc, #180] @ (8000840 ) + 800078c: f043 0308 orr.w r3, r3, #8 + 8000790: 61d3 str r3, [r2, #28] + 8000792: 4b2b ldr r3, [pc, #172] @ (8000840 ) + 8000794: 69db ldr r3, [r3, #28] + 8000796: f003 0308 and.w r3, r3, #8 + 800079a: 607b str r3, [r7, #4] + 800079c: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 800079e: 2200 movs r2, #0 + 80007a0: 2101 movs r1, #1 + 80007a2: 4828 ldr r0, [pc, #160] @ (8000844 ) + 80007a4: f000 fca4 bl 80010f0 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_SET); + 80007a8: 2201 movs r2, #1 + 80007aa: 210e movs r1, #14 + 80007ac: 4825 ldr r0, [pc, #148] @ (8000844 ) + 80007ae: f000 fc9f bl 80010f0 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET); + 80007b2: 2201 movs r2, #1 + 80007b4: 2104 movs r1, #4 + 80007b6: 4824 ldr r0, [pc, #144] @ (8000848 ) + 80007b8: f000 fc9a bl 80010f0 + + /*Configure GPIO pins : PC0 PC1 PC2 PC3 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; + 80007bc: 230f movs r3, #15 + 80007be: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80007c0: 2301 movs r3, #1 + 80007c2: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007c4: 2300 movs r3, #0 + 80007c6: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80007c8: 2300 movs r3, #0 + 80007ca: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80007cc: f107 0314 add.w r3, r7, #20 + 80007d0: 4619 mov r1, r3 + 80007d2: 481c ldr r0, [pc, #112] @ (8000844 ) + 80007d4: f000 fafc bl 8000dd0 + + /*Configure GPIO pin : PB15 */ + GPIO_InitStruct.Pin = GPIO_PIN_15; + 80007d8: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80007dc: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80007de: 2302 movs r3, #2 + 80007e0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007e2: 2300 movs r3, #0 + 80007e4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80007e6: 2300 movs r3, #0 + 80007e8: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + 80007ea: 2303 movs r3, #3 + 80007ec: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80007ee: f107 0314 add.w r3, r7, #20 + 80007f2: 4619 mov r1, r3 + 80007f4: 4815 ldr r0, [pc, #84] @ (800084c ) + 80007f6: f000 faeb bl 8000dd0 + + /*Configure GPIO pin : PD2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + 80007fa: 2304 movs r3, #4 + 80007fc: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80007fe: 2301 movs r3, #1 + 8000800: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000802: 2300 movs r3, #0 + 8000804: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000806: 2300 movs r3, #0 + 8000808: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 800080a: f107 0314 add.w r3, r7, #20 + 800080e: 4619 mov r1, r3 + 8000810: 480d ldr r0, [pc, #52] @ (8000848 ) + 8000812: f000 fadd bl 8000dd0 + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + 8000816: 2380 movs r3, #128 @ 0x80 + 8000818: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800081a: 2302 movs r3, #2 + 800081c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800081e: 2300 movs r3, #0 + 8000820: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000822: 2300 movs r3, #0 + 8000824: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 8000826: 2302 movs r3, #2 + 8000828: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800082a: f107 0314 add.w r3, r7, #20 + 800082e: 4619 mov r1, r3 + 8000830: 4806 ldr r0, [pc, #24] @ (800084c ) + 8000832: f000 facd bl 8000dd0 + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 8000836: bf00 nop + 8000838: 3728 adds r7, #40 @ 0x28 + 800083a: 46bd mov sp, r7 + 800083c: bd80 pop {r7, pc} + 800083e: bf00 nop + 8000840: 40023800 .word 0x40023800 + 8000844: 40020800 .word 0x40020800 + 8000848: 40020c00 .word 0x40020c00 + 800084c: 40020400 .word 0x40020400 + +08000850 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000850: b480 push {r7} + 8000852: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000854: b672 cpsid i +} + 8000856: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000858: bf00 nop + 800085a: e7fd b.n 8000858 + +0800085c : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 800085c: b480 push {r7} + 800085e: b085 sub sp, #20 + 8000860: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 8000862: 4b14 ldr r3, [pc, #80] @ (80008b4 ) + 8000864: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000866: 4a13 ldr r2, [pc, #76] @ (80008b4 ) + 8000868: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 800086c: 6253 str r3, [r2, #36] @ 0x24 + 800086e: 4b11 ldr r3, [pc, #68] @ (80008b4 ) + 8000870: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000872: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 8000876: 60fb str r3, [r7, #12] + 8000878: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800087a: 4b0e ldr r3, [pc, #56] @ (80008b4 ) + 800087c: 6a1b ldr r3, [r3, #32] + 800087e: 4a0d ldr r2, [pc, #52] @ (80008b4 ) + 8000880: f043 0301 orr.w r3, r3, #1 + 8000884: 6213 str r3, [r2, #32] + 8000886: 4b0b ldr r3, [pc, #44] @ (80008b4 ) + 8000888: 6a1b ldr r3, [r3, #32] + 800088a: f003 0301 and.w r3, r3, #1 + 800088e: 60bb str r3, [r7, #8] + 8000890: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 8000892: 4b08 ldr r3, [pc, #32] @ (80008b4 ) + 8000894: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000896: 4a07 ldr r2, [pc, #28] @ (80008b4 ) + 8000898: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800089c: 6253 str r3, [r2, #36] @ 0x24 + 800089e: 4b05 ldr r3, [pc, #20] @ (80008b4 ) + 80008a0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80008a2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80008a6: 607b str r3, [r7, #4] + 80008a8: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 80008aa: bf00 nop + 80008ac: 3714 adds r7, #20 + 80008ae: 46bd mov sp, r7 + 80008b0: bc80 pop {r7} + 80008b2: 4770 bx lr + 80008b4: 40023800 .word 0x40023800 + +080008b8 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 80008b8: b580 push {r7, lr} + 80008ba: b08a sub sp, #40 @ 0x28 + 80008bc: af00 add r7, sp, #0 + 80008be: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80008c0: f107 0314 add.w r3, r7, #20 + 80008c4: 2200 movs r2, #0 + 80008c6: 601a str r2, [r3, #0] + 80008c8: 605a str r2, [r3, #4] + 80008ca: 609a str r2, [r3, #8] + 80008cc: 60da str r2, [r3, #12] + 80008ce: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 80008d0: 687b ldr r3, [r7, #4] + 80008d2: 681b ldr r3, [r3, #0] + 80008d4: 4a17 ldr r2, [pc, #92] @ (8000934 ) + 80008d6: 4293 cmp r3, r2 + 80008d8: d127 bne.n 800092a + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 80008da: 4b17 ldr r3, [pc, #92] @ (8000938 ) + 80008dc: 6a1b ldr r3, [r3, #32] + 80008de: 4a16 ldr r2, [pc, #88] @ (8000938 ) + 80008e0: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 80008e4: 6213 str r3, [r2, #32] + 80008e6: 4b14 ldr r3, [pc, #80] @ (8000938 ) + 80008e8: 6a1b ldr r3, [r3, #32] + 80008ea: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80008ee: 613b str r3, [r7, #16] + 80008f0: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80008f2: 4b11 ldr r3, [pc, #68] @ (8000938 ) + 80008f4: 69db ldr r3, [r3, #28] + 80008f6: 4a10 ldr r2, [pc, #64] @ (8000938 ) + 80008f8: f043 0301 orr.w r3, r3, #1 + 80008fc: 61d3 str r3, [r2, #28] + 80008fe: 4b0e ldr r3, [pc, #56] @ (8000938 ) + 8000900: 69db ldr r3, [r3, #28] + 8000902: f003 0301 and.w r3, r3, #1 + 8000906: 60fb str r3, [r7, #12] + 8000908: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 800090a: 23e0 movs r3, #224 @ 0xe0 + 800090c: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800090e: 2302 movs r3, #2 + 8000910: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000912: 2300 movs r3, #0 + 8000914: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8000916: 2303 movs r3, #3 + 8000918: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 800091a: 2305 movs r3, #5 + 800091c: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800091e: f107 0314 add.w r3, r7, #20 + 8000922: 4619 mov r1, r3 + 8000924: 4805 ldr r0, [pc, #20] @ (800093c ) + 8000926: f000 fa53 bl 8000dd0 + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 800092a: bf00 nop + 800092c: 3728 adds r7, #40 @ 0x28 + 800092e: 46bd mov sp, r7 + 8000930: bd80 pop {r7, pc} + 8000932: bf00 nop + 8000934: 40013000 .word 0x40013000 + 8000938: 40023800 .word 0x40023800 + 800093c: 40020000 .word 0x40020000 + +08000940 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000940: b480 push {r7} + 8000942: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000944: bf00 nop + 8000946: e7fd b.n 8000944 + +08000948 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000948: b480 push {r7} + 800094a: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 800094c: bf00 nop + 800094e: e7fd b.n 800094c + +08000950 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000950: b480 push {r7} + 8000952: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000954: bf00 nop + 8000956: e7fd b.n 8000954 + +08000958 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000958: b480 push {r7} + 800095a: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 800095c: bf00 nop + 800095e: e7fd b.n 800095c + +08000960 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000960: b480 push {r7} + 8000962: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000964: bf00 nop + 8000966: e7fd b.n 8000964 + +08000968 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000968: b480 push {r7} + 800096a: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 800096c: bf00 nop + 800096e: 46bd mov sp, r7 + 8000970: bc80 pop {r7} + 8000972: 4770 bx lr + +08000974 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000974: b480 push {r7} + 8000976: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000978: bf00 nop + 800097a: 46bd mov sp, r7 + 800097c: bc80 pop {r7} + 800097e: 4770 bx lr + +08000980 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000980: b480 push {r7} + 8000982: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000984: bf00 nop + 8000986: 46bd mov sp, r7 + 8000988: bc80 pop {r7} + 800098a: 4770 bx lr + +0800098c : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800098c: b580 push {r7, lr} + 800098e: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000990: f000 f8fc bl 8000b8c + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000994: bf00 nop + 8000996: bd80 pop {r7, pc} + +08000998 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000998: b480 push {r7} + 800099a: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 800099c: bf00 nop + 800099e: 46bd mov sp, r7 + 80009a0: bc80 pop {r7} + 80009a2: 4770 bx lr + +080009a4 : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 80009a4: f7ff fff8 bl 8000998 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 80009a8: 480b ldr r0, [pc, #44] @ (80009d8 ) + ldr r1, =_edata + 80009aa: 490c ldr r1, [pc, #48] @ (80009dc ) + ldr r2, =_sidata + 80009ac: 4a0c ldr r2, [pc, #48] @ (80009e0 ) + movs r3, #0 + 80009ae: 2300 movs r3, #0 + b LoopCopyDataInit + 80009b0: e002 b.n 80009b8 + +080009b2 : + +CopyDataInit: + ldr r4, [r2, r3] + 80009b2: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 80009b4: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 80009b6: 3304 adds r3, #4 + +080009b8 : + +LoopCopyDataInit: + adds r4, r0, r3 + 80009b8: 18c4 adds r4, r0, r3 + cmp r4, r1 + 80009ba: 428c cmp r4, r1 + bcc CopyDataInit + 80009bc: d3f9 bcc.n 80009b2 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 80009be: 4a09 ldr r2, [pc, #36] @ (80009e4 ) + ldr r4, =_ebss + 80009c0: 4c09 ldr r4, [pc, #36] @ (80009e8 ) + movs r3, #0 + 80009c2: 2300 movs r3, #0 + b LoopFillZerobss + 80009c4: e001 b.n 80009ca + +080009c6 : + +FillZerobss: + str r3, [r2] + 80009c6: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 80009c8: 3204 adds r2, #4 + +080009ca : + +LoopFillZerobss: + cmp r2, r4 + 80009ca: 42a2 cmp r2, r4 + bcc FillZerobss + 80009cc: d3fb bcc.n 80009c6 + +/* Call static constructors */ + bl __libc_init_array + 80009ce: f001 ffad bl 800292c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 80009d2: f7ff fe0f bl 80005f4
+ bx lr + 80009d6: 4770 bx lr + ldr r0, =_sdata + 80009d8: 20000000 .word 0x20000000 + ldr r1, =_edata + 80009dc: 2000005c .word 0x2000005c + ldr r2, =_sidata + 80009e0: 08003300 .word 0x08003300 + ldr r2, =_sbss + 80009e4: 2000005c .word 0x2000005c + ldr r4, =_ebss + 80009e8: 2000020c .word 0x2000020c + +080009ec : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80009ec: e7fe b.n 80009ec + +080009ee : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 80009ee: b580 push {r7, lr} + 80009f0: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 80009f2: 2107 movs r1, #7 + 80009f4: 200b movs r0, #11 + 80009f6: f000 f847 bl 8000a88 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 80009fa: 2100 movs r1, #0 + 80009fc: 2009 movs r0, #9 + 80009fe: f000 f843 bl 8000a88 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 8000a02: f000 f809 bl 8000a18 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 8000a06: f000 f80f bl 8000a28 + MAX7219_Clear(); // clear all digits + 8000a0a: f000 f827 bl 8000a5c + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 8000a0e: 200f movs r0, #15 + 8000a10: f000 f812 bl 8000a38 +} + 8000a14: bf00 nop + 8000a16: bd80 pop {r7, pc} + +08000a18 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000a18: b580 push {r7, lr} + 8000a1a: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000a1c: 2101 movs r1, #1 + 8000a1e: 200c movs r0, #12 + 8000a20: f000 f832 bl 8000a88 +} + 8000a24: bf00 nop + 8000a26: bd80 pop {r7, pc} + +08000a28 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 8000a28: b580 push {r7, lr} + 8000a2a: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 8000a2c: 2100 movs r1, #0 + 8000a2e: 200f movs r0, #15 + 8000a30: f000 f82a bl 8000a88 +} + 8000a34: bf00 nop + 8000a36: bd80 pop {r7, pc} + +08000a38 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 8000a38: b580 push {r7, lr} + 8000a3a: b082 sub sp, #8 + 8000a3c: af00 add r7, sp, #0 + 8000a3e: 4603 mov r3, r0 + 8000a40: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 8000a42: 79fb ldrb r3, [r7, #7] + 8000a44: f003 030f and.w r3, r3, #15 + 8000a48: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 8000a4a: 79fb ldrb r3, [r7, #7] + 8000a4c: 4619 mov r1, r3 + 8000a4e: 200a movs r0, #10 + 8000a50: f000 f81a bl 8000a88 +} + 8000a54: bf00 nop + 8000a56: 3708 adds r7, #8 + 8000a58: 46bd mov sp, r7 + 8000a5a: bd80 pop {r7, pc} + +08000a5c : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 8000a5c: b580 push {r7, lr} + 8000a5e: b082 sub sp, #8 + 8000a60: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 8000a62: 2300 movs r3, #0 + 8000a64: 71fb strb r3, [r7, #7] + 8000a66: e007 b.n 8000a78 + MAX7219_Write(i, 0x00); // turn all segments off + 8000a68: 79fb ldrb r3, [r7, #7] + 8000a6a: 2100 movs r1, #0 + 8000a6c: 4618 mov r0, r3 + 8000a6e: f000 f80b bl 8000a88 + for (i=0; i < 8; i++) + 8000a72: 79fb ldrb r3, [r7, #7] + 8000a74: 3301 adds r3, #1 + 8000a76: 71fb strb r3, [r7, #7] + 8000a78: 79fb ldrb r3, [r7, #7] + 8000a7a: 2b07 cmp r3, #7 + 8000a7c: d9f4 bls.n 8000a68 +} + 8000a7e: bf00 nop + 8000a80: bf00 nop + 8000a82: 3708 adds r7, #8 + 8000a84: 46bd mov sp, r7 + 8000a86: bd80 pop {r7, pc} + +08000a88 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8000a88: b580 push {r7, lr} + 8000a8a: b082 sub sp, #8 + 8000a8c: af00 add r7, sp, #0 + 8000a8e: 4603 mov r3, r0 + 8000a90: 460a mov r2, r1 + 8000a92: 71fb strb r3, [r7, #7] + 8000a94: 4613 mov r3, r2 + 8000a96: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8000a98: 4b09 ldr r3, [pc, #36] @ (8000ac0 ) + 8000a9a: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000a9e: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8000aa0: 79fb ldrb r3, [r7, #7] + 8000aa2: 4618 mov r0, r3 + 8000aa4: f000 f80e bl 8000ac4 + MAX7219_SendByte(dataout); // write data to MAX7219 + 8000aa8: 79bb ldrb r3, [r7, #6] + 8000aaa: 4618 mov r0, r3 + 8000aac: f000 f80a bl 8000ac4 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 8000ab0: 4b03 ldr r3, [pc, #12] @ (8000ac0 ) + 8000ab2: 2201 movs r2, #1 + 8000ab4: 619a str r2, [r3, #24] + } + 8000ab6: bf00 nop + 8000ab8: 3708 adds r7, #8 + 8000aba: 46bd mov sp, r7 + 8000abc: bd80 pop {r7, pc} + 8000abe: bf00 nop + 8000ac0: 40020800 .word 0x40020800 + +08000ac4 : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000ac4: b580 push {r7, lr} + 8000ac6: b082 sub sp, #8 + 8000ac8: af00 add r7, sp, #0 + 8000aca: 4603 mov r3, r0 + 8000acc: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 8000ace: 1df9 adds r1, r7, #7 + 8000ad0: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000ad4: 2201 movs r2, #1 + 8000ad6: 4803 ldr r0, [pc, #12] @ (8000ae4 ) + 8000ad8: f001 f92d bl 8001d36 + +} + 8000adc: bf00 nop + 8000ade: 3708 adds r7, #8 + 8000ae0: 46bd mov sp, r7 + 8000ae2: bd80 pop {r7, pc} + 8000ae4: 20000078 .word 0x20000078 + +08000ae8 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000ae8: b580 push {r7, lr} + 8000aea: b082 sub sp, #8 + 8000aec: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000aee: 2300 movs r3, #0 + 8000af0: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000af2: 2003 movs r0, #3 + 8000af4: f000 f938 bl 8000d68 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000af8: 200f movs r0, #15 + 8000afa: f000 f80d bl 8000b18 + 8000afe: 4603 mov r3, r0 + 8000b00: 2b00 cmp r3, #0 + 8000b02: d002 beq.n 8000b0a + { + status = HAL_ERROR; + 8000b04: 2301 movs r3, #1 + 8000b06: 71fb strb r3, [r7, #7] + 8000b08: e001 b.n 8000b0e + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000b0a: f7ff fea7 bl 800085c + } + + /* Return function status */ + return status; + 8000b0e: 79fb ldrb r3, [r7, #7] +} + 8000b10: 4618 mov r0, r3 + 8000b12: 3708 adds r7, #8 + 8000b14: 46bd mov sp, r7 + 8000b16: bd80 pop {r7, pc} + +08000b18 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000b18: b580 push {r7, lr} + 8000b1a: b084 sub sp, #16 + 8000b1c: af00 add r7, sp, #0 + 8000b1e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000b20: 2300 movs r3, #0 + 8000b22: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 8000b24: 4b16 ldr r3, [pc, #88] @ (8000b80 ) + 8000b26: 681b ldr r3, [r3, #0] + 8000b28: 2b00 cmp r3, #0 + 8000b2a: d022 beq.n 8000b72 + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 8000b2c: 4b15 ldr r3, [pc, #84] @ (8000b84 ) + 8000b2e: 681a ldr r2, [r3, #0] + 8000b30: 4b13 ldr r3, [pc, #76] @ (8000b80 ) + 8000b32: 681b ldr r3, [r3, #0] + 8000b34: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8000b38: fbb1 f3f3 udiv r3, r1, r3 + 8000b3c: fbb2 f3f3 udiv r3, r2, r3 + 8000b40: 4618 mov r0, r3 + 8000b42: f000 f938 bl 8000db6 + 8000b46: 4603 mov r3, r0 + 8000b48: 2b00 cmp r3, #0 + 8000b4a: d10f bne.n 8000b6c + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000b4c: 687b ldr r3, [r7, #4] + 8000b4e: 2b0f cmp r3, #15 + 8000b50: d809 bhi.n 8000b66 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000b52: 2200 movs r2, #0 + 8000b54: 6879 ldr r1, [r7, #4] + 8000b56: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000b5a: f000 f910 bl 8000d7e + uwTickPrio = TickPriority; + 8000b5e: 4a0a ldr r2, [pc, #40] @ (8000b88 ) + 8000b60: 687b ldr r3, [r7, #4] + 8000b62: 6013 str r3, [r2, #0] + 8000b64: e007 b.n 8000b76 + } + else + { + status = HAL_ERROR; + 8000b66: 2301 movs r3, #1 + 8000b68: 73fb strb r3, [r7, #15] + 8000b6a: e004 b.n 8000b76 + } + } + else + { + status = HAL_ERROR; + 8000b6c: 2301 movs r3, #1 + 8000b6e: 73fb strb r3, [r7, #15] + 8000b70: e001 b.n 8000b76 + } + } + else + { + status = HAL_ERROR; + 8000b72: 2301 movs r3, #1 + 8000b74: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8000b76: 7bfb ldrb r3, [r7, #15] +} + 8000b78: 4618 mov r0, r3 + 8000b7a: 3710 adds r7, #16 + 8000b7c: 46bd mov sp, r7 + 8000b7e: bd80 pop {r7, pc} + 8000b80: 20000008 .word 0x20000008 + 8000b84: 20000000 .word 0x20000000 + 8000b88: 20000004 .word 0x20000004 + +08000b8c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000b8c: b480 push {r7} + 8000b8e: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000b90: 4b05 ldr r3, [pc, #20] @ (8000ba8 ) + 8000b92: 681a ldr r2, [r3, #0] + 8000b94: 4b05 ldr r3, [pc, #20] @ (8000bac ) + 8000b96: 681b ldr r3, [r3, #0] + 8000b98: 4413 add r3, r2 + 8000b9a: 4a03 ldr r2, [pc, #12] @ (8000ba8 ) + 8000b9c: 6013 str r3, [r2, #0] +} + 8000b9e: bf00 nop + 8000ba0: 46bd mov sp, r7 + 8000ba2: bc80 pop {r7} + 8000ba4: 4770 bx lr + 8000ba6: bf00 nop + 8000ba8: 200000d0 .word 0x200000d0 + 8000bac: 20000008 .word 0x20000008 + +08000bb0 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000bb0: b480 push {r7} + 8000bb2: af00 add r7, sp, #0 + return uwTick; + 8000bb4: 4b02 ldr r3, [pc, #8] @ (8000bc0 ) + 8000bb6: 681b ldr r3, [r3, #0] +} + 8000bb8: 4618 mov r0, r3 + 8000bba: 46bd mov sp, r7 + 8000bbc: bc80 pop {r7} + 8000bbe: 4770 bx lr + 8000bc0: 200000d0 .word 0x200000d0 + +08000bc4 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000bc4: b580 push {r7, lr} + 8000bc6: b084 sub sp, #16 + 8000bc8: af00 add r7, sp, #0 + 8000bca: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8000bcc: f7ff fff0 bl 8000bb0 + 8000bd0: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8000bd2: 687b ldr r3, [r7, #4] + 8000bd4: 60fb str r3, [r7, #12] + + /* Add a period to guaranty minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000bd6: 68fb ldr r3, [r7, #12] + 8000bd8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8000bdc: d004 beq.n 8000be8 + { + wait += (uint32_t)(uwTickFreq); + 8000bde: 4b09 ldr r3, [pc, #36] @ (8000c04 ) + 8000be0: 681b ldr r3, [r3, #0] + 8000be2: 68fa ldr r2, [r7, #12] + 8000be4: 4413 add r3, r2 + 8000be6: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 8000be8: bf00 nop + 8000bea: f7ff ffe1 bl 8000bb0 + 8000bee: 4602 mov r2, r0 + 8000bf0: 68bb ldr r3, [r7, #8] + 8000bf2: 1ad3 subs r3, r2, r3 + 8000bf4: 68fa ldr r2, [r7, #12] + 8000bf6: 429a cmp r2, r3 + 8000bf8: d8f7 bhi.n 8000bea + { + } +} + 8000bfa: bf00 nop + 8000bfc: bf00 nop + 8000bfe: 3710 adds r7, #16 + 8000c00: 46bd mov sp, r7 + 8000c02: bd80 pop {r7, pc} + 8000c04: 20000008 .word 0x20000008 + +08000c08 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000c08: b480 push {r7} + 8000c0a: b085 sub sp, #20 + 8000c0c: af00 add r7, sp, #0 + 8000c0e: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000c10: 687b ldr r3, [r7, #4] + 8000c12: f003 0307 and.w r3, r3, #7 + 8000c16: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000c18: 4b0c ldr r3, [pc, #48] @ (8000c4c <__NVIC_SetPriorityGrouping+0x44>) + 8000c1a: 68db ldr r3, [r3, #12] + 8000c1c: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000c1e: 68ba ldr r2, [r7, #8] + 8000c20: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000c24: 4013 ands r3, r2 + 8000c26: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000c28: 68fb ldr r3, [r7, #12] + 8000c2a: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000c2c: 68bb ldr r3, [r7, #8] + 8000c2e: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000c30: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000c34: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000c38: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000c3a: 4a04 ldr r2, [pc, #16] @ (8000c4c <__NVIC_SetPriorityGrouping+0x44>) + 8000c3c: 68bb ldr r3, [r7, #8] + 8000c3e: 60d3 str r3, [r2, #12] +} + 8000c40: bf00 nop + 8000c42: 3714 adds r7, #20 + 8000c44: 46bd mov sp, r7 + 8000c46: bc80 pop {r7} + 8000c48: 4770 bx lr + 8000c4a: bf00 nop + 8000c4c: e000ed00 .word 0xe000ed00 + +08000c50 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000c50: b480 push {r7} + 8000c52: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000c54: 4b04 ldr r3, [pc, #16] @ (8000c68 <__NVIC_GetPriorityGrouping+0x18>) + 8000c56: 68db ldr r3, [r3, #12] + 8000c58: 0a1b lsrs r3, r3, #8 + 8000c5a: f003 0307 and.w r3, r3, #7 +} + 8000c5e: 4618 mov r0, r3 + 8000c60: 46bd mov sp, r7 + 8000c62: bc80 pop {r7} + 8000c64: 4770 bx lr + 8000c66: bf00 nop + 8000c68: e000ed00 .word 0xe000ed00 + +08000c6c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000c6c: b480 push {r7} + 8000c6e: b083 sub sp, #12 + 8000c70: af00 add r7, sp, #0 + 8000c72: 4603 mov r3, r0 + 8000c74: 6039 str r1, [r7, #0] + 8000c76: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000c78: f997 3007 ldrsb.w r3, [r7, #7] + 8000c7c: 2b00 cmp r3, #0 + 8000c7e: db0a blt.n 8000c96 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000c80: 683b ldr r3, [r7, #0] + 8000c82: b2da uxtb r2, r3 + 8000c84: 490c ldr r1, [pc, #48] @ (8000cb8 <__NVIC_SetPriority+0x4c>) + 8000c86: f997 3007 ldrsb.w r3, [r7, #7] + 8000c8a: 0112 lsls r2, r2, #4 + 8000c8c: b2d2 uxtb r2, r2 + 8000c8e: 440b add r3, r1 + 8000c90: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000c94: e00a b.n 8000cac <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000c96: 683b ldr r3, [r7, #0] + 8000c98: b2da uxtb r2, r3 + 8000c9a: 4908 ldr r1, [pc, #32] @ (8000cbc <__NVIC_SetPriority+0x50>) + 8000c9c: 79fb ldrb r3, [r7, #7] + 8000c9e: f003 030f and.w r3, r3, #15 + 8000ca2: 3b04 subs r3, #4 + 8000ca4: 0112 lsls r2, r2, #4 + 8000ca6: b2d2 uxtb r2, r2 + 8000ca8: 440b add r3, r1 + 8000caa: 761a strb r2, [r3, #24] +} + 8000cac: bf00 nop + 8000cae: 370c adds r7, #12 + 8000cb0: 46bd mov sp, r7 + 8000cb2: bc80 pop {r7} + 8000cb4: 4770 bx lr + 8000cb6: bf00 nop + 8000cb8: e000e100 .word 0xe000e100 + 8000cbc: e000ed00 .word 0xe000ed00 + +08000cc0 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000cc0: b480 push {r7} + 8000cc2: b089 sub sp, #36 @ 0x24 + 8000cc4: af00 add r7, sp, #0 + 8000cc6: 60f8 str r0, [r7, #12] + 8000cc8: 60b9 str r1, [r7, #8] + 8000cca: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000ccc: 68fb ldr r3, [r7, #12] + 8000cce: f003 0307 and.w r3, r3, #7 + 8000cd2: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000cd4: 69fb ldr r3, [r7, #28] + 8000cd6: f1c3 0307 rsb r3, r3, #7 + 8000cda: 2b04 cmp r3, #4 + 8000cdc: bf28 it cs + 8000cde: 2304 movcs r3, #4 + 8000ce0: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000ce2: 69fb ldr r3, [r7, #28] + 8000ce4: 3304 adds r3, #4 + 8000ce6: 2b06 cmp r3, #6 + 8000ce8: d902 bls.n 8000cf0 + 8000cea: 69fb ldr r3, [r7, #28] + 8000cec: 3b03 subs r3, #3 + 8000cee: e000 b.n 8000cf2 + 8000cf0: 2300 movs r3, #0 + 8000cf2: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000cf4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000cf8: 69bb ldr r3, [r7, #24] + 8000cfa: fa02 f303 lsl.w r3, r2, r3 + 8000cfe: 43da mvns r2, r3 + 8000d00: 68bb ldr r3, [r7, #8] + 8000d02: 401a ands r2, r3 + 8000d04: 697b ldr r3, [r7, #20] + 8000d06: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000d08: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000d0c: 697b ldr r3, [r7, #20] + 8000d0e: fa01 f303 lsl.w r3, r1, r3 + 8000d12: 43d9 mvns r1, r3 + 8000d14: 687b ldr r3, [r7, #4] + 8000d16: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000d18: 4313 orrs r3, r2 + ); +} + 8000d1a: 4618 mov r0, r3 + 8000d1c: 3724 adds r7, #36 @ 0x24 + 8000d1e: 46bd mov sp, r7 + 8000d20: bc80 pop {r7} + 8000d22: 4770 bx lr + +08000d24 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000d24: b580 push {r7, lr} + 8000d26: b082 sub sp, #8 + 8000d28: af00 add r7, sp, #0 + 8000d2a: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000d2c: 687b ldr r3, [r7, #4] + 8000d2e: 3b01 subs r3, #1 + 8000d30: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000d34: d301 bcc.n 8000d3a + { + return (1UL); /* Reload value impossible */ + 8000d36: 2301 movs r3, #1 + 8000d38: e00f b.n 8000d5a + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000d3a: 4a0a ldr r2, [pc, #40] @ (8000d64 ) + 8000d3c: 687b ldr r3, [r7, #4] + 8000d3e: 3b01 subs r3, #1 + 8000d40: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000d42: 210f movs r1, #15 + 8000d44: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000d48: f7ff ff90 bl 8000c6c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000d4c: 4b05 ldr r3, [pc, #20] @ (8000d64 ) + 8000d4e: 2200 movs r2, #0 + 8000d50: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000d52: 4b04 ldr r3, [pc, #16] @ (8000d64 ) + 8000d54: 2207 movs r2, #7 + 8000d56: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000d58: 2300 movs r3, #0 +} + 8000d5a: 4618 mov r0, r3 + 8000d5c: 3708 adds r7, #8 + 8000d5e: 46bd mov sp, r7 + 8000d60: bd80 pop {r7, pc} + 8000d62: bf00 nop + 8000d64: e000e010 .word 0xe000e010 + +08000d68 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000d68: b580 push {r7, lr} + 8000d6a: b082 sub sp, #8 + 8000d6c: af00 add r7, sp, #0 + 8000d6e: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8000d70: 6878 ldr r0, [r7, #4] + 8000d72: f7ff ff49 bl 8000c08 <__NVIC_SetPriorityGrouping> +} + 8000d76: bf00 nop + 8000d78: 3708 adds r7, #8 + 8000d7a: 46bd mov sp, r7 + 8000d7c: bd80 pop {r7, pc} + +08000d7e : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000d7e: b580 push {r7, lr} + 8000d80: b086 sub sp, #24 + 8000d82: af00 add r7, sp, #0 + 8000d84: 4603 mov r3, r0 + 8000d86: 60b9 str r1, [r7, #8] + 8000d88: 607a str r2, [r7, #4] + 8000d8a: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8000d8c: 2300 movs r3, #0 + 8000d8e: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8000d90: f7ff ff5e bl 8000c50 <__NVIC_GetPriorityGrouping> + 8000d94: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8000d96: 687a ldr r2, [r7, #4] + 8000d98: 68b9 ldr r1, [r7, #8] + 8000d9a: 6978 ldr r0, [r7, #20] + 8000d9c: f7ff ff90 bl 8000cc0 + 8000da0: 4602 mov r2, r0 + 8000da2: f997 300f ldrsb.w r3, [r7, #15] + 8000da6: 4611 mov r1, r2 + 8000da8: 4618 mov r0, r3 + 8000daa: f7ff ff5f bl 8000c6c <__NVIC_SetPriority> +} + 8000dae: bf00 nop + 8000db0: 3718 adds r7, #24 + 8000db2: 46bd mov sp, r7 + 8000db4: bd80 pop {r7, pc} + +08000db6 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000db6: b580 push {r7, lr} + 8000db8: b082 sub sp, #8 + 8000dba: af00 add r7, sp, #0 + 8000dbc: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000dbe: 6878 ldr r0, [r7, #4] + 8000dc0: f7ff ffb0 bl 8000d24 + 8000dc4: 4603 mov r3, r0 +} + 8000dc6: 4618 mov r0, r3 + 8000dc8: 3708 adds r7, #8 + 8000dca: 46bd mov sp, r7 + 8000dcc: bd80 pop {r7, pc} + ... + +08000dd0 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000dd0: b480 push {r7} + 8000dd2: b087 sub sp, #28 + 8000dd4: af00 add r7, sp, #0 + 8000dd6: 6078 str r0, [r7, #4] + 8000dd8: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8000dda: 2300 movs r3, #0 + 8000ddc: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8000dde: 2300 movs r3, #0 + 8000de0: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 8000de2: 2300 movs r3, #0 + 8000de4: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8000de6: e160 b.n 80010aa + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8000de8: 683b ldr r3, [r7, #0] + 8000dea: 681a ldr r2, [r3, #0] + 8000dec: 2101 movs r1, #1 + 8000dee: 697b ldr r3, [r7, #20] + 8000df0: fa01 f303 lsl.w r3, r1, r3 + 8000df4: 4013 ands r3, r2 + 8000df6: 60fb str r3, [r7, #12] + + if (iocurrent) + 8000df8: 68fb ldr r3, [r7, #12] + 8000dfa: 2b00 cmp r3, #0 + 8000dfc: f000 8152 beq.w 80010a4 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000e00: 683b ldr r3, [r7, #0] + 8000e02: 685b ldr r3, [r3, #4] + 8000e04: f003 0303 and.w r3, r3, #3 + 8000e08: 2b01 cmp r3, #1 + 8000e0a: d005 beq.n 8000e18 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8000e0c: 683b ldr r3, [r7, #0] + 8000e0e: 685b ldr r3, [r3, #4] + 8000e10: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8000e14: 2b02 cmp r3, #2 + 8000e16: d130 bne.n 8000e7a + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8000e18: 687b ldr r3, [r7, #4] + 8000e1a: 689b ldr r3, [r3, #8] + 8000e1c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8000e1e: 697b ldr r3, [r7, #20] + 8000e20: 005b lsls r3, r3, #1 + 8000e22: 2203 movs r2, #3 + 8000e24: fa02 f303 lsl.w r3, r2, r3 + 8000e28: 43db mvns r3, r3 + 8000e2a: 693a ldr r2, [r7, #16] + 8000e2c: 4013 ands r3, r2 + 8000e2e: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 8000e30: 683b ldr r3, [r7, #0] + 8000e32: 68da ldr r2, [r3, #12] + 8000e34: 697b ldr r3, [r7, #20] + 8000e36: 005b lsls r3, r3, #1 + 8000e38: fa02 f303 lsl.w r3, r2, r3 + 8000e3c: 693a ldr r2, [r7, #16] + 8000e3e: 4313 orrs r3, r2 + 8000e40: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8000e42: 687b ldr r3, [r7, #4] + 8000e44: 693a ldr r2, [r7, #16] + 8000e46: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8000e48: 687b ldr r3, [r7, #4] + 8000e4a: 685b ldr r3, [r3, #4] + 8000e4c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 8000e4e: 2201 movs r2, #1 + 8000e50: 697b ldr r3, [r7, #20] + 8000e52: fa02 f303 lsl.w r3, r2, r3 + 8000e56: 43db mvns r3, r3 + 8000e58: 693a ldr r2, [r7, #16] + 8000e5a: 4013 ands r3, r2 + 8000e5c: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8000e5e: 683b ldr r3, [r7, #0] + 8000e60: 685b ldr r3, [r3, #4] + 8000e62: 091b lsrs r3, r3, #4 + 8000e64: f003 0201 and.w r2, r3, #1 + 8000e68: 697b ldr r3, [r7, #20] + 8000e6a: fa02 f303 lsl.w r3, r2, r3 + 8000e6e: 693a ldr r2, [r7, #16] + 8000e70: 4313 orrs r3, r2 + 8000e72: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8000e74: 687b ldr r3, [r7, #4] + 8000e76: 693a ldr r2, [r7, #16] + 8000e78: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8000e7a: 683b ldr r3, [r7, #0] + 8000e7c: 685b ldr r3, [r3, #4] + 8000e7e: f003 0303 and.w r3, r3, #3 + 8000e82: 2b03 cmp r3, #3 + 8000e84: d017 beq.n 8000eb6 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8000e86: 687b ldr r3, [r7, #4] + 8000e88: 68db ldr r3, [r3, #12] + 8000e8a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 8000e8c: 697b ldr r3, [r7, #20] + 8000e8e: 005b lsls r3, r3, #1 + 8000e90: 2203 movs r2, #3 + 8000e92: fa02 f303 lsl.w r3, r2, r3 + 8000e96: 43db mvns r3, r3 + 8000e98: 693a ldr r2, [r7, #16] + 8000e9a: 4013 ands r3, r2 + 8000e9c: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 8000e9e: 683b ldr r3, [r7, #0] + 8000ea0: 689a ldr r2, [r3, #8] + 8000ea2: 697b ldr r3, [r7, #20] + 8000ea4: 005b lsls r3, r3, #1 + 8000ea6: fa02 f303 lsl.w r3, r2, r3 + 8000eaa: 693a ldr r2, [r7, #16] + 8000eac: 4313 orrs r3, r2 + 8000eae: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8000eb0: 687b ldr r3, [r7, #4] + 8000eb2: 693a ldr r2, [r7, #16] + 8000eb4: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8000eb6: 683b ldr r3, [r7, #0] + 8000eb8: 685b ldr r3, [r3, #4] + 8000eba: f003 0303 and.w r3, r3, #3 + 8000ebe: 2b02 cmp r3, #2 + 8000ec0: d123 bne.n 8000f0a + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 8000ec2: 697b ldr r3, [r7, #20] + 8000ec4: 08da lsrs r2, r3, #3 + 8000ec6: 687b ldr r3, [r7, #4] + 8000ec8: 3208 adds r2, #8 + 8000eca: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8000ece: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 8000ed0: 697b ldr r3, [r7, #20] + 8000ed2: f003 0307 and.w r3, r3, #7 + 8000ed6: 009b lsls r3, r3, #2 + 8000ed8: 220f movs r2, #15 + 8000eda: fa02 f303 lsl.w r3, r2, r3 + 8000ede: 43db mvns r3, r3 + 8000ee0: 693a ldr r2, [r7, #16] + 8000ee2: 4013 ands r3, r2 + 8000ee4: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8000ee6: 683b ldr r3, [r7, #0] + 8000ee8: 691a ldr r2, [r3, #16] + 8000eea: 697b ldr r3, [r7, #20] + 8000eec: f003 0307 and.w r3, r3, #7 + 8000ef0: 009b lsls r3, r3, #2 + 8000ef2: fa02 f303 lsl.w r3, r2, r3 + 8000ef6: 693a ldr r2, [r7, #16] + 8000ef8: 4313 orrs r3, r2 + 8000efa: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 8000efc: 697b ldr r3, [r7, #20] + 8000efe: 08da lsrs r2, r3, #3 + 8000f00: 687b ldr r3, [r7, #4] + 8000f02: 3208 adds r2, #8 + 8000f04: 6939 ldr r1, [r7, #16] + 8000f06: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8000f0a: 687b ldr r3, [r7, #4] + 8000f0c: 681b ldr r3, [r3, #0] + 8000f0e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 8000f10: 697b ldr r3, [r7, #20] + 8000f12: 005b lsls r3, r3, #1 + 8000f14: 2203 movs r2, #3 + 8000f16: fa02 f303 lsl.w r3, r2, r3 + 8000f1a: 43db mvns r3, r3 + 8000f1c: 693a ldr r2, [r7, #16] + 8000f1e: 4013 ands r3, r2 + 8000f20: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8000f22: 683b ldr r3, [r7, #0] + 8000f24: 685b ldr r3, [r3, #4] + 8000f26: f003 0203 and.w r2, r3, #3 + 8000f2a: 697b ldr r3, [r7, #20] + 8000f2c: 005b lsls r3, r3, #1 + 8000f2e: fa02 f303 lsl.w r3, r2, r3 + 8000f32: 693a ldr r2, [r7, #16] + 8000f34: 4313 orrs r3, r2 + 8000f36: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8000f38: 687b ldr r3, [r7, #4] + 8000f3a: 693a ldr r2, [r7, #16] + 8000f3c: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8000f3e: 683b ldr r3, [r7, #0] + 8000f40: 685b ldr r3, [r3, #4] + 8000f42: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8000f46: 2b00 cmp r3, #0 + 8000f48: f000 80ac beq.w 80010a4 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000f4c: 4b5e ldr r3, [pc, #376] @ (80010c8 ) + 8000f4e: 6a1b ldr r3, [r3, #32] + 8000f50: 4a5d ldr r2, [pc, #372] @ (80010c8 ) + 8000f52: f043 0301 orr.w r3, r3, #1 + 8000f56: 6213 str r3, [r2, #32] + 8000f58: 4b5b ldr r3, [pc, #364] @ (80010c8 ) + 8000f5a: 6a1b ldr r3, [r3, #32] + 8000f5c: f003 0301 and.w r3, r3, #1 + 8000f60: 60bb str r3, [r7, #8] + 8000f62: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8000f64: 4a59 ldr r2, [pc, #356] @ (80010cc ) + 8000f66: 697b ldr r3, [r7, #20] + 8000f68: 089b lsrs r3, r3, #2 + 8000f6a: 3302 adds r3, #2 + 8000f6c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8000f70: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 8000f72: 697b ldr r3, [r7, #20] + 8000f74: f003 0303 and.w r3, r3, #3 + 8000f78: 009b lsls r3, r3, #2 + 8000f7a: 220f movs r2, #15 + 8000f7c: fa02 f303 lsl.w r3, r2, r3 + 8000f80: 43db mvns r3, r3 + 8000f82: 693a ldr r2, [r7, #16] + 8000f84: 4013 ands r3, r2 + 8000f86: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 8000f88: 687b ldr r3, [r7, #4] + 8000f8a: 4a51 ldr r2, [pc, #324] @ (80010d0 ) + 8000f8c: 4293 cmp r3, r2 + 8000f8e: d025 beq.n 8000fdc + 8000f90: 687b ldr r3, [r7, #4] + 8000f92: 4a50 ldr r2, [pc, #320] @ (80010d4 ) + 8000f94: 4293 cmp r3, r2 + 8000f96: d01f beq.n 8000fd8 + 8000f98: 687b ldr r3, [r7, #4] + 8000f9a: 4a4f ldr r2, [pc, #316] @ (80010d8 ) + 8000f9c: 4293 cmp r3, r2 + 8000f9e: d019 beq.n 8000fd4 + 8000fa0: 687b ldr r3, [r7, #4] + 8000fa2: 4a4e ldr r2, [pc, #312] @ (80010dc ) + 8000fa4: 4293 cmp r3, r2 + 8000fa6: d013 beq.n 8000fd0 + 8000fa8: 687b ldr r3, [r7, #4] + 8000faa: 4a4d ldr r2, [pc, #308] @ (80010e0 ) + 8000fac: 4293 cmp r3, r2 + 8000fae: d00d beq.n 8000fcc + 8000fb0: 687b ldr r3, [r7, #4] + 8000fb2: 4a4c ldr r2, [pc, #304] @ (80010e4 ) + 8000fb4: 4293 cmp r3, r2 + 8000fb6: d007 beq.n 8000fc8 + 8000fb8: 687b ldr r3, [r7, #4] + 8000fba: 4a4b ldr r2, [pc, #300] @ (80010e8 ) + 8000fbc: 4293 cmp r3, r2 + 8000fbe: d101 bne.n 8000fc4 + 8000fc0: 2306 movs r3, #6 + 8000fc2: e00c b.n 8000fde + 8000fc4: 2307 movs r3, #7 + 8000fc6: e00a b.n 8000fde + 8000fc8: 2305 movs r3, #5 + 8000fca: e008 b.n 8000fde + 8000fcc: 2304 movs r3, #4 + 8000fce: e006 b.n 8000fde + 8000fd0: 2303 movs r3, #3 + 8000fd2: e004 b.n 8000fde + 8000fd4: 2302 movs r3, #2 + 8000fd6: e002 b.n 8000fde + 8000fd8: 2301 movs r3, #1 + 8000fda: e000 b.n 8000fde + 8000fdc: 2300 movs r3, #0 + 8000fde: 697a ldr r2, [r7, #20] + 8000fe0: f002 0203 and.w r2, r2, #3 + 8000fe4: 0092 lsls r2, r2, #2 + 8000fe6: 4093 lsls r3, r2 + 8000fe8: 693a ldr r2, [r7, #16] + 8000fea: 4313 orrs r3, r2 + 8000fec: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 8000fee: 4937 ldr r1, [pc, #220] @ (80010cc ) + 8000ff0: 697b ldr r3, [r7, #20] + 8000ff2: 089b lsrs r3, r3, #2 + 8000ff4: 3302 adds r3, #2 + 8000ff6: 693a ldr r2, [r7, #16] + 8000ff8: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8000ffc: 4b3b ldr r3, [pc, #236] @ (80010ec ) + 8000ffe: 689b ldr r3, [r3, #8] + 8001000: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001002: 68fb ldr r3, [r7, #12] + 8001004: 43db mvns r3, r3 + 8001006: 693a ldr r2, [r7, #16] + 8001008: 4013 ands r3, r2 + 800100a: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 800100c: 683b ldr r3, [r7, #0] + 800100e: 685b ldr r3, [r3, #4] + 8001010: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001014: 2b00 cmp r3, #0 + 8001016: d003 beq.n 8001020 + { + SET_BIT(temp, iocurrent); + 8001018: 693a ldr r2, [r7, #16] + 800101a: 68fb ldr r3, [r7, #12] + 800101c: 4313 orrs r3, r2 + 800101e: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 8001020: 4a32 ldr r2, [pc, #200] @ (80010ec ) + 8001022: 693b ldr r3, [r7, #16] + 8001024: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8001026: 4b31 ldr r3, [pc, #196] @ (80010ec ) + 8001028: 68db ldr r3, [r3, #12] + 800102a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 800102c: 68fb ldr r3, [r7, #12] + 800102e: 43db mvns r3, r3 + 8001030: 693a ldr r2, [r7, #16] + 8001032: 4013 ands r3, r2 + 8001034: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8001036: 683b ldr r3, [r7, #0] + 8001038: 685b ldr r3, [r3, #4] + 800103a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800103e: 2b00 cmp r3, #0 + 8001040: d003 beq.n 800104a + { + SET_BIT(temp, iocurrent); + 8001042: 693a ldr r2, [r7, #16] + 8001044: 68fb ldr r3, [r7, #12] + 8001046: 4313 orrs r3, r2 + 8001048: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 800104a: 4a28 ldr r2, [pc, #160] @ (80010ec ) + 800104c: 693b ldr r3, [r7, #16] + 800104e: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 8001050: 4b26 ldr r3, [pc, #152] @ (80010ec ) + 8001052: 685b ldr r3, [r3, #4] + 8001054: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001056: 68fb ldr r3, [r7, #12] + 8001058: 43db mvns r3, r3 + 800105a: 693a ldr r2, [r7, #16] + 800105c: 4013 ands r3, r2 + 800105e: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8001060: 683b ldr r3, [r7, #0] + 8001062: 685b ldr r3, [r3, #4] + 8001064: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001068: 2b00 cmp r3, #0 + 800106a: d003 beq.n 8001074 + { + SET_BIT(temp, iocurrent); + 800106c: 693a ldr r2, [r7, #16] + 800106e: 68fb ldr r3, [r7, #12] + 8001070: 4313 orrs r3, r2 + 8001072: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8001074: 4a1d ldr r2, [pc, #116] @ (80010ec ) + 8001076: 693b ldr r3, [r7, #16] + 8001078: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 800107a: 4b1c ldr r3, [pc, #112] @ (80010ec ) + 800107c: 681b ldr r3, [r3, #0] + 800107e: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001080: 68fb ldr r3, [r7, #12] + 8001082: 43db mvns r3, r3 + 8001084: 693a ldr r2, [r7, #16] + 8001086: 4013 ands r3, r2 + 8001088: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 800108a: 683b ldr r3, [r7, #0] + 800108c: 685b ldr r3, [r3, #4] + 800108e: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001092: 2b00 cmp r3, #0 + 8001094: d003 beq.n 800109e + { + SET_BIT(temp, iocurrent); + 8001096: 693a ldr r2, [r7, #16] + 8001098: 68fb ldr r3, [r7, #12] + 800109a: 4313 orrs r3, r2 + 800109c: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 800109e: 4a13 ldr r2, [pc, #76] @ (80010ec ) + 80010a0: 693b ldr r3, [r7, #16] + 80010a2: 6013 str r3, [r2, #0] + } + } + + position++; + 80010a4: 697b ldr r3, [r7, #20] + 80010a6: 3301 adds r3, #1 + 80010a8: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 80010aa: 683b ldr r3, [r7, #0] + 80010ac: 681a ldr r2, [r3, #0] + 80010ae: 697b ldr r3, [r7, #20] + 80010b0: fa22 f303 lsr.w r3, r2, r3 + 80010b4: 2b00 cmp r3, #0 + 80010b6: f47f ae97 bne.w 8000de8 + } +} + 80010ba: bf00 nop + 80010bc: bf00 nop + 80010be: 371c adds r7, #28 + 80010c0: 46bd mov sp, r7 + 80010c2: bc80 pop {r7} + 80010c4: 4770 bx lr + 80010c6: bf00 nop + 80010c8: 40023800 .word 0x40023800 + 80010cc: 40010000 .word 0x40010000 + 80010d0: 40020000 .word 0x40020000 + 80010d4: 40020400 .word 0x40020400 + 80010d8: 40020800 .word 0x40020800 + 80010dc: 40020c00 .word 0x40020c00 + 80010e0: 40021000 .word 0x40021000 + 80010e4: 40021400 .word 0x40021400 + 80010e8: 40021800 .word 0x40021800 + 80010ec: 40010400 .word 0x40010400 + +080010f0 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80010f0: b480 push {r7} + 80010f2: b083 sub sp, #12 + 80010f4: af00 add r7, sp, #0 + 80010f6: 6078 str r0, [r7, #4] + 80010f8: 460b mov r3, r1 + 80010fa: 807b strh r3, [r7, #2] + 80010fc: 4613 mov r3, r2 + 80010fe: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 8001100: 787b ldrb r3, [r7, #1] + 8001102: 2b00 cmp r3, #0 + 8001104: d003 beq.n 800110e + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8001106: 887a ldrh r2, [r7, #2] + 8001108: 687b ldr r3, [r7, #4] + 800110a: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 800110c: e003 b.n 8001116 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 800110e: 887b ldrh r3, [r7, #2] + 8001110: 041a lsls r2, r3, #16 + 8001112: 687b ldr r3, [r7, #4] + 8001114: 619a str r2, [r3, #24] +} + 8001116: bf00 nop + 8001118: 370c adds r7, #12 + 800111a: 46bd mov sp, r7 + 800111c: bc80 pop {r7} + 800111e: 4770 bx lr + +08001120 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8001120: b580 push {r7, lr} + 8001122: b088 sub sp, #32 + 8001124: af00 add r7, sp, #0 + 8001126: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 8001128: 687b ldr r3, [r7, #4] + 800112a: 2b00 cmp r3, #0 + 800112c: d101 bne.n 8001132 + { + return HAL_ERROR; + 800112e: 2301 movs r3, #1 + 8001130: e31d b.n 800176e + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8001132: 4b94 ldr r3, [pc, #592] @ (8001384 ) + 8001134: 689b ldr r3, [r3, #8] + 8001136: f003 030c and.w r3, r3, #12 + 800113a: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 800113c: 4b91 ldr r3, [pc, #580] @ (8001384 ) + 800113e: 689b ldr r3, [r3, #8] + 8001140: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001144: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8001146: 687b ldr r3, [r7, #4] + 8001148: 681b ldr r3, [r3, #0] + 800114a: f003 0301 and.w r3, r3, #1 + 800114e: 2b00 cmp r3, #0 + 8001150: d07b beq.n 800124a + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 8001152: 69bb ldr r3, [r7, #24] + 8001154: 2b08 cmp r3, #8 + 8001156: d006 beq.n 8001166 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8001158: 69bb ldr r3, [r7, #24] + 800115a: 2b0c cmp r3, #12 + 800115c: d10f bne.n 800117e + 800115e: 697b ldr r3, [r7, #20] + 8001160: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001164: d10b bne.n 800117e + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001166: 4b87 ldr r3, [pc, #540] @ (8001384 ) + 8001168: 681b ldr r3, [r3, #0] + 800116a: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800116e: 2b00 cmp r3, #0 + 8001170: d06a beq.n 8001248 + 8001172: 687b ldr r3, [r7, #4] + 8001174: 685b ldr r3, [r3, #4] + 8001176: 2b00 cmp r3, #0 + 8001178: d166 bne.n 8001248 + { + return HAL_ERROR; + 800117a: 2301 movs r3, #1 + 800117c: e2f7 b.n 800176e + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800117e: 687b ldr r3, [r7, #4] + 8001180: 685b ldr r3, [r3, #4] + 8001182: 2b01 cmp r3, #1 + 8001184: d106 bne.n 8001194 + 8001186: 4b7f ldr r3, [pc, #508] @ (8001384 ) + 8001188: 681b ldr r3, [r3, #0] + 800118a: 4a7e ldr r2, [pc, #504] @ (8001384 ) + 800118c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001190: 6013 str r3, [r2, #0] + 8001192: e02d b.n 80011f0 + 8001194: 687b ldr r3, [r7, #4] + 8001196: 685b ldr r3, [r3, #4] + 8001198: 2b00 cmp r3, #0 + 800119a: d10c bne.n 80011b6 + 800119c: 4b79 ldr r3, [pc, #484] @ (8001384 ) + 800119e: 681b ldr r3, [r3, #0] + 80011a0: 4a78 ldr r2, [pc, #480] @ (8001384 ) + 80011a2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80011a6: 6013 str r3, [r2, #0] + 80011a8: 4b76 ldr r3, [pc, #472] @ (8001384 ) + 80011aa: 681b ldr r3, [r3, #0] + 80011ac: 4a75 ldr r2, [pc, #468] @ (8001384 ) + 80011ae: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 80011b2: 6013 str r3, [r2, #0] + 80011b4: e01c b.n 80011f0 + 80011b6: 687b ldr r3, [r7, #4] + 80011b8: 685b ldr r3, [r3, #4] + 80011ba: 2b05 cmp r3, #5 + 80011bc: d10c bne.n 80011d8 + 80011be: 4b71 ldr r3, [pc, #452] @ (8001384 ) + 80011c0: 681b ldr r3, [r3, #0] + 80011c2: 4a70 ldr r2, [pc, #448] @ (8001384 ) + 80011c4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 80011c8: 6013 str r3, [r2, #0] + 80011ca: 4b6e ldr r3, [pc, #440] @ (8001384 ) + 80011cc: 681b ldr r3, [r3, #0] + 80011ce: 4a6d ldr r2, [pc, #436] @ (8001384 ) + 80011d0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 80011d4: 6013 str r3, [r2, #0] + 80011d6: e00b b.n 80011f0 + 80011d8: 4b6a ldr r3, [pc, #424] @ (8001384 ) + 80011da: 681b ldr r3, [r3, #0] + 80011dc: 4a69 ldr r2, [pc, #420] @ (8001384 ) + 80011de: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 80011e2: 6013 str r3, [r2, #0] + 80011e4: 4b67 ldr r3, [pc, #412] @ (8001384 ) + 80011e6: 681b ldr r3, [r3, #0] + 80011e8: 4a66 ldr r2, [pc, #408] @ (8001384 ) + 80011ea: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 80011ee: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80011f0: 687b ldr r3, [r7, #4] + 80011f2: 685b ldr r3, [r3, #4] + 80011f4: 2b00 cmp r3, #0 + 80011f6: d013 beq.n 8001220 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80011f8: f7ff fcda bl 8000bb0 + 80011fc: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 80011fe: e008 b.n 8001212 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001200: f7ff fcd6 bl 8000bb0 + 8001204: 4602 mov r2, r0 + 8001206: 693b ldr r3, [r7, #16] + 8001208: 1ad3 subs r3, r2, r3 + 800120a: 2b64 cmp r3, #100 @ 0x64 + 800120c: d901 bls.n 8001212 + { + return HAL_TIMEOUT; + 800120e: 2303 movs r3, #3 + 8001210: e2ad b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001212: 4b5c ldr r3, [pc, #368] @ (8001384 ) + 8001214: 681b ldr r3, [r3, #0] + 8001216: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800121a: 2b00 cmp r3, #0 + 800121c: d0f0 beq.n 8001200 + 800121e: e014 b.n 800124a + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001220: f7ff fcc6 bl 8000bb0 + 8001224: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 8001226: e008 b.n 800123a + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001228: f7ff fcc2 bl 8000bb0 + 800122c: 4602 mov r2, r0 + 800122e: 693b ldr r3, [r7, #16] + 8001230: 1ad3 subs r3, r2, r3 + 8001232: 2b64 cmp r3, #100 @ 0x64 + 8001234: d901 bls.n 800123a + { + return HAL_TIMEOUT; + 8001236: 2303 movs r3, #3 + 8001238: e299 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 800123a: 4b52 ldr r3, [pc, #328] @ (8001384 ) + 800123c: 681b ldr r3, [r3, #0] + 800123e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001242: 2b00 cmp r3, #0 + 8001244: d1f0 bne.n 8001228 + 8001246: e000 b.n 800124a + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8001248: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 800124a: 687b ldr r3, [r7, #4] + 800124c: 681b ldr r3, [r3, #0] + 800124e: f003 0302 and.w r3, r3, #2 + 8001252: 2b00 cmp r3, #0 + 8001254: d05a beq.n 800130c + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 8001256: 69bb ldr r3, [r7, #24] + 8001258: 2b04 cmp r3, #4 + 800125a: d005 beq.n 8001268 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 800125c: 69bb ldr r3, [r7, #24] + 800125e: 2b0c cmp r3, #12 + 8001260: d119 bne.n 8001296 + 8001262: 697b ldr r3, [r7, #20] + 8001264: 2b00 cmp r3, #0 + 8001266: d116 bne.n 8001296 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001268: 4b46 ldr r3, [pc, #280] @ (8001384 ) + 800126a: 681b ldr r3, [r3, #0] + 800126c: f003 0302 and.w r3, r3, #2 + 8001270: 2b00 cmp r3, #0 + 8001272: d005 beq.n 8001280 + 8001274: 687b ldr r3, [r7, #4] + 8001276: 68db ldr r3, [r3, #12] + 8001278: 2b01 cmp r3, #1 + 800127a: d001 beq.n 8001280 + { + return HAL_ERROR; + 800127c: 2301 movs r3, #1 + 800127e: e276 b.n 800176e + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8001280: 4b40 ldr r3, [pc, #256] @ (8001384 ) + 8001282: 685b ldr r3, [r3, #4] + 8001284: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001288: 687b ldr r3, [r7, #4] + 800128a: 691b ldr r3, [r3, #16] + 800128c: 021b lsls r3, r3, #8 + 800128e: 493d ldr r1, [pc, #244] @ (8001384 ) + 8001290: 4313 orrs r3, r2 + 8001292: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001294: e03a b.n 800130c + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8001296: 687b ldr r3, [r7, #4] + 8001298: 68db ldr r3, [r3, #12] + 800129a: 2b00 cmp r3, #0 + 800129c: d020 beq.n 80012e0 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800129e: 4b3a ldr r3, [pc, #232] @ (8001388 ) + 80012a0: 2201 movs r2, #1 + 80012a2: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80012a4: f7ff fc84 bl 8000bb0 + 80012a8: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80012aa: e008 b.n 80012be + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80012ac: f7ff fc80 bl 8000bb0 + 80012b0: 4602 mov r2, r0 + 80012b2: 693b ldr r3, [r7, #16] + 80012b4: 1ad3 subs r3, r2, r3 + 80012b6: 2b02 cmp r3, #2 + 80012b8: d901 bls.n 80012be + { + return HAL_TIMEOUT; + 80012ba: 2303 movs r3, #3 + 80012bc: e257 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80012be: 4b31 ldr r3, [pc, #196] @ (8001384 ) + 80012c0: 681b ldr r3, [r3, #0] + 80012c2: f003 0302 and.w r3, r3, #2 + 80012c6: 2b00 cmp r3, #0 + 80012c8: d0f0 beq.n 80012ac + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80012ca: 4b2e ldr r3, [pc, #184] @ (8001384 ) + 80012cc: 685b ldr r3, [r3, #4] + 80012ce: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 80012d2: 687b ldr r3, [r7, #4] + 80012d4: 691b ldr r3, [r3, #16] + 80012d6: 021b lsls r3, r3, #8 + 80012d8: 492a ldr r1, [pc, #168] @ (8001384 ) + 80012da: 4313 orrs r3, r2 + 80012dc: 604b str r3, [r1, #4] + 80012de: e015 b.n 800130c + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80012e0: 4b29 ldr r3, [pc, #164] @ (8001388 ) + 80012e2: 2200 movs r2, #0 + 80012e4: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80012e6: f7ff fc63 bl 8000bb0 + 80012ea: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 80012ec: e008 b.n 8001300 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 80012ee: f7ff fc5f bl 8000bb0 + 80012f2: 4602 mov r2, r0 + 80012f4: 693b ldr r3, [r7, #16] + 80012f6: 1ad3 subs r3, r2, r3 + 80012f8: 2b02 cmp r3, #2 + 80012fa: d901 bls.n 8001300 + { + return HAL_TIMEOUT; + 80012fc: 2303 movs r3, #3 + 80012fe: e236 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001300: 4b20 ldr r3, [pc, #128] @ (8001384 ) + 8001302: 681b ldr r3, [r3, #0] + 8001304: f003 0302 and.w r3, r3, #2 + 8001308: 2b00 cmp r3, #0 + 800130a: d1f0 bne.n 80012ee + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 800130c: 687b ldr r3, [r7, #4] + 800130e: 681b ldr r3, [r3, #0] + 8001310: f003 0310 and.w r3, r3, #16 + 8001314: 2b00 cmp r3, #0 + 8001316: f000 80b8 beq.w 800148a + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 800131a: 69bb ldr r3, [r7, #24] + 800131c: 2b00 cmp r3, #0 + 800131e: d170 bne.n 8001402 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8001320: 4b18 ldr r3, [pc, #96] @ (8001384 ) + 8001322: 681b ldr r3, [r3, #0] + 8001324: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001328: 2b00 cmp r3, #0 + 800132a: d005 beq.n 8001338 + 800132c: 687b ldr r3, [r7, #4] + 800132e: 699b ldr r3, [r3, #24] + 8001330: 2b00 cmp r3, #0 + 8001332: d101 bne.n 8001338 + { + return HAL_ERROR; + 8001334: 2301 movs r3, #1 + 8001336: e21a b.n 800176e + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 8001338: 687b ldr r3, [r7, #4] + 800133a: 6a1a ldr r2, [r3, #32] + 800133c: 4b11 ldr r3, [pc, #68] @ (8001384 ) + 800133e: 685b ldr r3, [r3, #4] + 8001340: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 8001344: 429a cmp r2, r3 + 8001346: d921 bls.n 800138c + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001348: 687b ldr r3, [r7, #4] + 800134a: 6a1b ldr r3, [r3, #32] + 800134c: 4618 mov r0, r3 + 800134e: f000 fc09 bl 8001b64 + 8001352: 4603 mov r3, r0 + 8001354: 2b00 cmp r3, #0 + 8001356: d001 beq.n 800135c + { + return HAL_ERROR; + 8001358: 2301 movs r3, #1 + 800135a: e208 b.n 800176e + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800135c: 4b09 ldr r3, [pc, #36] @ (8001384 ) + 800135e: 685b ldr r3, [r3, #4] + 8001360: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001364: 687b ldr r3, [r7, #4] + 8001366: 6a1b ldr r3, [r3, #32] + 8001368: 4906 ldr r1, [pc, #24] @ (8001384 ) + 800136a: 4313 orrs r3, r2 + 800136c: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800136e: 4b05 ldr r3, [pc, #20] @ (8001384 ) + 8001370: 685b ldr r3, [r3, #4] + 8001372: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001376: 687b ldr r3, [r7, #4] + 8001378: 69db ldr r3, [r3, #28] + 800137a: 061b lsls r3, r3, #24 + 800137c: 4901 ldr r1, [pc, #4] @ (8001384 ) + 800137e: 4313 orrs r3, r2 + 8001380: 604b str r3, [r1, #4] + 8001382: e020 b.n 80013c6 + 8001384: 40023800 .word 0x40023800 + 8001388: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 800138c: 4b99 ldr r3, [pc, #612] @ (80015f4 ) + 800138e: 685b ldr r3, [r3, #4] + 8001390: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001394: 687b ldr r3, [r7, #4] + 8001396: 6a1b ldr r3, [r3, #32] + 8001398: 4996 ldr r1, [pc, #600] @ (80015f4 ) + 800139a: 4313 orrs r3, r2 + 800139c: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800139e: 4b95 ldr r3, [pc, #596] @ (80015f4 ) + 80013a0: 685b ldr r3, [r3, #4] + 80013a2: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80013a6: 687b ldr r3, [r7, #4] + 80013a8: 69db ldr r3, [r3, #28] + 80013aa: 061b lsls r3, r3, #24 + 80013ac: 4991 ldr r1, [pc, #580] @ (80015f4 ) + 80013ae: 4313 orrs r3, r2 + 80013b0: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80013b2: 687b ldr r3, [r7, #4] + 80013b4: 6a1b ldr r3, [r3, #32] + 80013b6: 4618 mov r0, r3 + 80013b8: f000 fbd4 bl 8001b64 + 80013bc: 4603 mov r3, r0 + 80013be: 2b00 cmp r3, #0 + 80013c0: d001 beq.n 80013c6 + { + return HAL_ERROR; + 80013c2: 2301 movs r3, #1 + 80013c4: e1d3 b.n 800176e + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 80013c6: 687b ldr r3, [r7, #4] + 80013c8: 6a1b ldr r3, [r3, #32] + 80013ca: 0b5b lsrs r3, r3, #13 + 80013cc: 3301 adds r3, #1 + 80013ce: f44f 4200 mov.w r2, #32768 @ 0x8000 + 80013d2: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 80013d6: 4a87 ldr r2, [pc, #540] @ (80015f4 ) + 80013d8: 6892 ldr r2, [r2, #8] + 80013da: 0912 lsrs r2, r2, #4 + 80013dc: f002 020f and.w r2, r2, #15 + 80013e0: 4985 ldr r1, [pc, #532] @ (80015f8 ) + 80013e2: 5c8a ldrb r2, [r1, r2] + 80013e4: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 80013e6: 4a85 ldr r2, [pc, #532] @ (80015fc ) + 80013e8: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 80013ea: 4b85 ldr r3, [pc, #532] @ (8001600 ) + 80013ec: 681b ldr r3, [r3, #0] + 80013ee: 4618 mov r0, r3 + 80013f0: f7ff fb92 bl 8000b18 + 80013f4: 4603 mov r3, r0 + 80013f6: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 80013f8: 7bfb ldrb r3, [r7, #15] + 80013fa: 2b00 cmp r3, #0 + 80013fc: d045 beq.n 800148a + { + return status; + 80013fe: 7bfb ldrb r3, [r7, #15] + 8001400: e1b5 b.n 800176e + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8001402: 687b ldr r3, [r7, #4] + 8001404: 699b ldr r3, [r3, #24] + 8001406: 2b00 cmp r3, #0 + 8001408: d029 beq.n 800145e + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 800140a: 4b7e ldr r3, [pc, #504] @ (8001604 ) + 800140c: 2201 movs r2, #1 + 800140e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001410: f7ff fbce bl 8000bb0 + 8001414: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001416: e008 b.n 800142a + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001418: f7ff fbca bl 8000bb0 + 800141c: 4602 mov r2, r0 + 800141e: 693b ldr r3, [r7, #16] + 8001420: 1ad3 subs r3, r2, r3 + 8001422: 2b02 cmp r3, #2 + 8001424: d901 bls.n 800142a + { + return HAL_TIMEOUT; + 8001426: 2303 movs r3, #3 + 8001428: e1a1 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800142a: 4b72 ldr r3, [pc, #456] @ (80015f4 ) + 800142c: 681b ldr r3, [r3, #0] + 800142e: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001432: 2b00 cmp r3, #0 + 8001434: d0f0 beq.n 8001418 + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8001436: 4b6f ldr r3, [pc, #444] @ (80015f4 ) + 8001438: 685b ldr r3, [r3, #4] + 800143a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 800143e: 687b ldr r3, [r7, #4] + 8001440: 6a1b ldr r3, [r3, #32] + 8001442: 496c ldr r1, [pc, #432] @ (80015f4 ) + 8001444: 4313 orrs r3, r2 + 8001446: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8001448: 4b6a ldr r3, [pc, #424] @ (80015f4 ) + 800144a: 685b ldr r3, [r3, #4] + 800144c: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001450: 687b ldr r3, [r7, #4] + 8001452: 69db ldr r3, [r3, #28] + 8001454: 061b lsls r3, r3, #24 + 8001456: 4967 ldr r1, [pc, #412] @ (80015f4 ) + 8001458: 4313 orrs r3, r2 + 800145a: 604b str r3, [r1, #4] + 800145c: e015 b.n 800148a + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 800145e: 4b69 ldr r3, [pc, #420] @ (8001604 ) + 8001460: 2200 movs r2, #0 + 8001462: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001464: f7ff fba4 bl 8000bb0 + 8001468: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 800146a: e008 b.n 800147e + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 800146c: f7ff fba0 bl 8000bb0 + 8001470: 4602 mov r2, r0 + 8001472: 693b ldr r3, [r7, #16] + 8001474: 1ad3 subs r3, r2, r3 + 8001476: 2b02 cmp r3, #2 + 8001478: d901 bls.n 800147e + { + return HAL_TIMEOUT; + 800147a: 2303 movs r3, #3 + 800147c: e177 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 800147e: 4b5d ldr r3, [pc, #372] @ (80015f4 ) + 8001480: 681b ldr r3, [r3, #0] + 8001482: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001486: 2b00 cmp r3, #0 + 8001488: d1f0 bne.n 800146c + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 800148a: 687b ldr r3, [r7, #4] + 800148c: 681b ldr r3, [r3, #0] + 800148e: f003 0308 and.w r3, r3, #8 + 8001492: 2b00 cmp r3, #0 + 8001494: d030 beq.n 80014f8 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8001496: 687b ldr r3, [r7, #4] + 8001498: 695b ldr r3, [r3, #20] + 800149a: 2b00 cmp r3, #0 + 800149c: d016 beq.n 80014cc + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800149e: 4b5a ldr r3, [pc, #360] @ (8001608 ) + 80014a0: 2201 movs r2, #1 + 80014a2: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80014a4: f7ff fb84 bl 8000bb0 + 80014a8: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 80014aa: e008 b.n 80014be + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 80014ac: f7ff fb80 bl 8000bb0 + 80014b0: 4602 mov r2, r0 + 80014b2: 693b ldr r3, [r7, #16] + 80014b4: 1ad3 subs r3, r2, r3 + 80014b6: 2b02 cmp r3, #2 + 80014b8: d901 bls.n 80014be + { + return HAL_TIMEOUT; + 80014ba: 2303 movs r3, #3 + 80014bc: e157 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 80014be: 4b4d ldr r3, [pc, #308] @ (80015f4 ) + 80014c0: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014c2: f003 0302 and.w r3, r3, #2 + 80014c6: 2b00 cmp r3, #0 + 80014c8: d0f0 beq.n 80014ac + 80014ca: e015 b.n 80014f8 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 80014cc: 4b4e ldr r3, [pc, #312] @ (8001608 ) + 80014ce: 2200 movs r2, #0 + 80014d0: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80014d2: f7ff fb6d bl 8000bb0 + 80014d6: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 80014d8: e008 b.n 80014ec + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 80014da: f7ff fb69 bl 8000bb0 + 80014de: 4602 mov r2, r0 + 80014e0: 693b ldr r3, [r7, #16] + 80014e2: 1ad3 subs r3, r2, r3 + 80014e4: 2b02 cmp r3, #2 + 80014e6: d901 bls.n 80014ec + { + return HAL_TIMEOUT; + 80014e8: 2303 movs r3, #3 + 80014ea: e140 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 80014ec: 4b41 ldr r3, [pc, #260] @ (80015f4 ) + 80014ee: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014f0: f003 0302 and.w r3, r3, #2 + 80014f4: 2b00 cmp r3, #0 + 80014f6: d1f0 bne.n 80014da + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 80014f8: 687b ldr r3, [r7, #4] + 80014fa: 681b ldr r3, [r3, #0] + 80014fc: f003 0304 and.w r3, r3, #4 + 8001500: 2b00 cmp r3, #0 + 8001502: f000 80b5 beq.w 8001670 + { + FlagStatus pwrclkchanged = RESET; + 8001506: 2300 movs r3, #0 + 8001508: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800150a: 4b3a ldr r3, [pc, #232] @ (80015f4 ) + 800150c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800150e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001512: 2b00 cmp r3, #0 + 8001514: d10d bne.n 8001532 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001516: 4b37 ldr r3, [pc, #220] @ (80015f4 ) + 8001518: 6a5b ldr r3, [r3, #36] @ 0x24 + 800151a: 4a36 ldr r2, [pc, #216] @ (80015f4 ) + 800151c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001520: 6253 str r3, [r2, #36] @ 0x24 + 8001522: 4b34 ldr r3, [pc, #208] @ (80015f4 ) + 8001524: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001526: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800152a: 60bb str r3, [r7, #8] + 800152c: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 800152e: 2301 movs r3, #1 + 8001530: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001532: 4b36 ldr r3, [pc, #216] @ (800160c ) + 8001534: 681b ldr r3, [r3, #0] + 8001536: f403 7380 and.w r3, r3, #256 @ 0x100 + 800153a: 2b00 cmp r3, #0 + 800153c: d118 bne.n 8001570 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 800153e: 4b33 ldr r3, [pc, #204] @ (800160c ) + 8001540: 681b ldr r3, [r3, #0] + 8001542: 4a32 ldr r2, [pc, #200] @ (800160c ) + 8001544: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001548: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 800154a: f7ff fb31 bl 8000bb0 + 800154e: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001550: e008 b.n 8001564 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8001552: f7ff fb2d bl 8000bb0 + 8001556: 4602 mov r2, r0 + 8001558: 693b ldr r3, [r7, #16] + 800155a: 1ad3 subs r3, r2, r3 + 800155c: 2b64 cmp r3, #100 @ 0x64 + 800155e: d901 bls.n 8001564 + { + return HAL_TIMEOUT; + 8001560: 2303 movs r3, #3 + 8001562: e104 b.n 800176e + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8001564: 4b29 ldr r3, [pc, #164] @ (800160c ) + 8001566: 681b ldr r3, [r3, #0] + 8001568: f403 7380 and.w r3, r3, #256 @ 0x100 + 800156c: 2b00 cmp r3, #0 + 800156e: d0f0 beq.n 8001552 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8001570: 687b ldr r3, [r7, #4] + 8001572: 689b ldr r3, [r3, #8] + 8001574: 2b01 cmp r3, #1 + 8001576: d106 bne.n 8001586 + 8001578: 4b1e ldr r3, [pc, #120] @ (80015f4 ) + 800157a: 6b5b ldr r3, [r3, #52] @ 0x34 + 800157c: 4a1d ldr r2, [pc, #116] @ (80015f4 ) + 800157e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001582: 6353 str r3, [r2, #52] @ 0x34 + 8001584: e02d b.n 80015e2 + 8001586: 687b ldr r3, [r7, #4] + 8001588: 689b ldr r3, [r3, #8] + 800158a: 2b00 cmp r3, #0 + 800158c: d10c bne.n 80015a8 + 800158e: 4b19 ldr r3, [pc, #100] @ (80015f4 ) + 8001590: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001592: 4a18 ldr r2, [pc, #96] @ (80015f4 ) + 8001594: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001598: 6353 str r3, [r2, #52] @ 0x34 + 800159a: 4b16 ldr r3, [pc, #88] @ (80015f4 ) + 800159c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800159e: 4a15 ldr r2, [pc, #84] @ (80015f4 ) + 80015a0: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 80015a4: 6353 str r3, [r2, #52] @ 0x34 + 80015a6: e01c b.n 80015e2 + 80015a8: 687b ldr r3, [r7, #4] + 80015aa: 689b ldr r3, [r3, #8] + 80015ac: 2b05 cmp r3, #5 + 80015ae: d10c bne.n 80015ca + 80015b0: 4b10 ldr r3, [pc, #64] @ (80015f4 ) + 80015b2: 6b5b ldr r3, [r3, #52] @ 0x34 + 80015b4: 4a0f ldr r2, [pc, #60] @ (80015f4 ) + 80015b6: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 80015ba: 6353 str r3, [r2, #52] @ 0x34 + 80015bc: 4b0d ldr r3, [pc, #52] @ (80015f4 ) + 80015be: 6b5b ldr r3, [r3, #52] @ 0x34 + 80015c0: 4a0c ldr r2, [pc, #48] @ (80015f4 ) + 80015c2: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80015c6: 6353 str r3, [r2, #52] @ 0x34 + 80015c8: e00b b.n 80015e2 + 80015ca: 4b0a ldr r3, [pc, #40] @ (80015f4 ) + 80015cc: 6b5b ldr r3, [r3, #52] @ 0x34 + 80015ce: 4a09 ldr r2, [pc, #36] @ (80015f4 ) + 80015d0: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80015d4: 6353 str r3, [r2, #52] @ 0x34 + 80015d6: 4b07 ldr r3, [pc, #28] @ (80015f4 ) + 80015d8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80015da: 4a06 ldr r2, [pc, #24] @ (80015f4 ) + 80015dc: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 80015e0: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 80015e2: 687b ldr r3, [r7, #4] + 80015e4: 689b ldr r3, [r3, #8] + 80015e6: 2b00 cmp r3, #0 + 80015e8: d024 beq.n 8001634 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80015ea: f7ff fae1 bl 8000bb0 + 80015ee: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 80015f0: e019 b.n 8001626 + 80015f2: bf00 nop + 80015f4: 40023800 .word 0x40023800 + 80015f8: 08002998 .word 0x08002998 + 80015fc: 20000000 .word 0x20000000 + 8001600: 20000004 .word 0x20000004 + 8001604: 42470020 .word 0x42470020 + 8001608: 42470680 .word 0x42470680 + 800160c: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001610: f7ff face bl 8000bb0 + 8001614: 4602 mov r2, r0 + 8001616: 693b ldr r3, [r7, #16] + 8001618: 1ad3 subs r3, r2, r3 + 800161a: f241 3288 movw r2, #5000 @ 0x1388 + 800161e: 4293 cmp r3, r2 + 8001620: d901 bls.n 8001626 + { + return HAL_TIMEOUT; + 8001622: 2303 movs r3, #3 + 8001624: e0a3 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001626: 4b54 ldr r3, [pc, #336] @ (8001778 ) + 8001628: 6b5b ldr r3, [r3, #52] @ 0x34 + 800162a: f403 7300 and.w r3, r3, #512 @ 0x200 + 800162e: 2b00 cmp r3, #0 + 8001630: d0ee beq.n 8001610 + 8001632: e014 b.n 800165e + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001634: f7ff fabc bl 8000bb0 + 8001638: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 800163a: e00a b.n 8001652 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 800163c: f7ff fab8 bl 8000bb0 + 8001640: 4602 mov r2, r0 + 8001642: 693b ldr r3, [r7, #16] + 8001644: 1ad3 subs r3, r2, r3 + 8001646: f241 3288 movw r2, #5000 @ 0x1388 + 800164a: 4293 cmp r3, r2 + 800164c: d901 bls.n 8001652 + { + return HAL_TIMEOUT; + 800164e: 2303 movs r3, #3 + 8001650: e08d b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8001652: 4b49 ldr r3, [pc, #292] @ (8001778 ) + 8001654: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001656: f403 7300 and.w r3, r3, #512 @ 0x200 + 800165a: 2b00 cmp r3, #0 + 800165c: d1ee bne.n 800163c + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 800165e: 7ffb ldrb r3, [r7, #31] + 8001660: 2b01 cmp r3, #1 + 8001662: d105 bne.n 8001670 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8001664: 4b44 ldr r3, [pc, #272] @ (8001778 ) + 8001666: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001668: 4a43 ldr r2, [pc, #268] @ (8001778 ) + 800166a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 800166e: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8001670: 687b ldr r3, [r7, #4] + 8001672: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001674: 2b00 cmp r3, #0 + 8001676: d079 beq.n 800176c + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001678: 69bb ldr r3, [r7, #24] + 800167a: 2b0c cmp r3, #12 + 800167c: d056 beq.n 800172c + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 800167e: 687b ldr r3, [r7, #4] + 8001680: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001682: 2b02 cmp r3, #2 + 8001684: d13b bne.n 80016fe + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8001686: 4b3d ldr r3, [pc, #244] @ (800177c ) + 8001688: 2200 movs r2, #0 + 800168a: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800168c: f7ff fa90 bl 8000bb0 + 8001690: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001692: e008 b.n 80016a6 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001694: f7ff fa8c bl 8000bb0 + 8001698: 4602 mov r2, r0 + 800169a: 693b ldr r3, [r7, #16] + 800169c: 1ad3 subs r3, r2, r3 + 800169e: 2b02 cmp r3, #2 + 80016a0: d901 bls.n 80016a6 + { + return HAL_TIMEOUT; + 80016a2: 2303 movs r3, #3 + 80016a4: e063 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80016a6: 4b34 ldr r3, [pc, #208] @ (8001778 ) + 80016a8: 681b ldr r3, [r3, #0] + 80016aa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80016ae: 2b00 cmp r3, #0 + 80016b0: d1f0 bne.n 8001694 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 80016b2: 4b31 ldr r3, [pc, #196] @ (8001778 ) + 80016b4: 689b ldr r3, [r3, #8] + 80016b6: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 80016ba: 687b ldr r3, [r7, #4] + 80016bc: 6a99 ldr r1, [r3, #40] @ 0x28 + 80016be: 687b ldr r3, [r7, #4] + 80016c0: 6adb ldr r3, [r3, #44] @ 0x2c + 80016c2: 4319 orrs r1, r3 + 80016c4: 687b ldr r3, [r7, #4] + 80016c6: 6b1b ldr r3, [r3, #48] @ 0x30 + 80016c8: 430b orrs r3, r1 + 80016ca: 492b ldr r1, [pc, #172] @ (8001778 ) + 80016cc: 4313 orrs r3, r2 + 80016ce: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 80016d0: 4b2a ldr r3, [pc, #168] @ (800177c ) + 80016d2: 2201 movs r2, #1 + 80016d4: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80016d6: f7ff fa6b bl 8000bb0 + 80016da: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 80016dc: e008 b.n 80016f0 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80016de: f7ff fa67 bl 8000bb0 + 80016e2: 4602 mov r2, r0 + 80016e4: 693b ldr r3, [r7, #16] + 80016e6: 1ad3 subs r3, r2, r3 + 80016e8: 2b02 cmp r3, #2 + 80016ea: d901 bls.n 80016f0 + { + return HAL_TIMEOUT; + 80016ec: 2303 movs r3, #3 + 80016ee: e03e b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 80016f0: 4b21 ldr r3, [pc, #132] @ (8001778 ) + 80016f2: 681b ldr r3, [r3, #0] + 80016f4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80016f8: 2b00 cmp r3, #0 + 80016fa: d0f0 beq.n 80016de + 80016fc: e036 b.n 800176c + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80016fe: 4b1f ldr r3, [pc, #124] @ (800177c ) + 8001700: 2200 movs r2, #0 + 8001702: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001704: f7ff fa54 bl 8000bb0 + 8001708: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800170a: e008 b.n 800171e + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800170c: f7ff fa50 bl 8000bb0 + 8001710: 4602 mov r2, r0 + 8001712: 693b ldr r3, [r7, #16] + 8001714: 1ad3 subs r3, r2, r3 + 8001716: 2b02 cmp r3, #2 + 8001718: d901 bls.n 800171e + { + return HAL_TIMEOUT; + 800171a: 2303 movs r3, #3 + 800171c: e027 b.n 800176e + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800171e: 4b16 ldr r3, [pc, #88] @ (8001778 ) + 8001720: 681b ldr r3, [r3, #0] + 8001722: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001726: 2b00 cmp r3, #0 + 8001728: d1f0 bne.n 800170c + 800172a: e01f b.n 800176c + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 800172c: 687b ldr r3, [r7, #4] + 800172e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001730: 2b01 cmp r3, #1 + 8001732: d101 bne.n 8001738 + { + return HAL_ERROR; + 8001734: 2301 movs r3, #1 + 8001736: e01a b.n 800176e + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 8001738: 4b0f ldr r3, [pc, #60] @ (8001778 ) + 800173a: 689b ldr r3, [r3, #8] + 800173c: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 800173e: 697b ldr r3, [r7, #20] + 8001740: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 8001744: 687b ldr r3, [r7, #4] + 8001746: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001748: 429a cmp r2, r3 + 800174a: d10d bne.n 8001768 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 800174c: 697b ldr r3, [r7, #20] + 800174e: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 8001752: 687b ldr r3, [r7, #4] + 8001754: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8001756: 429a cmp r2, r3 + 8001758: d106 bne.n 8001768 + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 800175a: 697b ldr r3, [r7, #20] + 800175c: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 8001760: 687b ldr r3, [r7, #4] + 8001762: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8001764: 429a cmp r2, r3 + 8001766: d001 beq.n 800176c + { + return HAL_ERROR; + 8001768: 2301 movs r3, #1 + 800176a: e000 b.n 800176e + } + } + } + } + + return HAL_OK; + 800176c: 2300 movs r3, #0 +} + 800176e: 4618 mov r0, r3 + 8001770: 3720 adds r7, #32 + 8001772: 46bd mov sp, r7 + 8001774: bd80 pop {r7, pc} + 8001776: bf00 nop + 8001778: 40023800 .word 0x40023800 + 800177c: 42470060 .word 0x42470060 + +08001780 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8001780: b580 push {r7, lr} + 8001782: b084 sub sp, #16 + 8001784: af00 add r7, sp, #0 + 8001786: 6078 str r0, [r7, #4] + 8001788: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 800178a: 687b ldr r3, [r7, #4] + 800178c: 2b00 cmp r3, #0 + 800178e: d101 bne.n 8001794 + { + return HAL_ERROR; + 8001790: 2301 movs r3, #1 + 8001792: e11a b.n 80019ca + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8001794: 4b8f ldr r3, [pc, #572] @ (80019d4 ) + 8001796: 681b ldr r3, [r3, #0] + 8001798: f003 0301 and.w r3, r3, #1 + 800179c: 683a ldr r2, [r7, #0] + 800179e: 429a cmp r2, r3 + 80017a0: d919 bls.n 80017d6 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 80017a2: 683b ldr r3, [r7, #0] + 80017a4: 2b01 cmp r3, #1 + 80017a6: d105 bne.n 80017b4 + 80017a8: 4b8a ldr r3, [pc, #552] @ (80019d4 ) + 80017aa: 681b ldr r3, [r3, #0] + 80017ac: 4a89 ldr r2, [pc, #548] @ (80019d4 ) + 80017ae: f043 0304 orr.w r3, r3, #4 + 80017b2: 6013 str r3, [r2, #0] + 80017b4: 4b87 ldr r3, [pc, #540] @ (80019d4 ) + 80017b6: 681b ldr r3, [r3, #0] + 80017b8: f023 0201 bic.w r2, r3, #1 + 80017bc: 4985 ldr r1, [pc, #532] @ (80019d4 ) + 80017be: 683b ldr r3, [r7, #0] + 80017c0: 4313 orrs r3, r2 + 80017c2: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 80017c4: 4b83 ldr r3, [pc, #524] @ (80019d4 ) + 80017c6: 681b ldr r3, [r3, #0] + 80017c8: f003 0301 and.w r3, r3, #1 + 80017cc: 683a ldr r2, [r7, #0] + 80017ce: 429a cmp r2, r3 + 80017d0: d001 beq.n 80017d6 + { + return HAL_ERROR; + 80017d2: 2301 movs r3, #1 + 80017d4: e0f9 b.n 80019ca + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 80017d6: 687b ldr r3, [r7, #4] + 80017d8: 681b ldr r3, [r3, #0] + 80017da: f003 0302 and.w r3, r3, #2 + 80017de: 2b00 cmp r3, #0 + 80017e0: d008 beq.n 80017f4 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 80017e2: 4b7d ldr r3, [pc, #500] @ (80019d8 ) + 80017e4: 689b ldr r3, [r3, #8] + 80017e6: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 80017ea: 687b ldr r3, [r7, #4] + 80017ec: 689b ldr r3, [r3, #8] + 80017ee: 497a ldr r1, [pc, #488] @ (80019d8 ) + 80017f0: 4313 orrs r3, r2 + 80017f2: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 80017f4: 687b ldr r3, [r7, #4] + 80017f6: 681b ldr r3, [r3, #0] + 80017f8: f003 0301 and.w r3, r3, #1 + 80017fc: 2b00 cmp r3, #0 + 80017fe: f000 808e beq.w 800191e + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001802: 687b ldr r3, [r7, #4] + 8001804: 685b ldr r3, [r3, #4] + 8001806: 2b02 cmp r3, #2 + 8001808: d107 bne.n 800181a + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800180a: 4b73 ldr r3, [pc, #460] @ (80019d8 ) + 800180c: 681b ldr r3, [r3, #0] + 800180e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001812: 2b00 cmp r3, #0 + 8001814: d121 bne.n 800185a + { + return HAL_ERROR; + 8001816: 2301 movs r3, #1 + 8001818: e0d7 b.n 80019ca + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800181a: 687b ldr r3, [r7, #4] + 800181c: 685b ldr r3, [r3, #4] + 800181e: 2b03 cmp r3, #3 + 8001820: d107 bne.n 8001832 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001822: 4b6d ldr r3, [pc, #436] @ (80019d8 ) + 8001824: 681b ldr r3, [r3, #0] + 8001826: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800182a: 2b00 cmp r3, #0 + 800182c: d115 bne.n 800185a + { + return HAL_ERROR; + 800182e: 2301 movs r3, #1 + 8001830: e0cb b.n 80019ca + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001832: 687b ldr r3, [r7, #4] + 8001834: 685b ldr r3, [r3, #4] + 8001836: 2b01 cmp r3, #1 + 8001838: d107 bne.n 800184a + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800183a: 4b67 ldr r3, [pc, #412] @ (80019d8 ) + 800183c: 681b ldr r3, [r3, #0] + 800183e: f003 0302 and.w r3, r3, #2 + 8001842: 2b00 cmp r3, #0 + 8001844: d109 bne.n 800185a + { + return HAL_ERROR; + 8001846: 2301 movs r3, #1 + 8001848: e0bf b.n 80019ca + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800184a: 4b63 ldr r3, [pc, #396] @ (80019d8 ) + 800184c: 681b ldr r3, [r3, #0] + 800184e: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001852: 2b00 cmp r3, #0 + 8001854: d101 bne.n 800185a + { + return HAL_ERROR; + 8001856: 2301 movs r3, #1 + 8001858: e0b7 b.n 80019ca + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 800185a: 4b5f ldr r3, [pc, #380] @ (80019d8 ) + 800185c: 689b ldr r3, [r3, #8] + 800185e: f023 0203 bic.w r2, r3, #3 + 8001862: 687b ldr r3, [r7, #4] + 8001864: 685b ldr r3, [r3, #4] + 8001866: 495c ldr r1, [pc, #368] @ (80019d8 ) + 8001868: 4313 orrs r3, r2 + 800186a: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800186c: f7ff f9a0 bl 8000bb0 + 8001870: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001872: 687b ldr r3, [r7, #4] + 8001874: 685b ldr r3, [r3, #4] + 8001876: 2b02 cmp r3, #2 + 8001878: d112 bne.n 80018a0 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 800187a: e00a b.n 8001892 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 800187c: f7ff f998 bl 8000bb0 + 8001880: 4602 mov r2, r0 + 8001882: 68fb ldr r3, [r7, #12] + 8001884: 1ad3 subs r3, r2, r3 + 8001886: f241 3288 movw r2, #5000 @ 0x1388 + 800188a: 4293 cmp r3, r2 + 800188c: d901 bls.n 8001892 + { + return HAL_TIMEOUT; + 800188e: 2303 movs r3, #3 + 8001890: e09b b.n 80019ca + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001892: 4b51 ldr r3, [pc, #324] @ (80019d8 ) + 8001894: 689b ldr r3, [r3, #8] + 8001896: f003 030c and.w r3, r3, #12 + 800189a: 2b08 cmp r3, #8 + 800189c: d1ee bne.n 800187c + 800189e: e03e b.n 800191e + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80018a0: 687b ldr r3, [r7, #4] + 80018a2: 685b ldr r3, [r3, #4] + 80018a4: 2b03 cmp r3, #3 + 80018a6: d112 bne.n 80018ce + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80018a8: e00a b.n 80018c0 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80018aa: f7ff f981 bl 8000bb0 + 80018ae: 4602 mov r2, r0 + 80018b0: 68fb ldr r3, [r7, #12] + 80018b2: 1ad3 subs r3, r2, r3 + 80018b4: f241 3288 movw r2, #5000 @ 0x1388 + 80018b8: 4293 cmp r3, r2 + 80018ba: d901 bls.n 80018c0 + { + return HAL_TIMEOUT; + 80018bc: 2303 movs r3, #3 + 80018be: e084 b.n 80019ca + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80018c0: 4b45 ldr r3, [pc, #276] @ (80019d8 ) + 80018c2: 689b ldr r3, [r3, #8] + 80018c4: f003 030c and.w r3, r3, #12 + 80018c8: 2b0c cmp r3, #12 + 80018ca: d1ee bne.n 80018aa + 80018cc: e027 b.n 800191e + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 80018ce: 687b ldr r3, [r7, #4] + 80018d0: 685b ldr r3, [r3, #4] + 80018d2: 2b01 cmp r3, #1 + 80018d4: d11d bne.n 8001912 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 80018d6: e00a b.n 80018ee + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80018d8: f7ff f96a bl 8000bb0 + 80018dc: 4602 mov r2, r0 + 80018de: 68fb ldr r3, [r7, #12] + 80018e0: 1ad3 subs r3, r2, r3 + 80018e2: f241 3288 movw r2, #5000 @ 0x1388 + 80018e6: 4293 cmp r3, r2 + 80018e8: d901 bls.n 80018ee + { + return HAL_TIMEOUT; + 80018ea: 2303 movs r3, #3 + 80018ec: e06d b.n 80019ca + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 80018ee: 4b3a ldr r3, [pc, #232] @ (80019d8 ) + 80018f0: 689b ldr r3, [r3, #8] + 80018f2: f003 030c and.w r3, r3, #12 + 80018f6: 2b04 cmp r3, #4 + 80018f8: d1ee bne.n 80018d8 + 80018fa: e010 b.n 800191e + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80018fc: f7ff f958 bl 8000bb0 + 8001900: 4602 mov r2, r0 + 8001902: 68fb ldr r3, [r7, #12] + 8001904: 1ad3 subs r3, r2, r3 + 8001906: f241 3288 movw r2, #5000 @ 0x1388 + 800190a: 4293 cmp r3, r2 + 800190c: d901 bls.n 8001912 + { + return HAL_TIMEOUT; + 800190e: 2303 movs r3, #3 + 8001910: e05b b.n 80019ca + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 8001912: 4b31 ldr r3, [pc, #196] @ (80019d8 ) + 8001914: 689b ldr r3, [r3, #8] + 8001916: f003 030c and.w r3, r3, #12 + 800191a: 2b00 cmp r3, #0 + 800191c: d1ee bne.n 80018fc + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 800191e: 4b2d ldr r3, [pc, #180] @ (80019d4 ) + 8001920: 681b ldr r3, [r3, #0] + 8001922: f003 0301 and.w r3, r3, #1 + 8001926: 683a ldr r2, [r7, #0] + 8001928: 429a cmp r2, r3 + 800192a: d219 bcs.n 8001960 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800192c: 683b ldr r3, [r7, #0] + 800192e: 2b01 cmp r3, #1 + 8001930: d105 bne.n 800193e + 8001932: 4b28 ldr r3, [pc, #160] @ (80019d4 ) + 8001934: 681b ldr r3, [r3, #0] + 8001936: 4a27 ldr r2, [pc, #156] @ (80019d4 ) + 8001938: f043 0304 orr.w r3, r3, #4 + 800193c: 6013 str r3, [r2, #0] + 800193e: 4b25 ldr r3, [pc, #148] @ (80019d4 ) + 8001940: 681b ldr r3, [r3, #0] + 8001942: f023 0201 bic.w r2, r3, #1 + 8001946: 4923 ldr r1, [pc, #140] @ (80019d4 ) + 8001948: 683b ldr r3, [r7, #0] + 800194a: 4313 orrs r3, r2 + 800194c: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 800194e: 4b21 ldr r3, [pc, #132] @ (80019d4 ) + 8001950: 681b ldr r3, [r3, #0] + 8001952: f003 0301 and.w r3, r3, #1 + 8001956: 683a ldr r2, [r7, #0] + 8001958: 429a cmp r2, r3 + 800195a: d001 beq.n 8001960 + { + return HAL_ERROR; + 800195c: 2301 movs r3, #1 + 800195e: e034 b.n 80019ca + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001960: 687b ldr r3, [r7, #4] + 8001962: 681b ldr r3, [r3, #0] + 8001964: f003 0304 and.w r3, r3, #4 + 8001968: 2b00 cmp r3, #0 + 800196a: d008 beq.n 800197e + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 800196c: 4b1a ldr r3, [pc, #104] @ (80019d8 ) + 800196e: 689b ldr r3, [r3, #8] + 8001970: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001974: 687b ldr r3, [r7, #4] + 8001976: 68db ldr r3, [r3, #12] + 8001978: 4917 ldr r1, [pc, #92] @ (80019d8 ) + 800197a: 4313 orrs r3, r2 + 800197c: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 800197e: 687b ldr r3, [r7, #4] + 8001980: 681b ldr r3, [r3, #0] + 8001982: f003 0308 and.w r3, r3, #8 + 8001986: 2b00 cmp r3, #0 + 8001988: d009 beq.n 800199e + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 800198a: 4b13 ldr r3, [pc, #76] @ (80019d8 ) + 800198c: 689b ldr r3, [r3, #8] + 800198e: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001992: 687b ldr r3, [r7, #4] + 8001994: 691b ldr r3, [r3, #16] + 8001996: 00db lsls r3, r3, #3 + 8001998: 490f ldr r1, [pc, #60] @ (80019d8 ) + 800199a: 4313 orrs r3, r2 + 800199c: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 800199e: f000 f823 bl 80019e8 + 80019a2: 4602 mov r2, r0 + 80019a4: 4b0c ldr r3, [pc, #48] @ (80019d8 ) + 80019a6: 689b ldr r3, [r3, #8] + 80019a8: 091b lsrs r3, r3, #4 + 80019aa: f003 030f and.w r3, r3, #15 + 80019ae: 490b ldr r1, [pc, #44] @ (80019dc ) + 80019b0: 5ccb ldrb r3, [r1, r3] + 80019b2: fa22 f303 lsr.w r3, r2, r3 + 80019b6: 4a0a ldr r2, [pc, #40] @ (80019e0 ) + 80019b8: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 80019ba: 4b0a ldr r3, [pc, #40] @ (80019e4 ) + 80019bc: 681b ldr r3, [r3, #0] + 80019be: 4618 mov r0, r3 + 80019c0: f7ff f8aa bl 8000b18 + 80019c4: 4603 mov r3, r0 + 80019c6: 72fb strb r3, [r7, #11] + + return status; + 80019c8: 7afb ldrb r3, [r7, #11] +} + 80019ca: 4618 mov r0, r3 + 80019cc: 3710 adds r7, #16 + 80019ce: 46bd mov sp, r7 + 80019d0: bd80 pop {r7, pc} + 80019d2: bf00 nop + 80019d4: 40023c00 .word 0x40023c00 + 80019d8: 40023800 .word 0x40023800 + 80019dc: 08002998 .word 0x08002998 + 80019e0: 20000000 .word 0x20000000 + 80019e4: 20000004 .word 0x20000004 + +080019e8 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 80019e8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 80019ec: b08e sub sp, #56 @ 0x38 + 80019ee: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 80019f0: 4b58 ldr r3, [pc, #352] @ (8001b54 ) + 80019f2: 689b ldr r3, [r3, #8] + 80019f4: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 80019f6: 6afb ldr r3, [r7, #44] @ 0x2c + 80019f8: f003 030c and.w r3, r3, #12 + 80019fc: 2b0c cmp r3, #12 + 80019fe: d00d beq.n 8001a1c + 8001a00: 2b0c cmp r3, #12 + 8001a02: f200 8092 bhi.w 8001b2a + 8001a06: 2b04 cmp r3, #4 + 8001a08: d002 beq.n 8001a10 + 8001a0a: 2b08 cmp r3, #8 + 8001a0c: d003 beq.n 8001a16 + 8001a0e: e08c b.n 8001b2a + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8001a10: 4b51 ldr r3, [pc, #324] @ (8001b58 ) + 8001a12: 633b str r3, [r7, #48] @ 0x30 + break; + 8001a14: e097 b.n 8001b46 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001a16: 4b51 ldr r3, [pc, #324] @ (8001b5c ) + 8001a18: 633b str r3, [r7, #48] @ 0x30 + break; + 8001a1a: e094 b.n 8001b46 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8001a1c: 6afb ldr r3, [r7, #44] @ 0x2c + 8001a1e: 0c9b lsrs r3, r3, #18 + 8001a20: f003 020f and.w r2, r3, #15 + 8001a24: 4b4e ldr r3, [pc, #312] @ (8001b60 ) + 8001a26: 5c9b ldrb r3, [r3, r2] + 8001a28: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8001a2a: 6afb ldr r3, [r7, #44] @ 0x2c + 8001a2c: 0d9b lsrs r3, r3, #22 + 8001a2e: f003 0303 and.w r3, r3, #3 + 8001a32: 3301 adds r3, #1 + 8001a34: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8001a36: 4b47 ldr r3, [pc, #284] @ (8001b54 ) + 8001a38: 689b ldr r3, [r3, #8] + 8001a3a: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001a3e: 2b00 cmp r3, #0 + 8001a40: d021 beq.n 8001a86 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001a42: 6abb ldr r3, [r7, #40] @ 0x28 + 8001a44: 2200 movs r2, #0 + 8001a46: 61bb str r3, [r7, #24] + 8001a48: 61fa str r2, [r7, #28] + 8001a4a: 4b44 ldr r3, [pc, #272] @ (8001b5c ) + 8001a4c: e9d7 8906 ldrd r8, r9, [r7, #24] + 8001a50: 464a mov r2, r9 + 8001a52: fb03 f202 mul.w r2, r3, r2 + 8001a56: 2300 movs r3, #0 + 8001a58: 4644 mov r4, r8 + 8001a5a: fb04 f303 mul.w r3, r4, r3 + 8001a5e: 4413 add r3, r2 + 8001a60: 4a3e ldr r2, [pc, #248] @ (8001b5c ) + 8001a62: 4644 mov r4, r8 + 8001a64: fba4 0102 umull r0, r1, r4, r2 + 8001a68: 440b add r3, r1 + 8001a6a: 4619 mov r1, r3 + 8001a6c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001a6e: 2200 movs r2, #0 + 8001a70: 613b str r3, [r7, #16] + 8001a72: 617a str r2, [r7, #20] + 8001a74: e9d7 2304 ldrd r2, r3, [r7, #16] + 8001a78: f7fe fb80 bl 800017c <__aeabi_uldivmod> + 8001a7c: 4602 mov r2, r0 + 8001a7e: 460b mov r3, r1 + 8001a80: 4613 mov r3, r2 + 8001a82: 637b str r3, [r7, #52] @ 0x34 + 8001a84: e04e b.n 8001b24 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001a86: 6abb ldr r3, [r7, #40] @ 0x28 + 8001a88: 2200 movs r2, #0 + 8001a8a: 469a mov sl, r3 + 8001a8c: 4693 mov fp, r2 + 8001a8e: 4652 mov r2, sl + 8001a90: 465b mov r3, fp + 8001a92: f04f 0000 mov.w r0, #0 + 8001a96: f04f 0100 mov.w r1, #0 + 8001a9a: 0159 lsls r1, r3, #5 + 8001a9c: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001aa0: 0150 lsls r0, r2, #5 + 8001aa2: 4602 mov r2, r0 + 8001aa4: 460b mov r3, r1 + 8001aa6: ebb2 080a subs.w r8, r2, sl + 8001aaa: eb63 090b sbc.w r9, r3, fp + 8001aae: f04f 0200 mov.w r2, #0 + 8001ab2: f04f 0300 mov.w r3, #0 + 8001ab6: ea4f 1389 mov.w r3, r9, lsl #6 + 8001aba: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001abe: ea4f 1288 mov.w r2, r8, lsl #6 + 8001ac2: ebb2 0408 subs.w r4, r2, r8 + 8001ac6: eb63 0509 sbc.w r5, r3, r9 + 8001aca: f04f 0200 mov.w r2, #0 + 8001ace: f04f 0300 mov.w r3, #0 + 8001ad2: 00eb lsls r3, r5, #3 + 8001ad4: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8001ad8: 00e2 lsls r2, r4, #3 + 8001ada: 4614 mov r4, r2 + 8001adc: 461d mov r5, r3 + 8001ade: eb14 030a adds.w r3, r4, sl + 8001ae2: 603b str r3, [r7, #0] + 8001ae4: eb45 030b adc.w r3, r5, fp + 8001ae8: 607b str r3, [r7, #4] + 8001aea: f04f 0200 mov.w r2, #0 + 8001aee: f04f 0300 mov.w r3, #0 + 8001af2: e9d7 4500 ldrd r4, r5, [r7] + 8001af6: 4629 mov r1, r5 + 8001af8: 028b lsls r3, r1, #10 + 8001afa: 4620 mov r0, r4 + 8001afc: 4629 mov r1, r5 + 8001afe: 4604 mov r4, r0 + 8001b00: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8001b04: 4601 mov r1, r0 + 8001b06: 028a lsls r2, r1, #10 + 8001b08: 4610 mov r0, r2 + 8001b0a: 4619 mov r1, r3 + 8001b0c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001b0e: 2200 movs r2, #0 + 8001b10: 60bb str r3, [r7, #8] + 8001b12: 60fa str r2, [r7, #12] + 8001b14: e9d7 2302 ldrd r2, r3, [r7, #8] + 8001b18: f7fe fb30 bl 800017c <__aeabi_uldivmod> + 8001b1c: 4602 mov r2, r0 + 8001b1e: 460b mov r3, r1 + 8001b20: 4613 mov r3, r2 + 8001b22: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 8001b24: 6b7b ldr r3, [r7, #52] @ 0x34 + 8001b26: 633b str r3, [r7, #48] @ 0x30 + break; + 8001b28: e00d b.n 8001b46 + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8001b2a: 4b0a ldr r3, [pc, #40] @ (8001b54 ) + 8001b2c: 685b ldr r3, [r3, #4] + 8001b2e: 0b5b lsrs r3, r3, #13 + 8001b30: f003 0307 and.w r3, r3, #7 + 8001b34: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8001b36: 6a3b ldr r3, [r7, #32] + 8001b38: 3301 adds r3, #1 + 8001b3a: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001b3e: fa02 f303 lsl.w r3, r2, r3 + 8001b42: 633b str r3, [r7, #48] @ 0x30 + break; + 8001b44: bf00 nop + } + } + return sysclockfreq; + 8001b46: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 8001b48: 4618 mov r0, r3 + 8001b4a: 3738 adds r7, #56 @ 0x38 + 8001b4c: 46bd mov sp, r7 + 8001b4e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8001b52: bf00 nop + 8001b54: 40023800 .word 0x40023800 + 8001b58: 00f42400 .word 0x00f42400 + 8001b5c: 016e3600 .word 0x016e3600 + 8001b60: 0800298c .word 0x0800298c + +08001b64 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 8001b64: b480 push {r7} + 8001b66: b087 sub sp, #28 + 8001b68: af00 add r7, sp, #0 + 8001b6a: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8001b6c: 2300 movs r3, #0 + 8001b6e: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 8001b70: 4b29 ldr r3, [pc, #164] @ (8001c18 ) + 8001b72: 689b ldr r3, [r3, #8] + 8001b74: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001b78: 2b00 cmp r3, #0 + 8001b7a: d12c bne.n 8001bd6 + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 8001b7c: 4b26 ldr r3, [pc, #152] @ (8001c18 ) + 8001b7e: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001b80: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001b84: 2b00 cmp r3, #0 + 8001b86: d005 beq.n 8001b94 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001b88: 4b24 ldr r3, [pc, #144] @ (8001c1c ) + 8001b8a: 681b ldr r3, [r3, #0] + 8001b8c: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001b90: 617b str r3, [r7, #20] + 8001b92: e016 b.n 8001bc2 + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001b94: 4b20 ldr r3, [pc, #128] @ (8001c18 ) + 8001b96: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001b98: 4a1f ldr r2, [pc, #124] @ (8001c18 ) + 8001b9a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001b9e: 6253 str r3, [r2, #36] @ 0x24 + 8001ba0: 4b1d ldr r3, [pc, #116] @ (8001c18 ) + 8001ba2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ba4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001ba8: 60fb str r3, [r7, #12] + 8001baa: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001bac: 4b1b ldr r3, [pc, #108] @ (8001c1c ) + 8001bae: 681b ldr r3, [r3, #0] + 8001bb0: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001bb4: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001bb6: 4b18 ldr r3, [pc, #96] @ (8001c18 ) + 8001bb8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001bba: 4a17 ldr r2, [pc, #92] @ (8001c18 ) + 8001bbc: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001bc0: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001bc2: 697b ldr r3, [r7, #20] + 8001bc4: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001bc8: d105 bne.n 8001bd6 + 8001bca: 687b ldr r3, [r7, #4] + 8001bcc: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001bd0: d101 bne.n 8001bd6 + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001bd2: 2301 movs r3, #1 + 8001bd4: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001bd6: 693b ldr r3, [r7, #16] + 8001bd8: 2b01 cmp r3, #1 + 8001bda: d105 bne.n 8001be8 + 8001bdc: 4b10 ldr r3, [pc, #64] @ (8001c20 ) + 8001bde: 681b ldr r3, [r3, #0] + 8001be0: 4a0f ldr r2, [pc, #60] @ (8001c20 ) + 8001be2: f043 0304 orr.w r3, r3, #4 + 8001be6: 6013 str r3, [r2, #0] + 8001be8: 4b0d ldr r3, [pc, #52] @ (8001c20 ) + 8001bea: 681b ldr r3, [r3, #0] + 8001bec: f023 0201 bic.w r2, r3, #1 + 8001bf0: 490b ldr r1, [pc, #44] @ (8001c20 ) + 8001bf2: 693b ldr r3, [r7, #16] + 8001bf4: 4313 orrs r3, r2 + 8001bf6: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001bf8: 4b09 ldr r3, [pc, #36] @ (8001c20 ) + 8001bfa: 681b ldr r3, [r3, #0] + 8001bfc: f003 0301 and.w r3, r3, #1 + 8001c00: 693a ldr r2, [r7, #16] + 8001c02: 429a cmp r2, r3 + 8001c04: d001 beq.n 8001c0a + { + return HAL_ERROR; + 8001c06: 2301 movs r3, #1 + 8001c08: e000 b.n 8001c0c + } + + return HAL_OK; + 8001c0a: 2300 movs r3, #0 +} + 8001c0c: 4618 mov r0, r3 + 8001c0e: 371c adds r7, #28 + 8001c10: 46bd mov sp, r7 + 8001c12: bc80 pop {r7} + 8001c14: 4770 bx lr + 8001c16: bf00 nop + 8001c18: 40023800 .word 0x40023800 + 8001c1c: 40007000 .word 0x40007000 + 8001c20: 40023c00 .word 0x40023c00 + +08001c24 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001c24: b580 push {r7, lr} + 8001c26: b082 sub sp, #8 + 8001c28: af00 add r7, sp, #0 + 8001c2a: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001c2c: 687b ldr r3, [r7, #4] + 8001c2e: 2b00 cmp r3, #0 + 8001c30: d101 bne.n 8001c36 + { + return HAL_ERROR; + 8001c32: 2301 movs r3, #1 + 8001c34: e07b b.n 8001d2e + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001c36: 687b ldr r3, [r7, #4] + 8001c38: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001c3a: 2b00 cmp r3, #0 + 8001c3c: d108 bne.n 8001c50 + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001c3e: 687b ldr r3, [r7, #4] + 8001c40: 685b ldr r3, [r3, #4] + 8001c42: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001c46: d009 beq.n 8001c5c + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001c48: 687b ldr r3, [r7, #4] + 8001c4a: 2200 movs r2, #0 + 8001c4c: 61da str r2, [r3, #28] + 8001c4e: e005 b.n 8001c5c + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001c50: 687b ldr r3, [r7, #4] + 8001c52: 2200 movs r2, #0 + 8001c54: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001c56: 687b ldr r3, [r7, #4] + 8001c58: 2200 movs r2, #0 + 8001c5a: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001c5c: 687b ldr r3, [r7, #4] + 8001c5e: 2200 movs r2, #0 + 8001c60: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001c62: 687b ldr r3, [r7, #4] + 8001c64: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001c68: b2db uxtb r3, r3 + 8001c6a: 2b00 cmp r3, #0 + 8001c6c: d106 bne.n 8001c7c + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001c6e: 687b ldr r3, [r7, #4] + 8001c70: 2200 movs r2, #0 + 8001c72: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001c76: 6878 ldr r0, [r7, #4] + 8001c78: f7fe fe1e bl 80008b8 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001c7c: 687b ldr r3, [r7, #4] + 8001c7e: 2202 movs r2, #2 + 8001c80: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001c84: 687b ldr r3, [r7, #4] + 8001c86: 681b ldr r3, [r3, #0] + 8001c88: 681a ldr r2, [r3, #0] + 8001c8a: 687b ldr r3, [r7, #4] + 8001c8c: 681b ldr r3, [r3, #0] + 8001c8e: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001c92: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001c94: 687b ldr r3, [r7, #4] + 8001c96: 685b ldr r3, [r3, #4] + 8001c98: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001c9c: 687b ldr r3, [r7, #4] + 8001c9e: 689b ldr r3, [r3, #8] + 8001ca0: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001ca4: 431a orrs r2, r3 + 8001ca6: 687b ldr r3, [r7, #4] + 8001ca8: 68db ldr r3, [r3, #12] + 8001caa: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001cae: 431a orrs r2, r3 + 8001cb0: 687b ldr r3, [r7, #4] + 8001cb2: 691b ldr r3, [r3, #16] + 8001cb4: f003 0302 and.w r3, r3, #2 + 8001cb8: 431a orrs r2, r3 + 8001cba: 687b ldr r3, [r7, #4] + 8001cbc: 695b ldr r3, [r3, #20] + 8001cbe: f003 0301 and.w r3, r3, #1 + 8001cc2: 431a orrs r2, r3 + 8001cc4: 687b ldr r3, [r7, #4] + 8001cc6: 699b ldr r3, [r3, #24] + 8001cc8: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001ccc: 431a orrs r2, r3 + 8001cce: 687b ldr r3, [r7, #4] + 8001cd0: 69db ldr r3, [r3, #28] + 8001cd2: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001cd6: 431a orrs r2, r3 + 8001cd8: 687b ldr r3, [r7, #4] + 8001cda: 6a1b ldr r3, [r3, #32] + 8001cdc: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001ce0: ea42 0103 orr.w r1, r2, r3 + 8001ce4: 687b ldr r3, [r7, #4] + 8001ce6: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001ce8: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001cec: 687b ldr r3, [r7, #4] + 8001cee: 681b ldr r3, [r3, #0] + 8001cf0: 430a orrs r2, r1 + 8001cf2: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8001cf4: 687b ldr r3, [r7, #4] + 8001cf6: 699b ldr r3, [r3, #24] + 8001cf8: 0c1b lsrs r3, r3, #16 + 8001cfa: f003 0104 and.w r1, r3, #4 + 8001cfe: 687b ldr r3, [r7, #4] + 8001d00: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001d02: f003 0210 and.w r2, r3, #16 + 8001d06: 687b ldr r3, [r7, #4] + 8001d08: 681b ldr r3, [r3, #0] + 8001d0a: 430a orrs r2, r1 + 8001d0c: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8001d0e: 687b ldr r3, [r7, #4] + 8001d10: 681b ldr r3, [r3, #0] + 8001d12: 69da ldr r2, [r3, #28] + 8001d14: 687b ldr r3, [r7, #4] + 8001d16: 681b ldr r3, [r3, #0] + 8001d18: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001d1c: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001d1e: 687b ldr r3, [r7, #4] + 8001d20: 2200 movs r2, #0 + 8001d22: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8001d24: 687b ldr r3, [r7, #4] + 8001d26: 2201 movs r2, #1 + 8001d28: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8001d2c: 2300 movs r3, #0 +} + 8001d2e: 4618 mov r0, r3 + 8001d30: 3708 adds r7, #8 + 8001d32: 46bd mov sp, r7 + 8001d34: bd80 pop {r7, pc} + +08001d36 : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8001d36: b580 push {r7, lr} + 8001d38: b088 sub sp, #32 + 8001d3a: af00 add r7, sp, #0 + 8001d3c: 60f8 str r0, [r7, #12] + 8001d3e: 60b9 str r1, [r7, #8] + 8001d40: 603b str r3, [r7, #0] + 8001d42: 4613 mov r3, r2 + 8001d44: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001d46: f7fe ff33 bl 8000bb0 + 8001d4a: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8001d4c: 88fb ldrh r3, [r7, #6] + 8001d4e: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8001d50: 68fb ldr r3, [r7, #12] + 8001d52: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001d56: b2db uxtb r3, r3 + 8001d58: 2b01 cmp r3, #1 + 8001d5a: d001 beq.n 8001d60 + { + return HAL_BUSY; + 8001d5c: 2302 movs r3, #2 + 8001d5e: e12a b.n 8001fb6 + } + + if ((pData == NULL) || (Size == 0U)) + 8001d60: 68bb ldr r3, [r7, #8] + 8001d62: 2b00 cmp r3, #0 + 8001d64: d002 beq.n 8001d6c + 8001d66: 88fb ldrh r3, [r7, #6] + 8001d68: 2b00 cmp r3, #0 + 8001d6a: d101 bne.n 8001d70 + { + return HAL_ERROR; + 8001d6c: 2301 movs r3, #1 + 8001d6e: e122 b.n 8001fb6 + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 8001d70: 68fb ldr r3, [r7, #12] + 8001d72: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001d76: 2b01 cmp r3, #1 + 8001d78: d101 bne.n 8001d7e + 8001d7a: 2302 movs r3, #2 + 8001d7c: e11b b.n 8001fb6 + 8001d7e: 68fb ldr r3, [r7, #12] + 8001d80: 2201 movs r2, #1 + 8001d82: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8001d86: 68fb ldr r3, [r7, #12] + 8001d88: 2203 movs r2, #3 + 8001d8a: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001d8e: 68fb ldr r3, [r7, #12] + 8001d90: 2200 movs r2, #0 + 8001d92: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8001d94: 68fb ldr r3, [r7, #12] + 8001d96: 68ba ldr r2, [r7, #8] + 8001d98: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 8001d9a: 68fb ldr r3, [r7, #12] + 8001d9c: 88fa ldrh r2, [r7, #6] + 8001d9e: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8001da0: 68fb ldr r3, [r7, #12] + 8001da2: 88fa ldrh r2, [r7, #6] + 8001da4: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8001da6: 68fb ldr r3, [r7, #12] + 8001da8: 2200 movs r2, #0 + 8001daa: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 8001dac: 68fb ldr r3, [r7, #12] + 8001dae: 2200 movs r2, #0 + 8001db0: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8001db2: 68fb ldr r3, [r7, #12] + 8001db4: 2200 movs r2, #0 + 8001db6: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 8001db8: 68fb ldr r3, [r7, #12] + 8001dba: 2200 movs r2, #0 + 8001dbc: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 8001dbe: 68fb ldr r3, [r7, #12] + 8001dc0: 2200 movs r2, #0 + 8001dc2: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8001dc4: 68fb ldr r3, [r7, #12] + 8001dc6: 689b ldr r3, [r3, #8] + 8001dc8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001dcc: d10f bne.n 8001dee + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 8001dce: 68fb ldr r3, [r7, #12] + 8001dd0: 681b ldr r3, [r3, #0] + 8001dd2: 681a ldr r2, [r3, #0] + 8001dd4: 68fb ldr r3, [r7, #12] + 8001dd6: 681b ldr r3, [r3, #0] + 8001dd8: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001ddc: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 8001dde: 68fb ldr r3, [r7, #12] + 8001de0: 681b ldr r3, [r3, #0] + 8001de2: 681a ldr r2, [r3, #0] + 8001de4: 68fb ldr r3, [r7, #12] + 8001de6: 681b ldr r3, [r3, #0] + 8001de8: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8001dec: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8001dee: 68fb ldr r3, [r7, #12] + 8001df0: 681b ldr r3, [r3, #0] + 8001df2: 681b ldr r3, [r3, #0] + 8001df4: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001df8: 2b40 cmp r3, #64 @ 0x40 + 8001dfa: d007 beq.n 8001e0c + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8001dfc: 68fb ldr r3, [r7, #12] + 8001dfe: 681b ldr r3, [r3, #0] + 8001e00: 681a ldr r2, [r3, #0] + 8001e02: 68fb ldr r3, [r7, #12] + 8001e04: 681b ldr r3, [r3, #0] + 8001e06: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8001e0a: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 8001e0c: 68fb ldr r3, [r7, #12] + 8001e0e: 68db ldr r3, [r3, #12] + 8001e10: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8001e14: d152 bne.n 8001ebc + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001e16: 68fb ldr r3, [r7, #12] + 8001e18: 685b ldr r3, [r3, #4] + 8001e1a: 2b00 cmp r3, #0 + 8001e1c: d002 beq.n 8001e24 + 8001e1e: 8b7b ldrh r3, [r7, #26] + 8001e20: 2b01 cmp r3, #1 + 8001e22: d145 bne.n 8001eb0 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001e24: 68fb ldr r3, [r7, #12] + 8001e26: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001e28: 881a ldrh r2, [r3, #0] + 8001e2a: 68fb ldr r3, [r7, #12] + 8001e2c: 681b ldr r3, [r3, #0] + 8001e2e: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001e30: 68fb ldr r3, [r7, #12] + 8001e32: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001e34: 1c9a adds r2, r3, #2 + 8001e36: 68fb ldr r3, [r7, #12] + 8001e38: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001e3a: 68fb ldr r3, [r7, #12] + 8001e3c: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001e3e: b29b uxth r3, r3 + 8001e40: 3b01 subs r3, #1 + 8001e42: b29a uxth r2, r3 + 8001e44: 68fb ldr r3, [r7, #12] + 8001e46: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 8001e48: e032 b.n 8001eb0 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001e4a: 68fb ldr r3, [r7, #12] + 8001e4c: 681b ldr r3, [r3, #0] + 8001e4e: 689b ldr r3, [r3, #8] + 8001e50: f003 0302 and.w r3, r3, #2 + 8001e54: 2b02 cmp r3, #2 + 8001e56: d112 bne.n 8001e7e + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8001e58: 68fb ldr r3, [r7, #12] + 8001e5a: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001e5c: 881a ldrh r2, [r3, #0] + 8001e5e: 68fb ldr r3, [r7, #12] + 8001e60: 681b ldr r3, [r3, #0] + 8001e62: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8001e64: 68fb ldr r3, [r7, #12] + 8001e66: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001e68: 1c9a adds r2, r3, #2 + 8001e6a: 68fb ldr r3, [r7, #12] + 8001e6c: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001e6e: 68fb ldr r3, [r7, #12] + 8001e70: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001e72: b29b uxth r3, r3 + 8001e74: 3b01 subs r3, #1 + 8001e76: b29a uxth r2, r3 + 8001e78: 68fb ldr r3, [r7, #12] + 8001e7a: 86da strh r2, [r3, #54] @ 0x36 + 8001e7c: e018 b.n 8001eb0 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001e7e: f7fe fe97 bl 8000bb0 + 8001e82: 4602 mov r2, r0 + 8001e84: 69fb ldr r3, [r7, #28] + 8001e86: 1ad3 subs r3, r2, r3 + 8001e88: 683a ldr r2, [r7, #0] + 8001e8a: 429a cmp r2, r3 + 8001e8c: d803 bhi.n 8001e96 + 8001e8e: 683b ldr r3, [r7, #0] + 8001e90: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001e94: d102 bne.n 8001e9c + 8001e96: 683b ldr r3, [r7, #0] + 8001e98: 2b00 cmp r3, #0 + 8001e9a: d109 bne.n 8001eb0 + { + hspi->State = HAL_SPI_STATE_READY; + 8001e9c: 68fb ldr r3, [r7, #12] + 8001e9e: 2201 movs r2, #1 + 8001ea0: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001ea4: 68fb ldr r3, [r7, #12] + 8001ea6: 2200 movs r2, #0 + 8001ea8: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001eac: 2303 movs r3, #3 + 8001eae: e082 b.n 8001fb6 + while (hspi->TxXferCount > 0U) + 8001eb0: 68fb ldr r3, [r7, #12] + 8001eb2: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001eb4: b29b uxth r3, r3 + 8001eb6: 2b00 cmp r3, #0 + 8001eb8: d1c7 bne.n 8001e4a + 8001eba: e053 b.n 8001f64 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8001ebc: 68fb ldr r3, [r7, #12] + 8001ebe: 685b ldr r3, [r3, #4] + 8001ec0: 2b00 cmp r3, #0 + 8001ec2: d002 beq.n 8001eca + 8001ec4: 8b7b ldrh r3, [r7, #26] + 8001ec6: 2b01 cmp r3, #1 + 8001ec8: d147 bne.n 8001f5a + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001eca: 68fb ldr r3, [r7, #12] + 8001ecc: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001ece: 68fb ldr r3, [r7, #12] + 8001ed0: 681b ldr r3, [r3, #0] + 8001ed2: 330c adds r3, #12 + 8001ed4: 7812 ldrb r2, [r2, #0] + 8001ed6: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001ed8: 68fb ldr r3, [r7, #12] + 8001eda: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001edc: 1c5a adds r2, r3, #1 + 8001ede: 68fb ldr r3, [r7, #12] + 8001ee0: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001ee2: 68fb ldr r3, [r7, #12] + 8001ee4: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001ee6: b29b uxth r3, r3 + 8001ee8: 3b01 subs r3, #1 + 8001eea: b29a uxth r2, r3 + 8001eec: 68fb ldr r3, [r7, #12] + 8001eee: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8001ef0: e033 b.n 8001f5a + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8001ef2: 68fb ldr r3, [r7, #12] + 8001ef4: 681b ldr r3, [r3, #0] + 8001ef6: 689b ldr r3, [r3, #8] + 8001ef8: f003 0302 and.w r3, r3, #2 + 8001efc: 2b02 cmp r3, #2 + 8001efe: d113 bne.n 8001f28 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8001f00: 68fb ldr r3, [r7, #12] + 8001f02: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001f04: 68fb ldr r3, [r7, #12] + 8001f06: 681b ldr r3, [r3, #0] + 8001f08: 330c adds r3, #12 + 8001f0a: 7812 ldrb r2, [r2, #0] + 8001f0c: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8001f0e: 68fb ldr r3, [r7, #12] + 8001f10: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001f12: 1c5a adds r2, r3, #1 + 8001f14: 68fb ldr r3, [r7, #12] + 8001f16: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8001f18: 68fb ldr r3, [r7, #12] + 8001f1a: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001f1c: b29b uxth r3, r3 + 8001f1e: 3b01 subs r3, #1 + 8001f20: b29a uxth r2, r3 + 8001f22: 68fb ldr r3, [r7, #12] + 8001f24: 86da strh r2, [r3, #54] @ 0x36 + 8001f26: e018 b.n 8001f5a + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8001f28: f7fe fe42 bl 8000bb0 + 8001f2c: 4602 mov r2, r0 + 8001f2e: 69fb ldr r3, [r7, #28] + 8001f30: 1ad3 subs r3, r2, r3 + 8001f32: 683a ldr r2, [r7, #0] + 8001f34: 429a cmp r2, r3 + 8001f36: d803 bhi.n 8001f40 + 8001f38: 683b ldr r3, [r7, #0] + 8001f3a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001f3e: d102 bne.n 8001f46 + 8001f40: 683b ldr r3, [r7, #0] + 8001f42: 2b00 cmp r3, #0 + 8001f44: d109 bne.n 8001f5a + { + hspi->State = HAL_SPI_STATE_READY; + 8001f46: 68fb ldr r3, [r7, #12] + 8001f48: 2201 movs r2, #1 + 8001f4a: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8001f4e: 68fb ldr r3, [r7, #12] + 8001f50: 2200 movs r2, #0 + 8001f52: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 8001f56: 2303 movs r3, #3 + 8001f58: e02d b.n 8001fb6 + while (hspi->TxXferCount > 0U) + 8001f5a: 68fb ldr r3, [r7, #12] + 8001f5c: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001f5e: b29b uxth r3, r3 + 8001f60: 2b00 cmp r3, #0 + 8001f62: d1c6 bne.n 8001ef2 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 8001f64: 69fa ldr r2, [r7, #28] + 8001f66: 6839 ldr r1, [r7, #0] + 8001f68: 68f8 ldr r0, [r7, #12] + 8001f6a: f000 f8b1 bl 80020d0 + 8001f6e: 4603 mov r3, r0 + 8001f70: 2b00 cmp r3, #0 + 8001f72: d002 beq.n 8001f7a + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 8001f74: 68fb ldr r3, [r7, #12] + 8001f76: 2220 movs r2, #32 + 8001f78: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 8001f7a: 68fb ldr r3, [r7, #12] + 8001f7c: 689b ldr r3, [r3, #8] + 8001f7e: 2b00 cmp r3, #0 + 8001f80: d10a bne.n 8001f98 + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 8001f82: 2300 movs r3, #0 + 8001f84: 617b str r3, [r7, #20] + 8001f86: 68fb ldr r3, [r7, #12] + 8001f88: 681b ldr r3, [r3, #0] + 8001f8a: 68db ldr r3, [r3, #12] + 8001f8c: 617b str r3, [r7, #20] + 8001f8e: 68fb ldr r3, [r7, #12] + 8001f90: 681b ldr r3, [r3, #0] + 8001f92: 689b ldr r3, [r3, #8] + 8001f94: 617b str r3, [r7, #20] + 8001f96: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 8001f98: 68fb ldr r3, [r7, #12] + 8001f9a: 2201 movs r2, #1 + 8001f9c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8001fa0: 68fb ldr r3, [r7, #12] + 8001fa2: 2200 movs r2, #0 + 8001fa4: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 8001fa8: 68fb ldr r3, [r7, #12] + 8001faa: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001fac: 2b00 cmp r3, #0 + 8001fae: d001 beq.n 8001fb4 + { + return HAL_ERROR; + 8001fb0: 2301 movs r3, #1 + 8001fb2: e000 b.n 8001fb6 + } + else + { + return HAL_OK; + 8001fb4: 2300 movs r3, #0 + } +} + 8001fb6: 4618 mov r0, r3 + 8001fb8: 3720 adds r7, #32 + 8001fba: 46bd mov sp, r7 + 8001fbc: bd80 pop {r7, pc} + ... + +08001fc0 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8001fc0: b580 push {r7, lr} + 8001fc2: b088 sub sp, #32 + 8001fc4: af00 add r7, sp, #0 + 8001fc6: 60f8 str r0, [r7, #12] + 8001fc8: 60b9 str r1, [r7, #8] + 8001fca: 603b str r3, [r7, #0] + 8001fcc: 4613 mov r3, r2 + 8001fce: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 8001fd0: f7fe fdee bl 8000bb0 + 8001fd4: 4602 mov r2, r0 + 8001fd6: 6abb ldr r3, [r7, #40] @ 0x28 + 8001fd8: 1a9b subs r3, r3, r2 + 8001fda: 683a ldr r2, [r7, #0] + 8001fdc: 4413 add r3, r2 + 8001fde: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 8001fe0: f7fe fde6 bl 8000bb0 + 8001fe4: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 8001fe6: 4b39 ldr r3, [pc, #228] @ (80020cc ) + 8001fe8: 681b ldr r3, [r3, #0] + 8001fea: 015b lsls r3, r3, #5 + 8001fec: 0d1b lsrs r3, r3, #20 + 8001fee: 69fa ldr r2, [r7, #28] + 8001ff0: fb02 f303 mul.w r3, r2, r3 + 8001ff4: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8001ff6: e054 b.n 80020a2 + { + if (Timeout != HAL_MAX_DELAY) + 8001ff8: 683b ldr r3, [r7, #0] + 8001ffa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001ffe: d050 beq.n 80020a2 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8002000: f7fe fdd6 bl 8000bb0 + 8002004: 4602 mov r2, r0 + 8002006: 69bb ldr r3, [r7, #24] + 8002008: 1ad3 subs r3, r2, r3 + 800200a: 69fa ldr r2, [r7, #28] + 800200c: 429a cmp r2, r3 + 800200e: d902 bls.n 8002016 + 8002010: 69fb ldr r3, [r7, #28] + 8002012: 2b00 cmp r3, #0 + 8002014: d13d bne.n 8002092 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8002016: 68fb ldr r3, [r7, #12] + 8002018: 681b ldr r3, [r3, #0] + 800201a: 685a ldr r2, [r3, #4] + 800201c: 68fb ldr r3, [r7, #12] + 800201e: 681b ldr r3, [r3, #0] + 8002020: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8002024: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8002026: 68fb ldr r3, [r7, #12] + 8002028: 685b ldr r3, [r3, #4] + 800202a: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 800202e: d111 bne.n 8002054 + 8002030: 68fb ldr r3, [r7, #12] + 8002032: 689b ldr r3, [r3, #8] + 8002034: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8002038: d004 beq.n 8002044 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800203a: 68fb ldr r3, [r7, #12] + 800203c: 689b ldr r3, [r3, #8] + 800203e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8002042: d107 bne.n 8002054 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8002044: 68fb ldr r3, [r7, #12] + 8002046: 681b ldr r3, [r3, #0] + 8002048: 681a ldr r2, [r3, #0] + 800204a: 68fb ldr r3, [r7, #12] + 800204c: 681b ldr r3, [r3, #0] + 800204e: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8002052: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8002054: 68fb ldr r3, [r7, #12] + 8002056: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002058: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 800205c: d10f bne.n 800207e + { + SPI_RESET_CRC(hspi); + 800205e: 68fb ldr r3, [r7, #12] + 8002060: 681b ldr r3, [r3, #0] + 8002062: 681a ldr r2, [r3, #0] + 8002064: 68fb ldr r3, [r7, #12] + 8002066: 681b ldr r3, [r3, #0] + 8002068: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 800206c: 601a str r2, [r3, #0] + 800206e: 68fb ldr r3, [r7, #12] + 8002070: 681b ldr r3, [r3, #0] + 8002072: 681a ldr r2, [r3, #0] + 8002074: 68fb ldr r3, [r7, #12] + 8002076: 681b ldr r3, [r3, #0] + 8002078: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 800207c: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 800207e: 68fb ldr r3, [r7, #12] + 8002080: 2201 movs r2, #1 + 8002082: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8002086: 68fb ldr r3, [r7, #12] + 8002088: 2200 movs r2, #0 + 800208a: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 800208e: 2303 movs r3, #3 + 8002090: e017 b.n 80020c2 + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 8002092: 697b ldr r3, [r7, #20] + 8002094: 2b00 cmp r3, #0 + 8002096: d101 bne.n 800209c + { + tmp_timeout = 0U; + 8002098: 2300 movs r3, #0 + 800209a: 61fb str r3, [r7, #28] + } + count--; + 800209c: 697b ldr r3, [r7, #20] + 800209e: 3b01 subs r3, #1 + 80020a0: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 80020a2: 68fb ldr r3, [r7, #12] + 80020a4: 681b ldr r3, [r3, #0] + 80020a6: 689a ldr r2, [r3, #8] + 80020a8: 68bb ldr r3, [r7, #8] + 80020aa: 4013 ands r3, r2 + 80020ac: 68ba ldr r2, [r7, #8] + 80020ae: 429a cmp r2, r3 + 80020b0: bf0c ite eq + 80020b2: 2301 moveq r3, #1 + 80020b4: 2300 movne r3, #0 + 80020b6: b2db uxtb r3, r3 + 80020b8: 461a mov r2, r3 + 80020ba: 79fb ldrb r3, [r7, #7] + 80020bc: 429a cmp r2, r3 + 80020be: d19b bne.n 8001ff8 + } + } + + return HAL_OK; + 80020c0: 2300 movs r3, #0 +} + 80020c2: 4618 mov r0, r3 + 80020c4: 3720 adds r7, #32 + 80020c6: 46bd mov sp, r7 + 80020c8: bd80 pop {r7, pc} + 80020ca: bf00 nop + 80020cc: 20000000 .word 0x20000000 + +080020d0 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 80020d0: b580 push {r7, lr} + 80020d2: b088 sub sp, #32 + 80020d4: af02 add r7, sp, #8 + 80020d6: 60f8 str r0, [r7, #12] + 80020d8: 60b9 str r1, [r7, #8] + 80020da: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 80020dc: 687b ldr r3, [r7, #4] + 80020de: 9300 str r3, [sp, #0] + 80020e0: 68bb ldr r3, [r7, #8] + 80020e2: 2201 movs r2, #1 + 80020e4: 2102 movs r1, #2 + 80020e6: 68f8 ldr r0, [r7, #12] + 80020e8: f7ff ff6a bl 8001fc0 + 80020ec: 4603 mov r3, r0 + 80020ee: 2b00 cmp r3, #0 + 80020f0: d007 beq.n 8002102 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 80020f2: 68fb ldr r3, [r7, #12] + 80020f4: 6d5b ldr r3, [r3, #84] @ 0x54 + 80020f6: f043 0220 orr.w r2, r3, #32 + 80020fa: 68fb ldr r3, [r7, #12] + 80020fc: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 80020fe: 2303 movs r3, #3 + 8002100: e032 b.n 8002168 + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 8002102: 4b1b ldr r3, [pc, #108] @ (8002170 ) + 8002104: 681b ldr r3, [r3, #0] + 8002106: 4a1b ldr r2, [pc, #108] @ (8002174 ) + 8002108: fba2 2303 umull r2, r3, r2, r3 + 800210c: 0d5b lsrs r3, r3, #21 + 800210e: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8002112: fb02 f303 mul.w r3, r2, r3 + 8002116: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8002118: 68fb ldr r3, [r7, #12] + 800211a: 685b ldr r3, [r3, #4] + 800211c: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002120: d112 bne.n 8002148 + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8002122: 687b ldr r3, [r7, #4] + 8002124: 9300 str r3, [sp, #0] + 8002126: 68bb ldr r3, [r7, #8] + 8002128: 2200 movs r2, #0 + 800212a: 2180 movs r1, #128 @ 0x80 + 800212c: 68f8 ldr r0, [r7, #12] + 800212e: f7ff ff47 bl 8001fc0 + 8002132: 4603 mov r3, r0 + 8002134: 2b00 cmp r3, #0 + 8002136: d016 beq.n 8002166 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002138: 68fb ldr r3, [r7, #12] + 800213a: 6d5b ldr r3, [r3, #84] @ 0x54 + 800213c: f043 0220 orr.w r2, r3, #32 + 8002140: 68fb ldr r3, [r7, #12] + 8002142: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 8002144: 2303 movs r3, #3 + 8002146: e00f b.n 8002168 + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 8002148: 697b ldr r3, [r7, #20] + 800214a: 2b00 cmp r3, #0 + 800214c: d00a beq.n 8002164 + { + break; + } + count--; + 800214e: 697b ldr r3, [r7, #20] + 8002150: 3b01 subs r3, #1 + 8002152: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 8002154: 68fb ldr r3, [r7, #12] + 8002156: 681b ldr r3, [r3, #0] + 8002158: 689b ldr r3, [r3, #8] + 800215a: f003 0380 and.w r3, r3, #128 @ 0x80 + 800215e: 2b80 cmp r3, #128 @ 0x80 + 8002160: d0f2 beq.n 8002148 + 8002162: e000 b.n 8002166 + break; + 8002164: bf00 nop + } + + return HAL_OK; + 8002166: 2300 movs r3, #0 +} + 8002168: 4618 mov r0, r3 + 800216a: 3718 adds r7, #24 + 800216c: 46bd mov sp, r7 + 800216e: bd80 pop {r7, pc} + 8002170: 20000000 .word 0x20000000 + 8002174: 165e9f81 .word 0x165e9f81 + +08002178 : +* Input : command byte to write +* Output : None +* Return : None +*******************************************************************************/ +void writecommand(unsigned char cmdout) +{ + 8002178: b580 push {r7, lr} + 800217a: b082 sub sp, #8 + 800217c: af00 add r7, sp, #0 + 800217e: 4603 mov r3, r0 + 8002180: 71fb strb r3, [r7, #7] + + //HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); // HAL_ERROR + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1 + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN << 16 ;// D/nC = 0 commande + 8002182: 4b0a ldr r3, [pc, #40] @ (80021ac ) + 8002184: f44f 2280 mov.w r2, #262144 @ 0x40000 + 8002188: 619a str r2, [r3, #24] + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0 + 800218a: 4b08 ldr r3, [pc, #32] @ (80021ac ) + 800218c: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8002190: 619a str r2, [r3, #24] + HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); // + 8002192: 1df9 adds r1, r7, #7 + 8002194: 2364 movs r3, #100 @ 0x64 + 8002196: 2201 movs r2, #1 + 8002198: 4805 ldr r0, [pc, #20] @ (80021b0 ) + 800219a: f7ff fdcc bl 8001d36 + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + 800219e: 4b03 ldr r3, [pc, #12] @ (80021ac ) + 80021a0: 2202 movs r2, #2 + 80021a2: 619a str r2, [r3, #24] + +} + 80021a4: bf00 nop + 80021a6: 3708 adds r7, #8 + 80021a8: 46bd mov sp, r7 + 80021aa: bd80 pop {r7, pc} + 80021ac: 40020800 .word 0x40020800 + 80021b0: 20000078 .word 0x20000078 + +080021b4 : +* Input : data byte to write +* Output : None +* Return : None +*******************************************************************************/ +void writedata(unsigned char dataout) +{ + 80021b4: b580 push {r7, lr} + 80021b6: b082 sub sp, #8 + 80021b8: af00 add r7, sp, #0 + 80021ba: 4603 mov r3, r0 + 80021bc: 71fb strb r3, [r7, #7] + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1 + + + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + 80021be: 4b0a ldr r3, [pc, #40] @ (80021e8 ) + 80021c0: 2204 movs r2, #4 + 80021c2: 619a str r2, [r3, #24] + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0 + 80021c4: 4b08 ldr r3, [pc, #32] @ (80021e8 ) + 80021c6: f44f 3200 mov.w r2, #131072 @ 0x20000 + 80021ca: 619a str r2, [r3, #24] + HAL_SPI_Transmit(&hspi1, &dataout, 1, 100); // + 80021cc: 1df9 adds r1, r7, #7 + 80021ce: 2364 movs r3, #100 @ 0x64 + 80021d0: 2201 movs r2, #1 + 80021d2: 4806 ldr r0, [pc, #24] @ (80021ec ) + 80021d4: f7ff fdaf bl 8001d36 + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + 80021d8: 4b03 ldr r3, [pc, #12] @ (80021e8 ) + 80021da: 2202 movs r2, #2 + 80021dc: 619a str r2, [r3, #24] + +} + 80021de: bf00 nop + 80021e0: 3708 adds r7, #8 + 80021e2: 46bd mov sp, r7 + 80021e4: bd80 pop {r7, pc} + 80021e6: bf00 nop + 80021e8: 40020800 .word 0x40020800 + 80021ec: 20000078 .word 0x20000078 + +080021f0 : +* Input : addr = pointer on command byte array +* Output : None +* Return : None +*******************************************************************************/ +void commandList(const uint8_t *addr) +{ + 80021f0: b580 push {r7, lr} + 80021f2: b084 sub sp, #16 + 80021f4: af00 add r7, sp, #0 + 80021f6: 6078 str r0, [r7, #4] + uint8_t numCommands, numArgs; + uint16_t ms; + + numCommands = pgm_read_byte(addr++); // Number of commands to follow + 80021f8: 687b ldr r3, [r7, #4] + 80021fa: 1c5a adds r2, r3, #1 + 80021fc: 607a str r2, [r7, #4] + 80021fe: 781b ldrb r3, [r3, #0] + 8002200: 73fb strb r3, [r7, #15] + while(numCommands--) + 8002202: e033 b.n 800226c + { // For each command... + writecommand(pgm_read_byte(addr++)); // Read, issue command + 8002204: 687b ldr r3, [r7, #4] + 8002206: 1c5a adds r2, r3, #1 + 8002208: 607a str r2, [r7, #4] + 800220a: 781b ldrb r3, [r3, #0] + 800220c: 4618 mov r0, r3 + 800220e: f7ff ffb3 bl 8002178 + numArgs = pgm_read_byte(addr++); // Number of args to follow + 8002212: 687b ldr r3, [r7, #4] + 8002214: 1c5a adds r2, r3, #1 + 8002216: 607a str r2, [r7, #4] + 8002218: 781b ldrb r3, [r3, #0] + 800221a: 73bb strb r3, [r7, #14] + ms = numArgs & DELAY; // If hibit set, delay follows args + 800221c: 7bbb ldrb r3, [r7, #14] + 800221e: b29b uxth r3, r3 + 8002220: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002224: 81bb strh r3, [r7, #12] + numArgs &= ~DELAY; // Mask out delay bit + 8002226: 7bbb ldrb r3, [r7, #14] + 8002228: f003 037f and.w r3, r3, #127 @ 0x7f + 800222c: 73bb strb r3, [r7, #14] + while(numArgs--) { // For each argument... + 800222e: e006 b.n 800223e + writedata(pgm_read_byte(addr++)); // Read, issue argument + 8002230: 687b ldr r3, [r7, #4] + 8002232: 1c5a adds r2, r3, #1 + 8002234: 607a str r2, [r7, #4] + 8002236: 781b ldrb r3, [r3, #0] + 8002238: 4618 mov r0, r3 + 800223a: f7ff ffbb bl 80021b4 + while(numArgs--) { // For each argument... + 800223e: 7bbb ldrb r3, [r7, #14] + 8002240: 1e5a subs r2, r3, #1 + 8002242: 73ba strb r2, [r7, #14] + 8002244: 2b00 cmp r3, #0 + 8002246: d1f3 bne.n 8002230 + } + + if(ms) { + 8002248: 89bb ldrh r3, [r7, #12] + 800224a: 2b00 cmp r3, #0 + 800224c: d00e beq.n 800226c + ms = pgm_read_byte(addr++); // Read post-command delay time (ms) + 800224e: 687b ldr r3, [r7, #4] + 8002250: 1c5a adds r2, r3, #1 + 8002252: 607a str r2, [r7, #4] + 8002254: 781b ldrb r3, [r3, #0] + 8002256: 81bb strh r3, [r7, #12] + if(ms == 255) ms = 500; // If 255, delay for 500 ms + 8002258: 89bb ldrh r3, [r7, #12] + 800225a: 2bff cmp r3, #255 @ 0xff + 800225c: d102 bne.n 8002264 + 800225e: f44f 73fa mov.w r3, #500 @ 0x1f4 + 8002262: 81bb strh r3, [r7, #12] + HAL_Delay(500); + 8002264: f44f 70fa mov.w r0, #500 @ 0x1f4 + 8002268: f7fe fcac bl 8000bc4 + while(numCommands--) + 800226c: 7bfb ldrb r3, [r7, #15] + 800226e: 1e5a subs r2, r3, #1 + 8002270: 73fa strb r2, [r7, #15] + 8002272: 2b00 cmp r3, #0 + 8002274: d1c6 bne.n 8002204 + } + } +} + 8002276: bf00 nop + 8002278: bf00 nop + 800227a: 3710 adds r7, #16 + 800227c: 46bd mov sp, r7 + 800227e: bd80 pop {r7, pc} + +08002280 : +* : y2 vertical position = y1 to ST7735_TFTHEIGHT-1-y1 +* Output : None +* Return : None +*******************************************************************************/ +void setAddrWindow(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1) +{ + 8002280: b590 push {r4, r7, lr} + 8002282: b083 sub sp, #12 + 8002284: af00 add r7, sp, #0 + 8002286: 4604 mov r4, r0 + 8002288: 4608 mov r0, r1 + 800228a: 4611 mov r1, r2 + 800228c: 461a mov r2, r3 + 800228e: 4623 mov r3, r4 + 8002290: 71fb strb r3, [r7, #7] + 8002292: 4603 mov r3, r0 + 8002294: 71bb strb r3, [r7, #6] + 8002296: 460b mov r3, r1 + 8002298: 717b strb r3, [r7, #5] + 800229a: 4613 mov r3, r2 + 800229c: 713b strb r3, [r7, #4] + + writecommand(ST7735_CASET); // Column addr set + 800229e: 202a movs r0, #42 @ 0x2a + 80022a0: f7ff ff6a bl 8002178 + writedata(0x00); + 80022a4: 2000 movs r0, #0 + 80022a6: f7ff ff85 bl 80021b4 + writedata(x0); // XSTART + 80022aa: 79fb ldrb r3, [r7, #7] + 80022ac: 4618 mov r0, r3 + 80022ae: f7ff ff81 bl 80021b4 + writedata(0x00); + 80022b2: 2000 movs r0, #0 + 80022b4: f7ff ff7e bl 80021b4 + writedata(x1); // XEND + 80022b8: 797b ldrb r3, [r7, #5] + 80022ba: 4618 mov r0, r3 + 80022bc: f7ff ff7a bl 80021b4 + + writecommand(ST7735_RASET); // Row addr set + 80022c0: 202b movs r0, #43 @ 0x2b + 80022c2: f7ff ff59 bl 8002178 + writedata(0x00); + 80022c6: 2000 movs r0, #0 + 80022c8: f7ff ff74 bl 80021b4 + writedata(y0); // YSTART + 80022cc: 79bb ldrb r3, [r7, #6] + 80022ce: 4618 mov r0, r3 + 80022d0: f7ff ff70 bl 80021b4 + writedata(0x00); + 80022d4: 2000 movs r0, #0 + 80022d6: f7ff ff6d bl 80021b4 + writedata(y1); // YEND + 80022da: 793b ldrb r3, [r7, #4] + 80022dc: 4618 mov r0, r3 + 80022de: f7ff ff69 bl 80021b4 + + writecommand(ST7735_RAMWR); // write to RAM + 80022e2: 202c movs r0, #44 @ 0x2c + 80022e4: f7ff ff48 bl 8002178 +} + 80022e8: bf00 nop + 80022ea: 370c adds r7, #12 + 80022ec: 46bd mov sp, r7 + 80022ee: bd90 pop {r4, r7, pc} + +080022f0 : +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void init_TFT( void) +{ + 80022f0: b580 push {r7, lr} + 80022f2: b082 sub sp, #8 + 80022f4: af02 add r7, sp, #8 + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, 1); // nRESET = 1 + attend_500ms(); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/ + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // DC= 1 + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + 80022f6: 4b1e ldr r3, [pc, #120] @ (8002370 ) + 80022f8: 2204 movs r2, #4 + 80022fa: 619a str r2, [r3, #24] + ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1 + 80022fc: 4b1d ldr r3, [pc, #116] @ (8002374 ) + 80022fe: 2204 movs r2, #4 + 8002300: 619a str r2, [r3, #24] + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0 + 8002302: 4b1b ldr r3, [pc, #108] @ (8002370 ) + 8002304: f44f 3200 mov.w r2, #131072 @ 0x20000 + 8002308: 619a str r2, [r3, #24] + HAL_Delay(500); + 800230a: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800230e: f7fe fc59 bl 8000bc4 + ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN<<16;// nRESET = 0 + 8002312: 4b18 ldr r3, [pc, #96] @ (8002374 ) + 8002314: f44f 2280 mov.w r2, #262144 @ 0x40000 + 8002318: 619a str r2, [r3, #24] + HAL_Delay(500); + 800231a: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800231e: f7fe fc51 bl 8000bc4 + ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1 + 8002322: 4b14 ldr r3, [pc, #80] @ (8002374 ) + 8002324: 2204 movs r2, #4 + 8002326: 619a str r2, [r3, #24] + HAL_Delay(500); + 8002328: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800232c: f7fe fc4a bl 8000bc4 + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + 8002330: 4b0f ldr r3, [pc, #60] @ (8002370 ) + 8002332: 2202 movs r2, #2 + 8002334: 619a str r2, [r3, #24] + + // initialization instruction + commandList(Rcmd1); + 8002336: 4810 ldr r0, [pc, #64] @ (8002378 ) + 8002338: f7ff ff5a bl 80021f0 + commandList(Rcmd2red); + 800233c: 480f ldr r0, [pc, #60] @ (800237c ) + 800233e: f7ff ff57 bl 80021f0 + commandList(Rcmd3); + 8002342: 480f ldr r0, [pc, #60] @ (8002380 ) + 8002344: f7ff ff54 bl 80021f0 + + writecommand(ST7735_MADCTL); + 8002348: 2036 movs r0, #54 @ 0x36 + 800234a: f7ff ff15 bl 8002178 + writedata(0xC0); + 800234e: 20c0 movs r0, #192 @ 0xc0 + 8002350: f7ff ff30 bl 80021b4 + + // all display background is black + fillRect_TFT(0, 0, ST7735_TFTWIDTH, ST7735_TFTHEIGHT_18, ST7735_BLACK); + 8002354: 2300 movs r3, #0 + 8002356: 9300 str r3, [sp, #0] + 8002358: 23a0 movs r3, #160 @ 0xa0 + 800235a: 2280 movs r2, #128 @ 0x80 + 800235c: 2100 movs r1, #0 + 800235e: 2000 movs r0, #0 + 8002360: f000 f856 bl 8002410 + + // display LOGO + displayLogo_TFT(); + 8002364: f000 f998 bl 8002698 +} + 8002368: bf00 nop + 800236a: 46bd mov sp, r7 + 800236c: bd80 pop {r7, pc} + 800236e: bf00 nop + 8002370: 40020800 .word 0x40020800 + 8002374: 40020c00 .word 0x40020c00 + 8002378: 080029a8 .word 0x080029a8 + 800237c: 080029e4 .word 0x080029e4 + 8002380: 080029f4 .word 0x080029f4 + +08002384 : +* : color = 16bits RGB=(565) soit RRRRRGGGGGGGBBBBB +* Output : None +* Return : None +*******************************************************************************/ +void drawPixel_TFT(uint16_t x, uint16_t y, uint16_t color) +{ + 8002384: b580 push {r7, lr} + 8002386: b084 sub sp, #16 + 8002388: af00 add r7, sp, #0 + 800238a: 4603 mov r3, r0 + 800238c: 80fb strh r3, [r7, #6] + 800238e: 460b mov r3, r1 + 8002390: 80bb strh r3, [r7, #4] + 8002392: 4613 mov r3, r2 + 8002394: 807b strh r3, [r7, #2] + uint8_t hi, lo; + + // rudimentary clipping (drawChar w/big text requires this) + if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return; + 8002396: 88fb ldrh r3, [r7, #6] + 8002398: 2b7f cmp r3, #127 @ 0x7f + 800239a: d831 bhi.n 8002400 + 800239c: 88bb ldrh r3, [r7, #4] + 800239e: 2b9f cmp r3, #159 @ 0x9f + 80023a0: d82e bhi.n 8002400 + + setAddrWindow(x, y, x+1, y+1); + 80023a2: 88fb ldrh r3, [r7, #6] + 80023a4: b2d8 uxtb r0, r3 + 80023a6: 88bb ldrh r3, [r7, #4] + 80023a8: b2d9 uxtb r1, r3 + 80023aa: 88fb ldrh r3, [r7, #6] + 80023ac: b2db uxtb r3, r3 + 80023ae: 3301 adds r3, #1 + 80023b0: b2da uxtb r2, r3 + 80023b2: 88bb ldrh r3, [r7, #4] + 80023b4: b2db uxtb r3, r3 + 80023b6: 3301 adds r3, #1 + 80023b8: b2db uxtb r3, r3 + 80023ba: f7ff ff61 bl 8002280 + + hi = color >> 8; + 80023be: 887b ldrh r3, [r7, #2] + 80023c0: 0a1b lsrs r3, r3, #8 + 80023c2: b29b uxth r3, r3 + 80023c4: b2db uxtb r3, r3 + 80023c6: 73fb strb r3, [r7, #15] + lo = color ; + 80023c8: 887b ldrh r3, [r7, #2] + 80023ca: b2db uxtb r3, r3 + 80023cc: 73bb strb r3, [r7, #14] + HAL_SPI_Transmit(&hspi1, &lo, 1, 100); // + + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/ + + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + 80023ce: 4b0e ldr r3, [pc, #56] @ (8002408 ) + 80023d0: 2204 movs r2, #4 + 80023d2: 619a str r2, [r3, #24] + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0 + 80023d4: 4b0c ldr r3, [pc, #48] @ (8002408 ) + 80023d6: f44f 3200 mov.w r2, #131072 @ 0x20000 + 80023da: 619a str r2, [r3, #24] + + HAL_SPI_Transmit(&hspi1, &hi, 1, 100); // + 80023dc: f107 010f add.w r1, r7, #15 + 80023e0: 2364 movs r3, #100 @ 0x64 + 80023e2: 2201 movs r2, #1 + 80023e4: 4809 ldr r0, [pc, #36] @ (800240c ) + 80023e6: f7ff fca6 bl 8001d36 + HAL_SPI_Transmit(&hspi1, &lo, 1, 100); // + 80023ea: f107 010e add.w r1, r7, #14 + 80023ee: 2364 movs r3, #100 @ 0x64 + 80023f0: 2201 movs r2, #1 + 80023f2: 4806 ldr r0, [pc, #24] @ (800240c ) + 80023f4: f7ff fc9f bl 8001d36 + + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + 80023f8: 4b03 ldr r3, [pc, #12] @ (8002408 ) + 80023fa: 2202 movs r2, #2 + 80023fc: 619a str r2, [r3, #24] + 80023fe: e000 b.n 8002402 + if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return; + 8002400: bf00 nop +} + 8002402: 3710 adds r7, #16 + 8002404: 46bd mov sp, r7 + 8002406: bd80 pop {r7, pc} + 8002408: 40020800 .word 0x40020800 + 800240c: 20000078 .word 0x20000078 + +08002410 : +* : color = 16bits RGB(565) soit RRRRRGGGGGGGBBBBB +* Output : None +* Return : None +*******************************************************************************/ +void fillRect_TFT(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color) +{ + 8002410: b590 push {r4, r7, lr} + 8002412: b085 sub sp, #20 + 8002414: af00 add r7, sp, #0 + 8002416: 4604 mov r4, r0 + 8002418: 4608 mov r0, r1 + 800241a: 4611 mov r1, r2 + 800241c: 461a mov r2, r3 + 800241e: 4623 mov r3, r4 + 8002420: 80fb strh r3, [r7, #6] + 8002422: 4603 mov r3, r0 + 8002424: 80bb strh r3, [r7, #4] + 8002426: 460b mov r3, r1 + 8002428: 807b strh r3, [r7, #2] + 800242a: 4613 mov r3, r2 + 800242c: 803b strh r3, [r7, #0] + uint8_t hi, lo; + + // rudimentary clipping (drawChar w/big text requires this) + if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return; + 800242e: 88fb ldrh r3, [r7, #6] + 8002430: 2b7f cmp r3, #127 @ 0x7f + 8002432: d85e bhi.n 80024f2 + 8002434: 88bb ldrh r3, [r7, #4] + 8002436: 2b9f cmp r3, #159 @ 0x9f + 8002438: d85b bhi.n 80024f2 + + if((x + w - 1) >= ST7735_TFTWIDTH) w = ST7735_TFTWIDTH - x; + 800243a: 88fa ldrh r2, [r7, #6] + 800243c: 887b ldrh r3, [r7, #2] + 800243e: 4413 add r3, r2 + 8002440: 2b80 cmp r3, #128 @ 0x80 + 8002442: dd03 ble.n 800244c + 8002444: 88fb ldrh r3, [r7, #6] + 8002446: f1c3 0380 rsb r3, r3, #128 @ 0x80 + 800244a: 807b strh r3, [r7, #2] + if((y + h - 1) >= ST7735_TFTHEIGHT_18) h = ST7735_TFTHEIGHT_18 - y; + 800244c: 88ba ldrh r2, [r7, #4] + 800244e: 883b ldrh r3, [r7, #0] + 8002450: 4413 add r3, r2 + 8002452: 2ba0 cmp r3, #160 @ 0xa0 + 8002454: dd03 ble.n 800245e + 8002456: 88bb ldrh r3, [r7, #4] + 8002458: f1c3 03a0 rsb r3, r3, #160 @ 0xa0 + 800245c: 803b strh r3, [r7, #0] + + // select window + setAddrWindow(x, y, x+w-1, y+h-1); + 800245e: 88fb ldrh r3, [r7, #6] + 8002460: b2d8 uxtb r0, r3 + 8002462: 88bb ldrh r3, [r7, #4] + 8002464: b2d9 uxtb r1, r3 + 8002466: 88fb ldrh r3, [r7, #6] + 8002468: b2da uxtb r2, r3 + 800246a: 887b ldrh r3, [r7, #2] + 800246c: b2db uxtb r3, r3 + 800246e: 4413 add r3, r2 + 8002470: b2db uxtb r3, r3 + 8002472: 3b01 subs r3, #1 + 8002474: b2dc uxtb r4, r3 + 8002476: 88bb ldrh r3, [r7, #4] + 8002478: b2da uxtb r2, r3 + 800247a: 883b ldrh r3, [r7, #0] + 800247c: b2db uxtb r3, r3 + 800247e: 4413 add r3, r2 + 8002480: b2db uxtb r3, r3 + 8002482: 3b01 subs r3, #1 + 8002484: b2db uxtb r3, r3 + 8002486: 4622 mov r2, r4 + 8002488: f7ff fefa bl 8002280 + + hi = color >> 8; + 800248c: 8c3b ldrh r3, [r7, #32] + 800248e: 0a1b lsrs r3, r3, #8 + 8002490: b29b uxth r3, r3 + 8002492: b2db uxtb r3, r3 + 8002494: 73fb strb r3, [r7, #15] + lo = color ; + 8002496: 8c3b ldrh r3, [r7, #32] + 8002498: b2db uxtb r3, r3 + 800249a: 73bb strb r3, [r7, #14] + */ + + /*HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // D/nC = 1 data + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0*/ + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + 800249c: 4b17 ldr r3, [pc, #92] @ (80024fc ) + 800249e: 2204 movs r2, #4 + 80024a0: 619a str r2, [r3, #24] + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0 + 80024a2: 4b16 ldr r3, [pc, #88] @ (80024fc ) + 80024a4: f44f 3200 mov.w r2, #131072 @ 0x20000 + 80024a8: 619a str r2, [r3, #24] + + for(y=h; y>0; y--) + 80024aa: 883b ldrh r3, [r7, #0] + 80024ac: 80bb strh r3, [r7, #4] + 80024ae: e019 b.n 80024e4 + { + for(x=w; x>0; x--) + 80024b0: 887b ldrh r3, [r7, #2] + 80024b2: 80fb strh r3, [r7, #6] + 80024b4: e010 b.n 80024d8 + { + + HAL_SPI_Transmit(&hspi1, &hi, 1, 100); // + 80024b6: f107 010f add.w r1, r7, #15 + 80024ba: 2364 movs r3, #100 @ 0x64 + 80024bc: 2201 movs r2, #1 + 80024be: 4810 ldr r0, [pc, #64] @ (8002500 ) + 80024c0: f7ff fc39 bl 8001d36 + HAL_SPI_Transmit(&hspi1, &lo, 1, 100); // + 80024c4: f107 010e add.w r1, r7, #14 + 80024c8: 2364 movs r3, #100 @ 0x64 + 80024ca: 2201 movs r2, #1 + 80024cc: 480c ldr r0, [pc, #48] @ (8002500 ) + 80024ce: f7ff fc32 bl 8001d36 + for(x=w; x>0; x--) + 80024d2: 88fb ldrh r3, [r7, #6] + 80024d4: 3b01 subs r3, #1 + 80024d6: 80fb strh r3, [r7, #6] + 80024d8: 88fb ldrh r3, [r7, #6] + 80024da: 2b00 cmp r3, #0 + 80024dc: d1eb bne.n 80024b6 + for(y=h; y>0; y--) + 80024de: 88bb ldrh r3, [r7, #4] + 80024e0: 3b01 subs r3, #1 + 80024e2: 80bb strh r3, [r7, #4] + 80024e4: 88bb ldrh r3, [r7, #4] + 80024e6: 2b00 cmp r3, #0 + 80024e8: d1e2 bne.n 80024b0 + + } + } + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1 + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + 80024ea: 4b04 ldr r3, [pc, #16] @ (80024fc ) + 80024ec: 2202 movs r2, #2 + 80024ee: 619a str r2, [r3, #24] + 80024f0: e000 b.n 80024f4 + if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return; + 80024f2: bf00 nop + +} + 80024f4: 3714 adds r7, #20 + 80024f6: 46bd mov sp, r7 + 80024f8: bd90 pop {r4, r7, pc} + 80024fa: bf00 nop + 80024fc: 40020800 .word 0x40020800 + 8002500: 20000078 .word 0x20000078 + +08002504 : +* : size = 1 to 10 +* Output : None +* Return : None +*******************************************************************************/ +void displayChar_TFT(uint16_t x, uint16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size) +{ + 8002504: b590 push {r4, r7, lr} + 8002506: b087 sub sp, #28 + 8002508: af02 add r7, sp, #8 + 800250a: 4604 mov r4, r0 + 800250c: 4608 mov r0, r1 + 800250e: 4611 mov r1, r2 + 8002510: 461a mov r2, r3 + 8002512: 4623 mov r3, r4 + 8002514: 80fb strh r3, [r7, #6] + 8002516: 4603 mov r3, r0 + 8002518: 80bb strh r3, [r7, #4] + 800251a: 460b mov r3, r1 + 800251c: 70fb strb r3, [r7, #3] + 800251e: 4613 mov r3, r2 + 8002520: 803b strh r3, [r7, #0] + uint8_t i,j,line; + + + if((x >= ST7735_TFTWIDTH) || // Clip right + 8002522: 88fb ldrh r3, [r7, #6] + 8002524: 2b7f cmp r3, #127 @ 0x7f + 8002526: f200 80b1 bhi.w 800268c + 800252a: 88bb ldrh r3, [r7, #4] + 800252c: 2b9f cmp r3, #159 @ 0x9f + 800252e: f200 80ad bhi.w 800268c + (y >= ST7735_TFTHEIGHT_18) || // Clip bottom + ((x + 6 * size - 1) < 0) || // Clip left + 8002532: 88f9 ldrh r1, [r7, #6] + 8002534: f897 2024 ldrb.w r2, [r7, #36] @ 0x24 + 8002538: 4613 mov r3, r2 + 800253a: 005b lsls r3, r3, #1 + 800253c: 4413 add r3, r2 + 800253e: 005b lsls r3, r3, #1 + 8002540: 440b add r3, r1 + (y >= ST7735_TFTHEIGHT_18) || // Clip bottom + 8002542: 2b00 cmp r3, #0 + 8002544: f340 80a2 ble.w 800268c + ((y + 8 * size - 1) < 0)) // Clip top + 8002548: 88ba ldrh r2, [r7, #4] + 800254a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 800254e: 00db lsls r3, r3, #3 + 8002550: 4413 add r3, r2 + ((x + 6 * size - 1) < 0) || // Clip left + 8002552: 2b00 cmp r3, #0 + 8002554: f340 809a ble.w 800268c + return; + + for (i=0; i<6; i++ ) + 8002558: 2300 movs r3, #0 + 800255a: 73fb strb r3, [r7, #15] + 800255c: e091 b.n 8002682 + { + if (i == 5) + 800255e: 7bfb ldrb r3, [r7, #15] + 8002560: 2b05 cmp r3, #5 + 8002562: d102 bne.n 800256a + line = 0x0; + 8002564: 2300 movs r3, #0 + 8002566: 737b strb r3, [r7, #13] + 8002568: e00a b.n 8002580 + else + line = pgm_read_byte(tab_font + (c*5) + i); + 800256a: 78fa ldrb r2, [r7, #3] + 800256c: 4613 mov r3, r2 + 800256e: 009b lsls r3, r3, #2 + 8002570: 4413 add r3, r2 + 8002572: 461a mov r2, r3 + 8002574: 7bfb ldrb r3, [r7, #15] + 8002576: 4413 add r3, r2 + 8002578: 4a46 ldr r2, [pc, #280] @ (8002694 ) + 800257a: 4413 add r3, r2 + 800257c: 781b ldrb r3, [r3, #0] + 800257e: 737b strb r3, [r7, #13] + + for ( j = 0; j<8; j++) + 8002580: 2300 movs r3, #0 + 8002582: 73bb strb r3, [r7, #14] + 8002584: e077 b.n 8002676 + { + if (line & 0x1) + 8002586: 7b7b ldrb r3, [r7, #13] + 8002588: f003 0301 and.w r3, r3, #1 + 800258c: 2b00 cmp r3, #0 + 800258e: d034 beq.n 80025fa + { + if (size == 1) // default size + 8002590: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 8002594: 2b01 cmp r3, #1 + 8002596: d10e bne.n 80025b6 + drawPixel_TFT(x+i, y+j, color); + 8002598: 7bfb ldrb r3, [r7, #15] + 800259a: b29a uxth r2, r3 + 800259c: 88fb ldrh r3, [r7, #6] + 800259e: 4413 add r3, r2 + 80025a0: b298 uxth r0, r3 + 80025a2: 7bbb ldrb r3, [r7, #14] + 80025a4: b29a uxth r2, r3 + 80025a6: 88bb ldrh r3, [r7, #4] + 80025a8: 4413 add r3, r2 + 80025aa: b29b uxth r3, r3 + 80025ac: 883a ldrh r2, [r7, #0] + 80025ae: 4619 mov r1, r3 + 80025b0: f7ff fee8 bl 8002384 + 80025b4: e059 b.n 800266a + else + { // big size + fillRect_TFT(x+(i*size), y+(j*size), size, size, color); + 80025b6: 7bfb ldrb r3, [r7, #15] + 80025b8: b29b uxth r3, r3 + 80025ba: f897 2024 ldrb.w r2, [r7, #36] @ 0x24 + 80025be: b292 uxth r2, r2 + 80025c0: fb02 f303 mul.w r3, r2, r3 + 80025c4: b29a uxth r2, r3 + 80025c6: 88fb ldrh r3, [r7, #6] + 80025c8: 4413 add r3, r2 + 80025ca: b298 uxth r0, r3 + 80025cc: 7bbb ldrb r3, [r7, #14] + 80025ce: b29b uxth r3, r3 + 80025d0: f897 2024 ldrb.w r2, [r7, #36] @ 0x24 + 80025d4: b292 uxth r2, r2 + 80025d6: fb02 f303 mul.w r3, r2, r3 + 80025da: b29a uxth r2, r3 + 80025dc: 88bb ldrh r3, [r7, #4] + 80025de: 4413 add r3, r2 + 80025e0: b299 uxth r1, r3 + 80025e2: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 80025e6: b29a uxth r2, r3 + 80025e8: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 80025ec: b29c uxth r4, r3 + 80025ee: 883b ldrh r3, [r7, #0] + 80025f0: 9300 str r3, [sp, #0] + 80025f2: 4623 mov r3, r4 + 80025f4: f7ff ff0c bl 8002410 + 80025f8: e037 b.n 800266a + } + } + else if (bg != color) + 80025fa: 8c3a ldrh r2, [r7, #32] + 80025fc: 883b ldrh r3, [r7, #0] + 80025fe: 429a cmp r2, r3 + 8002600: d033 beq.n 800266a + { + if (size == 1) // default size + 8002602: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 8002606: 2b01 cmp r3, #1 + 8002608: d10e bne.n 8002628 + drawPixel_TFT(x+i, y+j, bg); + 800260a: 7bfb ldrb r3, [r7, #15] + 800260c: b29a uxth r2, r3 + 800260e: 88fb ldrh r3, [r7, #6] + 8002610: 4413 add r3, r2 + 8002612: b298 uxth r0, r3 + 8002614: 7bbb ldrb r3, [r7, #14] + 8002616: b29a uxth r2, r3 + 8002618: 88bb ldrh r3, [r7, #4] + 800261a: 4413 add r3, r2 + 800261c: b29b uxth r3, r3 + 800261e: 8c3a ldrh r2, [r7, #32] + 8002620: 4619 mov r1, r3 + 8002622: f7ff feaf bl 8002384 + 8002626: e020 b.n 800266a + else + { // big size + fillRect_TFT(x+i*size, y+j*size, size, size, bg); + 8002628: 7bfb ldrb r3, [r7, #15] + 800262a: b29b uxth r3, r3 + 800262c: f897 2024 ldrb.w r2, [r7, #36] @ 0x24 + 8002630: b292 uxth r2, r2 + 8002632: fb02 f303 mul.w r3, r2, r3 + 8002636: b29a uxth r2, r3 + 8002638: 88fb ldrh r3, [r7, #6] + 800263a: 4413 add r3, r2 + 800263c: b298 uxth r0, r3 + 800263e: 7bbb ldrb r3, [r7, #14] + 8002640: b29b uxth r3, r3 + 8002642: f897 2024 ldrb.w r2, [r7, #36] @ 0x24 + 8002646: b292 uxth r2, r2 + 8002648: fb02 f303 mul.w r3, r2, r3 + 800264c: b29a uxth r2, r3 + 800264e: 88bb ldrh r3, [r7, #4] + 8002650: 4413 add r3, r2 + 8002652: b299 uxth r1, r3 + 8002654: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 8002658: b29a uxth r2, r3 + 800265a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24 + 800265e: b29c uxth r4, r3 + 8002660: 8c3b ldrh r3, [r7, #32] + 8002662: 9300 str r3, [sp, #0] + 8002664: 4623 mov r3, r4 + 8002666: f7ff fed3 bl 8002410 + } + } + line = line >> 1; + 800266a: 7b7b ldrb r3, [r7, #13] + 800266c: 085b lsrs r3, r3, #1 + 800266e: 737b strb r3, [r7, #13] + for ( j = 0; j<8; j++) + 8002670: 7bbb ldrb r3, [r7, #14] + 8002672: 3301 adds r3, #1 + 8002674: 73bb strb r3, [r7, #14] + 8002676: 7bbb ldrb r3, [r7, #14] + 8002678: 2b07 cmp r3, #7 + 800267a: d984 bls.n 8002586 + for (i=0; i<6; i++ ) + 800267c: 7bfb ldrb r3, [r7, #15] + 800267e: 3301 adds r3, #1 + 8002680: 73fb strb r3, [r7, #15] + 8002682: 7bfb ldrb r3, [r7, #15] + 8002684: 2b05 cmp r3, #5 + 8002686: f67f af6a bls.w 800255e + 800268a: e000 b.n 800268e + return; + 800268c: bf00 nop + } + } +} + 800268e: 3714 adds r7, #20 + 8002690: 46bd mov sp, r7 + 8002692: bd90 pop {r4, r7, pc} + 8002694: 08002a20 .word 0x08002a20 + +08002698 : +* Input : +* Output : None +* Return : None +*******************************************************************************/ +void displayLogo_TFT( void) +{ + 8002698: b580 push {r7, lr} + 800269a: b082 sub sp, #8 + 800269c: af00 add r7, sp, #0 + uint8_t i,j,k,line; + uint16_t color=ST7735_WHITE; + 800269e: f64f 73ff movw r3, #65535 @ 0xffff + 80026a2: 807b strh r3, [r7, #2] + + + + for(i=0;i<=120;i++) + 80026a4: 2300 movs r3, #0 + 80026a6: 71fb strb r3, [r7, #7] + 80026a8: e09e b.n 80027e8 + { + + for(j=0;j<= 1;j++) + 80026aa: 2300 movs r3, #0 + 80026ac: 71bb strb r3, [r7, #6] + 80026ae: e02b b.n 8002708 + { + line=(ALL_IS_mono_120[i+120*j]); + 80026b0: 79f9 ldrb r1, [r7, #7] + 80026b2: 79ba ldrb r2, [r7, #6] + 80026b4: 4613 mov r3, r2 + 80026b6: 011b lsls r3, r3, #4 + 80026b8: 1a9b subs r3, r3, r2 + 80026ba: 00db lsls r3, r3, #3 + 80026bc: 440b add r3, r1 + 80026be: 4a4f ldr r2, [pc, #316] @ (80027fc ) + 80026c0: 5cd3 ldrb r3, [r2, r3] + 80026c2: 713b strb r3, [r7, #4] + for ( k = 0; k<8; k++) + 80026c4: 2300 movs r3, #0 + 80026c6: 717b strb r3, [r7, #5] + 80026c8: e018 b.n 80026fc + { + if (line & 0x1) + 80026ca: 793b ldrb r3, [r7, #4] + 80026cc: f003 0301 and.w r3, r3, #1 + 80026d0: 2b00 cmp r3, #0 + 80026d2: d00d beq.n 80026f0 + { + + drawPixel_TFT(i, j*8+k, color); + 80026d4: 79fb ldrb r3, [r7, #7] + 80026d6: b298 uxth r0, r3 + 80026d8: 79bb ldrb r3, [r7, #6] + 80026da: b29b uxth r3, r3 + 80026dc: 00db lsls r3, r3, #3 + 80026de: b29a uxth r2, r3 + 80026e0: 797b ldrb r3, [r7, #5] + 80026e2: b29b uxth r3, r3 + 80026e4: 4413 add r3, r2 + 80026e6: b29b uxth r3, r3 + 80026e8: 887a ldrh r2, [r7, #2] + 80026ea: 4619 mov r1, r3 + 80026ec: f7ff fe4a bl 8002384 + } + line = line >> 1; + 80026f0: 793b ldrb r3, [r7, #4] + 80026f2: 085b lsrs r3, r3, #1 + 80026f4: 713b strb r3, [r7, #4] + for ( k = 0; k<8; k++) + 80026f6: 797b ldrb r3, [r7, #5] + 80026f8: 3301 adds r3, #1 + 80026fa: 717b strb r3, [r7, #5] + 80026fc: 797b ldrb r3, [r7, #5] + 80026fe: 2b07 cmp r3, #7 + 8002700: d9e3 bls.n 80026ca + for(j=0;j<= 1;j++) + 8002702: 79bb ldrb r3, [r7, #6] + 8002704: 3301 adds r3, #1 + 8002706: 71bb strb r3, [r7, #6] + 8002708: 79bb ldrb r3, [r7, #6] + 800270a: 2b01 cmp r3, #1 + 800270c: d9d0 bls.n 80026b0 + } + } + + color=ST7735_RED; + 800270e: f44f 4378 mov.w r3, #63488 @ 0xf800 + 8002712: 807b strh r3, [r7, #2] + for(j=2;j<= 3;j++) + 8002714: 2302 movs r3, #2 + 8002716: 71bb strb r3, [r7, #6] + 8002718: e02b b.n 8002772 + { + line=(ALL_IS_mono_120[i+120*j]); + 800271a: 79f9 ldrb r1, [r7, #7] + 800271c: 79ba ldrb r2, [r7, #6] + 800271e: 4613 mov r3, r2 + 8002720: 011b lsls r3, r3, #4 + 8002722: 1a9b subs r3, r3, r2 + 8002724: 00db lsls r3, r3, #3 + 8002726: 440b add r3, r1 + 8002728: 4a34 ldr r2, [pc, #208] @ (80027fc ) + 800272a: 5cd3 ldrb r3, [r2, r3] + 800272c: 713b strb r3, [r7, #4] + for ( k = 0; k<8; k++) + 800272e: 2300 movs r3, #0 + 8002730: 717b strb r3, [r7, #5] + 8002732: e018 b.n 8002766 + { + if (line & 0x1) + 8002734: 793b ldrb r3, [r7, #4] + 8002736: f003 0301 and.w r3, r3, #1 + 800273a: 2b00 cmp r3, #0 + 800273c: d00d beq.n 800275a + { + + drawPixel_TFT(i, j*8+k, color); + 800273e: 79fb ldrb r3, [r7, #7] + 8002740: b298 uxth r0, r3 + 8002742: 79bb ldrb r3, [r7, #6] + 8002744: b29b uxth r3, r3 + 8002746: 00db lsls r3, r3, #3 + 8002748: b29a uxth r2, r3 + 800274a: 797b ldrb r3, [r7, #5] + 800274c: b29b uxth r3, r3 + 800274e: 4413 add r3, r2 + 8002750: b29b uxth r3, r3 + 8002752: 887a ldrh r2, [r7, #2] + 8002754: 4619 mov r1, r3 + 8002756: f7ff fe15 bl 8002384 + } + line = line >> 1; + 800275a: 793b ldrb r3, [r7, #4] + 800275c: 085b lsrs r3, r3, #1 + 800275e: 713b strb r3, [r7, #4] + for ( k = 0; k<8; k++) + 8002760: 797b ldrb r3, [r7, #5] + 8002762: 3301 adds r3, #1 + 8002764: 717b strb r3, [r7, #5] + 8002766: 797b ldrb r3, [r7, #5] + 8002768: 2b07 cmp r3, #7 + 800276a: d9e3 bls.n 8002734 + for(j=2;j<= 3;j++) + 800276c: 79bb ldrb r3, [r7, #6] + 800276e: 3301 adds r3, #1 + 8002770: 71bb strb r3, [r7, #6] + 8002772: 79bb ldrb r3, [r7, #6] + 8002774: 2b03 cmp r3, #3 + 8002776: d9d0 bls.n 800271a + } + } + + color=ST7735_WHITE; + 8002778: f64f 73ff movw r3, #65535 @ 0xffff + 800277c: 807b strh r3, [r7, #2] + for(j=4;j<= 5;j++) + 800277e: 2304 movs r3, #4 + 8002780: 71bb strb r3, [r7, #6] + 8002782: e02b b.n 80027dc + { + line=(ALL_IS_mono_120[i+120*j]); + 8002784: 79f9 ldrb r1, [r7, #7] + 8002786: 79ba ldrb r2, [r7, #6] + 8002788: 4613 mov r3, r2 + 800278a: 011b lsls r3, r3, #4 + 800278c: 1a9b subs r3, r3, r2 + 800278e: 00db lsls r3, r3, #3 + 8002790: 440b add r3, r1 + 8002792: 4a1a ldr r2, [pc, #104] @ (80027fc ) + 8002794: 5cd3 ldrb r3, [r2, r3] + 8002796: 713b strb r3, [r7, #4] + for ( k = 0; k<8; k++) + 8002798: 2300 movs r3, #0 + 800279a: 717b strb r3, [r7, #5] + 800279c: e018 b.n 80027d0 + { + if (line & 0x1) + 800279e: 793b ldrb r3, [r7, #4] + 80027a0: f003 0301 and.w r3, r3, #1 + 80027a4: 2b00 cmp r3, #0 + 80027a6: d00d beq.n 80027c4 + { + + drawPixel_TFT(i, j*8+k, color); + 80027a8: 79fb ldrb r3, [r7, #7] + 80027aa: b298 uxth r0, r3 + 80027ac: 79bb ldrb r3, [r7, #6] + 80027ae: b29b uxth r3, r3 + 80027b0: 00db lsls r3, r3, #3 + 80027b2: b29a uxth r2, r3 + 80027b4: 797b ldrb r3, [r7, #5] + 80027b6: b29b uxth r3, r3 + 80027b8: 4413 add r3, r2 + 80027ba: b29b uxth r3, r3 + 80027bc: 887a ldrh r2, [r7, #2] + 80027be: 4619 mov r1, r3 + 80027c0: f7ff fde0 bl 8002384 + } + line = line >> 1; + 80027c4: 793b ldrb r3, [r7, #4] + 80027c6: 085b lsrs r3, r3, #1 + 80027c8: 713b strb r3, [r7, #4] + for ( k = 0; k<8; k++) + 80027ca: 797b ldrb r3, [r7, #5] + 80027cc: 3301 adds r3, #1 + 80027ce: 717b strb r3, [r7, #5] + 80027d0: 797b ldrb r3, [r7, #5] + 80027d2: 2b07 cmp r3, #7 + 80027d4: d9e3 bls.n 800279e + for(j=4;j<= 5;j++) + 80027d6: 79bb ldrb r3, [r7, #6] + 80027d8: 3301 adds r3, #1 + 80027da: 71bb strb r3, [r7, #6] + 80027dc: 79bb ldrb r3, [r7, #6] + 80027de: 2b05 cmp r3, #5 + 80027e0: d9d0 bls.n 8002784 + for(i=0;i<=120;i++) + 80027e2: 79fb ldrb r3, [r7, #7] + 80027e4: 3301 adds r3, #1 + 80027e6: 71fb strb r3, [r7, #7] + 80027e8: 79fb ldrb r3, [r7, #7] + 80027ea: 2b78 cmp r3, #120 @ 0x78 + 80027ec: f67f af5d bls.w 80026aa + } + } + + } +} + 80027f0: bf00 nop + 80027f2: bf00 nop + 80027f4: 3708 adds r7, #8 + 80027f6: 46bd mov sp, r7 + 80027f8: bd80 pop {r7, pc} + 80027fa: bf00 nop + 80027fc: 08002f1c .word 0x08002f1c + +08002800 : + 8002800: 220a movs r2, #10 + 8002802: 2100 movs r1, #0 + 8002804: f000 b87a b.w 80028fc + +08002808 <_strtol_l.isra.0>: + 8002808: 2b24 cmp r3, #36 @ 0x24 + 800280a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800280e: 4686 mov lr, r0 + 8002810: 4690 mov r8, r2 + 8002812: d801 bhi.n 8002818 <_strtol_l.isra.0+0x10> + 8002814: 2b01 cmp r3, #1 + 8002816: d106 bne.n 8002826 <_strtol_l.isra.0+0x1e> + 8002818: f000 f882 bl 8002920 <__errno> + 800281c: 2316 movs r3, #22 + 800281e: 6003 str r3, [r0, #0] + 8002820: 2000 movs r0, #0 + 8002822: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8002826: 460d mov r5, r1 + 8002828: 4833 ldr r0, [pc, #204] @ (80028f8 <_strtol_l.isra.0+0xf0>) + 800282a: 462a mov r2, r5 + 800282c: f815 4b01 ldrb.w r4, [r5], #1 + 8002830: 5d06 ldrb r6, [r0, r4] + 8002832: f016 0608 ands.w r6, r6, #8 + 8002836: d1f8 bne.n 800282a <_strtol_l.isra.0+0x22> + 8002838: 2c2d cmp r4, #45 @ 0x2d + 800283a: d110 bne.n 800285e <_strtol_l.isra.0+0x56> + 800283c: 2601 movs r6, #1 + 800283e: 782c ldrb r4, [r5, #0] + 8002840: 1c95 adds r5, r2, #2 + 8002842: f033 0210 bics.w r2, r3, #16 + 8002846: d115 bne.n 8002874 <_strtol_l.isra.0+0x6c> + 8002848: 2c30 cmp r4, #48 @ 0x30 + 800284a: d10d bne.n 8002868 <_strtol_l.isra.0+0x60> + 800284c: 782a ldrb r2, [r5, #0] + 800284e: f002 02df and.w r2, r2, #223 @ 0xdf + 8002852: 2a58 cmp r2, #88 @ 0x58 + 8002854: d108 bne.n 8002868 <_strtol_l.isra.0+0x60> + 8002856: 786c ldrb r4, [r5, #1] + 8002858: 3502 adds r5, #2 + 800285a: 2310 movs r3, #16 + 800285c: e00a b.n 8002874 <_strtol_l.isra.0+0x6c> + 800285e: 2c2b cmp r4, #43 @ 0x2b + 8002860: bf04 itt eq + 8002862: 782c ldrbeq r4, [r5, #0] + 8002864: 1c95 addeq r5, r2, #2 + 8002866: e7ec b.n 8002842 <_strtol_l.isra.0+0x3a> + 8002868: 2b00 cmp r3, #0 + 800286a: d1f6 bne.n 800285a <_strtol_l.isra.0+0x52> + 800286c: 2c30 cmp r4, #48 @ 0x30 + 800286e: bf14 ite ne + 8002870: 230a movne r3, #10 + 8002872: 2308 moveq r3, #8 + 8002874: 2200 movs r2, #0 + 8002876: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000 + 800287a: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff + 800287e: fbbc f9f3 udiv r9, ip, r3 + 8002882: 4610 mov r0, r2 + 8002884: fb03 ca19 mls sl, r3, r9, ip + 8002888: f1a4 0730 sub.w r7, r4, #48 @ 0x30 + 800288c: 2f09 cmp r7, #9 + 800288e: d80f bhi.n 80028b0 <_strtol_l.isra.0+0xa8> + 8002890: 463c mov r4, r7 + 8002892: 42a3 cmp r3, r4 + 8002894: dd1b ble.n 80028ce <_strtol_l.isra.0+0xc6> + 8002896: 1c57 adds r7, r2, #1 + 8002898: d007 beq.n 80028aa <_strtol_l.isra.0+0xa2> + 800289a: 4581 cmp r9, r0 + 800289c: d314 bcc.n 80028c8 <_strtol_l.isra.0+0xc0> + 800289e: d101 bne.n 80028a4 <_strtol_l.isra.0+0x9c> + 80028a0: 45a2 cmp sl, r4 + 80028a2: db11 blt.n 80028c8 <_strtol_l.isra.0+0xc0> + 80028a4: 2201 movs r2, #1 + 80028a6: fb00 4003 mla r0, r0, r3, r4 + 80028aa: f815 4b01 ldrb.w r4, [r5], #1 + 80028ae: e7eb b.n 8002888 <_strtol_l.isra.0+0x80> + 80028b0: f1a4 0741 sub.w r7, r4, #65 @ 0x41 + 80028b4: 2f19 cmp r7, #25 + 80028b6: d801 bhi.n 80028bc <_strtol_l.isra.0+0xb4> + 80028b8: 3c37 subs r4, #55 @ 0x37 + 80028ba: e7ea b.n 8002892 <_strtol_l.isra.0+0x8a> + 80028bc: f1a4 0761 sub.w r7, r4, #97 @ 0x61 + 80028c0: 2f19 cmp r7, #25 + 80028c2: d804 bhi.n 80028ce <_strtol_l.isra.0+0xc6> + 80028c4: 3c57 subs r4, #87 @ 0x57 + 80028c6: e7e4 b.n 8002892 <_strtol_l.isra.0+0x8a> + 80028c8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 80028cc: e7ed b.n 80028aa <_strtol_l.isra.0+0xa2> + 80028ce: 1c53 adds r3, r2, #1 + 80028d0: d108 bne.n 80028e4 <_strtol_l.isra.0+0xdc> + 80028d2: 2322 movs r3, #34 @ 0x22 + 80028d4: 4660 mov r0, ip + 80028d6: f8ce 3000 str.w r3, [lr] + 80028da: f1b8 0f00 cmp.w r8, #0 + 80028de: d0a0 beq.n 8002822 <_strtol_l.isra.0+0x1a> + 80028e0: 1e69 subs r1, r5, #1 + 80028e2: e006 b.n 80028f2 <_strtol_l.isra.0+0xea> + 80028e4: b106 cbz r6, 80028e8 <_strtol_l.isra.0+0xe0> + 80028e6: 4240 negs r0, r0 + 80028e8: f1b8 0f00 cmp.w r8, #0 + 80028ec: d099 beq.n 8002822 <_strtol_l.isra.0+0x1a> + 80028ee: 2a00 cmp r2, #0 + 80028f0: d1f6 bne.n 80028e0 <_strtol_l.isra.0+0xd8> + 80028f2: f8c8 1000 str.w r1, [r8] + 80028f6: e794 b.n 8002822 <_strtol_l.isra.0+0x1a> + 80028f8: 080031ed .word 0x080031ed + +080028fc : + 80028fc: 4613 mov r3, r2 + 80028fe: 460a mov r2, r1 + 8002900: 4601 mov r1, r0 + 8002902: 4802 ldr r0, [pc, #8] @ (800290c ) + 8002904: 6800 ldr r0, [r0, #0] + 8002906: f7ff bf7f b.w 8002808 <_strtol_l.isra.0> + 800290a: bf00 nop + 800290c: 2000000c .word 0x2000000c + +08002910 : + 8002910: 4603 mov r3, r0 + 8002912: 4402 add r2, r0 + 8002914: 4293 cmp r3, r2 + 8002916: d100 bne.n 800291a + 8002918: 4770 bx lr + 800291a: f803 1b01 strb.w r1, [r3], #1 + 800291e: e7f9 b.n 8002914 + +08002920 <__errno>: + 8002920: 4b01 ldr r3, [pc, #4] @ (8002928 <__errno+0x8>) + 8002922: 6818 ldr r0, [r3, #0] + 8002924: 4770 bx lr + 8002926: bf00 nop + 8002928: 2000000c .word 0x2000000c + +0800292c <__libc_init_array>: + 800292c: b570 push {r4, r5, r6, lr} + 800292e: 2600 movs r6, #0 + 8002930: 4d0c ldr r5, [pc, #48] @ (8002964 <__libc_init_array+0x38>) + 8002932: 4c0d ldr r4, [pc, #52] @ (8002968 <__libc_init_array+0x3c>) + 8002934: 1b64 subs r4, r4, r5 + 8002936: 10a4 asrs r4, r4, #2 + 8002938: 42a6 cmp r6, r4 + 800293a: d109 bne.n 8002950 <__libc_init_array+0x24> + 800293c: f000 f81a bl 8002974 <_init> + 8002940: 2600 movs r6, #0 + 8002942: 4d0a ldr r5, [pc, #40] @ (800296c <__libc_init_array+0x40>) + 8002944: 4c0a ldr r4, [pc, #40] @ (8002970 <__libc_init_array+0x44>) + 8002946: 1b64 subs r4, r4, r5 + 8002948: 10a4 asrs r4, r4, #2 + 800294a: 42a6 cmp r6, r4 + 800294c: d105 bne.n 800295a <__libc_init_array+0x2e> + 800294e: bd70 pop {r4, r5, r6, pc} + 8002950: f855 3b04 ldr.w r3, [r5], #4 + 8002954: 4798 blx r3 + 8002956: 3601 adds r6, #1 + 8002958: e7ee b.n 8002938 <__libc_init_array+0xc> + 800295a: f855 3b04 ldr.w r3, [r5], #4 + 800295e: 4798 blx r3 + 8002960: 3601 adds r6, #1 + 8002962: e7f2 b.n 800294a <__libc_init_array+0x1e> + 8002964: 080032f8 .word 0x080032f8 + 8002968: 080032f8 .word 0x080032f8 + 800296c: 080032f8 .word 0x080032f8 + 8002970: 080032fc .word 0x080032fc + +08002974 <_init>: + 8002974: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002976: bf00 nop + 8002978: bcf8 pop {r3, r4, r5, r6, r7} + 800297a: bc08 pop {r3} + 800297c: 469e mov lr, r3 + 800297e: 4770 bx lr + +08002980 <_fini>: + 8002980: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002982: bf00 nop + 8002984: bcf8 pop {r3, r4, r5, r6, r7} + 8002986: bc08 pop {r3} + 8002988: 469e mov lr, r3 + 800298a: 4770 bx lr diff --git a/TP4_INIT_TFT/Debug/TP4_INIT_TFT.map b/TP4_INIT_TFT/Debug/TP4_INIT_TFT.map new file mode 100644 index 0000000..a693621 --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP4_INIT_TFT.map @@ -0,0 +1,3104 @@ +Archive member included to satisfy reference by file (symbol) + +/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-atoi.o) + ./Core/Src/main.o (atoi) +/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-exit.o) + /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o (exit) 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/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-strtol.o) + .debug_frame 0x00001bac 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00001bcc 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-errno.o) + .debug_frame 0x00001bec 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .debug_frame 0x00001c18 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00001c44 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x70 + .debug_line_str + 0x00000000 0x70 ./Core/Startup/startup_stm32l152retx.o diff --git a/TP4_INIT_TFT/Debug/TP4_MELODIE.list b/TP4_INIT_TFT/Debug/TP4_MELODIE.list new file mode 100644 index 0000000..6c6268e --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP4_MELODIE.list @@ -0,0 +1,8000 @@ + +TP4_MELODIE.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00002d74 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000003c 08002eb0 08002eb0 00003eb0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08002eec 08002eec 0000400c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 08002eec 08002eec 00003eec 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 08002ef4 08002ef4 0000400c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08002ef4 08002ef4 00003ef4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 08002ef8 08002ef8 00003ef8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000000c 20000000 08002efc 00004000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000000b8 2000000c 08002f08 0000400c 2**2 + ALLOC + 10 ._user_heap_stack 00000604 200000c4 08002f08 000040c4 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0 + CONTENTS, READONLY + 12 .debug_info 000090de 00000000 00000000 00004035 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 000018ef 00000000 00000000 0000d113 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000a80 00000000 00000000 0000ea08 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 000007f6 00000000 00000000 0000f488 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 000155f9 00000000 00000000 0000fc7e 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0000aa5f 00000000 00000000 00025277 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 00088693 00000000 00000000 0002fcd6 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000b8369 2**0 + CONTENTS, READONLY + 20 .debug_frame 00002b74 00000000 00000000 000b83ac 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000baf20 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 2000000c .word 0x2000000c + 8000158: 00000000 .word 0x00000000 + 800015c: 08002e98 .word 0x08002e98 + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000010 .word 0x20000010 + 8000178: 08002e98 .word 0x08002e98 + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0 : + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void note(int freq, uint8_t indice) { + 80004b0: b580 push {r7, lr} + 80004b2: b082 sub sp, #8 + 80004b4: af00 add r7, sp, #0 + 80004b6: 6078 str r0, [r7, #4] + 80004b8: 460b mov r3, r1 + 80004ba: 70fb strb r3, [r7, #3] + MAX7219_DisplayChar(4, indice); + 80004bc: 78fb ldrb r3, [r7, #3] + 80004be: 4619 mov r1, r3 + 80004c0: 2004 movs r0, #4 + 80004c2: f000 fbb7 bl 8000c34 + TIM3->PSC = ((16000000/freq)/1600) - 1; + 80004c6: 4a08 ldr r2, [pc, #32] @ (80004e8 ) + 80004c8: 687b ldr r3, [r7, #4] + 80004ca: fb92 f3f3 sdiv r3, r2, r3 + 80004ce: 4a07 ldr r2, [pc, #28] @ (80004ec ) + 80004d0: fb82 1203 smull r1, r2, r2, r3 + 80004d4: 1252 asrs r2, r2, #9 + 80004d6: 17db asrs r3, r3, #31 + 80004d8: 1ad3 subs r3, r2, r3 + 80004da: 1e5a subs r2, r3, #1 + 80004dc: 4b04 ldr r3, [pc, #16] @ (80004f0 ) + 80004de: 629a str r2, [r3, #40] @ 0x28 +} + 80004e0: bf00 nop + 80004e2: 3708 adds r7, #8 + 80004e4: 46bd mov sp, r7 + 80004e6: bd80 pop {r7, pc} + 80004e8: 00f42400 .word 0x00f42400 + 80004ec: 51eb851f .word 0x51eb851f + 80004f0: 40000400 .word 0x40000400 + +080004f4
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 80004f4: b580 push {r7, lr} + 80004f6: b082 sub sp, #8 + 80004f8: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80004fa: f000 fbe1 bl 8000cc0 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80004fe: f000 f8a5 bl 800064c + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000502: f000 f993 bl 800082c + MX_SPI1_Init(); + 8000506: f000 f8e7 bl 80006d8 + MX_TIM3_Init(); + 800050a: f000 f91b bl 8000744 + /* USER CODE BEGIN 2 */ + MAX7219_Init(); + 800050e: f000 fb44 bl 8000b9a + HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1); + 8000512: 2100 movs r1, #0 + 8000514: 484b ldr r0, [pc, #300] @ (8000644 ) + 8000516: f001 ffef bl 80024f8 + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + MAX7219_Clear(); + 800051a: f000 fb75 bl 8000c08 + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + for (int i = 0; tab_music[i] != 255; i++) { + 800051e: 2300 movs r3, #0 + 8000520: 607b str r3, [r7, #4] + 8000522: e087 b.n 8000634 + switch (tab_music[i]) { + 8000524: 4a48 ldr r2, [pc, #288] @ (8000648 ) + 8000526: 687b ldr r3, [r7, #4] + 8000528: 4413 add r3, r2 + 800052a: 781b ldrb r3, [r3, #0] + 800052c: 2b09 cmp r3, #9 + 800052e: d87b bhi.n 8000628 + 8000530: a201 add r2, pc, #4 @ (adr r2, 8000538 ) + 8000532: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8000536: bf00 nop + 8000538: 08000561 .word 0x08000561 + 800053c: 08000575 .word 0x08000575 + 8000540: 08000589 .word 0x08000589 + 8000544: 0800059d .word 0x0800059d + 8000548: 080005b1 .word 0x080005b1 + 800054c: 080005c5 .word 0x080005c5 + 8000550: 080005d9 .word 0x080005d9 + 8000554: 080005ed .word 0x080005ed + 8000558: 08000601 .word 0x08000601 + 800055c: 08000615 .word 0x08000615 + case 0: + note(524, tab_music[i]); + 8000560: 4a39 ldr r2, [pc, #228] @ (8000648 ) + 8000562: 687b ldr r3, [r7, #4] + 8000564: 4413 add r3, r2 + 8000566: 781b ldrb r3, [r3, #0] + 8000568: 4619 mov r1, r3 + 800056a: f44f 7003 mov.w r0, #524 @ 0x20c + 800056e: f7ff ff9f bl 80004b0 + break; + 8000572: e059 b.n 8000628 + case 1: + note(587, tab_music[i]); + 8000574: 4a34 ldr r2, [pc, #208] @ (8000648 ) + 8000576: 687b ldr r3, [r7, #4] + 8000578: 4413 add r3, r2 + 800057a: 781b ldrb r3, [r3, #0] + 800057c: 4619 mov r1, r3 + 800057e: f240 204b movw r0, #587 @ 0x24b + 8000582: f7ff ff95 bl 80004b0 + break; + 8000586: e04f b.n 8000628 + case 2: + note(662, tab_music[i]); + 8000588: 4a2f ldr r2, [pc, #188] @ (8000648 ) + 800058a: 687b ldr r3, [r7, #4] + 800058c: 4413 add r3, r2 + 800058e: 781b ldrb r3, [r3, #0] + 8000590: 4619 mov r1, r3 + 8000592: f240 2096 movw r0, #662 @ 0x296 + 8000596: f7ff ff8b bl 80004b0 + break; + 800059a: e045 b.n 8000628 + case 3: + note(701, tab_music[i]); + 800059c: 4a2a ldr r2, [pc, #168] @ (8000648 ) + 800059e: 687b ldr r3, [r7, #4] + 80005a0: 4413 add r3, r2 + 80005a2: 781b ldrb r3, [r3, #0] + 80005a4: 4619 mov r1, r3 + 80005a6: f240 20bd movw r0, #701 @ 0x2bd + 80005aa: f7ff ff81 bl 80004b0 + break; + 80005ae: e03b b.n 8000628 + case 4: + note(787, tab_music[i]); + 80005b0: 4a25 ldr r2, [pc, #148] @ (8000648 ) + 80005b2: 687b ldr r3, [r7, #4] + 80005b4: 4413 add r3, r2 + 80005b6: 781b ldrb r3, [r3, #0] + 80005b8: 4619 mov r1, r3 + 80005ba: f240 3013 movw r0, #787 @ 0x313 + 80005be: f7ff ff77 bl 80004b0 + break; + 80005c2: e031 b.n 8000628 + case 5: + note(878, tab_music[i]); + 80005c4: 4a20 ldr r2, [pc, #128] @ (8000648 ) + 80005c6: 687b ldr r3, [r7, #4] + 80005c8: 4413 add r3, r2 + 80005ca: 781b ldrb r3, [r3, #0] + 80005cc: 4619 mov r1, r3 + 80005ce: f240 306e movw r0, #878 @ 0x36e + 80005d2: f7ff ff6d bl 80004b0 + break; + 80005d6: e027 b.n 8000628 + case 6: + note(1004, tab_music[i]); + 80005d8: 4a1b ldr r2, [pc, #108] @ (8000648 ) + 80005da: 687b ldr r3, [r7, #4] + 80005dc: 4413 add r3, r2 + 80005de: 781b ldrb r3, [r3, #0] + 80005e0: 4619 mov r1, r3 + 80005e2: f44f 707b mov.w r0, #1004 @ 0x3ec + 80005e6: f7ff ff63 bl 80004b0 + break; + 80005ea: e01d b.n 8000628 + case 7: // LA Diese + note(932, tab_music[i]); + 80005ec: 4a16 ldr r2, [pc, #88] @ (8000648 ) + 80005ee: 687b ldr r3, [r7, #4] + 80005f0: 4413 add r3, r2 + 80005f2: 781b ldrb r3, [r3, #0] + 80005f4: 4619 mov r1, r3 + 80005f6: f44f 7069 mov.w r0, #932 @ 0x3a4 + 80005fa: f7ff ff59 bl 80004b0 + break; + 80005fe: e013 b.n 8000628 + case 8: // RE gamme 5 + note(1175, tab_music[i]); + 8000600: 4a11 ldr r2, [pc, #68] @ (8000648 ) + 8000602: 687b ldr r3, [r7, #4] + 8000604: 4413 add r3, r2 + 8000606: 781b ldrb r3, [r3, #0] + 8000608: 4619 mov r1, r3 + 800060a: f240 4097 movw r0, #1175 @ 0x497 + 800060e: f7ff ff4f bl 80004b0 + break; + 8000612: e009 b.n 8000628 + case 9: // MI Diese gamme 5 + note(1109, tab_music[i]); + 8000614: 4a0c ldr r2, [pc, #48] @ (8000648 ) + 8000616: 687b ldr r3, [r7, #4] + 8000618: 4413 add r3, r2 + 800061a: 781b ldrb r3, [r3, #0] + 800061c: 4619 mov r1, r3 + 800061e: f240 4055 movw r0, #1109 @ 0x455 + 8000622: f7ff ff45 bl 80004b0 + break; + 8000626: bf00 nop + } + HAL_Delay(250); + 8000628: 20fa movs r0, #250 @ 0xfa + 800062a: f000 fbb7 bl 8000d9c + for (int i = 0; tab_music[i] != 255; i++) { + 800062e: 687b ldr r3, [r7, #4] + 8000630: 3301 adds r3, #1 + 8000632: 607b str r3, [r7, #4] + 8000634: 4a04 ldr r2, [pc, #16] @ (8000648 ) + 8000636: 687b ldr r3, [r7, #4] + 8000638: 4413 add r3, r2 + 800063a: 781b ldrb r3, [r3, #0] + 800063c: 2bff cmp r3, #255 @ 0xff + 800063e: f47f af71 bne.w 8000524 + 8000642: e76c b.n 800051e + 8000644: 20000080 .word 0x20000080 + 8000648: 08002eb0 .word 0x08002eb0 + +0800064c : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 800064c: b580 push {r7, lr} + 800064e: b092 sub sp, #72 @ 0x48 + 8000650: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000652: f107 0314 add.w r3, r7, #20 + 8000656: 2234 movs r2, #52 @ 0x34 + 8000658: 2100 movs r1, #0 + 800065a: 4618 mov r0, r3 + 800065c: f002 fbf0 bl 8002e40 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000660: 463b mov r3, r7 + 8000662: 2200 movs r2, #0 + 8000664: 601a str r2, [r3, #0] + 8000666: 605a str r2, [r3, #4] + 8000668: 609a str r2, [r3, #8] + 800066a: 60da str r2, [r3, #12] + 800066c: 611a str r2, [r3, #16] + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 800066e: 4b19 ldr r3, [pc, #100] @ (80006d4 ) + 8000670: 681b ldr r3, [r3, #0] + 8000672: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 8000676: 4a17 ldr r2, [pc, #92] @ (80006d4 ) + 8000678: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 800067c: 6013 str r3, [r2, #0] + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 800067e: 2302 movs r3, #2 + 8000680: 617b str r3, [r7, #20] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8000682: 2301 movs r3, #1 + 8000684: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000686: 2310 movs r3, #16 + 8000688: 627b str r3, [r7, #36] @ 0x24 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 800068a: 2300 movs r3, #0 + 800068c: 63bb str r3, [r7, #56] @ 0x38 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 800068e: f107 0314 add.w r3, r7, #20 + 8000692: 4618 mov r0, r3 + 8000694: f000 fe7c bl 8001390 + 8000698: 4603 mov r3, r0 + 800069a: 2b00 cmp r3, #0 + 800069c: d001 beq.n 80006a2 + { + Error_Handler(); + 800069e: f000 f94b bl 8000938 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 80006a2: 230f movs r3, #15 + 80006a4: 603b str r3, [r7, #0] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 80006a6: 2301 movs r3, #1 + 80006a8: 607b str r3, [r7, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80006aa: 2300 movs r3, #0 + 80006ac: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80006ae: 2300 movs r3, #0 + 80006b0: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80006b2: 2300 movs r3, #0 + 80006b4: 613b str r3, [r7, #16] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 80006b6: 463b mov r3, r7 + 80006b8: 2100 movs r1, #0 + 80006ba: 4618 mov r0, r3 + 80006bc: f001 f998 bl 80019f0 + 80006c0: 4603 mov r3, r0 + 80006c2: 2b00 cmp r3, #0 + 80006c4: d001 beq.n 80006ca + { + Error_Handler(); + 80006c6: f000 f937 bl 8000938 + } +} + 80006ca: bf00 nop + 80006cc: 3748 adds r7, #72 @ 0x48 + 80006ce: 46bd mov sp, r7 + 80006d0: bd80 pop {r7, pc} + 80006d2: bf00 nop + 80006d4: 40007000 .word 0x40007000 + +080006d8 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 80006d8: b580 push {r7, lr} + 80006da: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 80006dc: 4b17 ldr r3, [pc, #92] @ (800073c ) + 80006de: 4a18 ldr r2, [pc, #96] @ (8000740 ) + 80006e0: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 80006e2: 4b16 ldr r3, [pc, #88] @ (800073c ) + 80006e4: f44f 7282 mov.w r2, #260 @ 0x104 + 80006e8: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 80006ea: 4b14 ldr r3, [pc, #80] @ (800073c ) + 80006ec: 2200 movs r2, #0 + 80006ee: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 80006f0: 4b12 ldr r3, [pc, #72] @ (800073c ) + 80006f2: 2200 movs r2, #0 + 80006f4: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 80006f6: 4b11 ldr r3, [pc, #68] @ (800073c ) + 80006f8: 2200 movs r2, #0 + 80006fa: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 80006fc: 4b0f ldr r3, [pc, #60] @ (800073c ) + 80006fe: 2200 movs r2, #0 + 8000700: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 8000702: 4b0e ldr r3, [pc, #56] @ (800073c ) + 8000704: f44f 7200 mov.w r2, #512 @ 0x200 + 8000708: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 800070a: 4b0c ldr r3, [pc, #48] @ (800073c ) + 800070c: 2200 movs r2, #0 + 800070e: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 8000710: 4b0a ldr r3, [pc, #40] @ (800073c ) + 8000712: 2200 movs r2, #0 + 8000714: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 8000716: 4b09 ldr r3, [pc, #36] @ (800073c ) + 8000718: 2200 movs r2, #0 + 800071a: 625a str r2, [r3, #36] @ 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 800071c: 4b07 ldr r3, [pc, #28] @ (800073c ) + 800071e: 2200 movs r2, #0 + 8000720: 629a str r2, [r3, #40] @ 0x28 + hspi1.Init.CRCPolynomial = 10; + 8000722: 4b06 ldr r3, [pc, #24] @ (800073c ) + 8000724: 220a movs r2, #10 + 8000726: 62da str r2, [r3, #44] @ 0x2c + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8000728: 4804 ldr r0, [pc, #16] @ (800073c ) + 800072a: f001 fbb3 bl 8001e94 + 800072e: 4603 mov r3, r0 + 8000730: 2b00 cmp r3, #0 + 8000732: d001 beq.n 8000738 + { + Error_Handler(); + 8000734: f000 f900 bl 8000938 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 8000738: bf00 nop + 800073a: bd80 pop {r7, pc} + 800073c: 20000028 .word 0x20000028 + 8000740: 40013000 .word 0x40013000 + +08000744 : + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + 8000744: b580 push {r7, lr} + 8000746: b08a sub sp, #40 @ 0x28 + 8000748: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800074a: f107 0318 add.w r3, r7, #24 + 800074e: 2200 movs r2, #0 + 8000750: 601a str r2, [r3, #0] + 8000752: 605a str r2, [r3, #4] + 8000754: 609a str r2, [r3, #8] + 8000756: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8000758: f107 0310 add.w r3, r7, #16 + 800075c: 2200 movs r2, #0 + 800075e: 601a str r2, [r3, #0] + 8000760: 605a str r2, [r3, #4] + TIM_OC_InitTypeDef sConfigOC = {0}; + 8000762: 463b mov r3, r7 + 8000764: 2200 movs r2, #0 + 8000766: 601a str r2, [r3, #0] + 8000768: 605a str r2, [r3, #4] + 800076a: 609a str r2, [r3, #8] + 800076c: 60da str r2, [r3, #12] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 800076e: 4b2d ldr r3, [pc, #180] @ (8000824 ) + 8000770: 4a2d ldr r2, [pc, #180] @ (8000828 ) + 8000772: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 19-1; + 8000774: 4b2b ldr r3, [pc, #172] @ (8000824 ) + 8000776: 2212 movs r2, #18 + 8000778: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 800077a: 4b2a ldr r3, [pc, #168] @ (8000824 ) + 800077c: 2200 movs r2, #0 + 800077e: 609a str r2, [r3, #8] + htim3.Init.Period = 1600-1; + 8000780: 4b28 ldr r3, [pc, #160] @ (8000824 ) + 8000782: f240 623f movw r2, #1599 @ 0x63f + 8000786: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8000788: 4b26 ldr r3, [pc, #152] @ (8000824 ) + 800078a: 2200 movs r2, #0 + 800078c: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 800078e: 4b25 ldr r3, [pc, #148] @ (8000824 ) + 8000790: 2280 movs r2, #128 @ 0x80 + 8000792: 615a str r2, [r3, #20] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + 8000794: 4823 ldr r0, [pc, #140] @ (8000824 ) + 8000796: f001 fe27 bl 80023e8 + 800079a: 4603 mov r3, r0 + 800079c: 2b00 cmp r3, #0 + 800079e: d001 beq.n 80007a4 + { + Error_Handler(); + 80007a0: f000 f8ca bl 8000938 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 80007a4: f44f 5380 mov.w r3, #4096 @ 0x1000 + 80007a8: 61bb str r3, [r7, #24] + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + 80007aa: f107 0318 add.w r3, r7, #24 + 80007ae: 4619 mov r1, r3 + 80007b0: 481c ldr r0, [pc, #112] @ (8000824 ) + 80007b2: f001 fff9 bl 80027a8 + 80007b6: 4603 mov r3, r0 + 80007b8: 2b00 cmp r3, #0 + 80007ba: d001 beq.n 80007c0 + { + Error_Handler(); + 80007bc: f000 f8bc bl 8000938 + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + 80007c0: 4818 ldr r0, [pc, #96] @ (8000824 ) + 80007c2: f001 fe50 bl 8002466 + 80007c6: 4603 mov r3, r0 + 80007c8: 2b00 cmp r3, #0 + 80007ca: d001 beq.n 80007d0 + { + Error_Handler(); + 80007cc: f000 f8b4 bl 8000938 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80007d0: 2300 movs r3, #0 + 80007d2: 613b str r3, [r7, #16] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80007d4: 2300 movs r3, #0 + 80007d6: 617b str r3, [r7, #20] + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 80007d8: f107 0310 add.w r3, r7, #16 + 80007dc: 4619 mov r1, r3 + 80007de: 4811 ldr r0, [pc, #68] @ (8000824 ) + 80007e0: f002 fad0 bl 8002d84 + 80007e4: 4603 mov r3, r0 + 80007e6: 2b00 cmp r3, #0 + 80007e8: d001 beq.n 80007ee + { + Error_Handler(); + 80007ea: f000 f8a5 bl 8000938 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 80007ee: 2360 movs r3, #96 @ 0x60 + 80007f0: 603b str r3, [r7, #0] + sConfigOC.Pulse = 800-1; + 80007f2: f240 331f movw r3, #799 @ 0x31f + 80007f6: 607b str r3, [r7, #4] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 80007f8: 2300 movs r3, #0 + 80007fa: 60bb str r3, [r7, #8] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 80007fc: 2300 movs r3, #0 + 80007fe: 60fb str r3, [r7, #12] + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 8000800: 463b mov r3, r7 + 8000802: 2200 movs r2, #0 + 8000804: 4619 mov r1, r3 + 8000806: 4807 ldr r0, [pc, #28] @ (8000824 ) + 8000808: f001 ff0c bl 8002624 + 800080c: 4603 mov r3, r0 + 800080e: 2b00 cmp r3, #0 + 8000810: d001 beq.n 8000816 + { + Error_Handler(); + 8000812: f000 f891 bl 8000938 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + 8000816: 4803 ldr r0, [pc, #12] @ (8000824 ) + 8000818: f000 f924 bl 8000a64 + +} + 800081c: bf00 nop + 800081e: 3728 adds r7, #40 @ 0x28 + 8000820: 46bd mov sp, r7 + 8000822: bd80 pop {r7, pc} + 8000824: 20000080 .word 0x20000080 + 8000828: 40000400 .word 0x40000400 + +0800082c : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 800082c: b580 push {r7, lr} + 800082e: b088 sub sp, #32 + 8000830: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000832: f107 030c add.w r3, r7, #12 + 8000836: 2200 movs r2, #0 + 8000838: 601a str r2, [r3, #0] + 800083a: 605a str r2, [r3, #4] + 800083c: 609a str r2, [r3, #8] + 800083e: 60da str r2, [r3, #12] + 8000840: 611a str r2, [r3, #16] + /* USER CODE BEGIN MX_GPIO_Init_1 */ + + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000842: 4b39 ldr r3, [pc, #228] @ (8000928 ) + 8000844: 69db ldr r3, [r3, #28] + 8000846: 4a38 ldr r2, [pc, #224] @ (8000928 ) + 8000848: f043 0304 orr.w r3, r3, #4 + 800084c: 61d3 str r3, [r2, #28] + 800084e: 4b36 ldr r3, [pc, #216] @ (8000928 ) + 8000850: 69db ldr r3, [r3, #28] + 8000852: f003 0304 and.w r3, r3, #4 + 8000856: 60bb str r3, [r7, #8] + 8000858: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800085a: 4b33 ldr r3, [pc, #204] @ (8000928 ) + 800085c: 69db ldr r3, [r3, #28] + 800085e: 4a32 ldr r2, [pc, #200] @ (8000928 ) + 8000860: f043 0301 orr.w r3, r3, #1 + 8000864: 61d3 str r3, [r2, #28] + 8000866: 4b30 ldr r3, [pc, #192] @ (8000928 ) + 8000868: 69db ldr r3, [r3, #28] + 800086a: f003 0301 and.w r3, r3, #1 + 800086e: 607b str r3, [r7, #4] + 8000870: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000872: 4b2d ldr r3, [pc, #180] @ (8000928 ) + 8000874: 69db ldr r3, [r3, #28] + 8000876: 4a2c ldr r2, [pc, #176] @ (8000928 ) + 8000878: f043 0302 orr.w r3, r3, #2 + 800087c: 61d3 str r3, [r2, #28] + 800087e: 4b2a ldr r3, [pc, #168] @ (8000928 ) + 8000880: 69db ldr r3, [r3, #28] + 8000882: f003 0302 and.w r3, r3, #2 + 8000886: 603b str r3, [r7, #0] + 8000888: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); + 800088a: 2200 movs r2, #0 + 800088c: 2101 movs r1, #1 + 800088e: 4827 ldr r0, [pc, #156] @ (800092c ) + 8000890: f000 fd44 bl 800131c + + /*Configure GPIO pin : PC0 */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 8000894: 2301 movs r3, #1 + 8000896: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000898: 2301 movs r3, #1 + 800089a: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800089c: 2300 movs r3, #0 + 800089e: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80008a0: 2300 movs r3, #0 + 80008a2: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80008a4: f107 030c add.w r3, r7, #12 + 80008a8: 4619 mov r1, r3 + 80008aa: 4820 ldr r0, [pc, #128] @ (800092c ) + 80008ac: f000 fba6 bl 8000ffc + + /*Configure GPIO pin : PB15 */ + GPIO_InitStruct.Pin = GPIO_PIN_15; + 80008b0: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80008b4: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80008b6: 2302 movs r3, #2 + 80008b8: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008ba: 2300 movs r3, #0 + 80008bc: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80008be: 2300 movs r3, #0 + 80008c0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + 80008c2: 2303 movs r3, #3 + 80008c4: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80008c6: f107 030c add.w r3, r7, #12 + 80008ca: 4619 mov r1, r3 + 80008cc: 4818 ldr r0, [pc, #96] @ (8000930 ) + 80008ce: f000 fb95 bl 8000ffc + + /*Configure GPIO pins : PA11 PA12 */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 80008d2: f44f 53c0 mov.w r3, #6144 @ 0x1800 + 80008d6: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + 80008d8: f44f 1388 mov.w r3, #1114112 @ 0x110000 + 80008dc: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008de: 2300 movs r3, #0 + 80008e0: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80008e2: f107 030c add.w r3, r7, #12 + 80008e6: 4619 mov r1, r3 + 80008e8: 4812 ldr r0, [pc, #72] @ (8000934 ) + 80008ea: f000 fb87 bl 8000ffc + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + 80008ee: 2380 movs r3, #128 @ 0x80 + 80008f0: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80008f2: 2302 movs r3, #2 + 80008f4: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80008f6: 2300 movs r3, #0 + 80008f8: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80008fa: 2300 movs r3, #0 + 80008fc: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 80008fe: 2302 movs r3, #2 + 8000900: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000902: f107 030c add.w r3, r7, #12 + 8000906: 4619 mov r1, r3 + 8000908: 4809 ldr r0, [pc, #36] @ (8000930 ) + 800090a: f000 fb77 bl 8000ffc + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + 800090e: 2200 movs r2, #0 + 8000910: 2100 movs r1, #0 + 8000912: 2028 movs r0, #40 @ 0x28 + 8000914: f000 fb3b bl 8000f8e + HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); + 8000918: 2028 movs r0, #40 @ 0x28 + 800091a: f000 fb54 bl 8000fc6 + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + + /* USER CODE END MX_GPIO_Init_2 */ +} + 800091e: bf00 nop + 8000920: 3720 adds r7, #32 + 8000922: 46bd mov sp, r7 + 8000924: bd80 pop {r7, pc} + 8000926: bf00 nop + 8000928: 40023800 .word 0x40023800 + 800092c: 40020800 .word 0x40020800 + 8000930: 40020400 .word 0x40020400 + 8000934: 40020000 .word 0x40020000 + +08000938 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000938: b480 push {r7} + 800093a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 800093c: b672 cpsid i +} + 800093e: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8000940: bf00 nop + 8000942: e7fd b.n 8000940 + +08000944 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000944: b480 push {r7} + 8000946: b085 sub sp, #20 + 8000948: af00 add r7, sp, #0 + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_COMP_CLK_ENABLE(); + 800094a: 4b14 ldr r3, [pc, #80] @ (800099c ) + 800094c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800094e: 4a13 ldr r2, [pc, #76] @ (800099c ) + 8000950: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 8000954: 6253 str r3, [r2, #36] @ 0x24 + 8000956: 4b11 ldr r3, [pc, #68] @ (800099c ) + 8000958: 6a5b ldr r3, [r3, #36] @ 0x24 + 800095a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 800095e: 60fb str r3, [r7, #12] + 8000960: 68fb ldr r3, [r7, #12] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000962: 4b0e ldr r3, [pc, #56] @ (800099c ) + 8000964: 6a1b ldr r3, [r3, #32] + 8000966: 4a0d ldr r2, [pc, #52] @ (800099c ) + 8000968: f043 0301 orr.w r3, r3, #1 + 800096c: 6213 str r3, [r2, #32] + 800096e: 4b0b ldr r3, [pc, #44] @ (800099c ) + 8000970: 6a1b ldr r3, [r3, #32] + 8000972: f003 0301 and.w r3, r3, #1 + 8000976: 60bb str r3, [r7, #8] + 8000978: 68bb ldr r3, [r7, #8] + __HAL_RCC_PWR_CLK_ENABLE(); + 800097a: 4b08 ldr r3, [pc, #32] @ (800099c ) + 800097c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800097e: 4a07 ldr r2, [pc, #28] @ (800099c ) + 8000980: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000984: 6253 str r3, [r2, #36] @ 0x24 + 8000986: 4b05 ldr r3, [pc, #20] @ (800099c ) + 8000988: 6a5b ldr r3, [r3, #36] @ 0x24 + 800098a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800098e: 607b str r3, [r7, #4] + 8000990: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000992: bf00 nop + 8000994: 3714 adds r7, #20 + 8000996: 46bd mov sp, r7 + 8000998: bc80 pop {r7} + 800099a: 4770 bx lr + 800099c: 40023800 .word 0x40023800 + +080009a0 : + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 80009a0: b580 push {r7, lr} + 80009a2: b08a sub sp, #40 @ 0x28 + 80009a4: af00 add r7, sp, #0 + 80009a6: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80009a8: f107 0314 add.w r3, r7, #20 + 80009ac: 2200 movs r2, #0 + 80009ae: 601a str r2, [r3, #0] + 80009b0: 605a str r2, [r3, #4] + 80009b2: 609a str r2, [r3, #8] + 80009b4: 60da str r2, [r3, #12] + 80009b6: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 80009b8: 687b ldr r3, [r7, #4] + 80009ba: 681b ldr r3, [r3, #0] + 80009bc: 4a17 ldr r2, [pc, #92] @ (8000a1c ) + 80009be: 4293 cmp r3, r2 + 80009c0: d127 bne.n 8000a12 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 80009c2: 4b17 ldr r3, [pc, #92] @ (8000a20 ) + 80009c4: 6a1b ldr r3, [r3, #32] + 80009c6: 4a16 ldr r2, [pc, #88] @ (8000a20 ) + 80009c8: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 80009cc: 6213 str r3, [r2, #32] + 80009ce: 4b14 ldr r3, [pc, #80] @ (8000a20 ) + 80009d0: 6a1b ldr r3, [r3, #32] + 80009d2: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80009d6: 613b str r3, [r7, #16] + 80009d8: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80009da: 4b11 ldr r3, [pc, #68] @ (8000a20 ) + 80009dc: 69db ldr r3, [r3, #28] + 80009de: 4a10 ldr r2, [pc, #64] @ (8000a20 ) + 80009e0: f043 0301 orr.w r3, r3, #1 + 80009e4: 61d3 str r3, [r2, #28] + 80009e6: 4b0e ldr r3, [pc, #56] @ (8000a20 ) + 80009e8: 69db ldr r3, [r3, #28] + 80009ea: f003 0301 and.w r3, r3, #1 + 80009ee: 60fb str r3, [r7, #12] + 80009f0: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 80009f2: 23e0 movs r3, #224 @ 0xe0 + 80009f4: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80009f6: 2302 movs r3, #2 + 80009f8: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80009fa: 2300 movs r3, #0 + 80009fc: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80009fe: 2303 movs r3, #3 + 8000a00: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 8000a02: 2305 movs r3, #5 + 8000a04: 627b str r3, [r7, #36] @ 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000a06: f107 0314 add.w r3, r7, #20 + 8000a0a: 4619 mov r1, r3 + 8000a0c: 4805 ldr r0, [pc, #20] @ (8000a24 ) + 8000a0e: f000 faf5 bl 8000ffc + + /* USER CODE END SPI1_MspInit 1 */ + + } + +} + 8000a12: bf00 nop + 8000a14: 3728 adds r7, #40 @ 0x28 + 8000a16: 46bd mov sp, r7 + 8000a18: bd80 pop {r7, pc} + 8000a1a: bf00 nop + 8000a1c: 40013000 .word 0x40013000 + 8000a20: 40023800 .word 0x40023800 + 8000a24: 40020000 .word 0x40020000 + +08000a28 : + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8000a28: b480 push {r7} + 8000a2a: b085 sub sp, #20 + 8000a2c: af00 add r7, sp, #0 + 8000a2e: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM3) + 8000a30: 687b ldr r3, [r7, #4] + 8000a32: 681b ldr r3, [r3, #0] + 8000a34: 4a09 ldr r2, [pc, #36] @ (8000a5c ) + 8000a36: 4293 cmp r3, r2 + 8000a38: d10b bne.n 8000a52 + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + 8000a3a: 4b09 ldr r3, [pc, #36] @ (8000a60 ) + 8000a3c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000a3e: 4a08 ldr r2, [pc, #32] @ (8000a60 ) + 8000a40: f043 0302 orr.w r3, r3, #2 + 8000a44: 6253 str r3, [r2, #36] @ 0x24 + 8000a46: 4b06 ldr r3, [pc, #24] @ (8000a60 ) + 8000a48: 6a5b ldr r3, [r3, #36] @ 0x24 + 8000a4a: f003 0302 and.w r3, r3, #2 + 8000a4e: 60fb str r3, [r7, #12] + 8000a50: 68fb ldr r3, [r7, #12] + + /* USER CODE END TIM3_MspInit 1 */ + + } + +} + 8000a52: bf00 nop + 8000a54: 3714 adds r7, #20 + 8000a56: 46bd mov sp, r7 + 8000a58: bc80 pop {r7} + 8000a5a: 4770 bx lr + 8000a5c: 40000400 .word 0x40000400 + 8000a60: 40023800 .word 0x40023800 + +08000a64 : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8000a64: b580 push {r7, lr} + 8000a66: b088 sub sp, #32 + 8000a68: af00 add r7, sp, #0 + 8000a6a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000a6c: f107 030c add.w r3, r7, #12 + 8000a70: 2200 movs r2, #0 + 8000a72: 601a str r2, [r3, #0] + 8000a74: 605a str r2, [r3, #4] + 8000a76: 609a str r2, [r3, #8] + 8000a78: 60da str r2, [r3, #12] + 8000a7a: 611a str r2, [r3, #16] + if(htim->Instance==TIM3) + 8000a7c: 687b ldr r3, [r7, #4] + 8000a7e: 681b ldr r3, [r3, #0] + 8000a80: 4a11 ldr r2, [pc, #68] @ (8000ac8 ) + 8000a82: 4293 cmp r3, r2 + 8000a84: d11b bne.n 8000abe + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000a86: 4b11 ldr r3, [pc, #68] @ (8000acc ) + 8000a88: 69db ldr r3, [r3, #28] + 8000a8a: 4a10 ldr r2, [pc, #64] @ (8000acc ) + 8000a8c: f043 0304 orr.w r3, r3, #4 + 8000a90: 61d3 str r3, [r2, #28] + 8000a92: 4b0e ldr r3, [pc, #56] @ (8000acc ) + 8000a94: 69db ldr r3, [r3, #28] + 8000a96: f003 0304 and.w r3, r3, #4 + 8000a9a: 60bb str r3, [r7, #8] + 8000a9c: 68bb ldr r3, [r7, #8] + /**TIM3 GPIO Configuration + PC6 ------> TIM3_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_6; + 8000a9e: 2340 movs r3, #64 @ 0x40 + 8000aa0: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8000aa2: 2302 movs r3, #2 + 8000aa4: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000aa6: 2300 movs r3, #0 + 8000aa8: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000aaa: 2300 movs r3, #0 + 8000aac: 61bb str r3, [r7, #24] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 8000aae: 2302 movs r3, #2 + 8000ab0: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8000ab2: f107 030c add.w r3, r7, #12 + 8000ab6: 4619 mov r1, r3 + 8000ab8: 4805 ldr r0, [pc, #20] @ (8000ad0 ) + 8000aba: f000 fa9f bl 8000ffc + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + +} + 8000abe: bf00 nop + 8000ac0: 3720 adds r7, #32 + 8000ac2: 46bd mov sp, r7 + 8000ac4: bd80 pop {r7, pc} + 8000ac6: bf00 nop + 8000ac8: 40000400 .word 0x40000400 + 8000acc: 40023800 .word 0x40023800 + 8000ad0: 40020800 .word 0x40020800 + +08000ad4 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000ad4: b480 push {r7} + 8000ad6: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000ad8: bf00 nop + 8000ada: e7fd b.n 8000ad8 + +08000adc : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000adc: b480 push {r7} + 8000ade: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000ae0: bf00 nop + 8000ae2: e7fd b.n 8000ae0 + +08000ae4 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000ae4: b480 push {r7} + 8000ae6: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000ae8: bf00 nop + 8000aea: e7fd b.n 8000ae8 + +08000aec : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000aec: b480 push {r7} + 8000aee: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000af0: bf00 nop + 8000af2: e7fd b.n 8000af0 + +08000af4 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000af4: b480 push {r7} + 8000af6: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000af8: bf00 nop + 8000afa: e7fd b.n 8000af8 + +08000afc : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000afc: b480 push {r7} + 8000afe: af00 add r7, sp, #0 + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000b00: bf00 nop + 8000b02: 46bd mov sp, r7 + 8000b04: bc80 pop {r7} + 8000b06: 4770 bx lr + +08000b08 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000b08: b480 push {r7} + 8000b0a: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000b0c: bf00 nop + 8000b0e: 46bd mov sp, r7 + 8000b10: bc80 pop {r7} + 8000b12: 4770 bx lr + +08000b14 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000b14: b480 push {r7} + 8000b16: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000b18: bf00 nop + 8000b1a: 46bd mov sp, r7 + 8000b1c: bc80 pop {r7} + 8000b1e: 4770 bx lr + +08000b20 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000b20: b580 push {r7, lr} + 8000b22: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000b24: f000 f91e bl 8000d64 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000b28: bf00 nop + 8000b2a: bd80 pop {r7, pc} + +08000b2c : + +/** + * @brief This function handles EXTI line[15:10] interrupts. + */ +void EXTI15_10_IRQHandler(void) +{ + 8000b2c: b580 push {r7, lr} + 8000b2e: af00 add r7, sp, #0 + /* USER CODE BEGIN EXTI15_10_IRQn 0 */ + + /* USER CODE END EXTI15_10_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + 8000b30: f44f 6000 mov.w r0, #2048 @ 0x800 + 8000b34: f000 fc0a bl 800134c + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + 8000b38: f44f 5080 mov.w r0, #4096 @ 0x1000 + 8000b3c: f000 fc06 bl 800134c + /* USER CODE BEGIN EXTI15_10_IRQn 1 */ + + /* USER CODE END EXTI15_10_IRQn 1 */ +} + 8000b40: bf00 nop + 8000b42: bd80 pop {r7, pc} + +08000b44 : + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000b44: b480 push {r7} + 8000b46: af00 add r7, sp, #0 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000b48: bf00 nop + 8000b4a: 46bd mov sp, r7 + 8000b4c: bc80 pop {r7} + 8000b4e: 4770 bx lr + +08000b50 : + .type Reset_Handler, %function +Reset_Handler: + + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000b50: f7ff fff8 bl 8000b44 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000b54: 480b ldr r0, [pc, #44] @ (8000b84 ) + ldr r1, =_edata + 8000b56: 490c ldr r1, [pc, #48] @ (8000b88 ) + ldr r2, =_sidata + 8000b58: 4a0c ldr r2, [pc, #48] @ (8000b8c ) + movs r3, #0 + 8000b5a: 2300 movs r3, #0 + b LoopCopyDataInit + 8000b5c: e002 b.n 8000b64 + +08000b5e : + +CopyDataInit: + ldr r4, [r2, r3] + 8000b5e: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000b60: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000b62: 3304 adds r3, #4 + +08000b64 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000b64: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000b66: 428c cmp r4, r1 + bcc CopyDataInit + 8000b68: d3f9 bcc.n 8000b5e + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000b6a: 4a09 ldr r2, [pc, #36] @ (8000b90 ) + ldr r4, =_ebss + 8000b6c: 4c09 ldr r4, [pc, #36] @ (8000b94 ) + movs r3, #0 + 8000b6e: 2300 movs r3, #0 + b LoopFillZerobss + 8000b70: e001 b.n 8000b76 + +08000b72 : + +FillZerobss: + str r3, [r2] + 8000b72: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000b74: 3204 adds r2, #4 + +08000b76 : + +LoopFillZerobss: + cmp r2, r4 + 8000b76: 42a2 cmp r2, r4 + bcc FillZerobss + 8000b78: d3fb bcc.n 8000b72 + +/* Call static constructors */ + bl __libc_init_array + 8000b7a: f002 f969 bl 8002e50 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8000b7e: f7ff fcb9 bl 80004f4
+ bx lr + 8000b82: 4770 bx lr + ldr r0, =_sdata + 8000b84: 20000000 .word 0x20000000 + ldr r1, =_edata + 8000b88: 2000000c .word 0x2000000c + ldr r2, =_sidata + 8000b8c: 08002efc .word 0x08002efc + ldr r2, =_sbss + 8000b90: 2000000c .word 0x2000000c + ldr r4, =_ebss + 8000b94: 200000c4 .word 0x200000c4 + +08000b98 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000b98: e7fe b.n 8000b98 + +08000b9a : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + 8000b9a: b580 push {r7, lr} + 8000b9c: af00 add r7, sp, #0 + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + 8000b9e: 2107 movs r1, #7 + 8000ba0: 200b movs r0, #11 + 8000ba2: f000 f85d bl 8000c60 + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + 8000ba6: 2100 movs r1, #0 + 8000ba8: 2009 movs r0, #9 + 8000baa: f000 f859 bl 8000c60 + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + 8000bae: f000 f809 bl 8000bc4 + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + 8000bb2: f000 f80f bl 8000bd4 + MAX7219_Clear(); // clear all digits + 8000bb6: f000 f827 bl 8000c08 + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity + 8000bba: 200f movs r0, #15 + 8000bbc: f000 f812 bl 8000be4 +} + 8000bc0: bf00 nop + 8000bc2: bd80 pop {r7, pc} + +08000bc4 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + 8000bc4: b580 push {r7, lr} + 8000bc6: af00 add r7, sp, #0 + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode + 8000bc8: 2101 movs r1, #1 + 8000bca: 200c movs r0, #12 + 8000bcc: f000 f848 bl 8000c60 +} + 8000bd0: bf00 nop + 8000bd2: bd80 pop {r7, pc} + +08000bd4 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + 8000bd4: b580 push {r7, lr} + 8000bd6: af00 add r7, sp, #0 + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode + 8000bd8: 2100 movs r1, #0 + 8000bda: 200f movs r0, #15 + 8000bdc: f000 f840 bl 8000c60 +} + 8000be0: bf00 nop + 8000be2: bd80 pop {r7, pc} + +08000be4 : +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + 8000be4: b580 push {r7, lr} + 8000be6: b082 sub sp, #8 + 8000be8: af00 add r7, sp, #0 + 8000bea: 4603 mov r3, r0 + 8000bec: 71fb strb r3, [r7, #7] + brightness &= 0x0f; // mask off extra bits + 8000bee: 79fb ldrb r3, [r7, #7] + 8000bf0: f003 030f and.w r3, r3, #15 + 8000bf4: 71fb strb r3, [r7, #7] + MAX7219_Write(REG_INTENSITY, brightness); // set brightness + 8000bf6: 79fb ldrb r3, [r7, #7] + 8000bf8: 4619 mov r1, r3 + 8000bfa: 200a movs r0, #10 + 8000bfc: f000 f830 bl 8000c60 +} + 8000c00: bf00 nop + 8000c02: 3708 adds r7, #8 + 8000c04: 46bd mov sp, r7 + 8000c06: bd80 pop {r7, pc} + +08000c08 : +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + 8000c08: b580 push {r7, lr} + 8000c0a: b082 sub sp, #8 + 8000c0c: af00 add r7, sp, #0 + char i; + for (i=0; i < 8; i++) + 8000c0e: 2300 movs r3, #0 + 8000c10: 71fb strb r3, [r7, #7] + 8000c12: e007 b.n 8000c24 + MAX7219_Write(i, 0x00); // turn all segments off + 8000c14: 79fb ldrb r3, [r7, #7] + 8000c16: 2100 movs r1, #0 + 8000c18: 4618 mov r0, r3 + 8000c1a: f000 f821 bl 8000c60 + for (i=0; i < 8; i++) + 8000c1e: 79fb ldrb r3, [r7, #7] + 8000c20: 3301 adds r3, #1 + 8000c22: 71fb strb r3, [r7, #7] + 8000c24: 79fb ldrb r3, [r7, #7] + 8000c26: 2b07 cmp r3, #7 + 8000c28: d9f4 bls.n 8000c14 +} + 8000c2a: bf00 nop + 8000c2c: bf00 nop + 8000c2e: 3708 adds r7, #8 + 8000c30: 46bd mov sp, r7 + 8000c32: bd80 pop {r7, pc} + +08000c34 : +* character = character to display (0-9, A-Z) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayChar(char digit, char character) +{ + 8000c34: b580 push {r7, lr} + 8000c36: b082 sub sp, #8 + 8000c38: af00 add r7, sp, #0 + 8000c3a: 4603 mov r3, r0 + 8000c3c: 460a mov r2, r1 + 8000c3e: 71fb strb r3, [r7, #7] + 8000c40: 4613 mov r3, r2 + 8000c42: 71bb strb r3, [r7, #6] + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]); + 8000c44: 79bb ldrb r3, [r7, #6] + 8000c46: 4a05 ldr r2, [pc, #20] @ (8000c5c ) + 8000c48: 5cd2 ldrb r2, [r2, r3] + 8000c4a: 79fb ldrb r3, [r7, #7] + 8000c4c: 4611 mov r1, r2 + 8000c4e: 4618 mov r0, r3 + 8000c50: f000 f806 bl 8000c60 +} + 8000c54: bf00 nop + 8000c56: 3708 adds r7, #8 + 8000c58: 46bd mov sp, r7 + 8000c5a: bd80 pop {r7, pc} + 8000c5c: 08002edc .word 0x08002edc + +08000c60 : +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + 8000c60: b580 push {r7, lr} + 8000c62: b082 sub sp, #8 + 8000c64: af00 add r7, sp, #0 + 8000c66: 4603 mov r3, r0 + 8000c68: 460a mov r2, r1 + 8000c6a: 71fb strb r3, [r7, #7] + 8000c6c: 4613 mov r3, r2 + 8000c6e: 71bb strb r3, [r7, #6] + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + 8000c70: 4b09 ldr r3, [pc, #36] @ (8000c98 ) + 8000c72: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000c76: 619a str r2, [r3, #24] + MAX7219_SendByte(reg_number); // write register number to MAX7219 + 8000c78: 79fb ldrb r3, [r7, #7] + 8000c7a: 4618 mov r0, r3 + 8000c7c: f000 f80e bl 8000c9c + MAX7219_SendByte(dataout); // write data to MAX7219 + 8000c80: 79bb ldrb r3, [r7, #6] + 8000c82: 4618 mov r0, r3 + 8000c84: f000 f80a bl 8000c9c + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + 8000c88: 4b03 ldr r3, [pc, #12] @ (8000c98 ) + 8000c8a: 2201 movs r2, #1 + 8000c8c: 619a str r2, [r3, #24] + } + 8000c8e: bf00 nop + 8000c90: 3708 adds r7, #8 + 8000c92: 46bd mov sp, r7 + 8000c94: bd80 pop {r7, pc} + 8000c96: bf00 nop + 8000c98: 40020800 .word 0x40020800 + +08000c9c : +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + 8000c9c: b580 push {r7, lr} + 8000c9e: b082 sub sp, #8 + 8000ca0: af00 add r7, sp, #0 + 8000ca2: 4603 mov r3, r0 + 8000ca4: 71fb strb r3, [r7, #7] + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + 8000ca6: 1df9 adds r1, r7, #7 + 8000ca8: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000cac: 2201 movs r2, #1 + 8000cae: 4803 ldr r0, [pc, #12] @ (8000cbc ) + 8000cb0: f001 f979 bl 8001fa6 + +} + 8000cb4: bf00 nop + 8000cb6: 3708 adds r7, #8 + 8000cb8: 46bd mov sp, r7 + 8000cba: bd80 pop {r7, pc} + 8000cbc: 20000028 .word 0x20000028 + +08000cc0 : + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000cc0: b580 push {r7, lr} + 8000cc2: b082 sub sp, #8 + 8000cc4: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8000cc6: 2300 movs r3, #0 + 8000cc8: 71fb strb r3, [r7, #7] +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000cca: 2003 movs r0, #3 + 8000ccc: f000 f954 bl 8000f78 + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000cd0: 200f movs r0, #15 + 8000cd2: f000 f80d bl 8000cf0 + 8000cd6: 4603 mov r3, r0 + 8000cd8: 2b00 cmp r3, #0 + 8000cda: d002 beq.n 8000ce2 + { + status = HAL_ERROR; + 8000cdc: 2301 movs r3, #1 + 8000cde: 71fb strb r3, [r7, #7] + 8000ce0: e001 b.n 8000ce6 + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8000ce2: f7ff fe2f bl 8000944 + } + + /* Return function status */ + return status; + 8000ce6: 79fb ldrb r3, [r7, #7] +} + 8000ce8: 4618 mov r0, r3 + 8000cea: 3708 adds r7, #8 + 8000cec: 46bd mov sp, r7 + 8000cee: bd80 pop {r7, pc} + +08000cf0 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000cf0: b580 push {r7, lr} + 8000cf2: b084 sub sp, #16 + 8000cf4: af00 add r7, sp, #0 + 8000cf6: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8000cf8: 2300 movs r3, #0 + 8000cfa: 73fb strb r3, [r7, #15] + + if (uwTickFreq != 0U) + 8000cfc: 4b16 ldr r3, [pc, #88] @ (8000d58 ) + 8000cfe: 681b ldr r3, [r3, #0] + 8000d00: 2b00 cmp r3, #0 + 8000d02: d022 beq.n 8000d4a + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + 8000d04: 4b15 ldr r3, [pc, #84] @ (8000d5c ) + 8000d06: 681a ldr r2, [r3, #0] + 8000d08: 4b13 ldr r3, [pc, #76] @ (8000d58 ) + 8000d0a: 681b ldr r3, [r3, #0] + 8000d0c: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8000d10: fbb1 f3f3 udiv r3, r1, r3 + 8000d14: fbb2 f3f3 udiv r3, r2, r3 + 8000d18: 4618 mov r0, r3 + 8000d1a: f000 f962 bl 8000fe2 + 8000d1e: 4603 mov r3, r0 + 8000d20: 2b00 cmp r3, #0 + 8000d22: d10f bne.n 8000d44 + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000d24: 687b ldr r3, [r7, #4] + 8000d26: 2b0f cmp r3, #15 + 8000d28: d809 bhi.n 8000d3e + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000d2a: 2200 movs r2, #0 + 8000d2c: 6879 ldr r1, [r7, #4] + 8000d2e: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000d32: f000 f92c bl 8000f8e + uwTickPrio = TickPriority; + 8000d36: 4a0a ldr r2, [pc, #40] @ (8000d60 ) + 8000d38: 687b ldr r3, [r7, #4] + 8000d3a: 6013 str r3, [r2, #0] + 8000d3c: e007 b.n 8000d4e + } + else + { + status = HAL_ERROR; + 8000d3e: 2301 movs r3, #1 + 8000d40: 73fb strb r3, [r7, #15] + 8000d42: e004 b.n 8000d4e + } + } + else + { + status = HAL_ERROR; + 8000d44: 2301 movs r3, #1 + 8000d46: 73fb strb r3, [r7, #15] + 8000d48: e001 b.n 8000d4e + } + } + else + { + status = HAL_ERROR; + 8000d4a: 2301 movs r3, #1 + 8000d4c: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8000d4e: 7bfb ldrb r3, [r7, #15] +} + 8000d50: 4618 mov r0, r3 + 8000d52: 3710 adds r7, #16 + 8000d54: 46bd mov sp, r7 + 8000d56: bd80 pop {r7, pc} + 8000d58: 20000008 .word 0x20000008 + 8000d5c: 20000000 .word 0x20000000 + 8000d60: 20000004 .word 0x20000004 + +08000d64 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000d64: b480 push {r7} + 8000d66: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8000d68: 4b05 ldr r3, [pc, #20] @ (8000d80 ) + 8000d6a: 681a ldr r2, [r3, #0] + 8000d6c: 4b05 ldr r3, [pc, #20] @ (8000d84 ) + 8000d6e: 681b ldr r3, [r3, #0] + 8000d70: 4413 add r3, r2 + 8000d72: 4a03 ldr r2, [pc, #12] @ (8000d80 ) + 8000d74: 6013 str r3, [r2, #0] +} + 8000d76: bf00 nop + 8000d78: 46bd mov sp, r7 + 8000d7a: bc80 pop {r7} + 8000d7c: 4770 bx lr + 8000d7e: bf00 nop + 8000d80: 200000c0 .word 0x200000c0 + 8000d84: 20000008 .word 0x20000008 + +08000d88 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8000d88: b480 push {r7} + 8000d8a: af00 add r7, sp, #0 + return uwTick; + 8000d8c: 4b02 ldr r3, [pc, #8] @ (8000d98 ) + 8000d8e: 681b ldr r3, [r3, #0] +} + 8000d90: 4618 mov r0, r3 + 8000d92: 46bd mov sp, r7 + 8000d94: bc80 pop {r7} + 8000d96: 4770 bx lr + 8000d98: 200000c0 .word 0x200000c0 + +08000d9c : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000d9c: b580 push {r7, lr} + 8000d9e: b084 sub sp, #16 + 8000da0: af00 add r7, sp, #0 + 8000da2: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8000da4: f7ff fff0 bl 8000d88 + 8000da8: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8000daa: 687b ldr r3, [r7, #4] + 8000dac: 60fb str r3, [r7, #12] + + /* Add a period to guaranty minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000dae: 68fb ldr r3, [r7, #12] + 8000db0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8000db4: d004 beq.n 8000dc0 + { + wait += (uint32_t)(uwTickFreq); + 8000db6: 4b09 ldr r3, [pc, #36] @ (8000ddc ) + 8000db8: 681b ldr r3, [r3, #0] + 8000dba: 68fa ldr r2, [r7, #12] + 8000dbc: 4413 add r3, r2 + 8000dbe: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 8000dc0: bf00 nop + 8000dc2: f7ff ffe1 bl 8000d88 + 8000dc6: 4602 mov r2, r0 + 8000dc8: 68bb ldr r3, [r7, #8] + 8000dca: 1ad3 subs r3, r2, r3 + 8000dcc: 68fa ldr r2, [r7, #12] + 8000dce: 429a cmp r2, r3 + 8000dd0: d8f7 bhi.n 8000dc2 + { + } +} + 8000dd2: bf00 nop + 8000dd4: bf00 nop + 8000dd6: 3710 adds r7, #16 + 8000dd8: 46bd mov sp, r7 + 8000dda: bd80 pop {r7, pc} + 8000ddc: 20000008 .word 0x20000008 + +08000de0 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000de0: b480 push {r7} + 8000de2: b085 sub sp, #20 + 8000de4: af00 add r7, sp, #0 + 8000de6: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000de8: 687b ldr r3, [r7, #4] + 8000dea: f003 0307 and.w r3, r3, #7 + 8000dee: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8000df0: 4b0c ldr r3, [pc, #48] @ (8000e24 <__NVIC_SetPriorityGrouping+0x44>) + 8000df2: 68db ldr r3, [r3, #12] + 8000df4: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8000df6: 68ba ldr r2, [r7, #8] + 8000df8: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000dfc: 4013 ands r3, r2 + 8000dfe: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8000e00: 68fb ldr r3, [r7, #12] + 8000e02: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8000e04: 68bb ldr r3, [r7, #8] + 8000e06: 4313 orrs r3, r2 + reg_value = (reg_value | + 8000e08: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000e0c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000e10: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8000e12: 4a04 ldr r2, [pc, #16] @ (8000e24 <__NVIC_SetPriorityGrouping+0x44>) + 8000e14: 68bb ldr r3, [r7, #8] + 8000e16: 60d3 str r3, [r2, #12] +} + 8000e18: bf00 nop + 8000e1a: 3714 adds r7, #20 + 8000e1c: 46bd mov sp, r7 + 8000e1e: bc80 pop {r7} + 8000e20: 4770 bx lr + 8000e22: bf00 nop + 8000e24: e000ed00 .word 0xe000ed00 + +08000e28 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8000e28: b480 push {r7} + 8000e2a: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8000e2c: 4b04 ldr r3, [pc, #16] @ (8000e40 <__NVIC_GetPriorityGrouping+0x18>) + 8000e2e: 68db ldr r3, [r3, #12] + 8000e30: 0a1b lsrs r3, r3, #8 + 8000e32: f003 0307 and.w r3, r3, #7 +} + 8000e36: 4618 mov r0, r3 + 8000e38: 46bd mov sp, r7 + 8000e3a: bc80 pop {r7} + 8000e3c: 4770 bx lr + 8000e3e: bf00 nop + 8000e40: e000ed00 .word 0xe000ed00 + +08000e44 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000e44: b480 push {r7} + 8000e46: b083 sub sp, #12 + 8000e48: af00 add r7, sp, #0 + 8000e4a: 4603 mov r3, r0 + 8000e4c: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000e4e: f997 3007 ldrsb.w r3, [r7, #7] + 8000e52: 2b00 cmp r3, #0 + 8000e54: db0b blt.n 8000e6e <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8000e56: 79fb ldrb r3, [r7, #7] + 8000e58: f003 021f and.w r2, r3, #31 + 8000e5c: 4906 ldr r1, [pc, #24] @ (8000e78 <__NVIC_EnableIRQ+0x34>) + 8000e5e: f997 3007 ldrsb.w r3, [r7, #7] + 8000e62: 095b lsrs r3, r3, #5 + 8000e64: 2001 movs r0, #1 + 8000e66: fa00 f202 lsl.w r2, r0, r2 + 8000e6a: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8000e6e: bf00 nop + 8000e70: 370c adds r7, #12 + 8000e72: 46bd mov sp, r7 + 8000e74: bc80 pop {r7} + 8000e76: 4770 bx lr + 8000e78: e000e100 .word 0xe000e100 + +08000e7c <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8000e7c: b480 push {r7} + 8000e7e: b083 sub sp, #12 + 8000e80: af00 add r7, sp, #0 + 8000e82: 4603 mov r3, r0 + 8000e84: 6039 str r1, [r7, #0] + 8000e86: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8000e88: f997 3007 ldrsb.w r3, [r7, #7] + 8000e8c: 2b00 cmp r3, #0 + 8000e8e: db0a blt.n 8000ea6 <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000e90: 683b ldr r3, [r7, #0] + 8000e92: b2da uxtb r2, r3 + 8000e94: 490c ldr r1, [pc, #48] @ (8000ec8 <__NVIC_SetPriority+0x4c>) + 8000e96: f997 3007 ldrsb.w r3, [r7, #7] + 8000e9a: 0112 lsls r2, r2, #4 + 8000e9c: b2d2 uxtb r2, r2 + 8000e9e: 440b add r3, r1 + 8000ea0: f883 2300 strb.w r2, [r3, #768] @ 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8000ea4: e00a b.n 8000ebc <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8000ea6: 683b ldr r3, [r7, #0] + 8000ea8: b2da uxtb r2, r3 + 8000eaa: 4908 ldr r1, [pc, #32] @ (8000ecc <__NVIC_SetPriority+0x50>) + 8000eac: 79fb ldrb r3, [r7, #7] + 8000eae: f003 030f and.w r3, r3, #15 + 8000eb2: 3b04 subs r3, #4 + 8000eb4: 0112 lsls r2, r2, #4 + 8000eb6: b2d2 uxtb r2, r2 + 8000eb8: 440b add r3, r1 + 8000eba: 761a strb r2, [r3, #24] +} + 8000ebc: bf00 nop + 8000ebe: 370c adds r7, #12 + 8000ec0: 46bd mov sp, r7 + 8000ec2: bc80 pop {r7} + 8000ec4: 4770 bx lr + 8000ec6: bf00 nop + 8000ec8: e000e100 .word 0xe000e100 + 8000ecc: e000ed00 .word 0xe000ed00 + +08000ed0 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000ed0: b480 push {r7} + 8000ed2: b089 sub sp, #36 @ 0x24 + 8000ed4: af00 add r7, sp, #0 + 8000ed6: 60f8 str r0, [r7, #12] + 8000ed8: 60b9 str r1, [r7, #8] + 8000eda: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8000edc: 68fb ldr r3, [r7, #12] + 8000ede: f003 0307 and.w r3, r3, #7 + 8000ee2: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8000ee4: 69fb ldr r3, [r7, #28] + 8000ee6: f1c3 0307 rsb r3, r3, #7 + 8000eea: 2b04 cmp r3, #4 + 8000eec: bf28 it cs + 8000eee: 2304 movcs r3, #4 + 8000ef0: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8000ef2: 69fb ldr r3, [r7, #28] + 8000ef4: 3304 adds r3, #4 + 8000ef6: 2b06 cmp r3, #6 + 8000ef8: d902 bls.n 8000f00 + 8000efa: 69fb ldr r3, [r7, #28] + 8000efc: 3b03 subs r3, #3 + 8000efe: e000 b.n 8000f02 + 8000f00: 2300 movs r3, #0 + 8000f02: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000f04: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000f08: 69bb ldr r3, [r7, #24] + 8000f0a: fa02 f303 lsl.w r3, r2, r3 + 8000f0e: 43da mvns r2, r3 + 8000f10: 68bb ldr r3, [r7, #8] + 8000f12: 401a ands r2, r3 + 8000f14: 697b ldr r3, [r7, #20] + 8000f16: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8000f18: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000f1c: 697b ldr r3, [r7, #20] + 8000f1e: fa01 f303 lsl.w r3, r1, r3 + 8000f22: 43d9 mvns r1, r3 + 8000f24: 687b ldr r3, [r7, #4] + 8000f26: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8000f28: 4313 orrs r3, r2 + ); +} + 8000f2a: 4618 mov r0, r3 + 8000f2c: 3724 adds r7, #36 @ 0x24 + 8000f2e: 46bd mov sp, r7 + 8000f30: bc80 pop {r7} + 8000f32: 4770 bx lr + +08000f34 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8000f34: b580 push {r7, lr} + 8000f36: b082 sub sp, #8 + 8000f38: af00 add r7, sp, #0 + 8000f3a: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000f3c: 687b ldr r3, [r7, #4] + 8000f3e: 3b01 subs r3, #1 + 8000f40: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000f44: d301 bcc.n 8000f4a + { + return (1UL); /* Reload value impossible */ + 8000f46: 2301 movs r3, #1 + 8000f48: e00f b.n 8000f6a + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000f4a: 4a0a ldr r2, [pc, #40] @ (8000f74 ) + 8000f4c: 687b ldr r3, [r7, #4] + 8000f4e: 3b01 subs r3, #1 + 8000f50: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 8000f52: 210f movs r1, #15 + 8000f54: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000f58: f7ff ff90 bl 8000e7c <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000f5c: 4b05 ldr r3, [pc, #20] @ (8000f74 ) + 8000f5e: 2200 movs r2, #0 + 8000f60: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000f62: 4b04 ldr r3, [pc, #16] @ (8000f74 ) + 8000f64: 2207 movs r2, #7 + 8000f66: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000f68: 2300 movs r3, #0 +} + 8000f6a: 4618 mov r0, r3 + 8000f6c: 3708 adds r7, #8 + 8000f6e: 46bd mov sp, r7 + 8000f70: bd80 pop {r7, pc} + 8000f72: bf00 nop + 8000f74: e000e010 .word 0xe000e010 + +08000f78 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8000f78: b580 push {r7, lr} + 8000f7a: b082 sub sp, #8 + 8000f7c: af00 add r7, sp, #0 + 8000f7e: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8000f80: 6878 ldr r0, [r7, #4] + 8000f82: f7ff ff2d bl 8000de0 <__NVIC_SetPriorityGrouping> +} + 8000f86: bf00 nop + 8000f88: 3708 adds r7, #8 + 8000f8a: 46bd mov sp, r7 + 8000f8c: bd80 pop {r7, pc} + +08000f8e : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8000f8e: b580 push {r7, lr} + 8000f90: b086 sub sp, #24 + 8000f92: af00 add r7, sp, #0 + 8000f94: 4603 mov r3, r0 + 8000f96: 60b9 str r1, [r7, #8] + 8000f98: 607a str r2, [r7, #4] + 8000f9a: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8000f9c: 2300 movs r3, #0 + 8000f9e: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8000fa0: f7ff ff42 bl 8000e28 <__NVIC_GetPriorityGrouping> + 8000fa4: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8000fa6: 687a ldr r2, [r7, #4] + 8000fa8: 68b9 ldr r1, [r7, #8] + 8000faa: 6978 ldr r0, [r7, #20] + 8000fac: f7ff ff90 bl 8000ed0 + 8000fb0: 4602 mov r2, r0 + 8000fb2: f997 300f ldrsb.w r3, [r7, #15] + 8000fb6: 4611 mov r1, r2 + 8000fb8: 4618 mov r0, r3 + 8000fba: f7ff ff5f bl 8000e7c <__NVIC_SetPriority> +} + 8000fbe: bf00 nop + 8000fc0: 3718 adds r7, #24 + 8000fc2: 46bd mov sp, r7 + 8000fc4: bd80 pop {r7, pc} + +08000fc6 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8000fc6: b580 push {r7, lr} + 8000fc8: b082 sub sp, #8 + 8000fca: af00 add r7, sp, #0 + 8000fcc: 4603 mov r3, r0 + 8000fce: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8000fd0: f997 3007 ldrsb.w r3, [r7, #7] + 8000fd4: 4618 mov r0, r3 + 8000fd6: f7ff ff35 bl 8000e44 <__NVIC_EnableIRQ> +} + 8000fda: bf00 nop + 8000fdc: 3708 adds r7, #8 + 8000fde: 46bd mov sp, r7 + 8000fe0: bd80 pop {r7, pc} + +08000fe2 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8000fe2: b580 push {r7, lr} + 8000fe4: b082 sub sp, #8 + 8000fe6: af00 add r7, sp, #0 + 8000fe8: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8000fea: 6878 ldr r0, [r7, #4] + 8000fec: f7ff ffa2 bl 8000f34 + 8000ff0: 4603 mov r3, r0 +} + 8000ff2: 4618 mov r0, r3 + 8000ff4: 3708 adds r7, #8 + 8000ff6: 46bd mov sp, r7 + 8000ff8: bd80 pop {r7, pc} + ... + +08000ffc : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8000ffc: b480 push {r7} + 8000ffe: b087 sub sp, #28 + 8001000: af00 add r7, sp, #0 + 8001002: 6078 str r0, [r7, #4] + 8001004: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 8001006: 2300 movs r3, #0 + 8001008: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 800100a: 2300 movs r3, #0 + 800100c: 60fb str r3, [r7, #12] + uint32_t temp = 0x00; + 800100e: 2300 movs r3, #0 + 8001010: 613b str r3, [r7, #16] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + 8001012: e160 b.n 80012d6 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + 8001014: 683b ldr r3, [r7, #0] + 8001016: 681a ldr r2, [r3, #0] + 8001018: 2101 movs r1, #1 + 800101a: 697b ldr r3, [r7, #20] + 800101c: fa01 f303 lsl.w r3, r1, r3 + 8001020: 4013 ands r3, r2 + 8001022: 60fb str r3, [r7, #12] + + if (iocurrent) + 8001024: 68fb ldr r3, [r7, #12] + 8001026: 2b00 cmp r3, #0 + 8001028: f000 8152 beq.w 80012d0 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 800102c: 683b ldr r3, [r7, #0] + 800102e: 685b ldr r3, [r3, #4] + 8001030: f003 0303 and.w r3, r3, #3 + 8001034: 2b01 cmp r3, #1 + 8001036: d005 beq.n 8001044 + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8001038: 683b ldr r3, [r7, #0] + 800103a: 685b ldr r3, [r3, #4] + 800103c: f003 0303 and.w r3, r3, #3 + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + 8001040: 2b02 cmp r3, #2 + 8001042: d130 bne.n 80010a6 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8001044: 687b ldr r3, [r7, #4] + 8001046: 689b ldr r3, [r3, #8] + 8001048: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 800104a: 697b ldr r3, [r7, #20] + 800104c: 005b lsls r3, r3, #1 + 800104e: 2203 movs r2, #3 + 8001050: fa02 f303 lsl.w r3, r2, r3 + 8001054: 43db mvns r3, r3 + 8001056: 693a ldr r2, [r7, #16] + 8001058: 4013 ands r3, r2 + 800105a: 613b str r3, [r7, #16] + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + 800105c: 683b ldr r3, [r7, #0] + 800105e: 68da ldr r2, [r3, #12] + 8001060: 697b ldr r3, [r7, #20] + 8001062: 005b lsls r3, r3, #1 + 8001064: fa02 f303 lsl.w r3, r2, r3 + 8001068: 693a ldr r2, [r7, #16] + 800106a: 4313 orrs r3, r2 + 800106c: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 800106e: 687b ldr r3, [r7, #4] + 8001070: 693a ldr r2, [r7, #16] + 8001072: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8001074: 687b ldr r3, [r7, #4] + 8001076: 685b ldr r3, [r3, #4] + 8001078: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + 800107a: 2201 movs r2, #1 + 800107c: 697b ldr r3, [r7, #20] + 800107e: fa02 f303 lsl.w r3, r2, r3 + 8001082: 43db mvns r3, r3 + 8001084: 693a ldr r2, [r7, #16] + 8001086: 4013 ands r3, r2 + 8001088: 613b str r3, [r7, #16] + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 800108a: 683b ldr r3, [r7, #0] + 800108c: 685b ldr r3, [r3, #4] + 800108e: 091b lsrs r3, r3, #4 + 8001090: f003 0201 and.w r2, r3, #1 + 8001094: 697b ldr r3, [r7, #20] + 8001096: fa02 f303 lsl.w r3, r2, r3 + 800109a: 693a ldr r2, [r7, #16] + 800109c: 4313 orrs r3, r2 + 800109e: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 80010a0: 687b ldr r3, [r7, #4] + 80010a2: 693a ldr r2, [r7, #16] + 80010a4: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 80010a6: 683b ldr r3, [r7, #0] + 80010a8: 685b ldr r3, [r3, #4] + 80010aa: f003 0303 and.w r3, r3, #3 + 80010ae: 2b03 cmp r3, #3 + 80010b0: d017 beq.n 80010e2 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 80010b2: 687b ldr r3, [r7, #4] + 80010b4: 68db ldr r3, [r3, #12] + 80010b6: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + 80010b8: 697b ldr r3, [r7, #20] + 80010ba: 005b lsls r3, r3, #1 + 80010bc: 2203 movs r2, #3 + 80010be: fa02 f303 lsl.w r3, r2, r3 + 80010c2: 43db mvns r3, r3 + 80010c4: 693a ldr r2, [r7, #16] + 80010c6: 4013 ands r3, r2 + 80010c8: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + 80010ca: 683b ldr r3, [r7, #0] + 80010cc: 689a ldr r2, [r3, #8] + 80010ce: 697b ldr r3, [r7, #20] + 80010d0: 005b lsls r3, r3, #1 + 80010d2: fa02 f303 lsl.w r3, r2, r3 + 80010d6: 693a ldr r2, [r7, #16] + 80010d8: 4313 orrs r3, r2 + 80010da: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 80010dc: 687b ldr r3, [r7, #4] + 80010de: 693a ldr r2, [r7, #16] + 80010e0: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 80010e2: 683b ldr r3, [r7, #0] + 80010e4: 685b ldr r3, [r3, #4] + 80010e6: f003 0303 and.w r3, r3, #3 + 80010ea: 2b02 cmp r3, #2 + 80010ec: d123 bne.n 8001136 + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + 80010ee: 697b ldr r3, [r7, #20] + 80010f0: 08da lsrs r2, r3, #3 + 80010f2: 687b ldr r3, [r7, #4] + 80010f4: 3208 adds r2, #8 + 80010f6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80010fa: 613b str r3, [r7, #16] + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + 80010fc: 697b ldr r3, [r7, #20] + 80010fe: f003 0307 and.w r3, r3, #7 + 8001102: 009b lsls r3, r3, #2 + 8001104: 220f movs r2, #15 + 8001106: fa02 f303 lsl.w r3, r2, r3 + 800110a: 43db mvns r3, r3 + 800110c: 693a ldr r2, [r7, #16] + 800110e: 4013 ands r3, r2 + 8001110: 613b str r3, [r7, #16] + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + 8001112: 683b ldr r3, [r7, #0] + 8001114: 691a ldr r2, [r3, #16] + 8001116: 697b ldr r3, [r7, #20] + 8001118: f003 0307 and.w r3, r3, #7 + 800111c: 009b lsls r3, r3, #2 + 800111e: fa02 f303 lsl.w r3, r2, r3 + 8001122: 693a ldr r2, [r7, #16] + 8001124: 4313 orrs r3, r2 + 8001126: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3] = temp; + 8001128: 697b ldr r3, [r7, #20] + 800112a: 08da lsrs r2, r3, #3 + 800112c: 687b ldr r3, [r7, #4] + 800112e: 3208 adds r2, #8 + 8001130: 6939 ldr r1, [r7, #16] + 8001132: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8001136: 687b ldr r3, [r7, #4] + 8001138: 681b ldr r3, [r3, #0] + 800113a: 613b str r3, [r7, #16] + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + 800113c: 697b ldr r3, [r7, #20] + 800113e: 005b lsls r3, r3, #1 + 8001140: 2203 movs r2, #3 + 8001142: fa02 f303 lsl.w r3, r2, r3 + 8001146: 43db mvns r3, r3 + 8001148: 693a ldr r2, [r7, #16] + 800114a: 4013 ands r3, r2 + 800114c: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 800114e: 683b ldr r3, [r7, #0] + 8001150: 685b ldr r3, [r3, #4] + 8001152: f003 0203 and.w r2, r3, #3 + 8001156: 697b ldr r3, [r7, #20] + 8001158: 005b lsls r3, r3, #1 + 800115a: fa02 f303 lsl.w r3, r2, r3 + 800115e: 693a ldr r2, [r7, #16] + 8001160: 4313 orrs r3, r2 + 8001162: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8001164: 687b ldr r3, [r7, #4] + 8001166: 693a ldr r2, [r7, #16] + 8001168: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 800116a: 683b ldr r3, [r7, #0] + 800116c: 685b ldr r3, [r3, #4] + 800116e: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8001172: 2b00 cmp r3, #0 + 8001174: f000 80ac beq.w 80012d0 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8001178: 4b5e ldr r3, [pc, #376] @ (80012f4 ) + 800117a: 6a1b ldr r3, [r3, #32] + 800117c: 4a5d ldr r2, [pc, #372] @ (80012f4 ) + 800117e: f043 0301 orr.w r3, r3, #1 + 8001182: 6213 str r3, [r2, #32] + 8001184: 4b5b ldr r3, [pc, #364] @ (80012f4 ) + 8001186: 6a1b ldr r3, [r3, #32] + 8001188: f003 0301 and.w r3, r3, #1 + 800118c: 60bb str r3, [r7, #8] + 800118e: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2]; + 8001190: 4a59 ldr r2, [pc, #356] @ (80012f8 ) + 8001192: 697b ldr r3, [r7, #20] + 8001194: 089b lsrs r3, r3, #2 + 8001196: 3302 adds r3, #2 + 8001198: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800119c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + 800119e: 697b ldr r3, [r7, #20] + 80011a0: f003 0303 and.w r3, r3, #3 + 80011a4: 009b lsls r3, r3, #2 + 80011a6: 220f movs r2, #15 + 80011a8: fa02 f303 lsl.w r3, r2, r3 + 80011ac: 43db mvns r3, r3 + 80011ae: 693a ldr r2, [r7, #16] + 80011b0: 4013 ands r3, r2 + 80011b2: 613b str r3, [r7, #16] + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 80011b4: 687b ldr r3, [r7, #4] + 80011b6: 4a51 ldr r2, [pc, #324] @ (80012fc ) + 80011b8: 4293 cmp r3, r2 + 80011ba: d025 beq.n 8001208 + 80011bc: 687b ldr r3, [r7, #4] + 80011be: 4a50 ldr r2, [pc, #320] @ (8001300 ) + 80011c0: 4293 cmp r3, r2 + 80011c2: d01f beq.n 8001204 + 80011c4: 687b ldr r3, [r7, #4] + 80011c6: 4a4f ldr r2, [pc, #316] @ (8001304 ) + 80011c8: 4293 cmp r3, r2 + 80011ca: d019 beq.n 8001200 + 80011cc: 687b ldr r3, [r7, #4] + 80011ce: 4a4e ldr r2, [pc, #312] @ (8001308 ) + 80011d0: 4293 cmp r3, r2 + 80011d2: d013 beq.n 80011fc + 80011d4: 687b ldr r3, [r7, #4] + 80011d6: 4a4d ldr r2, [pc, #308] @ (800130c ) + 80011d8: 4293 cmp r3, r2 + 80011da: d00d beq.n 80011f8 + 80011dc: 687b ldr r3, [r7, #4] + 80011de: 4a4c ldr r2, [pc, #304] @ (8001310 ) + 80011e0: 4293 cmp r3, r2 + 80011e2: d007 beq.n 80011f4 + 80011e4: 687b ldr r3, [r7, #4] + 80011e6: 4a4b ldr r2, [pc, #300] @ (8001314 ) + 80011e8: 4293 cmp r3, r2 + 80011ea: d101 bne.n 80011f0 + 80011ec: 2306 movs r3, #6 + 80011ee: e00c b.n 800120a + 80011f0: 2307 movs r3, #7 + 80011f2: e00a b.n 800120a + 80011f4: 2305 movs r3, #5 + 80011f6: e008 b.n 800120a + 80011f8: 2304 movs r3, #4 + 80011fa: e006 b.n 800120a + 80011fc: 2303 movs r3, #3 + 80011fe: e004 b.n 800120a + 8001200: 2302 movs r3, #2 + 8001202: e002 b.n 800120a + 8001204: 2301 movs r3, #1 + 8001206: e000 b.n 800120a + 8001208: 2300 movs r3, #0 + 800120a: 697a ldr r2, [r7, #20] + 800120c: f002 0203 and.w r2, r2, #3 + 8001210: 0092 lsls r2, r2, #2 + 8001212: 4093 lsls r3, r2 + 8001214: 693a ldr r2, [r7, #16] + 8001216: 4313 orrs r3, r2 + 8001218: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2] = temp; + 800121a: 4937 ldr r1, [pc, #220] @ (80012f8 ) + 800121c: 697b ldr r3, [r7, #20] + 800121e: 089b lsrs r3, r3, #2 + 8001220: 3302 adds r3, #2 + 8001222: 693a ldr r2, [r7, #16] + 8001224: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8001228: 4b3b ldr r3, [pc, #236] @ (8001318 ) + 800122a: 689b ldr r3, [r3, #8] + 800122c: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 800122e: 68fb ldr r3, [r7, #12] + 8001230: 43db mvns r3, r3 + 8001232: 693a ldr r2, [r7, #16] + 8001234: 4013 ands r3, r2 + 8001236: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8001238: 683b ldr r3, [r7, #0] + 800123a: 685b ldr r3, [r3, #4] + 800123c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8001240: 2b00 cmp r3, #0 + 8001242: d003 beq.n 800124c + { + SET_BIT(temp, iocurrent); + 8001244: 693a ldr r2, [r7, #16] + 8001246: 68fb ldr r3, [r7, #12] + 8001248: 4313 orrs r3, r2 + 800124a: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 800124c: 4a32 ldr r2, [pc, #200] @ (8001318 ) + 800124e: 693b ldr r3, [r7, #16] + 8001250: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8001252: 4b31 ldr r3, [pc, #196] @ (8001318 ) + 8001254: 68db ldr r3, [r3, #12] + 8001256: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001258: 68fb ldr r3, [r7, #12] + 800125a: 43db mvns r3, r3 + 800125c: 693a ldr r2, [r7, #16] + 800125e: 4013 ands r3, r2 + 8001260: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8001262: 683b ldr r3, [r7, #0] + 8001264: 685b ldr r3, [r3, #4] + 8001266: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 800126a: 2b00 cmp r3, #0 + 800126c: d003 beq.n 8001276 + { + SET_BIT(temp, iocurrent); + 800126e: 693a ldr r2, [r7, #16] + 8001270: 68fb ldr r3, [r7, #12] + 8001272: 4313 orrs r3, r2 + 8001274: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 8001276: 4a28 ldr r2, [pc, #160] @ (8001318 ) + 8001278: 693b ldr r3, [r7, #16] + 800127a: 60d3 str r3, [r2, #12] + + temp = EXTI->EMR; + 800127c: 4b26 ldr r3, [pc, #152] @ (8001318 ) + 800127e: 685b ldr r3, [r3, #4] + 8001280: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 8001282: 68fb ldr r3, [r7, #12] + 8001284: 43db mvns r3, r3 + 8001286: 693a ldr r2, [r7, #16] + 8001288: 4013 ands r3, r2 + 800128a: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 800128c: 683b ldr r3, [r7, #0] + 800128e: 685b ldr r3, [r3, #4] + 8001290: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001294: 2b00 cmp r3, #0 + 8001296: d003 beq.n 80012a0 + { + SET_BIT(temp, iocurrent); + 8001298: 693a ldr r2, [r7, #16] + 800129a: 68fb ldr r3, [r7, #12] + 800129c: 4313 orrs r3, r2 + 800129e: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 80012a0: 4a1d ldr r2, [pc, #116] @ (8001318 ) + 80012a2: 693b ldr r3, [r7, #16] + 80012a4: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 80012a6: 4b1c ldr r3, [pc, #112] @ (8001318 ) + 80012a8: 681b ldr r3, [r3, #0] + 80012aa: 613b str r3, [r7, #16] + CLEAR_BIT(temp, (uint32_t)iocurrent); + 80012ac: 68fb ldr r3, [r7, #12] + 80012ae: 43db mvns r3, r3 + 80012b0: 693a ldr r2, [r7, #16] + 80012b2: 4013 ands r3, r2 + 80012b4: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 80012b6: 683b ldr r3, [r7, #0] + 80012b8: 685b ldr r3, [r3, #4] + 80012ba: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80012be: 2b00 cmp r3, #0 + 80012c0: d003 beq.n 80012ca + { + SET_BIT(temp, iocurrent); + 80012c2: 693a ldr r2, [r7, #16] + 80012c4: 68fb ldr r3, [r7, #12] + 80012c6: 4313 orrs r3, r2 + 80012c8: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 80012ca: 4a13 ldr r2, [pc, #76] @ (8001318 ) + 80012cc: 693b ldr r3, [r7, #16] + 80012ce: 6013 str r3, [r2, #0] + } + } + + position++; + 80012d0: 697b ldr r3, [r7, #20] + 80012d2: 3301 adds r3, #1 + 80012d4: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0) + 80012d6: 683b ldr r3, [r7, #0] + 80012d8: 681a ldr r2, [r3, #0] + 80012da: 697b ldr r3, [r7, #20] + 80012dc: fa22 f303 lsr.w r3, r2, r3 + 80012e0: 2b00 cmp r3, #0 + 80012e2: f47f ae97 bne.w 8001014 + } +} + 80012e6: bf00 nop + 80012e8: bf00 nop + 80012ea: 371c adds r7, #28 + 80012ec: 46bd mov sp, r7 + 80012ee: bc80 pop {r7} + 80012f0: 4770 bx lr + 80012f2: bf00 nop + 80012f4: 40023800 .word 0x40023800 + 80012f8: 40010000 .word 0x40010000 + 80012fc: 40020000 .word 0x40020000 + 8001300: 40020400 .word 0x40020400 + 8001304: 40020800 .word 0x40020800 + 8001308: 40020c00 .word 0x40020c00 + 800130c: 40021000 .word 0x40021000 + 8001310: 40021400 .word 0x40021400 + 8001314: 40021800 .word 0x40021800 + 8001318: 40010400 .word 0x40010400 + +0800131c : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 800131c: b480 push {r7} + 800131e: b083 sub sp, #12 + 8001320: af00 add r7, sp, #0 + 8001322: 6078 str r0, [r7, #4] + 8001324: 460b mov r3, r1 + 8001326: 807b strh r3, [r7, #2] + 8001328: 4613 mov r3, r2 + 800132a: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 800132c: 787b ldrb r3, [r7, #1] + 800132e: 2b00 cmp r3, #0 + 8001330: d003 beq.n 800133a + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 8001332: 887a ldrh r2, [r7, #2] + 8001334: 687b ldr r3, [r7, #4] + 8001336: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + 8001338: e003 b.n 8001342 + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + 800133a: 887b ldrh r3, [r7, #2] + 800133c: 041a lsls r2, r3, #16 + 800133e: 687b ldr r3, [r7, #4] + 8001340: 619a str r2, [r3, #24] +} + 8001342: bf00 nop + 8001344: 370c adds r7, #12 + 8001346: 46bd mov sp, r7 + 8001348: bc80 pop {r7} + 800134a: 4770 bx lr + +0800134c : + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + 800134c: b580 push {r7, lr} + 800134e: b082 sub sp, #8 + 8001350: af00 add r7, sp, #0 + 8001352: 4603 mov r3, r0 + 8001354: 80fb strh r3, [r7, #6] + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 8001356: 4b08 ldr r3, [pc, #32] @ (8001378 ) + 8001358: 695a ldr r2, [r3, #20] + 800135a: 88fb ldrh r3, [r7, #6] + 800135c: 4013 ands r3, r2 + 800135e: 2b00 cmp r3, #0 + 8001360: d006 beq.n 8001370 + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 8001362: 4a05 ldr r2, [pc, #20] @ (8001378 ) + 8001364: 88fb ldrh r3, [r7, #6] + 8001366: 6153 str r3, [r2, #20] + HAL_GPIO_EXTI_Callback(GPIO_Pin); + 8001368: 88fb ldrh r3, [r7, #6] + 800136a: 4618 mov r0, r3 + 800136c: f000 f806 bl 800137c + } +} + 8001370: bf00 nop + 8001372: 3708 adds r7, #8 + 8001374: 46bd mov sp, r7 + 8001376: bd80 pop {r7, pc} + 8001378: 40010400 .word 0x40010400 + +0800137c : + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + 800137c: b480 push {r7} + 800137e: b083 sub sp, #12 + 8001380: af00 add r7, sp, #0 + 8001382: 4603 mov r3, r0 + 8001384: 80fb strh r3, [r7, #6] + UNUSED(GPIO_Pin); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + 8001386: bf00 nop + 8001388: 370c adds r7, #12 + 800138a: 46bd mov sp, r7 + 800138c: bc80 pop {r7} + 800138e: 4770 bx lr + +08001390 : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8001390: b580 push {r7, lr} + 8001392: b088 sub sp, #32 + 8001394: af00 add r7, sp, #0 + 8001396: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + 8001398: 687b ldr r3, [r7, #4] + 800139a: 2b00 cmp r3, #0 + 800139c: d101 bne.n 80013a2 + { + return HAL_ERROR; + 800139e: 2301 movs r3, #1 + 80013a0: e31d b.n 80019de + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80013a2: 4b94 ldr r3, [pc, #592] @ (80015f4 ) + 80013a4: 689b ldr r3, [r3, #8] + 80013a6: f003 030c and.w r3, r3, #12 + 80013aa: 61bb str r3, [r7, #24] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80013ac: 4b91 ldr r3, [pc, #580] @ (80015f4 ) + 80013ae: 689b ldr r3, [r3, #8] + 80013b0: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80013b4: 617b str r3, [r7, #20] + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80013b6: 687b ldr r3, [r7, #4] + 80013b8: 681b ldr r3, [r3, #0] + 80013ba: f003 0301 and.w r3, r3, #1 + 80013be: 2b00 cmp r3, #0 + 80013c0: d07b beq.n 80014ba + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 80013c2: 69bb ldr r3, [r7, #24] + 80013c4: 2b08 cmp r3, #8 + 80013c6: d006 beq.n 80013d6 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 80013c8: 69bb ldr r3, [r7, #24] + 80013ca: 2b0c cmp r3, #12 + 80013cc: d10f bne.n 80013ee + 80013ce: 697b ldr r3, [r7, #20] + 80013d0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 80013d4: d10b bne.n 80013ee + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80013d6: 4b87 ldr r3, [pc, #540] @ (80015f4 ) + 80013d8: 681b ldr r3, [r3, #0] + 80013da: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80013de: 2b00 cmp r3, #0 + 80013e0: d06a beq.n 80014b8 + 80013e2: 687b ldr r3, [r7, #4] + 80013e4: 685b ldr r3, [r3, #4] + 80013e6: 2b00 cmp r3, #0 + 80013e8: d166 bne.n 80014b8 + { + return HAL_ERROR; + 80013ea: 2301 movs r3, #1 + 80013ec: e2f7 b.n 80019de + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80013ee: 687b ldr r3, [r7, #4] + 80013f0: 685b ldr r3, [r3, #4] + 80013f2: 2b01 cmp r3, #1 + 80013f4: d106 bne.n 8001404 + 80013f6: 4b7f ldr r3, [pc, #508] @ (80015f4 ) + 80013f8: 681b ldr r3, [r3, #0] + 80013fa: 4a7e ldr r2, [pc, #504] @ (80015f4 ) + 80013fc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001400: 6013 str r3, [r2, #0] + 8001402: e02d b.n 8001460 + 8001404: 687b ldr r3, [r7, #4] + 8001406: 685b ldr r3, [r3, #4] + 8001408: 2b00 cmp r3, #0 + 800140a: d10c bne.n 8001426 + 800140c: 4b79 ldr r3, [pc, #484] @ (80015f4 ) + 800140e: 681b ldr r3, [r3, #0] + 8001410: 4a78 ldr r2, [pc, #480] @ (80015f4 ) + 8001412: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001416: 6013 str r3, [r2, #0] + 8001418: 4b76 ldr r3, [pc, #472] @ (80015f4 ) + 800141a: 681b ldr r3, [r3, #0] + 800141c: 4a75 ldr r2, [pc, #468] @ (80015f4 ) + 800141e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001422: 6013 str r3, [r2, #0] + 8001424: e01c b.n 8001460 + 8001426: 687b ldr r3, [r7, #4] + 8001428: 685b ldr r3, [r3, #4] + 800142a: 2b05 cmp r3, #5 + 800142c: d10c bne.n 8001448 + 800142e: 4b71 ldr r3, [pc, #452] @ (80015f4 ) + 8001430: 681b ldr r3, [r3, #0] + 8001432: 4a70 ldr r2, [pc, #448] @ (80015f4 ) + 8001434: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8001438: 6013 str r3, [r2, #0] + 800143a: 4b6e ldr r3, [pc, #440] @ (80015f4 ) + 800143c: 681b ldr r3, [r3, #0] + 800143e: 4a6d ldr r2, [pc, #436] @ (80015f4 ) + 8001440: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001444: 6013 str r3, [r2, #0] + 8001446: e00b b.n 8001460 + 8001448: 4b6a ldr r3, [pc, #424] @ (80015f4 ) + 800144a: 681b ldr r3, [r3, #0] + 800144c: 4a69 ldr r2, [pc, #420] @ (80015f4 ) + 800144e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001452: 6013 str r3, [r2, #0] + 8001454: 4b67 ldr r3, [pc, #412] @ (80015f4 ) + 8001456: 681b ldr r3, [r3, #0] + 8001458: 4a66 ldr r2, [pc, #408] @ (80015f4 ) + 800145a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 800145e: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8001460: 687b ldr r3, [r7, #4] + 8001462: 685b ldr r3, [r3, #4] + 8001464: 2b00 cmp r3, #0 + 8001466: d013 beq.n 8001490 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001468: f7ff fc8e bl 8000d88 + 800146c: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800146e: e008 b.n 8001482 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001470: f7ff fc8a bl 8000d88 + 8001474: 4602 mov r2, r0 + 8001476: 693b ldr r3, [r7, #16] + 8001478: 1ad3 subs r3, r2, r3 + 800147a: 2b64 cmp r3, #100 @ 0x64 + 800147c: d901 bls.n 8001482 + { + return HAL_TIMEOUT; + 800147e: 2303 movs r3, #3 + 8001480: e2ad b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001482: 4b5c ldr r3, [pc, #368] @ (80015f4 ) + 8001484: 681b ldr r3, [r3, #0] + 8001486: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800148a: 2b00 cmp r3, #0 + 800148c: d0f0 beq.n 8001470 + 800148e: e014 b.n 80014ba + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001490: f7ff fc7a bl 8000d88 + 8001494: 6138 str r0, [r7, #16] + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 8001496: e008 b.n 80014aa + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8001498: f7ff fc76 bl 8000d88 + 800149c: 4602 mov r2, r0 + 800149e: 693b ldr r3, [r7, #16] + 80014a0: 1ad3 subs r3, r2, r3 + 80014a2: 2b64 cmp r3, #100 @ 0x64 + 80014a4: d901 bls.n 80014aa + { + return HAL_TIMEOUT; + 80014a6: 2303 movs r3, #3 + 80014a8: e299 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 80014aa: 4b52 ldr r3, [pc, #328] @ (80015f4 ) + 80014ac: 681b ldr r3, [r3, #0] + 80014ae: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80014b2: 2b00 cmp r3, #0 + 80014b4: d1f0 bne.n 8001498 + 80014b6: e000 b.n 80014ba + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80014b8: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80014ba: 687b ldr r3, [r7, #4] + 80014bc: 681b ldr r3, [r3, #0] + 80014be: f003 0302 and.w r3, r3, #2 + 80014c2: 2b00 cmp r3, #0 + 80014c4: d05a beq.n 800157c + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 80014c6: 69bb ldr r3, [r7, #24] + 80014c8: 2b04 cmp r3, #4 + 80014ca: d005 beq.n 80014d8 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 80014cc: 69bb ldr r3, [r7, #24] + 80014ce: 2b0c cmp r3, #12 + 80014d0: d119 bne.n 8001506 + 80014d2: 697b ldr r3, [r7, #20] + 80014d4: 2b00 cmp r3, #0 + 80014d6: d116 bne.n 8001506 + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 80014d8: 4b46 ldr r3, [pc, #280] @ (80015f4 ) + 80014da: 681b ldr r3, [r3, #0] + 80014dc: f003 0302 and.w r3, r3, #2 + 80014e0: 2b00 cmp r3, #0 + 80014e2: d005 beq.n 80014f0 + 80014e4: 687b ldr r3, [r7, #4] + 80014e6: 68db ldr r3, [r3, #12] + 80014e8: 2b01 cmp r3, #1 + 80014ea: d001 beq.n 80014f0 + { + return HAL_ERROR; + 80014ec: 2301 movs r3, #1 + 80014ee: e276 b.n 80019de + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80014f0: 4b40 ldr r3, [pc, #256] @ (80015f4 ) + 80014f2: 685b ldr r3, [r3, #4] + 80014f4: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 80014f8: 687b ldr r3, [r7, #4] + 80014fa: 691b ldr r3, [r3, #16] + 80014fc: 021b lsls r3, r3, #8 + 80014fe: 493d ldr r1, [pc, #244] @ (80015f4 ) + 8001500: 4313 orrs r3, r2 + 8001502: 604b str r3, [r1, #4] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8001504: e03a b.n 800157c + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8001506: 687b ldr r3, [r7, #4] + 8001508: 68db ldr r3, [r3, #12] + 800150a: 2b00 cmp r3, #0 + 800150c: d020 beq.n 8001550 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800150e: 4b3a ldr r3, [pc, #232] @ (80015f8 ) + 8001510: 2201 movs r2, #1 + 8001512: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001514: f7ff fc38 bl 8000d88 + 8001518: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800151a: e008 b.n 800152e + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 800151c: f7ff fc34 bl 8000d88 + 8001520: 4602 mov r2, r0 + 8001522: 693b ldr r3, [r7, #16] + 8001524: 1ad3 subs r3, r2, r3 + 8001526: 2b02 cmp r3, #2 + 8001528: d901 bls.n 800152e + { + return HAL_TIMEOUT; + 800152a: 2303 movs r3, #3 + 800152c: e257 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800152e: 4b31 ldr r3, [pc, #196] @ (80015f4 ) + 8001530: 681b ldr r3, [r3, #0] + 8001532: f003 0302 and.w r3, r3, #2 + 8001536: 2b00 cmp r3, #0 + 8001538: d0f0 beq.n 800151c + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 800153a: 4b2e ldr r3, [pc, #184] @ (80015f4 ) + 800153c: 685b ldr r3, [r3, #4] + 800153e: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001542: 687b ldr r3, [r7, #4] + 8001544: 691b ldr r3, [r3, #16] + 8001546: 021b lsls r3, r3, #8 + 8001548: 492a ldr r1, [pc, #168] @ (80015f4 ) + 800154a: 4313 orrs r3, r2 + 800154c: 604b str r3, [r1, #4] + 800154e: e015 b.n 800157c + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8001550: 4b29 ldr r3, [pc, #164] @ (80015f8 ) + 8001552: 2200 movs r2, #0 + 8001554: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001556: f7ff fc17 bl 8000d88 + 800155a: 6138 str r0, [r7, #16] + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 800155c: e008 b.n 8001570 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 800155e: f7ff fc13 bl 8000d88 + 8001562: 4602 mov r2, r0 + 8001564: 693b ldr r3, [r7, #16] + 8001566: 1ad3 subs r3, r2, r3 + 8001568: 2b02 cmp r3, #2 + 800156a: d901 bls.n 8001570 + { + return HAL_TIMEOUT; + 800156c: 2303 movs r3, #3 + 800156e: e236 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8001570: 4b20 ldr r3, [pc, #128] @ (80015f4 ) + 8001572: 681b ldr r3, [r3, #0] + 8001574: f003 0302 and.w r3, r3, #2 + 8001578: 2b00 cmp r3, #0 + 800157a: d1f0 bne.n 800155e + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 800157c: 687b ldr r3, [r7, #4] + 800157e: 681b ldr r3, [r3, #0] + 8001580: f003 0310 and.w r3, r3, #16 + 8001584: 2b00 cmp r3, #0 + 8001586: f000 80b8 beq.w 80016fa + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + 800158a: 69bb ldr r3, [r7, #24] + 800158c: 2b00 cmp r3, #0 + 800158e: d170 bne.n 8001672 + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8001590: 4b18 ldr r3, [pc, #96] @ (80015f4 ) + 8001592: 681b ldr r3, [r3, #0] + 8001594: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001598: 2b00 cmp r3, #0 + 800159a: d005 beq.n 80015a8 + 800159c: 687b ldr r3, [r7, #4] + 800159e: 699b ldr r3, [r3, #24] + 80015a0: 2b00 cmp r3, #0 + 80015a2: d101 bne.n 80015a8 + { + return HAL_ERROR; + 80015a4: 2301 movs r3, #1 + 80015a6: e21a b.n 80019de + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 80015a8: 687b ldr r3, [r7, #4] + 80015aa: 6a1a ldr r2, [r3, #32] + 80015ac: 4b11 ldr r3, [pc, #68] @ (80015f4 ) + 80015ae: 685b ldr r3, [r3, #4] + 80015b0: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 80015b4: 429a cmp r2, r3 + 80015b6: d921 bls.n 80015fc + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80015b8: 687b ldr r3, [r7, #4] + 80015ba: 6a1b ldr r3, [r3, #32] + 80015bc: 4618 mov r0, r3 + 80015be: f000 fc09 bl 8001dd4 + 80015c2: 4603 mov r3, r0 + 80015c4: 2b00 cmp r3, #0 + 80015c6: d001 beq.n 80015cc + { + return HAL_ERROR; + 80015c8: 2301 movs r3, #1 + 80015ca: e208 b.n 80019de + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80015cc: 4b09 ldr r3, [pc, #36] @ (80015f4 ) + 80015ce: 685b ldr r3, [r3, #4] + 80015d0: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80015d4: 687b ldr r3, [r7, #4] + 80015d6: 6a1b ldr r3, [r3, #32] + 80015d8: 4906 ldr r1, [pc, #24] @ (80015f4 ) + 80015da: 4313 orrs r3, r2 + 80015dc: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80015de: 4b05 ldr r3, [pc, #20] @ (80015f4 ) + 80015e0: 685b ldr r3, [r3, #4] + 80015e2: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80015e6: 687b ldr r3, [r7, #4] + 80015e8: 69db ldr r3, [r3, #28] + 80015ea: 061b lsls r3, r3, #24 + 80015ec: 4901 ldr r1, [pc, #4] @ (80015f4 ) + 80015ee: 4313 orrs r3, r2 + 80015f0: 604b str r3, [r1, #4] + 80015f2: e020 b.n 8001636 + 80015f4: 40023800 .word 0x40023800 + 80015f8: 42470000 .word 0x42470000 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80015fc: 4b99 ldr r3, [pc, #612] @ (8001864 ) + 80015fe: 685b ldr r3, [r3, #4] + 8001600: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001604: 687b ldr r3, [r7, #4] + 8001606: 6a1b ldr r3, [r3, #32] + 8001608: 4996 ldr r1, [pc, #600] @ (8001864 ) + 800160a: 4313 orrs r3, r2 + 800160c: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800160e: 4b95 ldr r3, [pc, #596] @ (8001864 ) + 8001610: 685b ldr r3, [r3, #4] + 8001612: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 8001616: 687b ldr r3, [r7, #4] + 8001618: 69db ldr r3, [r3, #28] + 800161a: 061b lsls r3, r3, #24 + 800161c: 4991 ldr r1, [pc, #580] @ (8001864 ) + 800161e: 4313 orrs r3, r2 + 8001620: 604b str r3, [r1, #4] + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8001622: 687b ldr r3, [r7, #4] + 8001624: 6a1b ldr r3, [r3, #32] + 8001626: 4618 mov r0, r3 + 8001628: f000 fbd4 bl 8001dd4 + 800162c: 4603 mov r3, r0 + 800162e: 2b00 cmp r3, #0 + 8001630: d001 beq.n 8001636 + { + return HAL_ERROR; + 8001632: 2301 movs r3, #1 + 8001634: e1d3 b.n 80019de + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001636: 687b ldr r3, [r7, #4] + 8001638: 6a1b ldr r3, [r3, #32] + 800163a: 0b5b lsrs r3, r3, #13 + 800163c: 3301 adds r3, #1 + 800163e: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001642: fa02 f303 lsl.w r3, r2, r3 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 8001646: 4a87 ldr r2, [pc, #540] @ (8001864 ) + 8001648: 6892 ldr r2, [r2, #8] + 800164a: 0912 lsrs r2, r2, #4 + 800164c: f002 020f and.w r2, r2, #15 + 8001650: 4985 ldr r1, [pc, #532] @ (8001868 ) + 8001652: 5c8a ldrb r2, [r1, r2] + 8001654: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8001656: 4a85 ldr r2, [pc, #532] @ (800186c ) + 8001658: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 800165a: 4b85 ldr r3, [pc, #532] @ (8001870 ) + 800165c: 681b ldr r3, [r3, #0] + 800165e: 4618 mov r0, r3 + 8001660: f7ff fb46 bl 8000cf0 + 8001664: 4603 mov r3, r0 + 8001666: 73fb strb r3, [r7, #15] + if(status != HAL_OK) + 8001668: 7bfb ldrb r3, [r7, #15] + 800166a: 2b00 cmp r3, #0 + 800166c: d045 beq.n 80016fa + { + return status; + 800166e: 7bfb ldrb r3, [r7, #15] + 8001670: e1b5 b.n 80019de + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8001672: 687b ldr r3, [r7, #4] + 8001674: 699b ldr r3, [r3, #24] + 8001676: 2b00 cmp r3, #0 + 8001678: d029 beq.n 80016ce + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 800167a: 4b7e ldr r3, [pc, #504] @ (8001874 ) + 800167c: 2201 movs r2, #1 + 800167e: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001680: f7ff fb82 bl 8000d88 + 8001684: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001686: e008 b.n 800169a + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8001688: f7ff fb7e bl 8000d88 + 800168c: 4602 mov r2, r0 + 800168e: 693b ldr r3, [r7, #16] + 8001690: 1ad3 subs r3, r2, r3 + 8001692: 2b02 cmp r3, #2 + 8001694: d901 bls.n 800169a + { + return HAL_TIMEOUT; + 8001696: 2303 movs r3, #3 + 8001698: e1a1 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 800169a: 4b72 ldr r3, [pc, #456] @ (8001864 ) + 800169c: 681b ldr r3, [r3, #0] + 800169e: f403 7300 and.w r3, r3, #512 @ 0x200 + 80016a2: 2b00 cmp r3, #0 + 80016a4: d0f0 beq.n 8001688 + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80016a6: 4b6f ldr r3, [pc, #444] @ (8001864 ) + 80016a8: 685b ldr r3, [r3, #4] + 80016aa: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80016ae: 687b ldr r3, [r7, #4] + 80016b0: 6a1b ldr r3, [r3, #32] + 80016b2: 496c ldr r1, [pc, #432] @ (8001864 ) + 80016b4: 4313 orrs r3, r2 + 80016b6: 604b str r3, [r1, #4] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 80016b8: 4b6a ldr r3, [pc, #424] @ (8001864 ) + 80016ba: 685b ldr r3, [r3, #4] + 80016bc: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80016c0: 687b ldr r3, [r7, #4] + 80016c2: 69db ldr r3, [r3, #28] + 80016c4: 061b lsls r3, r3, #24 + 80016c6: 4967 ldr r1, [pc, #412] @ (8001864 ) + 80016c8: 4313 orrs r3, r2 + 80016ca: 604b str r3, [r1, #4] + 80016cc: e015 b.n 80016fa + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 80016ce: 4b69 ldr r3, [pc, #420] @ (8001874 ) + 80016d0: 2200 movs r2, #0 + 80016d2: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80016d4: f7ff fb58 bl 8000d88 + 80016d8: 6138 str r0, [r7, #16] + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80016da: e008 b.n 80016ee + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80016dc: f7ff fb54 bl 8000d88 + 80016e0: 4602 mov r2, r0 + 80016e2: 693b ldr r3, [r7, #16] + 80016e4: 1ad3 subs r3, r2, r3 + 80016e6: 2b02 cmp r3, #2 + 80016e8: d901 bls.n 80016ee + { + return HAL_TIMEOUT; + 80016ea: 2303 movs r3, #3 + 80016ec: e177 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 80016ee: 4b5d ldr r3, [pc, #372] @ (8001864 ) + 80016f0: 681b ldr r3, [r3, #0] + 80016f2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80016f6: 2b00 cmp r3, #0 + 80016f8: d1f0 bne.n 80016dc + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80016fa: 687b ldr r3, [r7, #4] + 80016fc: 681b ldr r3, [r3, #0] + 80016fe: f003 0308 and.w r3, r3, #8 + 8001702: 2b00 cmp r3, #0 + 8001704: d030 beq.n 8001768 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8001706: 687b ldr r3, [r7, #4] + 8001708: 695b ldr r3, [r3, #20] + 800170a: 2b00 cmp r3, #0 + 800170c: d016 beq.n 800173c + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800170e: 4b5a ldr r3, [pc, #360] @ (8001878 ) + 8001710: 2201 movs r2, #1 + 8001712: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001714: f7ff fb38 bl 8000d88 + 8001718: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800171a: e008 b.n 800172e + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800171c: f7ff fb34 bl 8000d88 + 8001720: 4602 mov r2, r0 + 8001722: 693b ldr r3, [r7, #16] + 8001724: 1ad3 subs r3, r2, r3 + 8001726: 2b02 cmp r3, #2 + 8001728: d901 bls.n 800172e + { + return HAL_TIMEOUT; + 800172a: 2303 movs r3, #3 + 800172c: e157 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800172e: 4b4d ldr r3, [pc, #308] @ (8001864 ) + 8001730: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001732: f003 0302 and.w r3, r3, #2 + 8001736: 2b00 cmp r3, #0 + 8001738: d0f0 beq.n 800171c + 800173a: e015 b.n 8001768 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 800173c: 4b4e ldr r3, [pc, #312] @ (8001878 ) + 800173e: 2200 movs r2, #0 + 8001740: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001742: f7ff fb21 bl 8000d88 + 8001746: 6138 str r0, [r7, #16] + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8001748: e008 b.n 800175c + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 800174a: f7ff fb1d bl 8000d88 + 800174e: 4602 mov r2, r0 + 8001750: 693b ldr r3, [r7, #16] + 8001752: 1ad3 subs r3, r2, r3 + 8001754: 2b02 cmp r3, #2 + 8001756: d901 bls.n 800175c + { + return HAL_TIMEOUT; + 8001758: 2303 movs r3, #3 + 800175a: e140 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 800175c: 4b41 ldr r3, [pc, #260] @ (8001864 ) + 800175e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001760: f003 0302 and.w r3, r3, #2 + 8001764: 2b00 cmp r3, #0 + 8001766: d1f0 bne.n 800174a + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8001768: 687b ldr r3, [r7, #4] + 800176a: 681b ldr r3, [r3, #0] + 800176c: f003 0304 and.w r3, r3, #4 + 8001770: 2b00 cmp r3, #0 + 8001772: f000 80b5 beq.w 80018e0 + { + FlagStatus pwrclkchanged = RESET; + 8001776: 2300 movs r3, #0 + 8001778: 77fb strb r3, [r7, #31] + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800177a: 4b3a ldr r3, [pc, #232] @ (8001864 ) + 800177c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800177e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001782: 2b00 cmp r3, #0 + 8001784: d10d bne.n 80017a2 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001786: 4b37 ldr r3, [pc, #220] @ (8001864 ) + 8001788: 6a5b ldr r3, [r3, #36] @ 0x24 + 800178a: 4a36 ldr r2, [pc, #216] @ (8001864 ) + 800178c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001790: 6253 str r3, [r2, #36] @ 0x24 + 8001792: 4b34 ldr r3, [pc, #208] @ (8001864 ) + 8001794: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001796: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800179a: 60bb str r3, [r7, #8] + 800179c: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 800179e: 2301 movs r3, #1 + 80017a0: 77fb strb r3, [r7, #31] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80017a2: 4b36 ldr r3, [pc, #216] @ (800187c ) + 80017a4: 681b ldr r3, [r3, #0] + 80017a6: f403 7380 and.w r3, r3, #256 @ 0x100 + 80017aa: 2b00 cmp r3, #0 + 80017ac: d118 bne.n 80017e0 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 80017ae: 4b33 ldr r3, [pc, #204] @ (800187c ) + 80017b0: 681b ldr r3, [r3, #0] + 80017b2: 4a32 ldr r2, [pc, #200] @ (800187c ) + 80017b4: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80017b8: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80017ba: f7ff fae5 bl 8000d88 + 80017be: 6138 str r0, [r7, #16] + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80017c0: e008 b.n 80017d4 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80017c2: f7ff fae1 bl 8000d88 + 80017c6: 4602 mov r2, r0 + 80017c8: 693b ldr r3, [r7, #16] + 80017ca: 1ad3 subs r3, r2, r3 + 80017cc: 2b64 cmp r3, #100 @ 0x64 + 80017ce: d901 bls.n 80017d4 + { + return HAL_TIMEOUT; + 80017d0: 2303 movs r3, #3 + 80017d2: e104 b.n 80019de + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80017d4: 4b29 ldr r3, [pc, #164] @ (800187c ) + 80017d6: 681b ldr r3, [r3, #0] + 80017d8: f403 7380 and.w r3, r3, #256 @ 0x100 + 80017dc: 2b00 cmp r3, #0 + 80017de: d0f0 beq.n 80017c2 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80017e0: 687b ldr r3, [r7, #4] + 80017e2: 689b ldr r3, [r3, #8] + 80017e4: 2b01 cmp r3, #1 + 80017e6: d106 bne.n 80017f6 + 80017e8: 4b1e ldr r3, [pc, #120] @ (8001864 ) + 80017ea: 6b5b ldr r3, [r3, #52] @ 0x34 + 80017ec: 4a1d ldr r2, [pc, #116] @ (8001864 ) + 80017ee: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80017f2: 6353 str r3, [r2, #52] @ 0x34 + 80017f4: e02d b.n 8001852 + 80017f6: 687b ldr r3, [r7, #4] + 80017f8: 689b ldr r3, [r3, #8] + 80017fa: 2b00 cmp r3, #0 + 80017fc: d10c bne.n 8001818 + 80017fe: 4b19 ldr r3, [pc, #100] @ (8001864 ) + 8001800: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001802: 4a18 ldr r2, [pc, #96] @ (8001864 ) + 8001804: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001808: 6353 str r3, [r2, #52] @ 0x34 + 800180a: 4b16 ldr r3, [pc, #88] @ (8001864 ) + 800180c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800180e: 4a15 ldr r2, [pc, #84] @ (8001864 ) + 8001810: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001814: 6353 str r3, [r2, #52] @ 0x34 + 8001816: e01c b.n 8001852 + 8001818: 687b ldr r3, [r7, #4] + 800181a: 689b ldr r3, [r3, #8] + 800181c: 2b05 cmp r3, #5 + 800181e: d10c bne.n 800183a + 8001820: 4b10 ldr r3, [pc, #64] @ (8001864 ) + 8001822: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001824: 4a0f ldr r2, [pc, #60] @ (8001864 ) + 8001826: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 800182a: 6353 str r3, [r2, #52] @ 0x34 + 800182c: 4b0d ldr r3, [pc, #52] @ (8001864 ) + 800182e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001830: 4a0c ldr r2, [pc, #48] @ (8001864 ) + 8001832: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001836: 6353 str r3, [r2, #52] @ 0x34 + 8001838: e00b b.n 8001852 + 800183a: 4b0a ldr r3, [pc, #40] @ (8001864 ) + 800183c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800183e: 4a09 ldr r2, [pc, #36] @ (8001864 ) + 8001840: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001844: 6353 str r3, [r2, #52] @ 0x34 + 8001846: 4b07 ldr r3, [pc, #28] @ (8001864 ) + 8001848: 6b5b ldr r3, [r3, #52] @ 0x34 + 800184a: 4a06 ldr r2, [pc, #24] @ (8001864 ) + 800184c: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001850: 6353 str r3, [r2, #52] @ 0x34 + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8001852: 687b ldr r3, [r7, #4] + 8001854: 689b ldr r3, [r3, #8] + 8001856: 2b00 cmp r3, #0 + 8001858: d024 beq.n 80018a4 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800185a: f7ff fa95 bl 8000d88 + 800185e: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001860: e019 b.n 8001896 + 8001862: bf00 nop + 8001864: 40023800 .word 0x40023800 + 8001868: 08002ecc .word 0x08002ecc + 800186c: 20000000 .word 0x20000000 + 8001870: 20000004 .word 0x20000004 + 8001874: 42470020 .word 0x42470020 + 8001878: 42470680 .word 0x42470680 + 800187c: 40007000 .word 0x40007000 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001880: f7ff fa82 bl 8000d88 + 8001884: 4602 mov r2, r0 + 8001886: 693b ldr r3, [r7, #16] + 8001888: 1ad3 subs r3, r2, r3 + 800188a: f241 3288 movw r2, #5000 @ 0x1388 + 800188e: 4293 cmp r3, r2 + 8001890: d901 bls.n 8001896 + { + return HAL_TIMEOUT; + 8001892: 2303 movs r3, #3 + 8001894: e0a3 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8001896: 4b54 ldr r3, [pc, #336] @ (80019e8 ) + 8001898: 6b5b ldr r3, [r3, #52] @ 0x34 + 800189a: f403 7300 and.w r3, r3, #512 @ 0x200 + 800189e: 2b00 cmp r3, #0 + 80018a0: d0ee beq.n 8001880 + 80018a2: e014 b.n 80018ce + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80018a4: f7ff fa70 bl 8000d88 + 80018a8: 6138 str r0, [r7, #16] + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80018aa: e00a b.n 80018c2 + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 80018ac: f7ff fa6c bl 8000d88 + 80018b0: 4602 mov r2, r0 + 80018b2: 693b ldr r3, [r7, #16] + 80018b4: 1ad3 subs r3, r2, r3 + 80018b6: f241 3288 movw r2, #5000 @ 0x1388 + 80018ba: 4293 cmp r3, r2 + 80018bc: d901 bls.n 80018c2 + { + return HAL_TIMEOUT; + 80018be: 2303 movs r3, #3 + 80018c0: e08d b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 80018c2: 4b49 ldr r3, [pc, #292] @ (80019e8 ) + 80018c4: 6b5b ldr r3, [r3, #52] @ 0x34 + 80018c6: f403 7300 and.w r3, r3, #512 @ 0x200 + 80018ca: 2b00 cmp r3, #0 + 80018cc: d1ee bne.n 80018ac + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 80018ce: 7ffb ldrb r3, [r7, #31] + 80018d0: 2b01 cmp r3, #1 + 80018d2: d105 bne.n 80018e0 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80018d4: 4b44 ldr r3, [pc, #272] @ (80019e8 ) + 80018d6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80018d8: 4a43 ldr r2, [pc, #268] @ (80019e8 ) + 80018da: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80018de: 6253 str r3, [r2, #36] @ 0x24 + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80018e0: 687b ldr r3, [r7, #4] + 80018e2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80018e4: 2b00 cmp r3, #0 + 80018e6: d079 beq.n 80019dc + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80018e8: 69bb ldr r3, [r7, #24] + 80018ea: 2b0c cmp r3, #12 + 80018ec: d056 beq.n 800199c + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80018ee: 687b ldr r3, [r7, #4] + 80018f0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80018f2: 2b02 cmp r3, #2 + 80018f4: d13b bne.n 800196e + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80018f6: 4b3d ldr r3, [pc, #244] @ (80019ec ) + 80018f8: 2200 movs r2, #0 + 80018fa: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80018fc: f7ff fa44 bl 8000d88 + 8001900: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001902: e008 b.n 8001916 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8001904: f7ff fa40 bl 8000d88 + 8001908: 4602 mov r2, r0 + 800190a: 693b ldr r3, [r7, #16] + 800190c: 1ad3 subs r3, r2, r3 + 800190e: 2b02 cmp r3, #2 + 8001910: d901 bls.n 8001916 + { + return HAL_TIMEOUT; + 8001912: 2303 movs r3, #3 + 8001914: e063 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8001916: 4b34 ldr r3, [pc, #208] @ (80019e8 ) + 8001918: 681b ldr r3, [r3, #0] + 800191a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800191e: 2b00 cmp r3, #0 + 8001920: d1f0 bne.n 8001904 + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8001922: 4b31 ldr r3, [pc, #196] @ (80019e8 ) + 8001924: 689b ldr r3, [r3, #8] + 8001926: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 800192a: 687b ldr r3, [r7, #4] + 800192c: 6a99 ldr r1, [r3, #40] @ 0x28 + 800192e: 687b ldr r3, [r7, #4] + 8001930: 6adb ldr r3, [r3, #44] @ 0x2c + 8001932: 4319 orrs r1, r3 + 8001934: 687b ldr r3, [r7, #4] + 8001936: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001938: 430b orrs r3, r1 + 800193a: 492b ldr r1, [pc, #172] @ (80019e8 ) + 800193c: 4313 orrs r3, r2 + 800193e: 608b str r3, [r1, #8] + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8001940: 4b2a ldr r3, [pc, #168] @ (80019ec ) + 8001942: 2201 movs r2, #1 + 8001944: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001946: f7ff fa1f bl 8000d88 + 800194a: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 800194c: e008 b.n 8001960 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800194e: f7ff fa1b bl 8000d88 + 8001952: 4602 mov r2, r0 + 8001954: 693b ldr r3, [r7, #16] + 8001956: 1ad3 subs r3, r2, r3 + 8001958: 2b02 cmp r3, #2 + 800195a: d901 bls.n 8001960 + { + return HAL_TIMEOUT; + 800195c: 2303 movs r3, #3 + 800195e: e03e b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001960: 4b21 ldr r3, [pc, #132] @ (80019e8 ) + 8001962: 681b ldr r3, [r3, #0] + 8001964: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001968: 2b00 cmp r3, #0 + 800196a: d0f0 beq.n 800194e + 800196c: e036 b.n 80019dc + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 800196e: 4b1f ldr r3, [pc, #124] @ (80019ec ) + 8001970: 2200 movs r2, #0 + 8001972: 601a str r2, [r3, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001974: f7ff fa08 bl 8000d88 + 8001978: 6138 str r0, [r7, #16] + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800197a: e008 b.n 800198e + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800197c: f7ff fa04 bl 8000d88 + 8001980: 4602 mov r2, r0 + 8001982: 693b ldr r3, [r7, #16] + 8001984: 1ad3 subs r3, r2, r3 + 8001986: 2b02 cmp r3, #2 + 8001988: d901 bls.n 800198e + { + return HAL_TIMEOUT; + 800198a: 2303 movs r3, #3 + 800198c: e027 b.n 80019de + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 800198e: 4b16 ldr r3, [pc, #88] @ (80019e8 ) + 8001990: 681b ldr r3, [r3, #0] + 8001992: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001996: 2b00 cmp r3, #0 + 8001998: d1f0 bne.n 800197c + 800199a: e01f b.n 80019dc + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 800199c: 687b ldr r3, [r7, #4] + 800199e: 6a5b ldr r3, [r3, #36] @ 0x24 + 80019a0: 2b01 cmp r3, #1 + 80019a2: d101 bne.n 80019a8 + { + return HAL_ERROR; + 80019a4: 2301 movs r3, #1 + 80019a6: e01a b.n 80019de + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 80019a8: 4b0f ldr r3, [pc, #60] @ (80019e8 ) + 80019aa: 689b ldr r3, [r3, #8] + 80019ac: 617b str r3, [r7, #20] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80019ae: 697b ldr r3, [r7, #20] + 80019b0: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 80019b4: 687b ldr r3, [r7, #4] + 80019b6: 6a9b ldr r3, [r3, #40] @ 0x28 + 80019b8: 429a cmp r2, r3 + 80019ba: d10d bne.n 80019d8 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80019bc: 697b ldr r3, [r7, #20] + 80019be: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 80019c2: 687b ldr r3, [r7, #4] + 80019c4: 6adb ldr r3, [r3, #44] @ 0x2c + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80019c6: 429a cmp r2, r3 + 80019c8: d106 bne.n 80019d8 + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 80019ca: 697b ldr r3, [r7, #20] + 80019cc: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 80019d0: 687b ldr r3, [r7, #4] + 80019d2: 6b1b ldr r3, [r3, #48] @ 0x30 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 80019d4: 429a cmp r2, r3 + 80019d6: d001 beq.n 80019dc + { + return HAL_ERROR; + 80019d8: 2301 movs r3, #1 + 80019da: e000 b.n 80019de + } + } + } + } + + return HAL_OK; + 80019dc: 2300 movs r3, #0 +} + 80019de: 4618 mov r0, r3 + 80019e0: 3720 adds r7, #32 + 80019e2: 46bd mov sp, r7 + 80019e4: bd80 pop {r7, pc} + 80019e6: bf00 nop + 80019e8: 40023800 .word 0x40023800 + 80019ec: 42470060 .word 0x42470060 + +080019f0 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80019f0: b580 push {r7, lr} + 80019f2: b084 sub sp, #16 + 80019f4: af00 add r7, sp, #0 + 80019f6: 6078 str r0, [r7, #4] + 80019f8: 6039 str r1, [r7, #0] + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + 80019fa: 687b ldr r3, [r7, #4] + 80019fc: 2b00 cmp r3, #0 + 80019fe: d101 bne.n 8001a04 + { + return HAL_ERROR; + 8001a00: 2301 movs r3, #1 + 8001a02: e11a b.n 8001c3a + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8001a04: 4b8f ldr r3, [pc, #572] @ (8001c44 ) + 8001a06: 681b ldr r3, [r3, #0] + 8001a08: f003 0301 and.w r3, r3, #1 + 8001a0c: 683a ldr r2, [r7, #0] + 8001a0e: 429a cmp r2, r3 + 8001a10: d919 bls.n 8001a46 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001a12: 683b ldr r3, [r7, #0] + 8001a14: 2b01 cmp r3, #1 + 8001a16: d105 bne.n 8001a24 + 8001a18: 4b8a ldr r3, [pc, #552] @ (8001c44 ) + 8001a1a: 681b ldr r3, [r3, #0] + 8001a1c: 4a89 ldr r2, [pc, #548] @ (8001c44 ) + 8001a1e: f043 0304 orr.w r3, r3, #4 + 8001a22: 6013 str r3, [r2, #0] + 8001a24: 4b87 ldr r3, [pc, #540] @ (8001c44 ) + 8001a26: 681b ldr r3, [r3, #0] + 8001a28: f023 0201 bic.w r2, r3, #1 + 8001a2c: 4985 ldr r1, [pc, #532] @ (8001c44 ) + 8001a2e: 683b ldr r3, [r7, #0] + 8001a30: 4313 orrs r3, r2 + 8001a32: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001a34: 4b83 ldr r3, [pc, #524] @ (8001c44 ) + 8001a36: 681b ldr r3, [r3, #0] + 8001a38: f003 0301 and.w r3, r3, #1 + 8001a3c: 683a ldr r2, [r7, #0] + 8001a3e: 429a cmp r2, r3 + 8001a40: d001 beq.n 8001a46 + { + return HAL_ERROR; + 8001a42: 2301 movs r3, #1 + 8001a44: e0f9 b.n 8001c3a + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8001a46: 687b ldr r3, [r7, #4] + 8001a48: 681b ldr r3, [r3, #0] + 8001a4a: f003 0302 and.w r3, r3, #2 + 8001a4e: 2b00 cmp r3, #0 + 8001a50: d008 beq.n 8001a64 + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8001a52: 4b7d ldr r3, [pc, #500] @ (8001c48 ) + 8001a54: 689b ldr r3, [r3, #8] + 8001a56: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 8001a5a: 687b ldr r3, [r7, #4] + 8001a5c: 689b ldr r3, [r3, #8] + 8001a5e: 497a ldr r1, [pc, #488] @ (8001c48 ) + 8001a60: 4313 orrs r3, r2 + 8001a62: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8001a64: 687b ldr r3, [r7, #4] + 8001a66: 681b ldr r3, [r3, #0] + 8001a68: f003 0301 and.w r3, r3, #1 + 8001a6c: 2b00 cmp r3, #0 + 8001a6e: f000 808e beq.w 8001b8e + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001a72: 687b ldr r3, [r7, #4] + 8001a74: 685b ldr r3, [r3, #4] + 8001a76: 2b02 cmp r3, #2 + 8001a78: d107 bne.n 8001a8a + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001a7a: 4b73 ldr r3, [pc, #460] @ (8001c48 ) + 8001a7c: 681b ldr r3, [r3, #0] + 8001a7e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001a82: 2b00 cmp r3, #0 + 8001a84: d121 bne.n 8001aca + { + return HAL_ERROR; + 8001a86: 2301 movs r3, #1 + 8001a88: e0d7 b.n 8001c3a + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001a8a: 687b ldr r3, [r7, #4] + 8001a8c: 685b ldr r3, [r3, #4] + 8001a8e: 2b03 cmp r3, #3 + 8001a90: d107 bne.n 8001aa2 + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001a92: 4b6d ldr r3, [pc, #436] @ (8001c48 ) + 8001a94: 681b ldr r3, [r3, #0] + 8001a96: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001a9a: 2b00 cmp r3, #0 + 8001a9c: d115 bne.n 8001aca + { + return HAL_ERROR; + 8001a9e: 2301 movs r3, #1 + 8001aa0: e0cb b.n 8001c3a + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001aa2: 687b ldr r3, [r7, #4] + 8001aa4: 685b ldr r3, [r3, #4] + 8001aa6: 2b01 cmp r3, #1 + 8001aa8: d107 bne.n 8001aba + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8001aaa: 4b67 ldr r3, [pc, #412] @ (8001c48 ) + 8001aac: 681b ldr r3, [r3, #0] + 8001aae: f003 0302 and.w r3, r3, #2 + 8001ab2: 2b00 cmp r3, #0 + 8001ab4: d109 bne.n 8001aca + { + return HAL_ERROR; + 8001ab6: 2301 movs r3, #1 + 8001ab8: e0bf b.n 8001c3a + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001aba: 4b63 ldr r3, [pc, #396] @ (8001c48 ) + 8001abc: 681b ldr r3, [r3, #0] + 8001abe: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001ac2: 2b00 cmp r3, #0 + 8001ac4: d101 bne.n 8001aca + { + return HAL_ERROR; + 8001ac6: 2301 movs r3, #1 + 8001ac8: e0b7 b.n 8001c3a + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8001aca: 4b5f ldr r3, [pc, #380] @ (8001c48 ) + 8001acc: 689b ldr r3, [r3, #8] + 8001ace: f023 0203 bic.w r2, r3, #3 + 8001ad2: 687b ldr r3, [r7, #4] + 8001ad4: 685b ldr r3, [r3, #4] + 8001ad6: 495c ldr r1, [pc, #368] @ (8001c48 ) + 8001ad8: 4313 orrs r3, r2 + 8001ada: 608b str r3, [r1, #8] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8001adc: f7ff f954 bl 8000d88 + 8001ae0: 60f8 str r0, [r7, #12] + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001ae2: 687b ldr r3, [r7, #4] + 8001ae4: 685b ldr r3, [r3, #4] + 8001ae6: 2b02 cmp r3, #2 + 8001ae8: d112 bne.n 8001b10 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001aea: e00a b.n 8001b02 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001aec: f7ff f94c bl 8000d88 + 8001af0: 4602 mov r2, r0 + 8001af2: 68fb ldr r3, [r7, #12] + 8001af4: 1ad3 subs r3, r2, r3 + 8001af6: f241 3288 movw r2, #5000 @ 0x1388 + 8001afa: 4293 cmp r3, r2 + 8001afc: d901 bls.n 8001b02 + { + return HAL_TIMEOUT; + 8001afe: 2303 movs r3, #3 + 8001b00: e09b b.n 8001c3a + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001b02: 4b51 ldr r3, [pc, #324] @ (8001c48 ) + 8001b04: 689b ldr r3, [r3, #8] + 8001b06: f003 030c and.w r3, r3, #12 + 8001b0a: 2b08 cmp r3, #8 + 8001b0c: d1ee bne.n 8001aec + 8001b0e: e03e b.n 8001b8e + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001b10: 687b ldr r3, [r7, #4] + 8001b12: 685b ldr r3, [r3, #4] + 8001b14: 2b03 cmp r3, #3 + 8001b16: d112 bne.n 8001b3e + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001b18: e00a b.n 8001b30 + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001b1a: f7ff f935 bl 8000d88 + 8001b1e: 4602 mov r2, r0 + 8001b20: 68fb ldr r3, [r7, #12] + 8001b22: 1ad3 subs r3, r2, r3 + 8001b24: f241 3288 movw r2, #5000 @ 0x1388 + 8001b28: 4293 cmp r3, r2 + 8001b2a: d901 bls.n 8001b30 + { + return HAL_TIMEOUT; + 8001b2c: 2303 movs r3, #3 + 8001b2e: e084 b.n 8001c3a + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8001b30: 4b45 ldr r3, [pc, #276] @ (8001c48 ) + 8001b32: 689b ldr r3, [r3, #8] + 8001b34: f003 030c and.w r3, r3, #12 + 8001b38: 2b0c cmp r3, #12 + 8001b3a: d1ee bne.n 8001b1a + 8001b3c: e027 b.n 8001b8e + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 8001b3e: 687b ldr r3, [r7, #4] + 8001b40: 685b ldr r3, [r3, #4] + 8001b42: 2b01 cmp r3, #1 + 8001b44: d11d bne.n 8001b82 + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001b46: e00a b.n 8001b5e + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001b48: f7ff f91e bl 8000d88 + 8001b4c: 4602 mov r2, r0 + 8001b4e: 68fb ldr r3, [r7, #12] + 8001b50: 1ad3 subs r3, r2, r3 + 8001b52: f241 3288 movw r2, #5000 @ 0x1388 + 8001b56: 4293 cmp r3, r2 + 8001b58: d901 bls.n 8001b5e + { + return HAL_TIMEOUT; + 8001b5a: 2303 movs r3, #3 + 8001b5c: e06d b.n 8001c3a + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 8001b5e: 4b3a ldr r3, [pc, #232] @ (8001c48 ) + 8001b60: 689b ldr r3, [r3, #8] + 8001b62: f003 030c and.w r3, r3, #12 + 8001b66: 2b04 cmp r3, #4 + 8001b68: d1ee bne.n 8001b48 + 8001b6a: e010 b.n 8001b8e + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001b6c: f7ff f90c bl 8000d88 + 8001b70: 4602 mov r2, r0 + 8001b72: 68fb ldr r3, [r7, #12] + 8001b74: 1ad3 subs r3, r2, r3 + 8001b76: f241 3288 movw r2, #5000 @ 0x1388 + 8001b7a: 4293 cmp r3, r2 + 8001b7c: d901 bls.n 8001b82 + { + return HAL_TIMEOUT; + 8001b7e: 2303 movs r3, #3 + 8001b80: e05b b.n 8001c3a + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 8001b82: 4b31 ldr r3, [pc, #196] @ (8001c48 ) + 8001b84: 689b ldr r3, [r3, #8] + 8001b86: f003 030c and.w r3, r3, #12 + 8001b8a: 2b00 cmp r3, #0 + 8001b8c: d1ee bne.n 8001b6c + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8001b8e: 4b2d ldr r3, [pc, #180] @ (8001c44 ) + 8001b90: 681b ldr r3, [r3, #0] + 8001b92: f003 0301 and.w r3, r3, #1 + 8001b96: 683a ldr r2, [r7, #0] + 8001b98: 429a cmp r2, r3 + 8001b9a: d219 bcs.n 8001bd0 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8001b9c: 683b ldr r3, [r7, #0] + 8001b9e: 2b01 cmp r3, #1 + 8001ba0: d105 bne.n 8001bae + 8001ba2: 4b28 ldr r3, [pc, #160] @ (8001c44 ) + 8001ba4: 681b ldr r3, [r3, #0] + 8001ba6: 4a27 ldr r2, [pc, #156] @ (8001c44 ) + 8001ba8: f043 0304 orr.w r3, r3, #4 + 8001bac: 6013 str r3, [r2, #0] + 8001bae: 4b25 ldr r3, [pc, #148] @ (8001c44 ) + 8001bb0: 681b ldr r3, [r3, #0] + 8001bb2: f023 0201 bic.w r2, r3, #1 + 8001bb6: 4923 ldr r1, [pc, #140] @ (8001c44 ) + 8001bb8: 683b ldr r3, [r7, #0] + 8001bba: 4313 orrs r3, r2 + 8001bbc: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8001bbe: 4b21 ldr r3, [pc, #132] @ (8001c44 ) + 8001bc0: 681b ldr r3, [r3, #0] + 8001bc2: f003 0301 and.w r3, r3, #1 + 8001bc6: 683a ldr r2, [r7, #0] + 8001bc8: 429a cmp r2, r3 + 8001bca: d001 beq.n 8001bd0 + { + return HAL_ERROR; + 8001bcc: 2301 movs r3, #1 + 8001bce: e034 b.n 8001c3a + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8001bd0: 687b ldr r3, [r7, #4] + 8001bd2: 681b ldr r3, [r3, #0] + 8001bd4: f003 0304 and.w r3, r3, #4 + 8001bd8: 2b00 cmp r3, #0 + 8001bda: d008 beq.n 8001bee + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8001bdc: 4b1a ldr r3, [pc, #104] @ (8001c48 ) + 8001bde: 689b ldr r3, [r3, #8] + 8001be0: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001be4: 687b ldr r3, [r7, #4] + 8001be6: 68db ldr r3, [r3, #12] + 8001be8: 4917 ldr r1, [pc, #92] @ (8001c48 ) + 8001bea: 4313 orrs r3, r2 + 8001bec: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8001bee: 687b ldr r3, [r7, #4] + 8001bf0: 681b ldr r3, [r3, #0] + 8001bf2: f003 0308 and.w r3, r3, #8 + 8001bf6: 2b00 cmp r3, #0 + 8001bf8: d009 beq.n 8001c0e + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 8001bfa: 4b13 ldr r3, [pc, #76] @ (8001c48 ) + 8001bfc: 689b ldr r3, [r3, #8] + 8001bfe: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001c02: 687b ldr r3, [r7, #4] + 8001c04: 691b ldr r3, [r3, #16] + 8001c06: 00db lsls r3, r3, #3 + 8001c08: 490f ldr r1, [pc, #60] @ (8001c48 ) + 8001c0a: 4313 orrs r3, r2 + 8001c0c: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8001c0e: f000 f823 bl 8001c58 + 8001c12: 4602 mov r2, r0 + 8001c14: 4b0c ldr r3, [pc, #48] @ (8001c48 ) + 8001c16: 689b ldr r3, [r3, #8] + 8001c18: 091b lsrs r3, r3, #4 + 8001c1a: f003 030f and.w r3, r3, #15 + 8001c1e: 490b ldr r1, [pc, #44] @ (8001c4c ) + 8001c20: 5ccb ldrb r3, [r1, r3] + 8001c22: fa22 f303 lsr.w r3, r2, r3 + 8001c26: 4a0a ldr r2, [pc, #40] @ (8001c50 ) + 8001c28: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + 8001c2a: 4b0a ldr r3, [pc, #40] @ (8001c54 ) + 8001c2c: 681b ldr r3, [r3, #0] + 8001c2e: 4618 mov r0, r3 + 8001c30: f7ff f85e bl 8000cf0 + 8001c34: 4603 mov r3, r0 + 8001c36: 72fb strb r3, [r7, #11] + + return status; + 8001c38: 7afb ldrb r3, [r7, #11] +} + 8001c3a: 4618 mov r0, r3 + 8001c3c: 3710 adds r7, #16 + 8001c3e: 46bd mov sp, r7 + 8001c40: bd80 pop {r7, pc} + 8001c42: bf00 nop + 8001c44: 40023c00 .word 0x40023c00 + 8001c48: 40023800 .word 0x40023800 + 8001c4c: 08002ecc .word 0x08002ecc + 8001c50: 20000000 .word 0x20000000 + 8001c54: 20000004 .word 0x20000004 + +08001c58 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8001c58: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001c5c: b08e sub sp, #56 @ 0x38 + 8001c5e: af00 add r7, sp, #0 + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + 8001c60: 4b58 ldr r3, [pc, #352] @ (8001dc4 ) + 8001c62: 689b ldr r3, [r3, #8] + 8001c64: 62fb str r3, [r7, #44] @ 0x2c + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8001c66: 6afb ldr r3, [r7, #44] @ 0x2c + 8001c68: f003 030c and.w r3, r3, #12 + 8001c6c: 2b0c cmp r3, #12 + 8001c6e: d00d beq.n 8001c8c + 8001c70: 2b0c cmp r3, #12 + 8001c72: f200 8092 bhi.w 8001d9a + 8001c76: 2b04 cmp r3, #4 + 8001c78: d002 beq.n 8001c80 + 8001c7a: 2b08 cmp r3, #8 + 8001c7c: d003 beq.n 8001c86 + 8001c7e: e08c b.n 8001d9a + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8001c80: 4b51 ldr r3, [pc, #324] @ (8001dc8 ) + 8001c82: 633b str r3, [r7, #48] @ 0x30 + break; + 8001c84: e097 b.n 8001db6 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8001c86: 4b51 ldr r3, [pc, #324] @ (8001dcc ) + 8001c88: 633b str r3, [r7, #48] @ 0x30 + break; + 8001c8a: e094 b.n 8001db6 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8001c8c: 6afb ldr r3, [r7, #44] @ 0x2c + 8001c8e: 0c9b lsrs r3, r3, #18 + 8001c90: f003 020f and.w r2, r3, #15 + 8001c94: 4b4e ldr r3, [pc, #312] @ (8001dd0 ) + 8001c96: 5c9b ldrb r3, [r3, r2] + 8001c98: 62bb str r3, [r7, #40] @ 0x28 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8001c9a: 6afb ldr r3, [r7, #44] @ 0x2c + 8001c9c: 0d9b lsrs r3, r3, #22 + 8001c9e: f003 0303 and.w r3, r3, #3 + 8001ca2: 3301 adds r3, #1 + 8001ca4: 627b str r3, [r7, #36] @ 0x24 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8001ca6: 4b47 ldr r3, [pc, #284] @ (8001dc4 ) + 8001ca8: 689b ldr r3, [r3, #8] + 8001caa: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8001cae: 2b00 cmp r3, #0 + 8001cb0: d021 beq.n 8001cf6 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001cb2: 6abb ldr r3, [r7, #40] @ 0x28 + 8001cb4: 2200 movs r2, #0 + 8001cb6: 61bb str r3, [r7, #24] + 8001cb8: 61fa str r2, [r7, #28] + 8001cba: 4b44 ldr r3, [pc, #272] @ (8001dcc ) + 8001cbc: e9d7 8906 ldrd r8, r9, [r7, #24] + 8001cc0: 464a mov r2, r9 + 8001cc2: fb03 f202 mul.w r2, r3, r2 + 8001cc6: 2300 movs r3, #0 + 8001cc8: 4644 mov r4, r8 + 8001cca: fb04 f303 mul.w r3, r4, r3 + 8001cce: 4413 add r3, r2 + 8001cd0: 4a3e ldr r2, [pc, #248] @ (8001dcc ) + 8001cd2: 4644 mov r4, r8 + 8001cd4: fba4 0102 umull r0, r1, r4, r2 + 8001cd8: 440b add r3, r1 + 8001cda: 4619 mov r1, r3 + 8001cdc: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001cde: 2200 movs r2, #0 + 8001ce0: 613b str r3, [r7, #16] + 8001ce2: 617a str r2, [r7, #20] + 8001ce4: e9d7 2304 ldrd r2, r3, [r7, #16] + 8001ce8: f7fe fa48 bl 800017c <__aeabi_uldivmod> + 8001cec: 4602 mov r2, r0 + 8001cee: 460b mov r3, r1 + 8001cf0: 4613 mov r3, r2 + 8001cf2: 637b str r3, [r7, #52] @ 0x34 + 8001cf4: e04e b.n 8001d94 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8001cf6: 6abb ldr r3, [r7, #40] @ 0x28 + 8001cf8: 2200 movs r2, #0 + 8001cfa: 469a mov sl, r3 + 8001cfc: 4693 mov fp, r2 + 8001cfe: 4652 mov r2, sl + 8001d00: 465b mov r3, fp + 8001d02: f04f 0000 mov.w r0, #0 + 8001d06: f04f 0100 mov.w r1, #0 + 8001d0a: 0159 lsls r1, r3, #5 + 8001d0c: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001d10: 0150 lsls r0, r2, #5 + 8001d12: 4602 mov r2, r0 + 8001d14: 460b mov r3, r1 + 8001d16: ebb2 080a subs.w r8, r2, sl + 8001d1a: eb63 090b sbc.w r9, r3, fp + 8001d1e: f04f 0200 mov.w r2, #0 + 8001d22: f04f 0300 mov.w r3, #0 + 8001d26: ea4f 1389 mov.w r3, r9, lsl #6 + 8001d2a: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001d2e: ea4f 1288 mov.w r2, r8, lsl #6 + 8001d32: ebb2 0408 subs.w r4, r2, r8 + 8001d36: eb63 0509 sbc.w r5, r3, r9 + 8001d3a: f04f 0200 mov.w r2, #0 + 8001d3e: f04f 0300 mov.w r3, #0 + 8001d42: 00eb lsls r3, r5, #3 + 8001d44: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8001d48: 00e2 lsls r2, r4, #3 + 8001d4a: 4614 mov r4, r2 + 8001d4c: 461d mov r5, r3 + 8001d4e: eb14 030a adds.w r3, r4, sl + 8001d52: 603b str r3, [r7, #0] + 8001d54: eb45 030b adc.w r3, r5, fp + 8001d58: 607b str r3, [r7, #4] + 8001d5a: f04f 0200 mov.w r2, #0 + 8001d5e: f04f 0300 mov.w r3, #0 + 8001d62: e9d7 4500 ldrd r4, r5, [r7] + 8001d66: 4629 mov r1, r5 + 8001d68: 028b lsls r3, r1, #10 + 8001d6a: 4620 mov r0, r4 + 8001d6c: 4629 mov r1, r5 + 8001d6e: 4604 mov r4, r0 + 8001d70: ea43 5394 orr.w r3, r3, r4, lsr #22 + 8001d74: 4601 mov r1, r0 + 8001d76: 028a lsls r2, r1, #10 + 8001d78: 4610 mov r0, r2 + 8001d7a: 4619 mov r1, r3 + 8001d7c: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001d7e: 2200 movs r2, #0 + 8001d80: 60bb str r3, [r7, #8] + 8001d82: 60fa str r2, [r7, #12] + 8001d84: e9d7 2302 ldrd r2, r3, [r7, #8] + 8001d88: f7fe f9f8 bl 800017c <__aeabi_uldivmod> + 8001d8c: 4602 mov r2, r0 + 8001d8e: 460b mov r3, r1 + 8001d90: 4613 mov r3, r2 + 8001d92: 637b str r3, [r7, #52] @ 0x34 + } + sysclockfreq = pllvco; + 8001d94: 6b7b ldr r3, [r7, #52] @ 0x34 + 8001d96: 633b str r3, [r7, #48] @ 0x30 + break; + 8001d98: e00d b.n 8001db6 + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8001d9a: 4b0a ldr r3, [pc, #40] @ (8001dc4 ) + 8001d9c: 685b ldr r3, [r3, #4] + 8001d9e: 0b5b lsrs r3, r3, #13 + 8001da0: f003 0307 and.w r3, r3, #7 + 8001da4: 623b str r3, [r7, #32] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8001da6: 6a3b ldr r3, [r7, #32] + 8001da8: 3301 adds r3, #1 + 8001daa: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001dae: fa02 f303 lsl.w r3, r2, r3 + 8001db2: 633b str r3, [r7, #48] @ 0x30 + break; + 8001db4: bf00 nop + } + } + return sysclockfreq; + 8001db6: 6b3b ldr r3, [r7, #48] @ 0x30 +} + 8001db8: 4618 mov r0, r3 + 8001dba: 3738 adds r7, #56 @ 0x38 + 8001dbc: 46bd mov sp, r7 + 8001dbe: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8001dc2: bf00 nop + 8001dc4: 40023800 .word 0x40023800 + 8001dc8: 00f42400 .word 0x00f42400 + 8001dcc: 016e3600 .word 0x016e3600 + 8001dd0: 08002ec0 .word 0x08002ec0 + +08001dd4 : + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + 8001dd4: b480 push {r7} + 8001dd6: b087 sub sp, #28 + 8001dd8: af00 add r7, sp, #0 + 8001dda: 6078 str r0, [r7, #4] + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8001ddc: 2300 movs r3, #0 + 8001dde: 613b str r3, [r7, #16] + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + 8001de0: 4b29 ldr r3, [pc, #164] @ (8001e88 ) + 8001de2: 689b ldr r3, [r3, #8] + 8001de4: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001de8: 2b00 cmp r3, #0 + 8001dea: d12c bne.n 8001e46 + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + 8001dec: 4b26 ldr r3, [pc, #152] @ (8001e88 ) + 8001dee: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001df0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001df4: 2b00 cmp r3, #0 + 8001df6: d005 beq.n 8001e04 + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001df8: 4b24 ldr r3, [pc, #144] @ (8001e8c ) + 8001dfa: 681b ldr r3, [r3, #0] + 8001dfc: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001e00: 617b str r3, [r7, #20] + 8001e02: e016 b.n 8001e32 + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001e04: 4b20 ldr r3, [pc, #128] @ (8001e88 ) + 8001e06: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e08: 4a1f ldr r2, [pc, #124] @ (8001e88 ) + 8001e0a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001e0e: 6253 str r3, [r2, #36] @ 0x24 + 8001e10: 4b1d ldr r3, [pc, #116] @ (8001e88 ) + 8001e12: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e14: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001e18: 60fb str r3, [r7, #12] + 8001e1a: 68fb ldr r3, [r7, #12] + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + 8001e1c: 4b1b ldr r3, [pc, #108] @ (8001e8c ) + 8001e1e: 681b ldr r3, [r3, #0] + 8001e20: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001e24: 617b str r3, [r7, #20] + __HAL_RCC_PWR_CLK_DISABLE(); + 8001e26: 4b18 ldr r3, [pc, #96] @ (8001e88 ) + 8001e28: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001e2a: 4a17 ldr r2, [pc, #92] @ (8001e88 ) + 8001e2c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001e30: 6253 str r3, [r2, #36] @ 0x24 + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + 8001e32: 697b ldr r3, [r7, #20] + 8001e34: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001e38: d105 bne.n 8001e46 + 8001e3a: 687b ldr r3, [r7, #4] + 8001e3c: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001e40: d101 bne.n 8001e46 + { + latency = FLASH_LATENCY_1; /* 1WS */ + 8001e42: 2301 movs r3, #1 + 8001e44: 613b str r3, [r7, #16] + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8001e46: 693b ldr r3, [r7, #16] + 8001e48: 2b01 cmp r3, #1 + 8001e4a: d105 bne.n 8001e58 + 8001e4c: 4b10 ldr r3, [pc, #64] @ (8001e90 ) + 8001e4e: 681b ldr r3, [r3, #0] + 8001e50: 4a0f ldr r2, [pc, #60] @ (8001e90 ) + 8001e52: f043 0304 orr.w r3, r3, #4 + 8001e56: 6013 str r3, [r2, #0] + 8001e58: 4b0d ldr r3, [pc, #52] @ (8001e90 ) + 8001e5a: 681b ldr r3, [r3, #0] + 8001e5c: f023 0201 bic.w r2, r3, #1 + 8001e60: 490b ldr r1, [pc, #44] @ (8001e90 ) + 8001e62: 693b ldr r3, [r7, #16] + 8001e64: 4313 orrs r3, r2 + 8001e66: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + 8001e68: 4b09 ldr r3, [pc, #36] @ (8001e90 ) + 8001e6a: 681b ldr r3, [r3, #0] + 8001e6c: f003 0301 and.w r3, r3, #1 + 8001e70: 693a ldr r2, [r7, #16] + 8001e72: 429a cmp r2, r3 + 8001e74: d001 beq.n 8001e7a + { + return HAL_ERROR; + 8001e76: 2301 movs r3, #1 + 8001e78: e000 b.n 8001e7c + } + + return HAL_OK; + 8001e7a: 2300 movs r3, #0 +} + 8001e7c: 4618 mov r0, r3 + 8001e7e: 371c adds r7, #28 + 8001e80: 46bd mov sp, r7 + 8001e82: bc80 pop {r7} + 8001e84: 4770 bx lr + 8001e86: bf00 nop + 8001e88: 40023800 .word 0x40023800 + 8001e8c: 40007000 .word 0x40007000 + 8001e90: 40023c00 .word 0x40023c00 + +08001e94 : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8001e94: b580 push {r7, lr} + 8001e96: b082 sub sp, #8 + 8001e98: af00 add r7, sp, #0 + 8001e9a: 6078 str r0, [r7, #4] + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8001e9c: 687b ldr r3, [r7, #4] + 8001e9e: 2b00 cmp r3, #0 + 8001ea0: d101 bne.n 8001ea6 + { + return HAL_ERROR; + 8001ea2: 2301 movs r3, #1 + 8001ea4: e07b b.n 8001f9e + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8001ea6: 687b ldr r3, [r7, #4] + 8001ea8: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001eaa: 2b00 cmp r3, #0 + 8001eac: d108 bne.n 8001ec0 + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8001eae: 687b ldr r3, [r7, #4] + 8001eb0: 685b ldr r3, [r3, #4] + 8001eb2: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001eb6: d009 beq.n 8001ecc + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001eb8: 687b ldr r3, [r7, #4] + 8001eba: 2200 movs r2, #0 + 8001ebc: 61da str r2, [r3, #28] + 8001ebe: e005 b.n 8001ecc + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8001ec0: 687b ldr r3, [r7, #4] + 8001ec2: 2200 movs r2, #0 + 8001ec4: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8001ec6: 687b ldr r3, [r7, #4] + 8001ec8: 2200 movs r2, #0 + 8001eca: 615a str r2, [r3, #20] + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001ecc: 687b ldr r3, [r7, #4] + 8001ece: 2200 movs r2, #0 + 8001ed0: 629a str r2, [r3, #40] @ 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8001ed2: 687b ldr r3, [r7, #4] + 8001ed4: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001ed8: b2db uxtb r3, r3 + 8001eda: 2b00 cmp r3, #0 + 8001edc: d106 bne.n 8001eec + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8001ede: 687b ldr r3, [r7, #4] + 8001ee0: 2200 movs r2, #0 + 8001ee2: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8001ee6: 6878 ldr r0, [r7, #4] + 8001ee8: f7fe fd5a bl 80009a0 +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8001eec: 687b ldr r3, [r7, #4] + 8001eee: 2202 movs r2, #2 + 8001ef0: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8001ef4: 687b ldr r3, [r7, #4] + 8001ef6: 681b ldr r3, [r3, #0] + 8001ef8: 681a ldr r2, [r3, #0] + 8001efa: 687b ldr r3, [r7, #4] + 8001efc: 681b ldr r3, [r3, #0] + 8001efe: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001f02: 601a str r2, [r3, #0] + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8001f04: 687b ldr r3, [r7, #4] + 8001f06: 685b ldr r3, [r3, #4] + 8001f08: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001f0c: 687b ldr r3, [r7, #4] + 8001f0e: 689b ldr r3, [r3, #8] + 8001f10: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001f14: 431a orrs r2, r3 + 8001f16: 687b ldr r3, [r7, #4] + 8001f18: 68db ldr r3, [r3, #12] + 8001f1a: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001f1e: 431a orrs r2, r3 + 8001f20: 687b ldr r3, [r7, #4] + 8001f22: 691b ldr r3, [r3, #16] + 8001f24: f003 0302 and.w r3, r3, #2 + 8001f28: 431a orrs r2, r3 + 8001f2a: 687b ldr r3, [r7, #4] + 8001f2c: 695b ldr r3, [r3, #20] + 8001f2e: f003 0301 and.w r3, r3, #1 + 8001f32: 431a orrs r2, r3 + 8001f34: 687b ldr r3, [r7, #4] + 8001f36: 699b ldr r3, [r3, #24] + 8001f38: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001f3c: 431a orrs r2, r3 + 8001f3e: 687b ldr r3, [r7, #4] + 8001f40: 69db ldr r3, [r3, #28] + 8001f42: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001f46: 431a orrs r2, r3 + 8001f48: 687b ldr r3, [r7, #4] + 8001f4a: 6a1b ldr r3, [r3, #32] + 8001f4c: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001f50: ea42 0103 orr.w r1, r2, r3 + 8001f54: 687b ldr r3, [r7, #4] + 8001f56: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001f58: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001f5c: 687b ldr r3, [r7, #4] + 8001f5e: 681b ldr r3, [r3, #0] + 8001f60: 430a orrs r2, r1 + 8001f62: 601a str r2, [r3, #0] + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + 8001f64: 687b ldr r3, [r7, #4] + 8001f66: 699b ldr r3, [r3, #24] + 8001f68: 0c1b lsrs r3, r3, #16 + 8001f6a: f003 0104 and.w r1, r3, #4 + 8001f6e: 687b ldr r3, [r7, #4] + 8001f70: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001f72: f003 0210 and.w r2, r3, #16 + 8001f76: 687b ldr r3, [r7, #4] + 8001f78: 681b ldr r3, [r3, #0] + 8001f7a: 430a orrs r2, r1 + 8001f7c: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8001f7e: 687b ldr r3, [r7, #4] + 8001f80: 681b ldr r3, [r3, #0] + 8001f82: 69da ldr r2, [r3, #28] + 8001f84: 687b ldr r3, [r7, #4] + 8001f86: 681b ldr r3, [r3, #0] + 8001f88: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001f8c: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001f8e: 687b ldr r3, [r7, #4] + 8001f90: 2200 movs r2, #0 + 8001f92: 655a str r2, [r3, #84] @ 0x54 + hspi->State = HAL_SPI_STATE_READY; + 8001f94: 687b ldr r3, [r7, #4] + 8001f96: 2201 movs r2, #1 + 8001f98: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + return HAL_OK; + 8001f9c: 2300 movs r3, #0 +} + 8001f9e: 4618 mov r0, r3 + 8001fa0: 3708 adds r7, #8 + 8001fa2: 46bd mov sp, r7 + 8001fa4: bd80 pop {r7, pc} + +08001fa6 : + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8001fa6: b580 push {r7, lr} + 8001fa8: b088 sub sp, #32 + 8001faa: af00 add r7, sp, #0 + 8001fac: 60f8 str r0, [r7, #12] + 8001fae: 60b9 str r1, [r7, #8] + 8001fb0: 603b str r3, [r7, #0] + 8001fb2: 4613 mov r3, r2 + 8001fb4: 80fb strh r3, [r7, #6] + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8001fb6: f7fe fee7 bl 8000d88 + 8001fba: 61f8 str r0, [r7, #28] + initial_TxXferCount = Size; + 8001fbc: 88fb ldrh r3, [r7, #6] + 8001fbe: 837b strh r3, [r7, #26] + + if (hspi->State != HAL_SPI_STATE_READY) + 8001fc0: 68fb ldr r3, [r7, #12] + 8001fc2: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001fc6: b2db uxtb r3, r3 + 8001fc8: 2b01 cmp r3, #1 + 8001fca: d001 beq.n 8001fd0 + { + return HAL_BUSY; + 8001fcc: 2302 movs r3, #2 + 8001fce: e12a b.n 8002226 + } + + if ((pData == NULL) || (Size == 0U)) + 8001fd0: 68bb ldr r3, [r7, #8] + 8001fd2: 2b00 cmp r3, #0 + 8001fd4: d002 beq.n 8001fdc + 8001fd6: 88fb ldrh r3, [r7, #6] + 8001fd8: 2b00 cmp r3, #0 + 8001fda: d101 bne.n 8001fe0 + { + return HAL_ERROR; + 8001fdc: 2301 movs r3, #1 + 8001fde: e122 b.n 8002226 + } + + /* Process Locked */ + __HAL_LOCK(hspi); + 8001fe0: 68fb ldr r3, [r7, #12] + 8001fe2: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001fe6: 2b01 cmp r3, #1 + 8001fe8: d101 bne.n 8001fee + 8001fea: 2302 movs r3, #2 + 8001fec: e11b b.n 8002226 + 8001fee: 68fb ldr r3, [r7, #12] + 8001ff0: 2201 movs r2, #1 + 8001ff2: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + 8001ff6: 68fb ldr r3, [r7, #12] + 8001ff8: 2203 movs r2, #3 + 8001ffa: f883 2051 strb.w r2, [r3, #81] @ 0x51 + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8001ffe: 68fb ldr r3, [r7, #12] + 8002000: 2200 movs r2, #0 + 8002002: 655a str r2, [r3, #84] @ 0x54 + hspi->pTxBuffPtr = (const uint8_t *)pData; + 8002004: 68fb ldr r3, [r7, #12] + 8002006: 68ba ldr r2, [r7, #8] + 8002008: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferSize = Size; + 800200a: 68fb ldr r3, [r7, #12] + 800200c: 88fa ldrh r2, [r7, #6] + 800200e: 869a strh r2, [r3, #52] @ 0x34 + hspi->TxXferCount = Size; + 8002010: 68fb ldr r3, [r7, #12] + 8002012: 88fa ldrh r2, [r7, #6] + 8002014: 86da strh r2, [r3, #54] @ 0x36 + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + 8002016: 68fb ldr r3, [r7, #12] + 8002018: 2200 movs r2, #0 + 800201a: 639a str r2, [r3, #56] @ 0x38 + hspi->RxXferSize = 0U; + 800201c: 68fb ldr r3, [r7, #12] + 800201e: 2200 movs r2, #0 + 8002020: 879a strh r2, [r3, #60] @ 0x3c + hspi->RxXferCount = 0U; + 8002022: 68fb ldr r3, [r7, #12] + 8002024: 2200 movs r2, #0 + 8002026: 87da strh r2, [r3, #62] @ 0x3e + hspi->TxISR = NULL; + 8002028: 68fb ldr r3, [r7, #12] + 800202a: 2200 movs r2, #0 + 800202c: 645a str r2, [r3, #68] @ 0x44 + hspi->RxISR = NULL; + 800202e: 68fb ldr r3, [r7, #12] + 8002030: 2200 movs r2, #0 + 8002032: 641a str r2, [r3, #64] @ 0x40 + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8002034: 68fb ldr r3, [r7, #12] + 8002036: 689b ldr r3, [r3, #8] + 8002038: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 800203c: d10f bne.n 800205e + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + 800203e: 68fb ldr r3, [r7, #12] + 8002040: 681b ldr r3, [r3, #0] + 8002042: 681a ldr r2, [r3, #0] + 8002044: 68fb ldr r3, [r7, #12] + 8002046: 681b ldr r3, [r3, #0] + 8002048: f022 0240 bic.w r2, r2, #64 @ 0x40 + 800204c: 601a str r2, [r3, #0] + SPI_1LINE_TX(hspi); + 800204e: 68fb ldr r3, [r7, #12] + 8002050: 681b ldr r3, [r3, #0] + 8002052: 681a ldr r2, [r3, #0] + 8002054: 68fb ldr r3, [r7, #12] + 8002056: 681b ldr r3, [r3, #0] + 8002058: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 800205c: 601a str r2, [r3, #0] + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 800205e: 68fb ldr r3, [r7, #12] + 8002060: 681b ldr r3, [r3, #0] + 8002062: 681b ldr r3, [r3, #0] + 8002064: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002068: 2b40 cmp r3, #64 @ 0x40 + 800206a: d007 beq.n 800207c + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 800206c: 68fb ldr r3, [r7, #12] + 800206e: 681b ldr r3, [r3, #0] + 8002070: 681a ldr r2, [r3, #0] + 8002072: 68fb ldr r3, [r7, #12] + 8002074: 681b ldr r3, [r3, #0] + 8002076: f042 0240 orr.w r2, r2, #64 @ 0x40 + 800207a: 601a str r2, [r3, #0] + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + 800207c: 68fb ldr r3, [r7, #12] + 800207e: 68db ldr r3, [r3, #12] + 8002080: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8002084: d152 bne.n 800212c + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8002086: 68fb ldr r3, [r7, #12] + 8002088: 685b ldr r3, [r3, #4] + 800208a: 2b00 cmp r3, #0 + 800208c: d002 beq.n 8002094 + 800208e: 8b7b ldrh r3, [r7, #26] + 8002090: 2b01 cmp r3, #1 + 8002092: d145 bne.n 8002120 + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 8002094: 68fb ldr r3, [r7, #12] + 8002096: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002098: 881a ldrh r2, [r3, #0] + 800209a: 68fb ldr r3, [r7, #12] + 800209c: 681b ldr r3, [r3, #0] + 800209e: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 80020a0: 68fb ldr r3, [r7, #12] + 80020a2: 6b1b ldr r3, [r3, #48] @ 0x30 + 80020a4: 1c9a adds r2, r3, #2 + 80020a6: 68fb ldr r3, [r7, #12] + 80020a8: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 80020aa: 68fb ldr r3, [r7, #12] + 80020ac: 8edb ldrh r3, [r3, #54] @ 0x36 + 80020ae: b29b uxth r3, r3 + 80020b0: 3b01 subs r3, #1 + 80020b2: b29a uxth r2, r3 + 80020b4: 68fb ldr r3, [r7, #12] + 80020b6: 86da strh r2, [r3, #54] @ 0x36 + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + 80020b8: e032 b.n 8002120 + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 80020ba: 68fb ldr r3, [r7, #12] + 80020bc: 681b ldr r3, [r3, #0] + 80020be: 689b ldr r3, [r3, #8] + 80020c0: f003 0302 and.w r3, r3, #2 + 80020c4: 2b02 cmp r3, #2 + 80020c6: d112 bne.n 80020ee + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + 80020c8: 68fb ldr r3, [r7, #12] + 80020ca: 6b1b ldr r3, [r3, #48] @ 0x30 + 80020cc: 881a ldrh r2, [r3, #0] + 80020ce: 68fb ldr r3, [r7, #12] + 80020d0: 681b ldr r3, [r3, #0] + 80020d2: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 80020d4: 68fb ldr r3, [r7, #12] + 80020d6: 6b1b ldr r3, [r3, #48] @ 0x30 + 80020d8: 1c9a adds r2, r3, #2 + 80020da: 68fb ldr r3, [r7, #12] + 80020dc: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 80020de: 68fb ldr r3, [r7, #12] + 80020e0: 8edb ldrh r3, [r3, #54] @ 0x36 + 80020e2: b29b uxth r3, r3 + 80020e4: 3b01 subs r3, #1 + 80020e6: b29a uxth r2, r3 + 80020e8: 68fb ldr r3, [r7, #12] + 80020ea: 86da strh r2, [r3, #54] @ 0x36 + 80020ec: e018 b.n 8002120 + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 80020ee: f7fe fe4b bl 8000d88 + 80020f2: 4602 mov r2, r0 + 80020f4: 69fb ldr r3, [r7, #28] + 80020f6: 1ad3 subs r3, r2, r3 + 80020f8: 683a ldr r2, [r7, #0] + 80020fa: 429a cmp r2, r3 + 80020fc: d803 bhi.n 8002106 + 80020fe: 683b ldr r3, [r7, #0] + 8002100: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8002104: d102 bne.n 800210c + 8002106: 683b ldr r3, [r7, #0] + 8002108: 2b00 cmp r3, #0 + 800210a: d109 bne.n 8002120 + { + hspi->State = HAL_SPI_STATE_READY; + 800210c: 68fb ldr r3, [r7, #12] + 800210e: 2201 movs r2, #1 + 8002110: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 8002114: 68fb ldr r3, [r7, #12] + 8002116: 2200 movs r2, #0 + 8002118: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 800211c: 2303 movs r3, #3 + 800211e: e082 b.n 8002226 + while (hspi->TxXferCount > 0U) + 8002120: 68fb ldr r3, [r7, #12] + 8002122: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002124: b29b uxth r3, r3 + 8002126: 2b00 cmp r3, #0 + 8002128: d1c7 bne.n 80020ba + 800212a: e053 b.n 80021d4 + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 800212c: 68fb ldr r3, [r7, #12] + 800212e: 685b ldr r3, [r3, #4] + 8002130: 2b00 cmp r3, #0 + 8002132: d002 beq.n 800213a + 8002134: 8b7b ldrh r3, [r7, #26] + 8002136: 2b01 cmp r3, #1 + 8002138: d147 bne.n 80021ca + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 800213a: 68fb ldr r3, [r7, #12] + 800213c: 6b1a ldr r2, [r3, #48] @ 0x30 + 800213e: 68fb ldr r3, [r7, #12] + 8002140: 681b ldr r3, [r3, #0] + 8002142: 330c adds r3, #12 + 8002144: 7812 ldrb r2, [r2, #0] + 8002146: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 8002148: 68fb ldr r3, [r7, #12] + 800214a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800214c: 1c5a adds r2, r3, #1 + 800214e: 68fb ldr r3, [r7, #12] + 8002150: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8002152: 68fb ldr r3, [r7, #12] + 8002154: 8edb ldrh r3, [r3, #54] @ 0x36 + 8002156: b29b uxth r3, r3 + 8002158: 3b01 subs r3, #1 + 800215a: b29a uxth r2, r3 + 800215c: 68fb ldr r3, [r7, #12] + 800215e: 86da strh r2, [r3, #54] @ 0x36 + } + while (hspi->TxXferCount > 0U) + 8002160: e033 b.n 80021ca + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 8002162: 68fb ldr r3, [r7, #12] + 8002164: 681b ldr r3, [r3, #0] + 8002166: 689b ldr r3, [r3, #8] + 8002168: f003 0302 and.w r3, r3, #2 + 800216c: 2b02 cmp r3, #2 + 800216e: d113 bne.n 8002198 + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + 8002170: 68fb ldr r3, [r7, #12] + 8002172: 6b1a ldr r2, [r3, #48] @ 0x30 + 8002174: 68fb ldr r3, [r7, #12] + 8002176: 681b ldr r3, [r3, #0] + 8002178: 330c adds r3, #12 + 800217a: 7812 ldrb r2, [r2, #0] + 800217c: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr += sizeof(uint8_t); + 800217e: 68fb ldr r3, [r7, #12] + 8002180: 6b1b ldr r3, [r3, #48] @ 0x30 + 8002182: 1c5a adds r2, r3, #1 + 8002184: 68fb ldr r3, [r7, #12] + 8002186: 631a str r2, [r3, #48] @ 0x30 + hspi->TxXferCount--; + 8002188: 68fb ldr r3, [r7, #12] + 800218a: 8edb ldrh r3, [r3, #54] @ 0x36 + 800218c: b29b uxth r3, r3 + 800218e: 3b01 subs r3, #1 + 8002190: b29a uxth r2, r3 + 8002192: 68fb ldr r3, [r7, #12] + 8002194: 86da strh r2, [r3, #54] @ 0x36 + 8002196: e018 b.n 80021ca + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + 8002198: f7fe fdf6 bl 8000d88 + 800219c: 4602 mov r2, r0 + 800219e: 69fb ldr r3, [r7, #28] + 80021a0: 1ad3 subs r3, r2, r3 + 80021a2: 683a ldr r2, [r7, #0] + 80021a4: 429a cmp r2, r3 + 80021a6: d803 bhi.n 80021b0 + 80021a8: 683b ldr r3, [r7, #0] + 80021aa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 80021ae: d102 bne.n 80021b6 + 80021b0: 683b ldr r3, [r7, #0] + 80021b2: 2b00 cmp r3, #0 + 80021b4: d109 bne.n 80021ca + { + hspi->State = HAL_SPI_STATE_READY; + 80021b6: 68fb ldr r3, [r7, #12] + 80021b8: 2201 movs r2, #1 + 80021ba: f883 2051 strb.w r2, [r3, #81] @ 0x51 + __HAL_UNLOCK(hspi); + 80021be: 68fb ldr r3, [r7, #12] + 80021c0: 2200 movs r2, #0 + 80021c2: f883 2050 strb.w r2, [r3, #80] @ 0x50 + return HAL_TIMEOUT; + 80021c6: 2303 movs r3, #3 + 80021c8: e02d b.n 8002226 + while (hspi->TxXferCount > 0U) + 80021ca: 68fb ldr r3, [r7, #12] + 80021cc: 8edb ldrh r3, [r3, #54] @ 0x36 + 80021ce: b29b uxth r3, r3 + 80021d0: 2b00 cmp r3, #0 + 80021d2: d1c6 bne.n 8002162 + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 80021d4: 69fa ldr r2, [r7, #28] + 80021d6: 6839 ldr r1, [r7, #0] + 80021d8: 68f8 ldr r0, [r7, #12] + 80021da: f000 f8b1 bl 8002340 + 80021de: 4603 mov r3, r0 + 80021e0: 2b00 cmp r3, #0 + 80021e2: d002 beq.n 80021ea + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 80021e4: 68fb ldr r3, [r7, #12] + 80021e6: 2220 movs r2, #32 + 80021e8: 655a str r2, [r3, #84] @ 0x54 + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 80021ea: 68fb ldr r3, [r7, #12] + 80021ec: 689b ldr r3, [r3, #8] + 80021ee: 2b00 cmp r3, #0 + 80021f0: d10a bne.n 8002208 + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + 80021f2: 2300 movs r3, #0 + 80021f4: 617b str r3, [r7, #20] + 80021f6: 68fb ldr r3, [r7, #12] + 80021f8: 681b ldr r3, [r3, #0] + 80021fa: 68db ldr r3, [r3, #12] + 80021fc: 617b str r3, [r7, #20] + 80021fe: 68fb ldr r3, [r7, #12] + 8002200: 681b ldr r3, [r3, #0] + 8002202: 689b ldr r3, [r3, #8] + 8002204: 617b str r3, [r7, #20] + 8002206: 697b ldr r3, [r7, #20] + } + + hspi->State = HAL_SPI_STATE_READY; + 8002208: 68fb ldr r3, [r7, #12] + 800220a: 2201 movs r2, #1 + 800220c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 8002210: 68fb ldr r3, [r7, #12] + 8002212: 2200 movs r2, #0 + 8002214: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 8002218: 68fb ldr r3, [r7, #12] + 800221a: 6d5b ldr r3, [r3, #84] @ 0x54 + 800221c: 2b00 cmp r3, #0 + 800221e: d001 beq.n 8002224 + { + return HAL_ERROR; + 8002220: 2301 movs r3, #1 + 8002222: e000 b.n 8002226 + } + else + { + return HAL_OK; + 8002224: 2300 movs r3, #0 + } +} + 8002226: 4618 mov r0, r3 + 8002228: 3720 adds r7, #32 + 800222a: 46bd mov sp, r7 + 800222c: bd80 pop {r7, pc} + ... + +08002230 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 8002230: b580 push {r7, lr} + 8002232: b088 sub sp, #32 + 8002234: af00 add r7, sp, #0 + 8002236: 60f8 str r0, [r7, #12] + 8002238: 60b9 str r1, [r7, #8] + 800223a: 603b str r3, [r7, #0] + 800223c: 4613 mov r3, r2 + 800223e: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 8002240: f7fe fda2 bl 8000d88 + 8002244: 4602 mov r2, r0 + 8002246: 6abb ldr r3, [r7, #40] @ 0x28 + 8002248: 1a9b subs r3, r3, r2 + 800224a: 683a ldr r2, [r7, #0] + 800224c: 4413 add r3, r2 + 800224e: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 8002250: f7fe fd9a bl 8000d88 + 8002254: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 8002256: 4b39 ldr r3, [pc, #228] @ (800233c ) + 8002258: 681b ldr r3, [r3, #0] + 800225a: 015b lsls r3, r3, #5 + 800225c: 0d1b lsrs r3, r3, #20 + 800225e: 69fa ldr r2, [r7, #28] + 8002260: fb02 f303 mul.w r3, r2, r3 + 8002264: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8002266: e054 b.n 8002312 + { + if (Timeout != HAL_MAX_DELAY) + 8002268: 683b ldr r3, [r7, #0] + 800226a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 800226e: d050 beq.n 8002312 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8002270: f7fe fd8a bl 8000d88 + 8002274: 4602 mov r2, r0 + 8002276: 69bb ldr r3, [r7, #24] + 8002278: 1ad3 subs r3, r2, r3 + 800227a: 69fa ldr r2, [r7, #28] + 800227c: 429a cmp r2, r3 + 800227e: d902 bls.n 8002286 + 8002280: 69fb ldr r3, [r7, #28] + 8002282: 2b00 cmp r3, #0 + 8002284: d13d bne.n 8002302 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8002286: 68fb ldr r3, [r7, #12] + 8002288: 681b ldr r3, [r3, #0] + 800228a: 685a ldr r2, [r3, #4] + 800228c: 68fb ldr r3, [r7, #12] + 800228e: 681b ldr r3, [r3, #0] + 8002290: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8002294: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8002296: 68fb ldr r3, [r7, #12] + 8002298: 685b ldr r3, [r3, #4] + 800229a: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 800229e: d111 bne.n 80022c4 + 80022a0: 68fb ldr r3, [r7, #12] + 80022a2: 689b ldr r3, [r3, #8] + 80022a4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 80022a8: d004 beq.n 80022b4 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 80022aa: 68fb ldr r3, [r7, #12] + 80022ac: 689b ldr r3, [r3, #8] + 80022ae: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 80022b2: d107 bne.n 80022c4 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 80022b4: 68fb ldr r3, [r7, #12] + 80022b6: 681b ldr r3, [r3, #0] + 80022b8: 681a ldr r2, [r3, #0] + 80022ba: 68fb ldr r3, [r7, #12] + 80022bc: 681b ldr r3, [r3, #0] + 80022be: f022 0240 bic.w r2, r2, #64 @ 0x40 + 80022c2: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 80022c4: 68fb ldr r3, [r7, #12] + 80022c6: 6a9b ldr r3, [r3, #40] @ 0x28 + 80022c8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80022cc: d10f bne.n 80022ee + { + SPI_RESET_CRC(hspi); + 80022ce: 68fb ldr r3, [r7, #12] + 80022d0: 681b ldr r3, [r3, #0] + 80022d2: 681a ldr r2, [r3, #0] + 80022d4: 68fb ldr r3, [r7, #12] + 80022d6: 681b ldr r3, [r3, #0] + 80022d8: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 80022dc: 601a str r2, [r3, #0] + 80022de: 68fb ldr r3, [r7, #12] + 80022e0: 681b ldr r3, [r3, #0] + 80022e2: 681a ldr r2, [r3, #0] + 80022e4: 68fb ldr r3, [r7, #12] + 80022e6: 681b ldr r3, [r3, #0] + 80022e8: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 80022ec: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 80022ee: 68fb ldr r3, [r7, #12] + 80022f0: 2201 movs r2, #1 + 80022f2: f883 2051 strb.w r2, [r3, #81] @ 0x51 + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80022f6: 68fb ldr r3, [r7, #12] + 80022f8: 2200 movs r2, #0 + 80022fa: f883 2050 strb.w r2, [r3, #80] @ 0x50 + + return HAL_TIMEOUT; + 80022fe: 2303 movs r3, #3 + 8002300: e017 b.n 8002332 + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + 8002302: 697b ldr r3, [r7, #20] + 8002304: 2b00 cmp r3, #0 + 8002306: d101 bne.n 800230c + { + tmp_timeout = 0U; + 8002308: 2300 movs r3, #0 + 800230a: 61fb str r3, [r7, #28] + } + count--; + 800230c: 697b ldr r3, [r7, #20] + 800230e: 3b01 subs r3, #1 + 8002310: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 8002312: 68fb ldr r3, [r7, #12] + 8002314: 681b ldr r3, [r3, #0] + 8002316: 689a ldr r2, [r3, #8] + 8002318: 68bb ldr r3, [r7, #8] + 800231a: 4013 ands r3, r2 + 800231c: 68ba ldr r2, [r7, #8] + 800231e: 429a cmp r2, r3 + 8002320: bf0c ite eq + 8002322: 2301 moveq r3, #1 + 8002324: 2300 movne r3, #0 + 8002326: b2db uxtb r3, r3 + 8002328: 461a mov r2, r3 + 800232a: 79fb ldrb r3, [r7, #7] + 800232c: 429a cmp r2, r3 + 800232e: d19b bne.n 8002268 + } + } + + return HAL_OK; + 8002330: 2300 movs r3, #0 +} + 8002332: 4618 mov r0, r3 + 8002334: 3720 adds r7, #32 + 8002336: 46bd mov sp, r7 + 8002338: bd80 pop {r7, pc} + 800233a: bf00 nop + 800233c: 20000000 .word 0x20000000 + +08002340 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 8002340: b580 push {r7, lr} + 8002342: b088 sub sp, #32 + 8002344: af02 add r7, sp, #8 + 8002346: 60f8 str r0, [r7, #12] + 8002348: 60b9 str r1, [r7, #8] + 800234a: 607a str r2, [r7, #4] + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + 800234c: 687b ldr r3, [r7, #4] + 800234e: 9300 str r3, [sp, #0] + 8002350: 68bb ldr r3, [r7, #8] + 8002352: 2201 movs r2, #1 + 8002354: 2102 movs r1, #2 + 8002356: 68f8 ldr r0, [r7, #12] + 8002358: f7ff ff6a bl 8002230 + 800235c: 4603 mov r3, r0 + 800235e: 2b00 cmp r3, #0 + 8002360: d007 beq.n 8002372 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8002362: 68fb ldr r3, [r7, #12] + 8002364: 6d5b ldr r3, [r3, #84] @ 0x54 + 8002366: f043 0220 orr.w r2, r3, #32 + 800236a: 68fb ldr r3, [r7, #12] + 800236c: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 800236e: 2303 movs r3, #3 + 8002370: e032 b.n 80023d8 + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + 8002372: 4b1b ldr r3, [pc, #108] @ (80023e0 ) + 8002374: 681b ldr r3, [r3, #0] + 8002376: 4a1b ldr r2, [pc, #108] @ (80023e4 ) + 8002378: fba2 2303 umull r2, r3, r2, r3 + 800237c: 0d5b lsrs r3, r3, #21 + 800237e: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8002382: fb02 f303 mul.w r3, r2, r3 + 8002386: 617b str r3, [r7, #20] + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8002388: 68fb ldr r3, [r7, #12] + 800238a: 685b ldr r3, [r3, #4] + 800238c: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8002390: d112 bne.n 80023b8 + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8002392: 687b ldr r3, [r7, #4] + 8002394: 9300 str r3, [sp, #0] + 8002396: 68bb ldr r3, [r7, #8] + 8002398: 2200 movs r2, #0 + 800239a: 2180 movs r1, #128 @ 0x80 + 800239c: 68f8 ldr r0, [r7, #12] + 800239e: f7ff ff47 bl 8002230 + 80023a2: 4603 mov r3, r0 + 80023a4: 2b00 cmp r3, #0 + 80023a6: d016 beq.n 80023d6 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 80023a8: 68fb ldr r3, [r7, #12] + 80023aa: 6d5b ldr r3, [r3, #84] @ 0x54 + 80023ac: f043 0220 orr.w r2, r3, #32 + 80023b0: 68fb ldr r3, [r7, #12] + 80023b2: 655a str r2, [r3, #84] @ 0x54 + return HAL_TIMEOUT; + 80023b4: 2303 movs r3, #3 + 80023b6: e00f b.n 80023d8 + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + 80023b8: 697b ldr r3, [r7, #20] + 80023ba: 2b00 cmp r3, #0 + 80023bc: d00a beq.n 80023d4 + { + break; + } + count--; + 80023be: 697b ldr r3, [r7, #20] + 80023c0: 3b01 subs r3, #1 + 80023c2: 617b str r3, [r7, #20] + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + 80023c4: 68fb ldr r3, [r7, #12] + 80023c6: 681b ldr r3, [r3, #0] + 80023c8: 689b ldr r3, [r3, #8] + 80023ca: f003 0380 and.w r3, r3, #128 @ 0x80 + 80023ce: 2b80 cmp r3, #128 @ 0x80 + 80023d0: d0f2 beq.n 80023b8 + 80023d2: e000 b.n 80023d6 + break; + 80023d4: bf00 nop + } + + return HAL_OK; + 80023d6: 2300 movs r3, #0 +} + 80023d8: 4618 mov r0, r3 + 80023da: 3718 adds r7, #24 + 80023dc: 46bd mov sp, r7 + 80023de: bd80 pop {r7, pc} + 80023e0: 20000000 .word 0x20000000 + 80023e4: 165e9f81 .word 0x165e9f81 + +080023e8 : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 80023e8: b580 push {r7, lr} + 80023ea: b082 sub sp, #8 + 80023ec: af00 add r7, sp, #0 + 80023ee: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 80023f0: 687b ldr r3, [r7, #4] + 80023f2: 2b00 cmp r3, #0 + 80023f4: d101 bne.n 80023fa + { + return HAL_ERROR; + 80023f6: 2301 movs r3, #1 + 80023f8: e031 b.n 800245e + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 80023fa: 687b ldr r3, [r7, #4] + 80023fc: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 8002400: b2db uxtb r3, r3 + 8002402: 2b00 cmp r3, #0 + 8002404: d106 bne.n 8002414 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8002406: 687b ldr r3, [r7, #4] + 8002408: 2200 movs r2, #0 + 800240a: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 800240e: 6878 ldr r0, [r7, #4] + 8002410: f7fe fb0a bl 8000a28 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002414: 687b ldr r3, [r7, #4] + 8002416: 2202 movs r2, #2 + 8002418: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 800241c: 687b ldr r3, [r7, #4] + 800241e: 681a ldr r2, [r3, #0] + 8002420: 687b ldr r3, [r7, #4] + 8002422: 3304 adds r3, #4 + 8002424: 4619 mov r1, r3 + 8002426: 4610 mov r0, r2 + 8002428: f000 fa86 bl 8002938 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 800242c: 687b ldr r3, [r7, #4] + 800242e: 2201 movs r2, #1 + 8002430: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8002434: 687b ldr r3, [r7, #4] + 8002436: 2201 movs r2, #1 + 8002438: f883 203a strb.w r2, [r3, #58] @ 0x3a + 800243c: 687b ldr r3, [r7, #4] + 800243e: 2201 movs r2, #1 + 8002440: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002444: 687b ldr r3, [r7, #4] + 8002446: 2201 movs r2, #1 + 8002448: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800244c: 687b ldr r3, [r7, #4] + 800244e: 2201 movs r2, #1 + 8002450: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8002454: 687b ldr r3, [r7, #4] + 8002456: 2201 movs r2, #1 + 8002458: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 800245c: 2300 movs r3, #0 +} + 800245e: 4618 mov r0, r3 + 8002460: 3708 adds r7, #8 + 8002462: 46bd mov sp, r7 + 8002464: bd80 pop {r7, pc} + +08002466 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8002466: b580 push {r7, lr} + 8002468: b082 sub sp, #8 + 800246a: af00 add r7, sp, #0 + 800246c: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 800246e: 687b ldr r3, [r7, #4] + 8002470: 2b00 cmp r3, #0 + 8002472: d101 bne.n 8002478 + { + return HAL_ERROR; + 8002474: 2301 movs r3, #1 + 8002476: e031 b.n 80024dc + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8002478: 687b ldr r3, [r7, #4] + 800247a: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 + 800247e: b2db uxtb r3, r3 + 8002480: 2b00 cmp r3, #0 + 8002482: d106 bne.n 8002492 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8002484: 687b ldr r3, [r7, #4] + 8002486: 2200 movs r2, #0 + 8002488: f883 2038 strb.w r2, [r3, #56] @ 0x38 + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 800248c: 6878 ldr r0, [r7, #4] + 800248e: f000 f829 bl 80024e4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002492: 687b ldr r3, [r7, #4] + 8002494: 2202 movs r2, #2 + 8002496: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 800249a: 687b ldr r3, [r7, #4] + 800249c: 681a ldr r2, [r3, #0] + 800249e: 687b ldr r3, [r7, #4] + 80024a0: 3304 adds r3, #4 + 80024a2: 4619 mov r1, r3 + 80024a4: 4610 mov r0, r2 + 80024a6: f000 fa47 bl 8002938 + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 80024aa: 687b ldr r3, [r7, #4] + 80024ac: 2201 movs r2, #1 + 80024ae: f883 203e strb.w r2, [r3, #62] @ 0x3e + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 80024b2: 687b ldr r3, [r7, #4] + 80024b4: 2201 movs r2, #1 + 80024b6: f883 203a strb.w r2, [r3, #58] @ 0x3a + 80024ba: 687b ldr r3, [r7, #4] + 80024bc: 2201 movs r2, #1 + 80024be: f883 203b strb.w r2, [r3, #59] @ 0x3b + 80024c2: 687b ldr r3, [r7, #4] + 80024c4: 2201 movs r2, #1 + 80024c6: f883 203c strb.w r2, [r3, #60] @ 0x3c + 80024ca: 687b ldr r3, [r7, #4] + 80024cc: 2201 movs r2, #1 + 80024ce: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 80024d2: 687b ldr r3, [r7, #4] + 80024d4: 2201 movs r2, #1 + 80024d6: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + return HAL_OK; + 80024da: 2300 movs r3, #0 +} + 80024dc: 4618 mov r0, r3 + 80024de: 3708 adds r7, #8 + 80024e0: 46bd mov sp, r7 + 80024e2: bd80 pop {r7, pc} + +080024e4 : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 80024e4: b480 push {r7} + 80024e6: b083 sub sp, #12 + 80024e8: af00 add r7, sp, #0 + 80024ea: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 80024ec: bf00 nop + 80024ee: 370c adds r7, #12 + 80024f0: 46bd mov sp, r7 + 80024f2: bc80 pop {r7} + 80024f4: 4770 bx lr + ... + +080024f8 : + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + 80024f8: b580 push {r7, lr} + 80024fa: b084 sub sp, #16 + 80024fc: af00 add r7, sp, #0 + 80024fe: 6078 str r0, [r7, #4] + 8002500: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 8002502: 683b ldr r3, [r7, #0] + 8002504: 2b00 cmp r3, #0 + 8002506: d109 bne.n 800251c + 8002508: 687b ldr r3, [r7, #4] + 800250a: f893 303a ldrb.w r3, [r3, #58] @ 0x3a + 800250e: b2db uxtb r3, r3 + 8002510: 2b01 cmp r3, #1 + 8002512: bf14 ite ne + 8002514: 2301 movne r3, #1 + 8002516: 2300 moveq r3, #0 + 8002518: b2db uxtb r3, r3 + 800251a: e022 b.n 8002562 + 800251c: 683b ldr r3, [r7, #0] + 800251e: 2b04 cmp r3, #4 + 8002520: d109 bne.n 8002536 + 8002522: 687b ldr r3, [r7, #4] + 8002524: f893 303b ldrb.w r3, [r3, #59] @ 0x3b + 8002528: b2db uxtb r3, r3 + 800252a: 2b01 cmp r3, #1 + 800252c: bf14 ite ne + 800252e: 2301 movne r3, #1 + 8002530: 2300 moveq r3, #0 + 8002532: b2db uxtb r3, r3 + 8002534: e015 b.n 8002562 + 8002536: 683b ldr r3, [r7, #0] + 8002538: 2b08 cmp r3, #8 + 800253a: d109 bne.n 8002550 + 800253c: 687b ldr r3, [r7, #4] + 800253e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8002542: b2db uxtb r3, r3 + 8002544: 2b01 cmp r3, #1 + 8002546: bf14 ite ne + 8002548: 2301 movne r3, #1 + 800254a: 2300 moveq r3, #0 + 800254c: b2db uxtb r3, r3 + 800254e: e008 b.n 8002562 + 8002550: 687b ldr r3, [r7, #4] + 8002552: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8002556: b2db uxtb r3, r3 + 8002558: 2b01 cmp r3, #1 + 800255a: bf14 ite ne + 800255c: 2301 movne r3, #1 + 800255e: 2300 moveq r3, #0 + 8002560: b2db uxtb r3, r3 + 8002562: 2b00 cmp r3, #0 + 8002564: d001 beq.n 800256a + { + return HAL_ERROR; + 8002566: 2301 movs r3, #1 + 8002568: e051 b.n 800260e + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 800256a: 683b ldr r3, [r7, #0] + 800256c: 2b00 cmp r3, #0 + 800256e: d104 bne.n 800257a + 8002570: 687b ldr r3, [r7, #4] + 8002572: 2202 movs r2, #2 + 8002574: f883 203a strb.w r2, [r3, #58] @ 0x3a + 8002578: e013 b.n 80025a2 + 800257a: 683b ldr r3, [r7, #0] + 800257c: 2b04 cmp r3, #4 + 800257e: d104 bne.n 800258a + 8002580: 687b ldr r3, [r7, #4] + 8002582: 2202 movs r2, #2 + 8002584: f883 203b strb.w r2, [r3, #59] @ 0x3b + 8002588: e00b b.n 80025a2 + 800258a: 683b ldr r3, [r7, #0] + 800258c: 2b08 cmp r3, #8 + 800258e: d104 bne.n 800259a + 8002590: 687b ldr r3, [r7, #4] + 8002592: 2202 movs r2, #2 + 8002594: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8002598: e003 b.n 80025a2 + 800259a: 687b ldr r3, [r7, #4] + 800259c: 2202 movs r2, #2 + 800259e: f883 203d strb.w r2, [r3, #61] @ 0x3d + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 80025a2: 687b ldr r3, [r7, #4] + 80025a4: 681b ldr r3, [r3, #0] + 80025a6: 2201 movs r2, #1 + 80025a8: 6839 ldr r1, [r7, #0] + 80025aa: 4618 mov r0, r3 + 80025ac: f000 fbc5 bl 8002d3a + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 80025b0: 687b ldr r3, [r7, #4] + 80025b2: 681b ldr r3, [r3, #0] + 80025b4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80025b8: d00e beq.n 80025d8 + 80025ba: 687b ldr r3, [r7, #4] + 80025bc: 681b ldr r3, [r3, #0] + 80025be: 4a16 ldr r2, [pc, #88] @ (8002618 ) + 80025c0: 4293 cmp r3, r2 + 80025c2: d009 beq.n 80025d8 + 80025c4: 687b ldr r3, [r7, #4] + 80025c6: 681b ldr r3, [r3, #0] + 80025c8: 4a14 ldr r2, [pc, #80] @ (800261c ) + 80025ca: 4293 cmp r3, r2 + 80025cc: d004 beq.n 80025d8 + 80025ce: 687b ldr r3, [r7, #4] + 80025d0: 681b ldr r3, [r3, #0] + 80025d2: 4a13 ldr r2, [pc, #76] @ (8002620 ) + 80025d4: 4293 cmp r3, r2 + 80025d6: d111 bne.n 80025fc + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 80025d8: 687b ldr r3, [r7, #4] + 80025da: 681b ldr r3, [r3, #0] + 80025dc: 689b ldr r3, [r3, #8] + 80025de: f003 0307 and.w r3, r3, #7 + 80025e2: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80025e4: 68fb ldr r3, [r7, #12] + 80025e6: 2b06 cmp r3, #6 + 80025e8: d010 beq.n 800260c + { + __HAL_TIM_ENABLE(htim); + 80025ea: 687b ldr r3, [r7, #4] + 80025ec: 681b ldr r3, [r3, #0] + 80025ee: 681a ldr r2, [r3, #0] + 80025f0: 687b ldr r3, [r7, #4] + 80025f2: 681b ldr r3, [r3, #0] + 80025f4: f042 0201 orr.w r2, r2, #1 + 80025f8: 601a str r2, [r3, #0] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 80025fa: e007 b.n 800260c + } + } + else + { + __HAL_TIM_ENABLE(htim); + 80025fc: 687b ldr r3, [r7, #4] + 80025fe: 681b ldr r3, [r3, #0] + 8002600: 681a ldr r2, [r3, #0] + 8002602: 687b ldr r3, [r7, #4] + 8002604: 681b ldr r3, [r3, #0] + 8002606: f042 0201 orr.w r2, r2, #1 + 800260a: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 800260c: 2300 movs r3, #0 +} + 800260e: 4618 mov r0, r3 + 8002610: 3710 adds r7, #16 + 8002612: 46bd mov sp, r7 + 8002614: bd80 pop {r7, pc} + 8002616: bf00 nop + 8002618: 40000400 .word 0x40000400 + 800261c: 40000800 .word 0x40000800 + 8002620: 40010800 .word 0x40010800 + +08002624 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8002624: b580 push {r7, lr} + 8002626: b086 sub sp, #24 + 8002628: af00 add r7, sp, #0 + 800262a: 60f8 str r0, [r7, #12] + 800262c: 60b9 str r1, [r7, #8] + 800262e: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002630: 2300 movs r3, #0 + 8002632: 75fb strb r3, [r7, #23] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8002634: 68fb ldr r3, [r7, #12] + 8002636: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 800263a: 2b01 cmp r3, #1 + 800263c: d101 bne.n 8002642 + 800263e: 2302 movs r3, #2 + 8002640: e0ae b.n 80027a0 + 8002642: 68fb ldr r3, [r7, #12] + 8002644: 2201 movs r2, #1 + 8002646: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + switch (Channel) + 800264a: 687b ldr r3, [r7, #4] + 800264c: 2b0c cmp r3, #12 + 800264e: f200 809f bhi.w 8002790 + 8002652: a201 add r2, pc, #4 @ (adr r2, 8002658 ) + 8002654: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002658: 0800268d .word 0x0800268d + 800265c: 08002791 .word 0x08002791 + 8002660: 08002791 .word 0x08002791 + 8002664: 08002791 .word 0x08002791 + 8002668: 080026cd .word 0x080026cd + 800266c: 08002791 .word 0x08002791 + 8002670: 08002791 .word 0x08002791 + 8002674: 08002791 .word 0x08002791 + 8002678: 0800270f .word 0x0800270f + 800267c: 08002791 .word 0x08002791 + 8002680: 08002791 .word 0x08002791 + 8002684: 08002791 .word 0x08002791 + 8002688: 0800274f .word 0x0800274f + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 800268c: 68fb ldr r3, [r7, #12] + 800268e: 681b ldr r3, [r3, #0] + 8002690: 68b9 ldr r1, [r7, #8] + 8002692: 4618 mov r0, r3 + 8002694: f000 f9c6 bl 8002a24 + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 8002698: 68fb ldr r3, [r7, #12] + 800269a: 681b ldr r3, [r3, #0] + 800269c: 699a ldr r2, [r3, #24] + 800269e: 68fb ldr r3, [r7, #12] + 80026a0: 681b ldr r3, [r3, #0] + 80026a2: f042 0208 orr.w r2, r2, #8 + 80026a6: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 80026a8: 68fb ldr r3, [r7, #12] + 80026aa: 681b ldr r3, [r3, #0] + 80026ac: 699a ldr r2, [r3, #24] + 80026ae: 68fb ldr r3, [r7, #12] + 80026b0: 681b ldr r3, [r3, #0] + 80026b2: f022 0204 bic.w r2, r2, #4 + 80026b6: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 80026b8: 68fb ldr r3, [r7, #12] + 80026ba: 681b ldr r3, [r3, #0] + 80026bc: 6999 ldr r1, [r3, #24] + 80026be: 68bb ldr r3, [r7, #8] + 80026c0: 68da ldr r2, [r3, #12] + 80026c2: 68fb ldr r3, [r7, #12] + 80026c4: 681b ldr r3, [r3, #0] + 80026c6: 430a orrs r2, r1 + 80026c8: 619a str r2, [r3, #24] + break; + 80026ca: e064 b.n 8002796 + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 80026cc: 68fb ldr r3, [r7, #12] + 80026ce: 681b ldr r3, [r3, #0] + 80026d0: 68b9 ldr r1, [r7, #8] + 80026d2: 4618 mov r0, r3 + 80026d4: f000 f9e2 bl 8002a9c + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 80026d8: 68fb ldr r3, [r7, #12] + 80026da: 681b ldr r3, [r3, #0] + 80026dc: 699a ldr r2, [r3, #24] + 80026de: 68fb ldr r3, [r7, #12] + 80026e0: 681b ldr r3, [r3, #0] + 80026e2: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 80026e6: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 80026e8: 68fb ldr r3, [r7, #12] + 80026ea: 681b ldr r3, [r3, #0] + 80026ec: 699a ldr r2, [r3, #24] + 80026ee: 68fb ldr r3, [r7, #12] + 80026f0: 681b ldr r3, [r3, #0] + 80026f2: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 80026f6: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 80026f8: 68fb ldr r3, [r7, #12] + 80026fa: 681b ldr r3, [r3, #0] + 80026fc: 6999 ldr r1, [r3, #24] + 80026fe: 68bb ldr r3, [r7, #8] + 8002700: 68db ldr r3, [r3, #12] + 8002702: 021a lsls r2, r3, #8 + 8002704: 68fb ldr r3, [r7, #12] + 8002706: 681b ldr r3, [r3, #0] + 8002708: 430a orrs r2, r1 + 800270a: 619a str r2, [r3, #24] + break; + 800270c: e043 b.n 8002796 + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 800270e: 68fb ldr r3, [r7, #12] + 8002710: 681b ldr r3, [r3, #0] + 8002712: 68b9 ldr r1, [r7, #8] + 8002714: 4618 mov r0, r3 + 8002716: f000 f9ff bl 8002b18 + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 800271a: 68fb ldr r3, [r7, #12] + 800271c: 681b ldr r3, [r3, #0] + 800271e: 69da ldr r2, [r3, #28] + 8002720: 68fb ldr r3, [r7, #12] + 8002722: 681b ldr r3, [r3, #0] + 8002724: f042 0208 orr.w r2, r2, #8 + 8002728: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 800272a: 68fb ldr r3, [r7, #12] + 800272c: 681b ldr r3, [r3, #0] + 800272e: 69da ldr r2, [r3, #28] + 8002730: 68fb ldr r3, [r7, #12] + 8002732: 681b ldr r3, [r3, #0] + 8002734: f022 0204 bic.w r2, r2, #4 + 8002738: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 800273a: 68fb ldr r3, [r7, #12] + 800273c: 681b ldr r3, [r3, #0] + 800273e: 69d9 ldr r1, [r3, #28] + 8002740: 68bb ldr r3, [r7, #8] + 8002742: 68da ldr r2, [r3, #12] + 8002744: 68fb ldr r3, [r7, #12] + 8002746: 681b ldr r3, [r3, #0] + 8002748: 430a orrs r2, r1 + 800274a: 61da str r2, [r3, #28] + break; + 800274c: e023 b.n 8002796 + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 800274e: 68fb ldr r3, [r7, #12] + 8002750: 681b ldr r3, [r3, #0] + 8002752: 68b9 ldr r1, [r7, #8] + 8002754: 4618 mov r0, r3 + 8002756: f000 fa1c bl 8002b92 + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 800275a: 68fb ldr r3, [r7, #12] + 800275c: 681b ldr r3, [r3, #0] + 800275e: 69da ldr r2, [r3, #28] + 8002760: 68fb ldr r3, [r7, #12] + 8002762: 681b ldr r3, [r3, #0] + 8002764: f442 6200 orr.w r2, r2, #2048 @ 0x800 + 8002768: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 800276a: 68fb ldr r3, [r7, #12] + 800276c: 681b ldr r3, [r3, #0] + 800276e: 69da ldr r2, [r3, #28] + 8002770: 68fb ldr r3, [r7, #12] + 8002772: 681b ldr r3, [r3, #0] + 8002774: f422 6280 bic.w r2, r2, #1024 @ 0x400 + 8002778: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 800277a: 68fb ldr r3, [r7, #12] + 800277c: 681b ldr r3, [r3, #0] + 800277e: 69d9 ldr r1, [r3, #28] + 8002780: 68bb ldr r3, [r7, #8] + 8002782: 68db ldr r3, [r3, #12] + 8002784: 021a lsls r2, r3, #8 + 8002786: 68fb ldr r3, [r7, #12] + 8002788: 681b ldr r3, [r3, #0] + 800278a: 430a orrs r2, r1 + 800278c: 61da str r2, [r3, #28] + break; + 800278e: e002 b.n 8002796 + } + + default: + status = HAL_ERROR; + 8002790: 2301 movs r3, #1 + 8002792: 75fb strb r3, [r7, #23] + break; + 8002794: bf00 nop + } + + __HAL_UNLOCK(htim); + 8002796: 68fb ldr r3, [r7, #12] + 8002798: 2200 movs r2, #0 + 800279a: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 800279e: 7dfb ldrb r3, [r7, #23] +} + 80027a0: 4618 mov r0, r3 + 80027a2: 3718 adds r7, #24 + 80027a4: 46bd mov sp, r7 + 80027a6: bd80 pop {r7, pc} + +080027a8 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 80027a8: b580 push {r7, lr} + 80027aa: b084 sub sp, #16 + 80027ac: af00 add r7, sp, #0 + 80027ae: 6078 str r0, [r7, #4] + 80027b0: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 80027b2: 2300 movs r3, #0 + 80027b4: 73fb strb r3, [r7, #15] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 80027b6: 687b ldr r3, [r7, #4] + 80027b8: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 80027bc: 2b01 cmp r3, #1 + 80027be: d101 bne.n 80027c4 + 80027c0: 2302 movs r3, #2 + 80027c2: e0b4 b.n 800292e + 80027c4: 687b ldr r3, [r7, #4] + 80027c6: 2201 movs r2, #1 + 80027c8: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + htim->State = HAL_TIM_STATE_BUSY; + 80027cc: 687b ldr r3, [r7, #4] + 80027ce: 2202 movs r2, #2 + 80027d0: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 80027d4: 687b ldr r3, [r7, #4] + 80027d6: 681b ldr r3, [r3, #0] + 80027d8: 689b ldr r3, [r3, #8] + 80027da: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 80027dc: 68bb ldr r3, [r7, #8] + 80027de: f023 0377 bic.w r3, r3, #119 @ 0x77 + 80027e2: 60bb str r3, [r7, #8] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 80027e4: 68bb ldr r3, [r7, #8] + 80027e6: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 80027ea: 60bb str r3, [r7, #8] + htim->Instance->SMCR = tmpsmcr; + 80027ec: 687b ldr r3, [r7, #4] + 80027ee: 681b ldr r3, [r3, #0] + 80027f0: 68ba ldr r2, [r7, #8] + 80027f2: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 80027f4: 683b ldr r3, [r7, #0] + 80027f6: 681b ldr r3, [r3, #0] + 80027f8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 80027fc: d03e beq.n 800287c + 80027fe: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8002802: f200 8087 bhi.w 8002914 + 8002806: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 800280a: f000 8086 beq.w 800291a + 800280e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8002812: d87f bhi.n 8002914 + 8002814: 2b70 cmp r3, #112 @ 0x70 + 8002816: d01a beq.n 800284e + 8002818: 2b70 cmp r3, #112 @ 0x70 + 800281a: d87b bhi.n 8002914 + 800281c: 2b60 cmp r3, #96 @ 0x60 + 800281e: d050 beq.n 80028c2 + 8002820: 2b60 cmp r3, #96 @ 0x60 + 8002822: d877 bhi.n 8002914 + 8002824: 2b50 cmp r3, #80 @ 0x50 + 8002826: d03c beq.n 80028a2 + 8002828: 2b50 cmp r3, #80 @ 0x50 + 800282a: d873 bhi.n 8002914 + 800282c: 2b40 cmp r3, #64 @ 0x40 + 800282e: d058 beq.n 80028e2 + 8002830: 2b40 cmp r3, #64 @ 0x40 + 8002832: d86f bhi.n 8002914 + 8002834: 2b30 cmp r3, #48 @ 0x30 + 8002836: d064 beq.n 8002902 + 8002838: 2b30 cmp r3, #48 @ 0x30 + 800283a: d86b bhi.n 8002914 + 800283c: 2b20 cmp r3, #32 + 800283e: d060 beq.n 8002902 + 8002840: 2b20 cmp r3, #32 + 8002842: d867 bhi.n 8002914 + 8002844: 2b00 cmp r3, #0 + 8002846: d05c beq.n 8002902 + 8002848: 2b10 cmp r3, #16 + 800284a: d05a beq.n 8002902 + 800284c: e062 b.n 8002914 + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 800284e: 687b ldr r3, [r7, #4] + 8002850: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8002852: 683b ldr r3, [r7, #0] + 8002854: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8002856: 683b ldr r3, [r7, #0] + 8002858: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 800285a: 683b ldr r3, [r7, #0] + 800285c: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 800285e: f000 fa4d bl 8002cfc + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + 8002862: 687b ldr r3, [r7, #4] + 8002864: 681b ldr r3, [r3, #0] + 8002866: 689b ldr r3, [r3, #8] + 8002868: 60bb str r3, [r7, #8] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 800286a: 68bb ldr r3, [r7, #8] + 800286c: f043 0377 orr.w r3, r3, #119 @ 0x77 + 8002870: 60bb str r3, [r7, #8] + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8002872: 687b ldr r3, [r7, #4] + 8002874: 681b ldr r3, [r3, #0] + 8002876: 68ba ldr r2, [r7, #8] + 8002878: 609a str r2, [r3, #8] + break; + 800287a: e04f b.n 800291c + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + 800287c: 687b ldr r3, [r7, #4] + 800287e: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPrescaler, + 8002880: 683b ldr r3, [r7, #0] + 8002882: 6899 ldr r1, [r3, #8] + sClockSourceConfig->ClockPolarity, + 8002884: 683b ldr r3, [r7, #0] + 8002886: 685a ldr r2, [r3, #4] + sClockSourceConfig->ClockFilter); + 8002888: 683b ldr r3, [r7, #0] + 800288a: 68db ldr r3, [r3, #12] + TIM_ETR_SetConfig(htim->Instance, + 800288c: f000 fa36 bl 8002cfc + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + 8002890: 687b ldr r3, [r7, #4] + 8002892: 681b ldr r3, [r3, #0] + 8002894: 689a ldr r2, [r3, #8] + 8002896: 687b ldr r3, [r7, #4] + 8002898: 681b ldr r3, [r3, #0] + 800289a: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 800289e: 609a str r2, [r3, #8] + break; + 80028a0: e03c b.n 800291c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 80028a2: 687b ldr r3, [r7, #4] + 80028a4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80028a6: 683b ldr r3, [r7, #0] + 80028a8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80028aa: 683b ldr r3, [r7, #0] + 80028ac: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 80028ae: 461a mov r2, r3 + 80028b0: f000 f9ad bl 8002c0e + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 80028b4: 687b ldr r3, [r7, #4] + 80028b6: 681b ldr r3, [r3, #0] + 80028b8: 2150 movs r1, #80 @ 0x50 + 80028ba: 4618 mov r0, r3 + 80028bc: f000 fa04 bl 8002cc8 + break; + 80028c0: e02c b.n 800291c + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + 80028c2: 687b ldr r3, [r7, #4] + 80028c4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80028c6: 683b ldr r3, [r7, #0] + 80028c8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80028ca: 683b ldr r3, [r7, #0] + 80028cc: 68db ldr r3, [r3, #12] + TIM_TI2_ConfigInputStage(htim->Instance, + 80028ce: 461a mov r2, r3 + 80028d0: f000 f9cb bl 8002c6a + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 80028d4: 687b ldr r3, [r7, #4] + 80028d6: 681b ldr r3, [r3, #0] + 80028d8: 2160 movs r1, #96 @ 0x60 + 80028da: 4618 mov r0, r3 + 80028dc: f000 f9f4 bl 8002cc8 + break; + 80028e0: e01c b.n 800291c + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + 80028e2: 687b ldr r3, [r7, #4] + 80028e4: 6818 ldr r0, [r3, #0] + sClockSourceConfig->ClockPolarity, + 80028e6: 683b ldr r3, [r7, #0] + 80028e8: 6859 ldr r1, [r3, #4] + sClockSourceConfig->ClockFilter); + 80028ea: 683b ldr r3, [r7, #0] + 80028ec: 68db ldr r3, [r3, #12] + TIM_TI1_ConfigInputStage(htim->Instance, + 80028ee: 461a mov r2, r3 + 80028f0: f000 f98d bl 8002c0e + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 80028f4: 687b ldr r3, [r7, #4] + 80028f6: 681b ldr r3, [r3, #0] + 80028f8: 2140 movs r1, #64 @ 0x40 + 80028fa: 4618 mov r0, r3 + 80028fc: f000 f9e4 bl 8002cc8 + break; + 8002900: e00c b.n 800291c + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 8002902: 687b ldr r3, [r7, #4] + 8002904: 681a ldr r2, [r3, #0] + 8002906: 683b ldr r3, [r7, #0] + 8002908: 681b ldr r3, [r3, #0] + 800290a: 4619 mov r1, r3 + 800290c: 4610 mov r0, r2 + 800290e: f000 f9db bl 8002cc8 + break; + 8002912: e003 b.n 800291c + } + + default: + status = HAL_ERROR; + 8002914: 2301 movs r3, #1 + 8002916: 73fb strb r3, [r7, #15] + break; + 8002918: e000 b.n 800291c + break; + 800291a: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 800291c: 687b ldr r3, [r7, #4] + 800291e: 2201 movs r2, #1 + 8002920: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8002924: 687b ldr r3, [r7, #4] + 8002926: 2200 movs r2, #0 + 8002928: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return status; + 800292c: 7bfb ldrb r3, [r7, #15] +} + 800292e: 4618 mov r0, r3 + 8002930: 3710 adds r7, #16 + 8002932: 46bd mov sp, r7 + 8002934: bd80 pop {r7, pc} + ... + +08002938 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + 8002938: b480 push {r7} + 800293a: b085 sub sp, #20 + 800293c: af00 add r7, sp, #0 + 800293e: 6078 str r0, [r7, #4] + 8002940: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8002942: 687b ldr r3, [r7, #4] + 8002944: 681b ldr r3, [r3, #0] + 8002946: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8002948: 687b ldr r3, [r7, #4] + 800294a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 800294e: d00f beq.n 8002970 + 8002950: 687b ldr r3, [r7, #4] + 8002952: 4a2e ldr r2, [pc, #184] @ (8002a0c ) + 8002954: 4293 cmp r3, r2 + 8002956: d00b beq.n 8002970 + 8002958: 687b ldr r3, [r7, #4] + 800295a: 4a2d ldr r2, [pc, #180] @ (8002a10 ) + 800295c: 4293 cmp r3, r2 + 800295e: d007 beq.n 8002970 + 8002960: 687b ldr r3, [r7, #4] + 8002962: 4a2c ldr r2, [pc, #176] @ (8002a14 ) + 8002964: 4293 cmp r3, r2 + 8002966: d003 beq.n 8002970 + 8002968: 687b ldr r3, [r7, #4] + 800296a: 4a2b ldr r2, [pc, #172] @ (8002a18 ) + 800296c: 4293 cmp r3, r2 + 800296e: d108 bne.n 8002982 + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 8002970: 68fb ldr r3, [r7, #12] + 8002972: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002976: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 8002978: 683b ldr r3, [r7, #0] + 800297a: 685b ldr r3, [r3, #4] + 800297c: 68fa ldr r2, [r7, #12] + 800297e: 4313 orrs r3, r2 + 8002980: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 8002982: 687b ldr r3, [r7, #4] + 8002984: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002988: d017 beq.n 80029ba + 800298a: 687b ldr r3, [r7, #4] + 800298c: 4a1f ldr r2, [pc, #124] @ (8002a0c ) + 800298e: 4293 cmp r3, r2 + 8002990: d013 beq.n 80029ba + 8002992: 687b ldr r3, [r7, #4] + 8002994: 4a1e ldr r2, [pc, #120] @ (8002a10 ) + 8002996: 4293 cmp r3, r2 + 8002998: d00f beq.n 80029ba + 800299a: 687b ldr r3, [r7, #4] + 800299c: 4a1d ldr r2, [pc, #116] @ (8002a14 ) + 800299e: 4293 cmp r3, r2 + 80029a0: d00b beq.n 80029ba + 80029a2: 687b ldr r3, [r7, #4] + 80029a4: 4a1c ldr r2, [pc, #112] @ (8002a18 ) + 80029a6: 4293 cmp r3, r2 + 80029a8: d007 beq.n 80029ba + 80029aa: 687b ldr r3, [r7, #4] + 80029ac: 4a1b ldr r2, [pc, #108] @ (8002a1c ) + 80029ae: 4293 cmp r3, r2 + 80029b0: d003 beq.n 80029ba + 80029b2: 687b ldr r3, [r7, #4] + 80029b4: 4a1a ldr r2, [pc, #104] @ (8002a20 ) + 80029b6: 4293 cmp r3, r2 + 80029b8: d108 bne.n 80029cc + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 80029ba: 68fb ldr r3, [r7, #12] + 80029bc: f423 7340 bic.w r3, r3, #768 @ 0x300 + 80029c0: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 80029c2: 683b ldr r3, [r7, #0] + 80029c4: 68db ldr r3, [r3, #12] + 80029c6: 68fa ldr r2, [r7, #12] + 80029c8: 4313 orrs r3, r2 + 80029ca: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 80029cc: 68fb ldr r3, [r7, #12] + 80029ce: f023 0280 bic.w r2, r3, #128 @ 0x80 + 80029d2: 683b ldr r3, [r7, #0] + 80029d4: 691b ldr r3, [r3, #16] + 80029d6: 4313 orrs r3, r2 + 80029d8: 60fb str r3, [r7, #12] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 80029da: 683b ldr r3, [r7, #0] + 80029dc: 689a ldr r2, [r3, #8] + 80029de: 687b ldr r3, [r7, #4] + 80029e0: 62da str r2, [r3, #44] @ 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 80029e2: 683b ldr r3, [r7, #0] + 80029e4: 681a ldr r2, [r3, #0] + 80029e6: 687b ldr r3, [r7, #4] + 80029e8: 629a str r2, [r3, #40] @ 0x28 + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + 80029ea: 687b ldr r3, [r7, #4] + 80029ec: 681b ldr r3, [r3, #0] + 80029ee: f043 0204 orr.w r2, r3, #4 + 80029f2: 687b ldr r3, [r7, #4] + 80029f4: 601a str r2, [r3, #0] + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 80029f6: 687b ldr r3, [r7, #4] + 80029f8: 2201 movs r2, #1 + 80029fa: 615a str r2, [r3, #20] + + TIMx->CR1 = tmpcr1; + 80029fc: 687b ldr r3, [r7, #4] + 80029fe: 68fa ldr r2, [r7, #12] + 8002a00: 601a str r2, [r3, #0] +} + 8002a02: bf00 nop + 8002a04: 3714 adds r7, #20 + 8002a06: 46bd mov sp, r7 + 8002a08: bc80 pop {r7} + 8002a0a: 4770 bx lr + 8002a0c: 40000400 .word 0x40000400 + 8002a10: 40000800 .word 0x40000800 + 8002a14: 40000c00 .word 0x40000c00 + 8002a18: 40010800 .word 0x40010800 + 8002a1c: 40010c00 .word 0x40010c00 + 8002a20: 40011000 .word 0x40011000 + +08002a24 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002a24: b480 push {r7} + 8002a26: b087 sub sp, #28 + 8002a28: af00 add r7, sp, #0 + 8002a2a: 6078 str r0, [r7, #4] + 8002a2c: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002a2e: 687b ldr r3, [r7, #4] + 8002a30: 6a1b ldr r3, [r3, #32] + 8002a32: 617b str r3, [r7, #20] + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002a34: 687b ldr r3, [r7, #4] + 8002a36: 6a1b ldr r3, [r3, #32] + 8002a38: f023 0201 bic.w r2, r3, #1 + 8002a3c: 687b ldr r3, [r7, #4] + 8002a3e: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002a40: 687b ldr r3, [r7, #4] + 8002a42: 685b ldr r3, [r3, #4] + 8002a44: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002a46: 687b ldr r3, [r7, #4] + 8002a48: 699b ldr r3, [r3, #24] + 8002a4a: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 8002a4c: 68fb ldr r3, [r7, #12] + 8002a4e: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002a52: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 8002a54: 68fb ldr r3, [r7, #12] + 8002a56: f023 0303 bic.w r3, r3, #3 + 8002a5a: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002a5c: 683b ldr r3, [r7, #0] + 8002a5e: 681b ldr r3, [r3, #0] + 8002a60: 68fa ldr r2, [r7, #12] + 8002a62: 4313 orrs r3, r2 + 8002a64: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 8002a66: 697b ldr r3, [r7, #20] + 8002a68: f023 0302 bic.w r3, r3, #2 + 8002a6c: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 8002a6e: 683b ldr r3, [r7, #0] + 8002a70: 689b ldr r3, [r3, #8] + 8002a72: 697a ldr r2, [r7, #20] + 8002a74: 4313 orrs r3, r2 + 8002a76: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002a78: 687b ldr r3, [r7, #4] + 8002a7a: 693a ldr r2, [r7, #16] + 8002a7c: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002a7e: 687b ldr r3, [r7, #4] + 8002a80: 68fa ldr r2, [r7, #12] + 8002a82: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 8002a84: 683b ldr r3, [r7, #0] + 8002a86: 685a ldr r2, [r3, #4] + 8002a88: 687b ldr r3, [r7, #4] + 8002a8a: 635a str r2, [r3, #52] @ 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002a8c: 687b ldr r3, [r7, #4] + 8002a8e: 697a ldr r2, [r7, #20] + 8002a90: 621a str r2, [r3, #32] +} + 8002a92: bf00 nop + 8002a94: 371c adds r7, #28 + 8002a96: 46bd mov sp, r7 + 8002a98: bc80 pop {r7} + 8002a9a: 4770 bx lr + +08002a9c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002a9c: b480 push {r7} + 8002a9e: b087 sub sp, #28 + 8002aa0: af00 add r7, sp, #0 + 8002aa2: 6078 str r0, [r7, #4] + 8002aa4: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002aa6: 687b ldr r3, [r7, #4] + 8002aa8: 6a1b ldr r3, [r3, #32] + 8002aaa: 617b str r3, [r7, #20] + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002aac: 687b ldr r3, [r7, #4] + 8002aae: 6a1b ldr r3, [r3, #32] + 8002ab0: f023 0210 bic.w r2, r3, #16 + 8002ab4: 687b ldr r3, [r7, #4] + 8002ab6: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002ab8: 687b ldr r3, [r7, #4] + 8002aba: 685b ldr r3, [r3, #4] + 8002abc: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 8002abe: 687b ldr r3, [r7, #4] + 8002ac0: 699b ldr r3, [r3, #24] + 8002ac2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 8002ac4: 68fb ldr r3, [r7, #12] + 8002ac6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002aca: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 8002acc: 68fb ldr r3, [r7, #12] + 8002ace: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002ad2: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002ad4: 683b ldr r3, [r7, #0] + 8002ad6: 681b ldr r3, [r3, #0] + 8002ad8: 021b lsls r3, r3, #8 + 8002ada: 68fa ldr r2, [r7, #12] + 8002adc: 4313 orrs r3, r2 + 8002ade: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 8002ae0: 697b ldr r3, [r7, #20] + 8002ae2: f023 0320 bic.w r3, r3, #32 + 8002ae6: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 8002ae8: 683b ldr r3, [r7, #0] + 8002aea: 689b ldr r3, [r3, #8] + 8002aec: 011b lsls r3, r3, #4 + 8002aee: 697a ldr r2, [r7, #20] + 8002af0: 4313 orrs r3, r2 + 8002af2: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002af4: 687b ldr r3, [r7, #4] + 8002af6: 693a ldr r2, [r7, #16] + 8002af8: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8002afa: 687b ldr r3, [r7, #4] + 8002afc: 68fa ldr r2, [r7, #12] + 8002afe: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8002b00: 683b ldr r3, [r7, #0] + 8002b02: 685a ldr r2, [r3, #4] + 8002b04: 687b ldr r3, [r7, #4] + 8002b06: 639a str r2, [r3, #56] @ 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002b08: 687b ldr r3, [r7, #4] + 8002b0a: 697a ldr r2, [r7, #20] + 8002b0c: 621a str r2, [r3, #32] +} + 8002b0e: bf00 nop + 8002b10: 371c adds r7, #28 + 8002b12: 46bd mov sp, r7 + 8002b14: bc80 pop {r7} + 8002b16: 4770 bx lr + +08002b18 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002b18: b480 push {r7} + 8002b1a: b087 sub sp, #28 + 8002b1c: af00 add r7, sp, #0 + 8002b1e: 6078 str r0, [r7, #4] + 8002b20: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002b22: 687b ldr r3, [r7, #4] + 8002b24: 6a1b ldr r3, [r3, #32] + 8002b26: 617b str r3, [r7, #20] + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8002b28: 687b ldr r3, [r7, #4] + 8002b2a: 6a1b ldr r3, [r3, #32] + 8002b2c: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8002b30: 687b ldr r3, [r7, #4] + 8002b32: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002b34: 687b ldr r3, [r7, #4] + 8002b36: 685b ldr r3, [r3, #4] + 8002b38: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002b3a: 687b ldr r3, [r7, #4] + 8002b3c: 69db ldr r3, [r3, #28] + 8002b3e: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 8002b40: 68fb ldr r3, [r7, #12] + 8002b42: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002b46: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 8002b48: 68fb ldr r3, [r7, #12] + 8002b4a: f023 0303 bic.w r3, r3, #3 + 8002b4e: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8002b50: 683b ldr r3, [r7, #0] + 8002b52: 681b ldr r3, [r3, #0] + 8002b54: 68fa ldr r2, [r7, #12] + 8002b56: 4313 orrs r3, r2 + 8002b58: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 8002b5a: 697b ldr r3, [r7, #20] + 8002b5c: f423 7300 bic.w r3, r3, #512 @ 0x200 + 8002b60: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 8002b62: 683b ldr r3, [r7, #0] + 8002b64: 689b ldr r3, [r3, #8] + 8002b66: 021b lsls r3, r3, #8 + 8002b68: 697a ldr r2, [r7, #20] + 8002b6a: 4313 orrs r3, r2 + 8002b6c: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002b6e: 687b ldr r3, [r7, #4] + 8002b70: 693a ldr r2, [r7, #16] + 8002b72: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002b74: 687b ldr r3, [r7, #4] + 8002b76: 68fa ldr r2, [r7, #12] + 8002b78: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 8002b7a: 683b ldr r3, [r7, #0] + 8002b7c: 685a ldr r2, [r3, #4] + 8002b7e: 687b ldr r3, [r7, #4] + 8002b80: 63da str r2, [r3, #60] @ 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002b82: 687b ldr r3, [r7, #4] + 8002b84: 697a ldr r2, [r7, #20] + 8002b86: 621a str r2, [r3, #32] +} + 8002b88: bf00 nop + 8002b8a: 371c adds r7, #28 + 8002b8c: 46bd mov sp, r7 + 8002b8e: bc80 pop {r7} + 8002b90: 4770 bx lr + +08002b92 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + 8002b92: b480 push {r7} + 8002b94: b087 sub sp, #28 + 8002b96: af00 add r7, sp, #0 + 8002b98: 6078 str r0, [r7, #4] + 8002b9a: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8002b9c: 687b ldr r3, [r7, #4] + 8002b9e: 6a1b ldr r3, [r3, #32] + 8002ba0: 617b str r3, [r7, #20] + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8002ba2: 687b ldr r3, [r7, #4] + 8002ba4: 6a1b ldr r3, [r3, #32] + 8002ba6: f423 5280 bic.w r2, r3, #4096 @ 0x1000 + 8002baa: 687b ldr r3, [r7, #4] + 8002bac: 621a str r2, [r3, #32] + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8002bae: 687b ldr r3, [r7, #4] + 8002bb0: 685b ldr r3, [r3, #4] + 8002bb2: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 8002bb4: 687b ldr r3, [r7, #4] + 8002bb6: 69db ldr r3, [r3, #28] + 8002bb8: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8002bba: 68fb ldr r3, [r7, #12] + 8002bbc: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 + 8002bc0: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8002bc2: 68fb ldr r3, [r7, #12] + 8002bc4: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8002bc8: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 8002bca: 683b ldr r3, [r7, #0] + 8002bcc: 681b ldr r3, [r3, #0] + 8002bce: 021b lsls r3, r3, #8 + 8002bd0: 68fa ldr r2, [r7, #12] + 8002bd2: 4313 orrs r3, r2 + 8002bd4: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 8002bd6: 697b ldr r3, [r7, #20] + 8002bd8: f423 5300 bic.w r3, r3, #8192 @ 0x2000 + 8002bdc: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 8002bde: 683b ldr r3, [r7, #0] + 8002be0: 689b ldr r3, [r3, #8] + 8002be2: 031b lsls r3, r3, #12 + 8002be4: 697a ldr r2, [r7, #20] + 8002be6: 4313 orrs r3, r2 + 8002be8: 617b str r3, [r7, #20] + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8002bea: 687b ldr r3, [r7, #4] + 8002bec: 693a ldr r2, [r7, #16] + 8002bee: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 8002bf0: 687b ldr r3, [r7, #4] + 8002bf2: 68fa ldr r2, [r7, #12] + 8002bf4: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 8002bf6: 683b ldr r3, [r7, #0] + 8002bf8: 685a ldr r2, [r3, #4] + 8002bfa: 687b ldr r3, [r7, #4] + 8002bfc: 641a str r2, [r3, #64] @ 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8002bfe: 687b ldr r3, [r7, #4] + 8002c00: 697a ldr r2, [r7, #20] + 8002c02: 621a str r2, [r3, #32] +} + 8002c04: bf00 nop + 8002c06: 371c adds r7, #28 + 8002c08: 46bd mov sp, r7 + 8002c0a: bc80 pop {r7} + 8002c0c: 4770 bx lr + +08002c0e : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002c0e: b480 push {r7} + 8002c10: b087 sub sp, #28 + 8002c12: af00 add r7, sp, #0 + 8002c14: 60f8 str r0, [r7, #12] + 8002c16: 60b9 str r1, [r7, #8] + 8002c18: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8002c1a: 68fb ldr r3, [r7, #12] + 8002c1c: 6a1b ldr r3, [r3, #32] + 8002c1e: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 8002c20: 68fb ldr r3, [r7, #12] + 8002c22: 6a1b ldr r3, [r3, #32] + 8002c24: f023 0201 bic.w r2, r3, #1 + 8002c28: 68fb ldr r3, [r7, #12] + 8002c2a: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8002c2c: 68fb ldr r3, [r7, #12] + 8002c2e: 699b ldr r3, [r3, #24] + 8002c30: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8002c32: 693b ldr r3, [r7, #16] + 8002c34: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8002c38: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8002c3a: 687b ldr r3, [r7, #4] + 8002c3c: 011b lsls r3, r3, #4 + 8002c3e: 693a ldr r2, [r7, #16] + 8002c40: 4313 orrs r3, r2 + 8002c42: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 8002c44: 697b ldr r3, [r7, #20] + 8002c46: f023 030a bic.w r3, r3, #10 + 8002c4a: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8002c4c: 697a ldr r2, [r7, #20] + 8002c4e: 68bb ldr r3, [r7, #8] + 8002c50: 4313 orrs r3, r2 + 8002c52: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 8002c54: 68fb ldr r3, [r7, #12] + 8002c56: 693a ldr r2, [r7, #16] + 8002c58: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8002c5a: 68fb ldr r3, [r7, #12] + 8002c5c: 697a ldr r2, [r7, #20] + 8002c5e: 621a str r2, [r3, #32] +} + 8002c60: bf00 nop + 8002c62: 371c adds r7, #28 + 8002c64: 46bd mov sp, r7 + 8002c66: bc80 pop {r7} + 8002c68: 4770 bx lr + +08002c6a : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8002c6a: b480 push {r7} + 8002c6c: b087 sub sp, #28 + 8002c6e: af00 add r7, sp, #0 + 8002c70: 60f8 str r0, [r7, #12] + 8002c72: 60b9 str r1, [r7, #8] + 8002c74: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + 8002c76: 68fb ldr r3, [r7, #12] + 8002c78: 6a1b ldr r3, [r3, #32] + 8002c7a: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC2E; + 8002c7c: 68fb ldr r3, [r7, #12] + 8002c7e: 6a1b ldr r3, [r3, #32] + 8002c80: f023 0210 bic.w r2, r3, #16 + 8002c84: 68fb ldr r3, [r7, #12] + 8002c86: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8002c88: 68fb ldr r3, [r7, #12] + 8002c8a: 699b ldr r3, [r3, #24] + 8002c8c: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8002c8e: 693b ldr r3, [r7, #16] + 8002c90: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 8002c94: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 12U); + 8002c96: 687b ldr r3, [r7, #4] + 8002c98: 031b lsls r3, r3, #12 + 8002c9a: 693a ldr r2, [r7, #16] + 8002c9c: 4313 orrs r3, r2 + 8002c9e: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8002ca0: 697b ldr r3, [r7, #20] + 8002ca2: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 8002ca6: 617b str r3, [r7, #20] + tmpccer |= (TIM_ICPolarity << 4U); + 8002ca8: 68bb ldr r3, [r7, #8] + 8002caa: 011b lsls r3, r3, #4 + 8002cac: 697a ldr r2, [r7, #20] + 8002cae: 4313 orrs r3, r2 + 8002cb0: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 8002cb2: 68fb ldr r3, [r7, #12] + 8002cb4: 693a ldr r2, [r7, #16] + 8002cb6: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8002cb8: 68fb ldr r3, [r7, #12] + 8002cba: 697a ldr r2, [r7, #20] + 8002cbc: 621a str r2, [r3, #32] +} + 8002cbe: bf00 nop + 8002cc0: 371c adds r7, #28 + 8002cc2: 46bd mov sp, r7 + 8002cc4: bc80 pop {r7} + 8002cc6: 4770 bx lr + +08002cc8 : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 8002cc8: b480 push {r7} + 8002cca: b085 sub sp, #20 + 8002ccc: af00 add r7, sp, #0 + 8002cce: 6078 str r0, [r7, #4] + 8002cd0: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8002cd2: 687b ldr r3, [r7, #4] + 8002cd4: 689b ldr r3, [r3, #8] + 8002cd6: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8002cd8: 68fb ldr r3, [r7, #12] + 8002cda: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002cde: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8002ce0: 683a ldr r2, [r7, #0] + 8002ce2: 68fb ldr r3, [r7, #12] + 8002ce4: 4313 orrs r3, r2 + 8002ce6: f043 0307 orr.w r3, r3, #7 + 8002cea: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8002cec: 687b ldr r3, [r7, #4] + 8002cee: 68fa ldr r2, [r7, #12] + 8002cf0: 609a str r2, [r3, #8] +} + 8002cf2: bf00 nop + 8002cf4: 3714 adds r7, #20 + 8002cf6: 46bd mov sp, r7 + 8002cf8: bc80 pop {r7} + 8002cfa: 4770 bx lr + +08002cfc : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8002cfc: b480 push {r7} + 8002cfe: b087 sub sp, #28 + 8002d00: af00 add r7, sp, #0 + 8002d02: 60f8 str r0, [r7, #12] + 8002d04: 60b9 str r1, [r7, #8] + 8002d06: 607a str r2, [r7, #4] + 8002d08: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 8002d0a: 68fb ldr r3, [r7, #12] + 8002d0c: 689b ldr r3, [r3, #8] + 8002d0e: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8002d10: 697b ldr r3, [r7, #20] + 8002d12: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 8002d16: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8002d18: 683b ldr r3, [r7, #0] + 8002d1a: 021a lsls r2, r3, #8 + 8002d1c: 687b ldr r3, [r7, #4] + 8002d1e: 431a orrs r2, r3 + 8002d20: 68bb ldr r3, [r7, #8] + 8002d22: 4313 orrs r3, r2 + 8002d24: 697a ldr r2, [r7, #20] + 8002d26: 4313 orrs r3, r2 + 8002d28: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8002d2a: 68fb ldr r3, [r7, #12] + 8002d2c: 697a ldr r2, [r7, #20] + 8002d2e: 609a str r2, [r3, #8] +} + 8002d30: bf00 nop + 8002d32: 371c adds r7, #28 + 8002d34: 46bd mov sp, r7 + 8002d36: bc80 pop {r7} + 8002d38: 4770 bx lr + +08002d3a : + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + 8002d3a: b480 push {r7} + 8002d3c: b087 sub sp, #28 + 8002d3e: af00 add r7, sp, #0 + 8002d40: 60f8 str r0, [r7, #12] + 8002d42: 60b9 str r1, [r7, #8] + 8002d44: 607a str r2, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 8002d46: 68bb ldr r3, [r7, #8] + 8002d48: f003 031f and.w r3, r3, #31 + 8002d4c: 2201 movs r2, #1 + 8002d4e: fa02 f303 lsl.w r3, r2, r3 + 8002d52: 617b str r3, [r7, #20] + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + 8002d54: 68fb ldr r3, [r7, #12] + 8002d56: 6a1a ldr r2, [r3, #32] + 8002d58: 697b ldr r3, [r7, #20] + 8002d5a: 43db mvns r3, r3 + 8002d5c: 401a ands r2, r3 + 8002d5e: 68fb ldr r3, [r7, #12] + 8002d60: 621a str r2, [r3, #32] + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8002d62: 68fb ldr r3, [r7, #12] + 8002d64: 6a1a ldr r2, [r3, #32] + 8002d66: 68bb ldr r3, [r7, #8] + 8002d68: f003 031f and.w r3, r3, #31 + 8002d6c: 6879 ldr r1, [r7, #4] + 8002d6e: fa01 f303 lsl.w r3, r1, r3 + 8002d72: 431a orrs r2, r3 + 8002d74: 68fb ldr r3, [r7, #12] + 8002d76: 621a str r2, [r3, #32] +} + 8002d78: bf00 nop + 8002d7a: 371c adds r7, #28 + 8002d7c: 46bd mov sp, r7 + 8002d7e: bc80 pop {r7} + 8002d80: 4770 bx lr + ... + +08002d84 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8002d84: b480 push {r7} + 8002d86: b085 sub sp, #20 + 8002d88: af00 add r7, sp, #0 + 8002d8a: 6078 str r0, [r7, #4] + 8002d8c: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 8002d8e: 687b ldr r3, [r7, #4] + 8002d90: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 8002d94: 2b01 cmp r3, #1 + 8002d96: d101 bne.n 8002d9c + 8002d98: 2302 movs r3, #2 + 8002d9a: e046 b.n 8002e2a + 8002d9c: 687b ldr r3, [r7, #4] + 8002d9e: 2201 movs r2, #1 + 8002da0: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8002da4: 687b ldr r3, [r7, #4] + 8002da6: 2202 movs r2, #2 + 8002da8: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8002dac: 687b ldr r3, [r7, #4] + 8002dae: 681b ldr r3, [r3, #0] + 8002db0: 685b ldr r3, [r3, #4] + 8002db2: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8002db4: 687b ldr r3, [r7, #4] + 8002db6: 681b ldr r3, [r3, #0] + 8002db8: 689b ldr r3, [r3, #8] + 8002dba: 60bb str r3, [r7, #8] + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8002dbc: 68fb ldr r3, [r7, #12] + 8002dbe: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8002dc2: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8002dc4: 683b ldr r3, [r7, #0] + 8002dc6: 681b ldr r3, [r3, #0] + 8002dc8: 68fa ldr r2, [r7, #12] + 8002dca: 4313 orrs r3, r2 + 8002dcc: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8002dce: 687b ldr r3, [r7, #4] + 8002dd0: 681b ldr r3, [r3, #0] + 8002dd2: 68fa ldr r2, [r7, #12] + 8002dd4: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8002dd6: 687b ldr r3, [r7, #4] + 8002dd8: 681b ldr r3, [r3, #0] + 8002dda: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8002dde: d00e beq.n 8002dfe + 8002de0: 687b ldr r3, [r7, #4] + 8002de2: 681b ldr r3, [r3, #0] + 8002de4: 4a13 ldr r2, [pc, #76] @ (8002e34 ) + 8002de6: 4293 cmp r3, r2 + 8002de8: d009 beq.n 8002dfe + 8002dea: 687b ldr r3, [r7, #4] + 8002dec: 681b ldr r3, [r3, #0] + 8002dee: 4a12 ldr r2, [pc, #72] @ (8002e38 ) + 8002df0: 4293 cmp r3, r2 + 8002df2: d004 beq.n 8002dfe + 8002df4: 687b ldr r3, [r7, #4] + 8002df6: 681b ldr r3, [r3, #0] + 8002df8: 4a10 ldr r2, [pc, #64] @ (8002e3c ) + 8002dfa: 4293 cmp r3, r2 + 8002dfc: d10c bne.n 8002e18 + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8002dfe: 68bb ldr r3, [r7, #8] + 8002e00: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8002e04: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8002e06: 683b ldr r3, [r7, #0] + 8002e08: 685b ldr r3, [r3, #4] + 8002e0a: 68ba ldr r2, [r7, #8] + 8002e0c: 4313 orrs r3, r2 + 8002e0e: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8002e10: 687b ldr r3, [r7, #4] + 8002e12: 681b ldr r3, [r3, #0] + 8002e14: 68ba ldr r2, [r7, #8] + 8002e16: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8002e18: 687b ldr r3, [r7, #4] + 8002e1a: 2201 movs r2, #1 + 8002e1c: f883 2039 strb.w r2, [r3, #57] @ 0x39 + + __HAL_UNLOCK(htim); + 8002e20: 687b ldr r3, [r7, #4] + 8002e22: 2200 movs r2, #0 + 8002e24: f883 2038 strb.w r2, [r3, #56] @ 0x38 + + return HAL_OK; + 8002e28: 2300 movs r3, #0 +} + 8002e2a: 4618 mov r0, r3 + 8002e2c: 3714 adds r7, #20 + 8002e2e: 46bd mov sp, r7 + 8002e30: bc80 pop {r7} + 8002e32: 4770 bx lr + 8002e34: 40000400 .word 0x40000400 + 8002e38: 40000800 .word 0x40000800 + 8002e3c: 40010800 .word 0x40010800 + +08002e40 : + 8002e40: 4603 mov r3, r0 + 8002e42: 4402 add r2, r0 + 8002e44: 4293 cmp r3, r2 + 8002e46: d100 bne.n 8002e4a + 8002e48: 4770 bx lr + 8002e4a: f803 1b01 strb.w r1, [r3], #1 + 8002e4e: e7f9 b.n 8002e44 + +08002e50 <__libc_init_array>: + 8002e50: b570 push {r4, r5, r6, lr} + 8002e52: 2600 movs r6, #0 + 8002e54: 4d0c ldr r5, [pc, #48] @ (8002e88 <__libc_init_array+0x38>) + 8002e56: 4c0d ldr r4, [pc, #52] @ (8002e8c <__libc_init_array+0x3c>) + 8002e58: 1b64 subs r4, r4, r5 + 8002e5a: 10a4 asrs r4, r4, #2 + 8002e5c: 42a6 cmp r6, r4 + 8002e5e: d109 bne.n 8002e74 <__libc_init_array+0x24> + 8002e60: f000 f81a bl 8002e98 <_init> + 8002e64: 2600 movs r6, #0 + 8002e66: 4d0a ldr r5, [pc, #40] @ (8002e90 <__libc_init_array+0x40>) + 8002e68: 4c0a ldr r4, [pc, #40] @ (8002e94 <__libc_init_array+0x44>) + 8002e6a: 1b64 subs r4, r4, r5 + 8002e6c: 10a4 asrs r4, r4, #2 + 8002e6e: 42a6 cmp r6, r4 + 8002e70: d105 bne.n 8002e7e <__libc_init_array+0x2e> + 8002e72: bd70 pop {r4, r5, r6, pc} + 8002e74: f855 3b04 ldr.w r3, [r5], #4 + 8002e78: 4798 blx r3 + 8002e7a: 3601 adds r6, #1 + 8002e7c: e7ee b.n 8002e5c <__libc_init_array+0xc> + 8002e7e: f855 3b04 ldr.w r3, [r5], #4 + 8002e82: 4798 blx r3 + 8002e84: 3601 adds r6, #1 + 8002e86: e7f2 b.n 8002e6e <__libc_init_array+0x1e> + 8002e88: 08002ef4 .word 0x08002ef4 + 8002e8c: 08002ef4 .word 0x08002ef4 + 8002e90: 08002ef4 .word 0x08002ef4 + 8002e94: 08002ef8 .word 0x08002ef8 + +08002e98 <_init>: + 8002e98: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002e9a: bf00 nop + 8002e9c: bcf8 pop {r3, r4, r5, r6, r7} + 8002e9e: bc08 pop {r3} + 8002ea0: 469e mov lr, r3 + 8002ea2: 4770 bx lr + +08002ea4 <_fini>: + 8002ea4: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002ea6: bf00 nop + 8002ea8: bcf8 pop {r3, r4, r5, r6, r7} + 8002eaa: bc08 pop {r3} + 8002eac: 469e mov lr, r3 + 8002eae: 4770 bx lr diff --git a/TP4_INIT_TFT/Debug/TP4_MELODIE.map b/TP4_INIT_TFT/Debug/TP4_MELODIE.map new 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./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o +LOAD ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o +START GROUP +LOAD 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0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + 0x08002ef4 __exidx_end = . + 0x08002ef4 . = ALIGN (0x4) + +.preinit_array 0x08002ef4 0x0 + 0x08002ef4 . = ALIGN (0x4) + 0x08002ef4 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x08002ef4 PROVIDE (__preinit_array_end = .) + 0x08002ef4 . = ALIGN (0x4) + +.init_array 0x08002ef4 0x4 + 0x08002ef4 . = ALIGN (0x4) + 0x08002ef4 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x08002ef4 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + 0x08002ef8 PROVIDE (__init_array_end = .) + 0x08002ef8 . = ALIGN (0x4) + +.fini_array 0x08002ef8 0x4 + 0x08002ef8 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x08002ef8 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08002efc . = ALIGN (0x4) + 0x08002efc _sidata = LOADADDR (.data) + +.rel.dyn 0x08002efc 0x0 + .rel.iplt 0x08002efc 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + +.data 0x20000000 0xc load address 0x08002efc + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x20000000 0x4 ./Core/Src/system_stm32l1xx.o + 0x20000000 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100644 index 0000000..bb78ad5 --- /dev/null +++ b/TP4_INIT_TFT/Debug/makefile @@ -0,0 +1,96 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Drivers/TFT_ST7735/subdir.mk +-include Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk +-include Drivers/7Seg_MAX7219/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := TP4_INIT_TFT +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +TP4_INIT_TFT.elf \ + +MAP_FILES += \ +TP4_INIT_TFT.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +TP4_INIT_TFT.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: TP4_INIT_TFT.elf secondary-outputs + +# Tool invocations +TP4_INIT_TFT.elf TP4_INIT_TFT.map: $(OBJS) $(USER_OBJS) /Users/felixmarquet/Nextcloud/Programation/STM32/TP4_INIT_TFT/STM32L152RETX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "TP4_INIT_TFT.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m3 -T"/Users/felixmarquet/Nextcloud/Programation/STM32/TP4_INIT_TFT/STM32L152RETX_FLASH.ld" --specs=nosys.specs -Wl,-Map="TP4_INIT_TFT.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +TP4_INIT_TFT.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "TP4_INIT_TFT.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) TP4_INIT_TFT.elf TP4_INIT_TFT.list TP4_INIT_TFT.map default.size.stdout + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/TP4_INIT_TFT/Debug/objects.list b/TP4_INIT_TFT/Debug/objects.list new file mode 100644 index 0000000..2e3876b --- /dev/null +++ b/TP4_INIT_TFT/Debug/objects.list @@ -0,0 +1,22 @@ +"./Core/Src/main.o" +"./Core/Src/stm32l1xx_hal_msp.o" +"./Core/Src/stm32l1xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32l1xx.o" +"./Core/Startup/startup_stm32l152retx.o" +"./Drivers/7Seg_MAX7219/max7219.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o" +"./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o" +"./Drivers/TFT_ST7735/fonc_tft.o" diff --git a/TP4_INIT_TFT/Debug/objects.mk b/TP4_INIT_TFT/Debug/objects.mk new file mode 100644 index 0000000..b471e98 --- /dev/null +++ b/TP4_INIT_TFT/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/TP4_INIT_TFT/Debug/sources.mk b/TP4_INIT_TFT/Debug/sources.mk new file mode 100644 index 0000000..3e989bd --- /dev/null +++ b/TP4_INIT_TFT/Debug/sources.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/7Seg_MAX7219 \ +Drivers/STM32L1xx_HAL_Driver/Src \ +Drivers/TFT_ST7735 \ + diff --git a/TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.c b/TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.c new file mode 100644 index 0000000..5a71248 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.c @@ -0,0 +1,269 @@ +/* +********************************************************************************************************* +* Module : MAX7219.C +* Author : Randy Rasa modifié par Alain REBOUX pour STM32 +* Description: MAX7219 LED Display Driver Routines +* +* The Maxim MAX7219 is an LED display driver thant can control up to 64 individual LEDs, or +* eight 7-segment LED digits, or any combination of individual LEDs and digits. It frees the +* host from the chore of constantly multiplexing the 8 rows and 8 columns. In addition, it +* takes care of brightness control (16 steps), and implements display test and display blank +* (shutdown) features. +* +* The host communicates with the MAX7219 using three signals: DATA, CLK, and LOAD. This +* modules bit-bangs them, but Motorola's SPI interface (or similar interface from other +* manufacturers) may also be used to simplify and speed up the data transfer. +* ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ +* DATA _________|D15|D14|D13|D12|D11|D10|D09|D08|D07|D06|D05|D04|D03|D02|D01|D00|______ +* ________ __ __ __ __ __ __ __ __ __ __ ________ +* CLK |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| +* __________________________________________________________________ +* LOAD ______| |__ + +/* +********************************************************************************************************* +* Include Header Files +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* Include Header Files +********************************************************************************************************* +*/ + +#include "main.h" +#include "max7219.h" +extern SPI_HandleTypeDef hspi1; + +/*defined in main.h +#define MAX7219_nCS_PORT GPIOC +#define MAX7219_nCS_PIN GPIO_PIN_0 +*/ + +//Constantes + +/* +********************************************************************************************************* +* LED Segments: a +* ---- +* f| |b +* | g | +* ---- +* e| |c +* | | +* ---- o dp +* d +* Register bits: +* bit: 7 6 5 4 3 2 1 0 +* dp a b c d e f g +********************************************************************************************************* +*/ + + +char const conv_7seg[]={0x7E,0x30,0x6D,0x79,0x33,0x5B,0x5F,0x70,0x7F,0x7B,0x77,0x1F,0x4E,0x3D,0x4F,0x47}; + + +// define +#define REG_DECODE 0x09 // "decode mode" register +#define REG_INTENSITY 0x0a // "intensity" register +#define REG_SCAN_LIMIT 0x0b // "scan limit" register +#define REG_SHUTDOWN 0x0c // "shutdown" register +#define REG_DISPLAY_TEST 0x0f // "display test" register + +#define INTENSITY_MIN 0x00 // minimum display intensity +#define INTENSITY_MAX 0x0f // maximum display intensity + + +/* +********************************************************************************************************* +* Private Function Prototypes +********************************************************************************************************* +*/ + void MAX7219_Write (unsigned char reg_number, unsigned char data); +static void MAX7219_SendByte (unsigned char data); + + + +// ...................................... Public Functions .............................................. + + +/* +********************************************************************************************************* +* MAX7219_Init() +* +* Description: Initialize MAX7219 module; must be called before any other MAX7219 functions. +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Init (void) +{ + // configure "LOAD" as output + + MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits + MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits + MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) + MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) + MAX7219_Clear(); // clear all digits + MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity +} + +/* +********************************************************************************************************* +* MAX7219_ShutdownStart() +* +* Description: Shut down the display. +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStart (void) +{ + MAX7219_Write(REG_SHUTDOWN, 0); // put MAX7219 into "shutdown" mode +} + + +/* +********************************************************************************************************* +* MAX7219_ShutdownStop() +* +* Description: Take the display out of shutdown mode. +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_ShutdownStop (void) +{ + MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode +} +/* +********************************************************************************************************* +* MAX7219_DisplayTestStart() +* +* Description: Start a display test. +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStart (void) +{ + MAX7219_Write(REG_DISPLAY_TEST, 1); // put MAX7219 into "display test" mode +} + + + +/* +********************************************************************************************************* +* MAX7219_DisplayTestStop() +* +* Description: Stop a display test. +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayTestStop (void) +{ + MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode +} + + +/* +********************************************************************************************************* +* MAX7219_SetBrightness() +* +* Description: Set the LED display brightness +* Arguments : brightness (0-15) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_SetBrightness (char brightness) +{ + brightness &= 0x0f; // mask off extra bits + MAX7219_Write(REG_INTENSITY, brightness); // set brightness +} + + +/* +********************************************************************************************************* +* MAX7219_Clear() +* +* Description: Clear the display (all digits blank) +* Arguments : none +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Clear (void) +{ + char i; + for (i=0; i < 8; i++) + MAX7219_Write(i, 0x00); // turn all segments off +} + + +/* +********************************************************************************************************* +* MAX7219_DisplayChar() = MAX7219_DisplayCharPointOff(), MAX7219_DisplayCharPointON() +* +* Description: Display a character on the specified digit. +* Arguments : digit = digit number (0-7) +* character = character to display (0-9, A-Z) +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_DisplayChar(char digit, char character) +{ + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]); +} + +void MAX7219_DisplayCharPointOff (char digit, char character) +{ + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]); +} +void MAX7219_DisplayCharPointOn (char digit, char character) +{ + //MAX7219_Write(digit, MAX7219_LookupCode(character)); + MAX7219_Write(digit, conv_7seg[character]|128); +} + + + +/* +********************************************************************************************************* +* MAX7219_Write() +* +* Description: Write to MAX7219 +* Arguments : reg_number = register to write to +* dataout = data to write to MAX7219 +* Returns : none +********************************************************************************************************* +*/ +void MAX7219_Write (unsigned char reg_number, unsigned char dataout) +{ + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin + MAX7219_SendByte(reg_number); // write register number to MAX7219 + MAX7219_SendByte(dataout); // write data to MAX7219 + MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data + } + + +/* +********************************************************************************************************* +* MAX7219_SendByte() +* +* Description: Send one byte to the MAX7219 +* Arguments : dataout = data to send +* Returns : none +********************************************************************************************************* +*/ + +static void MAX7219_SendByte (unsigned char dataout) +{ + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); + +} + + diff --git a/TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.h b/TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.h new file mode 100644 index 0000000..9ce37ee --- /dev/null +++ b/TP4_INIT_TFT/Drivers/7Seg_MAX7219/max7219.h @@ -0,0 +1,15 @@ +void MAX7219_Init(void); +void MAX7219_ShutdownStart(void); +void MAX7219_ShutdownStop(void); +void MAX7219_DisplayTestStart(void); +void MAX7219_DisplayTestStop(void); +void MAX7219_SetBrightness(char brightness); +void MAX7219_Clear(void); +void MAX7219_DisplayChar(char digit, char character); +void MAX7219_DisplayCharPointOff(char digit, char character); +void MAX7219_DisplayCharPointOn(char digit, char character); + +// ST7735 CS (Chip Select) pin +#define MAX7219_nCS_PORT GPIOC //A +#define MAX7219_nCS_PIN GPIO_PIN_0 //8 + diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h b/TP4_INIT_TFT/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h new file mode 100644 index 0000000..dbe7432 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h @@ -0,0 +1,9022 @@ +/** + ****************************************************************************** + * @file stm32l152xe.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l152xe + * @{ + */ + +#ifndef __STM32L152xE_H +#define __STM32L152xE_H + +#ifdef __cplusplus + extern "C" { +#endif + + + /** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + UART4_IRQn = 48, /*!< UART4 global Interrupt */ + UART5_IRQn = 49, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32l1xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*! 0x7C */ + __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */ + __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */ +} OB_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ +} OPAMP_Common_TypeDef; + +/** + * @brief General Purpose IO + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ + __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ + __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ +} RCC_TypeDef; + +/** + * @brief Routing Interface + */ + +typedef struct +{ + __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ +} RI_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + uint32_t RESERVED12; /*!< Reserved, 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + uint32_t RESERVED17; /*!< Reserved, 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ +#define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /*!< FLASH EEPROM base address in the alias region */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */ +#define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */ +#define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */ +#define FLASH_END (0x0807FFFFUL) /*!< Program end FLASH address for Cat5 */ +#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) +#define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) + +/* USB device FS */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ + +/* USB device FS SRAM */ +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) +#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL) +#define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CUL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL) +#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL) +#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) + +/*!< AHB peripherals */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */ +#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ +#define FLASHSIZE_BASE (0x1FF800CCUL) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define UID_BASE (0x1FF800D0UL) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) +#define DBGMCU_BASE (0xE0042000UL) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +/* USB device FS */ +#define USB ((USB_TypeDef *) USB_BASE) +/* USB device FS SRAM */ +#define PWR ((PWR_TypeDef *) PWR_BASE) + +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +/* Legacy define */ +#define DAC DAC1 + +#define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ +#define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ +#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ + +#define RI ((RI_TypeDef *) RI_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) +#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +/* Legacy defines */ +#define ADC ADC1_COMMON + +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + + /** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_armclang.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..162a400 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_compiler.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..94212eb --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_gcc.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..2d9db15 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_iccarm.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..11c4af0 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_version.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_armv8mbl.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..251e4ed --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_armv8mml.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..3a3148e --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm0.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..f929bba --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm0plus.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..424011a --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm1.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..0ed678e --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm23.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..acbc5df --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm3.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..74bff64 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm33.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..6cd2db7 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm4.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..7d56873 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm7.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..a14dc62 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_sc000.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9b67c92 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/core_sc300.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..3e8a471 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/mpu_armv7.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..0142203 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/mpu_armv8.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..62571da --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/TP4_INIT_TFT/Drivers/CMSIS/Include/tz_context.h b/TP4_INIT_TFT/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/TP4_INIT_TFT/Drivers/CMSIS/LICENSE.txt b/TP4_INIT_TFT/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/TP4_INIT_TFT/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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+++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4422 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h new file mode 100644 index 0000000..54d3ad0 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h @@ -0,0 +1,995 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_H +#define __STM32L1xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_conf.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +#define HAL_TICK_FREQ_10HZ 100U +#define HAL_TICK_FREQ_100HZ 10U +#define HAL_TICK_FREQ_1KHZ 1U +#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ + +#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \ + ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \ + ((__FREQ__) == HAL_TICK_FREQ_1KHZ)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ + +#define SYSCFG_BOOT_MAINFLASH (0x00000000U) +#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0) +#if defined(FSMC_R_BASE) +#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1) +#endif /* FSMC_R_BASE */ +#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RI_Constants RI: Routing Interface + * @{ + */ + +/** @defgroup RI_InputCapture Input Capture + * @{ + */ + +#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ +#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ +#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ +#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ + +/** + * @} + */ + +/** @defgroup TIM_Select TIM Select + * @{ + */ + +#define TIM_SELECT_NONE (0x00000000U) /*!< None selected */ +#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */ +#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */ +#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */ + +#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \ + ((__TIM__) == TIM_SELECT_TIM2) || \ + ((__TIM__) == TIM_SELECT_TIM3) || \ + ((__TIM__) == TIM_SELECT_TIM4)) + +/** + * @} + */ + +/** @defgroup RI_InputCaptureRouting Input Capture Routing + * @{ + */ + /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ +#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */ +#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */ +#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */ +#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */ +#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */ +#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */ +#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */ +#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */ +#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */ +#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */ +#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */ +#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */ +#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */ +#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */ +#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */ +#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */ + +#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \ + ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15)) + +/** + * @} + */ + +/** @defgroup RI_IOSwitch IO Switch + * @{ + */ +#define RI_ASCR1_REGISTER (0x80000000U) +/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ +#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0) +#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1) +#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2) +#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3) +#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4) +#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5) +#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6) +#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7) +#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8) +#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9) +#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10) +#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11) +#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12) +#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13) +#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14) +#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15) +#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18) +#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19) +#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20) +#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21) +#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22) +#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23) +#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24) +#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25) +#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */ +#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ +#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27) +#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28) +#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29) +#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30) +#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31) +#endif /* RI_ASCR2_CH1b */ + +/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ +#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1) +#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2) +#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3) +#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4) +#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1) +#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2) +#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1) +#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2) +#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3) +#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1) +#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2) +#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3) +#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */ +#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b) +#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ +#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b) +#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b) +#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b) +#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b) +#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b) +#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b) +#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b) +#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b) +#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b) +#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b) +#endif /* RI_ASCR2_CH1b */ +#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3) +#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4) +#endif /* RI_ASCR2_CH0b */ + + +#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ + +#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ + ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12b)) + +#else /* !RI_ASCR2_CH1b */ + +#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */ + +#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ + ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b)) + +#else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */ + +#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ + ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ + ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ + ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)) + +#endif /* RI_ASCR2_CH0b */ +#endif /* RI_ASCR2_CH1b */ + +/** + * @} + */ + +/** @defgroup RI_Pin PIN define + * @{ + */ +#define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU + * @{ + */ + +/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode + * @brief Freeze/Unfreeze Peripherals in Debug mode + * @{ + */ + +/** + * @brief TIM2 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#endif + +/** + * @brief TIM3 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#endif + +/** + * @brief TIM4 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#endif + +/** + * @brief TIM5 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) +#endif + +/** + * @brief TIM6 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#endif + +/** + * @brief TIM7 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#endif + +/** + * @brief RTC Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#endif + +/** + * @brief WWDG Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#endif + +/** + * @brief IWDG Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#endif + +/** + * @brief I2C1 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) +#endif + +/** + * @brief I2C2 Peripherals Debug mode + */ +#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) +#endif + +/** + * @brief TIM9 Peripherals Debug mode + */ +#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) +#endif + +/** + * @brief TIM10 Peripherals Debug mode + */ +#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#endif + +/** + * @brief TIM11 Peripherals Debug mode + */ +#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG + * @{ + */ + +/** @defgroup SYSCFG_VrefInt VREFINT configuration + * @{ + */ + +/** + * @brief Enables or disables the output of internal reference voltage + * (VrefInt) on I/O pin. + * @note The VrefInt output can be routed to any I/O in group 3: + * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). + * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). + * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), + * CH1b (PF11) or CH2b (PF12). + * Note: Comparator peripheral clock must be preliminarily enabled, + * either in COMP user function "HAL_COMP_MspInit()" (should be + * done if comparators are used) or by direct clock enable: + * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()". + * Note: In addition with this macro, VrefInt output buffer must be + * connected to the selected I/O pin. Refer to macro + * "__HAL_RI_IOSWITCH_CLOSE()". + * @note VrefInt output enable: Internal reference voltage connected to I/O group 3 + * VrefInt output disable: Internal reference voltage disconnected from I/O group 3 + * @retval None + */ +#define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) +#define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) + +/** + * @} + */ + +/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration + * @{ + */ + +/** + * @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) + +#if defined(FSMC_R_BASE) +/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) + +#endif /* FSMC_R_BASE */ + +/** + * @brief Returns the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg SYSCFG_BOOT_MAINFLASH + * @arg SYSCFG_BOOT_SYSTEMFLASH + * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD) + * @arg SYSCFG_BOOT_SRAM + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE) + +/** + * @} + */ + +/** @defgroup SYSCFG_USBConfig USB DP line Configuration + * @{ + */ + +/** + * @brief Control the internal pull-up on USB DP line. + */ +#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) + +#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RI_Macris RI: Routing Interface + * @{ + */ + +/** @defgroup RI_InputCaputureConfig Input Capture configuration + * @{ + */ + +/** + * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin. + * @param __TIMSELECT__ Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__ selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * e.g. + * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1) + * allows routing of Input capture IC1 of TIM2 to PA4. + * For details about correspondence between RI_INPUTCAPTUREROUTING_x + * and I/O pins refer to the parameters' description in the header file + * or refer to the product reference manual. + * @note Input capture selection bits are not reset by this function. + * To reset input capture selection bits, use SYSCFG_RIDeInit() function. + * @note The I/O should be configured in alternate function mode (AF14) using + * GPIO_PinAFConfig() function. + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \ + MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \ + }while(0) + +/** + * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin. + * @param __TIMSELECT__ Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__ selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \ + MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \ + }while(0) + +/** + * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin. + * @param __TIMSELECT__ Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__ selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \ + MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \ + }while(0) + +/** + * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin. + * @param __TIMSELECT__ Timer select. + * This parameter can be one of the following values: + * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. + * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. + * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. + * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. + * @param __INPUT__ selects which pin to be routed to Input Capture. + * This parameter must be a value of @ref RI_InputCaptureRouting + * @retval None. + */ +#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \ + do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ + assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ + MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ + SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \ + MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \ + }while(0) + +/** + * @} + */ + +/** @defgroup RI_SwitchControlConfig Switch Control configuration + * @{ + */ + +/** + * @brief Enable or disable the switch control mode. + * @note ENABLE: ADC analog switches closed if the corresponding + * I/O switch is also closed. + * When using COMP1, switch control mode must be enabled. + * @note DISABLE: ADC analog switches open or controlled by the ADC interface. + * When using the ADC for acquisition, switch control mode + * must be disabled. + * @note COMP1 comparator and ADC cannot be used at the same time since + * they share the ADC switch matrix. + * @retval None + */ +#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM) + +#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM) + +/* + * @brief Close or Open the routing interface Input Output switches. + * @param __IOSWITCH__ selects the I/O analog switch number. + * This parameter must be a value of @ref RI_IOSwitch + * @retval None + */ +#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ + if ((__IOSWITCH__) >> 31 != 0 ) \ + { \ + SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ + } \ + else \ + { \ + SET_BIT(RI->ASCR2, (__IOSWITCH__)); \ + } \ + }while(0) + +#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ + if ((__IOSWITCH__) >> 31 != 0 ) \ + { \ + CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ + } \ + else \ + { \ + CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \ + } \ + }while(0) + +#if defined (COMP_CSR_SW1) +/** + * @brief Close or open the internal switch COMP1_SW1. + * This switch connects I/O pin PC3 (can be used as ADC channel 13) + * and OPAMP3 output to ADC switch matrix (ADC channel VCOMP, channel + * 26) and COMP1 non-inverting input. + * Pin PC3 connection depends on another switch setting, refer to + * macro "__HAL_ADC_CHANNEL_SPEED_FAST()". + * @retval None. + */ +#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1) + +#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1) +#endif /* COMP_CSR_SW1 */ + +/** + * @} + */ + +/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation + * @{ + */ + +/** + * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports A + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR1, (__IOPIN__)); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports B + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports C + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR2, (__IOPIN__)); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports D + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ + } while(0) + +#if defined (GPIOE_BASE) + +/** + * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports E + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR3, (__IOPIN__)); \ + } while(0) + +#endif /* GPIOE_BASE */ + +#if defined(GPIOF_BASE) || defined(GPIOG_BASE) + +/** + * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports F + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ + } while(0) + +/** + * @brief Enable or disable Hysteresis of the input schmitt trigger of Ports G + * When the I/Os are programmed in input mode by standard I/O port + * registers, the Schmitt trigger and the hysteresis are enabled by default. + * When hysteresis is disabled, it is possible to read the + * corresponding port with a trigger level of VDDIO/2. + * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. + * This parameter must be a value of @ref RI_Pin + * @retval None + */ +#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \ + } while(0) + +#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ + SET_BIT(RI->HYSCR4, (__IOPIN__)); \ + } while(0) + +#endif /* GPIOF_BASE || GPIOG_BASE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern uint32_t uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); +uint32_t HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h new file mode 100644 index 0000000..0d48123 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_CORTEX_H +#define __STM32L1xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ + +#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) +#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) +#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported Macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source + * @{ + */ +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Functions CORTEX Private Functions + * @brief CORTEX private functions + * @{ + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_CORTEX_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h new file mode 100644 index 0000000..1c5828a --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h @@ -0,0 +1,199 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_DEF +#define __STM32L1xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ + (__DMA_HANDLE_).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1) + + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" + +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32L1xx_HAL_DEF */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h new file mode 100644 index 0000000..2bdb1fc --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h @@ -0,0 +1,651 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L1xx_HAL_DMA_H +#define STM32L1xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ + +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE +#define DMA_IT_HT DMA_CCR_HTIE +#define DMA_IT_TE DMA_CCR_TEIE +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ +#define DMA_FLAG_GL1 DMA_ISR_GIF1 +#define DMA_FLAG_TC1 DMA_ISR_TCIF1 +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 +#define DMA_FLAG_GL2 DMA_ISR_GIF2 +#define DMA_FLAG_TC2 DMA_ISR_TCIF2 +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 +#define DMA_FLAG_GL3 DMA_ISR_GIF3 +#define DMA_FLAG_TC3 DMA_ISR_TCIF3 +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 +#define DMA_FLAG_GL4 DMA_ISR_GIF4 +#define DMA_FLAG_TC4 DMA_ISR_TCIF4 +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 +#define DMA_FLAG_GL5 DMA_ISR_GIF5 +#define DMA_FLAG_TC5 DMA_ISR_TCIF5 +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 +#define DMA_FLAG_GL6 DMA_ISR_GIF6 +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 +#define DMA_FLAG_GL7 DMA_ISR_GIF7 +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + + +/* Interrupt & Flag management */ +#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ + defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ + defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) + +/** + * @brief Return the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ + +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ + DMA_ISR_GIF7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be from 1 to 7 to select the DMA Channel x flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be from 1 to 7 to select the DMA Channel x flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ +(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) + +#else +/** + * @brief Return the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ + +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ + DMA_ISR_GIF7) + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag + * @arg DMA_FLAG_HTIFx: Half transfer complete flag + * @arg DMA_FLAG_TEIFx: Transfer error flag + * @arg DMA_ISR_GIFx: Global interrupt flag + * Where x can be from 1 to 7 to select the DMA Channel x flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag + * Where x can be from 1 to 7 to select the DMA Channel x flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Return the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__ DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L1xx_HAL_DMA_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h new file mode 100644 index 0000000..69331f9 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h @@ -0,0 +1,315 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L1xx_HAL_EXTI_H +#define STM32L1xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Device FS Wakeup from suspend event */ +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the channel acquisition interrupt */ +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ + +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +#define EXTI_GPIOH 0x00000007u + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_NB 24UL +#else +#define EXTI_LINE_NB 23UL +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if !defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#endif /* GPIOE */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32l1xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h new file mode 100644 index 0000000..511d469 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of Flash HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_FLASH_H +#define __STM32L1xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_PROGRAM = 2U, +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ + + __IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code + This parameter can be a value of @ref FLASH_Error_Codes */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Codes FLASH Error Codes + * @{ + */ + +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ +#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */ +#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */ +#define HAL_FLASH_ERROR_OPTVUSR 0x20U /*!< Option UserValidity Error. */ +#define HAL_FLASH_ERROR_OPERATION 0x40U /*!< Not used */ + +/** + * @} + */ + +/** @defgroup FLASH_Page_Size FLASH size information + * @{ + */ + +#if defined (FLASH_CUT1) || defined (FLASH_CUT2) +#define FLASH_SIZE_RAW (uint32_t)(*((uint32_t *)FLASHSIZE_BASE)&0xFFU) +#else /*FLASH_CUT3 || FLASH_CUT4 || FLASH_CUT5 || FLASH_CUT6*/ +#define FLASH_SIZE_RAW (uint32_t)(*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) +#endif +#define FLASH_SIZE (((FLASH_SIZE_RAW) == 0 ? 384 : ((FLASH_SIZE_RAW) == 1 ? 256 : (FLASH_SIZE_RAW))) * 1024) +#define FLASH_PAGE_SIZE (256U) /*!< FLASH Page Size in bytes */ + +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!PECR), (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_ERR Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag + * @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag +@if STM32L100xB +@elif STM32L100xBA + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) +@elif STM32L151xB +@elif STM32L151xBA + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) +@elif STM32L152xB +@elif STM32L152xBA + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) +@elif STM32L100xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@elif STM32L151xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@elif STM32L152xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@elif STM32L162xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@else + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@endif + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag +@if STM32L100xB +@elif STM32L100xBA + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) +@elif STM32L151xB +@elif STM32L151xBA + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) +@elif STM32L152xB +@elif STM32L152xBA + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) +@elif STM32L100xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@elif STM32L151xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@elif STM32L152xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@elif STM32L162xC + * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@else + * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error +@endif + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32l1xx_hal_flash_ex.h" +#include "stm32l1xx_hal_flash_ramfunc.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data); + +/* FLASH IRQ handler function */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_FLASH_GetError(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private function -------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_FLASH_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h new file mode 100644 index 0000000..24c4e3b --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h @@ -0,0 +1,965 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of Flash HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_FLASH_EX_H +#define __STM32L1xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR) + +#elif defined(FLASH_SR_RDERR) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_RDERR) + +#elif defined(FLASH_SR_OPTVERRUSR) + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERRUSR) + +#else + +#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR) + +#endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */ + +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ + || defined(STM32L151xBA) || defined(STM32L152xBA) + +/******* Devices with FLASH 128K *******/ +#define FLASH_NBPAGES_MAX 512U /* 512 pages from page 0 to page 511U */ + +#elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA) + +/******* Devices with FLASH 256K *******/ +#define FLASH_NBPAGES_MAX 1024U /* 1024 pages from page 0 to page 1023U */ + +#elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) + +/******* Devices with FLASH 384K *******/ +#define FLASH_NBPAGES_MAX 1536U /* 1536 pages from page 0 to page 1535U */ + +#elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + +/******* Devices with FLASH 512K *******/ +#define FLASH_NBPAGES_MAX 2048U /* 2048 pages from page 0 to page 2047U */ + +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ + +#define WRP_MASK_LOW (0x0000FFFFU) +#define WRP_MASK_HIGH (0xFFFF0000U) + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Macros + * @{ + */ + +#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES)) + +#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR))) + +#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ + ((__VALUE__) == OB_WRPSTATE_ENABLE)) + +#define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U)) + +#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_2)) + +#define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \ + ((__LEVEL__) == OB_BOR_LEVEL1) || \ + ((__LEVEL__) == OB_BOR_LEVEL2) || \ + ((__LEVEL__) == OB_BOR_LEVEL3) || \ + ((__LEVEL__) == OB_BOR_LEVEL4) || \ + ((__LEVEL__) == OB_BOR_LEVEL5)) + +#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) + +#if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2) + +#define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)) + +#elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2) + +#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP) + +#elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2) + +#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG) + +#endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */ + +#if defined(FLASH_OBR_SPRMOD) + +#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \ + ((__VALUE__) == OB_PCROP_STATE_ENABLE)) + +#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U)) +#endif /* FLASH_OBR_SPRMOD */ + +#if defined(FLASH_OBR_nRST_BFB2) + +#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) + +#endif /* FLASH_OBR_nRST_BFB2 */ + +#define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \ + ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \ + ((__VALUE__) == FLASH_TYPEERASEDATA_WORD)) +#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD)) + + +/** @defgroup FLASHEx_Address FLASHEx Address + * @{ + */ + +#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END)) + +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ + || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \ + || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \ + || defined(STM32L162xCA) + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) + +#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) +#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) +#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) + +#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */ + +#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) + +/** + * @} + */ + +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< TypeErase: Page Erase only. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased + This parameter must be a value belonging to FLASH Program address (depending on the devices) */ + + uint32_t NbPages; /*!< NbPages: Number of pages to be erased. + This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes PROGRAM structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) + uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95 + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) + uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or + Sectors 96 to 111 for STM32L1xxxDX devices. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ + + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, + @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ +} FLASH_OBProgramInitTypeDef; + +#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) +/** + * @brief FLASH Advanced Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . + This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ + +#if defined(FLASH_OBR_SPRMOD) + uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ + + uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */ + +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) + uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ +#endif /* STM32L151xC || STM32L152xC || STM32L162xC */ +#endif /* FLASH_OBR_SPRMOD */ + +#if defined(FLASH_OBR_nRST_BFB2) + uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ +#endif /* FLASH_OBR_nRST_BFB2*/ +} FLASH_AdvOBProgramInitTypeDef; + +/** + * @} + */ +#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase + * @{ + */ +#define FLASH_TYPEERASE_PAGES (0x00U) /*!= 256KB*/ +#define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */ +#define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */ +#define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */ +#define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */ +#define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */ +#define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */ +#define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */ +#define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */ +#define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */ +#define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */ +#define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */ +#define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */ +#define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */ +#define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */ +#define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */ +#define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */ +#define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */ +#define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */ +#define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */ +#define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */ +#define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */ +#define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */ +#define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */ +#define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */ +#define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */ +#define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */ +#define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */ +#define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */ +#define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */ +#define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */ +#define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */ +#define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */ + +#define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */ + +/** + * @} + */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ + +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) + +/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4 + * @{ + */ + +/* Pages for Cat5 devices*/ +#define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/ +#define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/ +#define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/ +#define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/ +#define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/ +#define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/ +#define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/ +#define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/ +#define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/ +#define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/ +#define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/ +#define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/ +#define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/ +#define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/ +#define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/ +#define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/ + +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + +#define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/ +#define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/ +#define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/ +#define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/ +#define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/ +#define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/ +#define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/ +#define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/ +#define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/ +#define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/ +#define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/ +#define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/ +#define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/ +#define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/ +#define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/ +#define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/ + +#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ + +#define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */ + +/** + * @} + */ + +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) +#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2 + it is no more possible to go back to level 1 or 0 */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level + * @{ + */ + +#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD + power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ +#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ +#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ +#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ +#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP + * @{ + */ + +#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY + * @{ + */ + +#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */ + +/** + * @} + */ + +#if defined(FLASH_OBR_SPRMOD) + +/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type + * @{ + */ + +#define OPTIONBYTE_PCROP (0x01U) /*!> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ + +/** + * @} + */ +#endif /* FLASH_OBR_nRST_BFB2 */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * This parameter can be one of the following values: + * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \ + if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \ + MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \ + } while(0U) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * This parameter can be one of the following values: + * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle + * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the FLASH 64-bit access. + * @note Read access 64 bit is used. + * @note This bit cannot be written at the same time as the LATENCY and + * PRFTEN bits. + * @retval none + */ +#define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64)) + + /** + * @brief Disable the FLASH 64-bit access. + * @note Read access 32 bit is used + * @note To reset this bit, the LATENCY should be zero wait state and the + * prefetch off. + * @retval none + */ +#define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64)) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \ + SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \ + } while(0U) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH power down during Sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @brief Disable the FLASH power down during Sleep mode + * @retval none + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @brief Enable the Flash Run power down mode. + * @note Writing this bit to 0 this bit, automatically the keys are + * loss and a new unlock sequence is necessary to re-write it to 1. + */ +#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ + FLASH->PDKEYR = FLASH_PDKEY2; \ + SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ + } while (0U) + +/** + * @brief Disable the Flash Run power down mode. + * @note Writing this bit to 0 this bit, automatically the keys are + * loss and a new unlock sequence is necessary to re-write it to 1. + */ +#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ + FLASH->PDKEYR = FLASH_PDKEY2; \ + CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ + } while (0U) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) + +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); + +#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ + +#if defined(FLASH_OBR_SPRMOD) + +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); + +#endif /* FLASH_OBR_SPRMOD */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ + +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); + +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address); +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); +void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); +void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_FLASH_EX_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h new file mode 100644 index 0000000..86e31fc --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h @@ -0,0 +1,116 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash_ramfunc.h + * @author MCD Application Team + * @brief Header file of FLASH RAMFUNC driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_FLASH_RAMFUNC_H +#define __STM32L1xx_FLASH_RAMFUNC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions + * @{ + */ + +/* + * @brief FLASH memory functions that should be executed from internal SRAM. + * These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c" + * file. + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 + * @{ + */ + +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void); + +/** + * @} + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2 + * @{ + */ + +#if defined(FLASH_PECR_PARALLBANK) + +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); + +#endif /* FLASH_PECR_PARALLBANK */ + +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); + +/** + * @} + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3 + * @{ + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t *Error); +/** + * @} + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group4 + * @{ + */ + +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_FLASH_RAMFUNC_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h new file mode 100644 index 0000000..990e85e --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h @@ -0,0 +1,333 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_GPIO_H +#define __STM32L1xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + + +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< max: 400 KHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */ + +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ + +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32l1xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_GPIO_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h new file mode 100644 index 0000000..472cf57 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h @@ -0,0 +1,203 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_GPIO_EX_H +#define __STM32L1xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +/* AF 0 selection */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /*!< TAMPER Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_OUT Alternate Function mapping */ + +/* AF 1 selection */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ + +/* AF 2 selection */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */ + +/* AF 3 selection */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */ + + +/* AF 4 selection */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ + +/* AF 5 selection */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */ + +/* AF 6 selection */ +#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\ + defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) + +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */ + +#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE || STM32L162xDX */ + + +/* AF 7 selection */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ + +/* AF 8 selection */ +#if defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\ + defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) + +#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */ + +#endif /* STM32L151xD || STM32L151xE || STM32L151xDX || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE || STM32L162xDX */ + + +/* AF 9 selection */ + +/* AF 10 selection */ + +/* AF 11 selection */ +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ + defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ + defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) + +#define GPIO_AF11_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */ + +#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +/* AF 12 selection */ +#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) + +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */ + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ +/* AF 13 selection */ + +/* AF 14 selection */ +#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ +#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ + +/* AF 15 selection */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros + * @{ + */ + + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOH))? 5U :\ + ((__GPIOx__) == (GPIOF))? 6U : 7U) +#endif + +#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif + +#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 5U) +#endif + + + +/** + * @} + */ + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_GPIO_EX_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h new file mode 100644 index 0000000..7728d4b --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_PWR_H +#define __STM32L1xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Internal constants --------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants + * @{ + */ +#define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +/** + * @} + */ + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00 +#define PWR_CSR_OFFSET 0x04 +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of LPSDSR bit */ +#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) +#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) + +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) +#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) + +/* Alias word address of LPRUN bit */ +#define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) +#define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) +#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) + +/* Alias word address of FWU bit */ +#define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) +#define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) + +/* Alias word address of ULP bit */ +#define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) +#define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ + +/* --- CSR Register ---*/ +/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ +#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) +/** + * @} + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage + (Compare internally to VREFINT) */ + +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ + + /** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR + +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ + +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS + + +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#define PWR_FLAG_VOS PWR_CSR_VOSF +#define PWR_FLAG_REGLP PWR_CSR_REGLPF + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, + * System frequency up to 32 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, + * System frequency up to 16 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, + * System frequency up to 4.2 MHz + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm B), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. + * This bit indicates the state of the internal voltage reference, VREFINT. + * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for + * the internal regulator to be ready after the voltage range is changed. + * The VOSF bit indicates that the regulator has reached the voltage level + * defined with bits VOS of PWR_CR register. + * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run + * mode, this bit stays at 1 until the regulator is ready in main mode. + * A polling on this bit is recommended to wait for the regulator main mode. + * This bit is reset by hardware when the regulator is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) + +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + + + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) + +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) + + +/** + * @} + */ + + + +/* Include PWR HAL Extension module */ +#include "stm32l1xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + + + +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_PWR_H */ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h new file mode 100644 index 0000000..9d98744 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_PWR_EX_H +#define __STM32L1xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + + +/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins + * @{ + */ + +#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) + +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 +#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) +#else +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ + +/* Peripheral Control methods ************************************************/ +uint32_t HAL_PWREx_GetVoltageRange(void); +void HAL_PWREx_EnableFastWakeUp(void); +void HAL_PWREx_DisableFastWakeUp(void); +void HAL_PWREx_EnableUltraLowPower(void); +void HAL_PWREx_DisableUltraLowPower(void); +void HAL_PWREx_EnableLowPowerRunMode(void); +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32L1xx_HAL_PWR_EX_H */ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h new file mode 100644 index 0000000..eb13d65 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h @@ -0,0 +1,1895 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_RCC_H +#define __STM32L1xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x08 +#define RCC_CIR_OFFSET 0x0C +#define RCC_CSR_OFFSET 0x34 +/** + * @} + */ + +/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) +/* Alias word address of MSION bit */ +#define RCC_MSION_BIT_NUMBER RCC_CR_MSION_Pos +#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U))) +/* Alias word address of HSEON bit */ +#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) + +/* Alias word address of RMVF bit */ +#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEON_BIT_NUMBER RCC_CSR_LSEON_Pos +#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEBYP_BIT_NUMBER RCC_CSR_LSEBYP_Pos +#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) + +/* Alias word address of RTCEN bit */ +#define RCC_RTCEN_BIT_NUMBER RCC_CSR_RTCEN_Pos +#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) + +/* Alias word address of RTCRST bit */ +#define RCC_RTCRST_BIT_NUMBER RCC_CSR_RTCRST_Pos +#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1U) +#define CSR_REG_INDEX ((uint8_t)2U) + +#define RCC_FLAG_MASK ((uint8_t)0x1FU) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU) +#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ + ((__RANGE__) == RCC_MSIRANGE_1) || \ + ((__RANGE__) == RCC_MSIRANGE_2) || \ + ((__RANGE__) == RCC_MSIRANGE_3) || \ + ((__RANGE__) == RCC_MSIRANGE_4) || \ + ((__RANGE__) == RCC_MSIRANGE_5) || \ + ((__RANGE__) == RCC_MSIRANGE_6)) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ + ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) + +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ + ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ + ((__MUL__) == RCC_PLL_MUL48)) +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \ + || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + + uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Division_Factor*/ +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t MSIState; /*!< The new state of the MSI. + This parameter can be a value of @ref RCC_MSI_Config */ + + uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ + + uint32_t MSIClockRange; /*!< The MSI frequency range. + This parameter can be a value of @ref RCC_MSI_Clock_Range */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE (0x00000000U) +#define RCC_OSCILLATORTYPE_HSE (0x00000001U) +#define RCC_OSCILLATORTYPE_HSI (0x00000002U) +#define RCC_OSCILLATORTYPE_LSE (0x00000004U) +#define RCC_OSCILLATORTYPE_LSI (0x00000008U) +#define RCC_OSCILLATORTYPE_MSI (0x00000010U) +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ +#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ +#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_MSI_Clock_Range MSI Clock Range + * @{ + */ + +#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ +#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ +#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ +#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ +#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ +#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ +#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ + +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +/** @defgroup RCC_MSI_Config MSI Config + * @{ + */ +#define RCC_MSI_OFF (0x00000000U) +#define RCC_MSI_ON (0x00000001U) + +#define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ +#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ +#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler + * @{ + */ +#define RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */ +#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ +#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ +#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Division_Factor PLL Division Factor + * @{ + */ + +#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 +#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 +#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 + +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor + * @{ + */ + +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 +#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 +#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 +#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 + +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 (0x00000000U) +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1) +#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4) +#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8) +#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16) + +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI +#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE +#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL + +/** + * @} + */ +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /*!< MSI Ready Interrupt flag */ +#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ +#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSECSSD_Pos)) /*!< CSS on LSE failure Detection */ +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Options bytes loading reset flag */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ +#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) + +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_COMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ + UNUSED(tmpreg); \ + } while(0U) + + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */\ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) + +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) + +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) +#define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) + +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST)) +#define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST)) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) + +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN)) + +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN)) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN)) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN)) + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != 0U) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != 0U) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == 0U) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == 0U) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != 0U) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0U) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0U) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U) +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != 0U) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != 0U) +#define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != 0U) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == 0U) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0U) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0U) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U) +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == 0U) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == 0U) +#define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0U) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0U) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0U) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0U) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0U) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0U) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0U) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0U) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != 0U) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != 0U) +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != 0U) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != 0U) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == 0U) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == 0U) +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == 0U) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != 0U) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != 0U) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != 0U) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != 0U) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != 0U) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != 0U) +#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != 0U) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == 0U) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == 0U) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == 0U) +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == 0U) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == 0U) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == 0U) +#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != 0U) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != 0U) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != 0U) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != 0U) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != 0U) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == 0U) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == 0U) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == 0U) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == 0U) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == 0U) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos)) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_MSI_Configuration MSI Configuration + * @{ + */ + +/** @brief Macro to enable Internal Multi Speed oscillator (MSI). + * @note After enabling the MSI, the application software should wait on MSIRDY + * flag to be set indicating that MSI clock is stable and can be used as + * system clock source. + */ +#define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Multi Speed oscillator (MSI). + * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note MSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the MSI. + * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator + * clock cycles. + */ +#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE) + +/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal MSI RC. + * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_MSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0xFF. + */ +#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos)) + +/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. + * @note After restart from Reset or wakeup from STANDBY, the MSI clock is + * around 2.097 MHz. The MSI clock does not change after wake-up from + * STOP mode. + * @note The MSI clock range can be modified on the fly. + * @param _MSIRANGEVALUE_ specifies the MSI Clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz + */ +#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \ + RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) + +/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode + * @retval MSI clock range. + * This parameter must be one of the following values: + * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz + * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz + * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz + * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz + * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz + * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) + * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz + */ +#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 + * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 + * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 + * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 + * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 + * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 + * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24 + * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32 + * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48 + * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in + * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is + * in Range 3. + * + * @param __PLLDIV__ specifies the division factor for PLL VCO input clock + * This parameter can be one of the following values: + * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2 + * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3 + * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4 + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** + * @} + */ + + /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \ + if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \ + { \ + MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \ + } \ + } while (0U) + +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \ + __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ + RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ + } while (0U) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) + +/** + * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK). + * + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock + * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock + * + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE))) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + * @arg @ref RCC_IT_CSS Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_MSIRDY MSI ready interrupt + * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*) + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + * @note (*) This bit is available in high and medium+ density devices only. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32l1xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_RCC_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h new file mode 100644 index 0000000..7339d6d --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h @@ -0,0 +1,1027 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_HAL_RCC_EX_H +#define __STM32L1xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/** @addtogroup RCCEx_Private_Constants + * @{ + */ + +#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\ + || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\ + || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +/* Alias word address of LSECSSON bit */ +#define LSECSSON_BITNUMBER RCC_CSR_LSECSSON_Pos +#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U))) + +#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/ + +/** + * @} + */ + +/** @addtogroup RCCEx_Private_Macros + * @{ + */ +#if defined(LCD) + +#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) + +#else /* Not LCD LINE */ + +#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) + +#endif /* LCD */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< specifies the RTC clock source. + This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ + +#if defined(LCD) + + uint32_t LCDClockSelection; /*!< specifies the LCD clock source. + This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ + +#endif /* LCD */ +} RCC_PeriphCLKInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_RTC (0x00000001U) + +#if defined(LCD) + +#define RCC_PERIPHCLK_LCD (0x00000002U) + +#endif /* LCD */ + +/** + * @} + */ + +#if defined(RCC_LSECSS_SUPPORT) +/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line + * @{ + */ +#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ +/** + * @} + */ +#endif /* RCC_LSECSS_SUPPORT */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_LCD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +/** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\ + || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */ + +/** @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases AHB peripheral reset. + * @{ + */ +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) + +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) +#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +/** @brief Forces or releases APB1 peripheral reset. + */ +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) + +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +/** @brief Forces or releases APB2 peripheral reset. + */ +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable + * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) + +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) +#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +/** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) + +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ +#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +/** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U) +#define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED() +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED() + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U) +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ + || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U) + +#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U) + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U) + +#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U) +#define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ + || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ + || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U) +#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U) + +#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U) + +#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ + || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ + || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ + || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ + || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U) + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) + +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + +#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ + || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ + || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ + || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) + +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() + +#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ + +#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) + +#define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U) +#define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U) + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ + +/** + * @} + */ + + +#if defined(RCC_LSECSS_SUPPORT) + +/** + * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable interrupt on RCC LSE CSS EXTI Line 19. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable event on RCC LSE CSS EXTI Line 19. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable event on RCC LSE CSS EXTI Line 19. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) + +/** + * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS)) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) + +#endif /* RCC_LSECSS_SUPPORT */ + +#if defined(LCD) + +/** @defgroup RCCEx_LCD_Configuration LCD Configuration + * @brief Macros to configure clock source of LCD peripherals. + * @{ + */ + +/** @brief Macro to configures LCD clock (LCDCLK). + * @note LCD and RTC use the same configuration + * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the + * LCD clock source. + * + * @param __LCD_CLKSOURCE__ specifies the LCD clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock + */ +#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) + +/** @brief Macro to get the LCD clock source. + */ +#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() + +/** @brief Macro to get the LCD clock pre-scaler. + */ +#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER() + +/** + * @} + */ + +#endif /* LCD */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +#if defined(RCC_LSECSS_SUPPORT) + +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); + +#endif /* RCC_LSECSS_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_HAL_RCC_EX_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h new file mode 100644 index 0000000..7b01759 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_spi.h @@ -0,0 +1,749 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L1xx_HAL_SPI_H +#define STM32L1xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal_def.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Code SPI Error Code + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000U) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000U) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_8BIT (0x00000000U) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000U) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000U) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI Mode + * @brief SPI TI Mode not supported for Category 1 and 2 + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000U) +#if defined(SPI_CR2_FRF) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF +#endif /* SPI_CR2_FRF */ +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#if defined(SPI_CR2_FRF) +#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE) +#else +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY\ + | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR) +#endif /* SPI_CR2_FRF */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + } while(0U) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR register. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 register. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Select management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +#if defined(SPI_I2SCFGR_I2SMOD) +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) +#else +/** @defgroup SPI_TI_mode SPI TI mode disable + * @brief SPI TI Mode not supported for Category 1 and 2 + * @{ + */ +#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) + +#endif /* SPI_I2SCFGR_I2SMOD */ +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) + +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L1xx_HAL_SPI_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h new file mode 100644 index 0000000..0d05861 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_bus.h @@ -0,0 +1,1100 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_BUS_H +#define __STM32L1xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN +#endif/*GPIOE*/ +#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN +#if defined(GPIOF) +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN +#endif/*GPIOF*/ +#if defined(GPIOG) +#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN +#endif/*GPIOG*/ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#if defined(DMA2) +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN +#endif/*DMA2*/ +#if defined(AES) +#define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN +#endif/*AES*/ +#if defined(FSMC_Bank1) +#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN +#endif/*FSMC_Bank1*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#if defined(TIM5) +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#endif /*TIM5*/ +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#if defined(LCD) +#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN +#endif /*LCD*/ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#endif /*SPI3*/ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#endif /*UART4*/ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#endif /*UART5*/ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN +#if defined(OPAMP) +/* Note: Peripherals COMP and OPAMP share the same clock domain */ +#define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP +#endif +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(SDIO) +#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN +#endif /*SDIO*/ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBLPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR COMPEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_COMP + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_COMP + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR COMPEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_COMP + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_COMP + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_COMP + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_COMP + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_USB + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_COMP + * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_BUS_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h new file mode 100644 index 0000000..3fec1a3 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_cortex.h @@ -0,0 +1,637 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_CORTEX_H +#define __STM32L1xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M3 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC23 for Cortex-M3 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_CORTEX_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h new file mode 100644 index 0000000..ee30c2b --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_dma.h @@ -0,0 +1,1996 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_DMA_H +#define __STM32L1xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +} + +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +} + +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +} + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +} + +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +} + +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +} + +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +} + +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +} + +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +} + +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_DMA_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h new file mode 100644 index 0000000..77d8e63 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_exti.h @@ -0,0 +1,1015 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L1xx_LL_EXTI_H +#define STM32L1xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L1xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h new file mode 100644 index 0000000..2de80e7 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_gpio.h @@ -0,0 +1,987 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_GPIO_H +#define __STM32L1xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin\n + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ +#if defined(GPIO_BRR_BR_0) + WRITE_REG(GPIOx->BRR, PinMask); +#else + WRITE_REG(GPIOx->BSRR, (PinMask << 16)); +#endif /* GPIO_BRR_BR_0 */ +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_GPIO_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h new file mode 100644 index 0000000..f7b5742 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_pwr.h @@ -0,0 +1,718 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_PWR_H +#define __STM32L1xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#if defined(PWR_PVD_SUPPORT) +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) +#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ +#endif /* PWR_CSR_VREFINTRDYF */ +#define LL_PWR_CSR_VOS PWR_CSR_VOSF /*!< Voltage scaling select flag */ +#define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */ +#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes + * @{ + */ +#define LL_PWR_REGU_LPMODES_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep/sleep/low-power run mode */ +#define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage Regulator in low-power mode during deepsleep/sleep/low-power run mode */ +/** + * @} + */ +#if defined(PWR_CR_LPDS) +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ +#endif /* PWR_CR_LPDS */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 1.9 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.1 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.9 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 3.1 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltage (Compare internally to VREFINT) */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Switch the Regulator from main mode to low-power mode + * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode + * @note Remind to set the Regulator to low power before enabling + * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER). + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPRUN); +} + +/** + * @brief Switch the Regulator from low-power mode to main mode + * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); +} + +/** + * @brief Check if the Regulator is in low-power mode + * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) +{ + return ((READ_BIT(PWR->CR, PWR_CR_LPRUN) == PWR_CR_LPRUN) ? 1UL : 0UL); +} + +/** + * @brief Set voltage Regulator to low-power and switch from + * run main mode to run low-power mode. + * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n + * CR LPRUN LL_PWR_EnterLowPowerRunMode + * @note This "high level" function is introduced to provide functional + * compatibility with other families. Notice that the two registers + * have to be written sequentially, so this function is not atomic. + * To assure atomicity you can call separately the following functions: + * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER); + * - @ref LL_PWR_EnableLowPowerRunMode(); + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */ + SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */ +} + +/** + * @brief Set voltage Regulator to main and switch from + * run main mode to low-power mode. + * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n + * CR LPRUN LL_PWR_ExitLowPowerRunMode + * @note This "high level" function is introduced to provide functional + * compatibility with other families. Notice that the two registers + * have to be written sequentially, so this function is not atomic. + * To assure atomicity you can call separately the following functions: + * - @ref LL_PWR_DisableLowPowerRunMode(); + * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN); + * @retval None + */ +__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */ + CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */ +} +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->CR, PWR_CR_DBP) == PWR_CR_DBP) ? 1UL : 0UL); +} + +/** + * @brief Set voltage Regulator mode during low power modes + * @rmtoll CR LPSDSR LL_PWR_SetRegulModeLP + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_LPMODES_MAIN + * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during low power modes + * @rmtoll CR LPSDSR LL_PWR_GetRegulModeLP + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_LPMODES_MAIN + * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR)); +} + +#if defined(PWR_CR_LPDS) +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} +#endif /* PWR_CR_LPDS */ + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP + * @arg @ref LL_PWR_MODE_STANDBY + * @note Set the Regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER) + * before setting MODE_STOP. If the Regulator remains in "main mode", + * it consumes more power without providing any additional feature. + * In MODE_STANDBY the Regulator is automatically off. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS)); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR, PWR_CR_PVDE) == PWR_CR_PVDE) ? 1UL : 0UL); +} +#endif /* PWR_PVD_SUPPORT */ + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->CSR, WakeUpPin) == WakeUpPin) ? 1UL : 0UL); +} + +/** + * @brief Enable ultra low-power mode by enabling VREFINT switch off in low-power modes + * @rmtoll CR ULP LL_PWR_EnableUltraLowPower + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUltraLowPower(void) +{ + SET_BIT(PWR->CR, PWR_CR_ULP); +} + +/** + * @brief Disable ultra low-power mode by disabling VREFINT switch off in low-power modes + * @rmtoll CR ULP LL_PWR_DisableUltraLowPower + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUltraLowPower(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_ULP); +} + +/** + * @brief Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled + * @rmtoll CR ULP LL_PWR_IsEnabledUltraLowPower + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void) +{ + return ((READ_BIT(PWR->CR, PWR_CR_ULP) == PWR_CR_ULP) ? 1UL : 0UL); +} + +/** + * @brief Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode + * @rmtoll CR FWU LL_PWR_EnableFastWakeUp + * @note Works in conjunction with ultra low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFastWakeUp(void) +{ + SET_BIT(PWR->CR, PWR_CR_FWU); +} + +/** + * @brief Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode + * @rmtoll CR FWU LL_PWR_DisableFastWakeUp + * @note Works in conjunction with ultra low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFastWakeUp(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FWU); +} + +/** + * @brief Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored + * @rmtoll CR FWU LL_PWR_IsEnabledFastWakeUp + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void) +{ + return ((READ_BIT(PWR->CR, PWR_CR_FWU) == PWR_CR_FWU) ? 1UL : 0UL); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return ((READ_BIT(PWR->CSR, PWR_CSR_WUF) == PWR_CSR_WUF) ? 1UL : 0UL); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CSR, PWR_CSR_SBF) == PWR_CSR_SBF) ? 1UL : 0UL); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->CSR, PWR_CSR_PVDO) == PWR_CSR_PVDO) ? 1UL : 0UL); +} +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_CSR_VREFINTRDYF) +/** + * @brief Get Internal Reference VrefInt Flag + * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) +{ + return ((READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == PWR_CSR_VREFINTRDYF) ? 1UL : 0UL); +} +#endif /* PWR_CSR_VREFINTRDYF */ +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level + * @rmtoll CSR VOSF LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return ((READ_BIT(PWR->CSR, PWR_CSR_VOSF) == PWR_CSR_VOSF) ? 1UL : 0UL); +} +/** + * @brief Indicate whether the Regulator is ready in main mode or is in low-power mode + * @rmtoll CSR REGLPF LL_PWR_IsActiveFlag_REGLPF + * @note Take care, return value "0" means the Regulator is ready. Return value "1" means the output voltage range is still changing. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) +{ + return ((READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == PWR_CSR_REGLPF) ? 1UL : 0UL); +} +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup PWR_LL_EF_Legacy_Functions PWR legacy functions name + * @{ + */ +/* Old functions name kept for legacy purpose, to be replaced by the */ +/* current functions name. */ +#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_PWR_H */ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h new file mode 100644 index 0000000..1fdbcd8 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_rcc.h @@ -0,0 +1,1796 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_RCC_H +#define __STM32L1xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 37000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC /*!< MSI Ready Interrupt Clear */ +#if defined(RCC_LSECSS_SUPPORT) +#define LL_RCC_CIR_LSECSSC RCC_CIR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#endif /* RCC_LSECSS_SUPPORT */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF /*!< MSI Ready Interrupt flag */ +#if defined(RCC_LSECSS_SUPPORT) +#define LL_RCC_CIR_LSECSSF RCC_CIR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#endif /* RCC_LSECSS_SUPPORT */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE /*!< MSI Ready Interrupt Enable */ +#if defined(RCC_LSECSS_SUPPORT) +#define LL_RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE /*!< LSE CSS Interrupt Enable */ +#endif /* RCC_LSECSS_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler + * @{ + */ +#define LL_RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */ +#define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ +#define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ +#define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges + * @{ + */ +#define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ +#define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/ +#define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ +#define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ +#define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ +#define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ +#define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MCO source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ +#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + + + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler + (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */ +#define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */ +#define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */ +#define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor + * @{ + */ +#define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */ +#define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */ +#define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, + * @ref LL_RCC_PLL_GetMultiplicator (), + * @ref LL_RCC_PLL_GetDivider ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_16 + * @arg @ref LL_RCC_PLL_MUL_24 + * @arg @ref LL_RCC_PLL_MUL_32 + * @arg @ref LL_RCC_PLL_MUL_48 + * @param __PLLDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_DIV_2 + * @arg @ref LL_RCC_PLL_DIV_3 + * @arg @ref LL_RCC_PLL_DIV_4 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1U)) + +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler + * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @brief Helper macro to calculate the MSI frequency (in Hz) + * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange + * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) + * @param __MSIRANGE__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @retval MSI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) ((32768U * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disable the Clock Security System. + * @note Cannot be disabled in HSE is ready (only by hardware) + * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); +} + +/** + * @brief Configure the RTC prescaler (divider) + * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Div This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div) +{ + MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); +} + +/** + * @brief Get the RTC divider (prescaler) + * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll CSR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll CSR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Enable Clock security system on LSE. + * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON); +} + +#endif /* RCC_LSECSS_SUPPORT */ +/** + * @brief Check if LSE oscillator Ready + * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL); +} + +#endif /* RCC_LSECSS_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSI MSI + * @{ + */ + +/** + * @brief Enable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Disable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Check if MSI oscillator Ready + * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range); +} + +/** + * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)); +} + +/** + * @brief Get MSI Calibration value + * @note When MSITRIM is written, MSICAL is updated with the sum of + * MSITRIM and the factory trim value + * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos); +} + +/** + * @brief Set MSI Calibration trimming + * @note user-programmable trimming value that is added to the MSICAL + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @brief Get MSI Calibration trimming + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_MSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + + + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The RTCRST bit can be used to reset them. + * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll CSR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll CSR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RTCRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_16 + * @arg @ref LL_RCC_PLL_MUL_24 + * @arg @ref LL_RCC_PLL_MUL_32 + * @arg @ref LL_RCC_PLL_MUL_48 + * @param PLLDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_DIV_2 + * @arg @ref LL_RCC_PLL_DIV_3 + * @arg @ref LL_RCC_PLL_DIV_4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv); +} + +/** + * @brief Configure PLL clock source + * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_16 + * @arg @ref LL_RCC_PLL_MUL_24 + * @arg @ref LL_RCC_PLL_MUL_32 + * @arg @ref LL_RCC_PLL_MUL_48 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_DIV_2 + * @arg @ref LL_RCC_PLL_DIV_3 + * @arg @ref LL_RCC_PLL_DIV_4 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear MSI ready interrupt flag + * @rmtoll CIR MSIRDYC LL_RCC_ClearFlag_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_MSIRDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CIR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSECSSC); +} + +#endif /* RCC_LSECSS_SUPPORT */ +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == RCC_CIR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == RCC_CIR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if MSI ready interrupt occurred or not + * @rmtoll CIR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYF) == RCC_CIR_MSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == RCC_CIR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == RCC_CIR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == RCC_CIR_PLLRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_CSSF) == RCC_CIR_CSSF) ? 1UL : 0UL); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSF) == RCC_CIR_LSECSSF) ? 1UL : 0UL); +} +#endif /* RCC_LSECSS_SUPPORT */ + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable MSI ready interrupt + * @rmtoll CIR MSIRDYIE LL_RCC_EnableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_MSIRDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Enable LSE clock security system interrupt + * @rmtoll CIR LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSECSSIE); +} +#endif /* RCC_LSECSS_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable MSI ready interrupt + * @rmtoll CIR MSIRDYIE LL_RCC_DisableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_MSIRDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Disable LSE clock security system interrupt + * @rmtoll CIR LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSECSSIE); +} +#endif /* RCC_LSECSS_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == RCC_CIR_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == RCC_CIR_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if MSI ready interrupt source is enabled or disabled. + * @rmtoll CIR MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_MSIRDYIE) == RCC_CIR_MSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == RCC_CIR_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == RCC_CIR_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == RCC_CIR_PLLRDYIE) ? 1UL : 0UL); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIR LSECSSIE LL_RCC_IsEnabledIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIR, RCC_CIR_LSECSSIE) == RCC_CIR_LSECSSIE) ? 1UL : 0UL); +} +#endif /* RCC_LSECSS_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_RCC_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h new file mode 100644 index 0000000..a61f40c --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_spi.h @@ -0,0 +1,2015 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L1xx_LL_SPI_H +#define STM32L1xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + * @brief SPI TI Mode not supported for Category 1 and 2 + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#if defined(SPI_CR2_FRF) +#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ +#endif /* SPI_CR2_FRF */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + +#if defined(SPI_CR2_FRF) +/** + * @brief Set serial protocol used. TI Mode not supported for Category 1 and 2. + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR2 FRF LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); +} + +/** + * @brief Get serial protocol used + * @rmtoll CR2 FRF LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); +} +#endif /* SPI_CR2_FRF */ + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR1 DFF LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR1 DFF LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_CRC_Management CRC Management + * @{ + */ + +/** + * @brief Enable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Disable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); +} + +/** + * @brief Set polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); +} + +/** + * @brief Get polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRCR)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRCR)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) +{ + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); +} + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); +} + +#if defined(SPI_CR2_FRF) +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); +} +#endif /* SPI_CR2_FRF */ + +/** + * @brief Clear CRC error flag + * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @brief Clear frame format error flag + * @note Clearing this flag is done by reading SPIx_SR register + * @rmtoll SR FRE LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->DR); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (*((__IO uint8_t *)&SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else + *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else + SPIx->DR = TxData; +#endif /* __GNUC__ */ +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +#if defined(SPI_I2S_SUPPORT) +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock output (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +#if defined(SPI_CR2_FRF) +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} +#endif /* SPI_CR2_FRF */ + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @brief Clear frame format error flag + * @rmtoll SR FRE LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L1xx_LL_SPI_H */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h new file mode 100644 index 0000000..806a57e --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_system.h @@ -0,0 +1,2007 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + (+) Access to Routing Interfaces registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_SYSTEM_H +#define __STM32L1xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @brief Power-down in Run mode Flash key + */ +#define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */ +#define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 + to unlock the RUN_PD bit in FLASH_ACR */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH (0x00000000U) /*MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); +} + +/** + * @brief Return the boot mode as configured by user. + * @rmtoll SYSCFG_MEMRMP BOOT_MODE LL_SYSCFG_GetBootMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BOOTMODE_FLASH + * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH + * @arg @ref LL_SYSCFG_BOOTMODE_FSMC (*) + * @arg @ref LL_SYSCFG_BOOTMODE_SRAM + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)); +} + +/** + * @brief Enable internal pull-up on USB DP line. + * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_EnableUSBPullUp + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableUSBPullUp(void) +{ + SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); +} + +/** + * @brief Disable internal pull-up on USB DP line. + * @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_DisableUSBPullUp + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableUSBPullUp(void) +{ + CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU); +} + +#if defined(LCD) +/** + * @brief Enable decoupling capacitance connection. + * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_EnableLCDCapacitanceConnection + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_LCDCAPA_PB2 + * @arg @ref LL_SYSCFG_LCDCAPA_PB12 + * @arg @ref LL_SYSCFG_LCDCAPA_PB0 + * @arg @ref LL_SYSCFG_LCDCAPA_PE11 + * @arg @ref LL_SYSCFG_LCDCAPA_PE12 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin) +{ + SET_BIT(SYSCFG->PMC, Pin); +} + +/** + * @brief DIsable decoupling capacitance connection. + * @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_DisableLCDCapacitanceConnection + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_LCDCAPA_PB2 + * @arg @ref LL_SYSCFG_LCDCAPA_PB12 + * @arg @ref LL_SYSCFG_LCDCAPA_PB0 + * @arg @ref LL_SYSCFG_LCDCAPA_PE11 + * @arg @ref LL_SYSCFG_LCDCAPA_PE12 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin) +{ + CLEAR_BIT(SYSCFG->PMC, Pin); +} +#endif /* LCD */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * + * (*) value not defined in all devices. + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16), Port << POSITION_VAL((Line >> 16))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16)) >> POSITION_VAL(Line >> 16)); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note 0x416: Cat.1 device\n + * 0x429: Cat.2 device\n + * 0x427: Cat.3 device\n + * 0x436: Cat.4 device or Cat.3 device(1)\n + * 0x437: Cat.5 device\n + * + * (1) Cat.3 devices: STM32L15xxC or STM3216xxC devices with + * RPN ending with letter 'A', in WLCSP64 packages or with more then 100 pin. + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as Cat.1 RevA -> 0x1000, Cat.2 Rev Z -> 0x1018... + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @} + */ + +#if defined(COMP_CSR_VREFOUTEN) +/** @defgroup SYSTEM_LL_EF_VREFOUT VREFOUT + * @{ + */ + +/** + * @brief Enable the output of internal reference voltage (VrefInt) on I/O pin. + * @note The VrefInt output can be routed to any I/O in group 3: + * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). + * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). + * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), + * CH1b (PF11) or CH2b (PF12). + * Note: Comparator peripheral clock must be preliminarily enabled. + * Refer to function "LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_COMP)". + * Note: In addition with this macro, VrefInt output buffer must be + * connected to the selected I/O pin. Refer to functions + * "LL_RI_EnableSwitchControlMode()" and "LL_RI_CloseIOSwitchLinkedToADC()". + * @note VrefInt output enable: Internal reference voltage connected to I/O group 3 + * VrefInt output disable: Internal reference voltage disconnected from I/O group 3 + * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Enable + * @retval None + */ +__STATIC_INLINE void LL_VREFOUT_Enable(void) +{ + SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN); +} + +/** + * @brief Disable the output of internal reference voltage (VrefInt) on I/O pin. + * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_Disable + * @retval None + */ +__STATIC_INLINE void LL_VREFOUT_Disable(void) +{ + CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN); +} + +/** + * @brief Check if output of internal reference voltage (VrefInt) is connected to I/O pin. + * @rmtoll COMP_CSR VREFOUTEN LL_VREFOUT_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_VREFOUT_IsEnabled(void) +{ + return ((READ_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) == COMP_CSR_VREFOUTEN) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /* COMP_CSR_VREFOUTEN */ + +/** @defgroup SYSTEM_LL_EF_RI RI + * @{ + */ + +/** + * @brief Configures the routing interface to map Input Capture x of TIMx to a selected I/O pin. + * @rmtoll RI_ICR IC1OS LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR IC2OS LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR IC3OS LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR IC4OS LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR TIM LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR IC1 LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR IC2 LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR IC3 LL_RI_SetRemapInputCapture_TIM\n + * RI_ICR IC4 LL_RI_SetRemapInputCapture_TIM + * @param TIM_Select This parameter can be one of the following values: + * @arg @ref LL_RI_TIM_SELECT_NONE + * @arg @ref LL_RI_TIM_SELECT_TIM2 + * @arg @ref LL_RI_TIM_SELECT_TIM3 + * @arg @ref LL_RI_TIM_SELECT_TIM4 + * @param InputCaptureChannel This parameter can be one of the following values: + * @arg @ref LL_RI_INPUTCAPTURE_1 + * @arg @ref LL_RI_INPUTCAPTURE_2 + * @arg @ref LL_RI_INPUTCAPTURE_3 + * @arg @ref LL_RI_INPUTCAPTURE_4 + * @param Input This parameter can be one of the following values: + * @arg @ref LL_RI_INPUTCAPTUREROUTING_0 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_1 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_2 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_3 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_4 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_5 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_6 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_7 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_8 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_9 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_10 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_11 + * @arg @ref LL_RI_INPUTCAPTUREROUTING_12 (*) + * @arg @ref LL_RI_INPUTCAPTUREROUTING_13 (*) + * @arg @ref LL_RI_INPUTCAPTUREROUTING_14 (*) + * @arg @ref LL_RI_INPUTCAPTUREROUTING_15 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select, uint32_t InputCaptureChannel, uint32_t Input) +{ + MODIFY_REG(RI->ICR, + RI_ICR_TIM | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (InputCaptureChannel & (RI_ICR_IC4OS | RI_ICR_IC3OS | RI_ICR_IC2OS | RI_ICR_IC1OS)), + TIM_Select | (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1)) | (Input << POSITION_VAL(InputCaptureChannel))); +} + +/** + * @brief Disable the TIM Input capture remap (select the standard AF) + * @rmtoll RI_ICR IC1 LL_RI_DisableRemapInputCapture_TIM\n + * RI_ICR IC2 LL_RI_DisableRemapInputCapture_TIM\n + * RI_ICR IC3 LL_RI_DisableRemapInputCapture_TIM\n + * RI_ICR IC4 LL_RI_DisableRemapInputCapture_TIM + * @param InputCaptureChannel This parameter can be a combination of the following values: + * @arg @ref LL_RI_INPUTCAPTURE_1 + * @arg @ref LL_RI_INPUTCAPTURE_2 + * @arg @ref LL_RI_INPUTCAPTURE_3 + * @arg @ref LL_RI_INPUTCAPTURE_4 + * @retval None + */ +__STATIC_INLINE void LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel) +{ + CLEAR_BIT(RI->ICR, (InputCaptureChannel & (RI_ICR_IC4 | RI_ICR_IC3 | RI_ICR_IC2 | RI_ICR_IC1))); +} + +/** + * @brief Close the routing interface Input Output switches linked to ADC. + * @rmtoll RI_ASCR1 CH LL_RI_CloseIOSwitchLinkedToADC\n + * RI_ASCR1 VCOMP LL_RI_CloseIOSwitchLinkedToADC + * @param IOSwitch This parameter can be a combination of the following values: + * @arg @ref LL_RI_IOSWITCH_CH0 + * @arg @ref LL_RI_IOSWITCH_CH1 + * @arg @ref LL_RI_IOSWITCH_CH2 + * @arg @ref LL_RI_IOSWITCH_CH3 + * @arg @ref LL_RI_IOSWITCH_CH4 + * @arg @ref LL_RI_IOSWITCH_CH5 + * @arg @ref LL_RI_IOSWITCH_CH6 + * @arg @ref LL_RI_IOSWITCH_CH7 + * @arg @ref LL_RI_IOSWITCH_CH8 + * @arg @ref LL_RI_IOSWITCH_CH9 + * @arg @ref LL_RI_IOSWITCH_CH10 + * @arg @ref LL_RI_IOSWITCH_CH11 + * @arg @ref LL_RI_IOSWITCH_CH12 + * @arg @ref LL_RI_IOSWITCH_CH13 + * @arg @ref LL_RI_IOSWITCH_CH14 + * @arg @ref LL_RI_IOSWITCH_CH15 + * @arg @ref LL_RI_IOSWITCH_CH18 + * @arg @ref LL_RI_IOSWITCH_CH19 + * @arg @ref LL_RI_IOSWITCH_CH20 + * @arg @ref LL_RI_IOSWITCH_CH21 + * @arg @ref LL_RI_IOSWITCH_CH22 + * @arg @ref LL_RI_IOSWITCH_CH23 + * @arg @ref LL_RI_IOSWITCH_CH24 + * @arg @ref LL_RI_IOSWITCH_CH25 + * @arg @ref LL_RI_IOSWITCH_VCOMP + * @arg @ref LL_RI_IOSWITCH_CH27 (*) + * @arg @ref LL_RI_IOSWITCH_CH28 (*) + * @arg @ref LL_RI_IOSWITCH_CH29 (*) + * @arg @ref LL_RI_IOSWITCH_CH30 (*) + * @arg @ref LL_RI_IOSWITCH_CH31 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch) +{ + SET_BIT(RI->ASCR1, IOSwitch); +} + +/** + * @brief Open the routing interface Input Output switches linked to ADC. + * @rmtoll RI_ASCR1 CH LL_RI_OpenIOSwitchLinkedToADC\n + * RI_ASCR1 VCOMP LL_RI_OpenIOSwitchLinkedToADC + * @param IOSwitch This parameter can be a combination of the following values: + * @arg @ref LL_RI_IOSWITCH_CH0 + * @arg @ref LL_RI_IOSWITCH_CH1 + * @arg @ref LL_RI_IOSWITCH_CH2 + * @arg @ref LL_RI_IOSWITCH_CH3 + * @arg @ref LL_RI_IOSWITCH_CH4 + * @arg @ref LL_RI_IOSWITCH_CH5 + * @arg @ref LL_RI_IOSWITCH_CH6 + * @arg @ref LL_RI_IOSWITCH_CH7 + * @arg @ref LL_RI_IOSWITCH_CH8 + * @arg @ref LL_RI_IOSWITCH_CH9 + * @arg @ref LL_RI_IOSWITCH_CH10 + * @arg @ref LL_RI_IOSWITCH_CH11 + * @arg @ref LL_RI_IOSWITCH_CH12 + * @arg @ref LL_RI_IOSWITCH_CH13 + * @arg @ref LL_RI_IOSWITCH_CH14 + * @arg @ref LL_RI_IOSWITCH_CH15 + * @arg @ref LL_RI_IOSWITCH_CH18 + * @arg @ref LL_RI_IOSWITCH_CH19 + * @arg @ref LL_RI_IOSWITCH_CH20 + * @arg @ref LL_RI_IOSWITCH_CH21 + * @arg @ref LL_RI_IOSWITCH_CH22 + * @arg @ref LL_RI_IOSWITCH_CH23 + * @arg @ref LL_RI_IOSWITCH_CH24 + * @arg @ref LL_RI_IOSWITCH_CH25 + * @arg @ref LL_RI_IOSWITCH_VCOMP + * @arg @ref LL_RI_IOSWITCH_CH27 (*) + * @arg @ref LL_RI_IOSWITCH_CH28 (*) + * @arg @ref LL_RI_IOSWITCH_CH29 (*) + * @arg @ref LL_RI_IOSWITCH_CH30 (*) + * @arg @ref LL_RI_IOSWITCH_CH31 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch) +{ + CLEAR_BIT(RI->ASCR1, IOSwitch); +} + +/** + * @brief Enable the switch control mode. + * @rmtoll RI_ASCR1 SCM LL_RI_EnableSwitchControlMode + * @retval None + */ +__STATIC_INLINE void LL_RI_EnableSwitchControlMode(void) +{ + SET_BIT(RI->ASCR1, RI_ASCR1_SCM); +} + +/** + * @brief Disable the switch control mode. + * @rmtoll RI_ASCR1 SCM LL_RI_DisableSwitchControlMode + * @retval None + */ +__STATIC_INLINE void LL_RI_DisableSwitchControlMode(void) +{ + CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM); +} + +/** + * @brief Close the routing interface Input Output switches not linked to ADC. + * @rmtoll RI_ASCR2 GR10_1 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR10_2 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR10_3 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR10_4 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_1 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_2 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR5_1 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR5_2 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR5_3 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_1 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_2 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_3 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_4 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH0b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH1b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH2b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH3b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH6b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH7b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH8b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH9b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH10b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH11b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH12b LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_3 LL_RI_CloseIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_4 LL_RI_CloseIOSwitchNotLinkedToADC + * @param IOSwitch This parameter can be a combination of the following values: + * @arg @ref LL_RI_IOSWITCH_GR10_1 + * @arg @ref LL_RI_IOSWITCH_GR10_2 + * @arg @ref LL_RI_IOSWITCH_GR10_3 + * @arg @ref LL_RI_IOSWITCH_GR10_4 + * @arg @ref LL_RI_IOSWITCH_GR6_1 + * @arg @ref LL_RI_IOSWITCH_GR6_2 + * @arg @ref LL_RI_IOSWITCH_GR5_1 + * @arg @ref LL_RI_IOSWITCH_GR5_2 + * @arg @ref LL_RI_IOSWITCH_GR5_3 + * @arg @ref LL_RI_IOSWITCH_GR4_1 + * @arg @ref LL_RI_IOSWITCH_GR4_2 + * @arg @ref LL_RI_IOSWITCH_GR4_3 + * @arg @ref LL_RI_IOSWITCH_CH0b (*) + * @arg @ref LL_RI_IOSWITCH_CH1b (*) + * @arg @ref LL_RI_IOSWITCH_CH2b (*) + * @arg @ref LL_RI_IOSWITCH_CH3b (*) + * @arg @ref LL_RI_IOSWITCH_CH6b (*) + * @arg @ref LL_RI_IOSWITCH_CH7b (*) + * @arg @ref LL_RI_IOSWITCH_CH8b (*) + * @arg @ref LL_RI_IOSWITCH_CH9b (*) + * @arg @ref LL_RI_IOSWITCH_CH10b (*) + * @arg @ref LL_RI_IOSWITCH_CH11b (*) + * @arg @ref LL_RI_IOSWITCH_CH12b (*) + * @arg @ref LL_RI_IOSWITCH_GR6_3 + * @arg @ref LL_RI_IOSWITCH_GR6_4 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch) +{ + SET_BIT(RI->ASCR2, IOSwitch); +} + +/** + * @brief Open the routing interface Input Output switches not linked to ADC. + * @rmtoll RI_ASCR2 GR10_1 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR10_2 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR10_3 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR10_4 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_1 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_2 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR5_1 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR5_2 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR5_3 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_1 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_2 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_3 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR4_4 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH0b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH1b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH2b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH3b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH6b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH7b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH8b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH9b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH10b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH11b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 CH12b LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_3 LL_RI_OpenIOSwitchNotLinkedToADC\n + * RI_ASCR2 GR6_4 LL_RI_OpenIOSwitchNotLinkedToADC + * @param IOSwitch This parameter can be a combination of the following values: + * @arg @ref LL_RI_IOSWITCH_GR10_1 + * @arg @ref LL_RI_IOSWITCH_GR10_2 + * @arg @ref LL_RI_IOSWITCH_GR10_3 + * @arg @ref LL_RI_IOSWITCH_GR10_4 + * @arg @ref LL_RI_IOSWITCH_GR6_1 + * @arg @ref LL_RI_IOSWITCH_GR6_2 + * @arg @ref LL_RI_IOSWITCH_GR5_1 + * @arg @ref LL_RI_IOSWITCH_GR5_2 + * @arg @ref LL_RI_IOSWITCH_GR5_3 + * @arg @ref LL_RI_IOSWITCH_GR4_1 + * @arg @ref LL_RI_IOSWITCH_GR4_2 + * @arg @ref LL_RI_IOSWITCH_GR4_3 + * @arg @ref LL_RI_IOSWITCH_CH0b (*) + * @arg @ref LL_RI_IOSWITCH_CH1b (*) + * @arg @ref LL_RI_IOSWITCH_CH2b (*) + * @arg @ref LL_RI_IOSWITCH_CH3b (*) + * @arg @ref LL_RI_IOSWITCH_CH6b (*) + * @arg @ref LL_RI_IOSWITCH_CH7b (*) + * @arg @ref LL_RI_IOSWITCH_CH8b (*) + * @arg @ref LL_RI_IOSWITCH_CH9b (*) + * @arg @ref LL_RI_IOSWITCH_CH10b (*) + * @arg @ref LL_RI_IOSWITCH_CH11b (*) + * @arg @ref LL_RI_IOSWITCH_CH12b (*) + * @arg @ref LL_RI_IOSWITCH_GR6_3 + * @arg @ref LL_RI_IOSWITCH_GR6_4 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch) +{ + CLEAR_BIT(RI->ASCR2, IOSwitch); +} + +/** + * @brief Enable Hysteresis of the input schmitt trigger of the port X + * @rmtoll RI_HYSCR1 PA LL_RI_EnableHysteresis\n + * RI_HYSCR1 PB LL_RI_EnableHysteresis\n + * RI_HYSCR1 PC LL_RI_EnableHysteresis\n + * RI_HYSCR1 PD LL_RI_EnableHysteresis\n + * RI_HYSCR1 PE LL_RI_EnableHysteresis\n + * RI_HYSCR1 PF LL_RI_EnableHysteresis\n + * RI_HYSCR1 PG LL_RI_EnableHysteresis\n + * RI_HYSCR2 PA LL_RI_EnableHysteresis\n + * RI_HYSCR2 PB LL_RI_EnableHysteresis\n + * RI_HYSCR2 PC LL_RI_EnableHysteresis\n + * RI_HYSCR2 PD LL_RI_EnableHysteresis\n + * RI_HYSCR2 PE LL_RI_EnableHysteresis\n + * RI_HYSCR2 PF LL_RI_EnableHysteresis\n + * RI_HYSCR2 PG LL_RI_EnableHysteresis\n + * RI_HYSCR3 PA LL_RI_EnableHysteresis\n + * RI_HYSCR3 PB LL_RI_EnableHysteresis\n + * RI_HYSCR3 PC LL_RI_EnableHysteresis\n + * RI_HYSCR3 PD LL_RI_EnableHysteresis\n + * RI_HYSCR3 PE LL_RI_EnableHysteresis\n + * RI_HYSCR3 PF LL_RI_EnableHysteresis\n + * RI_HYSCR3 PG LL_RI_EnableHysteresis\n + * RI_HYSCR4 PA LL_RI_EnableHysteresis\n + * RI_HYSCR4 PB LL_RI_EnableHysteresis\n + * RI_HYSCR4 PC LL_RI_EnableHysteresis\n + * RI_HYSCR4 PD LL_RI_EnableHysteresis\n + * RI_HYSCR4 PE LL_RI_EnableHysteresis\n + * RI_HYSCR4 PF LL_RI_EnableHysteresis\n + * RI_HYSCR4 PG LL_RI_EnableHysteresis + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_HSYTERESIS_PORT_A + * @arg @ref LL_RI_HSYTERESIS_PORT_B + * @arg @ref LL_RI_HSYTERESIS_PORT_C + * @arg @ref LL_RI_HSYTERESIS_PORT_D + * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) + * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) + * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_EnableHysteresis(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + (Port >> 1U)); + CLEAR_BIT(*reg, Pin << (16U * (Port & 1U))); +} + +/** + * @brief Disable Hysteresis of the input schmitt trigger of the port X + * @rmtoll RI_HYSCR1 PA LL_RI_DisableHysteresis\n + * RI_HYSCR1 PB LL_RI_DisableHysteresis\n + * RI_HYSCR1 PC LL_RI_DisableHysteresis\n + * RI_HYSCR1 PD LL_RI_DisableHysteresis\n + * RI_HYSCR1 PE LL_RI_DisableHysteresis\n + * RI_HYSCR1 PF LL_RI_DisableHysteresis\n + * RI_HYSCR1 PG LL_RI_DisableHysteresis\n + * RI_HYSCR2 PA LL_RI_DisableHysteresis\n + * RI_HYSCR2 PB LL_RI_DisableHysteresis\n + * RI_HYSCR2 PC LL_RI_DisableHysteresis\n + * RI_HYSCR2 PD LL_RI_DisableHysteresis\n + * RI_HYSCR2 PE LL_RI_DisableHysteresis\n + * RI_HYSCR2 PF LL_RI_DisableHysteresis\n + * RI_HYSCR2 PG LL_RI_DisableHysteresis\n + * RI_HYSCR3 PA LL_RI_DisableHysteresis\n + * RI_HYSCR3 PB LL_RI_DisableHysteresis\n + * RI_HYSCR3 PC LL_RI_DisableHysteresis\n + * RI_HYSCR3 PD LL_RI_DisableHysteresis\n + * RI_HYSCR3 PE LL_RI_DisableHysteresis\n + * RI_HYSCR3 PF LL_RI_DisableHysteresis\n + * RI_HYSCR3 PG LL_RI_DisableHysteresis\n + * RI_HYSCR4 PA LL_RI_DisableHysteresis\n + * RI_HYSCR4 PB LL_RI_DisableHysteresis\n + * RI_HYSCR4 PC LL_RI_DisableHysteresis\n + * RI_HYSCR4 PD LL_RI_DisableHysteresis\n + * RI_HYSCR4 PE LL_RI_DisableHysteresis\n + * RI_HYSCR4 PF LL_RI_DisableHysteresis\n + * RI_HYSCR4 PG LL_RI_DisableHysteresis + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_HSYTERESIS_PORT_A + * @arg @ref LL_RI_HSYTERESIS_PORT_B + * @arg @ref LL_RI_HSYTERESIS_PORT_C + * @arg @ref LL_RI_HSYTERESIS_PORT_D + * @arg @ref LL_RI_HSYTERESIS_PORT_E (*) + * @arg @ref LL_RI_HSYTERESIS_PORT_F (*) + * @arg @ref LL_RI_HSYTERESIS_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_DisableHysteresis(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->HYSCR1) + ((Port >> 1U) << 2U)); + SET_BIT(*reg, Pin << (16U * (Port & 1U))); +} + +#if defined(RI_ASMR1_PA) +/** + * @brief Control analog switches of port X through the ADC interface or RI_ASCRx registers. + * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByADC\n + * RI_ASMR1 PB LL_RI_ControlSwitchByADC\n + * RI_ASMR1 PC LL_RI_ControlSwitchByADC\n + * RI_ASMR1 PF LL_RI_ControlSwitchByADC\n + * RI_ASMR1 PG LL_RI_ControlSwitchByADC\n + * RI_ASMR2 PA LL_RI_ControlSwitchByADC\n + * RI_ASMR2 PB LL_RI_ControlSwitchByADC\n + * RI_ASMR2 PC LL_RI_ControlSwitchByADC\n + * RI_ASMR2 PF LL_RI_ControlSwitchByADC\n + * RI_ASMR2 PG LL_RI_ControlSwitchByADC\n + * RI_ASMR3 PA LL_RI_ControlSwitchByADC\n + * RI_ASMR3 PB LL_RI_ControlSwitchByADC\n + * RI_ASMR3 PC LL_RI_ControlSwitchByADC\n + * RI_ASMR3 PF LL_RI_ControlSwitchByADC\n + * RI_ASMR3 PG LL_RI_ControlSwitchByADC\n + * RI_ASMR4 PA LL_RI_ControlSwitchByADC\n + * RI_ASMR4 PB LL_RI_ControlSwitchByADC\n + * RI_ASMR4 PC LL_RI_ControlSwitchByADC\n + * RI_ASMR4 PF LL_RI_ControlSwitchByADC\n + * RI_ASMR4 PG LL_RI_ControlSwitchByADC\n + * RI_ASMR5 PA LL_RI_ControlSwitchByADC\n + * RI_ASMR5 PB LL_RI_ControlSwitchByADC\n + * RI_ASMR5 PC LL_RI_ControlSwitchByADC\n + * RI_ASMR5 PF LL_RI_ControlSwitchByADC\n + * RI_ASMR5 PG LL_RI_ControlSwitchByADC + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_PORT_A + * @arg @ref LL_RI_PORT_B + * @arg @ref LL_RI_PORT_C + * @arg @ref LL_RI_PORT_F (*) + * @arg @ref LL_RI_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_ControlSwitchByADC(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); + CLEAR_BIT(*reg, Pin); +} +#endif /* RI_ASMR1_PA */ + +#if defined(RI_ASMR1_PA) +/** + * @brief Control analog switches of port X by the timer OC. + * @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByTIM\n + * RI_ASMR1 PB LL_RI_ControlSwitchByTIM\n + * RI_ASMR1 PC LL_RI_ControlSwitchByTIM\n + * RI_ASMR1 PF LL_RI_ControlSwitchByTIM\n + * RI_ASMR1 PG LL_RI_ControlSwitchByTIM\n + * RI_ASMR2 PA LL_RI_ControlSwitchByTIM\n + * RI_ASMR2 PB LL_RI_ControlSwitchByTIM\n + * RI_ASMR2 PC LL_RI_ControlSwitchByTIM\n + * RI_ASMR2 PF LL_RI_ControlSwitchByTIM\n + * RI_ASMR2 PG LL_RI_ControlSwitchByTIM\n + * RI_ASMR3 PA LL_RI_ControlSwitchByTIM\n + * RI_ASMR3 PB LL_RI_ControlSwitchByTIM\n + * RI_ASMR3 PC LL_RI_ControlSwitchByTIM\n + * RI_ASMR3 PF LL_RI_ControlSwitchByTIM\n + * RI_ASMR3 PG LL_RI_ControlSwitchByTIM\n + * RI_ASMR4 PA LL_RI_ControlSwitchByTIM\n + * RI_ASMR4 PB LL_RI_ControlSwitchByTIM\n + * RI_ASMR4 PC LL_RI_ControlSwitchByTIM\n + * RI_ASMR4 PF LL_RI_ControlSwitchByTIM\n + * RI_ASMR4 PG LL_RI_ControlSwitchByTIM\n + * RI_ASMR5 PA LL_RI_ControlSwitchByTIM\n + * RI_ASMR5 PB LL_RI_ControlSwitchByTIM\n + * RI_ASMR5 PC LL_RI_ControlSwitchByTIM\n + * RI_ASMR5 PF LL_RI_ControlSwitchByTIM\n + * RI_ASMR5 PG LL_RI_ControlSwitchByTIM + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_PORT_A + * @arg @ref LL_RI_PORT_B + * @arg @ref LL_RI_PORT_C + * @arg @ref LL_RI_PORT_F (*) + * @arg @ref LL_RI_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_ControlSwitchByTIM(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2)); + SET_BIT(*reg, Pin); +} +#endif /* RI_ASMR1_PA */ + +#if defined(RI_CMR1_PA) +/** + * @brief Mask the input of port X during the capacitive sensing acquisition. + * @rmtoll RI_CMR1 PA LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR1 PB LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR1 PC LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR1 PF LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR1 PG LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR2 PA LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR2 PB LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR2 PC LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR2 PF LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR2 PG LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR3 PA LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR3 PB LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR3 PC LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR3 PF LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR3 PG LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR4 PA LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR4 PB LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR4 PC LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR4 PF LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR4 PG LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR5 PA LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR5 PB LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR5 PC LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR5 PF LL_RI_MaskChannelDuringAcquisition\n + * RI_CMR5 PG LL_RI_MaskChannelDuringAcquisition + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_PORT_A + * @arg @ref LL_RI_PORT_B + * @arg @ref LL_RI_PORT_C + * @arg @ref LL_RI_PORT_F (*) + * @arg @ref LL_RI_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_MaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); + CLEAR_BIT(*reg, Pin); +} +#endif /* RI_CMR1_PA */ + +#if defined(RI_CMR1_PA) +/** + * @brief Unmask the input of port X during the capacitive sensing acquisition. + * @rmtoll RI_CMR1 PA LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR1 PB LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR1 PC LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR1 PF LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR1 PG LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR2 PA LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR2 PB LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR2 PC LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR2 PF LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR2 PG LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR3 PA LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR3 PB LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR3 PC LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR3 PF LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR3 PG LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR4 PA LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR4 PB LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR4 PC LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR4 PF LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR4 PG LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR5 PA LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR5 PB LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR5 PC LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR5 PF LL_RI_UnmaskChannelDuringAcquisition\n + * RI_CMR5 PG LL_RI_UnmaskChannelDuringAcquisition + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_PORT_A + * @arg @ref LL_RI_PORT_B + * @arg @ref LL_RI_PORT_C + * @arg @ref LL_RI_PORT_F (*) + * @arg @ref LL_RI_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2)); + SET_BIT(*reg, Pin); +} +#endif /* RI_CMR1_PA */ + +#if defined(RI_CICR1_PA) +/** + * @brief Identify channel for timer input capture + * @rmtoll RI_CICR1 PA LL_RI_IdentifyChannelIO\n + * RI_CICR1 PB LL_RI_IdentifyChannelIO\n + * RI_CICR1 PC LL_RI_IdentifyChannelIO\n + * RI_CICR1 PF LL_RI_IdentifyChannelIO\n + * RI_CICR1 PG LL_RI_IdentifyChannelIO\n + * RI_CICR2 PA LL_RI_IdentifyChannelIO\n + * RI_CICR2 PB LL_RI_IdentifyChannelIO\n + * RI_CICR2 PC LL_RI_IdentifyChannelIO\n + * RI_CICR2 PF LL_RI_IdentifyChannelIO\n + * RI_CICR2 PG LL_RI_IdentifyChannelIO\n + * RI_CICR3 PA LL_RI_IdentifyChannelIO\n + * RI_CICR3 PB LL_RI_IdentifyChannelIO\n + * RI_CICR3 PC LL_RI_IdentifyChannelIO\n + * RI_CICR3 PF LL_RI_IdentifyChannelIO\n + * RI_CICR3 PG LL_RI_IdentifyChannelIO\n + * RI_CICR4 PA LL_RI_IdentifyChannelIO\n + * RI_CICR4 PB LL_RI_IdentifyChannelIO\n + * RI_CICR4 PC LL_RI_IdentifyChannelIO\n + * RI_CICR4 PF LL_RI_IdentifyChannelIO\n + * RI_CICR4 PG LL_RI_IdentifyChannelIO\n + * RI_CICR5 PA LL_RI_IdentifyChannelIO\n + * RI_CICR5 PB LL_RI_IdentifyChannelIO\n + * RI_CICR5 PC LL_RI_IdentifyChannelIO\n + * RI_CICR5 PF LL_RI_IdentifyChannelIO\n + * RI_CICR5 PG LL_RI_IdentifyChannelIO + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_PORT_A + * @arg @ref LL_RI_PORT_B + * @arg @ref LL_RI_PORT_C + * @arg @ref LL_RI_PORT_F (*) + * @arg @ref LL_RI_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_IdentifyChannelIO(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); + CLEAR_BIT(*reg, Pin); +} +#endif /* RI_CICR1_PA */ + +#if defined(RI_CICR1_PA) +/** + * @brief Identify sampling capacitor for timer input capture + * @rmtoll RI_CICR1 PA LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR1 PB LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR1 PC LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR1 PF LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR1 PG LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR2 PA LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR2 PB LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR2 PC LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR2 PF LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR2 PG LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR3 PA LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR3 PB LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR3 PC LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR3 PF LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR3 PG LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR4 PA LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR4 PB LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR4 PC LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR4 PF LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR4 PG LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR5 PA LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR5 PB LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR5 PC LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR5 PF LL_RI_IdentifySamplingCapacitorIO\n + * RI_CICR5 PG LL_RI_IdentifySamplingCapacitorIO + * @param Port This parameter can be one of the following values: + * @arg @ref LL_RI_PORT_A + * @arg @ref LL_RI_PORT_B + * @arg @ref LL_RI_PORT_C + * @arg @ref LL_RI_PORT_F (*) + * @arg @ref LL_RI_PORT_G (*) + * + * (*) value not defined in all devices. + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_RI_PIN_0 + * @arg @ref LL_RI_PIN_1 + * @arg @ref LL_RI_PIN_2 + * @arg @ref LL_RI_PIN_3 + * @arg @ref LL_RI_PIN_4 + * @arg @ref LL_RI_PIN_5 + * @arg @ref LL_RI_PIN_6 + * @arg @ref LL_RI_PIN_7 + * @arg @ref LL_RI_PIN_8 + * @arg @ref LL_RI_PIN_9 + * @arg @ref LL_RI_PIN_10 + * @arg @ref LL_RI_PIN_11 + * @arg @ref LL_RI_PIN_12 + * @arg @ref LL_RI_PIN_13 + * @arg @ref LL_RI_PIN_14 + * @arg @ref LL_RI_PIN_15 + * @arg @ref LL_RI_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_RI_IdentifySamplingCapacitorIO(uint32_t Port, uint32_t Pin) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2)); + SET_BIT(*reg, Pin); +} +#endif /* RI_CICR1_PA */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @note Latetency can be modified only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @note Prefetch can be enabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @note Prefetch can be disabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess) + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == FLASH_ACR_PRFTEN) ? 1UL : 0UL); +} + +/** + * @brief Enable 64-bit access + * @rmtoll FLASH_ACR ACC64 LL_FLASH_Enable64bitAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_Enable64bitAccess(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ACC64); +} + +/** + * @brief Disable 64-bit access + * @rmtoll FLASH_ACR ACC64 LL_FLASH_Disable64bitAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_Disable64bitAccess(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ACC64); +} + +/** + * @brief Check if 64-bit access is enabled + * @rmtoll FLASH_ACR ACC64 LL_FLASH_Is64bitAccessEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_Is64bitAccessEnabled(void) +{ + return ((READ_BIT(FLASH->ACR, FLASH_ACR_ACC64) == FLASH_ACR_ACC64) ? 1UL : 0UL); +} + + +/** + * @brief Enable Flash Power-down mode during run mode or Low-power run mode + * @note Flash memory can be put in power-down mode only when the code is executed + * from RAM + * @note Flash must not be accessed when power down is enabled + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); + SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); +} + +/** + * @brief Disable Flash Power-down mode during run mode or Low-power run mode + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n + * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n + * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); + CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); +} + +/** + * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined(RI) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_SYSTEM_H */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h new file mode 100644 index 0000000..262bdf1 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_ll_utils.h @@ -0,0 +1,270 @@ +/** + ****************************************************************************** + * @file stm32l1xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L1xx_LL_UTILS_H +#define __STM32L1xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx.h" + +/** @addtogroup STM32L1xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x04U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x14U)))); +} + +/** + * @brief Get Flash memory size + * @note For DEV_ID = 0x416 or 0x427 or 0x429 or 0x437, this field value indicates the Flash memory + * size of the device in Kbytes.\n + * Example: 0x0080 = 128 Kbytes.\n + * For DEV_ID = 0x436, the field value can be '0' or '1', with '0' for 384 Kbytes and '1' for 256 Kbytes. + * @note For DEV_ID = 0x429, only LSB part of F_SIZE: F_SIZE[7:0] is valid. The MSB part + * F_SIZE[15:8] is reserved and must be ignored. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L1xx_LL_UTILS_H */ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/LICENSE.txt b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/License.md b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/License.md new file mode 100644 index 0000000..f8a5385 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/License.md @@ -0,0 +1,3 @@ +# Copyright (c) 2017 STMicroelectronics + +This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). \ No newline at end of file diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c new file mode 100644 index 0000000..cf8ec0d --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c @@ -0,0 +1,570 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Defines HAL Private Defines + * @{ + */ + +/** + * @brief STM32L1xx HAL Driver version number + */ +#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __STM32L1xx_HAL_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ +#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\ + |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32L1xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK (0x00000FFFU) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/* Exported variables --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */ +uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) De-initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Flash prefetch, + * configures time base source, NVIC and Low level hardware + * @note This function is called at the beginning of program after reset and before + * the clock configuration + * @note The time base configuration is based on MSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation,Systick is used as source of time base. + * the tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } + + /* Return function status */ + return status; +} + +/** + * @brief This function de-initializes common part of the HAL and stops the source + * of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base: + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (uwTickFreq != 0U) + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Get the unique device identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provide a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @param Freq tick frequency + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +uint32_t HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a period to guaranty minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend the Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume the Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Return the HAL revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32L1xx_HAL_VERSION; +} + +/** + * @brief Return the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Return the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier 31:0 bits + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier 63:32 bits + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 0x4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier 95:64 bits + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U)))); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions + * @brief DBGMCU Peripheral Control functions + * +@verbatim + =============================================================================== + ##### DBGMCU Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c new file mode 100644 index 0000000..37fb751 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using Cortex HAL driver *** + =========================================================== + [..] + This section provide functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M3 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using Cortex HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for 1 msec interrupts. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32l1xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* + Additional Tables: CORTEX_NVIC_Priority_Table + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ========================================================================================================================== +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provide the Cortex HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @param PreemptPriority The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c new file mode 100644 index 0000000..2c476a4 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c @@ -0,0 +1,909 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function to register callbacks with HAL_DMA_RegisterCallback(). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ + +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp; + + /* Check the DMA handle allocation */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + +#if defined (DMA2) + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + /* calculation of the channel index */ + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + + /* Check the DMA handle allocation */ + if (NULL == hdma ) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + +#if defined (DMA2) + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + /* calculation of the channel index */ + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif + + /* Reset DMA Channel CR register */ + hdma->Instance->CCR = 0U; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if(NULL != hdma->XferHalfCpltCallback ) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral state */ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return status; + } +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while((hdma->DmaBaseAddress->ISR & temp) == 0U) + { + if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU)); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) + { + + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + /* Disable the transfer complete and error interrupt */ + /* if the DMA mode is not CIRCULAR */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + return; +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + + + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA handle state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c new file mode 100644 index 0000000..a28531e --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c @@ -0,0 +1,547 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c new file mode 100644 index 0000000..daae63e --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c @@ -0,0 +1,723 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32L1xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page + (++) Program functions: Fast Word and Half Page(should be + executed from internal SRAM). + + (#) DATA EEPROM Programming functions: this group includes all + needed functions to erase and program the DATA EEPROM memory: + (++) Lock and Unlock the DATA EEPROM interface. + (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase + Double Word (should be executed from internal SRAM). + (++) Program functions: Fast Program Byte, Fast Program Half-Word, + FastProgramWord, Program Byte, Program Half-Word, + Program Word and Program Double-Word (should be executed + from internal SRAM). + + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Set/Get the Read protection Level. + (++) Set/Get the BOR level. + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + (#) FLASH Interface configuration functions: this group includes + the management of following features: + (++) Enable/Disable the RUN PowerDown mode. + (++) Enable/Disable the SLEEP PowerDown mode. + + (#) FLASH Peripheral State methods: this group includes + the management of following features: + (++) Wait for the FLASH operation + (++) Get the specific FLASH error flag + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the 64 bit Read Access. + (+) Enable/Disable the Flash power-down + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + + [..] The FLASH Memory Programming functions, includes the following functions: + (+) HAL_FLASH_Unlock(void); + (+) HAL_FLASH_Lock(void); + (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page or program data. + (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + + ##### Option Bytes Programming functions ##### + ============================================================================== + + [..] The FLASH_Option Bytes Programming_functions, includes the following functions: + (+) HAL_FLASH_OB_Unlock(void); + (+) HAL_FLASH_OB_Lock(void); + (+) HAL_FLASH_OB_Launch(void); + (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); + (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control + register access. + (#) Call the following functions to program the desired option bytes. + (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); + (#) Once all needed option bytes to be programmed are correctly written, call the + HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended + to protect the option Bytes against possible unwanted operations). + + [..] Proprietary code Read Out Protection (PcROP): + (#) The PcROP sector is selected by using the same option bytes as the Write + protection. As a result, these 2 options are exclusive each other. + (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below: + (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program word at a specified address + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /*Program word (32-bit) at a specified address.*/ + *(__IO uint32_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program word at a specified address with interrupt enabled. + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + pFlash.Address = Address; + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit) at a specified address. */ + *(__IO uint32_t *)Address = Data; + } + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ + if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || +#if defined(FLASH_SR_RDERR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || +#endif /* FLASH_SR_OPTVERRUSR */ + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Return the faulty sector */ + addresstmp = pFlash.Page; + pFlash.Page = 0xFFFFFFFFU; + } + else + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + } + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase */ + if(pFlash.NbPagesToErase != 0U) + { + addresstmp = pFlash.Page; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Page + FLASH_PAGE_SIZE; + pFlash.Page = addresstmp; + + /* If the erase operation is completed, disable the ERASE Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Page = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else + { + /* If the program operation is completed, disable the PROG Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PROG and ERASE */ + CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) + { + /* Unlocking FLASH_PECR register access*/ + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) + { + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); + + /* Verify that PELOCK is unlocked */ + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) + { + return HAL_ERROR; + } + } + + /* Unlocking the program memory access */ + WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); + WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); + + /* Verify that PRGLOCK is unlocked */ + if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the PRGLOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) + { + /* Unlocking FLASH_PECR register access*/ + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) + { + /* Unlocking FLASH_PECR register access*/ + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); + + /* Verify that PELOCK is unlocked */ + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) + { + return HAL_ERROR; + } + } + + /* Unlocking the option bytes block access */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* Verify that OPTLOCK is unlocked */ + if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the option bytes block access */ + SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to launch the option byte loading */ + SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || +#if defined(FLASH_SR_RDERR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || +#endif /* FLASH_SR_OPTVERRUSR */ + __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + flags |= FLASH_FLAG_WRPERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + flags |= FLASH_FLAG_PGAERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + flags |= FLASH_FLAG_OPTVERR; + } + +#if defined(FLASH_SR_RDERR) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + flags |= FLASH_FLAG_RDERR; + } +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR; + flags |= FLASH_FLAG_OPTVERRUSR; + } +#endif /* FLASH_SR_OPTVERRUSR */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; + flags |= FLASH_FLAG_SIZERR; + } + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c new file mode 100644 index 0000000..d698393 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c @@ -0,0 +1,1870 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + FLASH Interface configuration + * + FLASH Memory Erasing + * + DATA EEPROM Programming/Erasing + * + Option Bytes Programming + * + Interrupts management + * + @verbatim + ============================================================================== + ##### Flash peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other products, the FLASH interface for STM32L1xx + devices contains the following additional features + (+) Erase functions + (+) DATA_EEPROM memory management + (+) BOOT option bit configuration + (+) PCROP protection for all sectors + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32L1xx. It includes: + (+) Full DATA_EEPROM erase and program management + (+) Boot activation + (+) PCROP protection configuration and control for all pages + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_PageErase(uint32_t PageAddress); +static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState); +static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState); +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) +static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState); +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) +static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState); +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) +static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState); +#endif /* STM32L151xE || STM32L152xE || STM32L151xDX || ... */ +#if defined(FLASH_OBR_SPRMOD) +static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState); +#endif /* FLASH_OBR_SPRMOD */ +#if defined(FLASH_OBR_nRST_BFB2) +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT); +#endif /* FLASH_OBR_nRST_BFB2 */ +static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); +static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR); +static uint8_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); +static uint8_t FLASH_OB_GetBOR(void); +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) HAL_FLASHEx_Erase: return only when erase has been done + (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + +/** + * @brief Erase the specified FLASH memory Pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between + * 2 banks, user should perform pages erase by bank only. + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Check the parameters */ + assert_param(IS_NBPAGES(pEraseInit->NbPages)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U)); + +#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX) + /* Check on which bank belongs the 1st address to erase */ + if (pEraseInit->PageAddress < FLASH_BANK2_BASE) + { + /* BANK1 */ + /* Check that last page to erase still belongs to BANK1 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END) + { + /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } + else + { + /* BANK2 */ + /* Check that last page to erase still belongs to BANK2 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END) + { + /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } +#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */ + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the ERASE Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * End of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter + * 0xFFFFFFFF + * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between + * 2 banks, user should perform pages erase by bank only. + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_NBPAGES(pEraseInit->NbPages)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + +#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX) + /* Check on which bank belongs the 1st address to erase */ + if (pEraseInit->PageAddress < FLASH_BANK2_BASE) + { + /* BANK1 */ + /* Check that last page to erase still belongs to BANK1 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END) + { + /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } + else + { + /* BANK2 */ + /* Check that last page to erase still belongs to BANK2 */ + if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END) + { + /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not + continuous */ + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return HAL_ERROR; + } + } +#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control + register access. + (#) Call following function to program the desired option bytes. + (++) HAL_FLASHEx_OBProgram: + - To Enable/Disable the desired sector write protection. + - To set the desired read Protection Level. + - To configure the user option Bytes: IWDG, STOP and the Standby. + - To Set the BOR level. + (#) Once all needed option bytes to be programmed are correctly written, call the + HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended + to protect the option Bytes against possible unwanted operations). + + [..] Proprietary code Read Out Protection (PcROP): + (#) The PcROP sector is selected by using the same option bytes as the Write + protection (nWRPi bits). As a result, these 2 options are exclusive each other. + (#) In order to activate the PcROP (change the function of the nWRPi option bits), + the SPRMOD option bit must be activated. + (#) The active value of nWRPi bits is inverted when PCROP mode is active, this + means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" + is read/write protected. + (#) To activate PCROP mode for Flash sector(s), you need to call the following function: + (++) HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected + (++) HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection + (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices. + +@endverbatim + * @{ + */ + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /*Write protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected Sector*/ + status = FLASH_OB_WRPConfig(pOBInit, ENABLE); + } + else + { + /* Disable of Write protection on the selected Sector*/ + status = FLASH_OB_WRPConfig(pOBInit, DISABLE); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDPConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NORST, + pOBInit->USERConfig & OB_STDBY_NORST); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* BOR Level configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BORConfig(pOBInit->BORLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + + /*Get WRP1*/ + pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1); + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + + /*Get WRP2*/ + pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2); + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) + + /*Get WRP3*/ + pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3); + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) + + /*Get WRP4*/ + pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4); + +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); +} + +#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) + +/** + * @brief Program option bytes + * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OBEX(pAdvOBInit->OptionType)); + +#if defined(FLASH_OBR_SPRMOD) + + /* Program PCROP option byte*/ + if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + /* Check the parameters */ + assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); + if (pAdvOBInit->PCROPState == OB_PCROP_STATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE); + if (status != HAL_OK) + { + return status; + } + } + else + { + /* Disable of Write protection on the selected Sector*/ + status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE); + if (status != HAL_OK) + { + return status; + } + } + } + +#endif /* FLASH_OBR_SPRMOD */ + +#if defined(FLASH_OBR_nRST_BFB2) + + /* Program BOOT config option byte */ + if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) + { + status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); + } + +#endif /* FLASH_OBR_nRST_BFB2 */ + + return status; +} + +/** + * @brief Get the OBEX byte configuration + * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ + pAdvOBInit->OptionType = 0U; + +#if defined(FLASH_OBR_SPRMOD) + + pAdvOBInit->OptionType |= OPTIONBYTE_PCROP; + + /*Get PCROP state */ + pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD); + + /*Get PCROP protected sector from 0 to 31 */ + pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1; + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) + + /*Get PCROP protected sector from 32 to 63 */ + pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2; + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ +#endif /* FLASH_OBR_SPRMOD */ + +#if defined(FLASH_OBR_nRST_BFB2) + + pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG; + + /* Get Boot config OB */ + pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16U; + +#endif /* FLASH_OBR_nRST_BFB2 */ +} + +#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ + +#if defined(FLASH_OBR_SPRMOD) + +/** + * @brief Select the Protection Mode (SPRMOD). + * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices + * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t tmp1 = 0U; + uint32_t tmp2 = 0U; + uint8_t optiontmp = 0U; + uint16_t optiontmp2 = 0U; + + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* Mask RDP Byte */ + optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); + + /* Update Option Byte */ + optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); + + /* calculate the option byte to write */ + tmp1 = (uint16_t)(~(optiontmp2 )); + tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* program PCRop */ + OB->RDP = tmp2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the Read protection operation Status */ + return status; +} + +/** + * @brief Deselect the Protection Mode (SPRMOD). + * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices + * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t tmp1 = 0U; + uint32_t tmp2 = 0U; + uint8_t optiontmp = 0U; + uint16_t optiontmp2 = 0U; + + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* Mask RDP Byte */ + optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); + + /* Update Option Byte */ + optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); + + /* calculate the option byte to write */ + tmp1 = (uint16_t)(~(optiontmp2 )); + tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* program PCRop */ + OB->RDP = tmp2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the Read protection operation Status */ + return status; +} + +#endif /* FLASH_OBR_SPRMOD */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions + * @brief DATA EEPROM Programming functions + * +@verbatim + =============================================================================== + ##### DATA EEPROM Programming functions ##### + =============================================================================== + + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access + and Flash program erase control register access. + (#) Call the desired function to erase or program data. + (#) Call the HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access + and Flash program erase control register access(recommended + to protect the DATA_EEPROM against possible unwanted operation). + +@endverbatim + * @{ + */ + +/** + * @brief Unlocks the data memory and FLASH_PECR register access. + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void) +{ + if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + { + /* Unlocking the Data memory and FLASH_PECR register access*/ + FLASH->PEKEYR = FLASH_PEKEY1; + FLASH->PEKEYR = FLASH_PEKEY2; + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Locks the Data memory and FLASH_PECR register access. + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) +{ + /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ + SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK); + + return HAL_OK; +} + +/** + * @brief Erase a word in data memory. + * @param Address specifies the address to be erased. + * @param TypeErase Indicate the way to erase at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function + * must be called before. + * Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TYPEERASEDATA(TypeErase)); + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + if(TypeErase == FLASH_TYPEERASEDATA_WORD) + { + /* Write 00000000h to valid address in the data memory */ + *(__IO uint32_t *) Address = 0x00000000U; + } + + if(TypeErase == FLASH_TYPEERASEDATA_HALFWORD) + { + /* Write 0000h to valid address in the data memory */ + *(__IO uint16_t *) Address = (uint16_t)0x0000; + } + + if(TypeErase == FLASH_TYPEERASEDATA_BYTE) + { + /* Write 00h to valid address in the data memory */ + *(__IO uint8_t *) Address = (uint8_t)0x00; + } + + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program word at a specified address + * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function + * must be called before. + * Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @note The function @ref HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before + * this function to configure the Fixed Time Programming. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASHEx_Type_Program_Data + * @param Address specifie the address to be programmed. + * @param Data specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ + +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_TYPEPROGRAMDATA(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD) + { + /* Program word (32-bit) at a specified address.*/ + status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD) + { + /* Program halfword (16-bit) at a specified address.*/ + status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE) + { + /* Program byte (8-bit) at a specified address.*/ + status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE) + { + /*Program word (8-bit) at a specified address.*/ + status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) + { + /* Program halfword (16-bit) at a specified address.*/ + status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data); + } + else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD) + { + /* Program word (32-bit) at a specified address.*/ + status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data); + } + else + { + status = HAL_ERROR; + } + + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Enable DATA EEPROM fixed Time programming (2*Tprog). + * @retval None + */ +void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void) +{ + SET_BIT(FLASH->PECR, FLASH_PECR_FTDW); +} + +/** + * @brief Disables DATA EEPROM fixed Time programming (2*Tprog). + * @retval None + */ +void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) +{ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/* +============================================================================== + OPTIONS BYTES +============================================================================== +*/ +/** + * @brief Enables or disables the read out protection. + * @note To correctly run this function, the @ref HAL_FLASH_OB_Unlock() function + * must be called before. + * @param OB_RDP specifies the read protection level. + * This parameter can be: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Chip protection + * + * !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + + tmp1 = (uint32_t)(OB->RDP & FLASH_OBR_RDPRT); + + /* According to errata sheet, DocID022054 Rev 5, par2.1.5 + Before setting Level0 in the RDP register, check that the current level is not equal to Level0. + If the current level is not equal to Level0, Level0 can be activated. + If the current level is Level0 then the RDP register must not be written again with Level0. */ + + if ((tmp1 == OB_RDP_LEVEL_0) && (OB_RDP == OB_RDP_LEVEL_0)) + { + /*current level is Level0 then the RDP register must not be written again with Level0. */ + status = HAL_ERROR; + } + else + { +#if defined(FLASH_OBR_SPRMOD) + /* Mask SPRMOD bit */ + tmp3 = (uint32_t)(OB->RDP & FLASH_OBR_SPRMOD); +#endif + + /* calculate the option byte to write */ + tmp1 = (~((uint32_t)(OB_RDP | tmp3))); + tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* program read protection level */ + OB->RDP = tmp2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + } + + /* Return the Read protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH brownout reset threshold level Option Byte. + * @param OB_BOR Selects the brownout reset threshold level. + * This parameter can be one of the following values: + * @arg @ref OB_BOR_OFF BOR is disabled at power down, the reset is asserted when the VDD + * power supply reaches the PDR(Power Down Reset) threshold (1.5V) + * @arg @ref OB_BOR_LEVEL1 BOR Reset threshold levels for 1.7V - 1.8V VDD power supply + * @arg @ref OB_BOR_LEVEL2 BOR Reset threshold levels for 1.9V - 2.0V VDD power supply + * @arg @ref OB_BOR_LEVEL3 BOR Reset threshold levels for 2.3V - 2.4V VDD power supply + * @arg @ref OB_BOR_LEVEL4 BOR Reset threshold levels for 2.55V - 2.65V VDD power supply + * @arg @ref OB_BOR_LEVEL5 BOR Reset threshold levels for 2.8V - 2.9V VDD power supply + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0U, tmp1 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(OB_BOR)); + + /* Get the User Option byte register */ + tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16U); + + /* Calculate the option byte to write - [0xFFU | nUSER | 0x00U | USER]*/ + tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U; + tmp |= (OB_BOR | tmp1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write the BOR Option Byte */ + OB->USER = tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the Option Byte BOR Programming Status */ + return status; +} + +/** + * @brief Returns the FLASH User Option Bytes values. + * @retval The FLASH User Option Bytes. + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((FLASH->OBR & (FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + uint8_t rdp_level = (uint8_t)(FLASH->OBR & FLASH_OBR_RDPRT); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return (rdp_level); + } +} + +/** + * @brief Returns the FLASH BOR level. + * @retval The BOR level Option Bytes. + */ +static uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the BOR level */ + return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16U); +} + +/** + * @brief Write protects the desired pages of the first 64KB of the Flash. + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains WRP parameters. + * @param NewState new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval HAL_StatusTypeDef + */ +static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* WRP for sector between 0 to 31 */ + if (pOBInit->WRPSector0To31 != 0U) + { + FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState); + } + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) + + /* Pages for Cat3, Cat4 & Cat5 devices*/ + /* WRP for sector between 32 to 63 */ + if (pOBInit->WRPSector32To63 != 0U) + { + FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState); + } + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) + + /* Pages for devices with FLASH >= 256KB*/ + /* WRP for sector between 64 to 95 */ + if (pOBInit->WRPSector64To95 != 0U) + { + FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState); + } + +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) + + /* Pages for Cat5 devices*/ + /* WRP for sector between 96 to 127 */ + if (pOBInit->WRPSector96To127 != 0U) + { + FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState); + } + +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the write protection operation Status */ + return status; +} + +#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ + || defined(STM32L162xC) +/** + * @brief Enables the read/write protection (PCROP) of the desired + * sectors. + * @note This function can be used only for Cat2 & Cat3 devices + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains PCROP parameters. + * @param NewState new state of the specified FLASH Pages read/Write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState) +{ + HAL_StatusTypeDef status = HAL_OK; + FunctionalState pcropstate = DISABLE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* Invert state to use same function of WRP */ + if (NewState == DISABLE) + { + pcropstate = ENABLE; + } + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Pages for Cat2 devices*/ + /* PCROP for sector between 0 to 31 */ + if (pAdvOBInit->PCROPSector0To31 != 0U) + { + FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate); + } + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) + + /* Pages for Cat3 devices*/ + /* WRP for sector between 32 to 63 */ + if (pAdvOBInit->PCROPSector32To63 != 0U) + { + FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate); + } + +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the write protection operation Status */ + return status; +} +#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ + +/** + * @brief Write protects the desired pages of the first 128KB of the Flash. + * @param WRP1OrPCROP1 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 + * @param NewState new state of the specified FLASH Pages Write protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState) +{ + uint32_t wrp01data = 0U, wrp23data = 0U; + + uint32_t tmp1 = 0U, tmp2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WRP(WRP1OrPCROP1)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01)); + wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U | OB->WRP23))); + tmp1 = (uint32_t)(~(wrp01data) << 16U)|(wrp01data); + OB->WRP01 = tmp1; + + tmp2 = (uint32_t)(~(wrp23data) << 16U)|(wrp23data); + OB->WRP23 = tmp2; + } + else + { + wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01)); + wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U & OB->WRP23))); + + tmp1 = (uint32_t)((~wrp01data) << 16U)|(wrp01data); + OB->WRP01 = tmp1; + + tmp2 = (uint32_t)((~wrp23data) << 16U)|(wrp23data); + OB->WRP23 = tmp2; + } +} + +#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ + || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ + || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ + || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) +/** + * @brief Enable Write protects the desired pages of the second 128KB of the Flash. + * @note This function can be used only for Cat3, Cat4 & Cat5 devices. + * @param WRP2OrPCROP2 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 + * @param NewState new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState) +{ + uint32_t wrp45data = 0U, wrp67data = 0U; + + uint32_t tmp1 = 0U, tmp2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WRP(WRP2OrPCROP2)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45)); + wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U | OB->WRP67))); + tmp1 = (uint32_t)(~(wrp45data) << 16U)|(wrp45data); + OB->WRP45 = tmp1; + + tmp2 = (uint32_t)(~(wrp67data) << 16U)|(wrp67data); + OB->WRP67 = tmp2; + } + else + { + wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45)); + wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U & OB->WRP67))); + + tmp1 = (uint32_t)((~wrp45data) << 16U)|(wrp45data); + OB->WRP45 = tmp1; + + tmp2 = (uint32_t)((~wrp67data) << 16U)|(wrp67data); + OB->WRP67 = tmp2; + } +} +#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ + || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ + || defined(STM32L162xE) +/** + * @brief Enable Write protects the desired pages of the third 128KB of the Flash. + * @note This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD & Cat5 devices. + * @param WRP3 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 + * @param NewState new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState) +{ + uint32_t wrp89data = 0U, wrp1011data = 0U; + + uint32_t tmp1 = 0U, tmp2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WRP(WRP3)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89)); + wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16U | OB->WRP1011))); + tmp1 = (uint32_t)(~(wrp89data) << 16U)|(wrp89data); + OB->WRP89 = tmp1; + + tmp2 = (uint32_t)(~(wrp1011data) << 16U)|(wrp1011data); + OB->WRP1011 = tmp2; + } + else + { + wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89)); + wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16U & OB->WRP1011))); + + tmp1 = (uint32_t)((~wrp89data) << 16U)|(wrp89data); + OB->WRP89 = tmp1; + + tmp2 = (uint32_t)((~wrp1011data) << 16U)|(wrp1011data); + OB->WRP1011 = tmp2; + } +} +#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ + +#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ + || defined(STM32L152xDX) || defined(STM32L162xDX) +/** + * @brief Enable Write protects the desired pages of the Fourth 128KB of the Flash. + * @note This function can be used only for Cat5 & STM32L1xxDX devices. + * @param WRP4 specifies the address of the pages to be write protected. + * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 + * @param NewState new state of the specified FLASH Pages Wtite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState) +{ + uint32_t wrp1213data = 0U, wrp1415data = 0U; + + uint32_t tmp1 = 0U, tmp2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WRP(WRP4)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213)); + wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16U | OB->WRP1415))); + tmp1 = (uint32_t)(~(wrp1213data) << 16U)|(wrp1213data); + OB->WRP1213 = tmp1; + + tmp2 = (uint32_t)(~(wrp1415data) << 16U)|(wrp1415data); + OB->WRP1415 = tmp2; + } + else + { + wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213)); + wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16U & OB->WRP1415))); + + tmp1 = (uint32_t)((~wrp1213data) << 16U)|(wrp1213data); + OB->WRP1213 = tmp1; + + tmp2 = (uint32_t)((~wrp1415data) << 16U)|(wrp1415data); + OB->WRP1415 = tmp2; + } +} +#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param OB_IWDG Selects the WDG mode. + * This parameter can be one of the following values: + * @arg @ref OB_IWDG_SW Software WDG selected + * @arg @ref OB_IWDG_HW Hardware WDG selected + * @param OB_STOP Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg @ref OB_STOP_NORST No reset generated when entering in STOP + * @arg @ref OB_STOP_RST Reset generated when entering in STOP + * @param OB_STDBY Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg @ref OB_STDBY_NORST No reset generated when entering in STANDBY + * @arg @ref OB_STDBY_RST Reset generated when entering in STANDBY + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0U, tmp1 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Get the User Option byte register */ + tmp1 = OB->USER & ((~(FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U); + + /* Calculate the user option byte to write */ + tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16U); + tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write the User Option Byte */ + OB->USER = tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the Option Byte program Status */ + return status; +} + +#if defined(FLASH_OBR_nRST_BFB2) +/** + * @brief Configures to boot from Bank1 or Bank2. + * @param OB_BOOT select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg @ref OB_BOOT_BANK2 At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * @arg @ref OB_BOOT_BANK1 At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * For more information, please refer to AN2606 from www.st.com. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0U, tmp1 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_BOOT_BANK(OB_BOOT)); + + /* Get the User Option byte register and BOR Level*/ + tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16U); + + /* Calculate the option byte to write */ + tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U; + tmp |= (OB_BOOT | tmp1); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write the BOOT Option Byte */ + OB->USER = tmp; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Return the Option Byte program Status */ + return status; +} + +#endif /* FLASH_OBR_nRST_BFB2 */ + +/* +============================================================================== + DATA +============================================================================== +*/ + +/** + * @brief Write a Byte at a specified address in data memory. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. + * @note This function assumes that the is data word is already erased. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + uint32_t tmp = 0U, tmpaddr = 0U; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clear the FTDW bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); + +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + /* Possible only on Cat1 devices */ + if(Data != (uint8_t)0x00U) + { + /* If the previous operation is completed, proceed to write the new Data */ + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + tmpaddr = Address & 0xFFFFFFFCU; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); + /* Process Locked */ + __HAL_LOCK(&pFlash); + } +#else /*!Cat1*/ + /* If the previous operation is completed, proceed to write the new Data */ + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Writes a half word at a specified address in data memory. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. + * @note This function assumes that the is data word is already erased. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + uint32_t tmp = 0U, tmpaddr = 0U; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clear the FTDW bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); + +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + /* Possible only on Cat1 devices */ + if(Data != (uint16_t)0x0000U) + { + /* If the previous operation is completed, proceed to write the new data */ + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + if((Address & 0x3U) != 0x3U) + { + tmpaddr = Address & 0xFFFFFFFCU; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); + } + else + { + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U); + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U); + } + /* Process Locked */ + __HAL_LOCK(&pFlash); + } +#else /* !Cat1 */ + /* If the previous operation is completed, proceed to write the new data */ + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Programs a word at a specified address in data memory. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. + * @note This function assumes that the is data word is already erased. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clear the FTDW bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); + + /* If the previous operation is completed, proceed to program the new data */ + *(__IO uint32_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Write a Byte at a specified address in data memory without erase. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + uint32_t tmp = 0U, tmpaddr = 0U; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + if(Data != (uint8_t) 0x00U) + { + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + } + else + { + tmpaddr = Address & 0xFFFFFFFCU; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); + /* Process Locked */ + __HAL_LOCK(&pFlash); + } +#else /* Not Cat1*/ + *(__IO uint8_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Writes a half word at a specified address in data memory without erase. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + uint32_t tmp = 0U, tmpaddr = 0U; +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { +#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) + if(Data != (uint16_t)0x0000U) + { + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + if((Address & 0x3U) != 0x3U) + { + tmpaddr = Address & 0xFFFFFFFCU; + tmp = * (__IO uint32_t *) tmpaddr; + tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U))); + tmp &= ~tmpaddr; + status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); + status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); + } + else + { + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U); + HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U); + } + /* Process Locked */ + __HAL_LOCK(&pFlash); + } +#else /* Not Cat1*/ + *(__IO uint16_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); +#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ + } + /* Return the Write Status */ + return status; +} + +/** + * @brief Programs a word at a specified address in data memory without erase. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint32_t *)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + /* Return the Write Status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erases a specified page in program memory. + * @param PageAddress The page address in program memory to be erased. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Set the ERASE bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + /* Set PROG bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /* Write 00000000h to the first word of the program page to erase */ + *(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c new file mode 100644 index 0000000..a3b3d3d --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c @@ -0,0 +1,640 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_flash_ramfunc.c + * @author MCD Application Team + * @brief FLASH RAMFUNC driver. + * This file provides a Flash firmware functions which should be + * executed from internal SRAM + * + * @verbatim + + *** ARM Compiler *** + -------------------- + [..] RAM functions are defined using the toolchain options. + Functions that are be executed in RAM should reside in a separate + source module. Using the 'Options for File' dialog you can simply change + the 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + Options for Target' dialog. + + *** ICCARM Compiler *** + ----------------------- + [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + + *** GNU Compiler *** + -------------------- + [..] RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". + +@endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC + * @brief FLASH functions executed from RAM + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions + * @{ + */ + +static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout); +static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void); + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions + * +@verbatim + =============================================================================== + ##### ramfunc functions ##### + =============================================================================== + [..] + This subsection provides a set of functions that should be executed from RAM + transfers. + +@endverbatim + * @{ + */ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions + * @{ + */ + +/** + * @brief Enable the power down mode during RUN mode. + * @note This function can be used only when the user code is running from Internal SRAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void) +{ + /* Enable the Power Down in Run mode*/ + __HAL_FLASH_POWER_DOWN_ENABLE(); + + return HAL_OK; +} + +/** + * @brief Disable the power down mode during RUN mode. + * @note This function can be used only when the user code is running from Internal SRAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) +{ + /* Disable the Power Down in Run mode*/ + __HAL_FLASH_POWER_DOWN_DISABLE(); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions + * +@verbatim +@endverbatim + * @{ + */ + +#if defined(FLASH_PECR_PARALLBANK) +/** + * @brief Erases a specified 2 pages in program memory in parallel. + * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. + * To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * @param Page_Address1: The page address in program memory to be erased in + * the first Bank (BANK1). This parameter should be between FLASH_BASE + * and FLASH_BANK1_END. + * @param Page_Address2: The page address in program memory to be erased in + * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE + * and FLASH_BANK2_END. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Proceed to erase the page */ + SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /* Write 00000000h to the first word of the first program page to erase */ + *(__IO uint32_t *)Page_Address1 = 0x00000000U; + /* Write 00000000h to the first word of the second program page to erase */ + *(__IO uint32_t *)Page_Address2 = 0x00000000U; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + } + /* Return the Erase Status */ + return status; +} + +/** + * @brief Program 2 half pages in program memory in parallel (half page size is 32 Words). + * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. + * @param Address1: specifies the first address to be written in the first bank + * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE). + * @param pBuffer1: pointer to the buffer containing the data to be written + * to the first half page in the first bank. + * @param Address2: specifies the second address to be written in the second bank + * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE). + * @param pBuffer2: pointer to the buffer containing the data to be written + * to the second half page in the second bank. + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * @note Half page write is possible only from SRAM. + * @note If there are more than 32 words to write, after 32 words another + * Half Page programming operation starts and has to be finished. + * @note A half page is written to the program memory only if the first + * address to load is the start address of a half page (multiple of 128 + * bytes) and the 31 remaining words to load are in the same half page. + * @note During the Program memory half page write all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @note If a PGAERR is set during a Program memory half page write, the + * complete write operation is aborted. Software should then reset the + * FPRG and PROG/DATA bits and restart the write operation from the + * beginning. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) +{ + uint32_t primask_bit; + uint32_t count = 0U; + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Disable all IRQs */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Proceed to program the new half page */ + SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /* Write the first half page directly with 32 different words */ + while(count < 32U) + { + *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1; + pBuffer1++; + count ++; + } + + /* Write the second half page directly with 32 different words */ + count = 0U; + while(count < 32U) + { + *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2; + pBuffer2++; + count ++; + } + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + + /* Enable IRQs */ + __set_PRIMASK(primask_bit); + } + + /* Return the Write Status */ + return status; +} +#endif /* FLASH_PECR_PARALLBANK */ + +/** + * @brief Program a half page in program memory. + * @param Address specifies the address to be written. + * @param pBuffer pointer to the buffer containing the data to be written to + * the half page. + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @note Half page write is possible only from SRAM. + * @note If there are more than 32 words to write, after 32 words another + * Half Page programming operation starts and has to be finished. + * @note A half page is written to the program memory only if the first + * address to load is the start address of a half page (multiple of 128 + * bytes) and the 31 remaining words to load are in the same half page. + * @note During the Program memory half page write all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @note If a PGAERR is set during a Program memory half page write, the + * complete write operation is aborted. Software should then reset the + * FPRG and PROG/DATA bits and restart the write operation from the + * beginning. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) +{ + uint32_t primask_bit; + uint32_t count = 0U; + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Disable all IRQs */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Proceed to program the new half page */ + SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + /* Write one half page directly with 32 different words */ + while(count < 32U) + { + *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer; + pBuffer++; + count ++; + } + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the write operation is completed, disable the PROG and FPRG bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + + /* Enable IRQs */ + __set_PRIMASK(primask_bit); + } + + /* Return the Write Status */ + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH errors flag. + * @param Error pointer is the error value. It can be a mixed of: +@if STM32L100xB +@elif STM32L100xBA + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) +@elif STM32L151xB +@elif STM32L151xBA + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) +@elif STM32L152xB +@elif STM32L152xBA + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) +@elif STM32L100xC + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) + * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error +@elif STM32L151xC + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) + * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error +@elif STM32L152xC + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) + * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error +@elif STM32L162xC + * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) + * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error +@else + * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error +@endif + * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag + * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag + * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag + * @retval HAL Status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error) +{ + *Error = pFlash.ErrorCode; + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions + * + * @{ + */ + +/** + * @brief Erase a double word in data memory. + * @param Address specifies the address to be erased. + * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function + * must be called before. + * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @note Data memory double word erase is possible only from SRAM. + * @note A double word is erased to the data memory only if the first address + * to load is the start address of a double word (multiple of 8 bytes). + * @note During the Data memory double word erase, all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @retval HAL status + */ + +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address) +{ + uint32_t primask_bit; + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Disable all IRQs */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* If the previous operation is completed, proceed to erase the next double word */ + /* Set the ERASE bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + /* Set DATA bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_DATA); + + /* Write 00000000h to the 2 words to erase */ + *(__IO uint32_t *)Address = 0x00000000U; + Address += 4U; + *(__IO uint32_t *)Address = 0x00000000U; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the ERASE and DATA bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA); + + /* Enable IRQs */ + __set_PRIMASK(primask_bit); + + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Write a double word in data memory without erase. + * @param Address specifies the address to be written. + * @param Data specifies the data to be written. + * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function + * must be called before. + * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access + * and Flash program erase control register access(recommended to protect + * the DATA_EEPROM against possible unwanted operation). + * @note Data memory double word write is possible only from SRAM. + * @note A data memory double word is written to the data memory only if the + * first address to load is the start address of a double word (multiple + * of double word). + * @note During the Data memory double word write, all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data) +{ + uint32_t primask_bit; + HAL_StatusTypeDef status = HAL_OK; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Disable all IRQs */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* If the previous operation is completed, proceed to program the new data*/ + SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + SET_BIT(FLASH->PECR, FLASH_PECR_DATA); + + /* Write the 2 words */ + *(__IO uint32_t *)Address = (uint32_t) Data; + Address += 4U; + *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the write operation is completed, disable the FPRG and DATA bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA); + + /* Enable IRQs */ + __set_PRIMASK(primask_bit); + } + + /* Return the Write Status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_RAMFUNC_Private_Functions + * @{ + */ + +/** + * @brief Set the specific FLASH error flag. + * @retval HAL Status + */ +static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void) +{ + uint32_t flags = 0U; + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + flags |= FLASH_FLAG_WRPERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + flags |= FLASH_FLAG_PGAERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + flags |= FLASH_FLAG_OPTVERR; + } + +#if defined(FLASH_SR_RDERR) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + flags |= FLASH_FLAG_RDERR; + } +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR; + flags |= FLASH_FLAG_OPTVERRUSR; + } +#endif /* FLASH_SR_OPTVERRUSR */ + + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); + + return HAL_OK; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operationtimeout + * @retval HAL status + */ +static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) + { + Timeout--; + } + + if(Timeout == 0x00U) + { + return HAL_TIMEOUT; + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || +#if defined(FLASH_SR_RDERR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || +#endif /* FLASH_SR_RDERR */ +#if defined(FLASH_SR_OPTVERRUSR) + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || +#endif /* FLASH_SR_OPTVERRUSR */ + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + { + /*Save the error code*/ + FLASHRAM_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c new file mode 100644 index 0000000..9e75b40 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c @@ -0,0 +1,546 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral s alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 28 edge detectors + (depending on products 16 lines are connected to GPIO) for generating event/interrupt + requests (each input line can be independently configured to select the type + (interrupt or event) and the corresponding trigger event (rising or falling or both). + Each line can also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure, + the speed is configurable: Low, Medium and High. + (++) If alternate mode is selected, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also + recommended to use it to unconfigure pin which was used as an external interrupt + or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG + registers. + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants + * @{ + */ +#define GPIO_NUMBER (16U) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00; + uint32_t iocurrent = 0x00; + uint32_t temp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1U << position); + + if (iocurrent) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + SET_BIT(temp, GPIO_Init->Speed << (position * 2)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + /* Identify AFRL or AFRH register based on IO position*/ + temp = GPIOx->AFR[position >> 3]; + CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); + SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); + GPIOx->AFR[position >> 3] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); + SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + SET_BIT(temp, iocurrent); + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + SET_BIT(temp, iocurrent); + } + EXTI->FTSR = temp; + + temp = EXTI->EMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + SET_BIT(temp, iocurrent); + } + EXTI->EMR = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + CLEAR_BIT(temp, (uint32_t)iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + SET_BIT(temp, iocurrent); + } + EXTI->IMR = temp; + } + } + + position++; + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00; + uint32_t iocurrent = 0x00; + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1U << position); + + if (iocurrent) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2]; + tmp &= ((0x0FU) << (4 * (position & 0x03))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); + CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); + + tmp = (0x0FU) << (4 * (position & 0x03)); + CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); + + /* Configure the default Alternate Function in current IO */ + CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ; + /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ + CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2)); + + /* Configure the default value IO Output Type */ + CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + } +} + +/** + * @brief Toggles the specified GPIO pin + * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices + * @param GPIO_Pin specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, +* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. +* @note The configuration of the locked GPIO pins can no longer be modified +* until the next reset. +* @note Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8 +* depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i]. +* GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8]. +* It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also +* GPIOx_OTYPER[i-8]. +* Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15, +* you must call also HAL_GPIO_LockPin with GPIO_Pin - 8. +* (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding +* GPIO_PIN_0 to GPIO_PIN_7). +* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices +* @param GPIO_Pin Specifies the port bit to be locked. +* This parameter can be any combination of GPIO_PIN_x where x can be (0..15). +* @retval None +*/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + SET_BIT(tmp, GPIO_Pin); + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* Read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c new file mode 100644 index 0000000..c3a342f --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c @@ -0,0 +1,650 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @note Before calling this function, the VOS[1:0] bits should be configured + * to "10" and the system frequency has to be configured accordingly. + * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() + * function. + * @note ULP and FWU bits are not reset by this function. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers ). + * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers). + * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) The PVD can use an external input analog voltage (PVD_IN) which is compared + internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode + when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). + + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There are two or three WakeUp pins: + WakeUp Pin 1 on PA.00. + WakeUp Pin 2 on PC.13. + WakeUp Pin 3 on PE.06. : Only on product with GPIOE available + + [..] + *** Main and Backup Regulators configuration *** + ================================================ + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() + macro which configure VOS bit in PWR_CR register: + (++) When this bit is set (Regulator voltage output Scale 1 mode selected) + the System frequency can go up to 32 MHz. + (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) + the System frequency can go up to 16 MHz. + (++) When this bit is reset (Regulator voltage output Scale 3 mode selected) + the System frequency can go up to 4.2 MHz. + + Refer to the datasheets for more details. + + *** Low Power modes configuration *** + ===================================== + [..] + The device features 5 low-power modes: + (+) Low power run mode: regulator in low power mode, limited clock frequency, + limited number of peripherals running. + (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running. + (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, + limited number of peripherals running, regulator in low power mode. + (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. + (+) Standby mode: VCORE domain powered off + + *** Low power run mode *** + ========================= + [..] + To further reduce the consumption when the system is in Run mode, the regulator can be + configured in low power mode. In this mode, the system frequency should not exceed + MSI frequency range1. + In Low power run mode, all I/O pins keep the same state as in Run mode. + + (+) Entry: + (++) VCORE in range2 + (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1. + (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() + function. + (+) Exit: + (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode() + function. + (++) Increase the system frequency if needed. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Low power sleep mode *** + ============================ + [..] + (+) Entry: + The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. + This reduces power consumption but increases the wake-up time. + + (+) Exit: + (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt + acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device + from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode, + the MCU exits Sleep mode as soon as an event occurs. + + *** Stop mode *** + ================= + [..] + The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral + clock gating. The voltage regulator can be configured either in normal or low-power mode. + In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and + the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. + To get the lowest consumption in Stop mode, the internal Flash memory also enters low + power mode. When the Flash memory is in power-down mode, an additional startup delay is + incurred when waking up from Stop mode. + To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature + sensor can be switched off before entering Stop mode. They can be switched on again by + software after exiting Stop mode using the ULP bit in the PWR_CR register. + In Stop mode, all I/O pins keep the same state as in Run mode. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI ) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (+) Exit: + (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock. + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based on the + Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is + consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are + also switched off. SRAM and register contents are lost except for the RTC registers, RTC + backup registers and Standby circuitry. + + To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature + sensor can be switched off before entering the Standby mode. They can be switched + on again by software after exiting the Standby mode. + function. + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: + (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt + or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() + function + (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() + and HAL_RTC_SetTime() functions. + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and + Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT() + or HAL_RTCEx_SetTimeStamp_IT() functions. + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: + (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and + Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer() + function. + + (+) RTC auto-wakeup (AWU) from the Standby mode + (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: + (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function. + (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() + and HAL_RTC_SetTime() functions. + (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it + is necessary to: + (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to + detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() + or HAL_RTCEx_SetTamper_IT()functions. + (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: + (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup + event, it is necessary to: + (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the + selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using + the COMP functions. + (+++) Configure the comparator to generate the event. + + + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator: Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Additional NOP() instruction to ensure that all pending instructions are flushed before entering sleep mode */ + __NOP(); +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by using an interrupt or a wakeup event, + * MSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator: Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - WKUP pin 1 (PA0) if enabled. + * - WKUP pin 2 (PC13) if enabled. + * - WKUP pin 3 (PE6) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enables CORTEX M3 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M3 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c new file mode 100644 index 0000000..b1e4aab --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c @@ -0,0 +1,158 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR & PWR_CR_VOS); +} + + +/** + * @brief Enables the Fast WakeUp from Ultra Low Power mode. + * @note This bit works in conjunction with ULP bit. + * Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when + * exiting from low power mode. + * @retval None + */ +void HAL_PWREx_EnableFastWakeUp(void) +{ + /* Enable the fast wake up */ + *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Fast WakeUp from Ultra Low Power mode. + * @retval None + */ +void HAL_PWREx_DisableFastWakeUp(void) +{ + /* Disable the fast wake up */ + *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the Ultra Low Power mode + * @retval None + */ +void HAL_PWREx_EnableUltraLowPower(void) +{ + /* Enable the Ultra Low Power mode */ + *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Ultra Low Power mode + * @retval None + */ +void HAL_PWREx_DisableUltraLowPower(void) +{ + /* Disable the Ultra Low Power mode */ + *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enters the Low Power Run mode. + * @note Low power run mode can only be entered when VCORE is in range 2. + * In addition, the dynamic voltage scaling must not be used when Low + * power run mode is selected. Only Stop and Sleep modes with regulator + * configured in Low power mode is allowed when Low power run mode is + * selected. + * @note In Low power run mode, all I/O pins keep the same state as in Run mode. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + /* Enters the Low Power Run mode */ + *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE; + *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE; +} + +/** + * @brief Exits the Low Power Run mode. + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + /* Exits the Low Power Run mode */ + *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE; + *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE; + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c new file mode 100644 index 0000000..c52899b --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c @@ -0,0 +1,1394 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from multispeed internal oscillator clock + (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at MSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + (*) SDIO only for STM32L1xxxD devices + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz, + 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. + + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 32 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to MSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M3 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE, + HSE or PLL clock (through a configurable prescaler) on PA8 pin. + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() + macros to configure this clock. + (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 16. You have to use __HAL_RCC_LCD_CONFIG() + macros to configure this clock. + (+@) USB OTG FS: USB OTG FS require a frequency equal to 48 MHz + to work correctly. This clock is derived of the main PLL through PLL Multiplier. + + (+@) IWDG clock which is always the LSI clock. + + (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz + and PCLK1 32 MHz. Depending on the device voltage range, the maximum + frequency should be adapted accordingly. + @endverbatim + * @{ + */ + +/* + Additional consideration on the HCLK based on Latency settings: + +----------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |------------------------------------------------------| + | | voltage range 1 | voltage range 2 | voltage range 3 | + | | 1.8 V | 1.5 V | 1.2 V | + |---------------|------------------|-----------------|-----------------| + |0WS(1CPU cycle)| 0 < HCLK <= 16 | 0 < HCLK <= 8 | 0 < HCLK <= 2 | + |---------------|------------------|-----------------|-----------------| + |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 | + +----------------------------------------------------------------------+ + + The following table gives the different clock source frequencies depending on the product + voltage range: + +------------------------------------------------------------------------------------------+ + | Product voltage | Clock frequency | + | |------------------|-----------------------------|-----------------------| + | range | MSI | HSI | HSE | PLL | + |-----------------|---------|--------|-----------------------------|-----------------------| + | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) | 32 MHz | + | | | | or 24 MHz (crystal) | (PLLVCO max = 96 MHz) | + |-----------------|---------|--------|-----------------------------|-----------------------| + | Range 2 (1.5 V) | 4.2 MHz | 16 MHz | 16 MHz | 16 MHz | + | | | | | (PLLVCO max = 48 MHz) | + |-----------------|---------|--------|-----------------------------|-----------------------| + | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz | + | | | | | (PLLVCO max = 24 MHz) | + +------------------------------------------------------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - MSI ON and used as system clock source + * - HSI, HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Set MSIClockRange, HSITRIM and MSITRIM bits to the reset values */ + MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSITRIM | RCC_ICSCR_HSITRIM | RCC_ICSCR_MSIRANGE), \ + ((RCC_MSICALIBRATION_DEFAULT << RCC_ICSCR_MSITRIM_Pos) | (RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos) | RCC_ICSCR_MSIRANGE_5)); + + /* Set MSION bit */ + SET_BIT(RCC->CR, RCC_CR_MSION); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Switch SYSCLK to MSI*/ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); + + /* Wait till MSI as SYSCLK status is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = MSI_VALUE; + + /* Configure the source of time base considering new system clock settings */ + status = HAL_InitTick(uwTickPrio); + if(status != HAL_OK) + { + return status; + } + + /* Reset HSION, HSEON, CSSON & PLLON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is not ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + /* Clear all flags */ +#if defined(RCC_LSECSS_SUPPORT) + WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC | RCC_CIR_LSECSSC | RCC_CIR_CSSC); +#else + WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC | RCC_CIR_CSSC); +#endif + + /* Clear all reset flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + HAL_StatusTypeDef status; + uint32_t sysclk_source, pll_config; + + /* Check the parameters */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- MSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + { + /* When the MSI is used as system clock it will not be disabled */ + if(sysclk_source == RCC_CFGR_SWS_MSI) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration and MSI range change are allowed */ + else + { + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + { + /* First increase number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + + /* Decrease number of wait states update if necessary */ + if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + if(status != HAL_OK) + { + return status; + } + } + } + else + { + /* Check MSI State */ + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + + /* Check the MSI State */ + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + { + /* Enable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Check MSICalibrationValue and MSIClockRange input parameters */ + assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + + } + else + { + /* Disable the Multi Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLMUL, + RCC_OscInitStruct->PLL.PLLDIV); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The MSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + HAL_StatusTypeDef status; + + /* Check the parameters */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* MSI is selected as System Clock Source */ + else + { + /* Check the MSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + { + return HAL_ERROR; + } + } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + { + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + status = HAL_InitTick(uwTickPrio); + + return status; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + gpio.Alternate = GPIO_AF0_MCO; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is MSI, function returns a value based on MSI + * Value as defined by the MSI range. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + } + sysclockfreq = pllvco; + break; + } + case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + default: /* MSI used as system clock */ + { + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI; + + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); + + /* Get the MSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION) + { + RCC_OscInitStruct->MSIState = RCC_MSI_ON; + } + else + { + RCC_OscInitStruct->MSIState = RCC_MSI_OFF; + } + + RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); + RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE)); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = __HAL_FLASH_GET_LATENCY(); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ +/** + * @brief Update number of Flash wait states in line with MSI range and current + voltage range + * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) +{ + uint32_t vos; + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + + /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) + { + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) + { + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + } + else + { + __HAL_RCC_PWR_CLK_ENABLE(); + vos = READ_BIT(PWR->CR, PWR_CR_VOS); + __HAL_RCC_PWR_CLK_DISABLE(); + } + + /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ + if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) + { + latency = FLASH_LATENCY_1; /* 1WS */ + } + } + + __HAL_FLASH_SET_LATENCY(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != latency) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c new file mode 100644 index 0000000..b6cbb68 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c @@ -0,0 +1,447 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock). + * @retval HAL status + * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig() + * to possibly update HSE divider. + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart; + uint32_t temp_reg; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) +#if defined(LCD) + || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) +#endif /* LCD */ + ) + { + /* check for RTC Parameters used to output RTCCLK */ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + } + +#if defined(LCD) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) + { + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection)); + } +#endif /* LCD */ + + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ + temp_reg = (RCC->CR & RCC_CR_RTCPRE); + if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) +#if defined (LCD) + || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) +#endif /* LCD */ + ) + { /* Check HSE State */ + if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + /* To update HSE divider, first switch-OFF HSE clock oscillator*/ + return HAL_ERROR; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); + + if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ + && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#if defined(LCD) + || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \ + && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) +#endif /* LCD */ + )) + { + /* Store the content of CSR register before the reset of Backup Domain */ + temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of CSR register */ + RCC->CSR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } +#if defined(LCD) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) + { + __HAL_RCC_LCD_CONFIG(PeriphClkInit->LCDClockSelection); + } +#endif /* LCD */ + + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + return HAL_OK; +} + +/** + * @brief Get the PeriphClkInit according to the internal RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t srcclk; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; +#if defined(LCD) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; +#endif /* LCD */ + + /* Get the RTC/LCD configuration -----------------------------------------------*/ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2) + { + /* Source clock is LSE or LSI*/ + PeriphClkInit->RTCClockSelection = srcclk; + } + else + { + /* Source clock is HSE. Need to get the prescaler value*/ + PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); + } +#if defined(LCD) + PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; +#endif /* LCD */ +} + +/** + * @brief Return the peripheral clock frequency + * @note Return 0 if peripheral clock is unknown + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*) + * @note (*) means that this peripheral is not present on all the devices + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0; + uint32_t srcclk; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: +#if defined(LCD) + case RCC_PERIPHCLK_LCD: +#endif /* LCD */ + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready if RTC clock selection is LSE */ + if (srcclk == RCC_RTCCLKSOURCE_LSE) + { + if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)) + { + frequency = LSE_VALUE; + } + } + /* Check if LSI is ready if RTC clock selection is LSI */ + else if (srcclk == RCC_RTCCLKSOURCE_LSI) + { + if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) + { + frequency = LSI_VALUE; + } + } + /* Check if HSE is ready and if RTC clock selection is HSE */ + else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + /* Get the current HSE clock divider */ + switch (__HAL_RCC_GET_RTC_HSE_PRESCALER()) + { + case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ + { + frequency = HSE_VALUE / 16U; + break; + } + case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ + { + frequency = HSE_VALUE / 8U; + break; + } + case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ + { + frequency = HSE_VALUE / 4U; + break; + } + default: /* HSE DIV2 has been selected */ + { + frequency = HSE_VALUE / 2U; + break; + } + } + } + } + else + { + /* No clock source, frequency default init at 0 */ + } + break; + } + + default: + break; + } + + return(frequency); +} + +#if defined(RCC_LSECSS_SUPPORT) +/** + * @brief Enables the LSE Clock Security System. + * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied + * to the RTC but no hardware action is made to the registers. + * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup + * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104). + * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator + * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with + * RTCSEL), or take any required action to secure the application. + * @note LSE CSS available only for high density and medium+ devices + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the LSE Clock Security System. + * @note Once enabled this bit cannot be disabled, except after an LSE failure detection + * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit. + * Reset by power on reset and RTC software reset (RTCRST bit). + * @note LSE CSS available only for high density and medium+ devices + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + /* Disable LSE CSS */ + *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE; + + /* Disable LSE CSS IT */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +} + +/** + * @brief Enable the LSE Clock Security System IT & corresponding EXTI line. + * @note LSE Clock Security System IT is mapped on RTC EXTI line 19 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 19 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} +#endif /* RCC_LSECSS_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c new file mode 100644 index 0000000..13af2fb --- /dev/null +++ b/TP4_INIT_TFT/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c @@ -0,0 +1,3962 @@ +/** + ****************************************************************************** + * @file stm32l1xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + + [..] + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + + @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l1xx_hal.h" + +/** @addtogroup STM32L1xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100U +#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 us */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + /* TI mode is not supported on all devices in stm32l1xx series. + TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + } +#if (USE_SPI_CRC != 0U) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.DataSize & SPI_CR1_DFF) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + +#if defined(SPI_CR2_FRF) + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); +#else + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE)); +#endif /* SPI_CR2_FRF */ + +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t initial_TxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + initial_TxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms + * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint16_t initial_TxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + /* Read CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + /* Clear CRC Flag */ + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size amount of data elements (u8 or u16) to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + /* Check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size amount of data elements (u8 or u16) to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + + /* Check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); +#if defined(SPI_CR2_FRF) + __HAL_SPI_CLEAR_FREFLAG(hspi); +#endif /* SPI_CR2_FRF */ + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); +#if defined(SPI_CR2_FRF) + __HAL_SPI_CLEAR_FREFLAG(hspi); +#endif /* SPI_CR2_FRF */ + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->State = HAL_SPI_STATE_READY; + return errorcode; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ +#if defined(SPI_CR2_FRF) + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) +#else + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)) + && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) +#endif /* SPI_CR2_FRF */ + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + { + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; + } + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ +#if defined(SPI_CR2_FRF) + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } +#endif /* SPI_CR2_FRF */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + __IO uint32_t count; + + hspi->hdmatx->XferAbortCallback = NULL; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); +#if defined(SPI_CR2_FRF) + __HAL_SPI_CLEAR_FREFLAG(hspi); +#endif /* SPI_CR2_FRF */ + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Check Busy flag */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); +#if defined(SPI_CR2_FRF) + __HAL_SPI_CLEAR_FREFLAG(hspi); +#endif /* SPI_CR2_FRF */ + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8bit mode */ + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + + /* Check end of the reception */ + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + /* Check the end of the transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + { + tmp_timeout = 0U; + } + count--; + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Wait the RXNE reset */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + } + else + { + /* Wait the RXNE reset */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Timeout in us */ + __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer + * If Timeout is reached, the transfer is considered as finish. + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + { + break; + } + count--; + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + } + + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle abort a Rx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Flush Data Register by a blank read */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.c b/TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.c new file mode 100644 index 0000000..598064d --- /dev/null +++ b/TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.c @@ -0,0 +1,1065 @@ +/************************************************************************ +* TITLE: fonc_tft.c +* AUTHOR: +* DESCRIPTION: fonction pour afficheur graphique TFT ST7735 +* VERSION : +* +************************************************************************/ + + + +/* INCLUDE *************************************************************/ +#include "main.h" + +extern SPI_HandleTypeDef hspi1; +#include "stm32l1xx_hal_gpio.h" +#include "stm32l1xx_hal_spi.h" + +#include "fonc_tft.h" + +/* DEFINE **************************************************************/ +#define pgm_read_byte(addr) (*(const unsigned char *)(addr)) +#define pgm_read_word(addr) (*(const unsigned short *)(addr)) + + +// some flags for initR() :( +#define INITR_GREENTAB 0x0 +#define INITR_REDTAB 0x1 +#define INITR_BLACKTAB 0x2 + +#define INITR_18GREENTAB INITR_GREENTAB +#define INITR_18REDTAB INITR_REDTAB +#define INITR_18BLACKTAB INITR_BLACKTAB +#define INITR_144GREENTAB 0x1 + +// dimension TFT display +#define ST7735_TFTWIDTH 128 // Width TFT display +#define ST7735_TFTHEIGHT_18 160 // Heigt TFT 1.8" display + +// intruction TFT display +#define ST7735_NOP 0x00 +#define ST7735_SWRESET 0x01 +#define ST7735_RDDID 0x04 +#define ST7735_RDDST 0x09 + +#define ST7735_SLPIN 0x10 +#define ST7735_SLPOUT 0x11 +#define ST7735_PTLON 0x12 +#define ST7735_NORON 0x13 + +#define ST7735_INVOFF 0x20 +#define ST7735_INVON 0x21 +#define ST7735_DISPOFF 0x28 +#define ST7735_DISPON 0x29 +#define ST7735_CASET 0x2A +#define ST7735_RASET 0x2B +#define ST7735_RAMWR 0x2C +#define ST7735_RAMRD 0x2E + +#define ST7735_PTLAR 0x30 +#define ST7735_COLMOD 0x3A +#define ST7735_MADCTL 0x36 + +#define ST7735_FRMCTR1 0xB1 +#define ST7735_FRMCTR2 0xB2 +#define ST7735_FRMCTR3 0xB3 +#define ST7735_INVCTR 0xB4 +#define ST7735_DISSET5 0xB6 + +#define ST7735_PWCTR1 0xC0 +#define ST7735_PWCTR2 0xC1 +#define ST7735_PWCTR3 0xC2 +#define ST7735_PWCTR4 0xC3 +#define ST7735_PWCTR5 0xC4 +#define ST7735_VMCTR1 0xC5 + +#define ST7735_RDID1 0xDA +#define ST7735_RDID2 0xDB +#define ST7735_RDID3 0xDC +#define ST7735_RDID4 0xDD + +#define ST7735_PWCTR6 0xFC + +#define ST7735_GMCTRP1 0xE0 +#define ST7735_GMCTRN1 0xE1 + +/* VARIABLE ************************************************************/ + + +/* CONSTANTE ***********************************************************/ + +/* initialization commands and arguments for TFT controller */ +// commands and arguments are organized in these tables +// function commandList tables read theses tables +#define DELAY 0x80 +/*static const uint8_t Bcmd[] = { // Initialization commands for 7735B screens + 18, // 18 commands in list: + ST7735_SWRESET, DELAY, // 1: Software reset, no args, w/delay + 50, // 50 ms delay + ST7735_SLPOUT , DELAY, // 2: Out of sleep mode, no args, w/delay + 255, // 255 = 500 ms delay + ST7735_COLMOD , 1+DELAY, // 3: Set color mode, 1 arg + delay: + 0x05, // 16-bit color + 10, // 10 ms delay + ST7735_FRMCTR1, 3+DELAY, // 4: Frame rate control, 3 args + delay: + 0x00, // fastest refresh + 0x06, // 6 lines front porch + 0x03, // 3 lines back porch + 10, // 10 ms delay + ST7735_MADCTL , 1 , // 5: Memory access ctrl (directions), 1 arg: + 0x08, // Row addr/col addr, bottom to top refresh + ST7735_DISSET5, 2 , // 6: Display settings #5, 2 args, no delay: + 0x15, // 1 clk cycle nonoverlap, 2 cycle gate + // rise, 3 cycle osc equalize + 0x02, // Fix on VTL + ST7735_INVCTR , 1 , // 7: Display inversion control, 1 arg: + 0x0, // Line inversion + ST7735_PWCTR1 , 2+DELAY, // 8: Power control, 2 args + delay: + 0x02, // GVDD = 4.7V + 0x70, // 1.0uA + 10, // 10 ms delay + ST7735_PWCTR2 , 1 , // 9: Power control, 1 arg, no delay: + 0x05, // VGH = 14.7V, VGL = -7.35V + ST7735_PWCTR3 , 2 , // 10: Power control, 2 args, no delay: + 0x01, // Opamp current small + 0x02, // Boost frequency + ST7735_VMCTR1 , 2+DELAY, // 11: Power control, 2 args + delay: + 0x3C, // VCOMH = 4V + 0x38, // VCOML = -1.1V + 10, // 10 ms delay + ST7735_PWCTR6 , 2 , // 12: Power control, 2 args, no delay: + 0x11, 0x15, + ST7735_GMCTRP1,16 , // 13: Magical unicorn dust, 16 args, no delay: + 0x09, 0x16, 0x09, 0x20, // (seriously though, not sure what + 0x21, 0x1B, 0x13, 0x19, // these config values represent) + 0x17, 0x15, 0x1E, 0x2B, + 0x04, 0x05, 0x02, 0x0E, + ST7735_GMCTRN1,16+DELAY, // 14: Sparkles and rainbows, 16 args + delay: + 0x0B, 0x14, 0x08, 0x1E, // (ditto) + 0x22, 0x1D, 0x18, 0x1E, + 0x1B, 0x1A, 0x24, 0x2B, + 0x06, 0x06, 0x02, 0x0F, + 10, // 10 ms delay + ST7735_CASET , 4 , // 15: Column addr set, 4 args, no delay: + 0x00, 0x02, // XSTART = 2 + 0x00, 0x81, // XEND = 129 + ST7735_RASET , 4 , // 16: Row addr set, 4 args, no delay: + 0x00, 0x02, // XSTART = 1 + 0x00, 0x81, // XEND = 160 + ST7735_NORON , DELAY, // 17: Normal display on, no args, w/delay + 10, // 10 ms delay + ST7735_DISPON , DELAY, // 18: Main screen turn on, no args, w/delay + 255 }; // 255 = 500 ms delay +*/ +static const uint8_t Rcmd1[] = { // Init for 7735R, part 1 (red or green tab) + 15, // 15 commands in list: + ST7735_SWRESET, DELAY, // 1: Software reset, 0 args, w/delay + 150, // 150 ms delay + ST7735_SLPOUT , DELAY, // 2: Out of sleep mode, 0 args, w/delay + 255, // 500 ms delay + ST7735_FRMCTR1, 3 , // 3: Frame rate ctrl - normal mode, 3 args: + 0x01, 0x2C, 0x2D, // Rate = fosc/(1x2+40) * (LINE+2C+2D) + ST7735_FRMCTR2, 3 , // 4: Frame rate control - idle mode, 3 args: + 0x01, 0x2C, 0x2D, // Rate = fosc/(1x2+40) * (LINE+2C+2D) + ST7735_FRMCTR3, 6 , // 5: Frame rate ctrl - partial mode, 6 args: + 0x01, 0x2C, 0x2D, // Dot inversion mode + 0x01, 0x2C, 0x2D, // Line inversion mode + ST7735_INVCTR , 1 , // 6: Display inversion ctrl, 1 arg, no delay: + 0x07, // No inversion + ST7735_PWCTR1 , 3 , // 7: Power control, 3 args, no delay: + 0xA2, + 0x02, // -4.6V + 0x84, // AUTO mode + ST7735_PWCTR2 , 1 , // 8: Power control, 1 arg, no delay: + 0xC5, // VGH25 = 2.4C VGSEL = -10 VGH = 3 * AVDD + ST7735_PWCTR3 , 2 , // 9: Power control, 2 args, no delay: + 0x0A, // Opamp current small + 0x00, // Boost frequency + ST7735_PWCTR4 , 2 , // 10: Power control, 2 args, no delay: + 0x8A, // BCLK/2, Opamp current small & Medium low + 0x2A, + ST7735_PWCTR5 , 2 , // 11: Power control, 2 args, no delay: + 0x8A, 0xEE, + ST7735_VMCTR1 , 1 , // 12: Power control, 1 arg, no delay: + 0x0E, + ST7735_INVOFF , 0 , // 13: Don't invert display, no args, no delay + ST7735_MADCTL , 1 , // 14: Memory access control (directions), 1 arg: + 0xC8, // row addr/col addr, bottom to top refresh + ST7735_COLMOD , 1 , // 15: set color mode, 1 arg, no delay: + 0x05 }; // 16-bit color + +/*static const uint8_t Rcmd2green[] = { // Init for 7735R, part 2 (green tab only) + 2, // 2 commands in list: + ST7735_CASET , 4 , // 1: Column addr set, 4 args, no delay: + 0x00, 0x02, // XSTART = 0 + 0x00, 0x7F+0x02, // XEND = 127 + ST7735_RASET , 4 , // 2: Row addr set, 4 args, no delay: + 0x00, 0x01, // XSTART = 0 + 0x00, 0x9F+0x01 }; // XEND = 159 + */ +static const uint8_t Rcmd2red[] = { // Init for 7735R, part 2 (red tab only) + 2, // 2 commands in list: + ST7735_CASET , 4 , // 1: Column addr set, 4 args, no delay: + 0x00, 0x00, // XSTART = 0 + 0x00, 0x7F, // XEND = 127 + ST7735_RASET , 4 , // 2: Row addr set, 4 args, no delay: + 0x00, 0x00, // XSTART = 0 + 0x00, 0x9F }; // XEND = 159 + +/*static const uint8_t Rcmd2green144[] = { // Init for 7735R, part 2 (green 1.44 tab) + 2, // 2 commands in list: + ST7735_CASET , 4 , // 1: Column addr set, 4 args, no delay: + 0x00, 0x00, // XSTART = 0 + 0x00, 0x7F, // XEND = 127 + ST7735_RASET , 4 , // 2: Row addr set, 4 args, no delay: + 0x00, 0x00, // XSTART = 0 + 0x00, 0x7F }; // XEND = 127 +*/ +static const uint8_t Rcmd3[] = { // Init for 7735R, part 3 (red or green tab) + 4, // 4 commands in list: + ST7735_GMCTRP1, 16 , // 1: Magical unicorn dust, 16 args, no delay: + 0x02, 0x1c, 0x07, 0x12, + 0x37, 0x32, 0x29, 0x2d, + 0x29, 0x25, 0x2B, 0x39, + 0x00, 0x01, 0x03, 0x10, + ST7735_GMCTRN1, 16 , // 2: Sparkles and rainbows, 16 args, no delay: + 0x03, 0x1d, 0x07, 0x06, + 0x2E, 0x2C, 0x29, 0x2D, + 0x2E, 0x2E, 0x37, 0x3F, + 0x00, 0x00, 0x02, 0x10, + ST7735_NORON , DELAY, // 3: Normal display on, no args, w/delay + 10, // 10 ms delay + ST7735_DISPON , DELAY, // 4: Main screen turn on, no args w/delay + 100 }; // 100 ms delay + +/* table of font caracter */ +// Standard ASCII 5x7 font + + +static const unsigned char tab_font[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x3E, 0x5B, 0x4F, 0x5B, 0x3E, + 0x3E, 0x6B, 0x4F, 0x6B, 0x3E, + 0x1C, 0x3E, 0x7C, 0x3E, 0x1C, + 0x18, 0x3C, 0x7E, 0x3C, 0x18, + 0x1C, 0x57, 0x7D, 0x57, 0x1C, + 0x1C, 0x5E, 0x7F, 0x5E, 0x1C, + 0x00, 0x18, 0x3C, 0x18, 0x00, + 0xFF, 0xE7, 0xC3, 0xE7, 0xFF, + 0x00, 0x18, 0x24, 0x18, 0x00, + 0xFF, 0xE7, 0xDB, 0xE7, 0xFF, + 0x30, 0x48, 0x3A, 0x06, 0x0E, + 0x26, 0x29, 0x79, 0x29, 0x26, + 0x40, 0x7F, 0x05, 0x05, 0x07, + 0x40, 0x7F, 0x05, 0x25, 0x3F, + 0x5A, 0x3C, 0xE7, 0x3C, 0x5A, + 0x7F, 0x3E, 0x1C, 0x1C, 0x08, + 0x08, 0x1C, 0x1C, 0x3E, 0x7F, + 0x14, 0x22, 0x7F, 0x22, 0x14, + 0x5F, 0x5F, 0x00, 0x5F, 0x5F, + 0x06, 0x09, 0x7F, 0x01, 0x7F, + 0x00, 0x66, 0x89, 0x95, 0x6A, + 0x60, 0x60, 0x60, 0x60, 0x60, + 0x94, 0xA2, 0xFF, 0xA2, 0x94, + 0x08, 0x04, 0x7E, 0x04, 0x08, + 0x10, 0x20, 0x7E, 0x20, 0x10, + 0x08, 0x08, 0x2A, 0x1C, 0x08, + 0x08, 0x1C, 0x2A, 0x08, 0x08, + 0x1E, 0x10, 0x10, 0x10, 0x10, + 0x0C, 0x1E, 0x0C, 0x1E, 0x0C, + 0x30, 0x38, 0x3E, 0x38, 0x30, + 0x06, 0x0E, 0x3E, 0x0E, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x5F, 0x00, 0x00, + 0x00, 0x07, 0x00, 0x07, 0x00, + 0x14, 0x7F, 0x14, 0x7F, 0x14, + 0x24, 0x2A, 0x7F, 0x2A, 0x12, + 0x23, 0x13, 0x08, 0x64, 0x62, + 0x36, 0x49, 0x56, 0x20, 0x50, + 0x00, 0x08, 0x07, 0x03, 0x00, + 0x00, 0x1C, 0x22, 0x41, 0x00, + 0x00, 0x41, 0x22, 0x1C, 0x00, + 0x2A, 0x1C, 0x7F, 0x1C, 0x2A, + 0x08, 0x08, 0x3E, 0x08, 0x08, + 0x00, 0x80, 0x70, 0x30, 0x00, + 0x08, 0x08, 0x08, 0x08, 0x08, + 0x00, 0x00, 0x60, 0x60, 0x00, + 0x20, 0x10, 0x08, 0x04, 0x02, + 0x3E, 0x51, 0x49, 0x45, 0x3E, + 0x00, 0x42, 0x7F, 0x40, 0x00, + 0x72, 0x49, 0x49, 0x49, 0x46, + 0x21, 0x41, 0x49, 0x4D, 0x33, + 0x18, 0x14, 0x12, 0x7F, 0x10, + 0x27, 0x45, 0x45, 0x45, 0x39, + 0x3C, 0x4A, 0x49, 0x49, 0x31, + 0x41, 0x21, 0x11, 0x09, 0x07, + 0x36, 0x49, 0x49, 0x49, 0x36, + 0x46, 0x49, 0x49, 0x29, 0x1E, + 0x00, 0x00, 0x14, 0x00, 0x00, + 0x00, 0x40, 0x34, 0x00, 0x00, + 0x00, 0x08, 0x14, 0x22, 0x41, + 0x14, 0x14, 0x14, 0x14, 0x14, + 0x00, 0x41, 0x22, 0x14, 0x08, + 0x02, 0x01, 0x59, 0x09, 0x06, + 0x3E, 0x41, 0x5D, 0x59, 0x4E, + 0x7C, 0x12, 0x11, 0x12, 0x7C, + 0x7F, 0x49, 0x49, 0x49, 0x36, + 0x3E, 0x41, 0x41, 0x41, 0x22, + 0x7F, 0x41, 0x41, 0x41, 0x3E, + 0x7F, 0x49, 0x49, 0x49, 0x41, + 0x7F, 0x09, 0x09, 0x09, 0x01, + 0x3E, 0x41, 0x41, 0x51, 0x73, + 0x7F, 0x08, 0x08, 0x08, 0x7F, + 0x00, 0x41, 0x7F, 0x41, 0x00, + 0x20, 0x40, 0x41, 0x3F, 0x01, + 0x7F, 0x08, 0x14, 0x22, 0x41, + 0x7F, 0x40, 0x40, 0x40, 0x40, + 0x7F, 0x02, 0x1C, 0x02, 0x7F, + 0x7F, 0x04, 0x08, 0x10, 0x7F, + 0x3E, 0x41, 0x41, 0x41, 0x3E, + 0x7F, 0x09, 0x09, 0x09, 0x06, + 0x3E, 0x41, 0x51, 0x21, 0x5E, + 0x7F, 0x09, 0x19, 0x29, 0x46, + 0x26, 0x49, 0x49, 0x49, 0x32, + 0x03, 0x01, 0x7F, 0x01, 0x03, + 0x3F, 0x40, 0x40, 0x40, 0x3F, + 0x1F, 0x20, 0x40, 0x20, 0x1F, + 0x3F, 0x40, 0x38, 0x40, 0x3F, + 0x63, 0x14, 0x08, 0x14, 0x63, + 0x03, 0x04, 0x78, 0x04, 0x03, + 0x61, 0x59, 0x49, 0x4D, 0x43, + 0x00, 0x7F, 0x41, 0x41, 0x41, + 0x02, 0x04, 0x08, 0x10, 0x20, + 0x00, 0x41, 0x41, 0x41, 0x7F, + 0x04, 0x02, 0x01, 0x02, 0x04, + 0x40, 0x40, 0x40, 0x40, 0x40, + 0x00, 0x03, 0x07, 0x08, 0x00, + 0x20, 0x54, 0x54, 0x78, 0x40, + 0x7F, 0x28, 0x44, 0x44, 0x38, + 0x38, 0x44, 0x44, 0x44, 0x28, + 0x38, 0x44, 0x44, 0x28, 0x7F, + 0x38, 0x54, 0x54, 0x54, 0x18, + 0x00, 0x08, 0x7E, 0x09, 0x02, + 0x18, 0xA4, 0xA4, 0x9C, 0x78, + 0x7F, 0x08, 0x04, 0x04, 0x78, + 0x00, 0x44, 0x7D, 0x40, 0x00, + 0x20, 0x40, 0x40, 0x3D, 0x00, + 0x7F, 0x10, 0x28, 0x44, 0x00, + 0x00, 0x41, 0x7F, 0x40, 0x00, + 0x7C, 0x04, 0x78, 0x04, 0x78, + 0x7C, 0x08, 0x04, 0x04, 0x78, + 0x38, 0x44, 0x44, 0x44, 0x38, + 0xFC, 0x18, 0x24, 0x24, 0x18, + 0x18, 0x24, 0x24, 0x18, 0xFC, + 0x7C, 0x08, 0x04, 0x04, 0x08, + 0x48, 0x54, 0x54, 0x54, 0x24, + 0x04, 0x04, 0x3F, 0x44, 0x24, + 0x3C, 0x40, 0x40, 0x20, 0x7C, + 0x1C, 0x20, 0x40, 0x20, 0x1C, + 0x3C, 0x40, 0x30, 0x40, 0x3C, + 0x44, 0x28, 0x10, 0x28, 0x44, + 0x4C, 0x90, 0x90, 0x90, 0x7C, + 0x44, 0x64, 0x54, 0x4C, 0x44, + 0x00, 0x08, 0x36, 0x41, 0x00, + 0x00, 0x00, 0x77, 0x00, 0x00, + 0x00, 0x41, 0x36, 0x08, 0x00, + 0x02, 0x01, 0x02, 0x04, 0x02, + 0x3C, 0x26, 0x23, 0x26, 0x3C, + 0x1E, 0xA1, 0xA1, 0x61, 0x12, + 0x3A, 0x40, 0x40, 0x20, 0x7A, + 0x38, 0x54, 0x54, 0x55, 0x59, + 0x21, 0x55, 0x55, 0x79, 0x41, + 0x22, 0x54, 0x54, 0x78, 0x42, // a-umlaut + 0x21, 0x55, 0x54, 0x78, 0x40, + 0x20, 0x54, 0x55, 0x79, 0x40, + 0x0C, 0x1E, 0x52, 0x72, 0x12, + 0x39, 0x55, 0x55, 0x55, 0x59, + 0x39, 0x54, 0x54, 0x54, 0x59, + 0x39, 0x55, 0x54, 0x54, 0x58, + 0x00, 0x00, 0x45, 0x7C, 0x41, + 0x00, 0x02, 0x45, 0x7D, 0x42, + 0x00, 0x01, 0x45, 0x7C, 0x40, + 0x7D, 0x12, 0x11, 0x12, 0x7D, // A-umlaut + 0xF0, 0x28, 0x25, 0x28, 0xF0, + 0x7C, 0x54, 0x55, 0x45, 0x00, + 0x20, 0x54, 0x54, 0x7C, 0x54, + 0x7C, 0x0A, 0x09, 0x7F, 0x49, + 0x32, 0x49, 0x49, 0x49, 0x32, + 0x3A, 0x44, 0x44, 0x44, 0x3A, // o-umlaut + 0x32, 0x4A, 0x48, 0x48, 0x30, + 0x3A, 0x41, 0x41, 0x21, 0x7A, + 0x3A, 0x42, 0x40, 0x20, 0x78, + 0x00, 0x9D, 0xA0, 0xA0, 0x7D, + 0x3D, 0x42, 0x42, 0x42, 0x3D, // O-umlaut + 0x3D, 0x40, 0x40, 0x40, 0x3D, + 0x3C, 0x24, 0xFF, 0x24, 0x24, + 0x48, 0x7E, 0x49, 0x43, 0x66, + 0x2B, 0x2F, 0xFC, 0x2F, 0x2B, + 0xFF, 0x09, 0x29, 0xF6, 0x20, + 0xC0, 0x88, 0x7E, 0x09, 0x03, + 0x20, 0x54, 0x54, 0x79, 0x41, + 0x00, 0x00, 0x44, 0x7D, 0x41, + 0x30, 0x48, 0x48, 0x4A, 0x32, + 0x38, 0x40, 0x40, 0x22, 0x7A, + 0x00, 0x7A, 0x0A, 0x0A, 0x72, + 0x7D, 0x0D, 0x19, 0x31, 0x7D, + 0x26, 0x29, 0x29, 0x2F, 0x28, + 0x26, 0x29, 0x29, 0x29, 0x26, + 0x30, 0x48, 0x4D, 0x40, 0x20, + 0x38, 0x08, 0x08, 0x08, 0x08, + 0x08, 0x08, 0x08, 0x08, 0x38, + 0x2F, 0x10, 0xC8, 0xAC, 0xBA, + 0x2F, 0x10, 0x28, 0x34, 0xFA, + 0x00, 0x00, 0x7B, 0x00, 0x00, + 0x08, 0x14, 0x2A, 0x14, 0x22, + 0x22, 0x14, 0x2A, 0x14, 0x08, + 0xAA, 0x00, 0x55, 0x00, 0xAA, + 0xAA, 0x55, 0xAA, 0x55, 0xAA, + 0x00, 0x00, 0x00, 0xFF, 0x00, + 0x10, 0x10, 0x10, 0xFF, 0x00, + 0x14, 0x14, 0x14, 0xFF, 0x00, + 0x10, 0x10, 0xFF, 0x00, 0xFF, + 0x10, 0x10, 0xF0, 0x10, 0xF0, + 0x14, 0x14, 0x14, 0xFC, 0x00, + 0x14, 0x14, 0xF7, 0x00, 0xFF, + 0x00, 0x00, 0xFF, 0x00, 0xFF, + 0x14, 0x14, 0xF4, 0x04, 0xFC, + 0x14, 0x14, 0x17, 0x10, 0x1F, + 0x10, 0x10, 0x1F, 0x10, 0x1F, + 0x14, 0x14, 0x14, 0x1F, 0x00, + 0x10, 0x10, 0x10, 0xF0, 0x00, + 0x00, 0x00, 0x00, 0x1F, 0x10, + 0x10, 0x10, 0x10, 0x1F, 0x10, + 0x10, 0x10, 0x10, 0xF0, 0x10, + 0x00, 0x00, 0x00, 0xFF, 0x10, + 0x10, 0x10, 0x10, 0x10, 0x10, + 0x10, 0x10, 0x10, 0xFF, 0x10, + 0x00, 0x00, 0x00, 0xFF, 0x14, + 0x00, 0x00, 0xFF, 0x00, 0xFF, + 0x00, 0x00, 0x1F, 0x10, 0x17, + 0x00, 0x00, 0xFC, 0x04, 0xF4, + 0x14, 0x14, 0x17, 0x10, 0x17, + 0x14, 0x14, 0xF4, 0x04, 0xF4, + 0x00, 0x00, 0xFF, 0x00, 0xF7, + 0x14, 0x14, 0x14, 0x14, 0x14, + 0x14, 0x14, 0xF7, 0x00, 0xF7, + 0x14, 0x14, 0x14, 0x17, 0x14, + 0x10, 0x10, 0x1F, 0x10, 0x1F, + 0x14, 0x14, 0x14, 0xF4, 0x14, + 0x10, 0x10, 0xF0, 0x10, 0xF0, + 0x00, 0x00, 0x1F, 0x10, 0x1F, + 0x00, 0x00, 0x00, 0x1F, 0x14, + 0x00, 0x00, 0x00, 0xFC, 0x14, + 0x00, 0x00, 0xF0, 0x10, 0xF0, + 0x10, 0x10, 0xFF, 0x10, 0xFF, + 0x14, 0x14, 0x14, 0xFF, 0x14, + 0x10, 0x10, 0x10, 0x1F, 0x00, + 0x00, 0x00, 0x00, 0xF0, 0x10, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, + 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xFF, 0xFF, + 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, + 0x38, 0x44, 0x44, 0x38, 0x44, + 0xFC, 0x4A, 0x4A, 0x4A, 0x34, // sharp-s or beta + 0x7E, 0x02, 0x02, 0x06, 0x06, + 0x02, 0x7E, 0x02, 0x7E, 0x02, + 0x63, 0x55, 0x49, 0x41, 0x63, + 0x38, 0x44, 0x44, 0x3C, 0x04, + 0x40, 0x7E, 0x20, 0x1E, 0x20, + 0x06, 0x02, 0x7E, 0x02, 0x02, + 0x99, 0xA5, 0xE7, 0xA5, 0x99, + 0x1C, 0x2A, 0x49, 0x2A, 0x1C, + 0x4C, 0x72, 0x01, 0x72, 0x4C, + 0x30, 0x4A, 0x4D, 0x4D, 0x30, + 0x30, 0x48, 0x78, 0x48, 0x30, + 0xBC, 0x62, 0x5A, 0x46, 0x3D, + 0x3E, 0x49, 0x49, 0x49, 0x00, + 0x7E, 0x01, 0x01, 0x01, 0x7E, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x44, 0x44, 0x5F, 0x44, 0x44, + 0x40, 0x51, 0x4A, 0x44, 0x40, + 0x40, 0x44, 0x4A, 0x51, 0x40, + 0x00, 0x00, 0xFF, 0x01, 0x03, + 0xE0, 0x80, 0xFF, 0x00, 0x00, + 0x08, 0x08, 0x6B, 0x6B, 0x08, + 0x36, 0x12, 0x36, 0x24, 0x36, + 0x06, 0x0F, 0x09, 0x0F, 0x06, + 0x00, 0x00, 0x18, 0x18, 0x00, + 0x00, 0x00, 0x10, 0x10, 0x00, + 0x30, 0x40, 0xFF, 0x01, 0x01, + 0x00, 0x1F, 0x01, 0x01, 0x1E, + 0x00, 0x19, 0x1D, 0x17, 0x12, + 0x00, 0x3C, 0x3C, 0x3C, 0x3C, + 0x00, 0x00, 0x00, 0x00, 0x00 +}; + + +/* */ +const unsigned char ALL_IS_mono_120 [] = { +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, +0xF0, 0xF8, 0x38, 0x18, 0x78, 0xF8, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0xF8, +0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x20, 0x30, 0x3E, 0x3F, 0x0F, 0x07, 0x04, 0x04, 0x04, 0x04, 0x05, 0x0F, 0x1F, +0x3E, 0x38, 0x20, 0x00, 0x00, 0x3F, 0x3F, 0x3F, 0x3F, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, +0x00, 0x3F, 0x3F, 0x3F, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF0, 0xF8, 0x08, 0x0C, 0xDC, 0x8C, 0x2C, 0x74, +0x74, 0x64, 0xEC, 0xC8, 0xF0, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, +0x07, 0x0F, 0x18, 0x18, 0x1D, 0x19, 0x33, 0x37, 0x17, 0x13, 0x1A, 0x0C, 0x0F, 0x07, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x02, 0x02, 0x02, 0x02, 0x02, +0x04, 0x04, 0x04, 0x08, 0x10, 0x20, 0xC0, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xC0, 0x30, 0x10, 0x08, +0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x08, 0x18, 0x10, 0x00, 0x00, 0x00, 0xFC, 0x00, +0x00, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x0C, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x3F, 0x40, 0x40, 0x40, 0x40, 0x40, 0x60, 0x20, 0x20, 0x20, 0x10, 0x0C, 0x03, 0x00, +0x00, 0x1F, 0x00, 0x00, 0x03, 0x04, 0x08, 0x10, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x22, 0x22, +0x12, 0x0A, 0x06, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, +0x00, 0x00, 0x00, 0x20, 0x10, 0x10, 0x08, 0x04, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x3F, 0x00, 0x00, 0x00, 0x3F, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + + + +/* PROTOTYPE ************************************************************/ + +void Write_SPI (unsigned char dataout); +void writecommand(unsigned char cmdout); +void writedata(unsigned char dataout); +void commandList(const uint8_t *addr); +void displayLogo_TFT( void); + +/* SOUS-PROGRAMME *******************************************************/ + +/******************************************************************************* +* Function Name : Write_SPI +* Description : write byte for transmit via SPI +* Input : byte to write +* Output : None +* Return : None +*******************************************************************************/ +void Write_SPI(unsigned char dataout) +{ + //char temp; + + //SPI_DR=dataout; + + //while ( (SPI_SR & 0x02) == 0x00 ) ; // wait for transmission started + //while ( (SPI_SR & 0x80) != 0x00 ) ; // wait for transmission completed + + HAL_SPI_Transmit(&hspi1, &dataout, 1, 100); // HAL_ERROR + +} + +/******************************************************************************* +* Function Name : writecommand +* Description : write command to TFT controller +* Input : command byte to write +* Output : None +* Return : None +*******************************************************************************/ +void writecommand(unsigned char cmdout) +{ + //PD_ODR = PD_ODR & ~0x01; // PD0 = D/nC = 0 commande + //PC_ODR = PC_ODR & ~0x80; // PC7 = nCS = 0 + + //Write_SPI( cmdout); + + // PC_ODR = PC_ODR | 0x80; // PC7 = nCS = 1 + + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 0); // D/nC = 0 commande + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0 + + //HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); // HAL_ERROR + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1 + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN << 16 ;// D/nC = 0 commande + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0 + HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); // + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + +} + +/******************************************************************************* +* Function Name : writedata +* Description : write data to TFT controller +* Input : data byte to write +* Output : None +* Return : None +*******************************************************************************/ +void writedata(unsigned char dataout) +{ + //PD_ODR = PD_ODR | 0x01; // PD0 = D/nC = 1 data + //PC_ODR = PC_ODR & ~0x80; // PC7 = nCS = 0 + + //Write_SPI( dataout); + + //PC_ODR = PC_ODR | 0x80; // PC7 = nCS = 1 + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // D/nC = 1 data + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0 + + //HAL_SPI_Transmit(&hspi1, &dataout, 1, 100); // HAL_ERROR + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1 + + + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0 + HAL_SPI_Transmit(&hspi1, &dataout, 1, 100); // + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + +} + +/******************************************************************************* +* Function Name : commandList +* Description : Reads and issues a series of LCD commands stored in byte array +* Input : addr = pointer on command byte array +* Output : None +* Return : None +*******************************************************************************/ +void commandList(const uint8_t *addr) +{ + uint8_t numCommands, numArgs; + uint16_t ms; + + numCommands = pgm_read_byte(addr++); // Number of commands to follow + while(numCommands--) + { // For each command... + writecommand(pgm_read_byte(addr++)); // Read, issue command + numArgs = pgm_read_byte(addr++); // Number of args to follow + ms = numArgs & DELAY; // If hibit set, delay follows args + numArgs &= ~DELAY; // Mask out delay bit + while(numArgs--) { // For each argument... + writedata(pgm_read_byte(addr++)); // Read, issue argument + } + + if(ms) { + ms = pgm_read_byte(addr++); // Read post-command delay time (ms) + if(ms == 255) ms = 500; // If 255, delay for 500 ms + HAL_Delay(500); + } + } +} + +/******************************************************************************* +* Function Name : setAddrWindow +* Description : command for select a window to write pixel +* Input : x1 horizontal position = 0 to ST7735_TFTWIDTH-1 +* : y1 vertical position = 0 to ST7735_TFTHEIGHT-1 +* : x2 horizontal position = x1 to ST7735_TFTWIDTH-1-x1 +* : y2 vertical position = y1 to ST7735_TFTHEIGHT-1-y1 +* Output : None +* Return : None +*******************************************************************************/ +void setAddrWindow(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1) +{ + + writecommand(ST7735_CASET); // Column addr set + writedata(0x00); + writedata(x0); // XSTART + writedata(0x00); + writedata(x1); // XEND + + writecommand(ST7735_RASET); // Row addr set + writedata(0x00); + writedata(y0); // YSTART + writedata(0x00); + writedata(y1); // YEND + + writecommand(ST7735_RAMWR); // write to RAM +} + +/******************************************************************************* +* Function Name : init_TFT +* Description : initialization controller display TFT and default screen +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void init_TFT( void) +{ + //init_SPI(); + + // reset +// PD_ODR = PD_ODR | 0x80; // PD7 = nReset = 1 +// PC_ODR = PC_ODR & ~0x80; // PC7 = nCS = 0 +// attend_500ms(); +// PD_ODR = PD_ODR & ~0x80; // PD7 = nReset = 0 +// attend_500ms(); +// PD_ODR = PD_ODR | 0x80; // PD7 = nReset = 1 + +// attend_500ms(); +// PC_ODR = PC_ODR | 0x80; // PC7 = nCS = 1 + +/* HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // DC= 1 + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, 1); // nRESET = 1 + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0 + attend_500ms(); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, 0); // nRESET = 0 + attend_500ms(); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, 1); // nRESET = 1 + attend_500ms(); + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/ + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // DC= 1 + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1 + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0 + HAL_Delay(500); + ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN<<16;// nRESET = 0 + HAL_Delay(500); + ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1 + HAL_Delay(500); + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + + // initialization instruction + commandList(Rcmd1); + commandList(Rcmd2red); + commandList(Rcmd3); + + writecommand(ST7735_MADCTL); + writedata(0xC0); + + // all display background is black + fillRect_TFT(0, 0, ST7735_TFTWIDTH, ST7735_TFTHEIGHT_18, ST7735_BLACK); + + // display LOGO + displayLogo_TFT(); +} + +/******************************************************************************* +* Function Name : drawPixel_TFT +* Description : draw a pixel at position x y with specified color +* Input : x horizontal position = 0 to ST7735_TFTWIDTH-1 +* : y vertical position = 0 to ST7735_TFTHEIGHT-1 +* : color = 16bits RGB=(565) soit RRRRRGGGGGGGBBBBB +* Output : None +* Return : None +*******************************************************************************/ +void drawPixel_TFT(uint16_t x, uint16_t y, uint16_t color) +{ + uint8_t hi, lo; + + // rudimentary clipping (drawChar w/big text requires this) + if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return; + + setAddrWindow(x, y, x+1, y+1); + + hi = color >> 8; + lo = color ; + +/* + PD_ODR = PD_ODR | 0x01; // PD0 = D/nC = 1 data + PC_ODR = PC_ODR & ~0x80; // PC7 = nCS = 0 + + Write_SPI(hi); + Write_SPI(lo); + + PC_ODR = PC_ODR | 0x80; // PC7 = nCS = 1 +*/ + +/* HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // D/nC = 1 data + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0 + + HAL_SPI_Transmit(&hspi1, &hi, 1, 100); // + HAL_SPI_Transmit(&hspi1, &lo, 1, 100); // + + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/ + + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0 + + HAL_SPI_Transmit(&hspi1, &hi, 1, 100); // + HAL_SPI_Transmit(&hspi1, &lo, 1, 100); // + + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 +} + + +/******************************************************************************* +* Function Name : fillRect_TFT +* Description : draw a fill rectangle start position x y, dimension w h with specified color +* Input : x horizontal position = 0 to ST7735_TFTWIDTH-1 +* : y vertical position = 0 to ST7735_TFTHEIGHT-1 +* : w width = 1 to ST7735_TFTWIDTH-1-x +* : h height = 1 to ST7735_TFTHEIGHT-1-y +* : color = 16bits RGB(565) soit RRRRRGGGGGGGBBBBB +* Output : None +* Return : None +*******************************************************************************/ +void fillRect_TFT(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color) +{ + uint8_t hi, lo; + + // rudimentary clipping (drawChar w/big text requires this) + if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return; + + if((x + w - 1) >= ST7735_TFTWIDTH) w = ST7735_TFTWIDTH - x; + if((y + h - 1) >= ST7735_TFTHEIGHT_18) h = ST7735_TFTHEIGHT_18 - y; + + // select window + setAddrWindow(x, y, x+w-1, y+h-1); + + hi = color >> 8; + lo = color ; + + /* + PD_ODR = PD_ODR | 0x01; // PD0 = D/nC = 1 data + PC_ODR = PC_ODR & ~0x80; // PC7 = nCS = 0 + + // write pixel in the window + for(y=h; y>0; y--) + { + for(x=w; x>0; x--) + { + Write_SPI(hi); + Write_SPI(lo); + + + } + } + + PC_ODR = PC_ODR | 0x80; // PC7 = nCS = 1 + */ + + /*HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // D/nC = 1 data + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0*/ + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0 + + for(y=h; y>0; y--) + { + for(x=w; x>0; x--) + { + + HAL_SPI_Transmit(&hspi1, &hi, 1, 100); // + HAL_SPI_Transmit(&hspi1, &lo, 1, 100); // + + } + } + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1 + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 + +} + +/******************************************************************************* +* Function Name : fillScreen_TFT +* Description : fill all the screen with specified color : this take few seconds +* Input : color = 16bits RGB=(565) soit RRRRRGGGGGGGBBBBB +* Output : None +* Return : None +*******************************************************************************/ +void fillScreen_TFT(uint16_t color) +{ + fillRect_TFT(0, 0, ST7735_TFTWIDTH, ST7735_TFTHEIGHT_18, color); +} + +/******************************************************************************* +* Function Name : displayChar_TFT +* Description : Draw a character 5x7 font for size = 1 +* Input : x horizontal position = 0 to ST7735_TFTWIDTH-1-5xsize +* : y vertical position = 0 to ST7735_TFTHEIGHT-1-7xsize +* : c = 8 bits ASCII code caracter +* : color = 16bits RGB(565) soit RRRRRGGGGGGGBBBBB +* : bg back ground color = 16bits RGB(565) soit RRRRRGGGGGGGBBBBB +* : size = 1 to 10 +* Output : None +* Return : None +*******************************************************************************/ +void displayChar_TFT(uint16_t x, uint16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size) +{ + uint8_t i,j,line; + + + if((x >= ST7735_TFTWIDTH) || // Clip right + (y >= ST7735_TFTHEIGHT_18) || // Clip bottom + ((x + 6 * size - 1) < 0) || // Clip left + ((y + 8 * size - 1) < 0)) // Clip top + return; + + for (i=0; i<6; i++ ) + { + if (i == 5) + line = 0x0; + else + line = pgm_read_byte(tab_font + (c*5) + i); + + for ( j = 0; j<8; j++) + { + if (line & 0x1) + { + if (size == 1) // default size + drawPixel_TFT(x+i, y+j, color); + else + { // big size + fillRect_TFT(x+(i*size), y+(j*size), size, size, color); + } + } + else if (bg != color) + { + if (size == 1) // default size + drawPixel_TFT(x+i, y+j, bg); + else + { // big size + fillRect_TFT(x+i*size, y+j*size, size, size, bg); + } + } + line = line >> 1; + } + } +} + +/******************************************************************************* +* Function Name : drawVLine_TFT +* Description : draw a vertical line +* Input : x horizontal start position = 0 to ST7735_TFTWIDTH-1 +* : y vertical start position = 0 to ST7735_TFTHEIGHT-1-h +* : h height = 1 to ST7735_TFTHEIGHT-1-y +* : color = 16bits RGB(565) soit RRRRRGGGGGGGBBBBB +* Output : None +* Return : None +*******************************************************************************/ +void drawVLine_TFT(uint16_t x, uint16_t y, uint16_t h, uint16_t color) +{ + uint8_t hi = color >> 8, lo = color; +uint8_t i; + + // Rudimentary clipping + //if((x >= ST7735_TFTWIDTH) || // Clip right + // (y >= ST7735_TFTHEIGHT_18) ) // Clip bottom + //return; + // if((y+h-1) >= ST7735_TFTHEIGHT_18) +// h = ST7735_TFTHEIGHT_18-y; + + // select window + setAddrWindow(x, y, x, y+h-1); + +/* + PD_ODR = PD_ODR | 0x01; // PD0 = D/nC = 1 data + PC_ODR = PC_ODR & ~0x80; // PC7 = nCS = 0 + + for(i=y+h; i>=y; i--) + { + + Write_SPI(hi); + Write_SPI(lo); + + } + + PC_ODR = PC_ODR | 0x80; // PC7 = nCS = 1 +*/ + + /*HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // D/nC = 1 data + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0*/ + + ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0 + + + + for(i=y+h; i>y; i--) + { + HAL_SPI_Transmit(&hspi1, &hi, 1, 100); // + HAL_SPI_Transmit(&hspi1, &lo, 1, 100); // + } + + //HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1 + ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1 +} + +/******************************************************************************* +* Function Name : displayLogo_TFT +* Description : draw a LOGO on screen +* Input : +* Output : None +* Return : None +*******************************************************************************/ +void displayLogo_TFT( void) +{ + uint8_t i,j,k,line; + uint16_t color=ST7735_WHITE; + + + + for(i=0;i<=120;i++) + { + + for(j=0;j<= 1;j++) + { + line=(ALL_IS_mono_120[i+120*j]); + for ( k = 0; k<8; k++) + { + if (line & 0x1) + { + + drawPixel_TFT(i, j*8+k, color); + } + line = line >> 1; + } + } + + color=ST7735_RED; + for(j=2;j<= 3;j++) + { + line=(ALL_IS_mono_120[i+120*j]); + for ( k = 0; k<8; k++) + { + if (line & 0x1) + { + + drawPixel_TFT(i, j*8+k, color); + } + line = line >> 1; + } + } + + color=ST7735_WHITE; + for(j=4;j<= 5;j++) + { + line=(ALL_IS_mono_120[i+120*j]); + for ( k = 0; k<8; k++) + { + if (line & 0x1) + { + + drawPixel_TFT(i, j*8+k, color); + } + line = line >> 1; + } + } + + } +} + diff --git a/TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.h b/TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.h new file mode 100644 index 0000000..30eaaf2 --- /dev/null +++ b/TP4_INIT_TFT/Drivers/TFT_ST7735/fonc_tft.h @@ -0,0 +1,65 @@ +/************************************************************************ +* TITLE: fonc_tft.h +* AUTHOR: +* DESCRIPTION: include pour afficheur graphique TFT +* VERSION : 1.1 ajout dimension ecran et caractere +* 1.2 suppression redefinition uint8_t et uint16_t +* +************************************************************************/ + + + +/* DEFINE **************************************************************/ + + +// Color definitions +#define ST7735_BLACK 0x0000 +#define ST7735_BLUE 0x001F +#define ST7735_RED 0xF800 +#define ST7735_GREEN 0x07E0 +#define ST7735_CYAN 0x07FF +#define ST7735_MAGENTA 0xF81F +#define ST7735_YELLOW 0xFFE0 +#define ST7735_WHITE 0xFFFF + +// size TFT display +#define ST7735_TFTWIDTH 128 // Width TFT display +#define ST7735_TFTHEIGHT_18 160 // Heigt TFT 1.8" display + +// size character on screen +#define DIM_CHAR_X_TFT 6 // H character dimension (5 pixel + intercaracter 1 pixel) when size=1 +#define DIM_CHAR_Y_TFT 8 // V character dimension (7 pixel + intercaracter 1 pixel) when size=1 + + +// ST7735 RST (Reset) pin +#define ST7735_RST_PORT GPIOD +#define ST7735_RST_PIN GPIO_PIN_2 + +// ST7735 (Data/Command select) pin +#define ST7735_D_nC_PORT GPIOC +#define ST7735_D_nC_PIN GPIO_PIN_2 + +// ST7735 CS (Chip Select) pin +#define ST7735_nCS_PORT GPIOC +#define ST7735_nCS_PIN GPIO_PIN_1 + + +/* PROTOTYPE *************************************************************/ + +// init screen +void init_TFT( void); + +// draw pixel +void drawPixel_TFT(uint16_t x, uint16_t y, uint16_t color); + +// fill a rectangle +void fillRect_TFT(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color); + +// fill screen +void fillScreen_TFT(uint16_t color); + +// Draw a character +void displayChar_TFT(uint16_t x, uint16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size); + +// Draw a vertical line +void drawVLine_TFT(uint16_t x, uint16_t y, uint16_t h, uint16_t color); diff --git a/TP4_INIT_TFT/STM32L152RETX_FLASH.ld b/TP4_INIT_TFT/STM32L152RETX_FLASH.ld new file mode 100644 index 0000000..c25a2cf --- /dev/null +++ b/TP4_INIT_TFT/STM32L152RETX_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32L152RETx Device from STM32L1 series +** 512KBytes FLASH +** 80KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TP4_INIT_TFT/STM32L152RETX_RAM.ld b/TP4_INIT_TFT/STM32L152RETX_RAM.ld new file mode 100644 index 0000000..5686e2c --- /dev/null +++ b/TP4_INIT_TFT/STM32L152RETX_RAM.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld (debug in RAM dedicated) +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32L152RETx Device from STM32L1 series +** 512KBytes FLASH +** 80KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >RAM + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >RAM + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >RAM + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >RAM + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/TP4_INIT_TFT/TP4_INIT_TFT Debug.launch b/TP4_INIT_TFT/TP4_INIT_TFT Debug.launch new file mode 100644 index 0000000..648b7b0 --- /dev/null +++ b/TP4_INIT_TFT/TP4_INIT_TFT Debug.launch @@ -0,0 +1,85 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/TP4_INIT_TFT/TP4_INIT_TFT.ioc b/TP4_INIT_TFT/TP4_INIT_TFT.ioc new file mode 100644 index 0000000..533bd72 --- /dev/null +++ b/TP4_INIT_TFT/TP4_INIT_TFT.ioc @@ -0,0 +1,145 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32L152RET6 +Mcu.Family=STM32L1 +Mcu.IP0=NVIC +Mcu.IP1=RCC +Mcu.IP2=SPI1 +Mcu.IP3=SYS +Mcu.IPNb=4 +Mcu.Name=STM32L152RETx +Mcu.Package=LQFP64 +Mcu.Pin0=PC0 +Mcu.Pin1=PC1 +Mcu.Pin10=VP_SYS_VS_Systick +Mcu.Pin2=PC2 +Mcu.Pin3=PC3 +Mcu.Pin4=PA5 +Mcu.Pin5=PA6 +Mcu.Pin6=PA7 +Mcu.Pin7=PB15 +Mcu.Pin8=PD2 +Mcu.Pin9=PB7 +Mcu.PinsNb=11 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32L152RETx +MxCube.Version=6.14.1 +MxDb.Version=DB.6.0.141 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA5.Locked=true +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Locked=true +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Locked=true +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PB15.Locked=true +PB15.Signal=S_TIM11_CH1 +PB7.Locked=true +PB7.Signal=S_TIM4_CH2 +PC0.Locked=true +PC0.Signal=GPIO_Output +PC1.GPIOParameters=PinState +PC1.Locked=true +PC1.PinState=GPIO_PIN_SET +PC1.Signal=GPIO_Output +PC2.GPIOParameters=PinState +PC2.Locked=true +PC2.PinState=GPIO_PIN_SET +PC2.Signal=GPIO_Output +PC3.GPIOParameters=PinState +PC3.Locked=true +PC3.PinState=GPIO_PIN_SET +PC3.Signal=GPIO_Output +PD2.GPIOParameters=PinState +PD2.Locked=true +PD2.PinState=GPIO_PIN_SET +PD2.Signal=GPIO_Output +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32L152RETx +ProjectManager.FirmwarePackage=STM32Cube FW_L1 V1.10.5 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=TP4_INIT_TFT.ioc +ProjectManager.ProjectName=TP4_INIT_TFT +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_SPI1_Init-SPI1-false-HAL-true +RCC.AHBFreq_Value=16000000 +RCC.APB1Freq_Value=16000000 +RCC.APB1TimFreq_Value=16000000 +RCC.APB2Freq_Value=16000000 +RCC.APB2TimFreq_Value=16000000 +RCC.FCLKCortexFreq_Value=16000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=16000000 +RCC.HSE_VALUE=24000000 +RCC.HSI_VALUE=16000000 +RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,LSE_VALUE,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,VCOOutputFreq_Value +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=37000 +RCC.MCOPinFreq_Value=16000000 +RCC.MSI_VALUE=2097000 +RCC.PLLCLKFreq_Value=24000000 +RCC.PWRFreq_Value=16000000 +RCC.RTCFreq_Value=37000 +RCC.RTCHSEDivFreq_Value=12000000 +RCC.SYSCLKFreq_VALUE=16000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSI +RCC.TIMFreq_Value=16000000 +RCC.TimerFreq_Value=16000000 +RCC.VCOOutputFreq_Value=48000000 +SH.S_TIM11_CH1.0=TIM11_CH1 +SH.S_TIM11_CH1.ConfNb=1 +SH.S_TIM4_CH2.0=TIM4_CH2 +SH.S_TIM4_CH2.ConfNb=1 +SPI1.CalculateBaudRate=8.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom +isbadioc=false

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/dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/TFT_ST7735/fonc_tft.su @@ -0,0 +1,12 @@ +../Drivers/TFT_ST7735/fonc_tft.c:566:6:Write_SPI 16 static +../Drivers/TFT_ST7735/fonc_tft.c:586:6:writecommand 16 static +../Drivers/TFT_ST7735/fonc_tft.c:617:6:writedata 16 static +../Drivers/TFT_ST7735/fonc_tft.c:649:6:commandList 24 static +../Drivers/TFT_ST7735/fonc_tft.c:683:6:setAddrWindow 24 static +../Drivers/TFT_ST7735/fonc_tft.c:708:6:init_TFT 16 static +../Drivers/TFT_ST7735/fonc_tft.c:768:6:drawPixel_TFT 24 static +../Drivers/TFT_ST7735/fonc_tft.c:820:6:fillRect_TFT 32 static +../Drivers/TFT_ST7735/fonc_tft.c:884:6:fillScreen_TFT 24 static +../Drivers/TFT_ST7735/fonc_tft.c:901:6:displayChar_TFT 40 static +../Drivers/TFT_ST7735/fonc_tft.c:954:6:drawVLine_TFT 32 static +../Drivers/TFT_ST7735/fonc_tft.c:1009:6:displayLogo_TFT 16 static diff --git a/TP4_INIT_TFT/Debug/Drivers/TFT_ST7735/subdir.mk b/TP4_INIT_TFT/Debug/Drivers/TFT_ST7735/subdir.mk new file mode 100644 index 0000000..69902e9 --- /dev/null +++ b/TP4_INIT_TFT/Debug/Drivers/TFT_ST7735/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (13.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/TFT_ST7735/fonc_tft.c + +OBJS += \ +./Drivers/TFT_ST7735/fonc_tft.o + +C_DEPS += \ +./Drivers/TFT_ST7735/fonc_tft.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/TFT_ST7735/%.o Drivers/TFT_ST7735/%.su Drivers/TFT_ST7735/%.cyclo: ../Drivers/TFT_ST7735/%.c Drivers/TFT_ST7735/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32L152xE -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -I../Drivers/7Seg_MAX7219 -I../Drivers/TFT_ST7735 -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-TFT_ST7735 + +clean-Drivers-2f-TFT_ST7735: + -$(RM) ./Drivers/TFT_ST7735/fonc_tft.cyclo ./Drivers/TFT_ST7735/fonc_tft.d ./Drivers/TFT_ST7735/fonc_tft.o ./Drivers/TFT_ST7735/fonc_tft.su + +.PHONY: clean-Drivers-2f-TFT_ST7735 + diff --git a/TP4_INIT_TFT/Debug/TP2_INIT_DISPLAY.list b/TP4_INIT_TFT/Debug/TP2_INIT_DISPLAY.list new file mode 100644 index 0000000..b4aed8b --- /dev/null +++ b/TP4_INIT_TFT/Debug/TP2_INIT_DISPLAY.list @@ -0,0 +1,5454 @@ + +TP2_INIT_DISPLAY.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00001f50 0800013c 0800013c 0000113c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000002c 0800208c 0800208c 0000308c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 080020b8 080020b8 0000400c 2**0 + CONTENTS, READONLY + 4 .ARM 00000008 080020b8 080020b8 000030b8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 080020c0 080020c0 0000400c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 080020c0 080020c0 000030c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 7 .fini_array 00000004 080020c4 080020c4 000030c4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .data 0000000c 20000000 080020c8 00004000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000078 2000000c 080020d4 0000400c 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20000084 080020d4 00004084 2**0 + ALLOC + 11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0 + CONTENTS, READONLY + 12 .debug_info 0000573e 00000000 00000000 00004035 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 0000145f 00000000 00000000 00009773 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000660 00000000 00000000 0000abd8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_rnglists 000004b4 00000000 00000000 0000b238 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 0001499e 00000000 00000000 0000b6ec 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 00006fc2 00000000 00000000 0002008a 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 00081143 00000000 00000000 0002704c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000043 00000000 00000000 000a818f 2**0 + CONTENTS, READONLY + 20 .debug_frame 000018ac 00000000 00000000 000a81d4 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000070 00000000 00000000 000a9a80 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +0800013c <__do_global_dtors_aux>: + 800013c: b510 push {r4, lr} + 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) + 8000140: 7823 ldrb r3, [r4, #0] + 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> + 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) + 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> + 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) + 800014a: f3af 8000 nop.w + 800014e: 2301 movs r3, #1 + 8000150: 7023 strb r3, [r4, #0] + 8000152: bd10 pop {r4, pc} + 8000154: 2000000c .word 0x2000000c + 8000158: 00000000 .word 0x00000000 + 800015c: 08002074 .word 0x08002074 + +08000160 : + 8000160: b508 push {r3, lr} + 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) + 8000164: b11b cbz r3, 800016e + 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) + 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) + 800016a: f3af 8000 nop.w + 800016e: bd08 pop {r3, pc} + 8000170: 00000000 .word 0x00000000 + 8000174: 20000010 .word 0x20000010 + 8000178: 08002074 .word 0x08002074 + +0800017c <__aeabi_uldivmod>: + 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> + 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> + 8000180: 2900 cmp r1, #0 + 8000182: bf08 it eq + 8000184: 2800 cmpeq r0, #0 + 8000186: bf1c itt ne + 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff + 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff + 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> + 8000194: f1ad 0c08 sub.w ip, sp, #8 + 8000198: e96d ce04 strd ip, lr, [sp, #-16]! + 800019c: f000 f806 bl 80001ac <__udivmoddi4> + 80001a0: f8dd e004 ldr.w lr, [sp, #4] + 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] + 80001a8: b004 add sp, #16 + 80001aa: 4770 bx lr + +080001ac <__udivmoddi4>: + 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80001b0: 9d08 ldr r5, [sp, #32] + 80001b2: 468e mov lr, r1 + 80001b4: 4604 mov r4, r0 + 80001b6: 4688 mov r8, r1 + 80001b8: 2b00 cmp r3, #0 + 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> + 80001bc: 428a cmp r2, r1 + 80001be: 4617 mov r7, r2 + 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> + 80001c2: fab2 f682 clz r6, r2 + 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> + 80001c8: f1c6 0320 rsb r3, r6, #32 + 80001cc: fa01 f806 lsl.w r8, r1, r6 + 80001d0: fa20 f303 lsr.w r3, r0, r3 + 80001d4: 40b7 lsls r7, r6 + 80001d6: ea43 0808 orr.w r8, r3, r8 + 80001da: 40b4 lsls r4, r6 + 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 + 80001e0: fbb8 f1fe udiv r1, r8, lr + 80001e4: fa1f fc87 uxth.w ip, r7 + 80001e8: fb0e 8811 mls r8, lr, r1, r8 + 80001ec: fb01 f20c mul.w r2, r1, ip + 80001f0: 0c23 lsrs r3, r4, #16 + 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 + 80001f6: 429a cmp r2, r3 + 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> + 80001fa: 18fb adds r3, r7, r3 + 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff + 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> + 8000204: 429a cmp r2, r3 + 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> + 800020a: 3902 subs r1, #2 + 800020c: 443b add r3, r7 + 800020e: 1a9a subs r2, r3, r2 + 8000210: fbb2 f0fe udiv r0, r2, lr + 8000214: fb0e 2210 mls r2, lr, r0, r2 + 8000218: fb00 fc0c mul.w ip, r0, ip + 800021c: b2a3 uxth r3, r4 + 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 + 8000222: 459c cmp ip, r3 + 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> + 8000226: 18fb adds r3, r7, r3 + 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff + 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> + 8000230: 459c cmp ip, r3 + 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> + 8000236: 443b add r3, r7 + 8000238: 3802 subs r0, #2 + 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 + 800023e: 2100 movs r1, #0 + 8000240: eba3 030c sub.w r3, r3, ip + 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> + 8000246: 2200 movs r2, #0 + 8000248: 40f3 lsrs r3, r6 + 800024a: e9c5 3200 strd r3, r2, [r5] + 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000252: 428b cmp r3, r1 + 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> + 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> + 8000258: e9c5 0100 strd r0, r1, [r5] + 800025c: 2100 movs r1, #0 + 800025e: 4608 mov r0, r1 + 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> + 8000262: fab3 f183 clz r1, r3 + 8000266: 2900 cmp r1, #0 + 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> + 800026a: 4573 cmp r3, lr + 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> + 800026e: 4282 cmp r2, r0 + 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> + 8000274: 1a84 subs r4, r0, r2 + 8000276: eb6e 0203 sbc.w r2, lr, r3 + 800027a: 2001 movs r0, #1 + 800027c: 4690 mov r8, r2 + 800027e: 2d00 cmp r5, #0 + 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> + 8000282: e9c5 4800 strd r4, r8, [r5] + 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> + 8000288: 2a00 cmp r2, #0 + 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> + 800028e: fab2 f682 clz r6, r2 + 8000292: 2e00 cmp r6, #0 + 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> + 8000298: 1a8a subs r2, r1, r2 + 800029a: 2101 movs r1, #1 + 800029c: 0c03 lsrs r3, r0, #16 + 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 + 80002a2: b280 uxth r0, r0 + 80002a4: b2bc uxth r4, r7 + 80002a6: fbb2 fcfe udiv ip, r2, lr + 80002aa: fb0e 221c mls r2, lr, ip, r2 + 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 + 80002b2: fb04 f20c mul.w r2, r4, ip + 80002b6: 429a cmp r2, r3 + 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> + 80002ba: 18fb adds r3, r7, r3 + 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff + 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> + 80002c2: 429a cmp r2, r3 + 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> + 80002c8: 46c4 mov ip, r8 + 80002ca: 1a9b subs r3, r3, r2 + 80002cc: fbb3 f2fe udiv r2, r3, lr + 80002d0: fb0e 3312 mls r3, lr, r2, r3 + 80002d4: fb02 f404 mul.w r4, r2, r4 + 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 + 80002dc: 429c cmp r4, r3 + 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> + 80002e0: 18fb adds r3, r7, r3 + 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff + 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> + 80002e8: 429c cmp r4, r3 + 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> + 80002ee: 4602 mov r2, r0 + 80002f0: 1b1b subs r3, r3, r4 + 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 + 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> + 80002f8: f1c1 0620 rsb r6, r1, #32 + 80002fc: 408b lsls r3, r1 + 80002fe: fa22 f706 lsr.w r7, r2, r6 + 8000302: 431f orrs r7, r3 + 8000304: fa2e fa06 lsr.w sl, lr, r6 + 8000308: ea4f 4917 mov.w r9, r7, lsr #16 + 800030c: fbba f8f9 udiv r8, sl, r9 + 8000310: fa0e fe01 lsl.w lr, lr, r1 + 8000314: fa20 f306 lsr.w r3, r0, r6 + 8000318: fb09 aa18 mls sl, r9, r8, sl + 800031c: fa1f fc87 uxth.w ip, r7 + 8000320: ea43 030e orr.w r3, r3, lr + 8000324: fa00 fe01 lsl.w lr, r0, r1 + 8000328: fb08 f00c mul.w r0, r8, ip + 800032c: 0c1c lsrs r4, r3, #16 + 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 + 8000332: 42a0 cmp r0, r4 + 8000334: fa02 f201 lsl.w r2, r2, r1 + 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> + 800033a: 193c adds r4, r7, r4 + 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff + 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> + 8000344: 42a0 cmp r0, r4 + 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> + 800034a: f1a8 0802 sub.w r8, r8, #2 + 800034e: 443c add r4, r7 + 8000350: 1a24 subs r4, r4, r0 + 8000352: b298 uxth r0, r3 + 8000354: fbb4 f3f9 udiv r3, r4, r9 + 8000358: fb09 4413 mls r4, r9, r3, r4 + 800035c: fb03 fc0c mul.w ip, r3, ip + 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 + 8000364: 45a4 cmp ip, r4 + 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> + 8000368: 193c adds r4, r7, r4 + 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff + 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> + 8000372: 45a4 cmp ip, r4 + 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> + 8000378: 3b02 subs r3, #2 + 800037a: 443c add r4, r7 + 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 + 8000380: eba4 040c sub.w r4, r4, ip + 8000384: fba0 8c02 umull r8, ip, r0, r2 + 8000388: 4564 cmp r4, ip + 800038a: 4643 mov r3, r8 + 800038c: 46e1 mov r9, ip + 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> + 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> + 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> + 8000394: ebbe 0203 subs.w r2, lr, r3 + 8000398: eb64 0409 sbc.w r4, r4, r9 + 800039c: fa04 f606 lsl.w r6, r4, r6 + 80003a0: fa22 f301 lsr.w r3, r2, r1 + 80003a4: 431e orrs r6, r3 + 80003a6: 40cc lsrs r4, r1 + 80003a8: e9c5 6400 strd r6, r4, [r5] + 80003ac: 2100 movs r1, #0 + 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> + 80003b0: fbb1 fcf2 udiv ip, r1, r2 + 80003b4: 0c01 lsrs r1, r0, #16 + 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 + 80003ba: b280 uxth r0, r0 + 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 + 80003c0: 463b mov r3, r7 + 80003c2: fbb1 f1f7 udiv r1, r1, r7 + 80003c6: 4638 mov r0, r7 + 80003c8: 463c mov r4, r7 + 80003ca: 46b8 mov r8, r7 + 80003cc: 46be mov lr, r7 + 80003ce: 2620 movs r6, #32 + 80003d0: eba2 0208 sub.w r2, r2, r8 + 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 + 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> + 80003da: 4601 mov r1, r0 + 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> + 80003de: 4610 mov r0, r2 + 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> + 80003e2: f1c6 0120 rsb r1, r6, #32 + 80003e6: fa2e fc01 lsr.w ip, lr, r1 + 80003ea: 40b7 lsls r7, r6 + 80003ec: fa0e fe06 lsl.w lr, lr, r6 + 80003f0: fa20 f101 lsr.w r1, r0, r1 + 80003f4: ea41 010e orr.w r1, r1, lr + 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 + 80003fc: fbbc f8fe udiv r8, ip, lr + 8000400: b2bc uxth r4, r7 + 8000402: fb0e cc18 mls ip, lr, r8, ip + 8000406: fb08 f904 mul.w r9, r8, r4 + 800040a: 0c0a lsrs r2, r1, #16 + 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 + 8000410: 40b0 lsls r0, r6 + 8000412: 4591 cmp r9, r2 + 8000414: ea4f 4310 mov.w r3, r0, lsr #16 + 8000418: b280 uxth r0, r0 + 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> + 800041c: 18ba adds r2, r7, r2 + 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff + 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> + 8000424: 4591 cmp r9, r2 + 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> + 8000428: eba2 0209 sub.w r2, r2, r9 + 800042c: fbb2 f9fe udiv r9, r2, lr + 8000430: fb09 f804 mul.w r8, r9, r4 + 8000434: fb0e 2a19 mls sl, lr, r9, r2 + 8000438: b28a uxth r2, r1 + 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 + 800043e: 4542 cmp r2, r8 + 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> + 8000442: 18ba adds r2, r7, r2 + 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff + 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044a: 4542 cmp r2, r8 + 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> + 800044e: f1a9 0102 sub.w r1, r9, #2 + 8000452: 443a add r2, r7 + 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> + 8000456: 45c6 cmp lr, r8 + 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> + 800045a: ebb8 0302 subs.w r3, r8, r2 + 800045e: eb6c 0c07 sbc.w ip, ip, r7 + 8000462: 3801 subs r0, #1 + 8000464: 46e1 mov r9, ip + 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> + 8000468: eba7 0909 sub.w r9, r7, r9 + 800046c: 444a add r2, r9 + 800046e: fbb2 f9fe udiv r9, r2, lr + 8000472: f1a8 0c02 sub.w ip, r8, #2 + 8000476: fb09 f804 mul.w r8, r9, r4 + 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> + 800047c: 4603 mov r3, r0 + 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> + 8000480: 46d0 mov r8, sl + 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> + 8000484: 4608 mov r0, r1 + 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> + 8000488: 443b add r3, r7 + 800048a: 3a02 subs r2, #2 + 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> + 800048e: f1ac 0c02 sub.w ip, ip, #2 + 8000492: 443b add r3, r7 + 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> + 8000496: 4649 mov r1, r9 + 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> + 800049a: eba2 0209 sub.w r2, r2, r9 + 800049e: fbb2 f9fe udiv r9, r2, lr + 80004a2: 46c4 mov ip, r8 + 80004a4: fb09 f804 mul.w r8, r9, r4 + 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> + 80004aa: bf00 nop + +080004ac <__aeabi_idiv0>: + 80004ac: 4770 bx lr + 80004ae: bf00 nop + +080004b0 : + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void affiche(uint8_t nombre) { + 80004b0: b580 push {r7, lr} + 80004b2: b084 sub sp, #16 + 80004b4: af00 add r7, sp, #0 + 80004b6: 4603 mov r3, r0 + 80004b8: 71fb strb r3, [r7, #7] + uint8_t compt_uni; + uint8_t compt_diz; + + compt_uni = nombre % 10; + 80004ba: 79fa ldrb r2, [r7, #7] + 80004bc: 4b13 ldr r3, [pc, #76] @ (800050c ) + 80004be: fba3 1302 umull r1, r3, r3, r2 + 80004c2: 08d9 lsrs r1, r3, #3 + 80004c4: 460b mov r3, r1 + 80004c6: 009b lsls r3, r3, #2 + 80004c8: 440b add r3, r1 + 80004ca: 005b lsls r3, r3, #1 + 80004cc: 1ad3 subs r3, r2, r3 + 80004ce: 73fb strb r3, [r7, #15] + compt_diz = nombre / 10; + 80004d0: 79fb ldrb r3, [r7, #7] + 80004d2: 4a0e ldr r2, [pc, #56] @ (800050c ) + 80004d4: fba2 2303 umull r2, r3, r2, r3 + 80004d8: 08db lsrs r3, r3, #3 + 80004da: 73bb strb r3, [r7, #14] + + MAX7219_DisplayChar(1, compt_diz); + 80004dc: 7bbb ldrb r3, [r7, #14] + 80004de: 4619 mov r1, r3 + 80004e0: 2001 movs r0, #1 + 80004e2: f000 fa0d bl 8000900 + MAX7219_DisplayChar(2, compt_uni); + 80004e6: 7bfb ldrb r3, [r7, #15] + 80004e8: 4619 mov r1, r3 + 80004ea: 2002 movs r0, #2 + 80004ec: f000 fa08 bl 8000900 + MAX7219_DisplayChar(3, compt_diz); + 80004f0: 7bbb ldrb r3, [r7, #14] + 80004f2: 4619 mov r1, r3 + 80004f4: 2003 movs r0, #3 + 80004f6: f000 fa03 bl 8000900 + MAX7219_DisplayChar(4, compt_uni); + 80004fa: 7bfb ldrb r3, [r7, #15] + 80004fc: 4619 mov r1, r3 + 80004fe: 2004 movs r0, #4 + 8000500: f000 f9fe bl 8000900 +} + 8000504: bf00 nop + 8000506: 3710 adds r7, #16 + 8000508: 46bd mov sp, r7 + 800050a: bd80 pop {r7, pc} + 800050c: cccccccd .word 0xcccccccd + +08000510