diff --git a/TP2_INIT_DISPLAY/Core/Src/main.c b/TP2_INIT_DISPLAY/Core/Src/main.c index bbc8317..c4da778 100644 --- a/TP2_INIT_DISPLAY/Core/Src/main.c +++ b/TP2_INIT_DISPLAY/Core/Src/main.c @@ -18,10 +18,11 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" -#include "max7219.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "max7219.h" +#define V2 /* USER CODE END Includes */ @@ -52,11 +53,24 @@ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_SPI1_Init(void); /* USER CODE BEGIN PFP */ +void affiche (uint8_t nombre); /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ +void affiche(uint8_t nombre) { + uint8_t compt_uni; + uint8_t compt_diz; + + compt_uni = nombre % 10; + compt_diz = nombre / 10; + + MAX7219_DisplayChar(1, compt_diz); + MAX7219_DisplayChar(2, compt_uni); + MAX7219_DisplayChar(3, compt_diz); + MAX7219_DisplayChar(4, compt_uni); +} /* USER CODE END 0 */ @@ -99,13 +113,24 @@ int main(void) /* Infinite loop */ /* USER CODE BEGIN WHILE */ MAX7219_Clear(); + uint8_t compteur = 0; while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ +#ifdef V1 MAX7219_DisplayChar(1, 3); MAX7219_DisplayChar(2, 5); +#endif +#ifdef V2 + affiche(compteur); + compteur++; + if (compteur >= 100) { + compteur = 0; + } + HAL_Delay(500); +#endif } /* USER CODE END 3 */ } diff --git a/TP2_INIT_DISPLAY/Debug/Core/Src/main.cyclo b/TP2_INIT_DISPLAY/Debug/Core/Src/main.cyclo index 87373a2..8cf01c7 100644 --- a/TP2_INIT_DISPLAY/Debug/Core/Src/main.cyclo +++ b/TP2_INIT_DISPLAY/Debug/Core/Src/main.cyclo @@ -1,5 +1,6 @@ -../Core/Src/main.c:67:5:main 1 -../Core/Src/main.c:117:6:SystemClock_Config 3 -../Core/Src/main.c:158:13:MX_SPI1_Init 2 -../Core/Src/main.c:196:13:MX_GPIO_Init 1 -../Core/Src/main.c:230:6:Error_Handler 1 +../Core/Src/main.c:62:6:affiche 1 +../Core/Src/main.c:81:5:main 2 +../Core/Src/main.c:142:6:SystemClock_Config 3 +../Core/Src/main.c:183:13:MX_SPI1_Init 2 +../Core/Src/main.c:221:13:MX_GPIO_Init 1 +../Core/Src/main.c:255:6:Error_Handler 1 diff --git a/TP2_INIT_DISPLAY/Debug/Core/Src/main.o b/TP2_INIT_DISPLAY/Debug/Core/Src/main.o index 50e3553..078064b 100644 Binary files a/TP2_INIT_DISPLAY/Debug/Core/Src/main.o and b/TP2_INIT_DISPLAY/Debug/Core/Src/main.o differ diff --git a/TP2_INIT_DISPLAY/Debug/Core/Src/main.su b/TP2_INIT_DISPLAY/Debug/Core/Src/main.su index a34b05d..3ad3a16 100644 --- a/TP2_INIT_DISPLAY/Debug/Core/Src/main.su +++ b/TP2_INIT_DISPLAY/Debug/Core/Src/main.su @@ -1,5 +1,6 @@ -../Core/Src/main.c:67:5:main 8 static -../Core/Src/main.c:117:6:SystemClock_Config 80 static -../Core/Src/main.c:158:13:MX_SPI1_Init 8 static -../Core/Src/main.c:196:13:MX_GPIO_Init 40 static -../Core/Src/main.c:230:6:Error_Handler 4 static,ignoring_inline_asm +../Core/Src/main.c:62:6:affiche 24 static +../Core/Src/main.c:81:5:main 16 static +../Core/Src/main.c:142:6:SystemClock_Config 80 static +../Core/Src/main.c:183:13:MX_SPI1_Init 8 static +../Core/Src/main.c:221:13:MX_GPIO_Init 40 static +../Core/Src/main.c:255:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.elf b/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.elf index 38e1f4e..df74ea3 100755 Binary files a/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.elf and b/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.elf differ diff --git a/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.list b/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.list index e8d8a6c..b4aed8b 100644 --- a/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.list +++ b/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.list @@ -5,47 +5,47 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00001e98 0800013c 0800013c 0000113c 2**2 + 1 .text 00001f50 0800013c 0800013c 0000113c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 0000002c 08001fd4 08001fd4 00002fd4 2**2 + 2 .rodata 0000002c 0800208c 0800208c 0000308c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08002000 08002000 0000400c 2**0 + 3 .ARM.extab 00000000 080020b8 080020b8 0000400c 2**0 CONTENTS, READONLY - 4 .ARM 00000008 08002000 08002000 00003000 2**2 + 4 .ARM 00000008 080020b8 080020b8 000030b8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08002008 08002008 0000400c 2**0 + 5 .preinit_array 00000000 080020c0 080020c0 0000400c 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08002008 08002008 00003008 2**2 + 6 .init_array 00000004 080020c0 080020c0 000030c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 7 .fini_array 00000004 0800200c 0800200c 0000300c 2**2 + 7 .fini_array 00000004 080020c4 080020c4 000030c4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 8 .data 0000000c 20000000 08002010 00004000 2**2 + 8 .data 0000000c 20000000 080020c8 00004000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 00000078 2000000c 0800201c 0000400c 2**2 + 9 .bss 00000078 2000000c 080020d4 0000400c 2**2 ALLOC - 10 ._user_heap_stack 00000604 20000084 0800201c 00004084 2**0 + 10 ._user_heap_stack 00000604 20000084 080020d4 00004084 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0 CONTENTS, READONLY - 12 .debug_info 000056d5 00000000 00000000 00004035 2**0 + 12 .debug_info 0000573e 00000000 00000000 00004035 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 0000144c 00000000 00000000 0000970a 2**0 + 13 .debug_abbrev 0000145f 00000000 00000000 00009773 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 00000658 00000000 00000000 0000ab58 2**3 + 14 .debug_aranges 00000660 00000000 00000000 0000abd8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_rnglists 000004ae 00000000 00000000 0000b1b0 2**0 + 15 .debug_rnglists 000004b4 00000000 00000000 0000b238 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 00014998 00000000 00000000 0000b65e 2**0 + 16 .debug_macro 0001499e 00000000 00000000 0000b6ec 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 00006f98 00000000 00000000 0001fff6 2**0 + 17 .debug_line 00006fc2 00000000 00000000 0002008a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 00081117 00000000 00000000 00026f8e 2**0 + 18 .debug_str 00081143 00000000 00000000 0002704c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000043 00000000 00000000 000a80a5 2**0 + 19 .comment 00000043 00000000 00000000 000a818f 2**0 CONTENTS, READONLY - 20 .debug_frame 00001884 00000000 00000000 000a80e8 2**2 + 20 .debug_frame 000018ac 00000000 00000000 000a81d4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 00000070 00000000 00000000 000a996c 2**0 + 21 .debug_line_str 00000070 00000000 00000000 000a9a80 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -64,7 +64,7 @@ Disassembly of section .text: 8000152: bd10 pop {r4, pc} 8000154: 2000000c .word 0x2000000c 8000158: 00000000 .word 0x00000000 - 800015c: 08001fbc .word 0x08001fbc + 800015c: 08002074 .word 0x08002074 08000160 : 8000160: b508 push {r3, lr} @@ -76,7 +76,7 @@ Disassembly of section .text: 800016e: bd08 pop {r3, pc} 8000170: 00000000 .word 0x00000000 8000174: 20000010 .word 0x20000010 - 8000178: 08001fbc .word 0x08001fbc + 8000178: 08002074 .word 0x08002074 0800017c <__aeabi_uldivmod>: 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> @@ -370,4960 +370,5085 @@ Disassembly of section .text: 80004ac: 4770 bx lr 80004ae: bf00 nop -080004b0
: +080004b0 : + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void affiche(uint8_t nombre) { + 80004b0: b580 push {r7, lr} + 80004b2: b084 sub sp, #16 + 80004b4: af00 add r7, sp, #0 + 80004b6: 4603 mov r3, r0 + 80004b8: 71fb strb r3, [r7, #7] + uint8_t compt_uni; + uint8_t compt_diz; + + compt_uni = nombre % 10; + 80004ba: 79fa ldrb r2, [r7, #7] + 80004bc: 4b13 ldr r3, [pc, #76] @ (800050c ) + 80004be: fba3 1302 umull r1, r3, r3, r2 + 80004c2: 08d9 lsrs r1, r3, #3 + 80004c4: 460b mov r3, r1 + 80004c6: 009b lsls r3, r3, #2 + 80004c8: 440b add r3, r1 + 80004ca: 005b lsls r3, r3, #1 + 80004cc: 1ad3 subs r3, r2, r3 + 80004ce: 73fb strb r3, [r7, #15] + compt_diz = nombre / 10; + 80004d0: 79fb ldrb r3, [r7, #7] + 80004d2: 4a0e ldr r2, [pc, #56] @ (800050c ) + 80004d4: fba2 2303 umull r2, r3, r2, r3 + 80004d8: 08db lsrs r3, r3, #3 + 80004da: 73bb strb r3, [r7, #14] + + MAX7219_DisplayChar(1, compt_diz); + 80004dc: 7bbb ldrb r3, [r7, #14] + 80004de: 4619 mov r1, r3 + 80004e0: 2001 movs r0, #1 + 80004e2: f000 fa0d bl 8000900 + MAX7219_DisplayChar(2, compt_uni); + 80004e6: 7bfb ldrb r3, [r7, #15] + 80004e8: 4619 mov r1, r3 + 80004ea: 2002 movs r0, #2 + 80004ec: f000 fa08 bl 8000900 + MAX7219_DisplayChar(3, compt_diz); + 80004f0: 7bbb ldrb r3, [r7, #14] + 80004f2: 4619 mov r1, r3 + 80004f4: 2003 movs r0, #3 + 80004f6: f000 fa03 bl 8000900 + MAX7219_DisplayChar(4, compt_uni); + 80004fa: 7bfb ldrb r3, [r7, #15] + 80004fc: 4619 mov r1, r3 + 80004fe: 2004 movs r0, #4 + 8000500: f000 f9fe bl 8000900 +} + 8000504: bf00 nop + 8000506: 3710 adds r7, #16 + 8000508: 46bd mov sp, r7 + 800050a: bd80 pop {r7, pc} + 800050c: cccccccd .word 0xcccccccd + +08000510
: /** * @brief The application entry point. * @retval int */ int main(void) { - 80004b0: b580 push {r7, lr} - 80004b2: af00 add r7, sp, #0 + 8000510: b580 push {r7, lr} + 8000512: b082 sub sp, #8 + 8000514: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 80004b4: f000 fa30 bl 8000918 + 8000516: f000 fa39 bl 800098c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 80004b8: f000 f812 bl 80004e0 + 800051a: f000 f81b bl 8000554 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 80004bc: f000 f88c bl 80005d8 + 800051e: f000 f895 bl 800064c MX_SPI1_Init(); - 80004c0: f000 f854 bl 800056c + 8000522: f000 f85d bl 80005e0 /* USER CODE BEGIN 2 */ MAX7219_Init(); - 80004c4: f000 f995 bl 80007f2 + 8000526: f000 f99e bl 8000866 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ MAX7219_Clear(); - 80004c8: f000 f9ca bl 8000860 - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ + 800052a: f000 f9d3 bl 80008d4 + uint8_t compteur = 0; + 800052e: 2300 movs r3, #0 + 8000530: 71fb strb r3, [r7, #7] +#ifdef V1 MAX7219_DisplayChar(1, 3); - 80004cc: 2103 movs r1, #3 - 80004ce: 2001 movs r0, #1 - 80004d0: f000 f9dc bl 800088c MAX7219_DisplayChar(2, 5); - 80004d4: 2105 movs r1, #5 - 80004d6: 2002 movs r0, #2 - 80004d8: f000 f9d8 bl 800088c - MAX7219_DisplayChar(1, 3); - 80004dc: bf00 nop - 80004de: e7f5 b.n 80004cc +#endif +#ifdef V2 + affiche(compteur); + 8000532: 79fb ldrb r3, [r7, #7] + 8000534: 4618 mov r0, r3 + 8000536: f7ff ffbb bl 80004b0 + compteur++; + 800053a: 79fb ldrb r3, [r7, #7] + 800053c: 3301 adds r3, #1 + 800053e: 71fb strb r3, [r7, #7] + if (compteur >= 100) { + 8000540: 79fb ldrb r3, [r7, #7] + 8000542: 2b63 cmp r3, #99 @ 0x63 + 8000544: d901 bls.n 800054a + compteur = 0; + 8000546: 2300 movs r3, #0 + 8000548: 71fb strb r3, [r7, #7] + } + HAL_Delay(500); + 800054a: f44f 70fa mov.w r0, #500 @ 0x1f4 + 800054e: f000 fa8b bl 8000a68 + affiche(compteur); + 8000552: e7ee b.n 8000532 -080004e0 : +08000554 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 80004e0: b580 push {r7, lr} - 80004e2: b092 sub sp, #72 @ 0x48 - 80004e4: af00 add r7, sp, #0 + 8000554: b580 push {r7, lr} + 8000556: b092 sub sp, #72 @ 0x48 + 8000558: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 80004e6: f107 0314 add.w r3, r7, #20 - 80004ea: 2234 movs r2, #52 @ 0x34 - 80004ec: 2100 movs r1, #0 - 80004ee: 4618 mov r0, r3 - 80004f0: f001 fd38 bl 8001f64 + 800055a: f107 0314 add.w r3, r7, #20 + 800055e: 2234 movs r2, #52 @ 0x34 + 8000560: 2100 movs r1, #0 + 8000562: 4618 mov r0, r3 + 8000564: f001 fd5a bl 800201c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 80004f4: 463b mov r3, r7 - 80004f6: 2200 movs r2, #0 - 80004f8: 601a str r2, [r3, #0] - 80004fa: 605a str r2, [r3, #4] - 80004fc: 609a str r2, [r3, #8] - 80004fe: 60da str r2, [r3, #12] - 8000500: 611a str r2, [r3, #16] + 8000568: 463b mov r3, r7 + 800056a: 2200 movs r2, #0 + 800056c: 601a str r2, [r3, #0] + 800056e: 605a str r2, [r3, #4] + 8000570: 609a str r2, [r3, #8] + 8000572: 60da str r2, [r3, #12] + 8000574: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 8000502: 4b19 ldr r3, [pc, #100] @ (8000568 ) - 8000504: 681b ldr r3, [r3, #0] - 8000506: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 - 800050a: 4a17 ldr r2, [pc, #92] @ (8000568 ) - 800050c: f443 6300 orr.w r3, r3, #2048 @ 0x800 - 8000510: 6013 str r3, [r2, #0] + 8000576: 4b19 ldr r3, [pc, #100] @ (80005dc ) + 8000578: 681b ldr r3, [r3, #0] + 800057a: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 + 800057e: 4a17 ldr r2, [pc, #92] @ (80005dc ) + 8000580: f443 6300 orr.w r3, r3, #2048 @ 0x800 + 8000584: 6013 str r3, [r2, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - 8000512: 2302 movs r3, #2 - 8000514: 617b str r3, [r7, #20] + 8000586: 2302 movs r3, #2 + 8000588: 617b str r3, [r7, #20] RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 8000516: 2301 movs r3, #1 - 8000518: 623b str r3, [r7, #32] + 800058a: 2301 movs r3, #1 + 800058c: 623b str r3, [r7, #32] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - 800051a: 2310 movs r3, #16 - 800051c: 627b str r3, [r7, #36] @ 0x24 + 800058e: 2310 movs r3, #16 + 8000590: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - 800051e: 2300 movs r3, #0 - 8000520: 63bb str r3, [r7, #56] @ 0x38 + 8000592: 2300 movs r3, #0 + 8000594: 63bb str r3, [r7, #56] @ 0x38 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 8000522: f107 0314 add.w r3, r7, #20 - 8000526: 4618 mov r0, r3 - 8000528: f000 fcf0 bl 8000f0c - 800052c: 4603 mov r3, r0 - 800052e: 2b00 cmp r3, #0 - 8000530: d001 beq.n 8000536 + 8000596: f107 0314 add.w r3, r7, #20 + 800059a: 4618 mov r0, r3 + 800059c: f000 fd12 bl 8000fc4 + 80005a0: 4603 mov r3, r0 + 80005a2: 2b00 cmp r3, #0 + 80005a4: d001 beq.n 80005aa { Error_Handler(); - 8000532: f000 f88f bl 8000654 + 80005a6: f000 f88f bl 80006c8 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 8000536: 230f movs r3, #15 - 8000538: 603b str r3, [r7, #0] + 80005aa: 230f movs r3, #15 + 80005ac: 603b str r3, [r7, #0] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - 800053a: 2301 movs r3, #1 - 800053c: 607b str r3, [r7, #4] + 80005ae: 2301 movs r3, #1 + 80005b0: 607b str r3, [r7, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 800053e: 2300 movs r3, #0 - 8000540: 60bb str r3, [r7, #8] + 80005b2: 2300 movs r3, #0 + 80005b4: 60bb str r3, [r7, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 8000542: 2300 movs r3, #0 - 8000544: 60fb str r3, [r7, #12] + 80005b6: 2300 movs r3, #0 + 80005b8: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 8000546: 2300 movs r3, #0 - 8000548: 613b str r3, [r7, #16] + 80005ba: 2300 movs r3, #0 + 80005bc: 613b str r3, [r7, #16] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - 800054a: 463b mov r3, r7 - 800054c: 2100 movs r1, #0 - 800054e: 4618 mov r0, r3 - 8000550: f001 f80c bl 800156c - 8000554: 4603 mov r3, r0 - 8000556: 2b00 cmp r3, #0 - 8000558: d001 beq.n 800055e + 80005be: 463b mov r3, r7 + 80005c0: 2100 movs r1, #0 + 80005c2: 4618 mov r0, r3 + 80005c4: f001 f82e bl 8001624 + 80005c8: 4603 mov r3, r0 + 80005ca: 2b00 cmp r3, #0 + 80005cc: d001 beq.n 80005d2 { Error_Handler(); - 800055a: f000 f87b bl 8000654 + 80005ce: f000 f87b bl 80006c8 } } - 800055e: bf00 nop - 8000560: 3748 adds r7, #72 @ 0x48 - 8000562: 46bd mov sp, r7 - 8000564: bd80 pop {r7, pc} - 8000566: bf00 nop - 8000568: 40007000 .word 0x40007000 + 80005d2: bf00 nop + 80005d4: 3748 adds r7, #72 @ 0x48 + 80005d6: 46bd mov sp, r7 + 80005d8: bd80 pop {r7, pc} + 80005da: bf00 nop + 80005dc: 40007000 .word 0x40007000 -0800056c : +080005e0 : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { - 800056c: b580 push {r7, lr} - 800056e: af00 add r7, sp, #0 + 80005e0: b580 push {r7, lr} + 80005e2: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; - 8000570: 4b17 ldr r3, [pc, #92] @ (80005d0 ) - 8000572: 4a18 ldr r2, [pc, #96] @ (80005d4 ) - 8000574: 601a str r2, [r3, #0] + 80005e4: 4b17 ldr r3, [pc, #92] @ (8000644 ) + 80005e6: 4a18 ldr r2, [pc, #96] @ (8000648 ) + 80005e8: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; - 8000576: 4b16 ldr r3, [pc, #88] @ (80005d0 ) - 8000578: f44f 7282 mov.w r2, #260 @ 0x104 - 800057c: 605a str r2, [r3, #4] + 80005ea: 4b16 ldr r3, [pc, #88] @ (8000644 ) + 80005ec: f44f 7282 mov.w r2, #260 @ 0x104 + 80005f0: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; - 800057e: 4b14 ldr r3, [pc, #80] @ (80005d0 ) - 8000580: 2200 movs r2, #0 - 8000582: 609a str r2, [r3, #8] + 80005f2: 4b14 ldr r3, [pc, #80] @ (8000644 ) + 80005f4: 2200 movs r2, #0 + 80005f6: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; - 8000584: 4b12 ldr r3, [pc, #72] @ (80005d0 ) - 8000586: 2200 movs r2, #0 - 8000588: 60da str r2, [r3, #12] + 80005f8: 4b12 ldr r3, [pc, #72] @ (8000644 ) + 80005fa: 2200 movs r2, #0 + 80005fc: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; - 800058a: 4b11 ldr r3, [pc, #68] @ (80005d0 ) - 800058c: 2200 movs r2, #0 - 800058e: 611a str r2, [r3, #16] + 80005fe: 4b11 ldr r3, [pc, #68] @ (8000644 ) + 8000600: 2200 movs r2, #0 + 8000602: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; - 8000590: 4b0f ldr r3, [pc, #60] @ (80005d0 ) - 8000592: 2200 movs r2, #0 - 8000594: 615a str r2, [r3, #20] + 8000604: 4b0f ldr r3, [pc, #60] @ (8000644 ) + 8000606: 2200 movs r2, #0 + 8000608: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; - 8000596: 4b0e ldr r3, [pc, #56] @ (80005d0 ) - 8000598: f44f 7200 mov.w r2, #512 @ 0x200 - 800059c: 619a str r2, [r3, #24] + 800060a: 4b0e ldr r3, [pc, #56] @ (8000644 ) + 800060c: f44f 7200 mov.w r2, #512 @ 0x200 + 8000610: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; - 800059e: 4b0c ldr r3, [pc, #48] @ (80005d0 ) - 80005a0: 2200 movs r2, #0 - 80005a2: 61da str r2, [r3, #28] + 8000612: 4b0c ldr r3, [pc, #48] @ (8000644 ) + 8000614: 2200 movs r2, #0 + 8000616: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; - 80005a4: 4b0a ldr r3, [pc, #40] @ (80005d0 ) - 80005a6: 2200 movs r2, #0 - 80005a8: 621a str r2, [r3, #32] + 8000618: 4b0a ldr r3, [pc, #40] @ (8000644 ) + 800061a: 2200 movs r2, #0 + 800061c: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; - 80005aa: 4b09 ldr r3, [pc, #36] @ (80005d0 ) - 80005ac: 2200 movs r2, #0 - 80005ae: 625a str r2, [r3, #36] @ 0x24 + 800061e: 4b09 ldr r3, [pc, #36] @ (8000644 ) + 8000620: 2200 movs r2, #0 + 8000622: 625a str r2, [r3, #36] @ 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - 80005b0: 4b07 ldr r3, [pc, #28] @ (80005d0 ) - 80005b2: 2200 movs r2, #0 - 80005b4: 629a str r2, [r3, #40] @ 0x28 + 8000624: 4b07 ldr r3, [pc, #28] @ (8000644 ) + 8000626: 2200 movs r2, #0 + 8000628: 629a str r2, [r3, #40] @ 0x28 hspi1.Init.CRCPolynomial = 10; - 80005b6: 4b06 ldr r3, [pc, #24] @ (80005d0 ) - 80005b8: 220a movs r2, #10 - 80005ba: 62da str r2, [r3, #44] @ 0x2c + 800062a: 4b06 ldr r3, [pc, #24] @ (8000644 ) + 800062c: 220a movs r2, #10 + 800062e: 62da str r2, [r3, #44] @ 0x2c if (HAL_SPI_Init(&hspi1) != HAL_OK) - 80005bc: 4804 ldr r0, [pc, #16] @ (80005d0 ) - 80005be: f001 fa27 bl 8001a10 - 80005c2: 4603 mov r3, r0 - 80005c4: 2b00 cmp r3, #0 - 80005c6: d001 beq.n 80005cc + 8000630: 4804 ldr r0, [pc, #16] @ (8000644 ) + 8000632: f001 fa49 bl 8001ac8 + 8000636: 4603 mov r3, r0 + 8000638: 2b00 cmp r3, #0 + 800063a: d001 beq.n 8000640 { Error_Handler(); - 80005c8: f000 f844 bl 8000654 + 800063c: f000 f844 bl 80006c8 } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } - 80005cc: bf00 nop - 80005ce: bd80 pop {r7, pc} - 80005d0: 20000028 .word 0x20000028 - 80005d4: 40013000 .word 0x40013000 + 8000640: bf00 nop + 8000642: bd80 pop {r7, pc} + 8000644: 20000028 .word 0x20000028 + 8000648: 40013000 .word 0x40013000 -080005d8 : +0800064c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 80005d8: b580 push {r7, lr} - 80005da: b088 sub sp, #32 - 80005dc: af00 add r7, sp, #0 + 800064c: b580 push {r7, lr} + 800064e: b088 sub sp, #32 + 8000650: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80005de: f107 030c add.w r3, r7, #12 - 80005e2: 2200 movs r2, #0 - 80005e4: 601a str r2, [r3, #0] - 80005e6: 605a str r2, [r3, #4] - 80005e8: 609a str r2, [r3, #8] - 80005ea: 60da str r2, [r3, #12] - 80005ec: 611a str r2, [r3, #16] + 8000652: f107 030c add.w r3, r7, #12 + 8000656: 2200 movs r2, #0 + 8000658: 601a str r2, [r3, #0] + 800065a: 605a str r2, [r3, #4] + 800065c: 609a str r2, [r3, #8] + 800065e: 60da str r2, [r3, #12] + 8000660: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); - 80005ee: 4b17 ldr r3, [pc, #92] @ (800064c ) - 80005f0: 69db ldr r3, [r3, #28] - 80005f2: 4a16 ldr r2, [pc, #88] @ (800064c ) - 80005f4: f043 0304 orr.w r3, r3, #4 - 80005f8: 61d3 str r3, [r2, #28] - 80005fa: 4b14 ldr r3, [pc, #80] @ (800064c ) - 80005fc: 69db ldr r3, [r3, #28] - 80005fe: f003 0304 and.w r3, r3, #4 - 8000602: 60bb str r3, [r7, #8] - 8000604: 68bb ldr r3, [r7, #8] + 8000662: 4b17 ldr r3, [pc, #92] @ (80006c0 ) + 8000664: 69db ldr r3, [r3, #28] + 8000666: 4a16 ldr r2, [pc, #88] @ (80006c0 ) + 8000668: f043 0304 orr.w r3, r3, #4 + 800066c: 61d3 str r3, [r2, #28] + 800066e: 4b14 ldr r3, [pc, #80] @ (80006c0 ) + 8000670: 69db ldr r3, [r3, #28] + 8000672: f003 0304 and.w r3, r3, #4 + 8000676: 60bb str r3, [r7, #8] + 8000678: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000606: 4b11 ldr r3, [pc, #68] @ (800064c ) - 8000608: 69db ldr r3, [r3, #28] - 800060a: 4a10 ldr r2, [pc, #64] @ (800064c ) - 800060c: f043 0301 orr.w r3, r3, #1 - 8000610: 61d3 str r3, [r2, #28] - 8000612: 4b0e ldr r3, [pc, #56] @ (800064c ) - 8000614: 69db ldr r3, [r3, #28] - 8000616: f003 0301 and.w r3, r3, #1 - 800061a: 607b str r3, [r7, #4] - 800061c: 687b ldr r3, [r7, #4] + 800067a: 4b11 ldr r3, [pc, #68] @ (80006c0 ) + 800067c: 69db ldr r3, [r3, #28] + 800067e: 4a10 ldr r2, [pc, #64] @ (80006c0 ) + 8000680: f043 0301 orr.w r3, r3, #1 + 8000684: 61d3 str r3, [r2, #28] + 8000686: 4b0e ldr r3, [pc, #56] @ (80006c0 ) + 8000688: 69db ldr r3, [r3, #28] + 800068a: f003 0301 and.w r3, r3, #1 + 800068e: 607b str r3, [r7, #4] + 8000690: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET); - 800061e: 2200 movs r2, #0 - 8000620: 2101 movs r1, #1 - 8000622: 480b ldr r0, [pc, #44] @ (8000650 ) - 8000624: f000 fc5a bl 8000edc + 8000692: 2200 movs r2, #0 + 8000694: 2101 movs r1, #1 + 8000696: 480b ldr r0, [pc, #44] @ (80006c4 ) + 8000698: f000 fc7c bl 8000f94 /*Configure GPIO pin : PC0 */ GPIO_InitStruct.Pin = GPIO_PIN_0; - 8000628: 2301 movs r3, #1 - 800062a: 60fb str r3, [r7, #12] + 800069c: 2301 movs r3, #1 + 800069e: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 800062c: 2301 movs r3, #1 - 800062e: 613b str r3, [r7, #16] + 80006a0: 2301 movs r3, #1 + 80006a2: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000630: 2300 movs r3, #0 - 8000632: 617b str r3, [r7, #20] + 80006a4: 2300 movs r3, #0 + 80006a6: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000634: 2300 movs r3, #0 - 8000636: 61bb str r3, [r7, #24] + 80006a8: 2300 movs r3, #0 + 80006aa: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8000638: f107 030c add.w r3, r7, #12 - 800063c: 4619 mov r1, r3 - 800063e: 4804 ldr r0, [pc, #16] @ (8000650 ) - 8000640: f000 fabc bl 8000bbc + 80006ac: f107 030c add.w r3, r7, #12 + 80006b0: 4619 mov r1, r3 + 80006b2: 4804 ldr r0, [pc, #16] @ (80006c4 ) + 80006b4: f000 fade bl 8000c74 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } - 8000644: bf00 nop - 8000646: 3720 adds r7, #32 - 8000648: 46bd mov sp, r7 - 800064a: bd80 pop {r7, pc} - 800064c: 40023800 .word 0x40023800 - 8000650: 40020800 .word 0x40020800 + 80006b8: bf00 nop + 80006ba: 3720 adds r7, #32 + 80006bc: 46bd mov sp, r7 + 80006be: bd80 pop {r7, pc} + 80006c0: 40023800 .word 0x40023800 + 80006c4: 40020800 .word 0x40020800 -08000654 : +080006c8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 8000654: b480 push {r7} - 8000656: af00 add r7, sp, #0 + 80006c8: b480 push {r7} + 80006ca: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 8000658: b672 cpsid i + 80006cc: b672 cpsid i } - 800065a: bf00 nop + 80006ce: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 800065c: bf00 nop - 800065e: e7fd b.n 800065c + 80006d0: bf00 nop + 80006d2: e7fd b.n 80006d0 -08000660 : +080006d4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8000660: b480 push {r7} - 8000662: b085 sub sp, #20 - 8000664: af00 add r7, sp, #0 + 80006d4: b480 push {r7} + 80006d6: b085 sub sp, #20 + 80006d8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_COMP_CLK_ENABLE(); - 8000666: 4b14 ldr r3, [pc, #80] @ (80006b8 ) - 8000668: 6a5b ldr r3, [r3, #36] @ 0x24 - 800066a: 4a13 ldr r2, [pc, #76] @ (80006b8 ) - 800066c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 - 8000670: 6253 str r3, [r2, #36] @ 0x24 - 8000672: 4b11 ldr r3, [pc, #68] @ (80006b8 ) - 8000674: 6a5b ldr r3, [r3, #36] @ 0x24 - 8000676: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 - 800067a: 60fb str r3, [r7, #12] - 800067c: 68fb ldr r3, [r7, #12] + 80006da: 4b14 ldr r3, [pc, #80] @ (800072c ) + 80006dc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80006de: 4a13 ldr r2, [pc, #76] @ (800072c ) + 80006e0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 + 80006e4: 6253 str r3, [r2, #36] @ 0x24 + 80006e6: 4b11 ldr r3, [pc, #68] @ (800072c ) + 80006e8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80006ea: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 80006ee: 60fb str r3, [r7, #12] + 80006f0: 68fb ldr r3, [r7, #12] __HAL_RCC_SYSCFG_CLK_ENABLE(); - 800067e: 4b0e ldr r3, [pc, #56] @ (80006b8 ) - 8000680: 6a1b ldr r3, [r3, #32] - 8000682: 4a0d ldr r2, [pc, #52] @ (80006b8 ) - 8000684: f043 0301 orr.w r3, r3, #1 - 8000688: 6213 str r3, [r2, #32] - 800068a: 4b0b ldr r3, [pc, #44] @ (80006b8 ) - 800068c: 6a1b ldr r3, [r3, #32] - 800068e: f003 0301 and.w r3, r3, #1 - 8000692: 60bb str r3, [r7, #8] - 8000694: 68bb ldr r3, [r7, #8] + 80006f2: 4b0e ldr r3, [pc, #56] @ (800072c ) + 80006f4: 6a1b ldr r3, [r3, #32] + 80006f6: 4a0d ldr r2, [pc, #52] @ (800072c ) + 80006f8: f043 0301 orr.w r3, r3, #1 + 80006fc: 6213 str r3, [r2, #32] + 80006fe: 4b0b ldr r3, [pc, #44] @ (800072c ) + 8000700: 6a1b ldr r3, [r3, #32] + 8000702: f003 0301 and.w r3, r3, #1 + 8000706: 60bb str r3, [r7, #8] + 8000708: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); - 8000696: 4b08 ldr r3, [pc, #32] @ (80006b8 ) - 8000698: 6a5b ldr r3, [r3, #36] @ 0x24 - 800069a: 4a07 ldr r2, [pc, #28] @ (80006b8 ) - 800069c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 80006a0: 6253 str r3, [r2, #36] @ 0x24 - 80006a2: 4b05 ldr r3, [pc, #20] @ (80006b8 ) - 80006a4: 6a5b ldr r3, [r3, #36] @ 0x24 - 80006a6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80006aa: 607b str r3, [r7, #4] - 80006ac: 687b ldr r3, [r7, #4] + 800070a: 4b08 ldr r3, [pc, #32] @ (800072c ) + 800070c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800070e: 4a07 ldr r2, [pc, #28] @ (800072c ) + 8000710: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8000714: 6253 str r3, [r2, #36] @ 0x24 + 8000716: 4b05 ldr r3, [pc, #20] @ (800072c ) + 8000718: 6a5b ldr r3, [r3, #36] @ 0x24 + 800071a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800071e: 607b str r3, [r7, #4] + 8000720: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 80006ae: bf00 nop - 80006b0: 3714 adds r7, #20 - 80006b2: 46bd mov sp, r7 - 80006b4: bc80 pop {r7} - 80006b6: 4770 bx lr - 80006b8: 40023800 .word 0x40023800 + 8000722: bf00 nop + 8000724: 3714 adds r7, #20 + 8000726: 46bd mov sp, r7 + 8000728: bc80 pop {r7} + 800072a: 4770 bx lr + 800072c: 40023800 .word 0x40023800 -080006bc : +08000730 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { - 80006bc: b580 push {r7, lr} - 80006be: b08a sub sp, #40 @ 0x28 - 80006c0: af00 add r7, sp, #0 - 80006c2: 6078 str r0, [r7, #4] + 8000730: b580 push {r7, lr} + 8000732: b08a sub sp, #40 @ 0x28 + 8000734: af00 add r7, sp, #0 + 8000736: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80006c4: f107 0314 add.w r3, r7, #20 - 80006c8: 2200 movs r2, #0 - 80006ca: 601a str r2, [r3, #0] - 80006cc: 605a str r2, [r3, #4] - 80006ce: 609a str r2, [r3, #8] - 80006d0: 60da str r2, [r3, #12] - 80006d2: 611a str r2, [r3, #16] + 8000738: f107 0314 add.w r3, r7, #20 + 800073c: 2200 movs r2, #0 + 800073e: 601a str r2, [r3, #0] + 8000740: 605a str r2, [r3, #4] + 8000742: 609a str r2, [r3, #8] + 8000744: 60da str r2, [r3, #12] + 8000746: 611a str r2, [r3, #16] if(hspi->Instance==SPI1) - 80006d4: 687b ldr r3, [r7, #4] - 80006d6: 681b ldr r3, [r3, #0] - 80006d8: 4a17 ldr r2, [pc, #92] @ (8000738 ) - 80006da: 4293 cmp r3, r2 - 80006dc: d127 bne.n 800072e + 8000748: 687b ldr r3, [r7, #4] + 800074a: 681b ldr r3, [r3, #0] + 800074c: 4a17 ldr r2, [pc, #92] @ (80007ac ) + 800074e: 4293 cmp r3, r2 + 8000750: d127 bne.n 80007a2 { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); - 80006de: 4b17 ldr r3, [pc, #92] @ (800073c ) - 80006e0: 6a1b ldr r3, [r3, #32] - 80006e2: 4a16 ldr r2, [pc, #88] @ (800073c ) - 80006e4: f443 5380 orr.w r3, r3, #4096 @ 0x1000 - 80006e8: 6213 str r3, [r2, #32] - 80006ea: 4b14 ldr r3, [pc, #80] @ (800073c ) - 80006ec: 6a1b ldr r3, [r3, #32] - 80006ee: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 80006f2: 613b str r3, [r7, #16] - 80006f4: 693b ldr r3, [r7, #16] + 8000752: 4b17 ldr r3, [pc, #92] @ (80007b0 ) + 8000754: 6a1b ldr r3, [r3, #32] + 8000756: 4a16 ldr r2, [pc, #88] @ (80007b0 ) + 8000758: f443 5380 orr.w r3, r3, #4096 @ 0x1000 + 800075c: 6213 str r3, [r2, #32] + 800075e: 4b14 ldr r3, [pc, #80] @ (80007b0 ) + 8000760: 6a1b ldr r3, [r3, #32] + 8000762: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8000766: 613b str r3, [r7, #16] + 8000768: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); - 80006f6: 4b11 ldr r3, [pc, #68] @ (800073c ) - 80006f8: 69db ldr r3, [r3, #28] - 80006fa: 4a10 ldr r2, [pc, #64] @ (800073c ) - 80006fc: f043 0301 orr.w r3, r3, #1 - 8000700: 61d3 str r3, [r2, #28] - 8000702: 4b0e ldr r3, [pc, #56] @ (800073c ) - 8000704: 69db ldr r3, [r3, #28] - 8000706: f003 0301 and.w r3, r3, #1 - 800070a: 60fb str r3, [r7, #12] - 800070c: 68fb ldr r3, [r7, #12] + 800076a: 4b11 ldr r3, [pc, #68] @ (80007b0 ) + 800076c: 69db ldr r3, [r3, #28] + 800076e: 4a10 ldr r2, [pc, #64] @ (80007b0 ) + 8000770: f043 0301 orr.w r3, r3, #1 + 8000774: 61d3 str r3, [r2, #28] + 8000776: 4b0e ldr r3, [pc, #56] @ (80007b0 ) + 8000778: 69db ldr r3, [r3, #28] + 800077a: f003 0301 and.w r3, r3, #1 + 800077e: 60fb str r3, [r7, #12] + 8000780: 68fb ldr r3, [r7, #12] /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; - 800070e: 23e0 movs r3, #224 @ 0xe0 - 8000710: 617b str r3, [r7, #20] + 8000782: 23e0 movs r3, #224 @ 0xe0 + 8000784: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000712: 2302 movs r3, #2 - 8000714: 61bb str r3, [r7, #24] + 8000786: 2302 movs r3, #2 + 8000788: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000716: 2300 movs r3, #0 - 8000718: 61fb str r3, [r7, #28] + 800078a: 2300 movs r3, #0 + 800078c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 800071a: 2303 movs r3, #3 - 800071c: 623b str r3, [r7, #32] + 800078e: 2303 movs r3, #3 + 8000790: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; - 800071e: 2305 movs r3, #5 - 8000720: 627b str r3, [r7, #36] @ 0x24 + 8000792: 2305 movs r3, #5 + 8000794: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000722: f107 0314 add.w r3, r7, #20 - 8000726: 4619 mov r1, r3 - 8000728: 4805 ldr r0, [pc, #20] @ (8000740 ) - 800072a: f000 fa47 bl 8000bbc + 8000796: f107 0314 add.w r3, r7, #20 + 800079a: 4619 mov r1, r3 + 800079c: 4805 ldr r0, [pc, #20] @ (80007b4 ) + 800079e: f000 fa69 bl 8000c74 /* USER CODE END SPI1_MspInit 1 */ } } - 800072e: bf00 nop - 8000730: 3728 adds r7, #40 @ 0x28 - 8000732: 46bd mov sp, r7 - 8000734: bd80 pop {r7, pc} - 8000736: bf00 nop - 8000738: 40013000 .word 0x40013000 - 800073c: 40023800 .word 0x40023800 - 8000740: 40020000 .word 0x40020000 + 80007a2: bf00 nop + 80007a4: 3728 adds r7, #40 @ 0x28 + 80007a6: 46bd mov sp, r7 + 80007a8: bd80 pop {r7, pc} + 80007aa: bf00 nop + 80007ac: 40013000 .word 0x40013000 + 80007b0: 40023800 .word 0x40023800 + 80007b4: 40020000 .word 0x40020000 -08000744 : +080007b8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 8000744: b480 push {r7} - 8000746: af00 add r7, sp, #0 + 80007b8: b480 push {r7} + 80007ba: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8000748: bf00 nop - 800074a: e7fd b.n 8000748 + 80007bc: bf00 nop + 80007be: e7fd b.n 80007bc -0800074c : +080007c0 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 800074c: b480 push {r7} - 800074e: af00 add r7, sp, #0 + 80007c0: b480 push {r7} + 80007c2: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8000750: bf00 nop - 8000752: e7fd b.n 8000750 + 80007c4: bf00 nop + 80007c6: e7fd b.n 80007c4 -08000754 : +080007c8 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 8000754: b480 push {r7} - 8000756: af00 add r7, sp, #0 + 80007c8: b480 push {r7} + 80007ca: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8000758: bf00 nop - 800075a: e7fd b.n 8000758 + 80007cc: bf00 nop + 80007ce: e7fd b.n 80007cc -0800075c : +080007d0 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 800075c: b480 push {r7} - 800075e: af00 add r7, sp, #0 + 80007d0: b480 push {r7} + 80007d2: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 8000760: bf00 nop - 8000762: e7fd b.n 8000760 + 80007d4: bf00 nop + 80007d6: e7fd b.n 80007d4 -08000764 : +080007d8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 8000764: b480 push {r7} - 8000766: af00 add r7, sp, #0 + 80007d8: b480 push {r7} + 80007da: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8000768: bf00 nop - 800076a: e7fd b.n 8000768 + 80007dc: bf00 nop + 80007de: e7fd b.n 80007dc -0800076c : +080007e0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 800076c: b480 push {r7} - 800076e: af00 add r7, sp, #0 + 80007e0: b480 push {r7} + 80007e2: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } - 8000770: bf00 nop - 8000772: 46bd mov sp, r7 - 8000774: bc80 pop {r7} - 8000776: 4770 bx lr + 80007e4: bf00 nop + 80007e6: 46bd mov sp, r7 + 80007e8: bc80 pop {r7} + 80007ea: 4770 bx lr -08000778 : +080007ec : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8000778: b480 push {r7} - 800077a: af00 add r7, sp, #0 + 80007ec: b480 push {r7} + 80007ee: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 800077c: bf00 nop - 800077e: 46bd mov sp, r7 - 8000780: bc80 pop {r7} - 8000782: 4770 bx lr + 80007f0: bf00 nop + 80007f2: 46bd mov sp, r7 + 80007f4: bc80 pop {r7} + 80007f6: 4770 bx lr -08000784 : +080007f8 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8000784: b480 push {r7} - 8000786: af00 add r7, sp, #0 + 80007f8: b480 push {r7} + 80007fa: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 8000788: bf00 nop - 800078a: 46bd mov sp, r7 - 800078c: bc80 pop {r7} - 800078e: 4770 bx lr + 80007fc: bf00 nop + 80007fe: 46bd mov sp, r7 + 8000800: bc80 pop {r7} + 8000802: 4770 bx lr -08000790 : +08000804 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8000790: b580 push {r7, lr} - 8000792: af00 add r7, sp, #0 + 8000804: b580 push {r7, lr} + 8000806: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 8000794: f000 f912 bl 80009bc + 8000808: f000 f912 bl 8000a30 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8000798: bf00 nop - 800079a: bd80 pop {r7, pc} + 800080c: bf00 nop + 800080e: bd80 pop {r7, pc} -0800079c : +08000810 : * SystemCoreClock variable. * @param None * @retval None */ void SystemInit (void) { - 800079c: b480 push {r7} - 800079e: af00 add r7, sp, #0 + 8000810: b480 push {r7} + 8000812: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } - 80007a0: bf00 nop - 80007a2: 46bd mov sp, r7 - 80007a4: bc80 pop {r7} - 80007a6: 4770 bx lr + 8000814: bf00 nop + 8000816: 46bd mov sp, r7 + 8000818: bc80 pop {r7} + 800081a: 4770 bx lr -080007a8 : +0800081c : .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit - 80007a8: f7ff fff8 bl 800079c + 800081c: f7ff fff8 bl 8000810 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 80007ac: 480b ldr r0, [pc, #44] @ (80007dc ) + 8000820: 480b ldr r0, [pc, #44] @ (8000850 ) ldr r1, =_edata - 80007ae: 490c ldr r1, [pc, #48] @ (80007e0 ) + 8000822: 490c ldr r1, [pc, #48] @ (8000854 ) ldr r2, =_sidata - 80007b0: 4a0c ldr r2, [pc, #48] @ (80007e4 ) + 8000824: 4a0c ldr r2, [pc, #48] @ (8000858 ) movs r3, #0 - 80007b2: 2300 movs r3, #0 + 8000826: 2300 movs r3, #0 b LoopCopyDataInit - 80007b4: e002 b.n 80007bc + 8000828: e002 b.n 8000830 -080007b6 : +0800082a : CopyDataInit: ldr r4, [r2, r3] - 80007b6: 58d4 ldr r4, [r2, r3] + 800082a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 80007b8: 50c4 str r4, [r0, r3] + 800082c: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 80007ba: 3304 adds r3, #4 + 800082e: 3304 adds r3, #4 -080007bc : +08000830 : LoopCopyDataInit: adds r4, r0, r3 - 80007bc: 18c4 adds r4, r0, r3 + 8000830: 18c4 adds r4, r0, r3 cmp r4, r1 - 80007be: 428c cmp r4, r1 + 8000832: 428c cmp r4, r1 bcc CopyDataInit - 80007c0: d3f9 bcc.n 80007b6 + 8000834: d3f9 bcc.n 800082a /* Zero fill the bss segment. */ ldr r2, =_sbss - 80007c2: 4a09 ldr r2, [pc, #36] @ (80007e8 ) + 8000836: 4a09 ldr r2, [pc, #36] @ (800085c ) ldr r4, =_ebss - 80007c4: 4c09 ldr r4, [pc, #36] @ (80007ec ) + 8000838: 4c09 ldr r4, [pc, #36] @ (8000860 ) movs r3, #0 - 80007c6: 2300 movs r3, #0 + 800083a: 2300 movs r3, #0 b LoopFillZerobss - 80007c8: e001 b.n 80007ce + 800083c: e001 b.n 8000842 -080007ca : +0800083e : FillZerobss: str r3, [r2] - 80007ca: 6013 str r3, [r2, #0] + 800083e: 6013 str r3, [r2, #0] adds r2, r2, #4 - 80007cc: 3204 adds r2, #4 + 8000840: 3204 adds r2, #4 -080007ce : +08000842 : LoopFillZerobss: cmp r2, r4 - 80007ce: 42a2 cmp r2, r4 + 8000842: 42a2 cmp r2, r4 bcc FillZerobss - 80007d0: d3fb bcc.n 80007ca + 8000844: d3fb bcc.n 800083e /* Call static constructors */ bl __libc_init_array - 80007d2: f001 fbcf bl 8001f74 <__libc_init_array> + 8000846: f001 fbf1 bl 800202c <__libc_init_array> /* Call the application's entry point.*/ bl main - 80007d6: f7ff fe6b bl 80004b0
+ 800084a: f7ff fe61 bl 8000510
bx lr - 80007da: 4770 bx lr + 800084e: 4770 bx lr ldr r0, =_sdata - 80007dc: 20000000 .word 0x20000000 + 8000850: 20000000 .word 0x20000000 ldr r1, =_edata - 80007e0: 2000000c .word 0x2000000c + 8000854: 2000000c .word 0x2000000c ldr r2, =_sidata - 80007e4: 08002010 .word 0x08002010 + 8000858: 080020c8 .word 0x080020c8 ldr r2, =_sbss - 80007e8: 2000000c .word 0x2000000c + 800085c: 2000000c .word 0x2000000c ldr r4, =_ebss - 80007ec: 20000084 .word 0x20000084 + 8000860: 20000084 .word 0x20000084 -080007f0 : +08000864 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 80007f0: e7fe b.n 80007f0 + 8000864: e7fe b.n 8000864 -080007f2 : +08000866 : * Arguments : none * Returns : none ********************************************************************************************************* */ void MAX7219_Init (void) { - 80007f2: b580 push {r7, lr} - 80007f4: af00 add r7, sp, #0 + 8000866: b580 push {r7, lr} + 8000868: af00 add r7, sp, #0 // configure "LOAD" as output MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits - 80007f6: 2107 movs r1, #7 - 80007f8: 200b movs r0, #11 - 80007fa: f000 f85d bl 80008b8 + 800086a: 2107 movs r1, #7 + 800086c: 200b movs r0, #11 + 800086e: f000 f85d bl 800092c MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits - 80007fe: 2100 movs r1, #0 - 8000800: 2009 movs r0, #9 - 8000802: f000 f859 bl 80008b8 + 8000872: 2100 movs r1, #0 + 8000874: 2009 movs r0, #9 + 8000876: f000 f859 bl 800092c MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown) - 8000806: f000 f809 bl 800081c + 800087a: f000 f809 bl 8000890 MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode) - 800080a: f000 f80f bl 800082c + 800087e: f000 f80f bl 80008a0 MAX7219_Clear(); // clear all digits - 800080e: f000 f827 bl 8000860 + 8000882: f000 f827 bl 80008d4 MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity - 8000812: 200f movs r0, #15 - 8000814: f000 f812 bl 800083c + 8000886: 200f movs r0, #15 + 8000888: f000 f812 bl 80008b0 } - 8000818: bf00 nop - 800081a: bd80 pop {r7, pc} + 800088c: bf00 nop + 800088e: bd80 pop {r7, pc} -0800081c : +08000890 : * Arguments : none * Returns : none ********************************************************************************************************* */ void MAX7219_ShutdownStop (void) { - 800081c: b580 push {r7, lr} - 800081e: af00 add r7, sp, #0 + 8000890: b580 push {r7, lr} + 8000892: af00 add r7, sp, #0 MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode - 8000820: 2101 movs r1, #1 - 8000822: 200c movs r0, #12 - 8000824: f000 f848 bl 80008b8 + 8000894: 2101 movs r1, #1 + 8000896: 200c movs r0, #12 + 8000898: f000 f848 bl 800092c } - 8000828: bf00 nop - 800082a: bd80 pop {r7, pc} + 800089c: bf00 nop + 800089e: bd80 pop {r7, pc} -0800082c : +080008a0 : * Arguments : none * Returns : none ********************************************************************************************************* */ void MAX7219_DisplayTestStop (void) { - 800082c: b580 push {r7, lr} - 800082e: af00 add r7, sp, #0 + 80008a0: b580 push {r7, lr} + 80008a2: af00 add r7, sp, #0 MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode - 8000830: 2100 movs r1, #0 - 8000832: 200f movs r0, #15 - 8000834: f000 f840 bl 80008b8 + 80008a4: 2100 movs r1, #0 + 80008a6: 200f movs r0, #15 + 80008a8: f000 f840 bl 800092c } - 8000838: bf00 nop - 800083a: bd80 pop {r7, pc} + 80008ac: bf00 nop + 80008ae: bd80 pop {r7, pc} -0800083c : +080008b0 : * Arguments : brightness (0-15) * Returns : none ********************************************************************************************************* */ void MAX7219_SetBrightness (char brightness) { - 800083c: b580 push {r7, lr} - 800083e: b082 sub sp, #8 - 8000840: af00 add r7, sp, #0 - 8000842: 4603 mov r3, r0 - 8000844: 71fb strb r3, [r7, #7] + 80008b0: b580 push {r7, lr} + 80008b2: b082 sub sp, #8 + 80008b4: af00 add r7, sp, #0 + 80008b6: 4603 mov r3, r0 + 80008b8: 71fb strb r3, [r7, #7] brightness &= 0x0f; // mask off extra bits - 8000846: 79fb ldrb r3, [r7, #7] - 8000848: f003 030f and.w r3, r3, #15 - 800084c: 71fb strb r3, [r7, #7] + 80008ba: 79fb ldrb r3, [r7, #7] + 80008bc: f003 030f and.w r3, r3, #15 + 80008c0: 71fb strb r3, [r7, #7] MAX7219_Write(REG_INTENSITY, brightness); // set brightness - 800084e: 79fb ldrb r3, [r7, #7] - 8000850: 4619 mov r1, r3 - 8000852: 200a movs r0, #10 - 8000854: f000 f830 bl 80008b8 + 80008c2: 79fb ldrb r3, [r7, #7] + 80008c4: 4619 mov r1, r3 + 80008c6: 200a movs r0, #10 + 80008c8: f000 f830 bl 800092c } - 8000858: bf00 nop - 800085a: 3708 adds r7, #8 - 800085c: 46bd mov sp, r7 - 800085e: bd80 pop {r7, pc} + 80008cc: bf00 nop + 80008ce: 3708 adds r7, #8 + 80008d0: 46bd mov sp, r7 + 80008d2: bd80 pop {r7, pc} -08000860 : +080008d4 : * Arguments : none * Returns : none ********************************************************************************************************* */ void MAX7219_Clear (void) { - 8000860: b580 push {r7, lr} - 8000862: b082 sub sp, #8 - 8000864: af00 add r7, sp, #0 + 80008d4: b580 push {r7, lr} + 80008d6: b082 sub sp, #8 + 80008d8: af00 add r7, sp, #0 char i; for (i=0; i < 8; i++) - 8000866: 2300 movs r3, #0 - 8000868: 71fb strb r3, [r7, #7] - 800086a: e007 b.n 800087c + 80008da: 2300 movs r3, #0 + 80008dc: 71fb strb r3, [r7, #7] + 80008de: e007 b.n 80008f0 MAX7219_Write(i, 0x00); // turn all segments off - 800086c: 79fb ldrb r3, [r7, #7] - 800086e: 2100 movs r1, #0 - 8000870: 4618 mov r0, r3 - 8000872: f000 f821 bl 80008b8 + 80008e0: 79fb ldrb r3, [r7, #7] + 80008e2: 2100 movs r1, #0 + 80008e4: 4618 mov r0, r3 + 80008e6: f000 f821 bl 800092c for (i=0; i < 8; i++) - 8000876: 79fb ldrb r3, [r7, #7] - 8000878: 3301 adds r3, #1 - 800087a: 71fb strb r3, [r7, #7] - 800087c: 79fb ldrb r3, [r7, #7] - 800087e: 2b07 cmp r3, #7 - 8000880: d9f4 bls.n 800086c + 80008ea: 79fb ldrb r3, [r7, #7] + 80008ec: 3301 adds r3, #1 + 80008ee: 71fb strb r3, [r7, #7] + 80008f0: 79fb ldrb r3, [r7, #7] + 80008f2: 2b07 cmp r3, #7 + 80008f4: d9f4 bls.n 80008e0 } - 8000882: bf00 nop - 8000884: bf00 nop - 8000886: 3708 adds r7, #8 - 8000888: 46bd mov sp, r7 - 800088a: bd80 pop {r7, pc} + 80008f6: bf00 nop + 80008f8: bf00 nop + 80008fa: 3708 adds r7, #8 + 80008fc: 46bd mov sp, r7 + 80008fe: bd80 pop {r7, pc} -0800088c : +08000900 : * character = character to display (0-9, A-Z) * Returns : none ********************************************************************************************************* */ void MAX7219_DisplayChar(char digit, char character) { - 800088c: b580 push {r7, lr} - 800088e: b082 sub sp, #8 - 8000890: af00 add r7, sp, #0 - 8000892: 4603 mov r3, r0 - 8000894: 460a mov r2, r1 - 8000896: 71fb strb r3, [r7, #7] - 8000898: 4613 mov r3, r2 - 800089a: 71bb strb r3, [r7, #6] + 8000900: b580 push {r7, lr} + 8000902: b082 sub sp, #8 + 8000904: af00 add r7, sp, #0 + 8000906: 4603 mov r3, r0 + 8000908: 460a mov r2, r1 + 800090a: 71fb strb r3, [r7, #7] + 800090c: 4613 mov r3, r2 + 800090e: 71bb strb r3, [r7, #6] //MAX7219_Write(digit, MAX7219_LookupCode(character)); MAX7219_Write(digit, conv_7seg[character]); - 800089c: 79bb ldrb r3, [r7, #6] - 800089e: 4a05 ldr r2, [pc, #20] @ (80008b4 ) - 80008a0: 5cd2 ldrb r2, [r2, r3] - 80008a2: 79fb ldrb r3, [r7, #7] - 80008a4: 4611 mov r1, r2 - 80008a6: 4618 mov r0, r3 - 80008a8: f000 f806 bl 80008b8 + 8000910: 79bb ldrb r3, [r7, #6] + 8000912: 4a05 ldr r2, [pc, #20] @ (8000928 ) + 8000914: 5cd2 ldrb r2, [r2, r3] + 8000916: 79fb ldrb r3, [r7, #7] + 8000918: 4611 mov r1, r2 + 800091a: 4618 mov r0, r3 + 800091c: f000 f806 bl 800092c } - 80008ac: bf00 nop - 80008ae: 3708 adds r7, #8 - 80008b0: 46bd mov sp, r7 - 80008b2: bd80 pop {r7, pc} - 80008b4: 08001ff0 .word 0x08001ff0 + 8000920: bf00 nop + 8000922: 3708 adds r7, #8 + 8000924: 46bd mov sp, r7 + 8000926: bd80 pop {r7, pc} + 8000928: 080020a8 .word 0x080020a8 -080008b8 : +0800092c : * dataout = data to write to MAX7219 * Returns : none ********************************************************************************************************* */ void MAX7219_Write (unsigned char reg_number, unsigned char dataout) { - 80008b8: b580 push {r7, lr} - 80008ba: b082 sub sp, #8 - 80008bc: af00 add r7, sp, #0 - 80008be: 4603 mov r3, r0 - 80008c0: 460a mov r2, r1 - 80008c2: 71fb strb r3, [r7, #7] - 80008c4: 4613 mov r3, r2 - 80008c6: 71bb strb r3, [r7, #6] + 800092c: b580 push {r7, lr} + 800092e: b082 sub sp, #8 + 8000930: af00 add r7, sp, #0 + 8000932: 4603 mov r3, r0 + 8000934: 460a mov r2, r1 + 8000936: 71fb strb r3, [r7, #7] + 8000938: 4613 mov r3, r2 + 800093a: 71bb strb r3, [r7, #6] MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin - 80008c8: 4b09 ldr r3, [pc, #36] @ (80008f0 ) - 80008ca: f44f 3280 mov.w r2, #65536 @ 0x10000 - 80008ce: 619a str r2, [r3, #24] + 800093c: 4b09 ldr r3, [pc, #36] @ (8000964 ) + 800093e: f44f 3280 mov.w r2, #65536 @ 0x10000 + 8000942: 619a str r2, [r3, #24] MAX7219_SendByte(reg_number); // write register number to MAX7219 - 80008d0: 79fb ldrb r3, [r7, #7] - 80008d2: 4618 mov r0, r3 - 80008d4: f000 f80e bl 80008f4 + 8000944: 79fb ldrb r3, [r7, #7] + 8000946: 4618 mov r0, r3 + 8000948: f000 f80e bl 8000968 MAX7219_SendByte(dataout); // write data to MAX7219 - 80008d8: 79bb ldrb r3, [r7, #6] - 80008da: 4618 mov r0, r3 - 80008dc: f000 f80a bl 80008f4 + 800094c: 79bb ldrb r3, [r7, #6] + 800094e: 4618 mov r0, r3 + 8000950: f000 f80a bl 8000968 MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data - 80008e0: 4b03 ldr r3, [pc, #12] @ (80008f0 ) - 80008e2: 2201 movs r2, #1 - 80008e4: 619a str r2, [r3, #24] + 8000954: 4b03 ldr r3, [pc, #12] @ (8000964 ) + 8000956: 2201 movs r2, #1 + 8000958: 619a str r2, [r3, #24] } - 80008e6: bf00 nop - 80008e8: 3708 adds r7, #8 - 80008ea: 46bd mov sp, r7 - 80008ec: bd80 pop {r7, pc} - 80008ee: bf00 nop - 80008f0: 40020800 .word 0x40020800 + 800095a: bf00 nop + 800095c: 3708 adds r7, #8 + 800095e: 46bd mov sp, r7 + 8000960: bd80 pop {r7, pc} + 8000962: bf00 nop + 8000964: 40020800 .word 0x40020800 -080008f4 : +08000968 : * Returns : none ********************************************************************************************************* */ static void MAX7219_SendByte (unsigned char dataout) { - 80008f4: b580 push {r7, lr} - 80008f6: b082 sub sp, #8 - 80008f8: af00 add r7, sp, #0 - 80008fa: 4603 mov r3, r0 - 80008fc: 71fb strb r3, [r7, #7] + 8000968: b580 push {r7, lr} + 800096a: b082 sub sp, #8 + 800096c: af00 add r7, sp, #0 + 800096e: 4603 mov r3, r0 + 8000970: 71fb strb r3, [r7, #7] HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000); - 80008fe: 1df9 adds r1, r7, #7 - 8000900: f44f 737a mov.w r3, #1000 @ 0x3e8 - 8000904: 2201 movs r2, #1 - 8000906: 4803 ldr r0, [pc, #12] @ (8000914 ) - 8000908: f001 f90b bl 8001b22 + 8000972: 1df9 adds r1, r7, #7 + 8000974: f44f 737a mov.w r3, #1000 @ 0x3e8 + 8000978: 2201 movs r2, #1 + 800097a: 4803 ldr r0, [pc, #12] @ (8000988 ) + 800097c: f001 f92d bl 8001bda } - 800090c: bf00 nop - 800090e: 3708 adds r7, #8 - 8000910: 46bd mov sp, r7 - 8000912: bd80 pop {r7, pc} - 8000914: 20000028 .word 0x20000028 + 8000980: bf00 nop + 8000982: 3708 adds r7, #8 + 8000984: 46bd mov sp, r7 + 8000986: bd80 pop {r7, pc} + 8000988: 20000028 .word 0x20000028 -08000918 : +0800098c : * In the default implementation,Systick is used as source of time base. * the tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8000918: b580 push {r7, lr} - 800091a: b082 sub sp, #8 - 800091c: af00 add r7, sp, #0 + 800098c: b580 push {r7, lr} + 800098e: b082 sub sp, #8 + 8000990: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; - 800091e: 2300 movs r3, #0 - 8000920: 71fb strb r3, [r7, #7] + 8000992: 2300 movs r3, #0 + 8000994: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8000922: 2003 movs r0, #3 - 8000924: f000 f916 bl 8000b54 + 8000996: 2003 movs r0, #3 + 8000998: f000 f938 bl 8000c0c /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - 8000928: 200f movs r0, #15 - 800092a: f000 f80d bl 8000948 - 800092e: 4603 mov r3, r0 - 8000930: 2b00 cmp r3, #0 - 8000932: d002 beq.n 800093a + 800099c: 200f movs r0, #15 + 800099e: f000 f80d bl 80009bc + 80009a2: 4603 mov r3, r0 + 80009a4: 2b00 cmp r3, #0 + 80009a6: d002 beq.n 80009ae { status = HAL_ERROR; - 8000934: 2301 movs r3, #1 - 8000936: 71fb strb r3, [r7, #7] - 8000938: e001 b.n 800093e + 80009a8: 2301 movs r3, #1 + 80009aa: 71fb strb r3, [r7, #7] + 80009ac: e001 b.n 80009b2 } else { /* Init the low level hardware */ HAL_MspInit(); - 800093a: f7ff fe91 bl 8000660 + 80009ae: f7ff fe91 bl 80006d4 } /* Return function status */ return status; - 800093e: 79fb ldrb r3, [r7, #7] + 80009b2: 79fb ldrb r3, [r7, #7] } - 8000940: 4618 mov r0, r3 - 8000942: 3708 adds r7, #8 - 8000944: 46bd mov sp, r7 - 8000946: bd80 pop {r7, pc} + 80009b4: 4618 mov r0, r3 + 80009b6: 3708 adds r7, #8 + 80009b8: 46bd mov sp, r7 + 80009ba: bd80 pop {r7, pc} -08000948 : +080009bc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 8000948: b580 push {r7, lr} - 800094a: b084 sub sp, #16 - 800094c: af00 add r7, sp, #0 - 800094e: 6078 str r0, [r7, #4] + 80009bc: b580 push {r7, lr} + 80009be: b084 sub sp, #16 + 80009c0: af00 add r7, sp, #0 + 80009c2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8000950: 2300 movs r3, #0 - 8000952: 73fb strb r3, [r7, #15] + 80009c4: 2300 movs r3, #0 + 80009c6: 73fb strb r3, [r7, #15] if (uwTickFreq != 0U) - 8000954: 4b16 ldr r3, [pc, #88] @ (80009b0 ) - 8000956: 681b ldr r3, [r3, #0] - 8000958: 2b00 cmp r3, #0 - 800095a: d022 beq.n 80009a2 + 80009c8: 4b16 ldr r3, [pc, #88] @ (8000a24 ) + 80009ca: 681b ldr r3, [r3, #0] + 80009cc: 2b00 cmp r3, #0 + 80009ce: d022 beq.n 8000a16 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) - 800095c: 4b15 ldr r3, [pc, #84] @ (80009b4 ) - 800095e: 681a ldr r2, [r3, #0] - 8000960: 4b13 ldr r3, [pc, #76] @ (80009b0 ) - 8000962: 681b ldr r3, [r3, #0] - 8000964: f44f 717a mov.w r1, #1000 @ 0x3e8 - 8000968: fbb1 f3f3 udiv r3, r1, r3 - 800096c: fbb2 f3f3 udiv r3, r2, r3 - 8000970: 4618 mov r0, r3 - 8000972: f000 f916 bl 8000ba2 - 8000976: 4603 mov r3, r0 - 8000978: 2b00 cmp r3, #0 - 800097a: d10f bne.n 800099c + 80009d0: 4b15 ldr r3, [pc, #84] @ (8000a28 ) + 80009d2: 681a ldr r2, [r3, #0] + 80009d4: 4b13 ldr r3, [pc, #76] @ (8000a24 ) + 80009d6: 681b ldr r3, [r3, #0] + 80009d8: f44f 717a mov.w r1, #1000 @ 0x3e8 + 80009dc: fbb1 f3f3 udiv r3, r1, r3 + 80009e0: fbb2 f3f3 udiv r3, r2, r3 + 80009e4: 4618 mov r0, r3 + 80009e6: f000 f938 bl 8000c5a + 80009ea: 4603 mov r3, r0 + 80009ec: 2b00 cmp r3, #0 + 80009ee: d10f bne.n 8000a10 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 800097c: 687b ldr r3, [r7, #4] - 800097e: 2b0f cmp r3, #15 - 8000980: d809 bhi.n 8000996 + 80009f0: 687b ldr r3, [r7, #4] + 80009f2: 2b0f cmp r3, #15 + 80009f4: d809 bhi.n 8000a0a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 8000982: 2200 movs r2, #0 - 8000984: 6879 ldr r1, [r7, #4] - 8000986: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 800098a: f000 f8ee bl 8000b6a + 80009f6: 2200 movs r2, #0 + 80009f8: 6879 ldr r1, [r7, #4] + 80009fa: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 80009fe: f000 f910 bl 8000c22 uwTickPrio = TickPriority; - 800098e: 4a0a ldr r2, [pc, #40] @ (80009b8 ) - 8000990: 687b ldr r3, [r7, #4] - 8000992: 6013 str r3, [r2, #0] - 8000994: e007 b.n 80009a6 + 8000a02: 4a0a ldr r2, [pc, #40] @ (8000a2c ) + 8000a04: 687b ldr r3, [r7, #4] + 8000a06: 6013 str r3, [r2, #0] + 8000a08: e007 b.n 8000a1a } else { status = HAL_ERROR; - 8000996: 2301 movs r3, #1 - 8000998: 73fb strb r3, [r7, #15] - 800099a: e004 b.n 80009a6 + 8000a0a: 2301 movs r3, #1 + 8000a0c: 73fb strb r3, [r7, #15] + 8000a0e: e004 b.n 8000a1a } } else { status = HAL_ERROR; - 800099c: 2301 movs r3, #1 - 800099e: 73fb strb r3, [r7, #15] - 80009a0: e001 b.n 80009a6 + 8000a10: 2301 movs r3, #1 + 8000a12: 73fb strb r3, [r7, #15] + 8000a14: e001 b.n 8000a1a } } else { status = HAL_ERROR; - 80009a2: 2301 movs r3, #1 - 80009a4: 73fb strb r3, [r7, #15] + 8000a16: 2301 movs r3, #1 + 8000a18: 73fb strb r3, [r7, #15] } /* Return function status */ return status; - 80009a6: 7bfb ldrb r3, [r7, #15] + 8000a1a: 7bfb ldrb r3, [r7, #15] } - 80009a8: 4618 mov r0, r3 - 80009aa: 3710 adds r7, #16 - 80009ac: 46bd mov sp, r7 - 80009ae: bd80 pop {r7, pc} - 80009b0: 20000008 .word 0x20000008 - 80009b4: 20000000 .word 0x20000000 - 80009b8: 20000004 .word 0x20000004 + 8000a1c: 4618 mov r0, r3 + 8000a1e: 3710 adds r7, #16 + 8000a20: 46bd mov sp, r7 + 8000a22: bd80 pop {r7, pc} + 8000a24: 20000008 .word 0x20000008 + 8000a28: 20000000 .word 0x20000000 + 8000a2c: 20000004 .word 0x20000004 -080009bc : +08000a30 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 80009bc: b480 push {r7} - 80009be: af00 add r7, sp, #0 + 8000a30: b480 push {r7} + 8000a32: af00 add r7, sp, #0 uwTick += uwTickFreq; - 80009c0: 4b05 ldr r3, [pc, #20] @ (80009d8 ) - 80009c2: 681a ldr r2, [r3, #0] - 80009c4: 4b05 ldr r3, [pc, #20] @ (80009dc ) - 80009c6: 681b ldr r3, [r3, #0] - 80009c8: 4413 add r3, r2 - 80009ca: 4a03 ldr r2, [pc, #12] @ (80009d8 ) - 80009cc: 6013 str r3, [r2, #0] + 8000a34: 4b05 ldr r3, [pc, #20] @ (8000a4c ) + 8000a36: 681a ldr r2, [r3, #0] + 8000a38: 4b05 ldr r3, [pc, #20] @ (8000a50 ) + 8000a3a: 681b ldr r3, [r3, #0] + 8000a3c: 4413 add r3, r2 + 8000a3e: 4a03 ldr r2, [pc, #12] @ (8000a4c ) + 8000a40: 6013 str r3, [r2, #0] } - 80009ce: bf00 nop - 80009d0: 46bd mov sp, r7 - 80009d2: bc80 pop {r7} - 80009d4: 4770 bx lr - 80009d6: bf00 nop - 80009d8: 20000080 .word 0x20000080 - 80009dc: 20000008 .word 0x20000008 + 8000a42: bf00 nop + 8000a44: 46bd mov sp, r7 + 8000a46: bc80 pop {r7} + 8000a48: 4770 bx lr + 8000a4a: bf00 nop + 8000a4c: 20000080 .word 0x20000080 + 8000a50: 20000008 .word 0x20000008 -080009e0 : +08000a54 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 80009e0: b480 push {r7} - 80009e2: af00 add r7, sp, #0 + 8000a54: b480 push {r7} + 8000a56: af00 add r7, sp, #0 return uwTick; - 80009e4: 4b02 ldr r3, [pc, #8] @ (80009f0 ) - 80009e6: 681b ldr r3, [r3, #0] + 8000a58: 4b02 ldr r3, [pc, #8] @ (8000a64 ) + 8000a5a: 681b ldr r3, [r3, #0] } - 80009e8: 4618 mov r0, r3 - 80009ea: 46bd mov sp, r7 - 80009ec: bc80 pop {r7} - 80009ee: 4770 bx lr - 80009f0: 20000080 .word 0x20000080 + 8000a5c: 4618 mov r0, r3 + 8000a5e: 46bd mov sp, r7 + 8000a60: bc80 pop {r7} + 8000a62: 4770 bx lr + 8000a64: 20000080 .word 0x20000080 -080009f4 <__NVIC_SetPriorityGrouping>: +08000a68 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8000a68: b580 push {r7, lr} + 8000a6a: b084 sub sp, #16 + 8000a6c: af00 add r7, sp, #0 + 8000a6e: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8000a70: f7ff fff0 bl 8000a54 + 8000a74: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8000a76: 687b ldr r3, [r7, #4] + 8000a78: 60fb str r3, [r7, #12] + + /* Add a period to guaranty minimum wait */ + if (wait < HAL_MAX_DELAY) + 8000a7a: 68fb ldr r3, [r7, #12] + 8000a7c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8000a80: d004 beq.n 8000a8c + { + wait += (uint32_t)(uwTickFreq); + 8000a82: 4b09 ldr r3, [pc, #36] @ (8000aa8 ) + 8000a84: 681b ldr r3, [r3, #0] + 8000a86: 68fa ldr r2, [r7, #12] + 8000a88: 4413 add r3, r2 + 8000a8a: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 8000a8c: bf00 nop + 8000a8e: f7ff ffe1 bl 8000a54 + 8000a92: 4602 mov r2, r0 + 8000a94: 68bb ldr r3, [r7, #8] + 8000a96: 1ad3 subs r3, r2, r3 + 8000a98: 68fa ldr r2, [r7, #12] + 8000a9a: 429a cmp r2, r3 + 8000a9c: d8f7 bhi.n 8000a8e + { + } +} + 8000a9e: bf00 nop + 8000aa0: bf00 nop + 8000aa2: 3710 adds r7, #16 + 8000aa4: 46bd mov sp, r7 + 8000aa6: bd80 pop {r7, pc} + 8000aa8: 20000008 .word 0x20000008 + +08000aac <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 80009f4: b480 push {r7} - 80009f6: b085 sub sp, #20 - 80009f8: af00 add r7, sp, #0 - 80009fa: 6078 str r0, [r7, #4] + 8000aac: b480 push {r7} + 8000aae: b085 sub sp, #20 + 8000ab0: af00 add r7, sp, #0 + 8000ab2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 80009fc: 687b ldr r3, [r7, #4] - 80009fe: f003 0307 and.w r3, r3, #7 - 8000a02: 60fb str r3, [r7, #12] + 8000ab4: 687b ldr r3, [r7, #4] + 8000ab6: f003 0307 and.w r3, r3, #7 + 8000aba: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8000a04: 4b0c ldr r3, [pc, #48] @ (8000a38 <__NVIC_SetPriorityGrouping+0x44>) - 8000a06: 68db ldr r3, [r3, #12] - 8000a08: 60bb str r3, [r7, #8] + 8000abc: 4b0c ldr r3, [pc, #48] @ (8000af0 <__NVIC_SetPriorityGrouping+0x44>) + 8000abe: 68db ldr r3, [r3, #12] + 8000ac0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8000a0a: 68ba ldr r2, [r7, #8] - 8000a0c: f64f 03ff movw r3, #63743 @ 0xf8ff - 8000a10: 4013 ands r3, r2 - 8000a12: 60bb str r3, [r7, #8] + 8000ac2: 68ba ldr r2, [r7, #8] + 8000ac4: f64f 03ff movw r3, #63743 @ 0xf8ff + 8000ac8: 4013 ands r3, r2 + 8000aca: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8000a14: 68fb ldr r3, [r7, #12] - 8000a16: 021a lsls r2, r3, #8 + 8000acc: 68fb ldr r3, [r7, #12] + 8000ace: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8000a18: 68bb ldr r3, [r7, #8] - 8000a1a: 4313 orrs r3, r2 + 8000ad0: 68bb ldr r3, [r7, #8] + 8000ad2: 4313 orrs r3, r2 reg_value = (reg_value | - 8000a1c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 - 8000a20: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 8000a24: 60bb str r3, [r7, #8] + 8000ad4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 8000ad8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8000adc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8000a26: 4a04 ldr r2, [pc, #16] @ (8000a38 <__NVIC_SetPriorityGrouping+0x44>) - 8000a28: 68bb ldr r3, [r7, #8] - 8000a2a: 60d3 str r3, [r2, #12] + 8000ade: 4a04 ldr r2, [pc, #16] @ (8000af0 <__NVIC_SetPriorityGrouping+0x44>) + 8000ae0: 68bb ldr r3, [r7, #8] + 8000ae2: 60d3 str r3, [r2, #12] } - 8000a2c: bf00 nop - 8000a2e: 3714 adds r7, #20 - 8000a30: 46bd mov sp, r7 - 8000a32: bc80 pop {r7} - 8000a34: 4770 bx lr - 8000a36: bf00 nop - 8000a38: e000ed00 .word 0xe000ed00 + 8000ae4: bf00 nop + 8000ae6: 3714 adds r7, #20 + 8000ae8: 46bd mov sp, r7 + 8000aea: bc80 pop {r7} + 8000aec: 4770 bx lr + 8000aee: bf00 nop + 8000af0: e000ed00 .word 0xe000ed00 -08000a3c <__NVIC_GetPriorityGrouping>: +08000af4 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8000a3c: b480 push {r7} - 8000a3e: af00 add r7, sp, #0 + 8000af4: b480 push {r7} + 8000af6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 8000a40: 4b04 ldr r3, [pc, #16] @ (8000a54 <__NVIC_GetPriorityGrouping+0x18>) - 8000a42: 68db ldr r3, [r3, #12] - 8000a44: 0a1b lsrs r3, r3, #8 - 8000a46: f003 0307 and.w r3, r3, #7 + 8000af8: 4b04 ldr r3, [pc, #16] @ (8000b0c <__NVIC_GetPriorityGrouping+0x18>) + 8000afa: 68db ldr r3, [r3, #12] + 8000afc: 0a1b lsrs r3, r3, #8 + 8000afe: f003 0307 and.w r3, r3, #7 } - 8000a4a: 4618 mov r0, r3 - 8000a4c: 46bd mov sp, r7 - 8000a4e: bc80 pop {r7} - 8000a50: 4770 bx lr - 8000a52: bf00 nop - 8000a54: e000ed00 .word 0xe000ed00 + 8000b02: 4618 mov r0, r3 + 8000b04: 46bd mov sp, r7 + 8000b06: bc80 pop {r7} + 8000b08: 4770 bx lr + 8000b0a: bf00 nop + 8000b0c: e000ed00 .word 0xe000ed00 -08000a58 <__NVIC_SetPriority>: +08000b10 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8000a58: b480 push {r7} - 8000a5a: b083 sub sp, #12 - 8000a5c: af00 add r7, sp, #0 - 8000a5e: 4603 mov r3, r0 - 8000a60: 6039 str r1, [r7, #0] - 8000a62: 71fb strb r3, [r7, #7] + 8000b10: b480 push {r7} + 8000b12: b083 sub sp, #12 + 8000b14: af00 add r7, sp, #0 + 8000b16: 4603 mov r3, r0 + 8000b18: 6039 str r1, [r7, #0] + 8000b1a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8000a64: f997 3007 ldrsb.w r3, [r7, #7] - 8000a68: 2b00 cmp r3, #0 - 8000a6a: db0a blt.n 8000a82 <__NVIC_SetPriority+0x2a> + 8000b1c: f997 3007 ldrsb.w r3, [r7, #7] + 8000b20: 2b00 cmp r3, #0 + 8000b22: db0a blt.n 8000b3a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8000a6c: 683b ldr r3, [r7, #0] - 8000a6e: b2da uxtb r2, r3 - 8000a70: 490c ldr r1, [pc, #48] @ (8000aa4 <__NVIC_SetPriority+0x4c>) - 8000a72: f997 3007 ldrsb.w r3, [r7, #7] - 8000a76: 0112 lsls r2, r2, #4 - 8000a78: b2d2 uxtb r2, r2 - 8000a7a: 440b add r3, r1 - 8000a7c: f883 2300 strb.w r2, [r3, #768] @ 0x300 + 8000b24: 683b ldr r3, [r7, #0] + 8000b26: b2da uxtb r2, r3 + 8000b28: 490c ldr r1, [pc, #48] @ (8000b5c <__NVIC_SetPriority+0x4c>) + 8000b2a: f997 3007 ldrsb.w r3, [r7, #7] + 8000b2e: 0112 lsls r2, r2, #4 + 8000b30: b2d2 uxtb r2, r2 + 8000b32: 440b add r3, r1 + 8000b34: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8000a80: e00a b.n 8000a98 <__NVIC_SetPriority+0x40> + 8000b38: e00a b.n 8000b50 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8000a82: 683b ldr r3, [r7, #0] - 8000a84: b2da uxtb r2, r3 - 8000a86: 4908 ldr r1, [pc, #32] @ (8000aa8 <__NVIC_SetPriority+0x50>) - 8000a88: 79fb ldrb r3, [r7, #7] - 8000a8a: f003 030f and.w r3, r3, #15 - 8000a8e: 3b04 subs r3, #4 - 8000a90: 0112 lsls r2, r2, #4 - 8000a92: b2d2 uxtb r2, r2 - 8000a94: 440b add r3, r1 - 8000a96: 761a strb r2, [r3, #24] + 8000b3a: 683b ldr r3, [r7, #0] + 8000b3c: b2da uxtb r2, r3 + 8000b3e: 4908 ldr r1, [pc, #32] @ (8000b60 <__NVIC_SetPriority+0x50>) + 8000b40: 79fb ldrb r3, [r7, #7] + 8000b42: f003 030f and.w r3, r3, #15 + 8000b46: 3b04 subs r3, #4 + 8000b48: 0112 lsls r2, r2, #4 + 8000b4a: b2d2 uxtb r2, r2 + 8000b4c: 440b add r3, r1 + 8000b4e: 761a strb r2, [r3, #24] } - 8000a98: bf00 nop - 8000a9a: 370c adds r7, #12 - 8000a9c: 46bd mov sp, r7 - 8000a9e: bc80 pop {r7} - 8000aa0: 4770 bx lr - 8000aa2: bf00 nop - 8000aa4: e000e100 .word 0xe000e100 - 8000aa8: e000ed00 .word 0xe000ed00 + 8000b50: bf00 nop + 8000b52: 370c adds r7, #12 + 8000b54: 46bd mov sp, r7 + 8000b56: bc80 pop {r7} + 8000b58: 4770 bx lr + 8000b5a: bf00 nop + 8000b5c: e000e100 .word 0xe000e100 + 8000b60: e000ed00 .word 0xe000ed00 -08000aac : +08000b64 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8000aac: b480 push {r7} - 8000aae: b089 sub sp, #36 @ 0x24 - 8000ab0: af00 add r7, sp, #0 - 8000ab2: 60f8 str r0, [r7, #12] - 8000ab4: 60b9 str r1, [r7, #8] - 8000ab6: 607a str r2, [r7, #4] + 8000b64: b480 push {r7} + 8000b66: b089 sub sp, #36 @ 0x24 + 8000b68: af00 add r7, sp, #0 + 8000b6a: 60f8 str r0, [r7, #12] + 8000b6c: 60b9 str r1, [r7, #8] + 8000b6e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8000ab8: 68fb ldr r3, [r7, #12] - 8000aba: f003 0307 and.w r3, r3, #7 - 8000abe: 61fb str r3, [r7, #28] + 8000b70: 68fb ldr r3, [r7, #12] + 8000b72: f003 0307 and.w r3, r3, #7 + 8000b76: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8000ac0: 69fb ldr r3, [r7, #28] - 8000ac2: f1c3 0307 rsb r3, r3, #7 - 8000ac6: 2b04 cmp r3, #4 - 8000ac8: bf28 it cs - 8000aca: 2304 movcs r3, #4 - 8000acc: 61bb str r3, [r7, #24] + 8000b78: 69fb ldr r3, [r7, #28] + 8000b7a: f1c3 0307 rsb r3, r3, #7 + 8000b7e: 2b04 cmp r3, #4 + 8000b80: bf28 it cs + 8000b82: 2304 movcs r3, #4 + 8000b84: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8000ace: 69fb ldr r3, [r7, #28] - 8000ad0: 3304 adds r3, #4 - 8000ad2: 2b06 cmp r3, #6 - 8000ad4: d902 bls.n 8000adc - 8000ad6: 69fb ldr r3, [r7, #28] - 8000ad8: 3b03 subs r3, #3 - 8000ada: e000 b.n 8000ade - 8000adc: 2300 movs r3, #0 - 8000ade: 617b str r3, [r7, #20] + 8000b86: 69fb ldr r3, [r7, #28] + 8000b88: 3304 adds r3, #4 + 8000b8a: 2b06 cmp r3, #6 + 8000b8c: d902 bls.n 8000b94 + 8000b8e: 69fb ldr r3, [r7, #28] + 8000b90: 3b03 subs r3, #3 + 8000b92: e000 b.n 8000b96 + 8000b94: 2300 movs r3, #0 + 8000b96: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8000ae0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff - 8000ae4: 69bb ldr r3, [r7, #24] - 8000ae6: fa02 f303 lsl.w r3, r2, r3 - 8000aea: 43da mvns r2, r3 - 8000aec: 68bb ldr r3, [r7, #8] - 8000aee: 401a ands r2, r3 - 8000af0: 697b ldr r3, [r7, #20] - 8000af2: 409a lsls r2, r3 + 8000b98: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff + 8000b9c: 69bb ldr r3, [r7, #24] + 8000b9e: fa02 f303 lsl.w r3, r2, r3 + 8000ba2: 43da mvns r2, r3 + 8000ba4: 68bb ldr r3, [r7, #8] + 8000ba6: 401a ands r2, r3 + 8000ba8: 697b ldr r3, [r7, #20] + 8000baa: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8000af4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff - 8000af8: 697b ldr r3, [r7, #20] - 8000afa: fa01 f303 lsl.w r3, r1, r3 - 8000afe: 43d9 mvns r1, r3 - 8000b00: 687b ldr r3, [r7, #4] - 8000b02: 400b ands r3, r1 + 8000bac: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff + 8000bb0: 697b ldr r3, [r7, #20] + 8000bb2: fa01 f303 lsl.w r3, r1, r3 + 8000bb6: 43d9 mvns r1, r3 + 8000bb8: 687b ldr r3, [r7, #4] + 8000bba: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8000b04: 4313 orrs r3, r2 + 8000bbc: 4313 orrs r3, r2 ); } - 8000b06: 4618 mov r0, r3 - 8000b08: 3724 adds r7, #36 @ 0x24 - 8000b0a: 46bd mov sp, r7 - 8000b0c: bc80 pop {r7} - 8000b0e: 4770 bx lr + 8000bbe: 4618 mov r0, r3 + 8000bc0: 3724 adds r7, #36 @ 0x24 + 8000bc2: 46bd mov sp, r7 + 8000bc4: bc80 pop {r7} + 8000bc6: 4770 bx lr -08000b10 : +08000bc8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8000b10: b580 push {r7, lr} - 8000b12: b082 sub sp, #8 - 8000b14: af00 add r7, sp, #0 - 8000b16: 6078 str r0, [r7, #4] + 8000bc8: b580 push {r7, lr} + 8000bca: b082 sub sp, #8 + 8000bcc: af00 add r7, sp, #0 + 8000bce: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 8000b18: 687b ldr r3, [r7, #4] - 8000b1a: 3b01 subs r3, #1 - 8000b1c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 8000b20: d301 bcc.n 8000b26 + 8000bd0: 687b ldr r3, [r7, #4] + 8000bd2: 3b01 subs r3, #1 + 8000bd4: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8000bd8: d301 bcc.n 8000bde { return (1UL); /* Reload value impossible */ - 8000b22: 2301 movs r3, #1 - 8000b24: e00f b.n 8000b46 + 8000bda: 2301 movs r3, #1 + 8000bdc: e00f b.n 8000bfe } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 8000b26: 4a0a ldr r2, [pc, #40] @ (8000b50 ) - 8000b28: 687b ldr r3, [r7, #4] - 8000b2a: 3b01 subs r3, #1 - 8000b2c: 6053 str r3, [r2, #4] + 8000bde: 4a0a ldr r2, [pc, #40] @ (8000c08 ) + 8000be0: 687b ldr r3, [r7, #4] + 8000be2: 3b01 subs r3, #1 + 8000be4: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 8000b2e: 210f movs r1, #15 - 8000b30: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff - 8000b34: f7ff ff90 bl 8000a58 <__NVIC_SetPriority> + 8000be6: 210f movs r1, #15 + 8000be8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff + 8000bec: f7ff ff90 bl 8000b10 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 8000b38: 4b05 ldr r3, [pc, #20] @ (8000b50 ) - 8000b3a: 2200 movs r2, #0 - 8000b3c: 609a str r2, [r3, #8] + 8000bf0: 4b05 ldr r3, [pc, #20] @ (8000c08 ) + 8000bf2: 2200 movs r2, #0 + 8000bf4: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 8000b3e: 4b04 ldr r3, [pc, #16] @ (8000b50 ) - 8000b40: 2207 movs r2, #7 - 8000b42: 601a str r2, [r3, #0] + 8000bf6: 4b04 ldr r3, [pc, #16] @ (8000c08 ) + 8000bf8: 2207 movs r2, #7 + 8000bfa: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 8000b44: 2300 movs r3, #0 + 8000bfc: 2300 movs r3, #0 } - 8000b46: 4618 mov r0, r3 - 8000b48: 3708 adds r7, #8 - 8000b4a: 46bd mov sp, r7 - 8000b4c: bd80 pop {r7, pc} - 8000b4e: bf00 nop - 8000b50: e000e010 .word 0xe000e010 + 8000bfe: 4618 mov r0, r3 + 8000c00: 3708 adds r7, #8 + 8000c02: 46bd mov sp, r7 + 8000c04: bd80 pop {r7, pc} + 8000c06: bf00 nop + 8000c08: e000e010 .word 0xe000e010 -08000b54 : +08000c0c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8000b54: b580 push {r7, lr} - 8000b56: b082 sub sp, #8 - 8000b58: af00 add r7, sp, #0 - 8000b5a: 6078 str r0, [r7, #4] + 8000c0c: b580 push {r7, lr} + 8000c0e: b082 sub sp, #8 + 8000c10: af00 add r7, sp, #0 + 8000c12: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8000b5c: 6878 ldr r0, [r7, #4] - 8000b5e: f7ff ff49 bl 80009f4 <__NVIC_SetPriorityGrouping> + 8000c14: 6878 ldr r0, [r7, #4] + 8000c16: f7ff ff49 bl 8000aac <__NVIC_SetPriorityGrouping> } - 8000b62: bf00 nop - 8000b64: 3708 adds r7, #8 - 8000b66: 46bd mov sp, r7 - 8000b68: bd80 pop {r7, pc} + 8000c1a: bf00 nop + 8000c1c: 3708 adds r7, #8 + 8000c1e: 46bd mov sp, r7 + 8000c20: bd80 pop {r7, pc} -08000b6a : +08000c22 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 8000b6a: b580 push {r7, lr} - 8000b6c: b086 sub sp, #24 - 8000b6e: af00 add r7, sp, #0 - 8000b70: 4603 mov r3, r0 - 8000b72: 60b9 str r1, [r7, #8] - 8000b74: 607a str r2, [r7, #4] - 8000b76: 73fb strb r3, [r7, #15] + 8000c22: b580 push {r7, lr} + 8000c24: b086 sub sp, #24 + 8000c26: af00 add r7, sp, #0 + 8000c28: 4603 mov r3, r0 + 8000c2a: 60b9 str r1, [r7, #8] + 8000c2c: 607a str r2, [r7, #4] + 8000c2e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; - 8000b78: 2300 movs r3, #0 - 8000b7a: 617b str r3, [r7, #20] + 8000c30: 2300 movs r3, #0 + 8000c32: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8000b7c: f7ff ff5e bl 8000a3c <__NVIC_GetPriorityGrouping> - 8000b80: 6178 str r0, [r7, #20] + 8000c34: f7ff ff5e bl 8000af4 <__NVIC_GetPriorityGrouping> + 8000c38: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8000b82: 687a ldr r2, [r7, #4] - 8000b84: 68b9 ldr r1, [r7, #8] - 8000b86: 6978 ldr r0, [r7, #20] - 8000b88: f7ff ff90 bl 8000aac - 8000b8c: 4602 mov r2, r0 - 8000b8e: f997 300f ldrsb.w r3, [r7, #15] - 8000b92: 4611 mov r1, r2 - 8000b94: 4618 mov r0, r3 - 8000b96: f7ff ff5f bl 8000a58 <__NVIC_SetPriority> + 8000c3a: 687a ldr r2, [r7, #4] + 8000c3c: 68b9 ldr r1, [r7, #8] + 8000c3e: 6978 ldr r0, [r7, #20] + 8000c40: f7ff ff90 bl 8000b64 + 8000c44: 4602 mov r2, r0 + 8000c46: f997 300f ldrsb.w r3, [r7, #15] + 8000c4a: 4611 mov r1, r2 + 8000c4c: 4618 mov r0, r3 + 8000c4e: f7ff ff5f bl 8000b10 <__NVIC_SetPriority> } - 8000b9a: bf00 nop - 8000b9c: 3718 adds r7, #24 - 8000b9e: 46bd mov sp, r7 - 8000ba0: bd80 pop {r7, pc} + 8000c52: bf00 nop + 8000c54: 3718 adds r7, #24 + 8000c56: 46bd mov sp, r7 + 8000c58: bd80 pop {r7, pc} -08000ba2 : +08000c5a : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8000ba2: b580 push {r7, lr} - 8000ba4: b082 sub sp, #8 - 8000ba6: af00 add r7, sp, #0 - 8000ba8: 6078 str r0, [r7, #4] + 8000c5a: b580 push {r7, lr} + 8000c5c: b082 sub sp, #8 + 8000c5e: af00 add r7, sp, #0 + 8000c60: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8000baa: 6878 ldr r0, [r7, #4] - 8000bac: f7ff ffb0 bl 8000b10 - 8000bb0: 4603 mov r3, r0 + 8000c62: 6878 ldr r0, [r7, #4] + 8000c64: f7ff ffb0 bl 8000bc8 + 8000c68: 4603 mov r3, r0 } - 8000bb2: 4618 mov r0, r3 - 8000bb4: 3708 adds r7, #8 - 8000bb6: 46bd mov sp, r7 - 8000bb8: bd80 pop {r7, pc} + 8000c6a: 4618 mov r0, r3 + 8000c6c: 3708 adds r7, #8 + 8000c6e: 46bd mov sp, r7 + 8000c70: bd80 pop {r7, pc} ... -08000bbc : +08000c74 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 8000bbc: b480 push {r7} - 8000bbe: b087 sub sp, #28 - 8000bc0: af00 add r7, sp, #0 - 8000bc2: 6078 str r0, [r7, #4] - 8000bc4: 6039 str r1, [r7, #0] + 8000c74: b480 push {r7} + 8000c76: b087 sub sp, #28 + 8000c78: af00 add r7, sp, #0 + 8000c7a: 6078 str r0, [r7, #4] + 8000c7c: 6039 str r1, [r7, #0] uint32_t position = 0x00; - 8000bc6: 2300 movs r3, #0 - 8000bc8: 617b str r3, [r7, #20] + 8000c7e: 2300 movs r3, #0 + 8000c80: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00; - 8000bca: 2300 movs r3, #0 - 8000bcc: 60fb str r3, [r7, #12] + 8000c82: 2300 movs r3, #0 + 8000c84: 60fb str r3, [r7, #12] uint32_t temp = 0x00; - 8000bce: 2300 movs r3, #0 - 8000bd0: 613b str r3, [r7, #16] + 8000c86: 2300 movs r3, #0 + 8000c88: 613b str r3, [r7, #16] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0) - 8000bd2: e160 b.n 8000e96 + 8000c8a: e160 b.n 8000f4e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1U << position); - 8000bd4: 683b ldr r3, [r7, #0] - 8000bd6: 681a ldr r2, [r3, #0] - 8000bd8: 2101 movs r1, #1 - 8000bda: 697b ldr r3, [r7, #20] - 8000bdc: fa01 f303 lsl.w r3, r1, r3 - 8000be0: 4013 ands r3, r2 - 8000be2: 60fb str r3, [r7, #12] + 8000c8c: 683b ldr r3, [r7, #0] + 8000c8e: 681a ldr r2, [r3, #0] + 8000c90: 2101 movs r1, #1 + 8000c92: 697b ldr r3, [r7, #20] + 8000c94: fa01 f303 lsl.w r3, r1, r3 + 8000c98: 4013 ands r3, r2 + 8000c9a: 60fb str r3, [r7, #12] if (iocurrent) - 8000be4: 68fb ldr r3, [r7, #12] - 8000be6: 2b00 cmp r3, #0 - 8000be8: f000 8152 beq.w 8000e90 + 8000c9c: 68fb ldr r3, [r7, #12] + 8000c9e: 2b00 cmp r3, #0 + 8000ca0: f000 8152 beq.w 8000f48 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || - 8000bec: 683b ldr r3, [r7, #0] - 8000bee: 685b ldr r3, [r3, #4] - 8000bf0: f003 0303 and.w r3, r3, #3 - 8000bf4: 2b01 cmp r3, #1 - 8000bf6: d005 beq.n 8000c04 + 8000ca4: 683b ldr r3, [r7, #0] + 8000ca6: 685b ldr r3, [r3, #4] + 8000ca8: f003 0303 and.w r3, r3, #3 + 8000cac: 2b01 cmp r3, #1 + 8000cae: d005 beq.n 8000cbc ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) - 8000bf8: 683b ldr r3, [r7, #0] - 8000bfa: 685b ldr r3, [r3, #4] - 8000bfc: f003 0303 and.w r3, r3, #3 + 8000cb0: 683b ldr r3, [r7, #0] + 8000cb2: 685b ldr r3, [r3, #4] + 8000cb4: f003 0303 and.w r3, r3, #3 if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || - 8000c00: 2b02 cmp r3, #2 - 8000c02: d130 bne.n 8000c66 + 8000cb8: 2b02 cmp r3, #2 + 8000cba: d130 bne.n 8000d1e { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 8000c04: 687b ldr r3, [r7, #4] - 8000c06: 689b ldr r3, [r3, #8] - 8000c08: 613b str r3, [r7, #16] + 8000cbc: 687b ldr r3, [r7, #4] + 8000cbe: 689b ldr r3, [r3, #8] + 8000cc0: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - 8000c0a: 697b ldr r3, [r7, #20] - 8000c0c: 005b lsls r3, r3, #1 - 8000c0e: 2203 movs r2, #3 - 8000c10: fa02 f303 lsl.w r3, r2, r3 - 8000c14: 43db mvns r3, r3 - 8000c16: 693a ldr r2, [r7, #16] - 8000c18: 4013 ands r3, r2 - 8000c1a: 613b str r3, [r7, #16] + 8000cc2: 697b ldr r3, [r7, #20] + 8000cc4: 005b lsls r3, r3, #1 + 8000cc6: 2203 movs r2, #3 + 8000cc8: fa02 f303 lsl.w r3, r2, r3 + 8000ccc: 43db mvns r3, r3 + 8000cce: 693a ldr r2, [r7, #16] + 8000cd0: 4013 ands r3, r2 + 8000cd2: 613b str r3, [r7, #16] SET_BIT(temp, GPIO_Init->Speed << (position * 2)); - 8000c1c: 683b ldr r3, [r7, #0] - 8000c1e: 68da ldr r2, [r3, #12] - 8000c20: 697b ldr r3, [r7, #20] - 8000c22: 005b lsls r3, r3, #1 - 8000c24: fa02 f303 lsl.w r3, r2, r3 - 8000c28: 693a ldr r2, [r7, #16] - 8000c2a: 4313 orrs r3, r2 - 8000c2c: 613b str r3, [r7, #16] + 8000cd4: 683b ldr r3, [r7, #0] + 8000cd6: 68da ldr r2, [r3, #12] + 8000cd8: 697b ldr r3, [r7, #20] + 8000cda: 005b lsls r3, r3, #1 + 8000cdc: fa02 f303 lsl.w r3, r2, r3 + 8000ce0: 693a ldr r2, [r7, #16] + 8000ce2: 4313 orrs r3, r2 + 8000ce4: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; - 8000c2e: 687b ldr r3, [r7, #4] - 8000c30: 693a ldr r2, [r7, #16] - 8000c32: 609a str r2, [r3, #8] + 8000ce6: 687b ldr r3, [r7, #4] + 8000ce8: 693a ldr r2, [r7, #16] + 8000cea: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8000c34: 687b ldr r3, [r7, #4] - 8000c36: 685b ldr r3, [r3, #4] - 8000c38: 613b str r3, [r7, #16] + 8000cec: 687b ldr r3, [r7, #4] + 8000cee: 685b ldr r3, [r3, #4] + 8000cf0: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; - 8000c3a: 2201 movs r2, #1 - 8000c3c: 697b ldr r3, [r7, #20] - 8000c3e: fa02 f303 lsl.w r3, r2, r3 - 8000c42: 43db mvns r3, r3 - 8000c44: 693a ldr r2, [r7, #16] - 8000c46: 4013 ands r3, r2 - 8000c48: 613b str r3, [r7, #16] + 8000cf2: 2201 movs r2, #1 + 8000cf4: 697b ldr r3, [r7, #20] + 8000cf6: fa02 f303 lsl.w r3, r2, r3 + 8000cfa: 43db mvns r3, r3 + 8000cfc: 693a ldr r2, [r7, #16] + 8000cfe: 4013 ands r3, r2 + 8000d00: 613b str r3, [r7, #16] SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 8000c4a: 683b ldr r3, [r7, #0] - 8000c4c: 685b ldr r3, [r3, #4] - 8000c4e: 091b lsrs r3, r3, #4 - 8000c50: f003 0201 and.w r2, r3, #1 - 8000c54: 697b ldr r3, [r7, #20] - 8000c56: fa02 f303 lsl.w r3, r2, r3 - 8000c5a: 693a ldr r2, [r7, #16] - 8000c5c: 4313 orrs r3, r2 - 8000c5e: 613b str r3, [r7, #16] + 8000d02: 683b ldr r3, [r7, #0] + 8000d04: 685b ldr r3, [r3, #4] + 8000d06: 091b lsrs r3, r3, #4 + 8000d08: f003 0201 and.w r2, r3, #1 + 8000d0c: 697b ldr r3, [r7, #20] + 8000d0e: fa02 f303 lsl.w r3, r2, r3 + 8000d12: 693a ldr r2, [r7, #16] + 8000d14: 4313 orrs r3, r2 + 8000d16: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; - 8000c60: 687b ldr r3, [r7, #4] - 8000c62: 693a ldr r2, [r7, #16] - 8000c64: 605a str r2, [r3, #4] + 8000d18: 687b ldr r3, [r7, #4] + 8000d1a: 693a ldr r2, [r7, #16] + 8000d1c: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 8000c66: 683b ldr r3, [r7, #0] - 8000c68: 685b ldr r3, [r3, #4] - 8000c6a: f003 0303 and.w r3, r3, #3 - 8000c6e: 2b03 cmp r3, #3 - 8000c70: d017 beq.n 8000ca2 + 8000d1e: 683b ldr r3, [r7, #0] + 8000d20: 685b ldr r3, [r3, #4] + 8000d22: f003 0303 and.w r3, r3, #3 + 8000d26: 2b03 cmp r3, #3 + 8000d28: d017 beq.n 8000d5a { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 8000c72: 687b ldr r3, [r7, #4] - 8000c74: 68db ldr r3, [r3, #12] - 8000c76: 613b str r3, [r7, #16] + 8000d2a: 687b ldr r3, [r7, #4] + 8000d2c: 68db ldr r3, [r3, #12] + 8000d2e: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); - 8000c78: 697b ldr r3, [r7, #20] - 8000c7a: 005b lsls r3, r3, #1 - 8000c7c: 2203 movs r2, #3 - 8000c7e: fa02 f303 lsl.w r3, r2, r3 - 8000c82: 43db mvns r3, r3 - 8000c84: 693a ldr r2, [r7, #16] - 8000c86: 4013 ands r3, r2 - 8000c88: 613b str r3, [r7, #16] + 8000d30: 697b ldr r3, [r7, #20] + 8000d32: 005b lsls r3, r3, #1 + 8000d34: 2203 movs r2, #3 + 8000d36: fa02 f303 lsl.w r3, r2, r3 + 8000d3a: 43db mvns r3, r3 + 8000d3c: 693a ldr r2, [r7, #16] + 8000d3e: 4013 ands r3, r2 + 8000d40: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); - 8000c8a: 683b ldr r3, [r7, #0] - 8000c8c: 689a ldr r2, [r3, #8] - 8000c8e: 697b ldr r3, [r7, #20] - 8000c90: 005b lsls r3, r3, #1 - 8000c92: fa02 f303 lsl.w r3, r2, r3 - 8000c96: 693a ldr r2, [r7, #16] - 8000c98: 4313 orrs r3, r2 - 8000c9a: 613b str r3, [r7, #16] + 8000d42: 683b ldr r3, [r7, #0] + 8000d44: 689a ldr r2, [r3, #8] + 8000d46: 697b ldr r3, [r7, #20] + 8000d48: 005b lsls r3, r3, #1 + 8000d4a: fa02 f303 lsl.w r3, r2, r3 + 8000d4e: 693a ldr r2, [r7, #16] + 8000d50: 4313 orrs r3, r2 + 8000d52: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; - 8000c9c: 687b ldr r3, [r7, #4] - 8000c9e: 693a ldr r2, [r7, #16] - 8000ca0: 60da str r2, [r3, #12] + 8000d54: 687b ldr r3, [r7, #4] + 8000d56: 693a ldr r2, [r7, #16] + 8000d58: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 8000ca2: 683b ldr r3, [r7, #0] - 8000ca4: 685b ldr r3, [r3, #4] - 8000ca6: f003 0303 and.w r3, r3, #3 - 8000caa: 2b02 cmp r3, #2 - 8000cac: d123 bne.n 8000cf6 + 8000d5a: 683b ldr r3, [r7, #0] + 8000d5c: 685b ldr r3, [r3, #4] + 8000d5e: f003 0303 and.w r3, r3, #3 + 8000d62: 2b02 cmp r3, #2 + 8000d64: d123 bne.n 8000dae assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ /* Identify AFRL or AFRH register based on IO position*/ temp = GPIOx->AFR[position >> 3]; - 8000cae: 697b ldr r3, [r7, #20] - 8000cb0: 08da lsrs r2, r3, #3 - 8000cb2: 687b ldr r3, [r7, #4] - 8000cb4: 3208 adds r2, #8 - 8000cb6: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8000cba: 613b str r3, [r7, #16] + 8000d66: 697b ldr r3, [r7, #20] + 8000d68: 08da lsrs r2, r3, #3 + 8000d6a: 687b ldr r3, [r7, #4] + 8000d6c: 3208 adds r2, #8 + 8000d6e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8000d72: 613b str r3, [r7, #16] CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); - 8000cbc: 697b ldr r3, [r7, #20] - 8000cbe: f003 0307 and.w r3, r3, #7 - 8000cc2: 009b lsls r3, r3, #2 - 8000cc4: 220f movs r2, #15 - 8000cc6: fa02 f303 lsl.w r3, r2, r3 - 8000cca: 43db mvns r3, r3 - 8000ccc: 693a ldr r2, [r7, #16] - 8000cce: 4013 ands r3, r2 - 8000cd0: 613b str r3, [r7, #16] + 8000d74: 697b ldr r3, [r7, #20] + 8000d76: f003 0307 and.w r3, r3, #7 + 8000d7a: 009b lsls r3, r3, #2 + 8000d7c: 220f movs r2, #15 + 8000d7e: fa02 f303 lsl.w r3, r2, r3 + 8000d82: 43db mvns r3, r3 + 8000d84: 693a ldr r2, [r7, #16] + 8000d86: 4013 ands r3, r2 + 8000d88: 613b str r3, [r7, #16] SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); - 8000cd2: 683b ldr r3, [r7, #0] - 8000cd4: 691a ldr r2, [r3, #16] - 8000cd6: 697b ldr r3, [r7, #20] - 8000cd8: f003 0307 and.w r3, r3, #7 - 8000cdc: 009b lsls r3, r3, #2 - 8000cde: fa02 f303 lsl.w r3, r2, r3 - 8000ce2: 693a ldr r2, [r7, #16] - 8000ce4: 4313 orrs r3, r2 - 8000ce6: 613b str r3, [r7, #16] + 8000d8a: 683b ldr r3, [r7, #0] + 8000d8c: 691a ldr r2, [r3, #16] + 8000d8e: 697b ldr r3, [r7, #20] + 8000d90: f003 0307 and.w r3, r3, #7 + 8000d94: 009b lsls r3, r3, #2 + 8000d96: fa02 f303 lsl.w r3, r2, r3 + 8000d9a: 693a ldr r2, [r7, #16] + 8000d9c: 4313 orrs r3, r2 + 8000d9e: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3] = temp; - 8000ce8: 697b ldr r3, [r7, #20] - 8000cea: 08da lsrs r2, r3, #3 - 8000cec: 687b ldr r3, [r7, #4] - 8000cee: 3208 adds r2, #8 - 8000cf0: 6939 ldr r1, [r7, #16] - 8000cf2: f843 1022 str.w r1, [r3, r2, lsl #2] + 8000da0: 697b ldr r3, [r7, #20] + 8000da2: 08da lsrs r2, r3, #3 + 8000da4: 687b ldr r3, [r7, #4] + 8000da6: 3208 adds r2, #8 + 8000da8: 6939 ldr r1, [r7, #16] + 8000daa: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 8000cf6: 687b ldr r3, [r7, #4] - 8000cf8: 681b ldr r3, [r3, #0] - 8000cfa: 613b str r3, [r7, #16] + 8000dae: 687b ldr r3, [r7, #4] + 8000db0: 681b ldr r3, [r3, #0] + 8000db2: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); - 8000cfc: 697b ldr r3, [r7, #20] - 8000cfe: 005b lsls r3, r3, #1 - 8000d00: 2203 movs r2, #3 - 8000d02: fa02 f303 lsl.w r3, r2, r3 - 8000d06: 43db mvns r3, r3 - 8000d08: 693a ldr r2, [r7, #16] - 8000d0a: 4013 ands r3, r2 - 8000d0c: 613b str r3, [r7, #16] + 8000db4: 697b ldr r3, [r7, #20] + 8000db6: 005b lsls r3, r3, #1 + 8000db8: 2203 movs r2, #3 + 8000dba: fa02 f303 lsl.w r3, r2, r3 + 8000dbe: 43db mvns r3, r3 + 8000dc0: 693a ldr r2, [r7, #16] + 8000dc2: 4013 ands r3, r2 + 8000dc4: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - 8000d0e: 683b ldr r3, [r7, #0] - 8000d10: 685b ldr r3, [r3, #4] - 8000d12: f003 0203 and.w r2, r3, #3 - 8000d16: 697b ldr r3, [r7, #20] - 8000d18: 005b lsls r3, r3, #1 - 8000d1a: fa02 f303 lsl.w r3, r2, r3 - 8000d1e: 693a ldr r2, [r7, #16] - 8000d20: 4313 orrs r3, r2 - 8000d22: 613b str r3, [r7, #16] + 8000dc6: 683b ldr r3, [r7, #0] + 8000dc8: 685b ldr r3, [r3, #4] + 8000dca: f003 0203 and.w r2, r3, #3 + 8000dce: 697b ldr r3, [r7, #20] + 8000dd0: 005b lsls r3, r3, #1 + 8000dd2: fa02 f303 lsl.w r3, r2, r3 + 8000dd6: 693a ldr r2, [r7, #16] + 8000dd8: 4313 orrs r3, r2 + 8000dda: 613b str r3, [r7, #16] GPIOx->MODER = temp; - 8000d24: 687b ldr r3, [r7, #4] - 8000d26: 693a ldr r2, [r7, #16] - 8000d28: 601a str r2, [r3, #0] + 8000ddc: 687b ldr r3, [r7, #4] + 8000dde: 693a ldr r2, [r7, #16] + 8000de0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) - 8000d2a: 683b ldr r3, [r7, #0] - 8000d2c: 685b ldr r3, [r3, #4] - 8000d2e: f403 3340 and.w r3, r3, #196608 @ 0x30000 - 8000d32: 2b00 cmp r3, #0 - 8000d34: f000 80ac beq.w 8000e90 + 8000de2: 683b ldr r3, [r7, #0] + 8000de4: 685b ldr r3, [r3, #4] + 8000de6: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 8000dea: 2b00 cmp r3, #0 + 8000dec: f000 80ac beq.w 8000f48 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8000d38: 4b5e ldr r3, [pc, #376] @ (8000eb4 ) - 8000d3a: 6a1b ldr r3, [r3, #32] - 8000d3c: 4a5d ldr r2, [pc, #372] @ (8000eb4 ) - 8000d3e: f043 0301 orr.w r3, r3, #1 - 8000d42: 6213 str r3, [r2, #32] - 8000d44: 4b5b ldr r3, [pc, #364] @ (8000eb4 ) - 8000d46: 6a1b ldr r3, [r3, #32] - 8000d48: f003 0301 and.w r3, r3, #1 - 8000d4c: 60bb str r3, [r7, #8] - 8000d4e: 68bb ldr r3, [r7, #8] + 8000df0: 4b5e ldr r3, [pc, #376] @ (8000f6c ) + 8000df2: 6a1b ldr r3, [r3, #32] + 8000df4: 4a5d ldr r2, [pc, #372] @ (8000f6c ) + 8000df6: f043 0301 orr.w r3, r3, #1 + 8000dfa: 6213 str r3, [r2, #32] + 8000dfc: 4b5b ldr r3, [pc, #364] @ (8000f6c ) + 8000dfe: 6a1b ldr r3, [r3, #32] + 8000e00: f003 0301 and.w r3, r3, #1 + 8000e04: 60bb str r3, [r7, #8] + 8000e06: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2]; - 8000d50: 4a59 ldr r2, [pc, #356] @ (8000eb8 ) - 8000d52: 697b ldr r3, [r7, #20] - 8000d54: 089b lsrs r3, r3, #2 - 8000d56: 3302 adds r3, #2 - 8000d58: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8000d5c: 613b str r3, [r7, #16] + 8000e08: 4a59 ldr r2, [pc, #356] @ (8000f70 ) + 8000e0a: 697b ldr r3, [r7, #20] + 8000e0c: 089b lsrs r3, r3, #2 + 8000e0e: 3302 adds r3, #2 + 8000e10: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8000e14: 613b str r3, [r7, #16] CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); - 8000d5e: 697b ldr r3, [r7, #20] - 8000d60: f003 0303 and.w r3, r3, #3 - 8000d64: 009b lsls r3, r3, #2 - 8000d66: 220f movs r2, #15 - 8000d68: fa02 f303 lsl.w r3, r2, r3 - 8000d6c: 43db mvns r3, r3 - 8000d6e: 693a ldr r2, [r7, #16] - 8000d70: 4013 ands r3, r2 - 8000d72: 613b str r3, [r7, #16] + 8000e16: 697b ldr r3, [r7, #20] + 8000e18: f003 0303 and.w r3, r3, #3 + 8000e1c: 009b lsls r3, r3, #2 + 8000e1e: 220f movs r2, #15 + 8000e20: fa02 f303 lsl.w r3, r2, r3 + 8000e24: 43db mvns r3, r3 + 8000e26: 693a ldr r2, [r7, #16] + 8000e28: 4013 ands r3, r2 + 8000e2a: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - 8000d74: 687b ldr r3, [r7, #4] - 8000d76: 4a51 ldr r2, [pc, #324] @ (8000ebc ) - 8000d78: 4293 cmp r3, r2 - 8000d7a: d025 beq.n 8000dc8 - 8000d7c: 687b ldr r3, [r7, #4] - 8000d7e: 4a50 ldr r2, [pc, #320] @ (8000ec0 ) - 8000d80: 4293 cmp r3, r2 - 8000d82: d01f beq.n 8000dc4 - 8000d84: 687b ldr r3, [r7, #4] - 8000d86: 4a4f ldr r2, [pc, #316] @ (8000ec4 ) - 8000d88: 4293 cmp r3, r2 - 8000d8a: d019 beq.n 8000dc0 - 8000d8c: 687b ldr r3, [r7, #4] - 8000d8e: 4a4e ldr r2, [pc, #312] @ (8000ec8 ) - 8000d90: 4293 cmp r3, r2 - 8000d92: d013 beq.n 8000dbc - 8000d94: 687b ldr r3, [r7, #4] - 8000d96: 4a4d ldr r2, [pc, #308] @ (8000ecc ) - 8000d98: 4293 cmp r3, r2 - 8000d9a: d00d beq.n 8000db8 - 8000d9c: 687b ldr r3, [r7, #4] - 8000d9e: 4a4c ldr r2, [pc, #304] @ (8000ed0 ) - 8000da0: 4293 cmp r3, r2 - 8000da2: d007 beq.n 8000db4 - 8000da4: 687b ldr r3, [r7, #4] - 8000da6: 4a4b ldr r2, [pc, #300] @ (8000ed4 ) - 8000da8: 4293 cmp r3, r2 - 8000daa: d101 bne.n 8000db0 - 8000dac: 2306 movs r3, #6 - 8000dae: e00c b.n 8000dca - 8000db0: 2307 movs r3, #7 - 8000db2: e00a b.n 8000dca - 8000db4: 2305 movs r3, #5 - 8000db6: e008 b.n 8000dca - 8000db8: 2304 movs r3, #4 - 8000dba: e006 b.n 8000dca - 8000dbc: 2303 movs r3, #3 - 8000dbe: e004 b.n 8000dca - 8000dc0: 2302 movs r3, #2 - 8000dc2: e002 b.n 8000dca - 8000dc4: 2301 movs r3, #1 - 8000dc6: e000 b.n 8000dca - 8000dc8: 2300 movs r3, #0 - 8000dca: 697a ldr r2, [r7, #20] - 8000dcc: f002 0203 and.w r2, r2, #3 - 8000dd0: 0092 lsls r2, r2, #2 - 8000dd2: 4093 lsls r3, r2 - 8000dd4: 693a ldr r2, [r7, #16] - 8000dd6: 4313 orrs r3, r2 - 8000dd8: 613b str r3, [r7, #16] + 8000e2c: 687b ldr r3, [r7, #4] + 8000e2e: 4a51 ldr r2, [pc, #324] @ (8000f74 ) + 8000e30: 4293 cmp r3, r2 + 8000e32: d025 beq.n 8000e80 + 8000e34: 687b ldr r3, [r7, #4] + 8000e36: 4a50 ldr r2, [pc, #320] @ (8000f78 ) + 8000e38: 4293 cmp r3, r2 + 8000e3a: d01f beq.n 8000e7c + 8000e3c: 687b ldr r3, [r7, #4] + 8000e3e: 4a4f ldr r2, [pc, #316] @ (8000f7c ) + 8000e40: 4293 cmp r3, r2 + 8000e42: d019 beq.n 8000e78 + 8000e44: 687b ldr r3, [r7, #4] + 8000e46: 4a4e ldr r2, [pc, #312] @ (8000f80 ) + 8000e48: 4293 cmp r3, r2 + 8000e4a: d013 beq.n 8000e74 + 8000e4c: 687b ldr r3, [r7, #4] + 8000e4e: 4a4d ldr r2, [pc, #308] @ (8000f84 ) + 8000e50: 4293 cmp r3, r2 + 8000e52: d00d beq.n 8000e70 + 8000e54: 687b ldr r3, [r7, #4] + 8000e56: 4a4c ldr r2, [pc, #304] @ (8000f88 ) + 8000e58: 4293 cmp r3, r2 + 8000e5a: d007 beq.n 8000e6c + 8000e5c: 687b ldr r3, [r7, #4] + 8000e5e: 4a4b ldr r2, [pc, #300] @ (8000f8c ) + 8000e60: 4293 cmp r3, r2 + 8000e62: d101 bne.n 8000e68 + 8000e64: 2306 movs r3, #6 + 8000e66: e00c b.n 8000e82 + 8000e68: 2307 movs r3, #7 + 8000e6a: e00a b.n 8000e82 + 8000e6c: 2305 movs r3, #5 + 8000e6e: e008 b.n 8000e82 + 8000e70: 2304 movs r3, #4 + 8000e72: e006 b.n 8000e82 + 8000e74: 2303 movs r3, #3 + 8000e76: e004 b.n 8000e82 + 8000e78: 2302 movs r3, #2 + 8000e7a: e002 b.n 8000e82 + 8000e7c: 2301 movs r3, #1 + 8000e7e: e000 b.n 8000e82 + 8000e80: 2300 movs r3, #0 + 8000e82: 697a ldr r2, [r7, #20] + 8000e84: f002 0203 and.w r2, r2, #3 + 8000e88: 0092 lsls r2, r2, #2 + 8000e8a: 4093 lsls r3, r2 + 8000e8c: 693a ldr r2, [r7, #16] + 8000e8e: 4313 orrs r3, r2 + 8000e90: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2] = temp; - 8000dda: 4937 ldr r1, [pc, #220] @ (8000eb8 ) - 8000ddc: 697b ldr r3, [r7, #20] - 8000dde: 089b lsrs r3, r3, #2 - 8000de0: 3302 adds r3, #2 - 8000de2: 693a ldr r2, [r7, #16] - 8000de4: f841 2023 str.w r2, [r1, r3, lsl #2] + 8000e92: 4937 ldr r1, [pc, #220] @ (8000f70 ) + 8000e94: 697b ldr r3, [r7, #20] + 8000e96: 089b lsrs r3, r3, #2 + 8000e98: 3302 adds r3, #2 + 8000e9a: 693a ldr r2, [r7, #16] + 8000e9c: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 8000de8: 4b3b ldr r3, [pc, #236] @ (8000ed8 ) - 8000dea: 689b ldr r3, [r3, #8] - 8000dec: 613b str r3, [r7, #16] + 8000ea0: 4b3b ldr r3, [pc, #236] @ (8000f90 ) + 8000ea2: 689b ldr r3, [r3, #8] + 8000ea4: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000dee: 68fb ldr r3, [r7, #12] - 8000df0: 43db mvns r3, r3 - 8000df2: 693a ldr r2, [r7, #16] - 8000df4: 4013 ands r3, r2 - 8000df6: 613b str r3, [r7, #16] + 8000ea6: 68fb ldr r3, [r7, #12] + 8000ea8: 43db mvns r3, r3 + 8000eaa: 693a ldr r2, [r7, #16] + 8000eac: 4013 ands r3, r2 + 8000eae: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) - 8000df8: 683b ldr r3, [r7, #0] - 8000dfa: 685b ldr r3, [r3, #4] - 8000dfc: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 8000e00: 2b00 cmp r3, #0 - 8000e02: d003 beq.n 8000e0c + 8000eb0: 683b ldr r3, [r7, #0] + 8000eb2: 685b ldr r3, [r3, #4] + 8000eb4: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8000eb8: 2b00 cmp r3, #0 + 8000eba: d003 beq.n 8000ec4 { SET_BIT(temp, iocurrent); - 8000e04: 693a ldr r2, [r7, #16] - 8000e06: 68fb ldr r3, [r7, #12] - 8000e08: 4313 orrs r3, r2 - 8000e0a: 613b str r3, [r7, #16] + 8000ebc: 693a ldr r2, [r7, #16] + 8000ebe: 68fb ldr r3, [r7, #12] + 8000ec0: 4313 orrs r3, r2 + 8000ec2: 613b str r3, [r7, #16] } EXTI->RTSR = temp; - 8000e0c: 4a32 ldr r2, [pc, #200] @ (8000ed8 ) - 8000e0e: 693b ldr r3, [r7, #16] - 8000e10: 6093 str r3, [r2, #8] + 8000ec4: 4a32 ldr r2, [pc, #200] @ (8000f90 ) + 8000ec6: 693b ldr r3, [r7, #16] + 8000ec8: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 8000e12: 4b31 ldr r3, [pc, #196] @ (8000ed8 ) - 8000e14: 68db ldr r3, [r3, #12] - 8000e16: 613b str r3, [r7, #16] + 8000eca: 4b31 ldr r3, [pc, #196] @ (8000f90 ) + 8000ecc: 68db ldr r3, [r3, #12] + 8000ece: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000e18: 68fb ldr r3, [r7, #12] - 8000e1a: 43db mvns r3, r3 - 8000e1c: 693a ldr r2, [r7, #16] - 8000e1e: 4013 ands r3, r2 - 8000e20: 613b str r3, [r7, #16] + 8000ed0: 68fb ldr r3, [r7, #12] + 8000ed2: 43db mvns r3, r3 + 8000ed4: 693a ldr r2, [r7, #16] + 8000ed6: 4013 ands r3, r2 + 8000ed8: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) - 8000e22: 683b ldr r3, [r7, #0] - 8000e24: 685b ldr r3, [r3, #4] - 8000e26: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 8000e2a: 2b00 cmp r3, #0 - 8000e2c: d003 beq.n 8000e36 + 8000eda: 683b ldr r3, [r7, #0] + 8000edc: 685b ldr r3, [r3, #4] + 8000ede: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8000ee2: 2b00 cmp r3, #0 + 8000ee4: d003 beq.n 8000eee { SET_BIT(temp, iocurrent); - 8000e2e: 693a ldr r2, [r7, #16] - 8000e30: 68fb ldr r3, [r7, #12] - 8000e32: 4313 orrs r3, r2 - 8000e34: 613b str r3, [r7, #16] + 8000ee6: 693a ldr r2, [r7, #16] + 8000ee8: 68fb ldr r3, [r7, #12] + 8000eea: 4313 orrs r3, r2 + 8000eec: 613b str r3, [r7, #16] } EXTI->FTSR = temp; - 8000e36: 4a28 ldr r2, [pc, #160] @ (8000ed8 ) - 8000e38: 693b ldr r3, [r7, #16] - 8000e3a: 60d3 str r3, [r2, #12] + 8000eee: 4a28 ldr r2, [pc, #160] @ (8000f90 ) + 8000ef0: 693b ldr r3, [r7, #16] + 8000ef2: 60d3 str r3, [r2, #12] temp = EXTI->EMR; - 8000e3c: 4b26 ldr r3, [pc, #152] @ (8000ed8 ) - 8000e3e: 685b ldr r3, [r3, #4] - 8000e40: 613b str r3, [r7, #16] + 8000ef4: 4b26 ldr r3, [pc, #152] @ (8000f90 ) + 8000ef6: 685b ldr r3, [r3, #4] + 8000ef8: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000e42: 68fb ldr r3, [r7, #12] - 8000e44: 43db mvns r3, r3 - 8000e46: 693a ldr r2, [r7, #16] - 8000e48: 4013 ands r3, r2 - 8000e4a: 613b str r3, [r7, #16] + 8000efa: 68fb ldr r3, [r7, #12] + 8000efc: 43db mvns r3, r3 + 8000efe: 693a ldr r2, [r7, #16] + 8000f00: 4013 ands r3, r2 + 8000f02: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) - 8000e4c: 683b ldr r3, [r7, #0] - 8000e4e: 685b ldr r3, [r3, #4] - 8000e50: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8000e54: 2b00 cmp r3, #0 - 8000e56: d003 beq.n 8000e60 + 8000f04: 683b ldr r3, [r7, #0] + 8000f06: 685b ldr r3, [r3, #4] + 8000f08: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8000f0c: 2b00 cmp r3, #0 + 8000f0e: d003 beq.n 8000f18 { SET_BIT(temp, iocurrent); - 8000e58: 693a ldr r2, [r7, #16] - 8000e5a: 68fb ldr r3, [r7, #12] - 8000e5c: 4313 orrs r3, r2 - 8000e5e: 613b str r3, [r7, #16] + 8000f10: 693a ldr r2, [r7, #16] + 8000f12: 68fb ldr r3, [r7, #12] + 8000f14: 4313 orrs r3, r2 + 8000f16: 613b str r3, [r7, #16] } EXTI->EMR = temp; - 8000e60: 4a1d ldr r2, [pc, #116] @ (8000ed8 ) - 8000e62: 693b ldr r3, [r7, #16] - 8000e64: 6053 str r3, [r2, #4] + 8000f18: 4a1d ldr r2, [pc, #116] @ (8000f90 ) + 8000f1a: 693b ldr r3, [r7, #16] + 8000f1c: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 8000e66: 4b1c ldr r3, [pc, #112] @ (8000ed8 ) - 8000e68: 681b ldr r3, [r3, #0] - 8000e6a: 613b str r3, [r7, #16] + 8000f1e: 4b1c ldr r3, [pc, #112] @ (8000f90 ) + 8000f20: 681b ldr r3, [r3, #0] + 8000f22: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000e6c: 68fb ldr r3, [r7, #12] - 8000e6e: 43db mvns r3, r3 - 8000e70: 693a ldr r2, [r7, #16] - 8000e72: 4013 ands r3, r2 - 8000e74: 613b str r3, [r7, #16] + 8000f24: 68fb ldr r3, [r7, #12] + 8000f26: 43db mvns r3, r3 + 8000f28: 693a ldr r2, [r7, #16] + 8000f2a: 4013 ands r3, r2 + 8000f2c: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) - 8000e76: 683b ldr r3, [r7, #0] - 8000e78: 685b ldr r3, [r3, #4] - 8000e7a: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8000e7e: 2b00 cmp r3, #0 - 8000e80: d003 beq.n 8000e8a + 8000f2e: 683b ldr r3, [r7, #0] + 8000f30: 685b ldr r3, [r3, #4] + 8000f32: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8000f36: 2b00 cmp r3, #0 + 8000f38: d003 beq.n 8000f42 { SET_BIT(temp, iocurrent); - 8000e82: 693a ldr r2, [r7, #16] - 8000e84: 68fb ldr r3, [r7, #12] - 8000e86: 4313 orrs r3, r2 - 8000e88: 613b str r3, [r7, #16] + 8000f3a: 693a ldr r2, [r7, #16] + 8000f3c: 68fb ldr r3, [r7, #12] + 8000f3e: 4313 orrs r3, r2 + 8000f40: 613b str r3, [r7, #16] } EXTI->IMR = temp; - 8000e8a: 4a13 ldr r2, [pc, #76] @ (8000ed8 ) - 8000e8c: 693b ldr r3, [r7, #16] - 8000e8e: 6013 str r3, [r2, #0] + 8000f42: 4a13 ldr r2, [pc, #76] @ (8000f90 ) + 8000f44: 693b ldr r3, [r7, #16] + 8000f46: 6013 str r3, [r2, #0] } } position++; - 8000e90: 697b ldr r3, [r7, #20] - 8000e92: 3301 adds r3, #1 - 8000e94: 617b str r3, [r7, #20] + 8000f48: 697b ldr r3, [r7, #20] + 8000f4a: 3301 adds r3, #1 + 8000f4c: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0) - 8000e96: 683b ldr r3, [r7, #0] - 8000e98: 681a ldr r2, [r3, #0] - 8000e9a: 697b ldr r3, [r7, #20] - 8000e9c: fa22 f303 lsr.w r3, r2, r3 - 8000ea0: 2b00 cmp r3, #0 - 8000ea2: f47f ae97 bne.w 8000bd4 + 8000f4e: 683b ldr r3, [r7, #0] + 8000f50: 681a ldr r2, [r3, #0] + 8000f52: 697b ldr r3, [r7, #20] + 8000f54: fa22 f303 lsr.w r3, r2, r3 + 8000f58: 2b00 cmp r3, #0 + 8000f5a: f47f ae97 bne.w 8000c8c } } - 8000ea6: bf00 nop - 8000ea8: bf00 nop - 8000eaa: 371c adds r7, #28 - 8000eac: 46bd mov sp, r7 - 8000eae: bc80 pop {r7} - 8000eb0: 4770 bx lr - 8000eb2: bf00 nop - 8000eb4: 40023800 .word 0x40023800 - 8000eb8: 40010000 .word 0x40010000 - 8000ebc: 40020000 .word 0x40020000 - 8000ec0: 40020400 .word 0x40020400 - 8000ec4: 40020800 .word 0x40020800 - 8000ec8: 40020c00 .word 0x40020c00 - 8000ecc: 40021000 .word 0x40021000 - 8000ed0: 40021400 .word 0x40021400 - 8000ed4: 40021800 .word 0x40021800 - 8000ed8: 40010400 .word 0x40010400 + 8000f5e: bf00 nop + 8000f60: bf00 nop + 8000f62: 371c adds r7, #28 + 8000f64: 46bd mov sp, r7 + 8000f66: bc80 pop {r7} + 8000f68: 4770 bx lr + 8000f6a: bf00 nop + 8000f6c: 40023800 .word 0x40023800 + 8000f70: 40010000 .word 0x40010000 + 8000f74: 40020000 .word 0x40020000 + 8000f78: 40020400 .word 0x40020400 + 8000f7c: 40020800 .word 0x40020800 + 8000f80: 40020c00 .word 0x40020c00 + 8000f84: 40021000 .word 0x40021000 + 8000f88: 40021400 .word 0x40021400 + 8000f8c: 40021800 .word 0x40021800 + 8000f90: 40010400 .word 0x40010400 -08000edc : +08000f94 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8000edc: b480 push {r7} - 8000ede: b083 sub sp, #12 - 8000ee0: af00 add r7, sp, #0 - 8000ee2: 6078 str r0, [r7, #4] - 8000ee4: 460b mov r3, r1 - 8000ee6: 807b strh r3, [r7, #2] - 8000ee8: 4613 mov r3, r2 - 8000eea: 707b strb r3, [r7, #1] + 8000f94: b480 push {r7} + 8000f96: b083 sub sp, #12 + 8000f98: af00 add r7, sp, #0 + 8000f9a: 6078 str r0, [r7, #4] + 8000f9c: 460b mov r3, r1 + 8000f9e: 807b strh r3, [r7, #2] + 8000fa0: 4613 mov r3, r2 + 8000fa2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) - 8000eec: 787b ldrb r3, [r7, #1] - 8000eee: 2b00 cmp r3, #0 - 8000ef0: d003 beq.n 8000efa + 8000fa4: 787b ldrb r3, [r7, #1] + 8000fa6: 2b00 cmp r3, #0 + 8000fa8: d003 beq.n 8000fb2 { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 8000ef2: 887a ldrh r2, [r7, #2] - 8000ef4: 687b ldr r3, [r7, #4] - 8000ef6: 619a str r2, [r3, #24] + 8000faa: 887a ldrh r2, [r7, #2] + 8000fac: 687b ldr r3, [r7, #4] + 8000fae: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; } } - 8000ef8: e003 b.n 8000f02 + 8000fb0: e003 b.n 8000fba GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; - 8000efa: 887b ldrh r3, [r7, #2] - 8000efc: 041a lsls r2, r3, #16 - 8000efe: 687b ldr r3, [r7, #4] - 8000f00: 619a str r2, [r3, #24] + 8000fb2: 887b ldrh r3, [r7, #2] + 8000fb4: 041a lsls r2, r3, #16 + 8000fb6: 687b ldr r3, [r7, #4] + 8000fb8: 619a str r2, [r3, #24] } - 8000f02: bf00 nop - 8000f04: 370c adds r7, #12 - 8000f06: 46bd mov sp, r7 - 8000f08: bc80 pop {r7} - 8000f0a: 4770 bx lr + 8000fba: bf00 nop + 8000fbc: 370c adds r7, #12 + 8000fbe: 46bd mov sp, r7 + 8000fc0: bc80 pop {r7} + 8000fc2: 4770 bx lr -08000f0c : +08000fc4 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8000f0c: b580 push {r7, lr} - 8000f0e: b088 sub sp, #32 - 8000f10: af00 add r7, sp, #0 - 8000f12: 6078 str r0, [r7, #4] + 8000fc4: b580 push {r7, lr} + 8000fc6: b088 sub sp, #32 + 8000fc8: af00 add r7, sp, #0 + 8000fca: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status; uint32_t sysclk_source, pll_config; /* Check the parameters */ if(RCC_OscInitStruct == NULL) - 8000f14: 687b ldr r3, [r7, #4] - 8000f16: 2b00 cmp r3, #0 - 8000f18: d101 bne.n 8000f1e + 8000fcc: 687b ldr r3, [r7, #4] + 8000fce: 2b00 cmp r3, #0 + 8000fd0: d101 bne.n 8000fd6 { return HAL_ERROR; - 8000f1a: 2301 movs r3, #1 - 8000f1c: e31d b.n 800155a + 8000fd2: 2301 movs r3, #1 + 8000fd4: e31d b.n 8001612 } assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8000f1e: 4b94 ldr r3, [pc, #592] @ (8001170 ) - 8000f20: 689b ldr r3, [r3, #8] - 8000f22: f003 030c and.w r3, r3, #12 - 8000f26: 61bb str r3, [r7, #24] + 8000fd6: 4b94 ldr r3, [pc, #592] @ (8001228 ) + 8000fd8: 689b ldr r3, [r3, #8] + 8000fda: f003 030c and.w r3, r3, #12 + 8000fde: 61bb str r3, [r7, #24] pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); - 8000f28: 4b91 ldr r3, [pc, #580] @ (8001170 ) - 8000f2a: 689b ldr r3, [r3, #8] - 8000f2c: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8000f30: 617b str r3, [r7, #20] + 8000fe0: 4b91 ldr r3, [pc, #580] @ (8001228 ) + 8000fe2: 689b ldr r3, [r3, #8] + 8000fe4: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8000fe8: 617b str r3, [r7, #20] /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8000f32: 687b ldr r3, [r7, #4] - 8000f34: 681b ldr r3, [r3, #0] - 8000f36: f003 0301 and.w r3, r3, #1 - 8000f3a: 2b00 cmp r3, #0 - 8000f3c: d07b beq.n 8001036 + 8000fea: 687b ldr r3, [r7, #4] + 8000fec: 681b ldr r3, [r3, #0] + 8000fee: f003 0301 and.w r3, r3, #1 + 8000ff2: 2b00 cmp r3, #0 + 8000ff4: d07b beq.n 80010ee { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) - 8000f3e: 69bb ldr r3, [r7, #24] - 8000f40: 2b08 cmp r3, #8 - 8000f42: d006 beq.n 8000f52 + 8000ff6: 69bb ldr r3, [r7, #24] + 8000ff8: 2b08 cmp r3, #8 + 8000ffa: d006 beq.n 800100a || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) - 8000f44: 69bb ldr r3, [r7, #24] - 8000f46: 2b0c cmp r3, #12 - 8000f48: d10f bne.n 8000f6a - 8000f4a: 697b ldr r3, [r7, #20] - 8000f4c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8000f50: d10b bne.n 8000f6a + 8000ffc: 69bb ldr r3, [r7, #24] + 8000ffe: 2b0c cmp r3, #12 + 8001000: d10f bne.n 8001022 + 8001002: 697b ldr r3, [r7, #20] + 8001004: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8001008: d10b bne.n 8001022 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8000f52: 4b87 ldr r3, [pc, #540] @ (8001170 ) - 8000f54: 681b ldr r3, [r3, #0] - 8000f56: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8000f5a: 2b00 cmp r3, #0 - 8000f5c: d06a beq.n 8001034 - 8000f5e: 687b ldr r3, [r7, #4] - 8000f60: 685b ldr r3, [r3, #4] - 8000f62: 2b00 cmp r3, #0 - 8000f64: d166 bne.n 8001034 + 800100a: 4b87 ldr r3, [pc, #540] @ (8001228 ) + 800100c: 681b ldr r3, [r3, #0] + 800100e: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8001012: 2b00 cmp r3, #0 + 8001014: d06a beq.n 80010ec + 8001016: 687b ldr r3, [r7, #4] + 8001018: 685b ldr r3, [r3, #4] + 800101a: 2b00 cmp r3, #0 + 800101c: d166 bne.n 80010ec { return HAL_ERROR; - 8000f66: 2301 movs r3, #1 - 8000f68: e2f7 b.n 800155a + 800101e: 2301 movs r3, #1 + 8001020: e2f7 b.n 8001612 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8000f6a: 687b ldr r3, [r7, #4] - 8000f6c: 685b ldr r3, [r3, #4] - 8000f6e: 2b01 cmp r3, #1 - 8000f70: d106 bne.n 8000f80 - 8000f72: 4b7f ldr r3, [pc, #508] @ (8001170 ) - 8000f74: 681b ldr r3, [r3, #0] - 8000f76: 4a7e ldr r2, [pc, #504] @ (8001170 ) - 8000f78: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8000f7c: 6013 str r3, [r2, #0] - 8000f7e: e02d b.n 8000fdc - 8000f80: 687b ldr r3, [r7, #4] - 8000f82: 685b ldr r3, [r3, #4] - 8000f84: 2b00 cmp r3, #0 - 8000f86: d10c bne.n 8000fa2 - 8000f88: 4b79 ldr r3, [pc, #484] @ (8001170 ) - 8000f8a: 681b ldr r3, [r3, #0] - 8000f8c: 4a78 ldr r2, [pc, #480] @ (8001170 ) - 8000f8e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8000f92: 6013 str r3, [r2, #0] - 8000f94: 4b76 ldr r3, [pc, #472] @ (8001170 ) - 8000f96: 681b ldr r3, [r3, #0] - 8000f98: 4a75 ldr r2, [pc, #468] @ (8001170 ) - 8000f9a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 8000f9e: 6013 str r3, [r2, #0] - 8000fa0: e01c b.n 8000fdc - 8000fa2: 687b ldr r3, [r7, #4] - 8000fa4: 685b ldr r3, [r3, #4] - 8000fa6: 2b05 cmp r3, #5 - 8000fa8: d10c bne.n 8000fc4 - 8000faa: 4b71 ldr r3, [pc, #452] @ (8001170 ) - 8000fac: 681b ldr r3, [r3, #0] - 8000fae: 4a70 ldr r2, [pc, #448] @ (8001170 ) - 8000fb0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 8000fb4: 6013 str r3, [r2, #0] - 8000fb6: 4b6e ldr r3, [pc, #440] @ (8001170 ) - 8000fb8: 681b ldr r3, [r3, #0] - 8000fba: 4a6d ldr r2, [pc, #436] @ (8001170 ) - 8000fbc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8000fc0: 6013 str r3, [r2, #0] - 8000fc2: e00b b.n 8000fdc - 8000fc4: 4b6a ldr r3, [pc, #424] @ (8001170 ) - 8000fc6: 681b ldr r3, [r3, #0] - 8000fc8: 4a69 ldr r2, [pc, #420] @ (8001170 ) - 8000fca: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8000fce: 6013 str r3, [r2, #0] - 8000fd0: 4b67 ldr r3, [pc, #412] @ (8001170 ) - 8000fd2: 681b ldr r3, [r3, #0] - 8000fd4: 4a66 ldr r2, [pc, #408] @ (8001170 ) - 8000fd6: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 8000fda: 6013 str r3, [r2, #0] + 8001022: 687b ldr r3, [r7, #4] + 8001024: 685b ldr r3, [r3, #4] + 8001026: 2b01 cmp r3, #1 + 8001028: d106 bne.n 8001038 + 800102a: 4b7f ldr r3, [pc, #508] @ (8001228 ) + 800102c: 681b ldr r3, [r3, #0] + 800102e: 4a7e ldr r2, [pc, #504] @ (8001228 ) + 8001030: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001034: 6013 str r3, [r2, #0] + 8001036: e02d b.n 8001094 + 8001038: 687b ldr r3, [r7, #4] + 800103a: 685b ldr r3, [r3, #4] + 800103c: 2b00 cmp r3, #0 + 800103e: d10c bne.n 800105a + 8001040: 4b79 ldr r3, [pc, #484] @ (8001228 ) + 8001042: 681b ldr r3, [r3, #0] + 8001044: 4a78 ldr r2, [pc, #480] @ (8001228 ) + 8001046: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 800104a: 6013 str r3, [r2, #0] + 800104c: 4b76 ldr r3, [pc, #472] @ (8001228 ) + 800104e: 681b ldr r3, [r3, #0] + 8001050: 4a75 ldr r2, [pc, #468] @ (8001228 ) + 8001052: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001056: 6013 str r3, [r2, #0] + 8001058: e01c b.n 8001094 + 800105a: 687b ldr r3, [r7, #4] + 800105c: 685b ldr r3, [r3, #4] + 800105e: 2b05 cmp r3, #5 + 8001060: d10c bne.n 800107c + 8001062: 4b71 ldr r3, [pc, #452] @ (8001228 ) + 8001064: 681b ldr r3, [r3, #0] + 8001066: 4a70 ldr r2, [pc, #448] @ (8001228 ) + 8001068: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 800106c: 6013 str r3, [r2, #0] + 800106e: 4b6e ldr r3, [pc, #440] @ (8001228 ) + 8001070: 681b ldr r3, [r3, #0] + 8001072: 4a6d ldr r2, [pc, #436] @ (8001228 ) + 8001074: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8001078: 6013 str r3, [r2, #0] + 800107a: e00b b.n 8001094 + 800107c: 4b6a ldr r3, [pc, #424] @ (8001228 ) + 800107e: 681b ldr r3, [r3, #0] + 8001080: 4a69 ldr r2, [pc, #420] @ (8001228 ) + 8001082: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8001086: 6013 str r3, [r2, #0] + 8001088: 4b67 ldr r3, [pc, #412] @ (8001228 ) + 800108a: 681b ldr r3, [r3, #0] + 800108c: 4a66 ldr r2, [pc, #408] @ (8001228 ) + 800108e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8001092: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8000fdc: 687b ldr r3, [r7, #4] - 8000fde: 685b ldr r3, [r3, #4] - 8000fe0: 2b00 cmp r3, #0 - 8000fe2: d013 beq.n 800100c + 8001094: 687b ldr r3, [r7, #4] + 8001096: 685b ldr r3, [r3, #4] + 8001098: 2b00 cmp r3, #0 + 800109a: d013 beq.n 80010c4 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8000fe4: f7ff fcfc bl 80009e0 - 8000fe8: 6138 str r0, [r7, #16] + 800109c: f7ff fcda bl 8000a54 + 80010a0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - 8000fea: e008 b.n 8000ffe + 80010a2: e008 b.n 80010b6 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 8000fec: f7ff fcf8 bl 80009e0 - 8000ff0: 4602 mov r2, r0 - 8000ff2: 693b ldr r3, [r7, #16] - 8000ff4: 1ad3 subs r3, r2, r3 - 8000ff6: 2b64 cmp r3, #100 @ 0x64 - 8000ff8: d901 bls.n 8000ffe + 80010a4: f7ff fcd6 bl 8000a54 + 80010a8: 4602 mov r2, r0 + 80010aa: 693b ldr r3, [r7, #16] + 80010ac: 1ad3 subs r3, r2, r3 + 80010ae: 2b64 cmp r3, #100 @ 0x64 + 80010b0: d901 bls.n 80010b6 { return HAL_TIMEOUT; - 8000ffa: 2303 movs r3, #3 - 8000ffc: e2ad b.n 800155a + 80010b2: 2303 movs r3, #3 + 80010b4: e2ad b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - 8000ffe: 4b5c ldr r3, [pc, #368] @ (8001170 ) - 8001000: 681b ldr r3, [r3, #0] - 8001002: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8001006: 2b00 cmp r3, #0 - 8001008: d0f0 beq.n 8000fec - 800100a: e014 b.n 8001036 + 80010b6: 4b5c ldr r3, [pc, #368] @ (8001228 ) + 80010b8: 681b ldr r3, [r3, #0] + 80010ba: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80010be: 2b00 cmp r3, #0 + 80010c0: d0f0 beq.n 80010a4 + 80010c2: e014 b.n 80010ee } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 800100c: f7ff fce8 bl 80009e0 - 8001010: 6138 str r0, [r7, #16] + 80010c4: f7ff fcc6 bl 8000a54 + 80010c8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) - 8001012: e008 b.n 8001026 + 80010ca: e008 b.n 80010de { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 8001014: f7ff fce4 bl 80009e0 - 8001018: 4602 mov r2, r0 - 800101a: 693b ldr r3, [r7, #16] - 800101c: 1ad3 subs r3, r2, r3 - 800101e: 2b64 cmp r3, #100 @ 0x64 - 8001020: d901 bls.n 8001026 + 80010cc: f7ff fcc2 bl 8000a54 + 80010d0: 4602 mov r2, r0 + 80010d2: 693b ldr r3, [r7, #16] + 80010d4: 1ad3 subs r3, r2, r3 + 80010d6: 2b64 cmp r3, #100 @ 0x64 + 80010d8: d901 bls.n 80010de { return HAL_TIMEOUT; - 8001022: 2303 movs r3, #3 - 8001024: e299 b.n 800155a + 80010da: 2303 movs r3, #3 + 80010dc: e299 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) - 8001026: 4b52 ldr r3, [pc, #328] @ (8001170 ) - 8001028: 681b ldr r3, [r3, #0] - 800102a: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 800102e: 2b00 cmp r3, #0 - 8001030: d1f0 bne.n 8001014 - 8001032: e000 b.n 8001036 + 80010de: 4b52 ldr r3, [pc, #328] @ (8001228 ) + 80010e0: 681b ldr r3, [r3, #0] + 80010e2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80010e6: 2b00 cmp r3, #0 + 80010e8: d1f0 bne.n 80010cc + 80010ea: e000 b.n 80010ee if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8001034: bf00 nop + 80010ec: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8001036: 687b ldr r3, [r7, #4] - 8001038: 681b ldr r3, [r3, #0] - 800103a: f003 0302 and.w r3, r3, #2 - 800103e: 2b00 cmp r3, #0 - 8001040: d05a beq.n 80010f8 + 80010ee: 687b ldr r3, [r7, #4] + 80010f0: 681b ldr r3, [r3, #0] + 80010f2: f003 0302 and.w r3, r3, #2 + 80010f6: 2b00 cmp r3, #0 + 80010f8: d05a beq.n 80011b0 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) - 8001042: 69bb ldr r3, [r7, #24] - 8001044: 2b04 cmp r3, #4 - 8001046: d005 beq.n 8001054 + 80010fa: 69bb ldr r3, [r7, #24] + 80010fc: 2b04 cmp r3, #4 + 80010fe: d005 beq.n 800110c || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) - 8001048: 69bb ldr r3, [r7, #24] - 800104a: 2b0c cmp r3, #12 - 800104c: d119 bne.n 8001082 - 800104e: 697b ldr r3, [r7, #20] - 8001050: 2b00 cmp r3, #0 - 8001052: d116 bne.n 8001082 + 8001100: 69bb ldr r3, [r7, #24] + 8001102: 2b0c cmp r3, #12 + 8001104: d119 bne.n 800113a + 8001106: 697b ldr r3, [r7, #20] + 8001108: 2b00 cmp r3, #0 + 800110a: d116 bne.n 800113a { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001054: 4b46 ldr r3, [pc, #280] @ (8001170 ) - 8001056: 681b ldr r3, [r3, #0] - 8001058: f003 0302 and.w r3, r3, #2 - 800105c: 2b00 cmp r3, #0 - 800105e: d005 beq.n 800106c - 8001060: 687b ldr r3, [r7, #4] - 8001062: 68db ldr r3, [r3, #12] - 8001064: 2b01 cmp r3, #1 - 8001066: d001 beq.n 800106c + 800110c: 4b46 ldr r3, [pc, #280] @ (8001228 ) + 800110e: 681b ldr r3, [r3, #0] + 8001110: f003 0302 and.w r3, r3, #2 + 8001114: 2b00 cmp r3, #0 + 8001116: d005 beq.n 8001124 + 8001118: 687b ldr r3, [r7, #4] + 800111a: 68db ldr r3, [r3, #12] + 800111c: 2b01 cmp r3, #1 + 800111e: d001 beq.n 8001124 { return HAL_ERROR; - 8001068: 2301 movs r3, #1 - 800106a: e276 b.n 800155a + 8001120: 2301 movs r3, #1 + 8001122: e276 b.n 8001612 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 800106c: 4b40 ldr r3, [pc, #256] @ (8001170 ) - 800106e: 685b ldr r3, [r3, #4] - 8001070: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 - 8001074: 687b ldr r3, [r7, #4] - 8001076: 691b ldr r3, [r3, #16] - 8001078: 021b lsls r3, r3, #8 - 800107a: 493d ldr r1, [pc, #244] @ (8001170 ) - 800107c: 4313 orrs r3, r2 - 800107e: 604b str r3, [r1, #4] + 8001124: 4b40 ldr r3, [pc, #256] @ (8001228 ) + 8001126: 685b ldr r3, [r3, #4] + 8001128: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 800112c: 687b ldr r3, [r7, #4] + 800112e: 691b ldr r3, [r3, #16] + 8001130: 021b lsls r3, r3, #8 + 8001132: 493d ldr r1, [pc, #244] @ (8001228 ) + 8001134: 4313 orrs r3, r2 + 8001136: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001080: e03a b.n 80010f8 + 8001138: e03a b.n 80011b0 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 8001082: 687b ldr r3, [r7, #4] - 8001084: 68db ldr r3, [r3, #12] - 8001086: 2b00 cmp r3, #0 - 8001088: d020 beq.n 80010cc + 800113a: 687b ldr r3, [r7, #4] + 800113c: 68db ldr r3, [r3, #12] + 800113e: 2b00 cmp r3, #0 + 8001140: d020 beq.n 8001184 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 800108a: 4b3a ldr r3, [pc, #232] @ (8001174 ) - 800108c: 2201 movs r2, #1 - 800108e: 601a str r2, [r3, #0] + 8001142: 4b3a ldr r3, [pc, #232] @ (800122c ) + 8001144: 2201 movs r2, #1 + 8001146: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001090: f7ff fca6 bl 80009e0 - 8001094: 6138 str r0, [r7, #16] + 8001148: f7ff fc84 bl 8000a54 + 800114c: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - 8001096: e008 b.n 80010aa + 800114e: e008 b.n 8001162 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8001098: f7ff fca2 bl 80009e0 - 800109c: 4602 mov r2, r0 - 800109e: 693b ldr r3, [r7, #16] - 80010a0: 1ad3 subs r3, r2, r3 - 80010a2: 2b02 cmp r3, #2 - 80010a4: d901 bls.n 80010aa + 8001150: f7ff fc80 bl 8000a54 + 8001154: 4602 mov r2, r0 + 8001156: 693b ldr r3, [r7, #16] + 8001158: 1ad3 subs r3, r2, r3 + 800115a: 2b02 cmp r3, #2 + 800115c: d901 bls.n 8001162 { return HAL_TIMEOUT; - 80010a6: 2303 movs r3, #3 - 80010a8: e257 b.n 800155a + 800115e: 2303 movs r3, #3 + 8001160: e257 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - 80010aa: 4b31 ldr r3, [pc, #196] @ (8001170 ) - 80010ac: 681b ldr r3, [r3, #0] - 80010ae: f003 0302 and.w r3, r3, #2 - 80010b2: 2b00 cmp r3, #0 - 80010b4: d0f0 beq.n 8001098 + 8001162: 4b31 ldr r3, [pc, #196] @ (8001228 ) + 8001164: 681b ldr r3, [r3, #0] + 8001166: f003 0302 and.w r3, r3, #2 + 800116a: 2b00 cmp r3, #0 + 800116c: d0f0 beq.n 8001150 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 80010b6: 4b2e ldr r3, [pc, #184] @ (8001170 ) - 80010b8: 685b ldr r3, [r3, #4] - 80010ba: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 - 80010be: 687b ldr r3, [r7, #4] - 80010c0: 691b ldr r3, [r3, #16] - 80010c2: 021b lsls r3, r3, #8 - 80010c4: 492a ldr r1, [pc, #168] @ (8001170 ) - 80010c6: 4313 orrs r3, r2 - 80010c8: 604b str r3, [r1, #4] - 80010ca: e015 b.n 80010f8 + 800116e: 4b2e ldr r3, [pc, #184] @ (8001228 ) + 8001170: 685b ldr r3, [r3, #4] + 8001172: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 + 8001176: 687b ldr r3, [r7, #4] + 8001178: 691b ldr r3, [r3, #16] + 800117a: 021b lsls r3, r3, #8 + 800117c: 492a ldr r1, [pc, #168] @ (8001228 ) + 800117e: 4313 orrs r3, r2 + 8001180: 604b str r3, [r1, #4] + 8001182: e015 b.n 80011b0 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 80010cc: 4b29 ldr r3, [pc, #164] @ (8001174 ) - 80010ce: 2200 movs r2, #0 - 80010d0: 601a str r2, [r3, #0] + 8001184: 4b29 ldr r3, [pc, #164] @ (800122c ) + 8001186: 2200 movs r2, #0 + 8001188: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80010d2: f7ff fc85 bl 80009e0 - 80010d6: 6138 str r0, [r7, #16] + 800118a: f7ff fc63 bl 8000a54 + 800118e: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) - 80010d8: e008 b.n 80010ec + 8001190: e008 b.n 80011a4 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 80010da: f7ff fc81 bl 80009e0 - 80010de: 4602 mov r2, r0 - 80010e0: 693b ldr r3, [r7, #16] - 80010e2: 1ad3 subs r3, r2, r3 - 80010e4: 2b02 cmp r3, #2 - 80010e6: d901 bls.n 80010ec + 8001192: f7ff fc5f bl 8000a54 + 8001196: 4602 mov r2, r0 + 8001198: 693b ldr r3, [r7, #16] + 800119a: 1ad3 subs r3, r2, r3 + 800119c: 2b02 cmp r3, #2 + 800119e: d901 bls.n 80011a4 { return HAL_TIMEOUT; - 80010e8: 2303 movs r3, #3 - 80010ea: e236 b.n 800155a + 80011a0: 2303 movs r3, #3 + 80011a2: e236 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) - 80010ec: 4b20 ldr r3, [pc, #128] @ (8001170 ) - 80010ee: 681b ldr r3, [r3, #0] - 80010f0: f003 0302 and.w r3, r3, #2 - 80010f4: 2b00 cmp r3, #0 - 80010f6: d1f0 bne.n 80010da + 80011a4: 4b20 ldr r3, [pc, #128] @ (8001228 ) + 80011a6: 681b ldr r3, [r3, #0] + 80011a8: f003 0302 and.w r3, r3, #2 + 80011ac: 2b00 cmp r3, #0 + 80011ae: d1f0 bne.n 8001192 } } } } /*----------------------------- MSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - 80010f8: 687b ldr r3, [r7, #4] - 80010fa: 681b ldr r3, [r3, #0] - 80010fc: f003 0310 and.w r3, r3, #16 - 8001100: 2b00 cmp r3, #0 - 8001102: f000 80b8 beq.w 8001276 + 80011b0: 687b ldr r3, [r7, #4] + 80011b2: 681b ldr r3, [r3, #0] + 80011b4: f003 0310 and.w r3, r3, #16 + 80011b8: 2b00 cmp r3, #0 + 80011ba: f000 80b8 beq.w 800132e { /* When the MSI is used as system clock it will not be disabled */ if(sysclk_source == RCC_CFGR_SWS_MSI) - 8001106: 69bb ldr r3, [r7, #24] - 8001108: 2b00 cmp r3, #0 - 800110a: d170 bne.n 80011ee + 80011be: 69bb ldr r3, [r7, #24] + 80011c0: 2b00 cmp r3, #0 + 80011c2: d170 bne.n 80012a6 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) - 800110c: 4b18 ldr r3, [pc, #96] @ (8001170 ) - 800110e: 681b ldr r3, [r3, #0] - 8001110: f403 7300 and.w r3, r3, #512 @ 0x200 - 8001114: 2b00 cmp r3, #0 - 8001116: d005 beq.n 8001124 - 8001118: 687b ldr r3, [r7, #4] - 800111a: 699b ldr r3, [r3, #24] - 800111c: 2b00 cmp r3, #0 - 800111e: d101 bne.n 8001124 + 80011c4: 4b18 ldr r3, [pc, #96] @ (8001228 ) + 80011c6: 681b ldr r3, [r3, #0] + 80011c8: f403 7300 and.w r3, r3, #512 @ 0x200 + 80011cc: 2b00 cmp r3, #0 + 80011ce: d005 beq.n 80011dc + 80011d0: 687b ldr r3, [r7, #4] + 80011d2: 699b ldr r3, [r3, #24] + 80011d4: 2b00 cmp r3, #0 + 80011d6: d101 bne.n 80011dc { return HAL_ERROR; - 8001120: 2301 movs r3, #1 - 8001122: e21a b.n 800155a + 80011d8: 2301 movs r3, #1 + 80011da: e21a b.n 8001612 assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - 8001124: 687b ldr r3, [r7, #4] - 8001126: 6a1a ldr r2, [r3, #32] - 8001128: 4b11 ldr r3, [pc, #68] @ (8001170 ) - 800112a: 685b ldr r3, [r3, #4] - 800112c: f403 4360 and.w r3, r3, #57344 @ 0xe000 - 8001130: 429a cmp r2, r3 - 8001132: d921 bls.n 8001178 + 80011dc: 687b ldr r3, [r7, #4] + 80011de: 6a1a ldr r2, [r3, #32] + 80011e0: 4b11 ldr r3, [pc, #68] @ (8001228 ) + 80011e2: 685b ldr r3, [r3, #4] + 80011e4: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 80011e8: 429a cmp r2, r3 + 80011ea: d921 bls.n 8001230 { /* First increase number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 8001134: 687b ldr r3, [r7, #4] - 8001136: 6a1b ldr r3, [r3, #32] - 8001138: 4618 mov r0, r3 - 800113a: f000 fc09 bl 8001950 - 800113e: 4603 mov r3, r0 - 8001140: 2b00 cmp r3, #0 - 8001142: d001 beq.n 8001148 + 80011ec: 687b ldr r3, [r7, #4] + 80011ee: 6a1b ldr r3, [r3, #32] + 80011f0: 4618 mov r0, r3 + 80011f2: f000 fc09 bl 8001a08 + 80011f6: 4603 mov r3, r0 + 80011f8: 2b00 cmp r3, #0 + 80011fa: d001 beq.n 8001200 { return HAL_ERROR; - 8001144: 2301 movs r3, #1 - 8001146: e208 b.n 800155a + 80011fc: 2301 movs r3, #1 + 80011fe: e208 b.n 8001612 } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8001148: 4b09 ldr r3, [pc, #36] @ (8001170 ) - 800114a: 685b ldr r3, [r3, #4] - 800114c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 8001150: 687b ldr r3, [r7, #4] - 8001152: 6a1b ldr r3, [r3, #32] - 8001154: 4906 ldr r1, [pc, #24] @ (8001170 ) - 8001156: 4313 orrs r3, r2 - 8001158: 604b str r3, [r1, #4] + 8001200: 4b09 ldr r3, [pc, #36] @ (8001228 ) + 8001202: 685b ldr r3, [r3, #4] + 8001204: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001208: 687b ldr r3, [r7, #4] + 800120a: 6a1b ldr r3, [r3, #32] + 800120c: 4906 ldr r1, [pc, #24] @ (8001228 ) + 800120e: 4313 orrs r3, r2 + 8001210: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 800115a: 4b05 ldr r3, [pc, #20] @ (8001170 ) - 800115c: 685b ldr r3, [r3, #4] - 800115e: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 - 8001162: 687b ldr r3, [r7, #4] - 8001164: 69db ldr r3, [r3, #28] - 8001166: 061b lsls r3, r3, #24 - 8001168: 4901 ldr r1, [pc, #4] @ (8001170 ) - 800116a: 4313 orrs r3, r2 - 800116c: 604b str r3, [r1, #4] - 800116e: e020 b.n 80011b2 - 8001170: 40023800 .word 0x40023800 - 8001174: 42470000 .word 0x42470000 + 8001212: 4b05 ldr r3, [pc, #20] @ (8001228 ) + 8001214: 685b ldr r3, [r3, #4] + 8001216: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 800121a: 687b ldr r3, [r7, #4] + 800121c: 69db ldr r3, [r3, #28] + 800121e: 061b lsls r3, r3, #24 + 8001220: 4901 ldr r1, [pc, #4] @ (8001228 ) + 8001222: 4313 orrs r3, r2 + 8001224: 604b str r3, [r1, #4] + 8001226: e020 b.n 800126a + 8001228: 40023800 .word 0x40023800 + 800122c: 42470000 .word 0x42470000 } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8001178: 4b99 ldr r3, [pc, #612] @ (80013e0 ) - 800117a: 685b ldr r3, [r3, #4] - 800117c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 8001180: 687b ldr r3, [r7, #4] - 8001182: 6a1b ldr r3, [r3, #32] - 8001184: 4996 ldr r1, [pc, #600] @ (80013e0 ) - 8001186: 4313 orrs r3, r2 - 8001188: 604b str r3, [r1, #4] + 8001230: 4b99 ldr r3, [pc, #612] @ (8001498 ) + 8001232: 685b ldr r3, [r3, #4] + 8001234: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8001238: 687b ldr r3, [r7, #4] + 800123a: 6a1b ldr r3, [r3, #32] + 800123c: 4996 ldr r1, [pc, #600] @ (8001498 ) + 800123e: 4313 orrs r3, r2 + 8001240: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 800118a: 4b95 ldr r3, [pc, #596] @ (80013e0 ) - 800118c: 685b ldr r3, [r3, #4] - 800118e: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 - 8001192: 687b ldr r3, [r7, #4] - 8001194: 69db ldr r3, [r3, #28] - 8001196: 061b lsls r3, r3, #24 - 8001198: 4991 ldr r1, [pc, #580] @ (80013e0 ) - 800119a: 4313 orrs r3, r2 - 800119c: 604b str r3, [r1, #4] + 8001242: 4b95 ldr r3, [pc, #596] @ (8001498 ) + 8001244: 685b ldr r3, [r3, #4] + 8001246: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 800124a: 687b ldr r3, [r7, #4] + 800124c: 69db ldr r3, [r3, #28] + 800124e: 061b lsls r3, r3, #24 + 8001250: 4991 ldr r1, [pc, #580] @ (8001498 ) + 8001252: 4313 orrs r3, r2 + 8001254: 604b str r3, [r1, #4] /* Decrease number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 800119e: 687b ldr r3, [r7, #4] - 80011a0: 6a1b ldr r3, [r3, #32] - 80011a2: 4618 mov r0, r3 - 80011a4: f000 fbd4 bl 8001950 - 80011a8: 4603 mov r3, r0 - 80011aa: 2b00 cmp r3, #0 - 80011ac: d001 beq.n 80011b2 + 8001256: 687b ldr r3, [r7, #4] + 8001258: 6a1b ldr r3, [r3, #32] + 800125a: 4618 mov r0, r3 + 800125c: f000 fbd4 bl 8001a08 + 8001260: 4603 mov r3, r0 + 8001262: 2b00 cmp r3, #0 + 8001264: d001 beq.n 800126a { return HAL_ERROR; - 80011ae: 2301 movs r3, #1 - 80011b0: e1d3 b.n 800155a + 8001266: 2301 movs r3, #1 + 8001268: e1d3 b.n 8001612 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) - 80011b2: 687b ldr r3, [r7, #4] - 80011b4: 6a1b ldr r3, [r3, #32] - 80011b6: 0b5b lsrs r3, r3, #13 - 80011b8: 3301 adds r3, #1 - 80011ba: f44f 4200 mov.w r2, #32768 @ 0x8000 - 80011be: fa02 f303 lsl.w r3, r2, r3 + 800126a: 687b ldr r3, [r7, #4] + 800126c: 6a1b ldr r3, [r3, #32] + 800126e: 0b5b lsrs r3, r3, #13 + 8001270: 3301 adds r3, #1 + 8001272: f44f 4200 mov.w r2, #32768 @ 0x8000 + 8001276: fa02 f303 lsl.w r3, r2, r3 >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; - 80011c2: 4a87 ldr r2, [pc, #540] @ (80013e0 ) - 80011c4: 6892 ldr r2, [r2, #8] - 80011c6: 0912 lsrs r2, r2, #4 - 80011c8: f002 020f and.w r2, r2, #15 - 80011cc: 4985 ldr r1, [pc, #532] @ (80013e4 ) - 80011ce: 5c8a ldrb r2, [r1, r2] - 80011d0: 40d3 lsrs r3, r2 + 800127a: 4a87 ldr r2, [pc, #540] @ (8001498 ) + 800127c: 6892 ldr r2, [r2, #8] + 800127e: 0912 lsrs r2, r2, #4 + 8001280: f002 020f and.w r2, r2, #15 + 8001284: 4985 ldr r1, [pc, #532] @ (800149c ) + 8001286: 5c8a ldrb r2, [r1, r2] + 8001288: 40d3 lsrs r3, r2 SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) - 80011d2: 4a85 ldr r2, [pc, #532] @ (80013e8 ) - 80011d4: 6013 str r3, [r2, #0] + 800128a: 4a85 ldr r2, [pc, #532] @ (80014a0 ) + 800128c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); - 80011d6: 4b85 ldr r3, [pc, #532] @ (80013ec ) - 80011d8: 681b ldr r3, [r3, #0] - 80011da: 4618 mov r0, r3 - 80011dc: f7ff fbb4 bl 8000948 - 80011e0: 4603 mov r3, r0 - 80011e2: 73fb strb r3, [r7, #15] + 800128e: 4b85 ldr r3, [pc, #532] @ (80014a4 ) + 8001290: 681b ldr r3, [r3, #0] + 8001292: 4618 mov r0, r3 + 8001294: f7ff fb92 bl 80009bc + 8001298: 4603 mov r3, r0 + 800129a: 73fb strb r3, [r7, #15] if(status != HAL_OK) - 80011e4: 7bfb ldrb r3, [r7, #15] - 80011e6: 2b00 cmp r3, #0 - 80011e8: d045 beq.n 8001276 + 800129c: 7bfb ldrb r3, [r7, #15] + 800129e: 2b00 cmp r3, #0 + 80012a0: d045 beq.n 800132e { return status; - 80011ea: 7bfb ldrb r3, [r7, #15] - 80011ec: e1b5 b.n 800155a + 80012a2: 7bfb ldrb r3, [r7, #15] + 80012a4: e1b5 b.n 8001612 { /* Check MSI State */ assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); /* Check the MSI State */ if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) - 80011ee: 687b ldr r3, [r7, #4] - 80011f0: 699b ldr r3, [r3, #24] - 80011f2: 2b00 cmp r3, #0 - 80011f4: d029 beq.n 800124a + 80012a6: 687b ldr r3, [r7, #4] + 80012a8: 699b ldr r3, [r3, #24] + 80012aa: 2b00 cmp r3, #0 + 80012ac: d029 beq.n 8001302 { /* Enable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); - 80011f6: 4b7e ldr r3, [pc, #504] @ (80013f0 ) - 80011f8: 2201 movs r2, #1 - 80011fa: 601a str r2, [r3, #0] + 80012ae: 4b7e ldr r3, [pc, #504] @ (80014a8 ) + 80012b0: 2201 movs r2, #1 + 80012b2: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80011fc: f7ff fbf0 bl 80009e0 - 8001200: 6138 str r0, [r7, #16] + 80012b4: f7ff fbce bl 8000a54 + 80012b8: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - 8001202: e008 b.n 8001216 + 80012ba: e008 b.n 80012ce { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 8001204: f7ff fbec bl 80009e0 - 8001208: 4602 mov r2, r0 - 800120a: 693b ldr r3, [r7, #16] - 800120c: 1ad3 subs r3, r2, r3 - 800120e: 2b02 cmp r3, #2 - 8001210: d901 bls.n 8001216 + 80012bc: f7ff fbca bl 8000a54 + 80012c0: 4602 mov r2, r0 + 80012c2: 693b ldr r3, [r7, #16] + 80012c4: 1ad3 subs r3, r2, r3 + 80012c6: 2b02 cmp r3, #2 + 80012c8: d901 bls.n 80012ce { return HAL_TIMEOUT; - 8001212: 2303 movs r3, #3 - 8001214: e1a1 b.n 800155a + 80012ca: 2303 movs r3, #3 + 80012cc: e1a1 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - 8001216: 4b72 ldr r3, [pc, #456] @ (80013e0 ) - 8001218: 681b ldr r3, [r3, #0] - 800121a: f403 7300 and.w r3, r3, #512 @ 0x200 - 800121e: 2b00 cmp r3, #0 - 8001220: d0f0 beq.n 8001204 + 80012ce: 4b72 ldr r3, [pc, #456] @ (8001498 ) + 80012d0: 681b ldr r3, [r3, #0] + 80012d2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80012d6: 2b00 cmp r3, #0 + 80012d8: d0f0 beq.n 80012bc /* Check MSICalibrationValue and MSIClockRange input parameters */ assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8001222: 4b6f ldr r3, [pc, #444] @ (80013e0 ) - 8001224: 685b ldr r3, [r3, #4] - 8001226: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 800122a: 687b ldr r3, [r7, #4] - 800122c: 6a1b ldr r3, [r3, #32] - 800122e: 496c ldr r1, [pc, #432] @ (80013e0 ) - 8001230: 4313 orrs r3, r2 - 8001232: 604b str r3, [r1, #4] + 80012da: 4b6f ldr r3, [pc, #444] @ (8001498 ) + 80012dc: 685b ldr r3, [r3, #4] + 80012de: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 80012e2: 687b ldr r3, [r7, #4] + 80012e4: 6a1b ldr r3, [r3, #32] + 80012e6: 496c ldr r1, [pc, #432] @ (8001498 ) + 80012e8: 4313 orrs r3, r2 + 80012ea: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 8001234: 4b6a ldr r3, [pc, #424] @ (80013e0 ) - 8001236: 685b ldr r3, [r3, #4] - 8001238: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 - 800123c: 687b ldr r3, [r7, #4] - 800123e: 69db ldr r3, [r3, #28] - 8001240: 061b lsls r3, r3, #24 - 8001242: 4967 ldr r1, [pc, #412] @ (80013e0 ) - 8001244: 4313 orrs r3, r2 - 8001246: 604b str r3, [r1, #4] - 8001248: e015 b.n 8001276 + 80012ec: 4b6a ldr r3, [pc, #424] @ (8001498 ) + 80012ee: 685b ldr r3, [r3, #4] + 80012f0: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 + 80012f4: 687b ldr r3, [r7, #4] + 80012f6: 69db ldr r3, [r3, #28] + 80012f8: 061b lsls r3, r3, #24 + 80012fa: 4967 ldr r1, [pc, #412] @ (8001498 ) + 80012fc: 4313 orrs r3, r2 + 80012fe: 604b str r3, [r1, #4] + 8001300: e015 b.n 800132e } else { /* Disable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); - 800124a: 4b69 ldr r3, [pc, #420] @ (80013f0 ) - 800124c: 2200 movs r2, #0 - 800124e: 601a str r2, [r3, #0] + 8001302: 4b69 ldr r3, [pc, #420] @ (80014a8 ) + 8001304: 2200 movs r2, #0 + 8001306: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001250: f7ff fbc6 bl 80009e0 - 8001254: 6138 str r0, [r7, #16] + 8001308: f7ff fba4 bl 8000a54 + 800130c: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) - 8001256: e008 b.n 800126a + 800130e: e008 b.n 8001322 { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 8001258: f7ff fbc2 bl 80009e0 - 800125c: 4602 mov r2, r0 - 800125e: 693b ldr r3, [r7, #16] - 8001260: 1ad3 subs r3, r2, r3 - 8001262: 2b02 cmp r3, #2 - 8001264: d901 bls.n 800126a + 8001310: f7ff fba0 bl 8000a54 + 8001314: 4602 mov r2, r0 + 8001316: 693b ldr r3, [r7, #16] + 8001318: 1ad3 subs r3, r2, r3 + 800131a: 2b02 cmp r3, #2 + 800131c: d901 bls.n 8001322 { return HAL_TIMEOUT; - 8001266: 2303 movs r3, #3 - 8001268: e177 b.n 800155a + 800131e: 2303 movs r3, #3 + 8001320: e177 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) - 800126a: 4b5d ldr r3, [pc, #372] @ (80013e0 ) - 800126c: 681b ldr r3, [r3, #0] - 800126e: f403 7300 and.w r3, r3, #512 @ 0x200 - 8001272: 2b00 cmp r3, #0 - 8001274: d1f0 bne.n 8001258 + 8001322: 4b5d ldr r3, [pc, #372] @ (8001498 ) + 8001324: 681b ldr r3, [r3, #0] + 8001326: f403 7300 and.w r3, r3, #512 @ 0x200 + 800132a: 2b00 cmp r3, #0 + 800132c: d1f0 bne.n 8001310 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8001276: 687b ldr r3, [r7, #4] - 8001278: 681b ldr r3, [r3, #0] - 800127a: f003 0308 and.w r3, r3, #8 - 800127e: 2b00 cmp r3, #0 - 8001280: d030 beq.n 80012e4 + 800132e: 687b ldr r3, [r7, #4] + 8001330: 681b ldr r3, [r3, #0] + 8001332: f003 0308 and.w r3, r3, #8 + 8001336: 2b00 cmp r3, #0 + 8001338: d030 beq.n 800139c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8001282: 687b ldr r3, [r7, #4] - 8001284: 695b ldr r3, [r3, #20] - 8001286: 2b00 cmp r3, #0 - 8001288: d016 beq.n 80012b8 + 800133a: 687b ldr r3, [r7, #4] + 800133c: 695b ldr r3, [r3, #20] + 800133e: 2b00 cmp r3, #0 + 8001340: d016 beq.n 8001370 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 800128a: 4b5a ldr r3, [pc, #360] @ (80013f4 ) - 800128c: 2201 movs r2, #1 - 800128e: 601a str r2, [r3, #0] + 8001342: 4b5a ldr r3, [pc, #360] @ (80014ac ) + 8001344: 2201 movs r2, #1 + 8001346: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001290: f7ff fba6 bl 80009e0 - 8001294: 6138 str r0, [r7, #16] + 8001348: f7ff fb84 bl 8000a54 + 800134c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) - 8001296: e008 b.n 80012aa + 800134e: e008 b.n 8001362 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8001298: f7ff fba2 bl 80009e0 - 800129c: 4602 mov r2, r0 - 800129e: 693b ldr r3, [r7, #16] - 80012a0: 1ad3 subs r3, r2, r3 - 80012a2: 2b02 cmp r3, #2 - 80012a4: d901 bls.n 80012aa + 8001350: f7ff fb80 bl 8000a54 + 8001354: 4602 mov r2, r0 + 8001356: 693b ldr r3, [r7, #16] + 8001358: 1ad3 subs r3, r2, r3 + 800135a: 2b02 cmp r3, #2 + 800135c: d901 bls.n 8001362 { return HAL_TIMEOUT; - 80012a6: 2303 movs r3, #3 - 80012a8: e157 b.n 800155a + 800135e: 2303 movs r3, #3 + 8001360: e157 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) - 80012aa: 4b4d ldr r3, [pc, #308] @ (80013e0 ) - 80012ac: 6b5b ldr r3, [r3, #52] @ 0x34 - 80012ae: f003 0302 and.w r3, r3, #2 - 80012b2: 2b00 cmp r3, #0 - 80012b4: d0f0 beq.n 8001298 - 80012b6: e015 b.n 80012e4 + 8001362: 4b4d ldr r3, [pc, #308] @ (8001498 ) + 8001364: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001366: f003 0302 and.w r3, r3, #2 + 800136a: 2b00 cmp r3, #0 + 800136c: d0f0 beq.n 8001350 + 800136e: e015 b.n 800139c } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 80012b8: 4b4e ldr r3, [pc, #312] @ (80013f4 ) - 80012ba: 2200 movs r2, #0 - 80012bc: 601a str r2, [r3, #0] + 8001370: 4b4e ldr r3, [pc, #312] @ (80014ac ) + 8001372: 2200 movs r2, #0 + 8001374: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80012be: f7ff fb8f bl 80009e0 - 80012c2: 6138 str r0, [r7, #16] + 8001376: f7ff fb6d bl 8000a54 + 800137a: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) - 80012c4: e008 b.n 80012d8 + 800137c: e008 b.n 8001390 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 80012c6: f7ff fb8b bl 80009e0 - 80012ca: 4602 mov r2, r0 - 80012cc: 693b ldr r3, [r7, #16] - 80012ce: 1ad3 subs r3, r2, r3 - 80012d0: 2b02 cmp r3, #2 - 80012d2: d901 bls.n 80012d8 + 800137e: f7ff fb69 bl 8000a54 + 8001382: 4602 mov r2, r0 + 8001384: 693b ldr r3, [r7, #16] + 8001386: 1ad3 subs r3, r2, r3 + 8001388: 2b02 cmp r3, #2 + 800138a: d901 bls.n 8001390 { return HAL_TIMEOUT; - 80012d4: 2303 movs r3, #3 - 80012d6: e140 b.n 800155a + 800138c: 2303 movs r3, #3 + 800138e: e140 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) - 80012d8: 4b41 ldr r3, [pc, #260] @ (80013e0 ) - 80012da: 6b5b ldr r3, [r3, #52] @ 0x34 - 80012dc: f003 0302 and.w r3, r3, #2 - 80012e0: 2b00 cmp r3, #0 - 80012e2: d1f0 bne.n 80012c6 + 8001390: 4b41 ldr r3, [pc, #260] @ (8001498 ) + 8001392: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001394: f003 0302 and.w r3, r3, #2 + 8001398: 2b00 cmp r3, #0 + 800139a: d1f0 bne.n 800137e } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 80012e4: 687b ldr r3, [r7, #4] - 80012e6: 681b ldr r3, [r3, #0] - 80012e8: f003 0304 and.w r3, r3, #4 - 80012ec: 2b00 cmp r3, #0 - 80012ee: f000 80b5 beq.w 800145c + 800139c: 687b ldr r3, [r7, #4] + 800139e: 681b ldr r3, [r3, #0] + 80013a0: f003 0304 and.w r3, r3, #4 + 80013a4: 2b00 cmp r3, #0 + 80013a6: f000 80b5 beq.w 8001514 { FlagStatus pwrclkchanged = RESET; - 80012f2: 2300 movs r3, #0 - 80012f4: 77fb strb r3, [r7, #31] + 80013aa: 2300 movs r3, #0 + 80013ac: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 80012f6: 4b3a ldr r3, [pc, #232] @ (80013e0 ) - 80012f8: 6a5b ldr r3, [r3, #36] @ 0x24 - 80012fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80012fe: 2b00 cmp r3, #0 - 8001300: d10d bne.n 800131e + 80013ae: 4b3a ldr r3, [pc, #232] @ (8001498 ) + 80013b0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80013b2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80013b6: 2b00 cmp r3, #0 + 80013b8: d10d bne.n 80013d6 { __HAL_RCC_PWR_CLK_ENABLE(); - 8001302: 4b37 ldr r3, [pc, #220] @ (80013e0 ) - 8001304: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001306: 4a36 ldr r2, [pc, #216] @ (80013e0 ) - 8001308: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 800130c: 6253 str r3, [r2, #36] @ 0x24 - 800130e: 4b34 ldr r3, [pc, #208] @ (80013e0 ) - 8001310: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001312: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001316: 60bb str r3, [r7, #8] - 8001318: 68bb ldr r3, [r7, #8] + 80013ba: 4b37 ldr r3, [pc, #220] @ (8001498 ) + 80013bc: 6a5b ldr r3, [r3, #36] @ 0x24 + 80013be: 4a36 ldr r2, [pc, #216] @ (8001498 ) + 80013c0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 80013c4: 6253 str r3, [r2, #36] @ 0x24 + 80013c6: 4b34 ldr r3, [pc, #208] @ (8001498 ) + 80013c8: 6a5b ldr r3, [r3, #36] @ 0x24 + 80013ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80013ce: 60bb str r3, [r7, #8] + 80013d0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 800131a: 2301 movs r3, #1 - 800131c: 77fb strb r3, [r7, #31] + 80013d2: 2301 movs r3, #1 + 80013d4: 77fb strb r3, [r7, #31] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 800131e: 4b36 ldr r3, [pc, #216] @ (80013f8 ) - 8001320: 681b ldr r3, [r3, #0] - 8001322: f403 7380 and.w r3, r3, #256 @ 0x100 - 8001326: 2b00 cmp r3, #0 - 8001328: d118 bne.n 800135c + 80013d6: 4b36 ldr r3, [pc, #216] @ (80014b0 ) + 80013d8: 681b ldr r3, [r3, #0] + 80013da: f403 7380 and.w r3, r3, #256 @ 0x100 + 80013de: 2b00 cmp r3, #0 + 80013e0: d118 bne.n 8001414 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 800132a: 4b33 ldr r3, [pc, #204] @ (80013f8 ) - 800132c: 681b ldr r3, [r3, #0] - 800132e: 4a32 ldr r2, [pc, #200] @ (80013f8 ) - 8001330: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8001334: 6013 str r3, [r2, #0] + 80013e2: 4b33 ldr r3, [pc, #204] @ (80014b0 ) + 80013e4: 681b ldr r3, [r3, #0] + 80013e6: 4a32 ldr r2, [pc, #200] @ (80014b0 ) + 80013e8: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80013ec: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 8001336: f7ff fb53 bl 80009e0 - 800133a: 6138 str r0, [r7, #16] + 80013ee: f7ff fb31 bl 8000a54 + 80013f2: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 800133c: e008 b.n 8001350 + 80013f4: e008 b.n 8001408 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 800133e: f7ff fb4f bl 80009e0 - 8001342: 4602 mov r2, r0 - 8001344: 693b ldr r3, [r7, #16] - 8001346: 1ad3 subs r3, r2, r3 - 8001348: 2b64 cmp r3, #100 @ 0x64 - 800134a: d901 bls.n 8001350 + 80013f6: f7ff fb2d bl 8000a54 + 80013fa: 4602 mov r2, r0 + 80013fc: 693b ldr r3, [r7, #16] + 80013fe: 1ad3 subs r3, r2, r3 + 8001400: 2b64 cmp r3, #100 @ 0x64 + 8001402: d901 bls.n 8001408 { return HAL_TIMEOUT; - 800134c: 2303 movs r3, #3 - 800134e: e104 b.n 800155a + 8001404: 2303 movs r3, #3 + 8001406: e104 b.n 8001612 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001350: 4b29 ldr r3, [pc, #164] @ (80013f8 ) - 8001352: 681b ldr r3, [r3, #0] - 8001354: f403 7380 and.w r3, r3, #256 @ 0x100 - 8001358: 2b00 cmp r3, #0 - 800135a: d0f0 beq.n 800133e + 8001408: 4b29 ldr r3, [pc, #164] @ (80014b0 ) + 800140a: 681b ldr r3, [r3, #0] + 800140c: f403 7380 and.w r3, r3, #256 @ 0x100 + 8001410: 2b00 cmp r3, #0 + 8001412: d0f0 beq.n 80013f6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 800135c: 687b ldr r3, [r7, #4] - 800135e: 689b ldr r3, [r3, #8] - 8001360: 2b01 cmp r3, #1 - 8001362: d106 bne.n 8001372 - 8001364: 4b1e ldr r3, [pc, #120] @ (80013e0 ) - 8001366: 6b5b ldr r3, [r3, #52] @ 0x34 - 8001368: 4a1d ldr r2, [pc, #116] @ (80013e0 ) - 800136a: f443 7380 orr.w r3, r3, #256 @ 0x100 - 800136e: 6353 str r3, [r2, #52] @ 0x34 - 8001370: e02d b.n 80013ce - 8001372: 687b ldr r3, [r7, #4] - 8001374: 689b ldr r3, [r3, #8] - 8001376: 2b00 cmp r3, #0 - 8001378: d10c bne.n 8001394 - 800137a: 4b19 ldr r3, [pc, #100] @ (80013e0 ) - 800137c: 6b5b ldr r3, [r3, #52] @ 0x34 - 800137e: 4a18 ldr r2, [pc, #96] @ (80013e0 ) - 8001380: f423 7380 bic.w r3, r3, #256 @ 0x100 - 8001384: 6353 str r3, [r2, #52] @ 0x34 - 8001386: 4b16 ldr r3, [pc, #88] @ (80013e0 ) - 8001388: 6b5b ldr r3, [r3, #52] @ 0x34 - 800138a: 4a15 ldr r2, [pc, #84] @ (80013e0 ) - 800138c: f423 6380 bic.w r3, r3, #1024 @ 0x400 - 8001390: 6353 str r3, [r2, #52] @ 0x34 - 8001392: e01c b.n 80013ce - 8001394: 687b ldr r3, [r7, #4] - 8001396: 689b ldr r3, [r3, #8] - 8001398: 2b05 cmp r3, #5 - 800139a: d10c bne.n 80013b6 - 800139c: 4b10 ldr r3, [pc, #64] @ (80013e0 ) - 800139e: 6b5b ldr r3, [r3, #52] @ 0x34 - 80013a0: 4a0f ldr r2, [pc, #60] @ (80013e0 ) - 80013a2: f443 6380 orr.w r3, r3, #1024 @ 0x400 - 80013a6: 6353 str r3, [r2, #52] @ 0x34 - 80013a8: 4b0d ldr r3, [pc, #52] @ (80013e0 ) - 80013aa: 6b5b ldr r3, [r3, #52] @ 0x34 - 80013ac: 4a0c ldr r2, [pc, #48] @ (80013e0 ) - 80013ae: f443 7380 orr.w r3, r3, #256 @ 0x100 - 80013b2: 6353 str r3, [r2, #52] @ 0x34 - 80013b4: e00b b.n 80013ce - 80013b6: 4b0a ldr r3, [pc, #40] @ (80013e0 ) - 80013b8: 6b5b ldr r3, [r3, #52] @ 0x34 - 80013ba: 4a09 ldr r2, [pc, #36] @ (80013e0 ) - 80013bc: f423 7380 bic.w r3, r3, #256 @ 0x100 - 80013c0: 6353 str r3, [r2, #52] @ 0x34 - 80013c2: 4b07 ldr r3, [pc, #28] @ (80013e0 ) - 80013c4: 6b5b ldr r3, [r3, #52] @ 0x34 - 80013c6: 4a06 ldr r2, [pc, #24] @ (80013e0 ) - 80013c8: f423 6380 bic.w r3, r3, #1024 @ 0x400 - 80013cc: 6353 str r3, [r2, #52] @ 0x34 + 8001414: 687b ldr r3, [r7, #4] + 8001416: 689b ldr r3, [r3, #8] + 8001418: 2b01 cmp r3, #1 + 800141a: d106 bne.n 800142a + 800141c: 4b1e ldr r3, [pc, #120] @ (8001498 ) + 800141e: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001420: 4a1d ldr r2, [pc, #116] @ (8001498 ) + 8001422: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8001426: 6353 str r3, [r2, #52] @ 0x34 + 8001428: e02d b.n 8001486 + 800142a: 687b ldr r3, [r7, #4] + 800142c: 689b ldr r3, [r3, #8] + 800142e: 2b00 cmp r3, #0 + 8001430: d10c bne.n 800144c + 8001432: 4b19 ldr r3, [pc, #100] @ (8001498 ) + 8001434: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001436: 4a18 ldr r2, [pc, #96] @ (8001498 ) + 8001438: f423 7380 bic.w r3, r3, #256 @ 0x100 + 800143c: 6353 str r3, [r2, #52] @ 0x34 + 800143e: 4b16 ldr r3, [pc, #88] @ (8001498 ) + 8001440: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001442: 4a15 ldr r2, [pc, #84] @ (8001498 ) + 8001444: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001448: 6353 str r3, [r2, #52] @ 0x34 + 800144a: e01c b.n 8001486 + 800144c: 687b ldr r3, [r7, #4] + 800144e: 689b ldr r3, [r3, #8] + 8001450: 2b05 cmp r3, #5 + 8001452: d10c bne.n 800146e + 8001454: 4b10 ldr r3, [pc, #64] @ (8001498 ) + 8001456: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001458: 4a0f ldr r2, [pc, #60] @ (8001498 ) + 800145a: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 800145e: 6353 str r3, [r2, #52] @ 0x34 + 8001460: 4b0d ldr r3, [pc, #52] @ (8001498 ) + 8001462: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001464: 4a0c ldr r2, [pc, #48] @ (8001498 ) + 8001466: f443 7380 orr.w r3, r3, #256 @ 0x100 + 800146a: 6353 str r3, [r2, #52] @ 0x34 + 800146c: e00b b.n 8001486 + 800146e: 4b0a ldr r3, [pc, #40] @ (8001498 ) + 8001470: 6b5b ldr r3, [r3, #52] @ 0x34 + 8001472: 4a09 ldr r2, [pc, #36] @ (8001498 ) + 8001474: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8001478: 6353 str r3, [r2, #52] @ 0x34 + 800147a: 4b07 ldr r3, [pc, #28] @ (8001498 ) + 800147c: 6b5b ldr r3, [r3, #52] @ 0x34 + 800147e: 4a06 ldr r2, [pc, #24] @ (8001498 ) + 8001480: f423 6380 bic.w r3, r3, #1024 @ 0x400 + 8001484: 6353 str r3, [r2, #52] @ 0x34 /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 80013ce: 687b ldr r3, [r7, #4] - 80013d0: 689b ldr r3, [r3, #8] - 80013d2: 2b00 cmp r3, #0 - 80013d4: d024 beq.n 8001420 + 8001486: 687b ldr r3, [r7, #4] + 8001488: 689b ldr r3, [r3, #8] + 800148a: 2b00 cmp r3, #0 + 800148c: d024 beq.n 80014d8 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80013d6: f7ff fb03 bl 80009e0 - 80013da: 6138 str r0, [r7, #16] + 800148e: f7ff fae1 bl 8000a54 + 8001492: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - 80013dc: e019 b.n 8001412 - 80013de: bf00 nop - 80013e0: 40023800 .word 0x40023800 - 80013e4: 08001fe0 .word 0x08001fe0 - 80013e8: 20000000 .word 0x20000000 - 80013ec: 20000004 .word 0x20000004 - 80013f0: 42470020 .word 0x42470020 - 80013f4: 42470680 .word 0x42470680 - 80013f8: 40007000 .word 0x40007000 + 8001494: e019 b.n 80014ca + 8001496: bf00 nop + 8001498: 40023800 .word 0x40023800 + 800149c: 08002098 .word 0x08002098 + 80014a0: 20000000 .word 0x20000000 + 80014a4: 20000004 .word 0x20000004 + 80014a8: 42470020 .word 0x42470020 + 80014ac: 42470680 .word 0x42470680 + 80014b0: 40007000 .word 0x40007000 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 80013fc: f7ff faf0 bl 80009e0 - 8001400: 4602 mov r2, r0 - 8001402: 693b ldr r3, [r7, #16] - 8001404: 1ad3 subs r3, r2, r3 - 8001406: f241 3288 movw r2, #5000 @ 0x1388 - 800140a: 4293 cmp r3, r2 - 800140c: d901 bls.n 8001412 + 80014b4: f7ff face bl 8000a54 + 80014b8: 4602 mov r2, r0 + 80014ba: 693b ldr r3, [r7, #16] + 80014bc: 1ad3 subs r3, r2, r3 + 80014be: f241 3288 movw r2, #5000 @ 0x1388 + 80014c2: 4293 cmp r3, r2 + 80014c4: d901 bls.n 80014ca { return HAL_TIMEOUT; - 800140e: 2303 movs r3, #3 - 8001410: e0a3 b.n 800155a + 80014c6: 2303 movs r3, #3 + 80014c8: e0a3 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - 8001412: 4b54 ldr r3, [pc, #336] @ (8001564 ) - 8001414: 6b5b ldr r3, [r3, #52] @ 0x34 - 8001416: f403 7300 and.w r3, r3, #512 @ 0x200 - 800141a: 2b00 cmp r3, #0 - 800141c: d0ee beq.n 80013fc - 800141e: e014 b.n 800144a + 80014ca: 4b54 ldr r3, [pc, #336] @ (800161c ) + 80014cc: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014ce: f403 7300 and.w r3, r3, #512 @ 0x200 + 80014d2: 2b00 cmp r3, #0 + 80014d4: d0ee beq.n 80014b4 + 80014d6: e014 b.n 8001502 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001420: f7ff fade bl 80009e0 - 8001424: 6138 str r0, [r7, #16] + 80014d8: f7ff fabc bl 8000a54 + 80014dc: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) - 8001426: e00a b.n 800143e + 80014de: e00a b.n 80014f6 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 8001428: f7ff fada bl 80009e0 - 800142c: 4602 mov r2, r0 - 800142e: 693b ldr r3, [r7, #16] - 8001430: 1ad3 subs r3, r2, r3 - 8001432: f241 3288 movw r2, #5000 @ 0x1388 - 8001436: 4293 cmp r3, r2 - 8001438: d901 bls.n 800143e + 80014e0: f7ff fab8 bl 8000a54 + 80014e4: 4602 mov r2, r0 + 80014e6: 693b ldr r3, [r7, #16] + 80014e8: 1ad3 subs r3, r2, r3 + 80014ea: f241 3288 movw r2, #5000 @ 0x1388 + 80014ee: 4293 cmp r3, r2 + 80014f0: d901 bls.n 80014f6 { return HAL_TIMEOUT; - 800143a: 2303 movs r3, #3 - 800143c: e08d b.n 800155a + 80014f2: 2303 movs r3, #3 + 80014f4: e08d b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) - 800143e: 4b49 ldr r3, [pc, #292] @ (8001564 ) - 8001440: 6b5b ldr r3, [r3, #52] @ 0x34 - 8001442: f403 7300 and.w r3, r3, #512 @ 0x200 - 8001446: 2b00 cmp r3, #0 - 8001448: d1ee bne.n 8001428 + 80014f6: 4b49 ldr r3, [pc, #292] @ (800161c ) + 80014f8: 6b5b ldr r3, [r3, #52] @ 0x34 + 80014fa: f403 7300 and.w r3, r3, #512 @ 0x200 + 80014fe: 2b00 cmp r3, #0 + 8001500: d1ee bne.n 80014e0 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) - 800144a: 7ffb ldrb r3, [r7, #31] - 800144c: 2b01 cmp r3, #1 - 800144e: d105 bne.n 800145c + 8001502: 7ffb ldrb r3, [r7, #31] + 8001504: 2b01 cmp r3, #1 + 8001506: d105 bne.n 8001514 { __HAL_RCC_PWR_CLK_DISABLE(); - 8001450: 4b44 ldr r3, [pc, #272] @ (8001564 ) - 8001452: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001454: 4a43 ldr r2, [pc, #268] @ (8001564 ) - 8001456: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 800145a: 6253 str r3, [r2, #36] @ 0x24 + 8001508: 4b44 ldr r3, [pc, #272] @ (800161c ) + 800150a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800150c: 4a43 ldr r2, [pc, #268] @ (800161c ) + 800150e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001512: 6253 str r3, [r2, #36] @ 0x24 } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 800145c: 687b ldr r3, [r7, #4] - 800145e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001460: 2b00 cmp r3, #0 - 8001462: d079 beq.n 8001558 + 8001514: 687b ldr r3, [r7, #4] + 8001516: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001518: 2b00 cmp r3, #0 + 800151a: d079 beq.n 8001610 { /* Check if the PLL is used as system clock or not */ if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 8001464: 69bb ldr r3, [r7, #24] - 8001466: 2b0c cmp r3, #12 - 8001468: d056 beq.n 8001518 + 800151c: 69bb ldr r3, [r7, #24] + 800151e: 2b0c cmp r3, #12 + 8001520: d056 beq.n 80015d0 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 800146a: 687b ldr r3, [r7, #4] - 800146c: 6a5b ldr r3, [r3, #36] @ 0x24 - 800146e: 2b02 cmp r3, #2 - 8001470: d13b bne.n 80014ea + 8001522: 687b ldr r3, [r7, #4] + 8001524: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001526: 2b02 cmp r3, #2 + 8001528: d13b bne.n 80015a2 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8001472: 4b3d ldr r3, [pc, #244] @ (8001568 ) - 8001474: 2200 movs r2, #0 - 8001476: 601a str r2, [r3, #0] + 800152a: 4b3d ldr r3, [pc, #244] @ (8001620 ) + 800152c: 2200 movs r2, #0 + 800152e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001478: f7ff fab2 bl 80009e0 - 800147c: 6138 str r0, [r7, #16] + 8001530: f7ff fa90 bl 8000a54 + 8001534: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 800147e: e008 b.n 8001492 + 8001536: e008 b.n 800154a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 8001480: f7ff faae bl 80009e0 - 8001484: 4602 mov r2, r0 - 8001486: 693b ldr r3, [r7, #16] - 8001488: 1ad3 subs r3, r2, r3 - 800148a: 2b02 cmp r3, #2 - 800148c: d901 bls.n 8001492 + 8001538: f7ff fa8c bl 8000a54 + 800153c: 4602 mov r2, r0 + 800153e: 693b ldr r3, [r7, #16] + 8001540: 1ad3 subs r3, r2, r3 + 8001542: 2b02 cmp r3, #2 + 8001544: d901 bls.n 800154a { return HAL_TIMEOUT; - 800148e: 2303 movs r3, #3 - 8001490: e063 b.n 800155a + 8001546: 2303 movs r3, #3 + 8001548: e063 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 8001492: 4b34 ldr r3, [pc, #208] @ (8001564 ) - 8001494: 681b ldr r3, [r3, #0] - 8001496: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 800149a: 2b00 cmp r3, #0 - 800149c: d1f0 bne.n 8001480 + 800154a: 4b34 ldr r3, [pc, #208] @ (800161c ) + 800154c: 681b ldr r3, [r3, #0] + 800154e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8001552: 2b00 cmp r3, #0 + 8001554: d1f0 bne.n 8001538 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 800149e: 4b31 ldr r3, [pc, #196] @ (8001564 ) - 80014a0: 689b ldr r3, [r3, #8] - 80014a2: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 - 80014a6: 687b ldr r3, [r7, #4] - 80014a8: 6a99 ldr r1, [r3, #40] @ 0x28 - 80014aa: 687b ldr r3, [r7, #4] - 80014ac: 6adb ldr r3, [r3, #44] @ 0x2c - 80014ae: 4319 orrs r1, r3 - 80014b0: 687b ldr r3, [r7, #4] - 80014b2: 6b1b ldr r3, [r3, #48] @ 0x30 - 80014b4: 430b orrs r3, r1 - 80014b6: 492b ldr r1, [pc, #172] @ (8001564 ) - 80014b8: 4313 orrs r3, r2 - 80014ba: 608b str r3, [r1, #8] + 8001556: 4b31 ldr r3, [pc, #196] @ (800161c ) + 8001558: 689b ldr r3, [r3, #8] + 800155a: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 + 800155e: 687b ldr r3, [r7, #4] + 8001560: 6a99 ldr r1, [r3, #40] @ 0x28 + 8001562: 687b ldr r3, [r7, #4] + 8001564: 6adb ldr r3, [r3, #44] @ 0x2c + 8001566: 4319 orrs r1, r3 + 8001568: 687b ldr r3, [r7, #4] + 800156a: 6b1b ldr r3, [r3, #48] @ 0x30 + 800156c: 430b orrs r3, r1 + 800156e: 492b ldr r1, [pc, #172] @ (800161c ) + 8001570: 4313 orrs r3, r2 + 8001572: 608b str r3, [r1, #8] RCC_OscInitStruct->PLL.PLLMUL, RCC_OscInitStruct->PLL.PLLDIV); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 80014bc: 4b2a ldr r3, [pc, #168] @ (8001568 ) - 80014be: 2201 movs r2, #1 - 80014c0: 601a str r2, [r3, #0] + 8001574: 4b2a ldr r3, [pc, #168] @ (8001620 ) + 8001576: 2201 movs r2, #1 + 8001578: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80014c2: f7ff fa8d bl 80009e0 - 80014c6: 6138 str r0, [r7, #16] + 800157a: f7ff fa6b bl 8000a54 + 800157e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - 80014c8: e008 b.n 80014dc + 8001580: e008 b.n 8001594 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 80014ca: f7ff fa89 bl 80009e0 - 80014ce: 4602 mov r2, r0 - 80014d0: 693b ldr r3, [r7, #16] - 80014d2: 1ad3 subs r3, r2, r3 - 80014d4: 2b02 cmp r3, #2 - 80014d6: d901 bls.n 80014dc + 8001582: f7ff fa67 bl 8000a54 + 8001586: 4602 mov r2, r0 + 8001588: 693b ldr r3, [r7, #16] + 800158a: 1ad3 subs r3, r2, r3 + 800158c: 2b02 cmp r3, #2 + 800158e: d901 bls.n 8001594 { return HAL_TIMEOUT; - 80014d8: 2303 movs r3, #3 - 80014da: e03e b.n 800155a + 8001590: 2303 movs r3, #3 + 8001592: e03e b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - 80014dc: 4b21 ldr r3, [pc, #132] @ (8001564 ) - 80014de: 681b ldr r3, [r3, #0] - 80014e0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 80014e4: 2b00 cmp r3, #0 - 80014e6: d0f0 beq.n 80014ca - 80014e8: e036 b.n 8001558 + 8001594: 4b21 ldr r3, [pc, #132] @ (800161c ) + 8001596: 681b ldr r3, [r3, #0] + 8001598: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800159c: 2b00 cmp r3, #0 + 800159e: d0f0 beq.n 8001582 + 80015a0: e036 b.n 8001610 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 80014ea: 4b1f ldr r3, [pc, #124] @ (8001568 ) - 80014ec: 2200 movs r2, #0 - 80014ee: 601a str r2, [r3, #0] + 80015a2: 4b1f ldr r3, [pc, #124] @ (8001620 ) + 80015a4: 2200 movs r2, #0 + 80015a6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80014f0: f7ff fa76 bl 80009e0 - 80014f4: 6138 str r0, [r7, #16] + 80015a8: f7ff fa54 bl 8000a54 + 80015ac: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 80014f6: e008 b.n 800150a + 80015ae: e008 b.n 80015c2 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 80014f8: f7ff fa72 bl 80009e0 - 80014fc: 4602 mov r2, r0 - 80014fe: 693b ldr r3, [r7, #16] - 8001500: 1ad3 subs r3, r2, r3 - 8001502: 2b02 cmp r3, #2 - 8001504: d901 bls.n 800150a + 80015b0: f7ff fa50 bl 8000a54 + 80015b4: 4602 mov r2, r0 + 80015b6: 693b ldr r3, [r7, #16] + 80015b8: 1ad3 subs r3, r2, r3 + 80015ba: 2b02 cmp r3, #2 + 80015bc: d901 bls.n 80015c2 { return HAL_TIMEOUT; - 8001506: 2303 movs r3, #3 - 8001508: e027 b.n 800155a + 80015be: 2303 movs r3, #3 + 80015c0: e027 b.n 8001612 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 800150a: 4b16 ldr r3, [pc, #88] @ (8001564 ) - 800150c: 681b ldr r3, [r3, #0] - 800150e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8001512: 2b00 cmp r3, #0 - 8001514: d1f0 bne.n 80014f8 - 8001516: e01f b.n 8001558 + 80015c2: 4b16 ldr r3, [pc, #88] @ (800161c ) + 80015c4: 681b ldr r3, [r3, #0] + 80015c6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80015ca: 2b00 cmp r3, #0 + 80015cc: d1f0 bne.n 80015b0 + 80015ce: e01f b.n 8001610 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 8001518: 687b ldr r3, [r7, #4] - 800151a: 6a5b ldr r3, [r3, #36] @ 0x24 - 800151c: 2b01 cmp r3, #1 - 800151e: d101 bne.n 8001524 + 80015d0: 687b ldr r3, [r7, #4] + 80015d2: 6a5b ldr r3, [r3, #36] @ 0x24 + 80015d4: 2b01 cmp r3, #1 + 80015d6: d101 bne.n 80015dc { return HAL_ERROR; - 8001520: 2301 movs r3, #1 - 8001522: e01a b.n 800155a + 80015d8: 2301 movs r3, #1 + 80015da: e01a b.n 8001612 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; - 8001524: 4b0f ldr r3, [pc, #60] @ (8001564 ) - 8001526: 689b ldr r3, [r3, #8] - 8001528: 617b str r3, [r7, #20] + 80015dc: 4b0f ldr r3, [pc, #60] @ (800161c ) + 80015de: 689b ldr r3, [r3, #8] + 80015e0: 617b str r3, [r7, #20] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 800152a: 697b ldr r3, [r7, #20] - 800152c: f403 3280 and.w r2, r3, #65536 @ 0x10000 - 8001530: 687b ldr r3, [r7, #4] - 8001532: 6a9b ldr r3, [r3, #40] @ 0x28 - 8001534: 429a cmp r2, r3 - 8001536: d10d bne.n 8001554 + 80015e2: 697b ldr r3, [r7, #20] + 80015e4: f403 3280 and.w r2, r3, #65536 @ 0x10000 + 80015e8: 687b ldr r3, [r7, #4] + 80015ea: 6a9b ldr r3, [r3, #40] @ 0x28 + 80015ec: 429a cmp r2, r3 + 80015ee: d10d bne.n 800160c (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || - 8001538: 697b ldr r3, [r7, #20] - 800153a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 - 800153e: 687b ldr r3, [r7, #4] - 8001540: 6adb ldr r3, [r3, #44] @ 0x2c + 80015f0: 697b ldr r3, [r7, #20] + 80015f2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 + 80015f6: 687b ldr r3, [r7, #4] + 80015f8: 6adb ldr r3, [r3, #44] @ 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8001542: 429a cmp r2, r3 - 8001544: d106 bne.n 8001554 + 80015fa: 429a cmp r2, r3 + 80015fc: d106 bne.n 800160c (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) - 8001546: 697b ldr r3, [r7, #20] - 8001548: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 - 800154c: 687b ldr r3, [r7, #4] - 800154e: 6b1b ldr r3, [r3, #48] @ 0x30 + 80015fe: 697b ldr r3, [r7, #20] + 8001600: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 + 8001604: 687b ldr r3, [r7, #4] + 8001606: 6b1b ldr r3, [r3, #48] @ 0x30 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || - 8001550: 429a cmp r2, r3 - 8001552: d001 beq.n 8001558 + 8001608: 429a cmp r2, r3 + 800160a: d001 beq.n 8001610 { return HAL_ERROR; - 8001554: 2301 movs r3, #1 - 8001556: e000 b.n 800155a + 800160c: 2301 movs r3, #1 + 800160e: e000 b.n 8001612 } } } } return HAL_OK; - 8001558: 2300 movs r3, #0 + 8001610: 2300 movs r3, #0 } - 800155a: 4618 mov r0, r3 - 800155c: 3720 adds r7, #32 - 800155e: 46bd mov sp, r7 - 8001560: bd80 pop {r7, pc} - 8001562: bf00 nop - 8001564: 40023800 .word 0x40023800 - 8001568: 42470060 .word 0x42470060 + 8001612: 4618 mov r0, r3 + 8001614: 3720 adds r7, #32 + 8001616: 46bd mov sp, r7 + 8001618: bd80 pop {r7, pc} + 800161a: bf00 nop + 800161c: 40023800 .word 0x40023800 + 8001620: 42470060 .word 0x42470060 -0800156c : +08001624 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 800156c: b580 push {r7, lr} - 800156e: b084 sub sp, #16 - 8001570: af00 add r7, sp, #0 - 8001572: 6078 str r0, [r7, #4] - 8001574: 6039 str r1, [r7, #0] + 8001624: b580 push {r7, lr} + 8001626: b084 sub sp, #16 + 8001628: af00 add r7, sp, #0 + 800162a: 6078 str r0, [r7, #4] + 800162c: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status; /* Check the parameters */ if(RCC_ClkInitStruct == NULL) - 8001576: 687b ldr r3, [r7, #4] - 8001578: 2b00 cmp r3, #0 - 800157a: d101 bne.n 8001580 + 800162e: 687b ldr r3, [r7, #4] + 8001630: 2b00 cmp r3, #0 + 8001632: d101 bne.n 8001638 { return HAL_ERROR; - 800157c: 2301 movs r3, #1 - 800157e: e11a b.n 80017b6 + 8001634: 2301 movs r3, #1 + 8001636: e11a b.n 800186e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) - 8001580: 4b8f ldr r3, [pc, #572] @ (80017c0 ) - 8001582: 681b ldr r3, [r3, #0] - 8001584: f003 0301 and.w r3, r3, #1 - 8001588: 683a ldr r2, [r7, #0] - 800158a: 429a cmp r2, r3 - 800158c: d919 bls.n 80015c2 + 8001638: 4b8f ldr r3, [pc, #572] @ (8001878 ) + 800163a: 681b ldr r3, [r3, #0] + 800163c: f003 0301 and.w r3, r3, #1 + 8001640: 683a ldr r2, [r7, #0] + 8001642: 429a cmp r2, r3 + 8001644: d919 bls.n 800167a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 800158e: 683b ldr r3, [r7, #0] - 8001590: 2b01 cmp r3, #1 - 8001592: d105 bne.n 80015a0 - 8001594: 4b8a ldr r3, [pc, #552] @ (80017c0 ) - 8001596: 681b ldr r3, [r3, #0] - 8001598: 4a89 ldr r2, [pc, #548] @ (80017c0 ) - 800159a: f043 0304 orr.w r3, r3, #4 - 800159e: 6013 str r3, [r2, #0] - 80015a0: 4b87 ldr r3, [pc, #540] @ (80017c0 ) - 80015a2: 681b ldr r3, [r3, #0] - 80015a4: f023 0201 bic.w r2, r3, #1 - 80015a8: 4985 ldr r1, [pc, #532] @ (80017c0 ) - 80015aa: 683b ldr r3, [r7, #0] - 80015ac: 4313 orrs r3, r2 - 80015ae: 600b str r3, [r1, #0] + 8001646: 683b ldr r3, [r7, #0] + 8001648: 2b01 cmp r3, #1 + 800164a: d105 bne.n 8001658 + 800164c: 4b8a ldr r3, [pc, #552] @ (8001878 ) + 800164e: 681b ldr r3, [r3, #0] + 8001650: 4a89 ldr r2, [pc, #548] @ (8001878 ) + 8001652: f043 0304 orr.w r3, r3, #4 + 8001656: 6013 str r3, [r2, #0] + 8001658: 4b87 ldr r3, [pc, #540] @ (8001878 ) + 800165a: 681b ldr r3, [r3, #0] + 800165c: f023 0201 bic.w r2, r3, #1 + 8001660: 4985 ldr r1, [pc, #532] @ (8001878 ) + 8001662: 683b ldr r3, [r7, #0] + 8001664: 4313 orrs r3, r2 + 8001666: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 80015b0: 4b83 ldr r3, [pc, #524] @ (80017c0 ) - 80015b2: 681b ldr r3, [r3, #0] - 80015b4: f003 0301 and.w r3, r3, #1 - 80015b8: 683a ldr r2, [r7, #0] - 80015ba: 429a cmp r2, r3 - 80015bc: d001 beq.n 80015c2 + 8001668: 4b83 ldr r3, [pc, #524] @ (8001878 ) + 800166a: 681b ldr r3, [r3, #0] + 800166c: f003 0301 and.w r3, r3, #1 + 8001670: 683a ldr r2, [r7, #0] + 8001672: 429a cmp r2, r3 + 8001674: d001 beq.n 800167a { return HAL_ERROR; - 80015be: 2301 movs r3, #1 - 80015c0: e0f9 b.n 80017b6 + 8001676: 2301 movs r3, #1 + 8001678: e0f9 b.n 800186e } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 80015c2: 687b ldr r3, [r7, #4] - 80015c4: 681b ldr r3, [r3, #0] - 80015c6: f003 0302 and.w r3, r3, #2 - 80015ca: 2b00 cmp r3, #0 - 80015cc: d008 beq.n 80015e0 + 800167a: 687b ldr r3, [r7, #4] + 800167c: 681b ldr r3, [r3, #0] + 800167e: f003 0302 and.w r3, r3, #2 + 8001682: 2b00 cmp r3, #0 + 8001684: d008 beq.n 8001698 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 80015ce: 4b7d ldr r3, [pc, #500] @ (80017c4 ) - 80015d0: 689b ldr r3, [r3, #8] - 80015d2: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 80015d6: 687b ldr r3, [r7, #4] - 80015d8: 689b ldr r3, [r3, #8] - 80015da: 497a ldr r1, [pc, #488] @ (80017c4 ) - 80015dc: 4313 orrs r3, r2 - 80015de: 608b str r3, [r1, #8] + 8001686: 4b7d ldr r3, [pc, #500] @ (800187c ) + 8001688: 689b ldr r3, [r3, #8] + 800168a: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 800168e: 687b ldr r3, [r7, #4] + 8001690: 689b ldr r3, [r3, #8] + 8001692: 497a ldr r1, [pc, #488] @ (800187c ) + 8001694: 4313 orrs r3, r2 + 8001696: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 80015e0: 687b ldr r3, [r7, #4] - 80015e2: 681b ldr r3, [r3, #0] - 80015e4: f003 0301 and.w r3, r3, #1 - 80015e8: 2b00 cmp r3, #0 - 80015ea: f000 808e beq.w 800170a + 8001698: 687b ldr r3, [r7, #4] + 800169a: 681b ldr r3, [r3, #0] + 800169c: f003 0301 and.w r3, r3, #1 + 80016a0: 2b00 cmp r3, #0 + 80016a2: f000 808e beq.w 80017c2 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 80015ee: 687b ldr r3, [r7, #4] - 80015f0: 685b ldr r3, [r3, #4] - 80015f2: 2b02 cmp r3, #2 - 80015f4: d107 bne.n 8001606 + 80016a6: 687b ldr r3, [r7, #4] + 80016a8: 685b ldr r3, [r3, #4] + 80016aa: 2b02 cmp r3, #2 + 80016ac: d107 bne.n 80016be { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - 80015f6: 4b73 ldr r3, [pc, #460] @ (80017c4 ) - 80015f8: 681b ldr r3, [r3, #0] - 80015fa: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80015fe: 2b00 cmp r3, #0 - 8001600: d121 bne.n 8001646 + 80016ae: 4b73 ldr r3, [pc, #460] @ (800187c ) + 80016b0: 681b ldr r3, [r3, #0] + 80016b2: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80016b6: 2b00 cmp r3, #0 + 80016b8: d121 bne.n 80016fe { return HAL_ERROR; - 8001602: 2301 movs r3, #1 - 8001604: e0d7 b.n 80017b6 + 80016ba: 2301 movs r3, #1 + 80016bc: e0d7 b.n 800186e } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 8001606: 687b ldr r3, [r7, #4] - 8001608: 685b ldr r3, [r3, #4] - 800160a: 2b03 cmp r3, #3 - 800160c: d107 bne.n 800161e + 80016be: 687b ldr r3, [r7, #4] + 80016c0: 685b ldr r3, [r3, #4] + 80016c2: 2b03 cmp r3, #3 + 80016c4: d107 bne.n 80016d6 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - 800160e: 4b6d ldr r3, [pc, #436] @ (80017c4 ) - 8001610: 681b ldr r3, [r3, #0] - 8001612: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8001616: 2b00 cmp r3, #0 - 8001618: d115 bne.n 8001646 + 80016c6: 4b6d ldr r3, [pc, #436] @ (800187c ) + 80016c8: 681b ldr r3, [r3, #0] + 80016ca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80016ce: 2b00 cmp r3, #0 + 80016d0: d115 bne.n 80016fe { return HAL_ERROR; - 800161a: 2301 movs r3, #1 - 800161c: e0cb b.n 80017b6 + 80016d2: 2301 movs r3, #1 + 80016d4: e0cb b.n 800186e } } /* HSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - 800161e: 687b ldr r3, [r7, #4] - 8001620: 685b ldr r3, [r3, #4] - 8001622: 2b01 cmp r3, #1 - 8001624: d107 bne.n 8001636 + 80016d6: 687b ldr r3, [r7, #4] + 80016d8: 685b ldr r3, [r3, #4] + 80016da: 2b01 cmp r3, #1 + 80016dc: d107 bne.n 80016ee { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - 8001626: 4b67 ldr r3, [pc, #412] @ (80017c4 ) - 8001628: 681b ldr r3, [r3, #0] - 800162a: f003 0302 and.w r3, r3, #2 - 800162e: 2b00 cmp r3, #0 - 8001630: d109 bne.n 8001646 + 80016de: 4b67 ldr r3, [pc, #412] @ (800187c ) + 80016e0: 681b ldr r3, [r3, #0] + 80016e2: f003 0302 and.w r3, r3, #2 + 80016e6: 2b00 cmp r3, #0 + 80016e8: d109 bne.n 80016fe { return HAL_ERROR; - 8001632: 2301 movs r3, #1 - 8001634: e0bf b.n 80017b6 + 80016ea: 2301 movs r3, #1 + 80016ec: e0bf b.n 800186e } /* MSI is selected as System Clock Source */ else { /* Check the MSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - 8001636: 4b63 ldr r3, [pc, #396] @ (80017c4 ) - 8001638: 681b ldr r3, [r3, #0] - 800163a: f403 7300 and.w r3, r3, #512 @ 0x200 - 800163e: 2b00 cmp r3, #0 - 8001640: d101 bne.n 8001646 + 80016ee: 4b63 ldr r3, [pc, #396] @ (800187c ) + 80016f0: 681b ldr r3, [r3, #0] + 80016f2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80016f6: 2b00 cmp r3, #0 + 80016f8: d101 bne.n 80016fe { return HAL_ERROR; - 8001642: 2301 movs r3, #1 - 8001644: e0b7 b.n 80017b6 + 80016fa: 2301 movs r3, #1 + 80016fc: e0b7 b.n 800186e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 8001646: 4b5f ldr r3, [pc, #380] @ (80017c4 ) - 8001648: 689b ldr r3, [r3, #8] - 800164a: f023 0203 bic.w r2, r3, #3 - 800164e: 687b ldr r3, [r7, #4] - 8001650: 685b ldr r3, [r3, #4] - 8001652: 495c ldr r1, [pc, #368] @ (80017c4 ) - 8001654: 4313 orrs r3, r2 - 8001656: 608b str r3, [r1, #8] + 80016fe: 4b5f ldr r3, [pc, #380] @ (800187c ) + 8001700: 689b ldr r3, [r3, #8] + 8001702: f023 0203 bic.w r2, r3, #3 + 8001706: 687b ldr r3, [r7, #4] + 8001708: 685b ldr r3, [r3, #4] + 800170a: 495c ldr r1, [pc, #368] @ (800187c ) + 800170c: 4313 orrs r3, r2 + 800170e: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001658: f7ff f9c2 bl 80009e0 - 800165c: 60f8 str r0, [r7, #12] + 8001710: f7ff f9a0 bl 8000a54 + 8001714: 60f8 str r0, [r7, #12] if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 800165e: 687b ldr r3, [r7, #4] - 8001660: 685b ldr r3, [r3, #4] - 8001662: 2b02 cmp r3, #2 - 8001664: d112 bne.n 800168c + 8001716: 687b ldr r3, [r7, #4] + 8001718: 685b ldr r3, [r3, #4] + 800171a: 2b02 cmp r3, #2 + 800171c: d112 bne.n 8001744 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - 8001666: e00a b.n 800167e + 800171e: e00a b.n 8001736 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 8001668: f7ff f9ba bl 80009e0 - 800166c: 4602 mov r2, r0 - 800166e: 68fb ldr r3, [r7, #12] - 8001670: 1ad3 subs r3, r2, r3 - 8001672: f241 3288 movw r2, #5000 @ 0x1388 - 8001676: 4293 cmp r3, r2 - 8001678: d901 bls.n 800167e + 8001720: f7ff f998 bl 8000a54 + 8001724: 4602 mov r2, r0 + 8001726: 68fb ldr r3, [r7, #12] + 8001728: 1ad3 subs r3, r2, r3 + 800172a: f241 3288 movw r2, #5000 @ 0x1388 + 800172e: 4293 cmp r3, r2 + 8001730: d901 bls.n 8001736 { return HAL_TIMEOUT; - 800167a: 2303 movs r3, #3 - 800167c: e09b b.n 80017b6 + 8001732: 2303 movs r3, #3 + 8001734: e09b b.n 800186e while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - 800167e: 4b51 ldr r3, [pc, #324] @ (80017c4 ) - 8001680: 689b ldr r3, [r3, #8] - 8001682: f003 030c and.w r3, r3, #12 - 8001686: 2b08 cmp r3, #8 - 8001688: d1ee bne.n 8001668 - 800168a: e03e b.n 800170a + 8001736: 4b51 ldr r3, [pc, #324] @ (800187c ) + 8001738: 689b ldr r3, [r3, #8] + 800173a: f003 030c and.w r3, r3, #12 + 800173e: 2b08 cmp r3, #8 + 8001740: d1ee bne.n 8001720 + 8001742: e03e b.n 80017c2 } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 800168c: 687b ldr r3, [r7, #4] - 800168e: 685b ldr r3, [r3, #4] - 8001690: 2b03 cmp r3, #3 - 8001692: d112 bne.n 80016ba + 8001744: 687b ldr r3, [r7, #4] + 8001746: 685b ldr r3, [r3, #4] + 8001748: 2b03 cmp r3, #3 + 800174a: d112 bne.n 8001772 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 8001694: e00a b.n 80016ac + 800174c: e00a b.n 8001764 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 8001696: f7ff f9a3 bl 80009e0 - 800169a: 4602 mov r2, r0 - 800169c: 68fb ldr r3, [r7, #12] - 800169e: 1ad3 subs r3, r2, r3 - 80016a0: f241 3288 movw r2, #5000 @ 0x1388 - 80016a4: 4293 cmp r3, r2 - 80016a6: d901 bls.n 80016ac + 800174e: f7ff f981 bl 8000a54 + 8001752: 4602 mov r2, r0 + 8001754: 68fb ldr r3, [r7, #12] + 8001756: 1ad3 subs r3, r2, r3 + 8001758: f241 3288 movw r2, #5000 @ 0x1388 + 800175c: 4293 cmp r3, r2 + 800175e: d901 bls.n 8001764 { return HAL_TIMEOUT; - 80016a8: 2303 movs r3, #3 - 80016aa: e084 b.n 80017b6 + 8001760: 2303 movs r3, #3 + 8001762: e084 b.n 800186e while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 80016ac: 4b45 ldr r3, [pc, #276] @ (80017c4 ) - 80016ae: 689b ldr r3, [r3, #8] - 80016b0: f003 030c and.w r3, r3, #12 - 80016b4: 2b0c cmp r3, #12 - 80016b6: d1ee bne.n 8001696 - 80016b8: e027 b.n 800170a + 8001764: 4b45 ldr r3, [pc, #276] @ (800187c ) + 8001766: 689b ldr r3, [r3, #8] + 8001768: f003 030c and.w r3, r3, #12 + 800176c: 2b0c cmp r3, #12 + 800176e: d1ee bne.n 800174e + 8001770: e027 b.n 80017c2 } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - 80016ba: 687b ldr r3, [r7, #4] - 80016bc: 685b ldr r3, [r3, #4] - 80016be: 2b01 cmp r3, #1 - 80016c0: d11d bne.n 80016fe + 8001772: 687b ldr r3, [r7, #4] + 8001774: 685b ldr r3, [r3, #4] + 8001776: 2b01 cmp r3, #1 + 8001778: d11d bne.n 80017b6 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - 80016c2: e00a b.n 80016da + 800177a: e00a b.n 8001792 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 80016c4: f7ff f98c bl 80009e0 - 80016c8: 4602 mov r2, r0 - 80016ca: 68fb ldr r3, [r7, #12] - 80016cc: 1ad3 subs r3, r2, r3 - 80016ce: f241 3288 movw r2, #5000 @ 0x1388 - 80016d2: 4293 cmp r3, r2 - 80016d4: d901 bls.n 80016da + 800177c: f7ff f96a bl 8000a54 + 8001780: 4602 mov r2, r0 + 8001782: 68fb ldr r3, [r7, #12] + 8001784: 1ad3 subs r3, r2, r3 + 8001786: f241 3288 movw r2, #5000 @ 0x1388 + 800178a: 4293 cmp r3, r2 + 800178c: d901 bls.n 8001792 { return HAL_TIMEOUT; - 80016d6: 2303 movs r3, #3 - 80016d8: e06d b.n 80017b6 + 800178e: 2303 movs r3, #3 + 8001790: e06d b.n 800186e while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - 80016da: 4b3a ldr r3, [pc, #232] @ (80017c4 ) - 80016dc: 689b ldr r3, [r3, #8] - 80016de: f003 030c and.w r3, r3, #12 - 80016e2: 2b04 cmp r3, #4 - 80016e4: d1ee bne.n 80016c4 - 80016e6: e010 b.n 800170a + 8001792: 4b3a ldr r3, [pc, #232] @ (800187c ) + 8001794: 689b ldr r3, [r3, #8] + 8001796: f003 030c and.w r3, r3, #12 + 800179a: 2b04 cmp r3, #4 + 800179c: d1ee bne.n 800177c + 800179e: e010 b.n 80017c2 } else { while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 80016e8: f7ff f97a bl 80009e0 - 80016ec: 4602 mov r2, r0 - 80016ee: 68fb ldr r3, [r7, #12] - 80016f0: 1ad3 subs r3, r2, r3 - 80016f2: f241 3288 movw r2, #5000 @ 0x1388 - 80016f6: 4293 cmp r3, r2 - 80016f8: d901 bls.n 80016fe + 80017a0: f7ff f958 bl 8000a54 + 80017a4: 4602 mov r2, r0 + 80017a6: 68fb ldr r3, [r7, #12] + 80017a8: 1ad3 subs r3, r2, r3 + 80017aa: f241 3288 movw r2, #5000 @ 0x1388 + 80017ae: 4293 cmp r3, r2 + 80017b0: d901 bls.n 80017b6 { return HAL_TIMEOUT; - 80016fa: 2303 movs r3, #3 - 80016fc: e05b b.n 80017b6 + 80017b2: 2303 movs r3, #3 + 80017b4: e05b b.n 800186e while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) - 80016fe: 4b31 ldr r3, [pc, #196] @ (80017c4 ) - 8001700: 689b ldr r3, [r3, #8] - 8001702: f003 030c and.w r3, r3, #12 - 8001706: 2b00 cmp r3, #0 - 8001708: d1ee bne.n 80016e8 + 80017b6: 4b31 ldr r3, [pc, #196] @ (800187c ) + 80017b8: 689b ldr r3, [r3, #8] + 80017ba: f003 030c and.w r3, r3, #12 + 80017be: 2b00 cmp r3, #0 + 80017c0: d1ee bne.n 80017a0 } } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) - 800170a: 4b2d ldr r3, [pc, #180] @ (80017c0 ) - 800170c: 681b ldr r3, [r3, #0] - 800170e: f003 0301 and.w r3, r3, #1 - 8001712: 683a ldr r2, [r7, #0] - 8001714: 429a cmp r2, r3 - 8001716: d219 bcs.n 800174c + 80017c2: 4b2d ldr r3, [pc, #180] @ (8001878 ) + 80017c4: 681b ldr r3, [r3, #0] + 80017c6: f003 0301 and.w r3, r3, #1 + 80017ca: 683a ldr r2, [r7, #0] + 80017cc: 429a cmp r2, r3 + 80017ce: d219 bcs.n 8001804 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8001718: 683b ldr r3, [r7, #0] - 800171a: 2b01 cmp r3, #1 - 800171c: d105 bne.n 800172a - 800171e: 4b28 ldr r3, [pc, #160] @ (80017c0 ) - 8001720: 681b ldr r3, [r3, #0] - 8001722: 4a27 ldr r2, [pc, #156] @ (80017c0 ) - 8001724: f043 0304 orr.w r3, r3, #4 - 8001728: 6013 str r3, [r2, #0] - 800172a: 4b25 ldr r3, [pc, #148] @ (80017c0 ) - 800172c: 681b ldr r3, [r3, #0] - 800172e: f023 0201 bic.w r2, r3, #1 - 8001732: 4923 ldr r1, [pc, #140] @ (80017c0 ) - 8001734: 683b ldr r3, [r7, #0] - 8001736: 4313 orrs r3, r2 - 8001738: 600b str r3, [r1, #0] + 80017d0: 683b ldr r3, [r7, #0] + 80017d2: 2b01 cmp r3, #1 + 80017d4: d105 bne.n 80017e2 + 80017d6: 4b28 ldr r3, [pc, #160] @ (8001878 ) + 80017d8: 681b ldr r3, [r3, #0] + 80017da: 4a27 ldr r2, [pc, #156] @ (8001878 ) + 80017dc: f043 0304 orr.w r3, r3, #4 + 80017e0: 6013 str r3, [r2, #0] + 80017e2: 4b25 ldr r3, [pc, #148] @ (8001878 ) + 80017e4: 681b ldr r3, [r3, #0] + 80017e6: f023 0201 bic.w r2, r3, #1 + 80017ea: 4923 ldr r1, [pc, #140] @ (8001878 ) + 80017ec: 683b ldr r3, [r7, #0] + 80017ee: 4313 orrs r3, r2 + 80017f0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 800173a: 4b21 ldr r3, [pc, #132] @ (80017c0 ) - 800173c: 681b ldr r3, [r3, #0] - 800173e: f003 0301 and.w r3, r3, #1 - 8001742: 683a ldr r2, [r7, #0] - 8001744: 429a cmp r2, r3 - 8001746: d001 beq.n 800174c + 80017f2: 4b21 ldr r3, [pc, #132] @ (8001878 ) + 80017f4: 681b ldr r3, [r3, #0] + 80017f6: f003 0301 and.w r3, r3, #1 + 80017fa: 683a ldr r2, [r7, #0] + 80017fc: 429a cmp r2, r3 + 80017fe: d001 beq.n 8001804 { return HAL_ERROR; - 8001748: 2301 movs r3, #1 - 800174a: e034 b.n 80017b6 + 8001800: 2301 movs r3, #1 + 8001802: e034 b.n 800186e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 800174c: 687b ldr r3, [r7, #4] - 800174e: 681b ldr r3, [r3, #0] - 8001750: f003 0304 and.w r3, r3, #4 - 8001754: 2b00 cmp r3, #0 - 8001756: d008 beq.n 800176a + 8001804: 687b ldr r3, [r7, #4] + 8001806: 681b ldr r3, [r3, #0] + 8001808: f003 0304 and.w r3, r3, #4 + 800180c: 2b00 cmp r3, #0 + 800180e: d008 beq.n 8001822 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8001758: 4b1a ldr r3, [pc, #104] @ (80017c4 ) - 800175a: 689b ldr r3, [r3, #8] - 800175c: f423 62e0 bic.w r2, r3, #1792 @ 0x700 - 8001760: 687b ldr r3, [r7, #4] - 8001762: 68db ldr r3, [r3, #12] - 8001764: 4917 ldr r1, [pc, #92] @ (80017c4 ) - 8001766: 4313 orrs r3, r2 - 8001768: 608b str r3, [r1, #8] + 8001810: 4b1a ldr r3, [pc, #104] @ (800187c ) + 8001812: 689b ldr r3, [r3, #8] + 8001814: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8001818: 687b ldr r3, [r7, #4] + 800181a: 68db ldr r3, [r3, #12] + 800181c: 4917 ldr r1, [pc, #92] @ (800187c ) + 800181e: 4313 orrs r3, r2 + 8001820: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 800176a: 687b ldr r3, [r7, #4] - 800176c: 681b ldr r3, [r3, #0] - 800176e: f003 0308 and.w r3, r3, #8 - 8001772: 2b00 cmp r3, #0 - 8001774: d009 beq.n 800178a + 8001822: 687b ldr r3, [r7, #4] + 8001824: 681b ldr r3, [r3, #0] + 8001826: f003 0308 and.w r3, r3, #8 + 800182a: 2b00 cmp r3, #0 + 800182c: d009 beq.n 8001842 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 8001776: 4b13 ldr r3, [pc, #76] @ (80017c4 ) - 8001778: 689b ldr r3, [r3, #8] - 800177a: f423 5260 bic.w r2, r3, #14336 @ 0x3800 - 800177e: 687b ldr r3, [r7, #4] - 8001780: 691b ldr r3, [r3, #16] - 8001782: 00db lsls r3, r3, #3 - 8001784: 490f ldr r1, [pc, #60] @ (80017c4 ) - 8001786: 4313 orrs r3, r2 - 8001788: 608b str r3, [r1, #8] + 800182e: 4b13 ldr r3, [pc, #76] @ (800187c ) + 8001830: 689b ldr r3, [r3, #8] + 8001832: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8001836: 687b ldr r3, [r7, #4] + 8001838: 691b ldr r3, [r3, #16] + 800183a: 00db lsls r3, r3, #3 + 800183c: 490f ldr r1, [pc, #60] @ (800187c ) + 800183e: 4313 orrs r3, r2 + 8001840: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - 800178a: f000 f823 bl 80017d4 - 800178e: 4602 mov r2, r0 - 8001790: 4b0c ldr r3, [pc, #48] @ (80017c4 ) - 8001792: 689b ldr r3, [r3, #8] - 8001794: 091b lsrs r3, r3, #4 - 8001796: f003 030f and.w r3, r3, #15 - 800179a: 490b ldr r1, [pc, #44] @ (80017c8 ) - 800179c: 5ccb ldrb r3, [r1, r3] - 800179e: fa22 f303 lsr.w r3, r2, r3 - 80017a2: 4a0a ldr r2, [pc, #40] @ (80017cc ) - 80017a4: 6013 str r3, [r2, #0] + 8001842: f000 f823 bl 800188c + 8001846: 4602 mov r2, r0 + 8001848: 4b0c ldr r3, [pc, #48] @ (800187c ) + 800184a: 689b ldr r3, [r3, #8] + 800184c: 091b lsrs r3, r3, #4 + 800184e: f003 030f and.w r3, r3, #15 + 8001852: 490b ldr r1, [pc, #44] @ (8001880 ) + 8001854: 5ccb ldrb r3, [r1, r3] + 8001856: fa22 f303 lsr.w r3, r2, r3 + 800185a: 4a0a ldr r2, [pc, #40] @ (8001884 ) + 800185c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); - 80017a6: 4b0a ldr r3, [pc, #40] @ (80017d0 ) - 80017a8: 681b ldr r3, [r3, #0] - 80017aa: 4618 mov r0, r3 - 80017ac: f7ff f8cc bl 8000948 - 80017b0: 4603 mov r3, r0 - 80017b2: 72fb strb r3, [r7, #11] + 800185e: 4b0a ldr r3, [pc, #40] @ (8001888 ) + 8001860: 681b ldr r3, [r3, #0] + 8001862: 4618 mov r0, r3 + 8001864: f7ff f8aa bl 80009bc + 8001868: 4603 mov r3, r0 + 800186a: 72fb strb r3, [r7, #11] return status; - 80017b4: 7afb ldrb r3, [r7, #11] + 800186c: 7afb ldrb r3, [r7, #11] } - 80017b6: 4618 mov r0, r3 - 80017b8: 3710 adds r7, #16 - 80017ba: 46bd mov sp, r7 - 80017bc: bd80 pop {r7, pc} - 80017be: bf00 nop - 80017c0: 40023c00 .word 0x40023c00 - 80017c4: 40023800 .word 0x40023800 - 80017c8: 08001fe0 .word 0x08001fe0 - 80017cc: 20000000 .word 0x20000000 - 80017d0: 20000004 .word 0x20000004 + 800186e: 4618 mov r0, r3 + 8001870: 3710 adds r7, #16 + 8001872: 46bd mov sp, r7 + 8001874: bd80 pop {r7, pc} + 8001876: bf00 nop + 8001878: 40023c00 .word 0x40023c00 + 800187c: 40023800 .word 0x40023800 + 8001880: 08002098 .word 0x08002098 + 8001884: 20000000 .word 0x20000000 + 8001888: 20000004 .word 0x20000004 -080017d4 : +0800188c : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 80017d4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 80017d8: b08e sub sp, #56 @ 0x38 - 80017da: af00 add r7, sp, #0 + 800188c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8001890: b08e sub sp, #56 @ 0x38 + 8001892: af00 add r7, sp, #0 uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; tmpreg = RCC->CFGR; - 80017dc: 4b58 ldr r3, [pc, #352] @ (8001940 ) - 80017de: 689b ldr r3, [r3, #8] - 80017e0: 62fb str r3, [r7, #44] @ 0x2c + 8001894: 4b58 ldr r3, [pc, #352] @ (80019f8 ) + 8001896: 689b ldr r3, [r3, #8] + 8001898: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) - 80017e2: 6afb ldr r3, [r7, #44] @ 0x2c - 80017e4: f003 030c and.w r3, r3, #12 - 80017e8: 2b0c cmp r3, #12 - 80017ea: d00d beq.n 8001808 - 80017ec: 2b0c cmp r3, #12 - 80017ee: f200 8092 bhi.w 8001916 - 80017f2: 2b04 cmp r3, #4 - 80017f4: d002 beq.n 80017fc - 80017f6: 2b08 cmp r3, #8 - 80017f8: d003 beq.n 8001802 - 80017fa: e08c b.n 8001916 + 800189a: 6afb ldr r3, [r7, #44] @ 0x2c + 800189c: f003 030c and.w r3, r3, #12 + 80018a0: 2b0c cmp r3, #12 + 80018a2: d00d beq.n 80018c0 + 80018a4: 2b0c cmp r3, #12 + 80018a6: f200 8092 bhi.w 80019ce + 80018aa: 2b04 cmp r3, #4 + 80018ac: d002 beq.n 80018b4 + 80018ae: 2b08 cmp r3, #8 + 80018b0: d003 beq.n 80018ba + 80018b2: e08c b.n 80019ce { case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; - 80017fc: 4b51 ldr r3, [pc, #324] @ (8001944 ) - 80017fe: 633b str r3, [r7, #48] @ 0x30 + 80018b4: 4b51 ldr r3, [pc, #324] @ (80019fc ) + 80018b6: 633b str r3, [r7, #48] @ 0x30 break; - 8001800: e097 b.n 8001932 + 80018b8: e097 b.n 80019ea } case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; - 8001802: 4b51 ldr r3, [pc, #324] @ (8001948 ) - 8001804: 633b str r3, [r7, #48] @ 0x30 + 80018ba: 4b51 ldr r3, [pc, #324] @ (8001a00 ) + 80018bc: 633b str r3, [r7, #48] @ 0x30 break; - 8001806: e094 b.n 8001932 + 80018be: e094 b.n 80019ea } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; - 8001808: 6afb ldr r3, [r7, #44] @ 0x2c - 800180a: 0c9b lsrs r3, r3, #18 - 800180c: f003 020f and.w r2, r3, #15 - 8001810: 4b4e ldr r3, [pc, #312] @ (800194c ) - 8001812: 5c9b ldrb r3, [r3, r2] - 8001814: 62bb str r3, [r7, #40] @ 0x28 + 80018c0: 6afb ldr r3, [r7, #44] @ 0x2c + 80018c2: 0c9b lsrs r3, r3, #18 + 80018c4: f003 020f and.w r2, r3, #15 + 80018c8: 4b4e ldr r3, [pc, #312] @ (8001a04 ) + 80018ca: 5c9b ldrb r3, [r3, r2] + 80018cc: 62bb str r3, [r7, #40] @ 0x28 plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; - 8001816: 6afb ldr r3, [r7, #44] @ 0x2c - 8001818: 0d9b lsrs r3, r3, #22 - 800181a: f003 0303 and.w r3, r3, #3 - 800181e: 3301 adds r3, #1 - 8001820: 627b str r3, [r7, #36] @ 0x24 + 80018ce: 6afb ldr r3, [r7, #44] @ 0x2c + 80018d0: 0d9b lsrs r3, r3, #22 + 80018d2: f003 0303 and.w r3, r3, #3 + 80018d6: 3301 adds r3, #1 + 80018d8: 627b str r3, [r7, #36] @ 0x24 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - 8001822: 4b47 ldr r3, [pc, #284] @ (8001940 ) - 8001824: 689b ldr r3, [r3, #8] - 8001826: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 800182a: 2b00 cmp r3, #0 - 800182c: d021 beq.n 8001872 + 80018da: 4b47 ldr r3, [pc, #284] @ (80019f8 ) + 80018dc: 689b ldr r3, [r3, #8] + 80018de: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 80018e2: 2b00 cmp r3, #0 + 80018e4: d021 beq.n 800192a { /* HSE used as PLL clock source */ pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); - 800182e: 6abb ldr r3, [r7, #40] @ 0x28 - 8001830: 2200 movs r2, #0 - 8001832: 61bb str r3, [r7, #24] - 8001834: 61fa str r2, [r7, #28] - 8001836: 4b44 ldr r3, [pc, #272] @ (8001948 ) - 8001838: e9d7 8906 ldrd r8, r9, [r7, #24] - 800183c: 464a mov r2, r9 - 800183e: fb03 f202 mul.w r2, r3, r2 - 8001842: 2300 movs r3, #0 - 8001844: 4644 mov r4, r8 - 8001846: fb04 f303 mul.w r3, r4, r3 - 800184a: 4413 add r3, r2 - 800184c: 4a3e ldr r2, [pc, #248] @ (8001948 ) - 800184e: 4644 mov r4, r8 - 8001850: fba4 0102 umull r0, r1, r4, r2 - 8001854: 440b add r3, r1 - 8001856: 4619 mov r1, r3 - 8001858: 6a7b ldr r3, [r7, #36] @ 0x24 - 800185a: 2200 movs r2, #0 - 800185c: 613b str r3, [r7, #16] - 800185e: 617a str r2, [r7, #20] - 8001860: e9d7 2304 ldrd r2, r3, [r7, #16] - 8001864: f7fe fc8a bl 800017c <__aeabi_uldivmod> - 8001868: 4602 mov r2, r0 - 800186a: 460b mov r3, r1 - 800186c: 4613 mov r3, r2 - 800186e: 637b str r3, [r7, #52] @ 0x34 - 8001870: e04e b.n 8001910 + 80018e6: 6abb ldr r3, [r7, #40] @ 0x28 + 80018e8: 2200 movs r2, #0 + 80018ea: 61bb str r3, [r7, #24] + 80018ec: 61fa str r2, [r7, #28] + 80018ee: 4b44 ldr r3, [pc, #272] @ (8001a00 ) + 80018f0: e9d7 8906 ldrd r8, r9, [r7, #24] + 80018f4: 464a mov r2, r9 + 80018f6: fb03 f202 mul.w r2, r3, r2 + 80018fa: 2300 movs r3, #0 + 80018fc: 4644 mov r4, r8 + 80018fe: fb04 f303 mul.w r3, r4, r3 + 8001902: 4413 add r3, r2 + 8001904: 4a3e ldr r2, [pc, #248] @ (8001a00 ) + 8001906: 4644 mov r4, r8 + 8001908: fba4 0102 umull r0, r1, r4, r2 + 800190c: 440b add r3, r1 + 800190e: 4619 mov r1, r3 + 8001910: 6a7b ldr r3, [r7, #36] @ 0x24 + 8001912: 2200 movs r2, #0 + 8001914: 613b str r3, [r7, #16] + 8001916: 617a str r2, [r7, #20] + 8001918: e9d7 2304 ldrd r2, r3, [r7, #16] + 800191c: f7fe fc2e bl 800017c <__aeabi_uldivmod> + 8001920: 4602 mov r2, r0 + 8001922: 460b mov r3, r1 + 8001924: 4613 mov r3, r2 + 8001926: 637b str r3, [r7, #52] @ 0x34 + 8001928: e04e b.n 80019c8 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); - 8001872: 6abb ldr r3, [r7, #40] @ 0x28 - 8001874: 2200 movs r2, #0 - 8001876: 469a mov sl, r3 - 8001878: 4693 mov fp, r2 - 800187a: 4652 mov r2, sl - 800187c: 465b mov r3, fp - 800187e: f04f 0000 mov.w r0, #0 - 8001882: f04f 0100 mov.w r1, #0 - 8001886: 0159 lsls r1, r3, #5 - 8001888: ea41 61d2 orr.w r1, r1, r2, lsr #27 - 800188c: 0150 lsls r0, r2, #5 - 800188e: 4602 mov r2, r0 - 8001890: 460b mov r3, r1 - 8001892: ebb2 080a subs.w r8, r2, sl - 8001896: eb63 090b sbc.w r9, r3, fp - 800189a: f04f 0200 mov.w r2, #0 - 800189e: f04f 0300 mov.w r3, #0 - 80018a2: ea4f 1389 mov.w r3, r9, lsl #6 - 80018a6: ea43 6398 orr.w r3, r3, r8, lsr #26 - 80018aa: ea4f 1288 mov.w r2, r8, lsl #6 - 80018ae: ebb2 0408 subs.w r4, r2, r8 - 80018b2: eb63 0509 sbc.w r5, r3, r9 - 80018b6: f04f 0200 mov.w r2, #0 - 80018ba: f04f 0300 mov.w r3, #0 - 80018be: 00eb lsls r3, r5, #3 - 80018c0: ea43 7354 orr.w r3, r3, r4, lsr #29 - 80018c4: 00e2 lsls r2, r4, #3 - 80018c6: 4614 mov r4, r2 - 80018c8: 461d mov r5, r3 - 80018ca: eb14 030a adds.w r3, r4, sl - 80018ce: 603b str r3, [r7, #0] - 80018d0: eb45 030b adc.w r3, r5, fp - 80018d4: 607b str r3, [r7, #4] - 80018d6: f04f 0200 mov.w r2, #0 - 80018da: f04f 0300 mov.w r3, #0 - 80018de: e9d7 4500 ldrd r4, r5, [r7] - 80018e2: 4629 mov r1, r5 - 80018e4: 028b lsls r3, r1, #10 - 80018e6: 4620 mov r0, r4 - 80018e8: 4629 mov r1, r5 - 80018ea: 4604 mov r4, r0 - 80018ec: ea43 5394 orr.w r3, r3, r4, lsr #22 - 80018f0: 4601 mov r1, r0 - 80018f2: 028a lsls r2, r1, #10 - 80018f4: 4610 mov r0, r2 - 80018f6: 4619 mov r1, r3 - 80018f8: 6a7b ldr r3, [r7, #36] @ 0x24 - 80018fa: 2200 movs r2, #0 - 80018fc: 60bb str r3, [r7, #8] - 80018fe: 60fa str r2, [r7, #12] - 8001900: e9d7 2302 ldrd r2, r3, [r7, #8] - 8001904: f7fe fc3a bl 800017c <__aeabi_uldivmod> - 8001908: 4602 mov r2, r0 - 800190a: 460b mov r3, r1 - 800190c: 4613 mov r3, r2 - 800190e: 637b str r3, [r7, #52] @ 0x34 + 800192a: 6abb ldr r3, [r7, #40] @ 0x28 + 800192c: 2200 movs r2, #0 + 800192e: 469a mov sl, r3 + 8001930: 4693 mov fp, r2 + 8001932: 4652 mov r2, sl + 8001934: 465b mov r3, fp + 8001936: f04f 0000 mov.w r0, #0 + 800193a: f04f 0100 mov.w r1, #0 + 800193e: 0159 lsls r1, r3, #5 + 8001940: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8001944: 0150 lsls r0, r2, #5 + 8001946: 4602 mov r2, r0 + 8001948: 460b mov r3, r1 + 800194a: ebb2 080a subs.w r8, r2, sl + 800194e: eb63 090b sbc.w r9, r3, fp + 8001952: f04f 0200 mov.w r2, #0 + 8001956: f04f 0300 mov.w r3, #0 + 800195a: ea4f 1389 mov.w r3, r9, lsl #6 + 800195e: ea43 6398 orr.w r3, r3, r8, lsr #26 + 8001962: ea4f 1288 mov.w r2, r8, lsl #6 + 8001966: ebb2 0408 subs.w r4, r2, r8 + 800196a: eb63 0509 sbc.w r5, r3, r9 + 800196e: f04f 0200 mov.w r2, #0 + 8001972: f04f 0300 mov.w r3, #0 + 8001976: 00eb lsls r3, r5, #3 + 8001978: ea43 7354 orr.w r3, r3, r4, lsr #29 + 800197c: 00e2 lsls r2, r4, #3 + 800197e: 4614 mov r4, r2 + 8001980: 461d mov r5, r3 + 8001982: eb14 030a adds.w r3, r4, sl + 8001986: 603b str r3, [r7, #0] + 8001988: eb45 030b adc.w r3, r5, fp + 800198c: 607b str r3, [r7, #4] + 800198e: f04f 0200 mov.w r2, #0 + 8001992: f04f 0300 mov.w r3, #0 + 8001996: e9d7 4500 ldrd r4, r5, [r7] + 800199a: 4629 mov r1, r5 + 800199c: 028b lsls r3, r1, #10 + 800199e: 4620 mov r0, r4 + 80019a0: 4629 mov r1, r5 + 80019a2: 4604 mov r4, r0 + 80019a4: ea43 5394 orr.w r3, r3, r4, lsr #22 + 80019a8: 4601 mov r1, r0 + 80019aa: 028a lsls r2, r1, #10 + 80019ac: 4610 mov r0, r2 + 80019ae: 4619 mov r1, r3 + 80019b0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80019b2: 2200 movs r2, #0 + 80019b4: 60bb str r3, [r7, #8] + 80019b6: 60fa str r2, [r7, #12] + 80019b8: e9d7 2302 ldrd r2, r3, [r7, #8] + 80019bc: f7fe fbde bl 800017c <__aeabi_uldivmod> + 80019c0: 4602 mov r2, r0 + 80019c2: 460b mov r3, r1 + 80019c4: 4613 mov r3, r2 + 80019c6: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllvco; - 8001910: 6b7b ldr r3, [r7, #52] @ 0x34 - 8001912: 633b str r3, [r7, #48] @ 0x30 + 80019c8: 6b7b ldr r3, [r7, #52] @ 0x34 + 80019ca: 633b str r3, [r7, #48] @ 0x30 break; - 8001914: e00d b.n 8001932 + 80019cc: e00d b.n 80019ea } case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ default: /* MSI used as system clock */ { msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; - 8001916: 4b0a ldr r3, [pc, #40] @ (8001940 ) - 8001918: 685b ldr r3, [r3, #4] - 800191a: 0b5b lsrs r3, r3, #13 - 800191c: f003 0307 and.w r3, r3, #7 - 8001920: 623b str r3, [r7, #32] + 80019ce: 4b0a ldr r3, [pc, #40] @ (80019f8 ) + 80019d0: 685b ldr r3, [r3, #4] + 80019d2: 0b5b lsrs r3, r3, #13 + 80019d4: f003 0307 and.w r3, r3, #7 + 80019d8: 623b str r3, [r7, #32] sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); - 8001922: 6a3b ldr r3, [r7, #32] - 8001924: 3301 adds r3, #1 - 8001926: f44f 4200 mov.w r2, #32768 @ 0x8000 - 800192a: fa02 f303 lsl.w r3, r2, r3 - 800192e: 633b str r3, [r7, #48] @ 0x30 + 80019da: 6a3b ldr r3, [r7, #32] + 80019dc: 3301 adds r3, #1 + 80019de: f44f 4200 mov.w r2, #32768 @ 0x8000 + 80019e2: fa02 f303 lsl.w r3, r2, r3 + 80019e6: 633b str r3, [r7, #48] @ 0x30 break; - 8001930: bf00 nop + 80019e8: bf00 nop } } return sysclockfreq; - 8001932: 6b3b ldr r3, [r7, #48] @ 0x30 + 80019ea: 6b3b ldr r3, [r7, #48] @ 0x30 } - 8001934: 4618 mov r0, r3 - 8001936: 3738 adds r7, #56 @ 0x38 - 8001938: 46bd mov sp, r7 - 800193a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 800193e: bf00 nop - 8001940: 40023800 .word 0x40023800 - 8001944: 00f42400 .word 0x00f42400 - 8001948: 016e3600 .word 0x016e3600 - 800194c: 08001fd4 .word 0x08001fd4 + 80019ec: 4618 mov r0, r3 + 80019ee: 3738 adds r7, #56 @ 0x38 + 80019f0: 46bd mov sp, r7 + 80019f2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80019f6: bf00 nop + 80019f8: 40023800 .word 0x40023800 + 80019fc: 00f42400 .word 0x00f42400 + 8001a00: 016e3600 .word 0x016e3600 + 8001a04: 0800208c .word 0x0800208c -08001950 : +08001a08 : voltage range * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) { - 8001950: b480 push {r7} - 8001952: b087 sub sp, #28 - 8001954: af00 add r7, sp, #0 - 8001956: 6078 str r0, [r7, #4] + 8001a08: b480 push {r7} + 8001a0a: b087 sub sp, #28 + 8001a0c: af00 add r7, sp, #0 + 8001a0e: 6078 str r0, [r7, #4] uint32_t vos; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - 8001958: 2300 movs r3, #0 - 800195a: 613b str r3, [r7, #16] + 8001a10: 2300 movs r3, #0 + 8001a12: 613b str r3, [r7, #16] /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) - 800195c: 4b29 ldr r3, [pc, #164] @ (8001a04 ) - 800195e: 689b ldr r3, [r3, #8] - 8001960: f003 03f0 and.w r3, r3, #240 @ 0xf0 - 8001964: 2b00 cmp r3, #0 - 8001966: d12c bne.n 80019c2 + 8001a14: 4b29 ldr r3, [pc, #164] @ (8001abc ) + 8001a16: 689b ldr r3, [r3, #8] + 8001a18: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 8001a1c: 2b00 cmp r3, #0 + 8001a1e: d12c bne.n 8001a7a { if(__HAL_RCC_PWR_IS_CLK_ENABLED()) - 8001968: 4b26 ldr r3, [pc, #152] @ (8001a04 ) - 800196a: 6a5b ldr r3, [r3, #36] @ 0x24 - 800196c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001970: 2b00 cmp r3, #0 - 8001972: d005 beq.n 8001980 + 8001a20: 4b26 ldr r3, [pc, #152] @ (8001abc ) + 8001a22: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a24: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001a28: 2b00 cmp r3, #0 + 8001a2a: d005 beq.n 8001a38 { vos = READ_BIT(PWR->CR, PWR_CR_VOS); - 8001974: 4b24 ldr r3, [pc, #144] @ (8001a08 ) - 8001976: 681b ldr r3, [r3, #0] - 8001978: f403 53c0 and.w r3, r3, #6144 @ 0x1800 - 800197c: 617b str r3, [r7, #20] - 800197e: e016 b.n 80019ae + 8001a2c: 4b24 ldr r3, [pc, #144] @ (8001ac0 ) + 8001a2e: 681b ldr r3, [r3, #0] + 8001a30: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001a34: 617b str r3, [r7, #20] + 8001a36: e016 b.n 8001a66 } else { __HAL_RCC_PWR_CLK_ENABLE(); - 8001980: 4b20 ldr r3, [pc, #128] @ (8001a04 ) - 8001982: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001984: 4a1f ldr r2, [pc, #124] @ (8001a04 ) - 8001986: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 800198a: 6253 str r3, [r2, #36] @ 0x24 - 800198c: 4b1d ldr r3, [pc, #116] @ (8001a04 ) - 800198e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001990: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001994: 60fb str r3, [r7, #12] - 8001996: 68fb ldr r3, [r7, #12] + 8001a38: 4b20 ldr r3, [pc, #128] @ (8001abc ) + 8001a3a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a3c: 4a1f ldr r2, [pc, #124] @ (8001abc ) + 8001a3e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8001a42: 6253 str r3, [r2, #36] @ 0x24 + 8001a44: 4b1d ldr r3, [pc, #116] @ (8001abc ) + 8001a46: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a48: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001a4c: 60fb str r3, [r7, #12] + 8001a4e: 68fb ldr r3, [r7, #12] vos = READ_BIT(PWR->CR, PWR_CR_VOS); - 8001998: 4b1b ldr r3, [pc, #108] @ (8001a08 ) - 800199a: 681b ldr r3, [r3, #0] - 800199c: f403 53c0 and.w r3, r3, #6144 @ 0x1800 - 80019a0: 617b str r3, [r7, #20] + 8001a50: 4b1b ldr r3, [pc, #108] @ (8001ac0 ) + 8001a52: 681b ldr r3, [r3, #0] + 8001a54: f403 53c0 and.w r3, r3, #6144 @ 0x1800 + 8001a58: 617b str r3, [r7, #20] __HAL_RCC_PWR_CLK_DISABLE(); - 80019a2: 4b18 ldr r3, [pc, #96] @ (8001a04 ) - 80019a4: 6a5b ldr r3, [r3, #36] @ 0x24 - 80019a6: 4a17 ldr r2, [pc, #92] @ (8001a04 ) - 80019a8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 80019ac: 6253 str r3, [r2, #36] @ 0x24 + 8001a5a: 4b18 ldr r3, [pc, #96] @ (8001abc ) + 8001a5c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001a5e: 4a17 ldr r2, [pc, #92] @ (8001abc ) + 8001a60: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8001a64: 6253 str r3, [r2, #36] @ 0x24 } /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) - 80019ae: 697b ldr r3, [r7, #20] - 80019b0: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 - 80019b4: d105 bne.n 80019c2 - 80019b6: 687b ldr r3, [r7, #4] - 80019b8: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 - 80019bc: d101 bne.n 80019c2 + 8001a66: 697b ldr r3, [r7, #20] + 8001a68: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 + 8001a6c: d105 bne.n 8001a7a + 8001a6e: 687b ldr r3, [r7, #4] + 8001a70: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 + 8001a74: d101 bne.n 8001a7a { latency = FLASH_LATENCY_1; /* 1WS */ - 80019be: 2301 movs r3, #1 - 80019c0: 613b str r3, [r7, #16] + 8001a76: 2301 movs r3, #1 + 8001a78: 613b str r3, [r7, #16] } } __HAL_FLASH_SET_LATENCY(latency); - 80019c2: 693b ldr r3, [r7, #16] - 80019c4: 2b01 cmp r3, #1 - 80019c6: d105 bne.n 80019d4 - 80019c8: 4b10 ldr r3, [pc, #64] @ (8001a0c ) - 80019ca: 681b ldr r3, [r3, #0] - 80019cc: 4a0f ldr r2, [pc, #60] @ (8001a0c ) - 80019ce: f043 0304 orr.w r3, r3, #4 - 80019d2: 6013 str r3, [r2, #0] - 80019d4: 4b0d ldr r3, [pc, #52] @ (8001a0c ) - 80019d6: 681b ldr r3, [r3, #0] - 80019d8: f023 0201 bic.w r2, r3, #1 - 80019dc: 490b ldr r1, [pc, #44] @ (8001a0c ) - 80019de: 693b ldr r3, [r7, #16] - 80019e0: 4313 orrs r3, r2 - 80019e2: 600b str r3, [r1, #0] + 8001a7a: 693b ldr r3, [r7, #16] + 8001a7c: 2b01 cmp r3, #1 + 8001a7e: d105 bne.n 8001a8c + 8001a80: 4b10 ldr r3, [pc, #64] @ (8001ac4 ) + 8001a82: 681b ldr r3, [r3, #0] + 8001a84: 4a0f ldr r2, [pc, #60] @ (8001ac4 ) + 8001a86: f043 0304 orr.w r3, r3, #4 + 8001a8a: 6013 str r3, [r2, #0] + 8001a8c: 4b0d ldr r3, [pc, #52] @ (8001ac4 ) + 8001a8e: 681b ldr r3, [r3, #0] + 8001a90: f023 0201 bic.w r2, r3, #1 + 8001a94: 490b ldr r1, [pc, #44] @ (8001ac4 ) + 8001a96: 693b ldr r3, [r7, #16] + 8001a98: 4313 orrs r3, r2 + 8001a9a: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != latency) - 80019e4: 4b09 ldr r3, [pc, #36] @ (8001a0c ) - 80019e6: 681b ldr r3, [r3, #0] - 80019e8: f003 0301 and.w r3, r3, #1 - 80019ec: 693a ldr r2, [r7, #16] - 80019ee: 429a cmp r2, r3 - 80019f0: d001 beq.n 80019f6 + 8001a9c: 4b09 ldr r3, [pc, #36] @ (8001ac4 ) + 8001a9e: 681b ldr r3, [r3, #0] + 8001aa0: f003 0301 and.w r3, r3, #1 + 8001aa4: 693a ldr r2, [r7, #16] + 8001aa6: 429a cmp r2, r3 + 8001aa8: d001 beq.n 8001aae { return HAL_ERROR; - 80019f2: 2301 movs r3, #1 - 80019f4: e000 b.n 80019f8 + 8001aaa: 2301 movs r3, #1 + 8001aac: e000 b.n 8001ab0 } return HAL_OK; - 80019f6: 2300 movs r3, #0 + 8001aae: 2300 movs r3, #0 } - 80019f8: 4618 mov r0, r3 - 80019fa: 371c adds r7, #28 - 80019fc: 46bd mov sp, r7 - 80019fe: bc80 pop {r7} - 8001a00: 4770 bx lr - 8001a02: bf00 nop - 8001a04: 40023800 .word 0x40023800 - 8001a08: 40007000 .word 0x40007000 - 8001a0c: 40023c00 .word 0x40023c00 + 8001ab0: 4618 mov r0, r3 + 8001ab2: 371c adds r7, #28 + 8001ab4: 46bd mov sp, r7 + 8001ab6: bc80 pop {r7} + 8001ab8: 4770 bx lr + 8001aba: bf00 nop + 8001abc: 40023800 .word 0x40023800 + 8001ac0: 40007000 .word 0x40007000 + 8001ac4: 40023c00 .word 0x40023c00 -08001a10 : +08001ac8 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { - 8001a10: b580 push {r7, lr} - 8001a12: b082 sub sp, #8 - 8001a14: af00 add r7, sp, #0 - 8001a16: 6078 str r0, [r7, #4] + 8001ac8: b580 push {r7, lr} + 8001aca: b082 sub sp, #8 + 8001acc: af00 add r7, sp, #0 + 8001ace: 6078 str r0, [r7, #4] /* Check the SPI handle allocation */ if (hspi == NULL) - 8001a18: 687b ldr r3, [r7, #4] - 8001a1a: 2b00 cmp r3, #0 - 8001a1c: d101 bne.n 8001a22 + 8001ad0: 687b ldr r3, [r7, #4] + 8001ad2: 2b00 cmp r3, #0 + 8001ad4: d101 bne.n 8001ada { return HAL_ERROR; - 8001a1e: 2301 movs r3, #1 - 8001a20: e07b b.n 8001b1a + 8001ad6: 2301 movs r3, #1 + 8001ad8: e07b b.n 8001bd2 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); /* TI mode is not supported on all devices in stm32l1xx series. TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) - 8001a22: 687b ldr r3, [r7, #4] - 8001a24: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001a26: 2b00 cmp r3, #0 - 8001a28: d108 bne.n 8001a3c + 8001ada: 687b ldr r3, [r7, #4] + 8001adc: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ade: 2b00 cmp r3, #0 + 8001ae0: d108 bne.n 8001af4 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) - 8001a2a: 687b ldr r3, [r7, #4] - 8001a2c: 685b ldr r3, [r3, #4] - 8001a2e: f5b3 7f82 cmp.w r3, #260 @ 0x104 - 8001a32: d009 beq.n 8001a48 + 8001ae2: 687b ldr r3, [r7, #4] + 8001ae4: 685b ldr r3, [r3, #4] + 8001ae6: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001aea: d009 beq.n 8001b00 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; - 8001a34: 687b ldr r3, [r7, #4] - 8001a36: 2200 movs r2, #0 - 8001a38: 61da str r2, [r3, #28] - 8001a3a: e005 b.n 8001a48 + 8001aec: 687b ldr r3, [r7, #4] + 8001aee: 2200 movs r2, #0 + 8001af0: 61da str r2, [r3, #28] + 8001af2: e005 b.n 8001b00 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; - 8001a3c: 687b ldr r3, [r7, #4] - 8001a3e: 2200 movs r2, #0 - 8001a40: 611a str r2, [r3, #16] + 8001af4: 687b ldr r3, [r7, #4] + 8001af6: 2200 movs r2, #0 + 8001af8: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; - 8001a42: 687b ldr r3, [r7, #4] - 8001a44: 2200 movs r2, #0 - 8001a46: 615a str r2, [r3, #20] + 8001afa: 687b ldr r3, [r7, #4] + 8001afc: 2200 movs r2, #0 + 8001afe: 615a str r2, [r3, #20] if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - 8001a48: 687b ldr r3, [r7, #4] - 8001a4a: 2200 movs r2, #0 - 8001a4c: 629a str r2, [r3, #40] @ 0x28 + 8001b00: 687b ldr r3, [r7, #4] + 8001b02: 2200 movs r2, #0 + 8001b04: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) - 8001a4e: 687b ldr r3, [r7, #4] - 8001a50: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 - 8001a54: b2db uxtb r3, r3 - 8001a56: 2b00 cmp r3, #0 - 8001a58: d106 bne.n 8001a68 + 8001b06: 687b ldr r3, [r7, #4] + 8001b08: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001b0c: b2db uxtb r3, r3 + 8001b0e: 2b00 cmp r3, #0 + 8001b10: d106 bne.n 8001b20 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; - 8001a5a: 687b ldr r3, [r7, #4] - 8001a5c: 2200 movs r2, #0 - 8001a5e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + 8001b12: 687b ldr r3, [r7, #4] + 8001b14: 2200 movs r2, #0 + 8001b16: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); - 8001a62: 6878 ldr r0, [r7, #4] - 8001a64: f7fe fe2a bl 80006bc + 8001b1a: 6878 ldr r0, [r7, #4] + 8001b1c: f7fe fe08 bl 8000730 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; - 8001a68: 687b ldr r3, [r7, #4] - 8001a6a: 2202 movs r2, #2 - 8001a6c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + 8001b20: 687b ldr r3, [r7, #4] + 8001b22: 2202 movs r2, #2 + 8001b24: f883 2051 strb.w r2, [r3, #81] @ 0x51 /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); - 8001a70: 687b ldr r3, [r7, #4] - 8001a72: 681b ldr r3, [r3, #0] - 8001a74: 681a ldr r2, [r3, #0] - 8001a76: 687b ldr r3, [r7, #4] - 8001a78: 681b ldr r3, [r3, #0] - 8001a7a: f022 0240 bic.w r2, r2, #64 @ 0x40 - 8001a7e: 601a str r2, [r3, #0] + 8001b28: 687b ldr r3, [r7, #4] + 8001b2a: 681b ldr r3, [r3, #0] + 8001b2c: 681a ldr r2, [r3, #0] + 8001b2e: 687b ldr r3, [r7, #4] + 8001b30: 681b ldr r3, [r3, #0] + 8001b32: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001b36: 601a str r2, [r3, #0] /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | - 8001a80: 687b ldr r3, [r7, #4] - 8001a82: 685b ldr r3, [r3, #4] - 8001a84: f403 7282 and.w r2, r3, #260 @ 0x104 - 8001a88: 687b ldr r3, [r7, #4] - 8001a8a: 689b ldr r3, [r3, #8] - 8001a8c: f403 4304 and.w r3, r3, #33792 @ 0x8400 - 8001a90: 431a orrs r2, r3 - 8001a92: 687b ldr r3, [r7, #4] - 8001a94: 68db ldr r3, [r3, #12] - 8001a96: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8001a9a: 431a orrs r2, r3 - 8001a9c: 687b ldr r3, [r7, #4] - 8001a9e: 691b ldr r3, [r3, #16] - 8001aa0: f003 0302 and.w r3, r3, #2 - 8001aa4: 431a orrs r2, r3 - 8001aa6: 687b ldr r3, [r7, #4] - 8001aa8: 695b ldr r3, [r3, #20] - 8001aaa: f003 0301 and.w r3, r3, #1 - 8001aae: 431a orrs r2, r3 - 8001ab0: 687b ldr r3, [r7, #4] - 8001ab2: 699b ldr r3, [r3, #24] - 8001ab4: f403 7300 and.w r3, r3, #512 @ 0x200 - 8001ab8: 431a orrs r2, r3 - 8001aba: 687b ldr r3, [r7, #4] - 8001abc: 69db ldr r3, [r3, #28] - 8001abe: f003 0338 and.w r3, r3, #56 @ 0x38 - 8001ac2: 431a orrs r2, r3 - 8001ac4: 687b ldr r3, [r7, #4] - 8001ac6: 6a1b ldr r3, [r3, #32] - 8001ac8: f003 0380 and.w r3, r3, #128 @ 0x80 - 8001acc: ea42 0103 orr.w r1, r2, r3 - 8001ad0: 687b ldr r3, [r7, #4] - 8001ad2: 6a9b ldr r3, [r3, #40] @ 0x28 - 8001ad4: f403 5200 and.w r2, r3, #8192 @ 0x2000 - 8001ad8: 687b ldr r3, [r7, #4] - 8001ada: 681b ldr r3, [r3, #0] - 8001adc: 430a orrs r2, r1 - 8001ade: 601a str r2, [r3, #0] + 8001b38: 687b ldr r3, [r7, #4] + 8001b3a: 685b ldr r3, [r3, #4] + 8001b3c: f403 7282 and.w r2, r3, #260 @ 0x104 + 8001b40: 687b ldr r3, [r7, #4] + 8001b42: 689b ldr r3, [r3, #8] + 8001b44: f403 4304 and.w r3, r3, #33792 @ 0x8400 + 8001b48: 431a orrs r2, r3 + 8001b4a: 687b ldr r3, [r7, #4] + 8001b4c: 68db ldr r3, [r3, #12] + 8001b4e: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8001b52: 431a orrs r2, r3 + 8001b54: 687b ldr r3, [r7, #4] + 8001b56: 691b ldr r3, [r3, #16] + 8001b58: f003 0302 and.w r3, r3, #2 + 8001b5c: 431a orrs r2, r3 + 8001b5e: 687b ldr r3, [r7, #4] + 8001b60: 695b ldr r3, [r3, #20] + 8001b62: f003 0301 and.w r3, r3, #1 + 8001b66: 431a orrs r2, r3 + 8001b68: 687b ldr r3, [r7, #4] + 8001b6a: 699b ldr r3, [r3, #24] + 8001b6c: f403 7300 and.w r3, r3, #512 @ 0x200 + 8001b70: 431a orrs r2, r3 + 8001b72: 687b ldr r3, [r7, #4] + 8001b74: 69db ldr r3, [r3, #28] + 8001b76: f003 0338 and.w r3, r3, #56 @ 0x38 + 8001b7a: 431a orrs r2, r3 + 8001b7c: 687b ldr r3, [r7, #4] + 8001b7e: 6a1b ldr r3, [r3, #32] + 8001b80: f003 0380 and.w r3, r3, #128 @ 0x80 + 8001b84: ea42 0103 orr.w r1, r2, r3 + 8001b88: 687b ldr r3, [r7, #4] + 8001b8a: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001b8c: f403 5200 and.w r2, r3, #8192 @ 0x2000 + 8001b90: 687b ldr r3, [r7, #4] + 8001b92: 681b ldr r3, [r3, #0] + 8001b94: 430a orrs r2, r1 + 8001b96: 601a str r2, [r3, #0] (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); #if defined(SPI_CR2_FRF) /* Configure : NSS management, TI Mode */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); - 8001ae0: 687b ldr r3, [r7, #4] - 8001ae2: 699b ldr r3, [r3, #24] - 8001ae4: 0c1b lsrs r3, r3, #16 - 8001ae6: f003 0104 and.w r1, r3, #4 - 8001aea: 687b ldr r3, [r7, #4] - 8001aec: 6a5b ldr r3, [r3, #36] @ 0x24 - 8001aee: f003 0210 and.w r2, r3, #16 - 8001af2: 687b ldr r3, [r7, #4] - 8001af4: 681b ldr r3, [r3, #0] - 8001af6: 430a orrs r2, r1 - 8001af8: 605a str r2, [r3, #4] + 8001b98: 687b ldr r3, [r7, #4] + 8001b9a: 699b ldr r3, [r3, #24] + 8001b9c: 0c1b lsrs r3, r3, #16 + 8001b9e: f003 0104 and.w r1, r3, #4 + 8001ba2: 687b ldr r3, [r7, #4] + 8001ba4: 6a5b ldr r3, [r3, #36] @ 0x24 + 8001ba6: f003 0210 and.w r2, r3, #16 + 8001baa: 687b ldr r3, [r7, #4] + 8001bac: 681b ldr r3, [r3, #0] + 8001bae: 430a orrs r2, r1 + 8001bb0: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); - 8001afa: 687b ldr r3, [r7, #4] - 8001afc: 681b ldr r3, [r3, #0] - 8001afe: 69da ldr r2, [r3, #28] - 8001b00: 687b ldr r3, [r7, #4] - 8001b02: 681b ldr r3, [r3, #0] - 8001b04: f422 6200 bic.w r2, r2, #2048 @ 0x800 - 8001b08: 61da str r2, [r3, #28] + 8001bb2: 687b ldr r3, [r7, #4] + 8001bb4: 681b ldr r3, [r3, #0] + 8001bb6: 69da ldr r2, [r3, #28] + 8001bb8: 687b ldr r3, [r7, #4] + 8001bba: 681b ldr r3, [r3, #0] + 8001bbc: f422 6200 bic.w r2, r2, #2048 @ 0x800 + 8001bc0: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - 8001b0a: 687b ldr r3, [r7, #4] - 8001b0c: 2200 movs r2, #0 - 8001b0e: 655a str r2, [r3, #84] @ 0x54 + 8001bc2: 687b ldr r3, [r7, #4] + 8001bc4: 2200 movs r2, #0 + 8001bc6: 655a str r2, [r3, #84] @ 0x54 hspi->State = HAL_SPI_STATE_READY; - 8001b10: 687b ldr r3, [r7, #4] - 8001b12: 2201 movs r2, #1 - 8001b14: f883 2051 strb.w r2, [r3, #81] @ 0x51 + 8001bc8: 687b ldr r3, [r7, #4] + 8001bca: 2201 movs r2, #1 + 8001bcc: f883 2051 strb.w r2, [r3, #81] @ 0x51 return HAL_OK; - 8001b18: 2300 movs r3, #0 + 8001bd0: 2300 movs r3, #0 } - 8001b1a: 4618 mov r0, r3 - 8001b1c: 3708 adds r7, #8 - 8001b1e: 46bd mov sp, r7 - 8001b20: bd80 pop {r7, pc} + 8001bd2: 4618 mov r0, r3 + 8001bd4: 3708 adds r7, #8 + 8001bd6: 46bd mov sp, r7 + 8001bd8: bd80 pop {r7, pc} -08001b22 : +08001bda : * @param Size amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 8001b22: b580 push {r7, lr} - 8001b24: b088 sub sp, #32 - 8001b26: af00 add r7, sp, #0 - 8001b28: 60f8 str r0, [r7, #12] - 8001b2a: 60b9 str r1, [r7, #8] - 8001b2c: 603b str r3, [r7, #0] - 8001b2e: 4613 mov r3, r2 - 8001b30: 80fb strh r3, [r7, #6] + 8001bda: b580 push {r7, lr} + 8001bdc: b088 sub sp, #32 + 8001bde: af00 add r7, sp, #0 + 8001be0: 60f8 str r0, [r7, #12] + 8001be2: 60b9 str r1, [r7, #8] + 8001be4: 603b str r3, [r7, #0] + 8001be6: 4613 mov r3, r2 + 8001be8: 80fb strh r3, [r7, #6] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - 8001b32: f7fe ff55 bl 80009e0 - 8001b36: 61f8 str r0, [r7, #28] + 8001bea: f7fe ff33 bl 8000a54 + 8001bee: 61f8 str r0, [r7, #28] initial_TxXferCount = Size; - 8001b38: 88fb ldrh r3, [r7, #6] - 8001b3a: 837b strh r3, [r7, #26] + 8001bf0: 88fb ldrh r3, [r7, #6] + 8001bf2: 837b strh r3, [r7, #26] if (hspi->State != HAL_SPI_STATE_READY) - 8001b3c: 68fb ldr r3, [r7, #12] - 8001b3e: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 - 8001b42: b2db uxtb r3, r3 - 8001b44: 2b01 cmp r3, #1 - 8001b46: d001 beq.n 8001b4c + 8001bf4: 68fb ldr r3, [r7, #12] + 8001bf6: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 + 8001bfa: b2db uxtb r3, r3 + 8001bfc: 2b01 cmp r3, #1 + 8001bfe: d001 beq.n 8001c04 { return HAL_BUSY; - 8001b48: 2302 movs r3, #2 - 8001b4a: e12a b.n 8001da2 + 8001c00: 2302 movs r3, #2 + 8001c02: e12a b.n 8001e5a } if ((pData == NULL) || (Size == 0U)) - 8001b4c: 68bb ldr r3, [r7, #8] - 8001b4e: 2b00 cmp r3, #0 - 8001b50: d002 beq.n 8001b58 - 8001b52: 88fb ldrh r3, [r7, #6] - 8001b54: 2b00 cmp r3, #0 - 8001b56: d101 bne.n 8001b5c + 8001c04: 68bb ldr r3, [r7, #8] + 8001c06: 2b00 cmp r3, #0 + 8001c08: d002 beq.n 8001c10 + 8001c0a: 88fb ldrh r3, [r7, #6] + 8001c0c: 2b00 cmp r3, #0 + 8001c0e: d101 bne.n 8001c14 { return HAL_ERROR; - 8001b58: 2301 movs r3, #1 - 8001b5a: e122 b.n 8001da2 + 8001c10: 2301 movs r3, #1 + 8001c12: e122 b.n 8001e5a } /* Process Locked */ __HAL_LOCK(hspi); - 8001b5c: 68fb ldr r3, [r7, #12] - 8001b5e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 - 8001b62: 2b01 cmp r3, #1 - 8001b64: d101 bne.n 8001b6a - 8001b66: 2302 movs r3, #2 - 8001b68: e11b b.n 8001da2 - 8001b6a: 68fb ldr r3, [r7, #12] - 8001b6c: 2201 movs r2, #1 - 8001b6e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + 8001c14: 68fb ldr r3, [r7, #12] + 8001c16: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 + 8001c1a: 2b01 cmp r3, #1 + 8001c1c: d101 bne.n 8001c22 + 8001c1e: 2302 movs r3, #2 + 8001c20: e11b b.n 8001e5a + 8001c22: 68fb ldr r3, [r7, #12] + 8001c24: 2201 movs r2, #1 + 8001c26: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; - 8001b72: 68fb ldr r3, [r7, #12] - 8001b74: 2203 movs r2, #3 - 8001b76: f883 2051 strb.w r2, [r3, #81] @ 0x51 + 8001c2a: 68fb ldr r3, [r7, #12] + 8001c2c: 2203 movs r2, #3 + 8001c2e: f883 2051 strb.w r2, [r3, #81] @ 0x51 hspi->ErrorCode = HAL_SPI_ERROR_NONE; - 8001b7a: 68fb ldr r3, [r7, #12] - 8001b7c: 2200 movs r2, #0 - 8001b7e: 655a str r2, [r3, #84] @ 0x54 + 8001c32: 68fb ldr r3, [r7, #12] + 8001c34: 2200 movs r2, #0 + 8001c36: 655a str r2, [r3, #84] @ 0x54 hspi->pTxBuffPtr = (const uint8_t *)pData; - 8001b80: 68fb ldr r3, [r7, #12] - 8001b82: 68ba ldr r2, [r7, #8] - 8001b84: 631a str r2, [r3, #48] @ 0x30 + 8001c38: 68fb ldr r3, [r7, #12] + 8001c3a: 68ba ldr r2, [r7, #8] + 8001c3c: 631a str r2, [r3, #48] @ 0x30 hspi->TxXferSize = Size; - 8001b86: 68fb ldr r3, [r7, #12] - 8001b88: 88fa ldrh r2, [r7, #6] - 8001b8a: 869a strh r2, [r3, #52] @ 0x34 + 8001c3e: 68fb ldr r3, [r7, #12] + 8001c40: 88fa ldrh r2, [r7, #6] + 8001c42: 869a strh r2, [r3, #52] @ 0x34 hspi->TxXferCount = Size; - 8001b8c: 68fb ldr r3, [r7, #12] - 8001b8e: 88fa ldrh r2, [r7, #6] - 8001b90: 86da strh r2, [r3, #54] @ 0x36 + 8001c44: 68fb ldr r3, [r7, #12] + 8001c46: 88fa ldrh r2, [r7, #6] + 8001c48: 86da strh r2, [r3, #54] @ 0x36 /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; - 8001b92: 68fb ldr r3, [r7, #12] - 8001b94: 2200 movs r2, #0 - 8001b96: 639a str r2, [r3, #56] @ 0x38 + 8001c4a: 68fb ldr r3, [r7, #12] + 8001c4c: 2200 movs r2, #0 + 8001c4e: 639a str r2, [r3, #56] @ 0x38 hspi->RxXferSize = 0U; - 8001b98: 68fb ldr r3, [r7, #12] - 8001b9a: 2200 movs r2, #0 - 8001b9c: 879a strh r2, [r3, #60] @ 0x3c + 8001c50: 68fb ldr r3, [r7, #12] + 8001c52: 2200 movs r2, #0 + 8001c54: 879a strh r2, [r3, #60] @ 0x3c hspi->RxXferCount = 0U; - 8001b9e: 68fb ldr r3, [r7, #12] - 8001ba0: 2200 movs r2, #0 - 8001ba2: 87da strh r2, [r3, #62] @ 0x3e + 8001c56: 68fb ldr r3, [r7, #12] + 8001c58: 2200 movs r2, #0 + 8001c5a: 87da strh r2, [r3, #62] @ 0x3e hspi->TxISR = NULL; - 8001ba4: 68fb ldr r3, [r7, #12] - 8001ba6: 2200 movs r2, #0 - 8001ba8: 645a str r2, [r3, #68] @ 0x44 + 8001c5c: 68fb ldr r3, [r7, #12] + 8001c5e: 2200 movs r2, #0 + 8001c60: 645a str r2, [r3, #68] @ 0x44 hspi->RxISR = NULL; - 8001baa: 68fb ldr r3, [r7, #12] - 8001bac: 2200 movs r2, #0 - 8001bae: 641a str r2, [r3, #64] @ 0x40 + 8001c62: 68fb ldr r3, [r7, #12] + 8001c64: 2200 movs r2, #0 + 8001c66: 641a str r2, [r3, #64] @ 0x40 /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - 8001bb0: 68fb ldr r3, [r7, #12] - 8001bb2: 689b ldr r3, [r3, #8] - 8001bb4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 - 8001bb8: d10f bne.n 8001bda + 8001c68: 68fb ldr r3, [r7, #12] + 8001c6a: 689b ldr r3, [r3, #8] + 8001c6c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001c70: d10f bne.n 8001c92 { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); - 8001bba: 68fb ldr r3, [r7, #12] - 8001bbc: 681b ldr r3, [r3, #0] - 8001bbe: 681a ldr r2, [r3, #0] - 8001bc0: 68fb ldr r3, [r7, #12] - 8001bc2: 681b ldr r3, [r3, #0] - 8001bc4: f022 0240 bic.w r2, r2, #64 @ 0x40 - 8001bc8: 601a str r2, [r3, #0] + 8001c72: 68fb ldr r3, [r7, #12] + 8001c74: 681b ldr r3, [r3, #0] + 8001c76: 681a ldr r2, [r3, #0] + 8001c78: 68fb ldr r3, [r7, #12] + 8001c7a: 681b ldr r3, [r3, #0] + 8001c7c: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001c80: 601a str r2, [r3, #0] SPI_1LINE_TX(hspi); - 8001bca: 68fb ldr r3, [r7, #12] - 8001bcc: 681b ldr r3, [r3, #0] - 8001bce: 681a ldr r2, [r3, #0] - 8001bd0: 68fb ldr r3, [r7, #12] - 8001bd2: 681b ldr r3, [r3, #0] - 8001bd4: f442 4280 orr.w r2, r2, #16384 @ 0x4000 - 8001bd8: 601a str r2, [r3, #0] + 8001c82: 68fb ldr r3, [r7, #12] + 8001c84: 681b ldr r3, [r3, #0] + 8001c86: 681a ldr r2, [r3, #0] + 8001c88: 68fb ldr r3, [r7, #12] + 8001c8a: 681b ldr r3, [r3, #0] + 8001c8c: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8001c90: 601a str r2, [r3, #0] SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - 8001bda: 68fb ldr r3, [r7, #12] - 8001bdc: 681b ldr r3, [r3, #0] - 8001bde: 681b ldr r3, [r3, #0] - 8001be0: f003 0340 and.w r3, r3, #64 @ 0x40 - 8001be4: 2b40 cmp r3, #64 @ 0x40 - 8001be6: d007 beq.n 8001bf8 + 8001c92: 68fb ldr r3, [r7, #12] + 8001c94: 681b ldr r3, [r3, #0] + 8001c96: 681b ldr r3, [r3, #0] + 8001c98: f003 0340 and.w r3, r3, #64 @ 0x40 + 8001c9c: 2b40 cmp r3, #64 @ 0x40 + 8001c9e: d007 beq.n 8001cb0 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); - 8001be8: 68fb ldr r3, [r7, #12] - 8001bea: 681b ldr r3, [r3, #0] - 8001bec: 681a ldr r2, [r3, #0] - 8001bee: 68fb ldr r3, [r7, #12] - 8001bf0: 681b ldr r3, [r3, #0] - 8001bf2: f042 0240 orr.w r2, r2, #64 @ 0x40 - 8001bf6: 601a str r2, [r3, #0] + 8001ca0: 68fb ldr r3, [r7, #12] + 8001ca2: 681b ldr r3, [r3, #0] + 8001ca4: 681a ldr r2, [r3, #0] + 8001ca6: 68fb ldr r3, [r7, #12] + 8001ca8: 681b ldr r3, [r3, #0] + 8001caa: f042 0240 orr.w r2, r2, #64 @ 0x40 + 8001cae: 601a str r2, [r3, #0] } /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) - 8001bf8: 68fb ldr r3, [r7, #12] - 8001bfa: 68db ldr r3, [r3, #12] - 8001bfc: f5b3 6f00 cmp.w r3, #2048 @ 0x800 - 8001c00: d152 bne.n 8001ca8 + 8001cb0: 68fb ldr r3, [r7, #12] + 8001cb2: 68db ldr r3, [r3, #12] + 8001cb4: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8001cb8: d152 bne.n 8001d60 { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - 8001c02: 68fb ldr r3, [r7, #12] - 8001c04: 685b ldr r3, [r3, #4] - 8001c06: 2b00 cmp r3, #0 - 8001c08: d002 beq.n 8001c10 - 8001c0a: 8b7b ldrh r3, [r7, #26] - 8001c0c: 2b01 cmp r3, #1 - 8001c0e: d145 bne.n 8001c9c + 8001cba: 68fb ldr r3, [r7, #12] + 8001cbc: 685b ldr r3, [r3, #4] + 8001cbe: 2b00 cmp r3, #0 + 8001cc0: d002 beq.n 8001cc8 + 8001cc2: 8b7b ldrh r3, [r7, #26] + 8001cc4: 2b01 cmp r3, #1 + 8001cc6: d145 bne.n 8001d54 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); - 8001c10: 68fb ldr r3, [r7, #12] - 8001c12: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001c14: 881a ldrh r2, [r3, #0] - 8001c16: 68fb ldr r3, [r7, #12] - 8001c18: 681b ldr r3, [r3, #0] - 8001c1a: 60da str r2, [r3, #12] + 8001cc8: 68fb ldr r3, [r7, #12] + 8001cca: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001ccc: 881a ldrh r2, [r3, #0] + 8001cce: 68fb ldr r3, [r7, #12] + 8001cd0: 681b ldr r3, [r3, #0] + 8001cd2: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); - 8001c1c: 68fb ldr r3, [r7, #12] - 8001c1e: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001c20: 1c9a adds r2, r3, #2 - 8001c22: 68fb ldr r3, [r7, #12] - 8001c24: 631a str r2, [r3, #48] @ 0x30 + 8001cd4: 68fb ldr r3, [r7, #12] + 8001cd6: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001cd8: 1c9a adds r2, r3, #2 + 8001cda: 68fb ldr r3, [r7, #12] + 8001cdc: 631a str r2, [r3, #48] @ 0x30 hspi->TxXferCount--; - 8001c26: 68fb ldr r3, [r7, #12] - 8001c28: 8edb ldrh r3, [r3, #54] @ 0x36 - 8001c2a: b29b uxth r3, r3 - 8001c2c: 3b01 subs r3, #1 - 8001c2e: b29a uxth r2, r3 - 8001c30: 68fb ldr r3, [r7, #12] - 8001c32: 86da strh r2, [r3, #54] @ 0x36 + 8001cde: 68fb ldr r3, [r7, #12] + 8001ce0: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001ce2: b29b uxth r3, r3 + 8001ce4: 3b01 subs r3, #1 + 8001ce6: b29a uxth r2, r3 + 8001ce8: 68fb ldr r3, [r7, #12] + 8001cea: 86da strh r2, [r3, #54] @ 0x36 } /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0U) - 8001c34: e032 b.n 8001c9c + 8001cec: e032 b.n 8001d54 { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) - 8001c36: 68fb ldr r3, [r7, #12] - 8001c38: 681b ldr r3, [r3, #0] - 8001c3a: 689b ldr r3, [r3, #8] - 8001c3c: f003 0302 and.w r3, r3, #2 - 8001c40: 2b02 cmp r3, #2 - 8001c42: d112 bne.n 8001c6a + 8001cee: 68fb ldr r3, [r7, #12] + 8001cf0: 681b ldr r3, [r3, #0] + 8001cf2: 689b ldr r3, [r3, #8] + 8001cf4: f003 0302 and.w r3, r3, #2 + 8001cf8: 2b02 cmp r3, #2 + 8001cfa: d112 bne.n 8001d22 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); - 8001c44: 68fb ldr r3, [r7, #12] - 8001c46: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001c48: 881a ldrh r2, [r3, #0] - 8001c4a: 68fb ldr r3, [r7, #12] - 8001c4c: 681b ldr r3, [r3, #0] - 8001c4e: 60da str r2, [r3, #12] + 8001cfc: 68fb ldr r3, [r7, #12] + 8001cfe: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d00: 881a ldrh r2, [r3, #0] + 8001d02: 68fb ldr r3, [r7, #12] + 8001d04: 681b ldr r3, [r3, #0] + 8001d06: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); - 8001c50: 68fb ldr r3, [r7, #12] - 8001c52: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001c54: 1c9a adds r2, r3, #2 - 8001c56: 68fb ldr r3, [r7, #12] - 8001c58: 631a str r2, [r3, #48] @ 0x30 + 8001d08: 68fb ldr r3, [r7, #12] + 8001d0a: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d0c: 1c9a adds r2, r3, #2 + 8001d0e: 68fb ldr r3, [r7, #12] + 8001d10: 631a str r2, [r3, #48] @ 0x30 hspi->TxXferCount--; - 8001c5a: 68fb ldr r3, [r7, #12] - 8001c5c: 8edb ldrh r3, [r3, #54] @ 0x36 - 8001c5e: b29b uxth r3, r3 - 8001c60: 3b01 subs r3, #1 - 8001c62: b29a uxth r2, r3 - 8001c64: 68fb ldr r3, [r7, #12] - 8001c66: 86da strh r2, [r3, #54] @ 0x36 - 8001c68: e018 b.n 8001c9c + 8001d12: 68fb ldr r3, [r7, #12] + 8001d14: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d16: b29b uxth r3, r3 + 8001d18: 3b01 subs r3, #1 + 8001d1a: b29a uxth r2, r3 + 8001d1c: 68fb ldr r3, [r7, #12] + 8001d1e: 86da strh r2, [r3, #54] @ 0x36 + 8001d20: e018 b.n 8001d54 } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - 8001c6a: f7fe feb9 bl 80009e0 - 8001c6e: 4602 mov r2, r0 - 8001c70: 69fb ldr r3, [r7, #28] - 8001c72: 1ad3 subs r3, r2, r3 - 8001c74: 683a ldr r2, [r7, #0] - 8001c76: 429a cmp r2, r3 - 8001c78: d803 bhi.n 8001c82 - 8001c7a: 683b ldr r3, [r7, #0] - 8001c7c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8001c80: d102 bne.n 8001c88 - 8001c82: 683b ldr r3, [r7, #0] - 8001c84: 2b00 cmp r3, #0 - 8001c86: d109 bne.n 8001c9c + 8001d22: f7fe fe97 bl 8000a54 + 8001d26: 4602 mov r2, r0 + 8001d28: 69fb ldr r3, [r7, #28] + 8001d2a: 1ad3 subs r3, r2, r3 + 8001d2c: 683a ldr r2, [r7, #0] + 8001d2e: 429a cmp r2, r3 + 8001d30: d803 bhi.n 8001d3a + 8001d32: 683b ldr r3, [r7, #0] + 8001d34: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001d38: d102 bne.n 8001d40 + 8001d3a: 683b ldr r3, [r7, #0] + 8001d3c: 2b00 cmp r3, #0 + 8001d3e: d109 bne.n 8001d54 { hspi->State = HAL_SPI_STATE_READY; - 8001c88: 68fb ldr r3, [r7, #12] - 8001c8a: 2201 movs r2, #1 - 8001c8c: f883 2051 strb.w r2, [r3, #81] @ 0x51 + 8001d40: 68fb ldr r3, [r7, #12] + 8001d42: 2201 movs r2, #1 + 8001d44: f883 2051 strb.w r2, [r3, #81] @ 0x51 __HAL_UNLOCK(hspi); - 8001c90: 68fb ldr r3, [r7, #12] - 8001c92: 2200 movs r2, #0 - 8001c94: f883 2050 strb.w r2, [r3, #80] @ 0x50 + 8001d48: 68fb ldr r3, [r7, #12] + 8001d4a: 2200 movs r2, #0 + 8001d4c: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_TIMEOUT; - 8001c98: 2303 movs r3, #3 - 8001c9a: e082 b.n 8001da2 + 8001d50: 2303 movs r3, #3 + 8001d52: e082 b.n 8001e5a while (hspi->TxXferCount > 0U) - 8001c9c: 68fb ldr r3, [r7, #12] - 8001c9e: 8edb ldrh r3, [r3, #54] @ 0x36 - 8001ca0: b29b uxth r3, r3 - 8001ca2: 2b00 cmp r3, #0 - 8001ca4: d1c7 bne.n 8001c36 - 8001ca6: e053 b.n 8001d50 + 8001d54: 68fb ldr r3, [r7, #12] + 8001d56: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d58: b29b uxth r3, r3 + 8001d5a: 2b00 cmp r3, #0 + 8001d5c: d1c7 bne.n 8001cee + 8001d5e: e053 b.n 8001e08 } } /* Transmit data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - 8001ca8: 68fb ldr r3, [r7, #12] - 8001caa: 685b ldr r3, [r3, #4] - 8001cac: 2b00 cmp r3, #0 - 8001cae: d002 beq.n 8001cb6 - 8001cb0: 8b7b ldrh r3, [r7, #26] - 8001cb2: 2b01 cmp r3, #1 - 8001cb4: d147 bne.n 8001d46 + 8001d60: 68fb ldr r3, [r7, #12] + 8001d62: 685b ldr r3, [r3, #4] + 8001d64: 2b00 cmp r3, #0 + 8001d66: d002 beq.n 8001d6e + 8001d68: 8b7b ldrh r3, [r7, #26] + 8001d6a: 2b01 cmp r3, #1 + 8001d6c: d147 bne.n 8001dfe { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); - 8001cb6: 68fb ldr r3, [r7, #12] - 8001cb8: 6b1a ldr r2, [r3, #48] @ 0x30 - 8001cba: 68fb ldr r3, [r7, #12] - 8001cbc: 681b ldr r3, [r3, #0] - 8001cbe: 330c adds r3, #12 - 8001cc0: 7812 ldrb r2, [r2, #0] - 8001cc2: 701a strb r2, [r3, #0] + 8001d6e: 68fb ldr r3, [r7, #12] + 8001d70: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001d72: 68fb ldr r3, [r7, #12] + 8001d74: 681b ldr r3, [r3, #0] + 8001d76: 330c adds r3, #12 + 8001d78: 7812 ldrb r2, [r2, #0] + 8001d7a: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); - 8001cc4: 68fb ldr r3, [r7, #12] - 8001cc6: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001cc8: 1c5a adds r2, r3, #1 - 8001cca: 68fb ldr r3, [r7, #12] - 8001ccc: 631a str r2, [r3, #48] @ 0x30 + 8001d7c: 68fb ldr r3, [r7, #12] + 8001d7e: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001d80: 1c5a adds r2, r3, #1 + 8001d82: 68fb ldr r3, [r7, #12] + 8001d84: 631a str r2, [r3, #48] @ 0x30 hspi->TxXferCount--; - 8001cce: 68fb ldr r3, [r7, #12] - 8001cd0: 8edb ldrh r3, [r3, #54] @ 0x36 - 8001cd2: b29b uxth r3, r3 - 8001cd4: 3b01 subs r3, #1 - 8001cd6: b29a uxth r2, r3 - 8001cd8: 68fb ldr r3, [r7, #12] - 8001cda: 86da strh r2, [r3, #54] @ 0x36 + 8001d86: 68fb ldr r3, [r7, #12] + 8001d88: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001d8a: b29b uxth r3, r3 + 8001d8c: 3b01 subs r3, #1 + 8001d8e: b29a uxth r2, r3 + 8001d90: 68fb ldr r3, [r7, #12] + 8001d92: 86da strh r2, [r3, #54] @ 0x36 } while (hspi->TxXferCount > 0U) - 8001cdc: e033 b.n 8001d46 + 8001d94: e033 b.n 8001dfe { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) - 8001cde: 68fb ldr r3, [r7, #12] - 8001ce0: 681b ldr r3, [r3, #0] - 8001ce2: 689b ldr r3, [r3, #8] - 8001ce4: f003 0302 and.w r3, r3, #2 - 8001ce8: 2b02 cmp r3, #2 - 8001cea: d113 bne.n 8001d14 + 8001d96: 68fb ldr r3, [r7, #12] + 8001d98: 681b ldr r3, [r3, #0] + 8001d9a: 689b ldr r3, [r3, #8] + 8001d9c: f003 0302 and.w r3, r3, #2 + 8001da0: 2b02 cmp r3, #2 + 8001da2: d113 bne.n 8001dcc { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); - 8001cec: 68fb ldr r3, [r7, #12] - 8001cee: 6b1a ldr r2, [r3, #48] @ 0x30 - 8001cf0: 68fb ldr r3, [r7, #12] - 8001cf2: 681b ldr r3, [r3, #0] - 8001cf4: 330c adds r3, #12 - 8001cf6: 7812 ldrb r2, [r2, #0] - 8001cf8: 701a strb r2, [r3, #0] + 8001da4: 68fb ldr r3, [r7, #12] + 8001da6: 6b1a ldr r2, [r3, #48] @ 0x30 + 8001da8: 68fb ldr r3, [r7, #12] + 8001daa: 681b ldr r3, [r3, #0] + 8001dac: 330c adds r3, #12 + 8001dae: 7812 ldrb r2, [r2, #0] + 8001db0: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); - 8001cfa: 68fb ldr r3, [r7, #12] - 8001cfc: 6b1b ldr r3, [r3, #48] @ 0x30 - 8001cfe: 1c5a adds r2, r3, #1 - 8001d00: 68fb ldr r3, [r7, #12] - 8001d02: 631a str r2, [r3, #48] @ 0x30 + 8001db2: 68fb ldr r3, [r7, #12] + 8001db4: 6b1b ldr r3, [r3, #48] @ 0x30 + 8001db6: 1c5a adds r2, r3, #1 + 8001db8: 68fb ldr r3, [r7, #12] + 8001dba: 631a str r2, [r3, #48] @ 0x30 hspi->TxXferCount--; - 8001d04: 68fb ldr r3, [r7, #12] - 8001d06: 8edb ldrh r3, [r3, #54] @ 0x36 - 8001d08: b29b uxth r3, r3 - 8001d0a: 3b01 subs r3, #1 - 8001d0c: b29a uxth r2, r3 - 8001d0e: 68fb ldr r3, [r7, #12] - 8001d10: 86da strh r2, [r3, #54] @ 0x36 - 8001d12: e018 b.n 8001d46 + 8001dbc: 68fb ldr r3, [r7, #12] + 8001dbe: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001dc0: b29b uxth r3, r3 + 8001dc2: 3b01 subs r3, #1 + 8001dc4: b29a uxth r2, r3 + 8001dc6: 68fb ldr r3, [r7, #12] + 8001dc8: 86da strh r2, [r3, #54] @ 0x36 + 8001dca: e018 b.n 8001dfe } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - 8001d14: f7fe fe64 bl 80009e0 - 8001d18: 4602 mov r2, r0 - 8001d1a: 69fb ldr r3, [r7, #28] - 8001d1c: 1ad3 subs r3, r2, r3 - 8001d1e: 683a ldr r2, [r7, #0] - 8001d20: 429a cmp r2, r3 - 8001d22: d803 bhi.n 8001d2c - 8001d24: 683b ldr r3, [r7, #0] - 8001d26: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8001d2a: d102 bne.n 8001d32 - 8001d2c: 683b ldr r3, [r7, #0] - 8001d2e: 2b00 cmp r3, #0 - 8001d30: d109 bne.n 8001d46 + 8001dcc: f7fe fe42 bl 8000a54 + 8001dd0: 4602 mov r2, r0 + 8001dd2: 69fb ldr r3, [r7, #28] + 8001dd4: 1ad3 subs r3, r2, r3 + 8001dd6: 683a ldr r2, [r7, #0] + 8001dd8: 429a cmp r2, r3 + 8001dda: d803 bhi.n 8001de4 + 8001ddc: 683b ldr r3, [r7, #0] + 8001dde: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001de2: d102 bne.n 8001dea + 8001de4: 683b ldr r3, [r7, #0] + 8001de6: 2b00 cmp r3, #0 + 8001de8: d109 bne.n 8001dfe { hspi->State = HAL_SPI_STATE_READY; - 8001d32: 68fb ldr r3, [r7, #12] - 8001d34: 2201 movs r2, #1 - 8001d36: f883 2051 strb.w r2, [r3, #81] @ 0x51 + 8001dea: 68fb ldr r3, [r7, #12] + 8001dec: 2201 movs r2, #1 + 8001dee: f883 2051 strb.w r2, [r3, #81] @ 0x51 __HAL_UNLOCK(hspi); - 8001d3a: 68fb ldr r3, [r7, #12] - 8001d3c: 2200 movs r2, #0 - 8001d3e: f883 2050 strb.w r2, [r3, #80] @ 0x50 + 8001df2: 68fb ldr r3, [r7, #12] + 8001df4: 2200 movs r2, #0 + 8001df6: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_TIMEOUT; - 8001d42: 2303 movs r3, #3 - 8001d44: e02d b.n 8001da2 + 8001dfa: 2303 movs r3, #3 + 8001dfc: e02d b.n 8001e5a while (hspi->TxXferCount > 0U) - 8001d46: 68fb ldr r3, [r7, #12] - 8001d48: 8edb ldrh r3, [r3, #54] @ 0x36 - 8001d4a: b29b uxth r3, r3 - 8001d4c: 2b00 cmp r3, #0 - 8001d4e: d1c6 bne.n 8001cde + 8001dfe: 68fb ldr r3, [r7, #12] + 8001e00: 8edb ldrh r3, [r3, #54] @ 0x36 + 8001e02: b29b uxth r3, r3 + 8001e04: 2b00 cmp r3, #0 + 8001e06: d1c6 bne.n 8001d96 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - 8001d50: 69fa ldr r2, [r7, #28] - 8001d52: 6839 ldr r1, [r7, #0] - 8001d54: 68f8 ldr r0, [r7, #12] - 8001d56: f000 f8b1 bl 8001ebc - 8001d5a: 4603 mov r3, r0 - 8001d5c: 2b00 cmp r3, #0 - 8001d5e: d002 beq.n 8001d66 + 8001e08: 69fa ldr r2, [r7, #28] + 8001e0a: 6839 ldr r1, [r7, #0] + 8001e0c: 68f8 ldr r0, [r7, #12] + 8001e0e: f000 f8b1 bl 8001f74 + 8001e12: 4603 mov r3, r0 + 8001e14: 2b00 cmp r3, #0 + 8001e16: d002 beq.n 8001e1e { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - 8001d60: 68fb ldr r3, [r7, #12] - 8001d62: 2220 movs r2, #32 - 8001d64: 655a str r2, [r3, #84] @ 0x54 + 8001e18: 68fb ldr r3, [r7, #12] + 8001e1a: 2220 movs r2, #32 + 8001e1c: 655a str r2, [r3, #84] @ 0x54 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - 8001d66: 68fb ldr r3, [r7, #12] - 8001d68: 689b ldr r3, [r3, #8] - 8001d6a: 2b00 cmp r3, #0 - 8001d6c: d10a bne.n 8001d84 + 8001e1e: 68fb ldr r3, [r7, #12] + 8001e20: 689b ldr r3, [r3, #8] + 8001e22: 2b00 cmp r3, #0 + 8001e24: d10a bne.n 8001e3c { __HAL_SPI_CLEAR_OVRFLAG(hspi); - 8001d6e: 2300 movs r3, #0 - 8001d70: 617b str r3, [r7, #20] - 8001d72: 68fb ldr r3, [r7, #12] - 8001d74: 681b ldr r3, [r3, #0] - 8001d76: 68db ldr r3, [r3, #12] - 8001d78: 617b str r3, [r7, #20] - 8001d7a: 68fb ldr r3, [r7, #12] - 8001d7c: 681b ldr r3, [r3, #0] - 8001d7e: 689b ldr r3, [r3, #8] - 8001d80: 617b str r3, [r7, #20] - 8001d82: 697b ldr r3, [r7, #20] + 8001e26: 2300 movs r3, #0 + 8001e28: 617b str r3, [r7, #20] + 8001e2a: 68fb ldr r3, [r7, #12] + 8001e2c: 681b ldr r3, [r3, #0] + 8001e2e: 68db ldr r3, [r3, #12] + 8001e30: 617b str r3, [r7, #20] + 8001e32: 68fb ldr r3, [r7, #12] + 8001e34: 681b ldr r3, [r3, #0] + 8001e36: 689b ldr r3, [r3, #8] + 8001e38: 617b str r3, [r7, #20] + 8001e3a: 697b ldr r3, [r7, #20] } hspi->State = HAL_SPI_STATE_READY; - 8001d84: 68fb ldr r3, [r7, #12] - 8001d86: 2201 movs r2, #1 - 8001d88: f883 2051 strb.w r2, [r3, #81] @ 0x51 + 8001e3c: 68fb ldr r3, [r7, #12] + 8001e3e: 2201 movs r2, #1 + 8001e40: f883 2051 strb.w r2, [r3, #81] @ 0x51 /* Process Unlocked */ __HAL_UNLOCK(hspi); - 8001d8c: 68fb ldr r3, [r7, #12] - 8001d8e: 2200 movs r2, #0 - 8001d90: f883 2050 strb.w r2, [r3, #80] @ 0x50 + 8001e44: 68fb ldr r3, [r7, #12] + 8001e46: 2200 movs r2, #0 + 8001e48: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - 8001d94: 68fb ldr r3, [r7, #12] - 8001d96: 6d5b ldr r3, [r3, #84] @ 0x54 - 8001d98: 2b00 cmp r3, #0 - 8001d9a: d001 beq.n 8001da0 + 8001e4c: 68fb ldr r3, [r7, #12] + 8001e4e: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001e50: 2b00 cmp r3, #0 + 8001e52: d001 beq.n 8001e58 { return HAL_ERROR; - 8001d9c: 2301 movs r3, #1 - 8001d9e: e000 b.n 8001da2 + 8001e54: 2301 movs r3, #1 + 8001e56: e000 b.n 8001e5a } else { return HAL_OK; - 8001da0: 2300 movs r3, #0 + 8001e58: 2300 movs r3, #0 } } - 8001da2: 4618 mov r0, r3 - 8001da4: 3720 adds r7, #32 - 8001da6: 46bd mov sp, r7 - 8001da8: bd80 pop {r7, pc} + 8001e5a: 4618 mov r0, r3 + 8001e5c: 3720 adds r7, #32 + 8001e5e: 46bd mov sp, r7 + 8001e60: bd80 pop {r7, pc} ... -08001dac : +08001e64 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { - 8001dac: b580 push {r7, lr} - 8001dae: b088 sub sp, #32 - 8001db0: af00 add r7, sp, #0 - 8001db2: 60f8 str r0, [r7, #12] - 8001db4: 60b9 str r1, [r7, #8] - 8001db6: 603b str r3, [r7, #0] - 8001db8: 4613 mov r3, r2 - 8001dba: 71fb strb r3, [r7, #7] + 8001e64: b580 push {r7, lr} + 8001e66: b088 sub sp, #32 + 8001e68: af00 add r7, sp, #0 + 8001e6a: 60f8 str r0, [r7, #12] + 8001e6c: 60b9 str r1, [r7, #8] + 8001e6e: 603b str r3, [r7, #0] + 8001e70: 4613 mov r3, r2 + 8001e72: 71fb strb r3, [r7, #7] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); - 8001dbc: f7fe fe10 bl 80009e0 - 8001dc0: 4602 mov r2, r0 - 8001dc2: 6abb ldr r3, [r7, #40] @ 0x28 - 8001dc4: 1a9b subs r3, r3, r2 - 8001dc6: 683a ldr r2, [r7, #0] - 8001dc8: 4413 add r3, r2 - 8001dca: 61fb str r3, [r7, #28] + 8001e74: f7fe fdee bl 8000a54 + 8001e78: 4602 mov r2, r0 + 8001e7a: 6abb ldr r3, [r7, #40] @ 0x28 + 8001e7c: 1a9b subs r3, r3, r2 + 8001e7e: 683a ldr r2, [r7, #0] + 8001e80: 4413 add r3, r2 + 8001e82: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); - 8001dcc: f7fe fe08 bl 80009e0 - 8001dd0: 61b8 str r0, [r7, #24] + 8001e84: f7fe fde6 bl 8000a54 + 8001e88: 61b8 str r0, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); - 8001dd2: 4b39 ldr r3, [pc, #228] @ (8001eb8 ) - 8001dd4: 681b ldr r3, [r3, #0] - 8001dd6: 015b lsls r3, r3, #5 - 8001dd8: 0d1b lsrs r3, r3, #20 - 8001dda: 69fa ldr r2, [r7, #28] - 8001ddc: fb02 f303 mul.w r3, r2, r3 - 8001de0: 617b str r3, [r7, #20] + 8001e8a: 4b39 ldr r3, [pc, #228] @ (8001f70 ) + 8001e8c: 681b ldr r3, [r3, #0] + 8001e8e: 015b lsls r3, r3, #5 + 8001e90: 0d1b lsrs r3, r3, #20 + 8001e92: 69fa ldr r2, [r7, #28] + 8001e94: fb02 f303 mul.w r3, r2, r3 + 8001e98: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) - 8001de2: e054 b.n 8001e8e + 8001e9a: e054 b.n 8001f46 { if (Timeout != HAL_MAX_DELAY) - 8001de4: 683b ldr r3, [r7, #0] - 8001de6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff - 8001dea: d050 beq.n 8001e8e + 8001e9c: 683b ldr r3, [r7, #0] + 8001e9e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff + 8001ea2: d050 beq.n 8001f46 { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) - 8001dec: f7fe fdf8 bl 80009e0 - 8001df0: 4602 mov r2, r0 - 8001df2: 69bb ldr r3, [r7, #24] - 8001df4: 1ad3 subs r3, r2, r3 - 8001df6: 69fa ldr r2, [r7, #28] - 8001df8: 429a cmp r2, r3 - 8001dfa: d902 bls.n 8001e02 - 8001dfc: 69fb ldr r3, [r7, #28] - 8001dfe: 2b00 cmp r3, #0 - 8001e00: d13d bne.n 8001e7e + 8001ea4: f7fe fdd6 bl 8000a54 + 8001ea8: 4602 mov r2, r0 + 8001eaa: 69bb ldr r3, [r7, #24] + 8001eac: 1ad3 subs r3, r2, r3 + 8001eae: 69fa ldr r2, [r7, #28] + 8001eb0: 429a cmp r2, r3 + 8001eb2: d902 bls.n 8001eba + 8001eb4: 69fb ldr r3, [r7, #28] + 8001eb6: 2b00 cmp r3, #0 + 8001eb8: d13d bne.n 8001f36 /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - 8001e02: 68fb ldr r3, [r7, #12] - 8001e04: 681b ldr r3, [r3, #0] - 8001e06: 685a ldr r2, [r3, #4] - 8001e08: 68fb ldr r3, [r7, #12] - 8001e0a: 681b ldr r3, [r3, #0] - 8001e0c: f022 02e0 bic.w r2, r2, #224 @ 0xe0 - 8001e10: 605a str r2, [r3, #4] + 8001eba: 68fb ldr r3, [r7, #12] + 8001ebc: 681b ldr r3, [r3, #0] + 8001ebe: 685a ldr r2, [r3, #4] + 8001ec0: 68fb ldr r3, [r7, #12] + 8001ec2: 681b ldr r3, [r3, #0] + 8001ec4: f022 02e0 bic.w r2, r2, #224 @ 0xe0 + 8001ec8: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - 8001e12: 68fb ldr r3, [r7, #12] - 8001e14: 685b ldr r3, [r3, #4] - 8001e16: f5b3 7f82 cmp.w r3, #260 @ 0x104 - 8001e1a: d111 bne.n 8001e40 - 8001e1c: 68fb ldr r3, [r7, #12] - 8001e1e: 689b ldr r3, [r3, #8] - 8001e20: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 - 8001e24: d004 beq.n 8001e30 + 8001eca: 68fb ldr r3, [r7, #12] + 8001ecc: 685b ldr r3, [r3, #4] + 8001ece: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001ed2: d111 bne.n 8001ef8 + 8001ed4: 68fb ldr r3, [r7, #12] + 8001ed6: 689b ldr r3, [r3, #8] + 8001ed8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 8001edc: d004 beq.n 8001ee8 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - 8001e26: 68fb ldr r3, [r7, #12] - 8001e28: 689b ldr r3, [r3, #8] - 8001e2a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8001e2e: d107 bne.n 8001e40 + 8001ede: 68fb ldr r3, [r7, #12] + 8001ee0: 689b ldr r3, [r3, #8] + 8001ee2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8001ee6: d107 bne.n 8001ef8 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); - 8001e30: 68fb ldr r3, [r7, #12] - 8001e32: 681b ldr r3, [r3, #0] - 8001e34: 681a ldr r2, [r3, #0] - 8001e36: 68fb ldr r3, [r7, #12] - 8001e38: 681b ldr r3, [r3, #0] - 8001e3a: f022 0240 bic.w r2, r2, #64 @ 0x40 - 8001e3e: 601a str r2, [r3, #0] + 8001ee8: 68fb ldr r3, [r7, #12] + 8001eea: 681b ldr r3, [r3, #0] + 8001eec: 681a ldr r2, [r3, #0] + 8001eee: 68fb ldr r3, [r7, #12] + 8001ef0: 681b ldr r3, [r3, #0] + 8001ef2: f022 0240 bic.w r2, r2, #64 @ 0x40 + 8001ef6: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - 8001e40: 68fb ldr r3, [r7, #12] - 8001e42: 6a9b ldr r3, [r3, #40] @ 0x28 - 8001e44: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 - 8001e48: d10f bne.n 8001e6a + 8001ef8: 68fb ldr r3, [r7, #12] + 8001efa: 6a9b ldr r3, [r3, #40] @ 0x28 + 8001efc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8001f00: d10f bne.n 8001f22 { SPI_RESET_CRC(hspi); - 8001e4a: 68fb ldr r3, [r7, #12] - 8001e4c: 681b ldr r3, [r3, #0] - 8001e4e: 681a ldr r2, [r3, #0] - 8001e50: 68fb ldr r3, [r7, #12] - 8001e52: 681b ldr r3, [r3, #0] - 8001e54: f422 5200 bic.w r2, r2, #8192 @ 0x2000 - 8001e58: 601a str r2, [r3, #0] - 8001e5a: 68fb ldr r3, [r7, #12] - 8001e5c: 681b ldr r3, [r3, #0] - 8001e5e: 681a ldr r2, [r3, #0] - 8001e60: 68fb ldr r3, [r7, #12] - 8001e62: 681b ldr r3, [r3, #0] - 8001e64: f442 5200 orr.w r2, r2, #8192 @ 0x2000 - 8001e68: 601a str r2, [r3, #0] + 8001f02: 68fb ldr r3, [r7, #12] + 8001f04: 681b ldr r3, [r3, #0] + 8001f06: 681a ldr r2, [r3, #0] + 8001f08: 68fb ldr r3, [r7, #12] + 8001f0a: 681b ldr r3, [r3, #0] + 8001f0c: f422 5200 bic.w r2, r2, #8192 @ 0x2000 + 8001f10: 601a str r2, [r3, #0] + 8001f12: 68fb ldr r3, [r7, #12] + 8001f14: 681b ldr r3, [r3, #0] + 8001f16: 681a ldr r2, [r3, #0] + 8001f18: 68fb ldr r3, [r7, #12] + 8001f1a: 681b ldr r3, [r3, #0] + 8001f1c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 + 8001f20: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; - 8001e6a: 68fb ldr r3, [r7, #12] - 8001e6c: 2201 movs r2, #1 - 8001e6e: f883 2051 strb.w r2, [r3, #81] @ 0x51 + 8001f22: 68fb ldr r3, [r7, #12] + 8001f24: 2201 movs r2, #1 + 8001f26: f883 2051 strb.w r2, [r3, #81] @ 0x51 /* Process Unlocked */ __HAL_UNLOCK(hspi); - 8001e72: 68fb ldr r3, [r7, #12] - 8001e74: 2200 movs r2, #0 - 8001e76: f883 2050 strb.w r2, [r3, #80] @ 0x50 + 8001f2a: 68fb ldr r3, [r7, #12] + 8001f2c: 2200 movs r2, #0 + 8001f2e: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_TIMEOUT; - 8001e7a: 2303 movs r3, #3 - 8001e7c: e017 b.n 8001eae + 8001f32: 2303 movs r3, #3 + 8001f34: e017 b.n 8001f66 } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) - 8001e7e: 697b ldr r3, [r7, #20] - 8001e80: 2b00 cmp r3, #0 - 8001e82: d101 bne.n 8001e88 + 8001f36: 697b ldr r3, [r7, #20] + 8001f38: 2b00 cmp r3, #0 + 8001f3a: d101 bne.n 8001f40 { tmp_timeout = 0U; - 8001e84: 2300 movs r3, #0 - 8001e86: 61fb str r3, [r7, #28] + 8001f3c: 2300 movs r3, #0 + 8001f3e: 61fb str r3, [r7, #28] } count--; - 8001e88: 697b ldr r3, [r7, #20] - 8001e8a: 3b01 subs r3, #1 - 8001e8c: 617b str r3, [r7, #20] + 8001f40: 697b ldr r3, [r7, #20] + 8001f42: 3b01 subs r3, #1 + 8001f44: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) - 8001e8e: 68fb ldr r3, [r7, #12] - 8001e90: 681b ldr r3, [r3, #0] - 8001e92: 689a ldr r2, [r3, #8] - 8001e94: 68bb ldr r3, [r7, #8] - 8001e96: 4013 ands r3, r2 - 8001e98: 68ba ldr r2, [r7, #8] - 8001e9a: 429a cmp r2, r3 - 8001e9c: bf0c ite eq - 8001e9e: 2301 moveq r3, #1 - 8001ea0: 2300 movne r3, #0 - 8001ea2: b2db uxtb r3, r3 - 8001ea4: 461a mov r2, r3 - 8001ea6: 79fb ldrb r3, [r7, #7] - 8001ea8: 429a cmp r2, r3 - 8001eaa: d19b bne.n 8001de4 + 8001f46: 68fb ldr r3, [r7, #12] + 8001f48: 681b ldr r3, [r3, #0] + 8001f4a: 689a ldr r2, [r3, #8] + 8001f4c: 68bb ldr r3, [r7, #8] + 8001f4e: 4013 ands r3, r2 + 8001f50: 68ba ldr r2, [r7, #8] + 8001f52: 429a cmp r2, r3 + 8001f54: bf0c ite eq + 8001f56: 2301 moveq r3, #1 + 8001f58: 2300 movne r3, #0 + 8001f5a: b2db uxtb r3, r3 + 8001f5c: 461a mov r2, r3 + 8001f5e: 79fb ldrb r3, [r7, #7] + 8001f60: 429a cmp r2, r3 + 8001f62: d19b bne.n 8001e9c } } return HAL_OK; - 8001eac: 2300 movs r3, #0 + 8001f64: 2300 movs r3, #0 } - 8001eae: 4618 mov r0, r3 - 8001eb0: 3720 adds r7, #32 - 8001eb2: 46bd mov sp, r7 - 8001eb4: bd80 pop {r7, pc} - 8001eb6: bf00 nop - 8001eb8: 20000000 .word 0x20000000 + 8001f66: 4618 mov r0, r3 + 8001f68: 3720 adds r7, #32 + 8001f6a: 46bd mov sp, r7 + 8001f6c: bd80 pop {r7, pc} + 8001f6e: bf00 nop + 8001f70: 20000000 .word 0x20000000 -08001ebc : +08001f74 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { - 8001ebc: b580 push {r7, lr} - 8001ebe: b088 sub sp, #32 - 8001ec0: af02 add r7, sp, #8 - 8001ec2: 60f8 str r0, [r7, #12] - 8001ec4: 60b9 str r1, [r7, #8] - 8001ec6: 607a str r2, [r7, #4] + 8001f74: b580 push {r7, lr} + 8001f76: b088 sub sp, #32 + 8001f78: af02 add r7, sp, #8 + 8001f7a: 60f8 str r0, [r7, #12] + 8001f7c: 60b9 str r1, [r7, #8] + 8001f7e: 607a str r2, [r7, #4] /* Wait until TXE flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) - 8001ec8: 687b ldr r3, [r7, #4] - 8001eca: 9300 str r3, [sp, #0] - 8001ecc: 68bb ldr r3, [r7, #8] - 8001ece: 2201 movs r2, #1 - 8001ed0: 2102 movs r1, #2 - 8001ed2: 68f8 ldr r0, [r7, #12] - 8001ed4: f7ff ff6a bl 8001dac - 8001ed8: 4603 mov r3, r0 - 8001eda: 2b00 cmp r3, #0 - 8001edc: d007 beq.n 8001eee + 8001f80: 687b ldr r3, [r7, #4] + 8001f82: 9300 str r3, [sp, #0] + 8001f84: 68bb ldr r3, [r7, #8] + 8001f86: 2201 movs r2, #1 + 8001f88: 2102 movs r1, #2 + 8001f8a: 68f8 ldr r0, [r7, #12] + 8001f8c: f7ff ff6a bl 8001e64 + 8001f90: 4603 mov r3, r0 + 8001f92: 2b00 cmp r3, #0 + 8001f94: d007 beq.n 8001fa6 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - 8001ede: 68fb ldr r3, [r7, #12] - 8001ee0: 6d5b ldr r3, [r3, #84] @ 0x54 - 8001ee2: f043 0220 orr.w r2, r3, #32 - 8001ee6: 68fb ldr r3, [r7, #12] - 8001ee8: 655a str r2, [r3, #84] @ 0x54 + 8001f96: 68fb ldr r3, [r7, #12] + 8001f98: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001f9a: f043 0220 orr.w r2, r3, #32 + 8001f9e: 68fb ldr r3, [r7, #12] + 8001fa0: 655a str r2, [r3, #84] @ 0x54 return HAL_TIMEOUT; - 8001eea: 2303 movs r3, #3 - 8001eec: e032 b.n 8001f54 + 8001fa2: 2303 movs r3, #3 + 8001fa4: e032 b.n 800200c } /* Timeout in us */ __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); - 8001eee: 4b1b ldr r3, [pc, #108] @ (8001f5c ) - 8001ef0: 681b ldr r3, [r3, #0] - 8001ef2: 4a1b ldr r2, [pc, #108] @ (8001f60 ) - 8001ef4: fba2 2303 umull r2, r3, r2, r3 - 8001ef8: 0d5b lsrs r3, r3, #21 - 8001efa: f44f 727a mov.w r2, #1000 @ 0x3e8 - 8001efe: fb02 f303 mul.w r3, r2, r3 - 8001f02: 617b str r3, [r7, #20] + 8001fa6: 4b1b ldr r3, [pc, #108] @ (8002014 ) + 8001fa8: 681b ldr r3, [r3, #0] + 8001faa: 4a1b ldr r2, [pc, #108] @ (8002018 ) + 8001fac: fba2 2303 umull r2, r3, r2, r3 + 8001fb0: 0d5b lsrs r3, r3, #21 + 8001fb2: f44f 727a mov.w r2, #1000 @ 0x3e8 + 8001fb6: fb02 f303 mul.w r3, r2, r3 + 8001fba: 617b str r3, [r7, #20] /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ if (hspi->Init.Mode == SPI_MODE_MASTER) - 8001f04: 68fb ldr r3, [r7, #12] - 8001f06: 685b ldr r3, [r3, #4] - 8001f08: f5b3 7f82 cmp.w r3, #260 @ 0x104 - 8001f0c: d112 bne.n 8001f34 + 8001fbc: 68fb ldr r3, [r7, #12] + 8001fbe: 685b ldr r3, [r3, #4] + 8001fc0: f5b3 7f82 cmp.w r3, #260 @ 0x104 + 8001fc4: d112 bne.n 8001fec { /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) - 8001f0e: 687b ldr r3, [r7, #4] - 8001f10: 9300 str r3, [sp, #0] - 8001f12: 68bb ldr r3, [r7, #8] - 8001f14: 2200 movs r2, #0 - 8001f16: 2180 movs r1, #128 @ 0x80 - 8001f18: 68f8 ldr r0, [r7, #12] - 8001f1a: f7ff ff47 bl 8001dac - 8001f1e: 4603 mov r3, r0 - 8001f20: 2b00 cmp r3, #0 - 8001f22: d016 beq.n 8001f52 + 8001fc6: 687b ldr r3, [r7, #4] + 8001fc8: 9300 str r3, [sp, #0] + 8001fca: 68bb ldr r3, [r7, #8] + 8001fcc: 2200 movs r2, #0 + 8001fce: 2180 movs r1, #128 @ 0x80 + 8001fd0: 68f8 ldr r0, [r7, #12] + 8001fd2: f7ff ff47 bl 8001e64 + 8001fd6: 4603 mov r3, r0 + 8001fd8: 2b00 cmp r3, #0 + 8001fda: d016 beq.n 800200a { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - 8001f24: 68fb ldr r3, [r7, #12] - 8001f26: 6d5b ldr r3, [r3, #84] @ 0x54 - 8001f28: f043 0220 orr.w r2, r3, #32 - 8001f2c: 68fb ldr r3, [r7, #12] - 8001f2e: 655a str r2, [r3, #84] @ 0x54 + 8001fdc: 68fb ldr r3, [r7, #12] + 8001fde: 6d5b ldr r3, [r3, #84] @ 0x54 + 8001fe0: f043 0220 orr.w r2, r3, #32 + 8001fe4: 68fb ldr r3, [r7, #12] + 8001fe6: 655a str r2, [r3, #84] @ 0x54 return HAL_TIMEOUT; - 8001f30: 2303 movs r3, #3 - 8001f32: e00f b.n 8001f54 + 8001fe8: 2303 movs r3, #3 + 8001fea: e00f b.n 800200c * User have to calculate the timeout value to fit with the time of 1 byte transfer. * This time is directly link with the SPI clock from Master device. */ do { if (count == 0U) - 8001f34: 697b ldr r3, [r7, #20] - 8001f36: 2b00 cmp r3, #0 - 8001f38: d00a beq.n 8001f50 + 8001fec: 697b ldr r3, [r7, #20] + 8001fee: 2b00 cmp r3, #0 + 8001ff0: d00a beq.n 8002008 { break; } count--; - 8001f3a: 697b ldr r3, [r7, #20] - 8001f3c: 3b01 subs r3, #1 - 8001f3e: 617b str r3, [r7, #20] + 8001ff2: 697b ldr r3, [r7, #20] + 8001ff4: 3b01 subs r3, #1 + 8001ff6: 617b str r3, [r7, #20] } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); - 8001f40: 68fb ldr r3, [r7, #12] - 8001f42: 681b ldr r3, [r3, #0] - 8001f44: 689b ldr r3, [r3, #8] - 8001f46: f003 0380 and.w r3, r3, #128 @ 0x80 - 8001f4a: 2b80 cmp r3, #128 @ 0x80 - 8001f4c: d0f2 beq.n 8001f34 - 8001f4e: e000 b.n 8001f52 + 8001ff8: 68fb ldr r3, [r7, #12] + 8001ffa: 681b ldr r3, [r3, #0] + 8001ffc: 689b ldr r3, [r3, #8] + 8001ffe: f003 0380 and.w r3, r3, #128 @ 0x80 + 8002002: 2b80 cmp r3, #128 @ 0x80 + 8002004: d0f2 beq.n 8001fec + 8002006: e000 b.n 800200a break; - 8001f50: bf00 nop + 8002008: bf00 nop } return HAL_OK; - 8001f52: 2300 movs r3, #0 + 800200a: 2300 movs r3, #0 } - 8001f54: 4618 mov r0, r3 - 8001f56: 3718 adds r7, #24 - 8001f58: 46bd mov sp, r7 - 8001f5a: bd80 pop {r7, pc} - 8001f5c: 20000000 .word 0x20000000 - 8001f60: 165e9f81 .word 0x165e9f81 + 800200c: 4618 mov r0, r3 + 800200e: 3718 adds r7, #24 + 8002010: 46bd mov sp, r7 + 8002012: bd80 pop {r7, pc} + 8002014: 20000000 .word 0x20000000 + 8002018: 165e9f81 .word 0x165e9f81 -08001f64 : - 8001f64: 4603 mov r3, r0 - 8001f66: 4402 add r2, r0 - 8001f68: 4293 cmp r3, r2 - 8001f6a: d100 bne.n 8001f6e - 8001f6c: 4770 bx lr - 8001f6e: f803 1b01 strb.w r1, [r3], #1 - 8001f72: e7f9 b.n 8001f68 +0800201c : + 800201c: 4603 mov r3, r0 + 800201e: 4402 add r2, r0 + 8002020: 4293 cmp r3, r2 + 8002022: d100 bne.n 8002026 + 8002024: 4770 bx lr + 8002026: f803 1b01 strb.w r1, [r3], #1 + 800202a: e7f9 b.n 8002020 -08001f74 <__libc_init_array>: - 8001f74: b570 push {r4, r5, r6, lr} - 8001f76: 2600 movs r6, #0 - 8001f78: 4d0c ldr r5, [pc, #48] @ (8001fac <__libc_init_array+0x38>) - 8001f7a: 4c0d ldr r4, [pc, #52] @ (8001fb0 <__libc_init_array+0x3c>) - 8001f7c: 1b64 subs r4, r4, r5 - 8001f7e: 10a4 asrs r4, r4, #2 - 8001f80: 42a6 cmp r6, r4 - 8001f82: d109 bne.n 8001f98 <__libc_init_array+0x24> - 8001f84: f000 f81a bl 8001fbc <_init> - 8001f88: 2600 movs r6, #0 - 8001f8a: 4d0a ldr r5, [pc, #40] @ (8001fb4 <__libc_init_array+0x40>) - 8001f8c: 4c0a ldr r4, [pc, #40] @ (8001fb8 <__libc_init_array+0x44>) - 8001f8e: 1b64 subs r4, r4, r5 - 8001f90: 10a4 asrs r4, r4, #2 - 8001f92: 42a6 cmp r6, r4 - 8001f94: d105 bne.n 8001fa2 <__libc_init_array+0x2e> - 8001f96: bd70 pop {r4, r5, r6, pc} - 8001f98: f855 3b04 ldr.w r3, [r5], #4 - 8001f9c: 4798 blx r3 - 8001f9e: 3601 adds r6, #1 - 8001fa0: e7ee b.n 8001f80 <__libc_init_array+0xc> - 8001fa2: f855 3b04 ldr.w r3, [r5], #4 - 8001fa6: 4798 blx r3 - 8001fa8: 3601 adds r6, #1 - 8001faa: e7f2 b.n 8001f92 <__libc_init_array+0x1e> - 8001fac: 08002008 .word 0x08002008 - 8001fb0: 08002008 .word 0x08002008 - 8001fb4: 08002008 .word 0x08002008 - 8001fb8: 0800200c .word 0x0800200c +0800202c <__libc_init_array>: + 800202c: b570 push {r4, r5, r6, lr} + 800202e: 2600 movs r6, #0 + 8002030: 4d0c ldr r5, [pc, #48] @ (8002064 <__libc_init_array+0x38>) + 8002032: 4c0d ldr r4, [pc, #52] @ (8002068 <__libc_init_array+0x3c>) + 8002034: 1b64 subs r4, r4, r5 + 8002036: 10a4 asrs r4, r4, #2 + 8002038: 42a6 cmp r6, r4 + 800203a: d109 bne.n 8002050 <__libc_init_array+0x24> + 800203c: f000 f81a bl 8002074 <_init> + 8002040: 2600 movs r6, #0 + 8002042: 4d0a ldr r5, [pc, #40] @ (800206c <__libc_init_array+0x40>) + 8002044: 4c0a ldr r4, [pc, #40] @ (8002070 <__libc_init_array+0x44>) + 8002046: 1b64 subs r4, r4, r5 + 8002048: 10a4 asrs r4, r4, #2 + 800204a: 42a6 cmp r6, r4 + 800204c: d105 bne.n 800205a <__libc_init_array+0x2e> + 800204e: bd70 pop {r4, r5, r6, pc} + 8002050: f855 3b04 ldr.w r3, [r5], #4 + 8002054: 4798 blx r3 + 8002056: 3601 adds r6, #1 + 8002058: e7ee b.n 8002038 <__libc_init_array+0xc> + 800205a: f855 3b04 ldr.w r3, [r5], #4 + 800205e: 4798 blx r3 + 8002060: 3601 adds r6, #1 + 8002062: e7f2 b.n 800204a <__libc_init_array+0x1e> + 8002064: 080020c0 .word 0x080020c0 + 8002068: 080020c0 .word 0x080020c0 + 800206c: 080020c0 .word 0x080020c0 + 8002070: 080020c4 .word 0x080020c4 -08001fbc <_init>: - 8001fbc: b5f8 push {r3, r4, r5, r6, r7, lr} - 8001fbe: bf00 nop - 8001fc0: bcf8 pop {r3, r4, r5, r6, r7} - 8001fc2: bc08 pop {r3} - 8001fc4: 469e mov lr, r3 - 8001fc6: 4770 bx lr +08002074 <_init>: + 8002074: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002076: bf00 nop + 8002078: bcf8 pop {r3, r4, r5, r6, r7} + 800207a: bc08 pop {r3} + 800207c: 469e mov lr, r3 + 800207e: 4770 bx lr -08001fc8 <_fini>: - 8001fc8: b5f8 push {r3, r4, r5, r6, r7, lr} - 8001fca: bf00 nop - 8001fcc: bcf8 pop {r3, r4, r5, r6, r7} - 8001fce: bc08 pop {r3} - 8001fd0: 469e mov lr, r3 - 8001fd2: 4770 bx lr +08002080 <_fini>: + 8002080: b5f8 push {r3, r4, r5, r6, r7, lr} + 8002082: bf00 nop + 8002084: bcf8 pop {r3, r4, r5, r6, r7} + 8002086: bc08 pop {r3} + 8002088: 469e mov lr, r3 + 800208a: 4770 bx lr diff --git a/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.map b/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.map index 56b1f42..2dfbcb3 100644 --- a/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.map +++ b/TP2_INIT_DISPLAY/Debug/TP2_INIT_DISPLAY.map @@ -639,8 +639,6 @@ Discarded input sections 0x00000000 0x50 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o .text.HAL_GetTickFreq 0x00000000 0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .text.HAL_Delay - 0x00000000 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o .text.HAL_SuspendTick 0x00000000 0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o .text.HAL_ResumeTick @@ -2315,7 +2313,7 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id 0x08000000 g_pfnVectors 0x0800013c . = ALIGN (0x4) -.text 0x0800013c 0x1e98 +.text 0x0800013c 0x1f50 0x0800013c . = ALIGN (0x4) *(.text) .text 0x0800013c 0x40 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o @@ -2327,288 +2325,293 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id 0x080004ac __aeabi_ldiv0 0x080004ac __aeabi_idiv0 *(.text*) - .text.main 0x080004b0 0x30 ./Core/Src/main.o - 0x080004b0 main + .text.affiche 0x080004b0 0x60 ./Core/Src/main.o + 0x080004b0 affiche + .text.main 0x08000510 0x44 ./Core/Src/main.o + 0x08000510 main .text.SystemClock_Config - 0x080004e0 0x8c ./Core/Src/main.o - 0x080004e0 SystemClock_Config + 0x08000554 0x8c ./Core/Src/main.o + 0x08000554 SystemClock_Config .text.MX_SPI1_Init - 0x0800056c 0x6c ./Core/Src/main.o + 0x080005e0 0x6c ./Core/Src/main.o .text.MX_GPIO_Init - 0x080005d8 0x7c ./Core/Src/main.o + 0x0800064c 0x7c ./Core/Src/main.o .text.Error_Handler - 0x08000654 0xc ./Core/Src/main.o - 0x08000654 Error_Handler + 0x080006c8 0xc ./Core/Src/main.o + 0x080006c8 Error_Handler .text.HAL_MspInit - 0x08000660 0x5c ./Core/Src/stm32l1xx_hal_msp.o - 0x08000660 HAL_MspInit + 0x080006d4 0x5c ./Core/Src/stm32l1xx_hal_msp.o + 0x080006d4 HAL_MspInit .text.HAL_SPI_MspInit - 0x080006bc 0x88 ./Core/Src/stm32l1xx_hal_msp.o - 0x080006bc HAL_SPI_MspInit + 0x08000730 0x88 ./Core/Src/stm32l1xx_hal_msp.o + 0x08000730 HAL_SPI_MspInit .text.NMI_Handler - 0x08000744 0x8 ./Core/Src/stm32l1xx_it.o - 0x08000744 NMI_Handler + 0x080007b8 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007b8 NMI_Handler .text.HardFault_Handler - 0x0800074c 0x8 ./Core/Src/stm32l1xx_it.o - 0x0800074c HardFault_Handler + 0x080007c0 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007c0 HardFault_Handler .text.MemManage_Handler - 0x08000754 0x8 ./Core/Src/stm32l1xx_it.o - 0x08000754 MemManage_Handler + 0x080007c8 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007c8 MemManage_Handler .text.BusFault_Handler - 0x0800075c 0x8 ./Core/Src/stm32l1xx_it.o - 0x0800075c BusFault_Handler + 0x080007d0 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007d0 BusFault_Handler .text.UsageFault_Handler - 0x08000764 0x8 ./Core/Src/stm32l1xx_it.o - 0x08000764 UsageFault_Handler + 0x080007d8 0x8 ./Core/Src/stm32l1xx_it.o + 0x080007d8 UsageFault_Handler .text.SVC_Handler - 0x0800076c 0xc ./Core/Src/stm32l1xx_it.o - 0x0800076c SVC_Handler + 0x080007e0 0xc ./Core/Src/stm32l1xx_it.o + 0x080007e0 SVC_Handler .text.DebugMon_Handler - 0x08000778 0xc ./Core/Src/stm32l1xx_it.o - 0x08000778 DebugMon_Handler + 0x080007ec 0xc ./Core/Src/stm32l1xx_it.o + 0x080007ec DebugMon_Handler .text.PendSV_Handler - 0x08000784 0xc ./Core/Src/stm32l1xx_it.o - 0x08000784 PendSV_Handler + 0x080007f8 0xc ./Core/Src/stm32l1xx_it.o + 0x080007f8 PendSV_Handler .text.SysTick_Handler - 0x08000790 0xc ./Core/Src/stm32l1xx_it.o - 0x08000790 SysTick_Handler + 0x08000804 0xc ./Core/Src/stm32l1xx_it.o + 0x08000804 SysTick_Handler .text.SystemInit - 0x0800079c 0xc ./Core/Src/system_stm32l1xx.o - 0x0800079c SystemInit + 0x08000810 0xc ./Core/Src/system_stm32l1xx.o + 0x08000810 SystemInit .text.Reset_Handler - 0x080007a8 0x48 ./Core/Startup/startup_stm32l152retx.o - 0x080007a8 Reset_Handler + 0x0800081c 0x48 ./Core/Startup/startup_stm32l152retx.o + 0x0800081c Reset_Handler .text.Default_Handler - 0x080007f0 0x2 ./Core/Startup/startup_stm32l152retx.o - 0x080007f0 DMA2_Channel3_IRQHandler - 0x080007f0 EXTI2_IRQHandler - 0x080007f0 COMP_ACQ_IRQHandler - 0x080007f0 TIM10_IRQHandler - 0x080007f0 USB_HP_IRQHandler - 0x080007f0 TIM6_IRQHandler - 0x080007f0 PVD_IRQHandler - 0x080007f0 EXTI3_IRQHandler - 0x080007f0 EXTI0_IRQHandler - 0x080007f0 I2C2_EV_IRQHandler - 0x080007f0 SPI1_IRQHandler - 0x080007f0 USB_FS_WKUP_IRQHandler - 0x080007f0 DMA2_Channel2_IRQHandler - 0x080007f0 DMA1_Channel4_IRQHandler - 0x080007f0 ADC1_IRQHandler - 0x080007f0 USART3_IRQHandler - 0x080007f0 DMA1_Channel7_IRQHandler - 0x080007f0 LCD_IRQHandler - 0x080007f0 UART5_IRQHandler - 0x080007f0 TIM4_IRQHandler - 0x080007f0 DMA2_Channel1_IRQHandler - 0x080007f0 I2C1_EV_IRQHandler - 0x080007f0 DMA1_Channel6_IRQHandler - 0x080007f0 UART4_IRQHandler - 0x080007f0 DMA2_Channel4_IRQHandler - 0x080007f0 TIM3_IRQHandler - 0x080007f0 RCC_IRQHandler - 0x080007f0 DMA1_Channel1_IRQHandler - 0x080007f0 Default_Handler - 0x080007f0 EXTI15_10_IRQHandler - 0x080007f0 TIM7_IRQHandler - 0x080007f0 TIM5_IRQHandler - 0x080007f0 EXTI9_5_IRQHandler - 0x080007f0 TIM9_IRQHandler - 0x080007f0 TAMPER_STAMP_IRQHandler - 0x080007f0 RTC_WKUP_IRQHandler - 0x080007f0 SPI2_IRQHandler - 0x080007f0 DMA2_Channel5_IRQHandler - 0x080007f0 DMA1_Channel5_IRQHandler - 0x080007f0 USB_LP_IRQHandler - 0x080007f0 EXTI4_IRQHandler - 0x080007f0 DMA1_Channel3_IRQHandler - 0x080007f0 COMP_IRQHandler - 0x080007f0 WWDG_IRQHandler - 0x080007f0 TIM2_IRQHandler - 0x080007f0 DAC_IRQHandler - 0x080007f0 EXTI1_IRQHandler - 0x080007f0 TIM11_IRQHandler - 0x080007f0 USART2_IRQHandler - 0x080007f0 I2C2_ER_IRQHandler - 0x080007f0 DMA1_Channel2_IRQHandler - 0x080007f0 FLASH_IRQHandler - 0x080007f0 USART1_IRQHandler - 0x080007f0 SPI3_IRQHandler - 0x080007f0 I2C1_ER_IRQHandler - 0x080007f0 RTC_Alarm_IRQHandler + 0x08000864 0x2 ./Core/Startup/startup_stm32l152retx.o + 0x08000864 DMA2_Channel3_IRQHandler + 0x08000864 EXTI2_IRQHandler + 0x08000864 COMP_ACQ_IRQHandler + 0x08000864 TIM10_IRQHandler + 0x08000864 USB_HP_IRQHandler + 0x08000864 TIM6_IRQHandler + 0x08000864 PVD_IRQHandler + 0x08000864 EXTI3_IRQHandler + 0x08000864 EXTI0_IRQHandler + 0x08000864 I2C2_EV_IRQHandler + 0x08000864 SPI1_IRQHandler + 0x08000864 USB_FS_WKUP_IRQHandler + 0x08000864 DMA2_Channel2_IRQHandler + 0x08000864 DMA1_Channel4_IRQHandler + 0x08000864 ADC1_IRQHandler + 0x08000864 USART3_IRQHandler + 0x08000864 DMA1_Channel7_IRQHandler + 0x08000864 LCD_IRQHandler + 0x08000864 UART5_IRQHandler + 0x08000864 TIM4_IRQHandler + 0x08000864 DMA2_Channel1_IRQHandler + 0x08000864 I2C1_EV_IRQHandler + 0x08000864 DMA1_Channel6_IRQHandler + 0x08000864 UART4_IRQHandler + 0x08000864 DMA2_Channel4_IRQHandler + 0x08000864 TIM3_IRQHandler + 0x08000864 RCC_IRQHandler + 0x08000864 DMA1_Channel1_IRQHandler + 0x08000864 Default_Handler + 0x08000864 EXTI15_10_IRQHandler + 0x08000864 TIM7_IRQHandler + 0x08000864 TIM5_IRQHandler + 0x08000864 EXTI9_5_IRQHandler + 0x08000864 TIM9_IRQHandler + 0x08000864 TAMPER_STAMP_IRQHandler + 0x08000864 RTC_WKUP_IRQHandler + 0x08000864 SPI2_IRQHandler + 0x08000864 DMA2_Channel5_IRQHandler + 0x08000864 DMA1_Channel5_IRQHandler + 0x08000864 USB_LP_IRQHandler + 0x08000864 EXTI4_IRQHandler + 0x08000864 DMA1_Channel3_IRQHandler + 0x08000864 COMP_IRQHandler + 0x08000864 WWDG_IRQHandler + 0x08000864 TIM2_IRQHandler + 0x08000864 DAC_IRQHandler + 0x08000864 EXTI1_IRQHandler + 0x08000864 TIM11_IRQHandler + 0x08000864 USART2_IRQHandler + 0x08000864 I2C2_ER_IRQHandler + 0x08000864 DMA1_Channel2_IRQHandler + 0x08000864 FLASH_IRQHandler + 0x08000864 USART1_IRQHandler + 0x08000864 SPI3_IRQHandler + 0x08000864 I2C1_ER_IRQHandler + 0x08000864 RTC_Alarm_IRQHandler .text.MAX7219_Init - 0x080007f2 0x2a ./Drivers/7Seg_MAX7219/max7219.o - 0x080007f2 MAX7219_Init + 0x08000866 0x2a ./Drivers/7Seg_MAX7219/max7219.o + 0x08000866 MAX7219_Init .text.MAX7219_ShutdownStop - 0x0800081c 0x10 ./Drivers/7Seg_MAX7219/max7219.o - 0x0800081c MAX7219_ShutdownStop + 0x08000890 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x08000890 MAX7219_ShutdownStop .text.MAX7219_DisplayTestStop - 0x0800082c 0x10 ./Drivers/7Seg_MAX7219/max7219.o - 0x0800082c MAX7219_DisplayTestStop + 0x080008a0 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x080008a0 MAX7219_DisplayTestStop .text.MAX7219_SetBrightness - 0x0800083c 0x24 ./Drivers/7Seg_MAX7219/max7219.o - 0x0800083c MAX7219_SetBrightness + 0x080008b0 0x24 ./Drivers/7Seg_MAX7219/max7219.o + 0x080008b0 MAX7219_SetBrightness .text.MAX7219_Clear - 0x08000860 0x2c ./Drivers/7Seg_MAX7219/max7219.o - 0x08000860 MAX7219_Clear + 0x080008d4 0x2c ./Drivers/7Seg_MAX7219/max7219.o + 0x080008d4 MAX7219_Clear .text.MAX7219_DisplayChar - 0x0800088c 0x2c ./Drivers/7Seg_MAX7219/max7219.o - 0x0800088c MAX7219_DisplayChar + 0x08000900 0x2c ./Drivers/7Seg_MAX7219/max7219.o + 0x08000900 MAX7219_DisplayChar .text.MAX7219_Write - 0x080008b8 0x3c ./Drivers/7Seg_MAX7219/max7219.o - 0x080008b8 MAX7219_Write + 0x0800092c 0x3c ./Drivers/7Seg_MAX7219/max7219.o + 0x0800092c MAX7219_Write .text.MAX7219_SendByte - 0x080008f4 0x24 ./Drivers/7Seg_MAX7219/max7219.o + 0x08000968 0x24 ./Drivers/7Seg_MAX7219/max7219.o .text.HAL_Init - 0x08000918 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x08000918 HAL_Init + 0x0800098c 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0800098c HAL_Init .text.HAL_InitTick - 0x08000948 0x74 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x08000948 HAL_InitTick + 0x080009bc 0x74 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x080009bc HAL_InitTick .text.HAL_IncTick - 0x080009bc 0x24 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x080009bc HAL_IncTick + 0x08000a30 0x24 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a30 HAL_IncTick .text.HAL_GetTick - 0x080009e0 0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x080009e0 HAL_GetTick + 0x08000a54 0x14 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a54 HAL_GetTick + .text.HAL_Delay + 0x08000a68 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x08000a68 HAL_Delay .text.__NVIC_SetPriorityGrouping - 0x080009f4 0x48 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000aac 0x48 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o .text.__NVIC_GetPriorityGrouping - 0x08000a3c 0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000af4 0x1c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o .text.__NVIC_SetPriority - 0x08000a58 0x54 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000b10 0x54 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o .text.NVIC_EncodePriority - 0x08000aac 0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000b64 0x64 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o .text.SysTick_Config - 0x08000b10 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000bc8 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o .text.HAL_NVIC_SetPriorityGrouping - 0x08000b54 0x16 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - 0x08000b54 HAL_NVIC_SetPriorityGrouping + 0x08000c0c 0x16 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000c0c HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x08000b6a 0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - 0x08000b6a HAL_NVIC_SetPriority + 0x08000c22 0x38 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000c22 HAL_NVIC_SetPriority .text.HAL_SYSTICK_Config - 0x08000ba2 0x18 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - 0x08000ba2 HAL_SYSTICK_Config - *fill* 0x08000bba 0x2 + 0x08000c5a 0x18 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x08000c5a HAL_SYSTICK_Config + *fill* 0x08000c72 0x2 .text.HAL_GPIO_Init - 0x08000bbc 0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - 0x08000bbc HAL_GPIO_Init + 0x08000c74 0x320 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000c74 HAL_GPIO_Init .text.HAL_GPIO_WritePin - 0x08000edc 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - 0x08000edc HAL_GPIO_WritePin + 0x08000f94 0x30 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x08000f94 HAL_GPIO_WritePin .text.HAL_RCC_OscConfig - 0x08000f0c 0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x08000f0c HAL_RCC_OscConfig + 0x08000fc4 0x660 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08000fc4 HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x0800156c 0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x0800156c HAL_RCC_ClockConfig + 0x08001624 0x268 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08001624 HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x080017d4 0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x080017d4 HAL_RCC_GetSysClockFreq + 0x0800188c 0x17c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0800188c HAL_RCC_GetSysClockFreq .text.RCC_SetFlashLatencyFromMSIRange - 0x08001950 0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x08001a08 0xc0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o .text.HAL_SPI_Init - 0x08001a10 0x112 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o - 0x08001a10 HAL_SPI_Init + 0x08001ac8 0x112 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001ac8 HAL_SPI_Init .text.HAL_SPI_Transmit - 0x08001b22 0x288 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o - 0x08001b22 HAL_SPI_Transmit - *fill* 0x08001daa 0x2 + 0x08001bda 0x288 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001bda HAL_SPI_Transmit + *fill* 0x08001e62 0x2 .text.SPI_WaitFlagStateUntilTimeout - 0x08001dac 0x110 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x08001e64 0x110 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o .text.SPI_EndRxTxTransaction - 0x08001ebc 0xa8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o - .text.memset 0x08001f64 0x10 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) - 0x08001f64 memset + 0x08001f74 0xa8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .text.memset 0x0800201c 0x10 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + 0x0800201c memset .text.__libc_init_array - 0x08001f74 0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) - 0x08001f74 __libc_init_array + 0x0800202c 0x48 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + 0x0800202c __libc_init_array *(.glue_7) - .glue_7 0x08001fbc 0x0 linker stubs + .glue_7 0x08002074 0x0 linker stubs *(.glue_7t) - .glue_7t 0x08001fbc 0x0 linker stubs + .glue_7t 0x08002074 0x0 linker stubs *(.eh_frame) - .eh_frame 0x08001fbc 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + .eh_frame 0x08002074 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o *(.init) - .init 0x08001fbc 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o - 0x08001fbc _init - .init 0x08001fc0 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + .init 0x08002074 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x08002074 _init + .init 0x08002078 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o *(.fini) - .fini 0x08001fc8 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o - 0x08001fc8 _fini - .fini 0x08001fcc 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o - 0x08001fd4 . = ALIGN (0x4) - 0x08001fd4 _etext = . + .fini 0x08002080 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crti.o + 0x08002080 _fini + .fini 0x08002084 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtn.o + 0x0800208c . = ALIGN (0x4) + 0x0800208c _etext = . -.vfp11_veneer 0x08001fd4 0x0 - .vfp11_veneer 0x08001fd4 0x0 linker stubs +.vfp11_veneer 0x0800208c 0x0 + .vfp11_veneer 0x0800208c 0x0 linker stubs -.v4_bx 0x08001fd4 0x0 - .v4_bx 0x08001fd4 0x0 linker stubs +.v4_bx 0x0800208c 0x0 + .v4_bx 0x0800208c 0x0 linker stubs -.iplt 0x08001fd4 0x0 - .iplt 0x08001fd4 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o +.iplt 0x0800208c 0x0 + .iplt 0x0800208c 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o -.rodata 0x08001fd4 0x2c - 0x08001fd4 . = ALIGN (0x4) +.rodata 0x0800208c 0x2c + 0x0800208c . = ALIGN (0x4) *(.rodata) *(.rodata*) .rodata.PLLMulTable - 0x08001fd4 0x9 ./Core/Src/system_stm32l1xx.o - 0x08001fd4 PLLMulTable - *fill* 0x08001fdd 0x3 + 0x0800208c 0x9 ./Core/Src/system_stm32l1xx.o + 0x0800208c PLLMulTable + *fill* 0x08002095 0x3 .rodata.AHBPrescTable - 0x08001fe0 0x10 ./Core/Src/system_stm32l1xx.o - 0x08001fe0 AHBPrescTable + 0x08002098 0x10 ./Core/Src/system_stm32l1xx.o + 0x08002098 AHBPrescTable .rodata.conv_7seg - 0x08001ff0 0x10 ./Drivers/7Seg_MAX7219/max7219.o - 0x08001ff0 conv_7seg - 0x08002000 . = ALIGN (0x4) + 0x080020a8 0x10 ./Drivers/7Seg_MAX7219/max7219.o + 0x080020a8 conv_7seg + 0x080020b8 . = ALIGN (0x4) -.ARM.extab 0x08002000 0x0 - 0x08002000 . = ALIGN (0x4) +.ARM.extab 0x080020b8 0x0 + 0x080020b8 . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x08002000 . = ALIGN (0x4) + 0x080020b8 . = ALIGN (0x4) -.ARM 0x08002000 0x8 - 0x08002000 . = ALIGN (0x4) - 0x08002000 __exidx_start = . +.ARM 0x080020b8 0x8 + 0x080020b8 . = ALIGN (0x4) + 0x080020b8 __exidx_start = . *(.ARM.exidx*) - .ARM.exidx 0x08002000 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) - 0x08002008 __exidx_end = . - 0x08002008 . = ALIGN (0x4) + .ARM.exidx 0x080020b8 0x8 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) + 0x080020c0 __exidx_end = . + 0x080020c0 . = ALIGN (0x4) -.preinit_array 0x08002008 0x0 - 0x08002008 . = ALIGN (0x4) - 0x08002008 PROVIDE (__preinit_array_start = .) +.preinit_array 0x080020c0 0x0 + 0x080020c0 . = ALIGN (0x4) + 0x080020c0 PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x08002008 PROVIDE (__preinit_array_end = .) - 0x08002008 . = ALIGN (0x4) + 0x080020c0 PROVIDE (__preinit_array_end = .) + 0x080020c0 . = ALIGN (0x4) -.init_array 0x08002008 0x4 - 0x08002008 . = ALIGN (0x4) - 0x08002008 PROVIDE (__init_array_start = .) +.init_array 0x080020c0 0x4 + 0x080020c0 . = ALIGN (0x4) + 0x080020c0 PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x08002008 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o - 0x0800200c PROVIDE (__init_array_end = .) - 0x0800200c . = ALIGN (0x4) + .init_array 0x080020c0 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + 0x080020c4 PROVIDE (__init_array_end = .) + 0x080020c4 . = ALIGN (0x4) -.fini_array 0x0800200c 0x4 - 0x0800200c . = ALIGN (0x4) +.fini_array 0x080020c4 0x4 + 0x080020c4 . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x0800200c 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o + .fini_array 0x080020c4 0x4 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x08002010 . = ALIGN (0x4) - 0x08002010 _sidata = LOADADDR (.data) + 0x080020c8 . = ALIGN (0x4) + 0x080020c8 _sidata = LOADADDR (.data) -.rel.dyn 0x08002010 0x0 - .rel.iplt 0x08002010 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o +.rel.dyn 0x080020c8 0x0 + .rel.iplt 0x080020c8 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o -.data 0x20000000 0xc load address 0x08002010 +.data 0x20000000 0xc load address 0x080020c8 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) @@ -2627,11 +2630,11 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id 0x2000000c . = ALIGN (0x4) 0x2000000c _edata = . -.igot.plt 0x2000000c 0x0 load address 0x0800201c +.igot.plt 0x2000000c 0x0 load address 0x080020d4 .igot.plt 0x2000000c 0x0 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/crtbegin.o 0x2000000c . = ALIGN (0x4) -.bss 0x2000000c 0x78 load address 0x0800201c +.bss 0x2000000c 0x78 load address 0x080020d4 0x2000000c _sbss = . 0x2000000c __bss_start__ = _sbss *(.bss) @@ -2647,7 +2650,7 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id 0x20000084 __bss_end__ = _ebss ._user_heap_stack - 0x20000084 0x604 load address 0x0800201c + 0x20000084 0x604 load address 0x080020d4 0x20000088 . = ALIGN (0x8) *fill* 0x20000084 0x4 [!provide] PROVIDE (end = .) @@ -2710,153 +2713,153 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libm.a LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a -.debug_info 0x00000000 0x56d5 - .debug_info 0x00000000 0xae6 ./Core/Src/main.o - .debug_info 0x00000ae6 0x828 ./Core/Src/stm32l1xx_hal_msp.o - .debug_info 0x0000130e 0x113 ./Core/Src/stm32l1xx_it.o - .debug_info 0x00001421 0x27c ./Core/Src/system_stm32l1xx.o - .debug_info 0x0000169d 0x30 ./Core/Startup/startup_stm32l152retx.o - .debug_info 0x000016cd 0x80e ./Drivers/7Seg_MAX7219/max7219.o - .debug_info 0x00001edb 0x6ef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_info 0x000025ca 0xce5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_info 0x000032af 0x5b2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_info 0x00003861 0x99b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_info 0x000041fc 0x14d9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +.debug_info 0x00000000 0x573e + .debug_info 0x00000000 0xb4f ./Core/Src/main.o + .debug_info 0x00000b4f 0x828 ./Core/Src/stm32l1xx_hal_msp.o + .debug_info 0x00001377 0x113 ./Core/Src/stm32l1xx_it.o + .debug_info 0x0000148a 0x27c ./Core/Src/system_stm32l1xx.o + .debug_info 0x00001706 0x30 ./Core/Startup/startup_stm32l152retx.o + .debug_info 0x00001736 0x80e ./Drivers/7Seg_MAX7219/max7219.o + .debug_info 0x00001f44 0x6ef ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_info 0x00002633 0xce5 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_info 0x00003318 0x5b2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_info 0x000038ca 0x99b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_info 0x00004265 0x14d9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o -.debug_abbrev 0x00000000 0x144c - .debug_abbrev 0x00000000 0x26c ./Core/Src/main.o - .debug_abbrev 0x0000026c 0x1ad ./Core/Src/stm32l1xx_hal_msp.o - .debug_abbrev 0x00000419 0x73 ./Core/Src/stm32l1xx_it.o - .debug_abbrev 0x0000048c 0x11c ./Core/Src/system_stm32l1xx.o - .debug_abbrev 0x000005a8 0x24 ./Core/Startup/startup_stm32l152retx.o - .debug_abbrev 0x000005cc 0x1e9 ./Drivers/7Seg_MAX7219/max7219.o - .debug_abbrev 0x000007b5 0x275 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_abbrev 0x00000a2a 0x31c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_abbrev 0x00000d46 0x1d4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_abbrev 0x00000f1a 0x2b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_abbrev 0x000011d2 0x27a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +.debug_abbrev 0x00000000 0x145f + .debug_abbrev 0x00000000 0x27f ./Core/Src/main.o + .debug_abbrev 0x0000027f 0x1ad ./Core/Src/stm32l1xx_hal_msp.o + .debug_abbrev 0x0000042c 0x73 ./Core/Src/stm32l1xx_it.o + .debug_abbrev 0x0000049f 0x11c ./Core/Src/system_stm32l1xx.o + .debug_abbrev 0x000005bb 0x24 ./Core/Startup/startup_stm32l152retx.o + .debug_abbrev 0x000005df 0x1e9 ./Drivers/7Seg_MAX7219/max7219.o + .debug_abbrev 0x000007c8 0x275 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_abbrev 0x00000a3d 0x31c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_abbrev 0x00000d59 0x1d4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_abbrev 0x00000f2d 0x2b8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_abbrev 0x000011e5 0x27a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o -.debug_aranges 0x00000000 0x658 +.debug_aranges 0x00000000 0x660 .debug_aranges - 0x00000000 0x40 ./Core/Src/main.o + 0x00000000 0x48 ./Core/Src/main.o .debug_aranges - 0x00000040 0x30 ./Core/Src/stm32l1xx_hal_msp.o + 0x00000048 0x30 ./Core/Src/stm32l1xx_hal_msp.o .debug_aranges - 0x00000070 0x60 ./Core/Src/stm32l1xx_it.o + 0x00000078 0x60 ./Core/Src/stm32l1xx_it.o .debug_aranges - 0x000000d0 0x28 ./Core/Src/system_stm32l1xx.o + 0x000000d8 0x28 ./Core/Src/system_stm32l1xx.o .debug_aranges - 0x000000f8 0x28 ./Core/Startup/startup_stm32l152retx.o + 0x00000100 0x28 ./Core/Startup/startup_stm32l152retx.o .debug_aranges - 0x00000120 0x78 ./Drivers/7Seg_MAX7219/max7219.o + 0x00000128 0x78 ./Drivers/7Seg_MAX7219/max7219.o .debug_aranges - 0x00000198 0xe0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x000001a0 0xe0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o .debug_aranges - 0x00000278 0x128 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x00000280 0x128 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o .debug_aranges - 0x000003a0 0x58 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x000003a8 0x58 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o .debug_aranges - 0x000003f8 0x90 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x00000400 0x90 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o .debug_aranges - 0x00000488 0x1d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x00000490 0x1d0 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o .debug_rnglists - 0x00000000 0x4ae + 0x00000000 0x4b4 .debug_rnglists - 0x00000000 0x2c ./Core/Src/main.o + 0x00000000 0x32 ./Core/Src/main.o .debug_rnglists - 0x0000002c 0x20 ./Core/Src/stm32l1xx_hal_msp.o + 0x00000032 0x20 ./Core/Src/stm32l1xx_hal_msp.o .debug_rnglists - 0x0000004c 0x43 ./Core/Src/stm32l1xx_it.o + 0x00000052 0x43 ./Core/Src/stm32l1xx_it.o .debug_rnglists - 0x0000008f 0x1a ./Core/Src/system_stm32l1xx.o + 0x00000095 0x1a ./Core/Src/system_stm32l1xx.o .debug_rnglists - 0x000000a9 0x19 ./Core/Startup/startup_stm32l152retx.o + 0x000000af 0x19 ./Core/Startup/startup_stm32l152retx.o .debug_rnglists - 0x000000c2 0x55 ./Drivers/7Seg_MAX7219/max7219.o + 0x000000c8 0x55 ./Drivers/7Seg_MAX7219/max7219.o .debug_rnglists - 0x00000117 0xa3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000011d 0xa3 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o .debug_rnglists - 0x000001ba 0xd9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x000001c0 0xd9 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o .debug_rnglists - 0x00000293 0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x00000299 0x3f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o .debug_rnglists - 0x000002d2 0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x000002d8 0x6d ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o .debug_rnglists - 0x0000033f 0x16f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + 0x00000345 0x16f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o -.debug_macro 0x00000000 0x14998 - .debug_macro 0x00000000 0x1ae ./Core/Src/main.o - .debug_macro 0x000001ae 0xacc ./Core/Src/main.o - .debug_macro 0x00000c7a 0x109 ./Core/Src/main.o - .debug_macro 0x00000d83 0x2e ./Core/Src/main.o - .debug_macro 0x00000db1 0x22 ./Core/Src/main.o - .debug_macro 0x00000dd3 0x22 ./Core/Src/main.o - .debug_macro 0x00000df5 0x8e ./Core/Src/main.o - .debug_macro 0x00000e83 0x51 ./Core/Src/main.o - .debug_macro 0x00000ed4 0x103 ./Core/Src/main.o - .debug_macro 0x00000fd7 0x6a ./Core/Src/main.o - .debug_macro 0x00001041 0x1df ./Core/Src/main.o - .debug_macro 0x00001220 0x1c ./Core/Src/main.o - .debug_macro 0x0000123c 0x22 ./Core/Src/main.o - .debug_macro 0x0000125e 0xbd ./Core/Src/main.o - .debug_macro 0x0000131b 0xe49 ./Core/Src/main.o - .debug_macro 0x00002164 0x11f ./Core/Src/main.o - .debug_macro 0x00002283 0xb7a1 ./Core/Src/main.o - .debug_macro 0x0000da24 0x6d ./Core/Src/main.o - .debug_macro 0x0000da91 0x34e1 ./Core/Src/main.o - .debug_macro 0x00010f72 0x190 ./Core/Src/main.o - .debug_macro 0x00011102 0x5b ./Core/Src/main.o - .debug_macro 0x0001115d 0xe37 ./Core/Src/main.o - .debug_macro 0x00011f94 0x35b ./Core/Src/main.o - .debug_macro 0x000122ef 0x1b8 ./Core/Src/main.o - .debug_macro 0x000124a7 0xc5 ./Core/Src/main.o - .debug_macro 0x0001256c 0x21e ./Core/Src/main.o - .debug_macro 0x0001278a 0x236 ./Core/Src/main.o - .debug_macro 0x000129c0 0x115 ./Core/Src/main.o - .debug_macro 0x00012ad5 0x567 ./Core/Src/main.o - .debug_macro 0x0001303c 0x1e9 ./Core/Src/main.o - .debug_macro 0x00013225 0x22 ./Core/Src/main.o - .debug_macro 0x00013247 0x225 ./Core/Src/main.o - .debug_macro 0x0001346c 0x170 ./Core/Src/main.o - .debug_macro 0x000135dc 0x492 ./Core/Src/main.o - .debug_macro 0x00013a6e 0x10 ./Core/Src/main.o - .debug_macro 0x00013a7e 0x1a5 ./Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x00013c23 0x1af ./Core/Src/stm32l1xx_it.o - .debug_macro 0x00013dd2 0x19b ./Core/Src/system_stm32l1xx.o - .debug_macro 0x00013f6d 0x1d8 ./Drivers/7Seg_MAX7219/max7219.o - .debug_macro 0x00014145 0x1bf ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x00014304 0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0001449f 0x1a2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x00014641 0x1ad ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x000147ee 0x1aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +.debug_macro 0x00000000 0x1499e + .debug_macro 0x00000000 0x1b4 ./Core/Src/main.o + .debug_macro 0x000001b4 0xacc ./Core/Src/main.o + .debug_macro 0x00000c80 0x109 ./Core/Src/main.o + .debug_macro 0x00000d89 0x2e ./Core/Src/main.o + .debug_macro 0x00000db7 0x22 ./Core/Src/main.o + .debug_macro 0x00000dd9 0x22 ./Core/Src/main.o + .debug_macro 0x00000dfb 0x8e ./Core/Src/main.o + .debug_macro 0x00000e89 0x51 ./Core/Src/main.o + .debug_macro 0x00000eda 0x103 ./Core/Src/main.o + .debug_macro 0x00000fdd 0x6a ./Core/Src/main.o + .debug_macro 0x00001047 0x1df ./Core/Src/main.o + .debug_macro 0x00001226 0x1c ./Core/Src/main.o + .debug_macro 0x00001242 0x22 ./Core/Src/main.o + .debug_macro 0x00001264 0xbd ./Core/Src/main.o + .debug_macro 0x00001321 0xe49 ./Core/Src/main.o + .debug_macro 0x0000216a 0x11f ./Core/Src/main.o + .debug_macro 0x00002289 0xb7a1 ./Core/Src/main.o + .debug_macro 0x0000da2a 0x6d ./Core/Src/main.o + .debug_macro 0x0000da97 0x34e1 ./Core/Src/main.o + .debug_macro 0x00010f78 0x190 ./Core/Src/main.o + .debug_macro 0x00011108 0x5b ./Core/Src/main.o + .debug_macro 0x00011163 0xe37 ./Core/Src/main.o + .debug_macro 0x00011f9a 0x35b ./Core/Src/main.o + .debug_macro 0x000122f5 0x1b8 ./Core/Src/main.o + .debug_macro 0x000124ad 0xc5 ./Core/Src/main.o + .debug_macro 0x00012572 0x21e ./Core/Src/main.o + .debug_macro 0x00012790 0x236 ./Core/Src/main.o + .debug_macro 0x000129c6 0x115 ./Core/Src/main.o + .debug_macro 0x00012adb 0x567 ./Core/Src/main.o + .debug_macro 0x00013042 0x1e9 ./Core/Src/main.o + .debug_macro 0x0001322b 0x22 ./Core/Src/main.o + .debug_macro 0x0001324d 0x225 ./Core/Src/main.o + .debug_macro 0x00013472 0x170 ./Core/Src/main.o + .debug_macro 0x000135e2 0x492 ./Core/Src/main.o + .debug_macro 0x00013a74 0x10 ./Core/Src/main.o + .debug_macro 0x00013a84 0x1a5 ./Core/Src/stm32l1xx_hal_msp.o + .debug_macro 0x00013c29 0x1af ./Core/Src/stm32l1xx_it.o + .debug_macro 0x00013dd8 0x19b ./Core/Src/system_stm32l1xx.o + .debug_macro 0x00013f73 0x1d8 ./Drivers/7Seg_MAX7219/max7219.o + .debug_macro 0x0001414b 0x1bf ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_macro 0x0001430a 0x19b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_macro 0x000144a5 0x1a2 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_macro 0x00014647 0x1ad ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_macro 0x000147f4 0x1aa ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o -.debug_line 0x00000000 0x6f98 - .debug_line 0x00000000 0x79a ./Core/Src/main.o - .debug_line 0x0000079a 0x6dd ./Core/Src/stm32l1xx_hal_msp.o - .debug_line 0x00000e77 0x73e ./Core/Src/stm32l1xx_it.o - .debug_line 0x000015b5 0x730 ./Core/Src/system_stm32l1xx.o - .debug_line 0x00001ce5 0x79 ./Core/Startup/startup_stm32l152retx.o - .debug_line 0x00001d5e 0x7de ./Drivers/7Seg_MAX7219/max7219.o - .debug_line 0x0000253c 0x95b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_line 0x00002e97 0xc2a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_line 0x00003ac1 0x99f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_line 0x00004460 0xf1e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_line 0x0000537e 0x1c1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +.debug_line 0x00000000 0x6fc2 + .debug_line 0x00000000 0x7c4 ./Core/Src/main.o + .debug_line 0x000007c4 0x6dd ./Core/Src/stm32l1xx_hal_msp.o + .debug_line 0x00000ea1 0x73e ./Core/Src/stm32l1xx_it.o + .debug_line 0x000015df 0x730 ./Core/Src/system_stm32l1xx.o + .debug_line 0x00001d0f 0x79 ./Core/Startup/startup_stm32l152retx.o + .debug_line 0x00001d88 0x7de ./Drivers/7Seg_MAX7219/max7219.o + .debug_line 0x00002566 0x95b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_line 0x00002ec1 0xc2a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_line 0x00003aeb 0x99f ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_line 0x0000448a 0xf1e ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_line 0x000053a8 0x1c1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o -.debug_str 0x00000000 0x81117 - .debug_str 0x00000000 0x81117 ./Core/Src/main.o - 0x7fc64 (size before relaxing) - .debug_str 0x00081117 0x7fa10 ./Core/Src/stm32l1xx_hal_msp.o - .debug_str 0x00081117 0x7f5a7 ./Core/Src/stm32l1xx_it.o - .debug_str 0x00081117 0x7f5f8 ./Core/Src/system_stm32l1xx.o - .debug_str 0x00081117 0x8c ./Core/Startup/startup_stm32l152retx.o - .debug_str 0x00081117 0x7fb54 ./Drivers/7Seg_MAX7219/max7219.o - .debug_str 0x00081117 0x7fd20 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_str 0x00081117 0x7fe2c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_str 0x00081117 0x7f78b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_str 0x00081117 0x7fab4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_str 0x00081117 0x7ff1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o +.debug_str 0x00000000 0x81143 + .debug_str 0x00000000 0x81143 ./Core/Src/main.o + 0x7fc9a (size before relaxing) + .debug_str 0x00081143 0x7fa10 ./Core/Src/stm32l1xx_hal_msp.o + .debug_str 0x00081143 0x7f5a7 ./Core/Src/stm32l1xx_it.o + .debug_str 0x00081143 0x7f5f8 ./Core/Src/system_stm32l1xx.o + .debug_str 0x00081143 0x8c ./Core/Startup/startup_stm32l152retx.o + .debug_str 0x00081143 0x7fb54 ./Drivers/7Seg_MAX7219/max7219.o + .debug_str 0x00081143 0x7fd20 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_str 0x00081143 0x7fe2c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_str 0x00081143 0x7f78b ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_str 0x00081143 0x7fab4 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_str 0x00081143 0x7ff1a ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o .comment 0x00000000 0x43 .comment 0x00000000 0x43 ./Core/Src/main.o @@ -2871,21 +2874,21 @@ LOAD /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.id .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o .comment 0x00000043 0x44 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o -.debug_frame 0x00000000 0x1884 - .debug_frame 0x00000000 0xa8 ./Core/Src/main.o - .debug_frame 0x000000a8 0x80 ./Core/Src/stm32l1xx_hal_msp.o - .debug_frame 0x00000128 0x104 ./Core/Src/stm32l1xx_it.o - .debug_frame 0x0000022c 0x58 ./Core/Src/system_stm32l1xx.o - .debug_frame 0x00000284 0x198 ./Drivers/7Seg_MAX7219/max7219.o - .debug_frame 0x0000041c 0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_frame 0x00000758 0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_frame 0x00000c40 0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_frame 0x00000d8c 0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_frame 0x00000fb0 0x828 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o - .debug_frame 0x000017d8 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) - .debug_frame 0x000017f8 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) - .debug_frame 0x00001824 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) - .debug_frame 0x00001850 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) +.debug_frame 0x00000000 0x18ac + .debug_frame 0x00000000 0xd0 ./Core/Src/main.o + .debug_frame 0x000000d0 0x80 ./Core/Src/stm32l1xx_hal_msp.o + .debug_frame 0x00000150 0x104 ./Core/Src/stm32l1xx_it.o + .debug_frame 0x00000254 0x58 ./Core/Src/system_stm32l1xx.o + .debug_frame 0x000002ac 0x198 ./Drivers/7Seg_MAX7219/max7219.o + .debug_frame 0x00000444 0x33c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + .debug_frame 0x00000780 0x4e8 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + .debug_frame 0x00000c68 0x14c ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + .debug_frame 0x00000db4 0x224 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + .debug_frame 0x00000fd8 0x828 ./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.o + .debug_frame 0x00001800 0x20 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00001820 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/libc_nano.a(libc_a-init.o) + .debug_frame 0x0000184c 0x2c /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00001878 0x34 /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.macos64_1.0.0.202411102158/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7-m/nofp/libgcc.a(_udivmoddi4.o) .debug_line_str 0x00000000 0x70