TP1_BPLED1.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000013c 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00001794 0800013c 0800013c 0000113c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000001c 080018d0 080018d0 000028d0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080018ec 080018ec 0000300c 2**0 CONTENTS, READONLY 4 .ARM 00000008 080018ec 080018ec 000028ec 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 080018f4 080018f4 0000300c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080018f4 080018f4 000028f4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 080018f8 080018f8 000028f8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000000c 20000000 080018fc 00003000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000020 2000000c 08001908 0000300c 2**2 ALLOC 10 ._user_heap_stack 00000604 2000002c 08001908 0000302c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0000300c 2**0 CONTENTS, READONLY 12 .debug_info 00002e9c 00000000 00000000 00003035 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00000eaa 00000000 00000000 00005ed1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000418 00000000 00000000 00006d80 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 000002f0 00000000 00000000 00007198 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00014388 00000000 00000000 00007488 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00004ac1 00000000 00000000 0001b810 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0007f0f0 00000000 00000000 000202d1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 0009f3c1 2**0 CONTENTS, READONLY 20 .debug_frame 00000ee4 00000000 00000000 0009f404 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000006a 00000000 00000000 000a02e8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 0800013c <__do_global_dtors_aux>: 800013c: b510 push {r4, lr} 800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>) 8000140: 7823 ldrb r3, [r4, #0] 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> 8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>) 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> 8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>) 800014a: f3af 8000 nop.w 800014e: 2301 movs r3, #1 8000150: 7023 strb r3, [r4, #0] 8000152: bd10 pop {r4, pc} 8000154: 2000000c .word 0x2000000c 8000158: 00000000 .word 0x00000000 800015c: 080018b8 .word 0x080018b8 08000160 : 8000160: b508 push {r3, lr} 8000162: 4b03 ldr r3, [pc, #12] @ (8000170 ) 8000164: b11b cbz r3, 800016e 8000166: 4903 ldr r1, [pc, #12] @ (8000174 ) 8000168: 4803 ldr r0, [pc, #12] @ (8000178 ) 800016a: f3af 8000 nop.w 800016e: bd08 pop {r3, pc} 8000170: 00000000 .word 0x00000000 8000174: 20000010 .word 0x20000010 8000178: 080018b8 .word 0x080018b8 0800017c <__aeabi_uldivmod>: 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> 8000180: 2900 cmp r1, #0 8000182: bf08 it eq 8000184: 2800 cmpeq r0, #0 8000186: bf1c itt ne 8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000190: f000 b98c b.w 80004ac <__aeabi_idiv0> 8000194: f1ad 0c08 sub.w ip, sp, #8 8000198: e96d ce04 strd ip, lr, [sp, #-16]! 800019c: f000 f806 bl 80001ac <__udivmoddi4> 80001a0: f8dd e004 ldr.w lr, [sp, #4] 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] 80001a8: b004 add sp, #16 80001aa: 4770 bx lr 080001ac <__udivmoddi4>: 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80001b0: 9d08 ldr r5, [sp, #32] 80001b2: 468e mov lr, r1 80001b4: 4604 mov r4, r0 80001b6: 4688 mov r8, r1 80001b8: 2b00 cmp r3, #0 80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6> 80001bc: 428a cmp r2, r1 80001be: 4617 mov r7, r2 80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc> 80001c2: fab2 f682 clz r6, r2 80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30> 80001c8: f1c6 0320 rsb r3, r6, #32 80001cc: fa01 f806 lsl.w r8, r1, r6 80001d0: fa20 f303 lsr.w r3, r0, r3 80001d4: 40b7 lsls r7, r6 80001d6: ea43 0808 orr.w r8, r3, r8 80001da: 40b4 lsls r4, r6 80001dc: ea4f 4e17 mov.w lr, r7, lsr #16 80001e0: fbb8 f1fe udiv r1, r8, lr 80001e4: fa1f fc87 uxth.w ip, r7 80001e8: fb0e 8811 mls r8, lr, r1, r8 80001ec: fb01 f20c mul.w r2, r1, ip 80001f0: 0c23 lsrs r3, r4, #16 80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16 80001f6: 429a cmp r2, r3 80001f8: d909 bls.n 800020e <__udivmoddi4+0x62> 80001fa: 18fb adds r3, r7, r3 80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e> 8000204: 429a cmp r2, r3 8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e> 800020a: 3902 subs r1, #2 800020c: 443b add r3, r7 800020e: 1a9a subs r2, r3, r2 8000210: fbb2 f0fe udiv r0, r2, lr 8000214: fb0e 2210 mls r2, lr, r0, r2 8000218: fb00 fc0c mul.w ip, r0, ip 800021c: b2a3 uxth r3, r4 800021e: ea43 4302 orr.w r3, r3, r2, lsl #16 8000222: 459c cmp ip, r3 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> 8000226: 18fb adds r3, r7, r3 8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232> 8000230: 459c cmp ip, r3 8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232> 8000236: 443b add r3, r7 8000238: 3802 subs r0, #2 800023a: ea40 4001 orr.w r0, r0, r1, lsl #16 800023e: 2100 movs r1, #0 8000240: eba3 030c sub.w r3, r3, ip 8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2> 8000246: 2200 movs r2, #0 8000248: 40f3 lsrs r3, r6 800024a: e9c5 3200 strd r3, r2, [r5] 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000252: 428b cmp r3, r1 8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6> 8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0> 8000258: e9c5 0100 strd r0, r1, [r5] 800025c: 2100 movs r1, #0 800025e: 4608 mov r0, r1 8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2> 8000262: fab3 f183 clz r1, r3 8000266: 2900 cmp r1, #0 8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c> 800026a: 4573 cmp r3, lr 800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8> 800026e: 4282 cmp r2, r0 8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8> 8000274: 1a84 subs r4, r0, r2 8000276: eb6e 0203 sbc.w r2, lr, r3 800027a: 2001 movs r0, #1 800027c: 4690 mov r8, r2 800027e: 2d00 cmp r5, #0 8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2> 8000282: e9c5 4800 strd r4, r8, [r5] 8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2> 8000288: 2a00 cmp r2, #0 800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204> 800028e: fab2 f682 clz r6, r2 8000292: 2e00 cmp r6, #0 8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236> 8000298: 1a8a subs r2, r1, r2 800029a: 2101 movs r1, #1 800029c: 0c03 lsrs r3, r0, #16 800029e: ea4f 4e17 mov.w lr, r7, lsr #16 80002a2: b280 uxth r0, r0 80002a4: b2bc uxth r4, r7 80002a6: fbb2 fcfe udiv ip, r2, lr 80002aa: fb0e 221c mls r2, lr, ip, r2 80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16 80002b2: fb04 f20c mul.w r2, r4, ip 80002b6: 429a cmp r2, r3 80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e> 80002ba: 18fb adds r3, r7, r3 80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c> 80002c2: 429a cmp r2, r3 80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2> 80002c8: 46c4 mov ip, r8 80002ca: 1a9b subs r3, r3, r2 80002cc: fbb3 f2fe udiv r2, r3, lr 80002d0: fb0e 3312 mls r3, lr, r2, r3 80002d4: fb02 f404 mul.w r4, r2, r4 80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16 80002dc: 429c cmp r4, r3 80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144> 80002e0: 18fb adds r3, r7, r3 80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142> 80002e8: 429c cmp r4, r3 80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc> 80002ee: 4602 mov r2, r0 80002f0: 1b1b subs r3, r3, r4 80002f2: ea42 400c orr.w r0, r2, ip, lsl #16 80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98> 80002f8: f1c1 0620 rsb r6, r1, #32 80002fc: 408b lsls r3, r1 80002fe: fa22 f706 lsr.w r7, r2, r6 8000302: 431f orrs r7, r3 8000304: fa2e fa06 lsr.w sl, lr, r6 8000308: ea4f 4917 mov.w r9, r7, lsr #16 800030c: fbba f8f9 udiv r8, sl, r9 8000310: fa0e fe01 lsl.w lr, lr, r1 8000314: fa20 f306 lsr.w r3, r0, r6 8000318: fb09 aa18 mls sl, r9, r8, sl 800031c: fa1f fc87 uxth.w ip, r7 8000320: ea43 030e orr.w r3, r3, lr 8000324: fa00 fe01 lsl.w lr, r0, r1 8000328: fb08 f00c mul.w r0, r8, ip 800032c: 0c1c lsrs r4, r3, #16 800032e: ea44 440a orr.w r4, r4, sl, lsl #16 8000332: 42a0 cmp r0, r4 8000334: fa02 f201 lsl.w r2, r2, r1 8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4> 800033a: 193c adds r4, r7, r4 800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff 8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4> 8000344: 42a0 cmp r0, r4 8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4> 800034a: f1a8 0802 sub.w r8, r8, #2 800034e: 443c add r4, r7 8000350: 1a24 subs r4, r4, r0 8000352: b298 uxth r0, r3 8000354: fbb4 f3f9 udiv r3, r4, r9 8000358: fb09 4413 mls r4, r9, r3, r4 800035c: fb03 fc0c mul.w ip, r3, ip 8000360: ea40 4404 orr.w r4, r0, r4, lsl #16 8000364: 45a4 cmp ip, r4 8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0> 8000368: 193c adds r4, r7, r4 800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0> 8000372: 45a4 cmp ip, r4 8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0> 8000378: 3b02 subs r3, #2 800037a: 443c add r4, r7 800037c: ea43 4008 orr.w r0, r3, r8, lsl #16 8000380: eba4 040c sub.w r4, r4, ip 8000384: fba0 8c02 umull r8, ip, r0, r2 8000388: 4564 cmp r4, ip 800038a: 4643 mov r3, r8 800038c: 46e1 mov r9, ip 800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae> 8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa> 8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200> 8000394: ebbe 0203 subs.w r2, lr, r3 8000398: eb64 0409 sbc.w r4, r4, r9 800039c: fa04 f606 lsl.w r6, r4, r6 80003a0: fa22 f301 lsr.w r3, r2, r1 80003a4: 431e orrs r6, r3 80003a6: 40cc lsrs r4, r1 80003a8: e9c5 6400 strd r6, r4, [r5] 80003ac: 2100 movs r1, #0 80003ae: e74e b.n 800024e <__udivmoddi4+0xa2> 80003b0: fbb1 fcf2 udiv ip, r1, r2 80003b4: 0c01 lsrs r1, r0, #16 80003b6: ea41 410e orr.w r1, r1, lr, lsl #16 80003ba: b280 uxth r0, r0 80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16 80003c0: 463b mov r3, r7 80003c2: fbb1 f1f7 udiv r1, r1, r7 80003c6: 4638 mov r0, r7 80003c8: 463c mov r4, r7 80003ca: 46b8 mov r8, r7 80003cc: 46be mov lr, r7 80003ce: 2620 movs r6, #32 80003d0: eba2 0208 sub.w r2, r2, r8 80003d4: ea41 410c orr.w r1, r1, ip, lsl #16 80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa> 80003da: 4601 mov r1, r0 80003dc: e717 b.n 800020e <__udivmoddi4+0x62> 80003de: 4610 mov r0, r2 80003e0: e72b b.n 800023a <__udivmoddi4+0x8e> 80003e2: f1c6 0120 rsb r1, r6, #32 80003e6: fa2e fc01 lsr.w ip, lr, r1 80003ea: 40b7 lsls r7, r6 80003ec: fa0e fe06 lsl.w lr, lr, r6 80003f0: fa20 f101 lsr.w r1, r0, r1 80003f4: ea41 010e orr.w r1, r1, lr 80003f8: ea4f 4e17 mov.w lr, r7, lsr #16 80003fc: fbbc f8fe udiv r8, ip, lr 8000400: b2bc uxth r4, r7 8000402: fb0e cc18 mls ip, lr, r8, ip 8000406: fb08 f904 mul.w r9, r8, r4 800040a: 0c0a lsrs r2, r1, #16 800040c: ea42 420c orr.w r2, r2, ip, lsl #16 8000410: 40b0 lsls r0, r6 8000412: 4591 cmp r9, r2 8000414: ea4f 4310 mov.w r3, r0, lsr #16 8000418: b280 uxth r0, r0 800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee> 800041c: 18ba adds r2, r7, r2 800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c> 8000424: 4591 cmp r9, r2 8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc> 8000428: eba2 0209 sub.w r2, r2, r9 800042c: fbb2 f9fe udiv r9, r2, lr 8000430: fb09 f804 mul.w r8, r9, r4 8000434: fb0e 2a19 mls sl, lr, r9, r2 8000438: b28a uxth r2, r1 800043a: ea42 420a orr.w r2, r2, sl, lsl #16 800043e: 4542 cmp r2, r8 8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea> 8000442: 18ba adds r2, r7, r2 8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224> 800044a: 4542 cmp r2, r8 800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224> 800044e: f1a9 0102 sub.w r1, r9, #2 8000452: 443a add r2, r7 8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224> 8000456: 45c6 cmp lr, r8 8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6> 800045a: ebb8 0302 subs.w r3, r8, r2 800045e: eb6c 0c07 sbc.w ip, ip, r7 8000462: 3801 subs r0, #1 8000464: 46e1 mov r9, ip 8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6> 8000468: eba7 0909 sub.w r9, r7, r9 800046c: 444a add r2, r9 800046e: fbb2 f9fe udiv r9, r2, lr 8000472: f1a8 0c02 sub.w ip, r8, #2 8000476: fb09 f804 mul.w r8, r9, r4 800047a: e7db b.n 8000434 <__udivmoddi4+0x288> 800047c: 4603 mov r3, r0 800047e: e77d b.n 800037c <__udivmoddi4+0x1d0> 8000480: 46d0 mov r8, sl 8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4> 8000484: 4608 mov r0, r1 8000486: e6fa b.n 800027e <__udivmoddi4+0xd2> 8000488: 443b add r3, r7 800048a: 3a02 subs r2, #2 800048c: e730 b.n 80002f0 <__udivmoddi4+0x144> 800048e: f1ac 0c02 sub.w ip, ip, #2 8000492: 443b add r3, r7 8000494: e719 b.n 80002ca <__udivmoddi4+0x11e> 8000496: 4649 mov r1, r9 8000498: e79a b.n 80003d0 <__udivmoddi4+0x224> 800049a: eba2 0209 sub.w r2, r2, r9 800049e: fbb2 f9fe udiv r9, r2, lr 80004a2: 46c4 mov ip, r8 80004a4: fb09 f804 mul.w r8, r9, r4 80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288> 80004aa: bf00 nop 080004ac <__aeabi_idiv0>: 80004ac: 4770 bx lr 80004ae: bf00 nop 080004b0 : void eteint_LED(void); /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ void init_ports_LED(void) { 80004b0: b480 push {r7} 80004b2: af00 add r7, sp, #0 GPIOB->ODR |= 1<<0; 80004b4: 4b04 ldr r3, [pc, #16] @ (80004c8 ) 80004b6: 695b ldr r3, [r3, #20] 80004b8: 4a03 ldr r2, [pc, #12] @ (80004c8 ) 80004ba: f043 0301 orr.w r3, r3, #1 80004be: 6153 str r3, [r2, #20] } 80004c0: bf00 nop 80004c2: 46bd mov sp, r7 80004c4: bc80 pop {r7} 80004c6: 4770 bx lr 80004c8: 40020400 .word 0x40020400 080004cc : void init_ports_BP(void) { 80004cc: b480 push {r7} 80004ce: af00 add r7, sp, #0 GPIOA->MODER &= ~(1<<11); 80004d0: 4b04 ldr r3, [pc, #16] @ (80004e4 ) 80004d2: 681b ldr r3, [r3, #0] 80004d4: 4a03 ldr r2, [pc, #12] @ (80004e4 ) 80004d6: f423 6300 bic.w r3, r3, #2048 @ 0x800 80004da: 6013 str r3, [r2, #0] } 80004dc: bf00 nop 80004de: 46bd mov sp, r7 80004e0: bc80 pop {r7} 80004e2: 4770 bx lr 80004e4: 40020000 .word 0x40020000 080004e8
: /** * @brief The application entry point. * @retval int */ int main(void) { 80004e8: b580 push {r7, lr} 80004ea: b082 sub sp, #8 80004ec: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80004ee: f000 f93a bl 8000766 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80004f2: f000 f817 bl 8000524 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80004f6: f000 f85d bl 80005b4 /* USER CODE BEGIN 2 */ init_ports_LED(); 80004fa: f7ff ffd9 bl 80004b0 init_ports_BP(); 80004fe: f7ff ffe5 bl 80004cc eteint_LED(); HAL_Delay(1000); } #endif #ifdef V2 uint32_t bit_state = (GPIOA->IDR >> 11) & 1; 8000502: 4b06 ldr r3, [pc, #24] @ (800051c ) 8000504: 691b ldr r3, [r3, #16] 8000506: 0adb lsrs r3, r3, #11 8000508: f003 0301 and.w r3, r3, #1 800050c: 607b str r3, [r7, #4] GPIOB->BSRR = (1 << 16) | (bit_state << 0); 800050e: 4a04 ldr r2, [pc, #16] @ (8000520 ) 8000510: 687b ldr r3, [r7, #4] 8000512: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000516: 6193 str r3, [r2, #24] { 8000518: bf00 nop 800051a: e7f2 b.n 8000502 800051c: 40020000 .word 0x40020000 8000520: 40020400 .word 0x40020400 08000524 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000524: b580 push {r7, lr} 8000526: b092 sub sp, #72 @ 0x48 8000528: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800052a: f107 0314 add.w r3, r7, #20 800052e: 2234 movs r2, #52 @ 0x34 8000530: 2100 movs r1, #0 8000532: 4618 mov r0, r3 8000534: f001 f994 bl 8001860 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000538: 463b mov r3, r7 800053a: 2200 movs r2, #0 800053c: 601a str r2, [r3, #0] 800053e: 605a str r2, [r3, #4] 8000540: 609a str r2, [r3, #8] 8000542: 60da str r2, [r3, #12] 8000544: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8000546: 4b1a ldr r3, [pc, #104] @ (80005b0 ) 8000548: 681b ldr r3, [r3, #0] 800054a: f423 53c0 bic.w r3, r3, #6144 @ 0x1800 800054e: 4a18 ldr r2, [pc, #96] @ (80005b0 ) 8000550: f443 6300 orr.w r3, r3, #2048 @ 0x800 8000554: 6013 str r3, [r2, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; 8000556: 2310 movs r3, #16 8000558: 617b str r3, [r7, #20] RCC_OscInitStruct.MSIState = RCC_MSI_ON; 800055a: 2301 movs r3, #1 800055c: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.MSICalibrationValue = 0; 800055e: 2300 movs r3, #0 8000560: 633b str r3, [r7, #48] @ 0x30 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; 8000562: f44f 4320 mov.w r3, #40960 @ 0xa000 8000566: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000568: 2300 movs r3, #0 800056a: 63bb str r3, [r7, #56] @ 0x38 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800056c: f107 0314 add.w r3, r7, #20 8000570: 4618 mov r0, r3 8000572: f000 fbf3 bl 8000d5c 8000576: 4603 mov r3, r0 8000578: 2b00 cmp r3, #0 800057a: d001 beq.n 8000580 { Error_Handler(); 800057c: f000 f868 bl 8000650 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000580: 230f movs r3, #15 8000582: 603b str r3, [r7, #0] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; 8000584: 2300 movs r3, #0 8000586: 607b str r3, [r7, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000588: 2300 movs r3, #0 800058a: 60bb str r3, [r7, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800058c: 2300 movs r3, #0 800058e: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000590: 2300 movs r3, #0 8000592: 613b str r3, [r7, #16] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8000594: 463b mov r3, r7 8000596: 2100 movs r1, #0 8000598: 4618 mov r0, r3 800059a: f000 ff0f bl 80013bc 800059e: 4603 mov r3, r0 80005a0: 2b00 cmp r3, #0 80005a2: d001 beq.n 80005a8 { Error_Handler(); 80005a4: f000 f854 bl 8000650 } } 80005a8: bf00 nop 80005aa: 3748 adds r7, #72 @ 0x48 80005ac: 46bd mov sp, r7 80005ae: bd80 pop {r7, pc} 80005b0: 40007000 .word 0x40007000 080005b4 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80005b4: b580 push {r7, lr} 80005b6: b088 sub sp, #32 80005b8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80005ba: f107 030c add.w r3, r7, #12 80005be: 2200 movs r2, #0 80005c0: 601a str r2, [r3, #0] 80005c2: 605a str r2, [r3, #4] 80005c4: 609a str r2, [r3, #8] 80005c6: 60da str r2, [r3, #12] 80005c8: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); 80005ca: 4b1e ldr r3, [pc, #120] @ (8000644 ) 80005cc: 69db ldr r3, [r3, #28] 80005ce: 4a1d ldr r2, [pc, #116] @ (8000644 ) 80005d0: f043 0302 orr.w r3, r3, #2 80005d4: 61d3 str r3, [r2, #28] 80005d6: 4b1b ldr r3, [pc, #108] @ (8000644 ) 80005d8: 69db ldr r3, [r3, #28] 80005da: f003 0302 and.w r3, r3, #2 80005de: 60bb str r3, [r7, #8] 80005e0: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80005e2: 4b18 ldr r3, [pc, #96] @ (8000644 ) 80005e4: 69db ldr r3, [r3, #28] 80005e6: 4a17 ldr r2, [pc, #92] @ (8000644 ) 80005e8: f043 0301 orr.w r3, r3, #1 80005ec: 61d3 str r3, [r2, #28] 80005ee: 4b15 ldr r3, [pc, #84] @ (8000644 ) 80005f0: 69db ldr r3, [r3, #28] 80005f2: f003 0301 and.w r3, r3, #1 80005f6: 607b str r3, [r7, #4] 80005f8: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); 80005fa: 2200 movs r2, #0 80005fc: 2101 movs r1, #1 80005fe: 4812 ldr r0, [pc, #72] @ (8000648 ) 8000600: f000 fb94 bl 8000d2c /*Configure GPIO pin : PB0 */ GPIO_InitStruct.Pin = GPIO_PIN_0; 8000604: 2301 movs r3, #1 8000606: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000608: 2301 movs r3, #1 800060a: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800060c: 2300 movs r3, #0 800060e: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000610: 2300 movs r3, #0 8000612: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000614: f107 030c add.w r3, r7, #12 8000618: 4619 mov r1, r3 800061a: 480b ldr r0, [pc, #44] @ (8000648 ) 800061c: f000 f9f6 bl 8000a0c /*Configure GPIO pin : PA11 */ GPIO_InitStruct.Pin = GPIO_PIN_11; 8000620: f44f 6300 mov.w r3, #2048 @ 0x800 8000624: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000626: 2300 movs r3, #0 8000628: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800062a: 2300 movs r3, #0 800062c: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800062e: f107 030c add.w r3, r7, #12 8000632: 4619 mov r1, r3 8000634: 4805 ldr r0, [pc, #20] @ (800064c ) 8000636: f000 f9e9 bl 8000a0c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 800063a: bf00 nop 800063c: 3720 adds r7, #32 800063e: 46bd mov sp, r7 8000640: bd80 pop {r7, pc} 8000642: bf00 nop 8000644: 40023800 .word 0x40023800 8000648: 40020400 .word 0x40020400 800064c: 40020000 .word 0x40020000 08000650 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000650: b480 push {r7} 8000652: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000654: b672 cpsid i } 8000656: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000658: bf00 nop 800065a: e7fd b.n 8000658 0800065c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800065c: b480 push {r7} 800065e: b085 sub sp, #20 8000660: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_COMP_CLK_ENABLE(); 8000662: 4b14 ldr r3, [pc, #80] @ (80006b4 ) 8000664: 6a5b ldr r3, [r3, #36] @ 0x24 8000666: 4a13 ldr r2, [pc, #76] @ (80006b4 ) 8000668: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800066c: 6253 str r3, [r2, #36] @ 0x24 800066e: 4b11 ldr r3, [pc, #68] @ (80006b4 ) 8000670: 6a5b ldr r3, [r3, #36] @ 0x24 8000672: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8000676: 60fb str r3, [r7, #12] 8000678: 68fb ldr r3, [r7, #12] __HAL_RCC_SYSCFG_CLK_ENABLE(); 800067a: 4b0e ldr r3, [pc, #56] @ (80006b4 ) 800067c: 6a1b ldr r3, [r3, #32] 800067e: 4a0d ldr r2, [pc, #52] @ (80006b4 ) 8000680: f043 0301 orr.w r3, r3, #1 8000684: 6213 str r3, [r2, #32] 8000686: 4b0b ldr r3, [pc, #44] @ (80006b4 ) 8000688: 6a1b ldr r3, [r3, #32] 800068a: f003 0301 and.w r3, r3, #1 800068e: 60bb str r3, [r7, #8] 8000690: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8000692: 4b08 ldr r3, [pc, #32] @ (80006b4 ) 8000694: 6a5b ldr r3, [r3, #36] @ 0x24 8000696: 4a07 ldr r2, [pc, #28] @ (80006b4 ) 8000698: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800069c: 6253 str r3, [r2, #36] @ 0x24 800069e: 4b05 ldr r3, [pc, #20] @ (80006b4 ) 80006a0: 6a5b ldr r3, [r3, #36] @ 0x24 80006a2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80006a6: 607b str r3, [r7, #4] 80006a8: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80006aa: bf00 nop 80006ac: 3714 adds r7, #20 80006ae: 46bd mov sp, r7 80006b0: bc80 pop {r7} 80006b2: 4770 bx lr 80006b4: 40023800 .word 0x40023800 080006b8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80006b8: b480 push {r7} 80006ba: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80006bc: bf00 nop 80006be: e7fd b.n 80006bc 080006c0 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80006c0: b480 push {r7} 80006c2: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80006c4: bf00 nop 80006c6: e7fd b.n 80006c4 080006c8 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80006c8: b480 push {r7} 80006ca: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80006cc: bf00 nop 80006ce: e7fd b.n 80006cc 080006d0 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 80006d0: b480 push {r7} 80006d2: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80006d4: bf00 nop 80006d6: e7fd b.n 80006d4 080006d8 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80006d8: b480 push {r7} 80006da: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80006dc: bf00 nop 80006de: e7fd b.n 80006dc 080006e0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80006e0: b480 push {r7} 80006e2: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 80006e4: bf00 nop 80006e6: 46bd mov sp, r7 80006e8: bc80 pop {r7} 80006ea: 4770 bx lr 080006ec : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80006ec: b480 push {r7} 80006ee: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80006f0: bf00 nop 80006f2: 46bd mov sp, r7 80006f4: bc80 pop {r7} 80006f6: 4770 bx lr 080006f8 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80006f8: b480 push {r7} 80006fa: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80006fc: bf00 nop 80006fe: 46bd mov sp, r7 8000700: bc80 pop {r7} 8000702: 4770 bx lr 08000704 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000704: b580 push {r7, lr} 8000706: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000708: f000 f880 bl 800080c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800070c: bf00 nop 800070e: bd80 pop {r7, pc} 08000710 : * SystemCoreClock variable. * @param None * @retval None */ void SystemInit (void) { 8000710: b480 push {r7} 8000712: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000714: bf00 nop 8000716: 46bd mov sp, r7 8000718: bc80 pop {r7} 800071a: 4770 bx lr 0800071c : .type Reset_Handler, %function Reset_Handler: /* Call the clock system initialization function.*/ bl SystemInit 800071c: f7ff fff8 bl 8000710 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000720: 480b ldr r0, [pc, #44] @ (8000750 ) ldr r1, =_edata 8000722: 490c ldr r1, [pc, #48] @ (8000754 ) ldr r2, =_sidata 8000724: 4a0c ldr r2, [pc, #48] @ (8000758 ) movs r3, #0 8000726: 2300 movs r3, #0 b LoopCopyDataInit 8000728: e002 b.n 8000730 0800072a : CopyDataInit: ldr r4, [r2, r3] 800072a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 800072c: 50c4 str r4, [r0, r3] adds r3, r3, #4 800072e: 3304 adds r3, #4 08000730 : LoopCopyDataInit: adds r4, r0, r3 8000730: 18c4 adds r4, r0, r3 cmp r4, r1 8000732: 428c cmp r4, r1 bcc CopyDataInit 8000734: d3f9 bcc.n 800072a /* Zero fill the bss segment. */ ldr r2, =_sbss 8000736: 4a09 ldr r2, [pc, #36] @ (800075c ) ldr r4, =_ebss 8000738: 4c09 ldr r4, [pc, #36] @ (8000760 ) movs r3, #0 800073a: 2300 movs r3, #0 b LoopFillZerobss 800073c: e001 b.n 8000742 0800073e : FillZerobss: str r3, [r2] 800073e: 6013 str r3, [r2, #0] adds r2, r2, #4 8000740: 3204 adds r2, #4 08000742 : LoopFillZerobss: cmp r2, r4 8000742: 42a2 cmp r2, r4 bcc FillZerobss 8000744: d3fb bcc.n 800073e /* Call static constructors */ bl __libc_init_array 8000746: f001 f893 bl 8001870 <__libc_init_array> /* Call the application's entry point.*/ bl main 800074a: f7ff fecd bl 80004e8
bx lr 800074e: 4770 bx lr ldr r0, =_sdata 8000750: 20000000 .word 0x20000000 ldr r1, =_edata 8000754: 2000000c .word 0x2000000c ldr r2, =_sidata 8000758: 080018fc .word 0x080018fc ldr r2, =_sbss 800075c: 2000000c .word 0x2000000c ldr r4, =_ebss 8000760: 2000002c .word 0x2000002c 08000764 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000764: e7fe b.n 8000764 08000766 : * In the default implementation,Systick is used as source of time base. * the tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000766: b580 push {r7, lr} 8000768: b082 sub sp, #8 800076a: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 800076c: 2300 movs r3, #0 800076e: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000770: 2003 movs r0, #3 8000772: f000 f917 bl 80009a4 /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8000776: 200f movs r0, #15 8000778: f000 f80e bl 8000798 800077c: 4603 mov r3, r0 800077e: 2b00 cmp r3, #0 8000780: d002 beq.n 8000788 { status = HAL_ERROR; 8000782: 2301 movs r3, #1 8000784: 71fb strb r3, [r7, #7] 8000786: e001 b.n 800078c } else { /* Init the low level hardware */ HAL_MspInit(); 8000788: f7ff ff68 bl 800065c } /* Return function status */ return status; 800078c: 79fb ldrb r3, [r7, #7] } 800078e: 4618 mov r0, r3 8000790: 3708 adds r7, #8 8000792: 46bd mov sp, r7 8000794: bd80 pop {r7, pc} ... 08000798 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000798: b580 push {r7, lr} 800079a: b084 sub sp, #16 800079c: af00 add r7, sp, #0 800079e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80007a0: 2300 movs r3, #0 80007a2: 73fb strb r3, [r7, #15] if (uwTickFreq != 0U) 80007a4: 4b16 ldr r3, [pc, #88] @ (8000800 ) 80007a6: 681b ldr r3, [r3, #0] 80007a8: 2b00 cmp r3, #0 80007aa: d022 beq.n 80007f2 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) 80007ac: 4b15 ldr r3, [pc, #84] @ (8000804 ) 80007ae: 681a ldr r2, [r3, #0] 80007b0: 4b13 ldr r3, [pc, #76] @ (8000800 ) 80007b2: 681b ldr r3, [r3, #0] 80007b4: f44f 717a mov.w r1, #1000 @ 0x3e8 80007b8: fbb1 f3f3 udiv r3, r1, r3 80007bc: fbb2 f3f3 udiv r3, r2, r3 80007c0: 4618 mov r0, r3 80007c2: f000 f916 bl 80009f2 80007c6: 4603 mov r3, r0 80007c8: 2b00 cmp r3, #0 80007ca: d10f bne.n 80007ec { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80007cc: 687b ldr r3, [r7, #4] 80007ce: 2b0f cmp r3, #15 80007d0: d809 bhi.n 80007e6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80007d2: 2200 movs r2, #0 80007d4: 6879 ldr r1, [r7, #4] 80007d6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80007da: f000 f8ee bl 80009ba uwTickPrio = TickPriority; 80007de: 4a0a ldr r2, [pc, #40] @ (8000808 ) 80007e0: 687b ldr r3, [r7, #4] 80007e2: 6013 str r3, [r2, #0] 80007e4: e007 b.n 80007f6 } else { status = HAL_ERROR; 80007e6: 2301 movs r3, #1 80007e8: 73fb strb r3, [r7, #15] 80007ea: e004 b.n 80007f6 } } else { status = HAL_ERROR; 80007ec: 2301 movs r3, #1 80007ee: 73fb strb r3, [r7, #15] 80007f0: e001 b.n 80007f6 } } else { status = HAL_ERROR; 80007f2: 2301 movs r3, #1 80007f4: 73fb strb r3, [r7, #15] } /* Return function status */ return status; 80007f6: 7bfb ldrb r3, [r7, #15] } 80007f8: 4618 mov r0, r3 80007fa: 3710 adds r7, #16 80007fc: 46bd mov sp, r7 80007fe: bd80 pop {r7, pc} 8000800: 20000008 .word 0x20000008 8000804: 20000000 .word 0x20000000 8000808: 20000004 .word 0x20000004 0800080c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 800080c: b480 push {r7} 800080e: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000810: 4b05 ldr r3, [pc, #20] @ (8000828 ) 8000812: 681a ldr r2, [r3, #0] 8000814: 4b05 ldr r3, [pc, #20] @ (800082c ) 8000816: 681b ldr r3, [r3, #0] 8000818: 4413 add r3, r2 800081a: 4a03 ldr r2, [pc, #12] @ (8000828 ) 800081c: 6013 str r3, [r2, #0] } 800081e: bf00 nop 8000820: 46bd mov sp, r7 8000822: bc80 pop {r7} 8000824: 4770 bx lr 8000826: bf00 nop 8000828: 20000028 .word 0x20000028 800082c: 20000008 .word 0x20000008 08000830 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000830: b480 push {r7} 8000832: af00 add r7, sp, #0 return uwTick; 8000834: 4b02 ldr r3, [pc, #8] @ (8000840 ) 8000836: 681b ldr r3, [r3, #0] } 8000838: 4618 mov r0, r3 800083a: 46bd mov sp, r7 800083c: bc80 pop {r7} 800083e: 4770 bx lr 8000840: 20000028 .word 0x20000028 08000844 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000844: b480 push {r7} 8000846: b085 sub sp, #20 8000848: af00 add r7, sp, #0 800084a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800084c: 687b ldr r3, [r7, #4] 800084e: f003 0307 and.w r3, r3, #7 8000852: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000854: 4b0c ldr r3, [pc, #48] @ (8000888 <__NVIC_SetPriorityGrouping+0x44>) 8000856: 68db ldr r3, [r3, #12] 8000858: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800085a: 68ba ldr r2, [r7, #8] 800085c: f64f 03ff movw r3, #63743 @ 0xf8ff 8000860: 4013 ands r3, r2 8000862: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000864: 68fb ldr r3, [r7, #12] 8000866: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000868: 68bb ldr r3, [r7, #8] 800086a: 4313 orrs r3, r2 reg_value = (reg_value | 800086c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8000870: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000874: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000876: 4a04 ldr r2, [pc, #16] @ (8000888 <__NVIC_SetPriorityGrouping+0x44>) 8000878: 68bb ldr r3, [r7, #8] 800087a: 60d3 str r3, [r2, #12] } 800087c: bf00 nop 800087e: 3714 adds r7, #20 8000880: 46bd mov sp, r7 8000882: bc80 pop {r7} 8000884: 4770 bx lr 8000886: bf00 nop 8000888: e000ed00 .word 0xe000ed00 0800088c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 800088c: b480 push {r7} 800088e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000890: 4b04 ldr r3, [pc, #16] @ (80008a4 <__NVIC_GetPriorityGrouping+0x18>) 8000892: 68db ldr r3, [r3, #12] 8000894: 0a1b lsrs r3, r3, #8 8000896: f003 0307 and.w r3, r3, #7 } 800089a: 4618 mov r0, r3 800089c: 46bd mov sp, r7 800089e: bc80 pop {r7} 80008a0: 4770 bx lr 80008a2: bf00 nop 80008a4: e000ed00 .word 0xe000ed00 080008a8 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80008a8: b480 push {r7} 80008aa: b083 sub sp, #12 80008ac: af00 add r7, sp, #0 80008ae: 4603 mov r3, r0 80008b0: 6039 str r1, [r7, #0] 80008b2: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80008b4: f997 3007 ldrsb.w r3, [r7, #7] 80008b8: 2b00 cmp r3, #0 80008ba: db0a blt.n 80008d2 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80008bc: 683b ldr r3, [r7, #0] 80008be: b2da uxtb r2, r3 80008c0: 490c ldr r1, [pc, #48] @ (80008f4 <__NVIC_SetPriority+0x4c>) 80008c2: f997 3007 ldrsb.w r3, [r7, #7] 80008c6: 0112 lsls r2, r2, #4 80008c8: b2d2 uxtb r2, r2 80008ca: 440b add r3, r1 80008cc: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80008d0: e00a b.n 80008e8 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80008d2: 683b ldr r3, [r7, #0] 80008d4: b2da uxtb r2, r3 80008d6: 4908 ldr r1, [pc, #32] @ (80008f8 <__NVIC_SetPriority+0x50>) 80008d8: 79fb ldrb r3, [r7, #7] 80008da: f003 030f and.w r3, r3, #15 80008de: 3b04 subs r3, #4 80008e0: 0112 lsls r2, r2, #4 80008e2: b2d2 uxtb r2, r2 80008e4: 440b add r3, r1 80008e6: 761a strb r2, [r3, #24] } 80008e8: bf00 nop 80008ea: 370c adds r7, #12 80008ec: 46bd mov sp, r7 80008ee: bc80 pop {r7} 80008f0: 4770 bx lr 80008f2: bf00 nop 80008f4: e000e100 .word 0xe000e100 80008f8: e000ed00 .word 0xe000ed00 080008fc : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80008fc: b480 push {r7} 80008fe: b089 sub sp, #36 @ 0x24 8000900: af00 add r7, sp, #0 8000902: 60f8 str r0, [r7, #12] 8000904: 60b9 str r1, [r7, #8] 8000906: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000908: 68fb ldr r3, [r7, #12] 800090a: f003 0307 and.w r3, r3, #7 800090e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000910: 69fb ldr r3, [r7, #28] 8000912: f1c3 0307 rsb r3, r3, #7 8000916: 2b04 cmp r3, #4 8000918: bf28 it cs 800091a: 2304 movcs r3, #4 800091c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800091e: 69fb ldr r3, [r7, #28] 8000920: 3304 adds r3, #4 8000922: 2b06 cmp r3, #6 8000924: d902 bls.n 800092c 8000926: 69fb ldr r3, [r7, #28] 8000928: 3b03 subs r3, #3 800092a: e000 b.n 800092e 800092c: 2300 movs r3, #0 800092e: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000930: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000934: 69bb ldr r3, [r7, #24] 8000936: fa02 f303 lsl.w r3, r2, r3 800093a: 43da mvns r2, r3 800093c: 68bb ldr r3, [r7, #8] 800093e: 401a ands r2, r3 8000940: 697b ldr r3, [r7, #20] 8000942: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000944: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8000948: 697b ldr r3, [r7, #20] 800094a: fa01 f303 lsl.w r3, r1, r3 800094e: 43d9 mvns r1, r3 8000950: 687b ldr r3, [r7, #4] 8000952: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000954: 4313 orrs r3, r2 ); } 8000956: 4618 mov r0, r3 8000958: 3724 adds r7, #36 @ 0x24 800095a: 46bd mov sp, r7 800095c: bc80 pop {r7} 800095e: 4770 bx lr 08000960 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8000960: b580 push {r7, lr} 8000962: b082 sub sp, #8 8000964: af00 add r7, sp, #0 8000966: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000968: 687b ldr r3, [r7, #4] 800096a: 3b01 subs r3, #1 800096c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8000970: d301 bcc.n 8000976 { return (1UL); /* Reload value impossible */ 8000972: 2301 movs r3, #1 8000974: e00f b.n 8000996 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000976: 4a0a ldr r2, [pc, #40] @ (80009a0 ) 8000978: 687b ldr r3, [r7, #4] 800097a: 3b01 subs r3, #1 800097c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800097e: 210f movs r1, #15 8000980: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8000984: f7ff ff90 bl 80008a8 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000988: 4b05 ldr r3, [pc, #20] @ (80009a0 ) 800098a: 2200 movs r2, #0 800098c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800098e: 4b04 ldr r3, [pc, #16] @ (80009a0 ) 8000990: 2207 movs r2, #7 8000992: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000994: 2300 movs r3, #0 } 8000996: 4618 mov r0, r3 8000998: 3708 adds r7, #8 800099a: 46bd mov sp, r7 800099c: bd80 pop {r7, pc} 800099e: bf00 nop 80009a0: e000e010 .word 0xe000e010 080009a4 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80009a4: b580 push {r7, lr} 80009a6: b082 sub sp, #8 80009a8: af00 add r7, sp, #0 80009aa: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80009ac: 6878 ldr r0, [r7, #4] 80009ae: f7ff ff49 bl 8000844 <__NVIC_SetPriorityGrouping> } 80009b2: bf00 nop 80009b4: 3708 adds r7, #8 80009b6: 46bd mov sp, r7 80009b8: bd80 pop {r7, pc} 080009ba : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80009ba: b580 push {r7, lr} 80009bc: b086 sub sp, #24 80009be: af00 add r7, sp, #0 80009c0: 4603 mov r3, r0 80009c2: 60b9 str r1, [r7, #8] 80009c4: 607a str r2, [r7, #4] 80009c6: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; 80009c8: 2300 movs r3, #0 80009ca: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80009cc: f7ff ff5e bl 800088c <__NVIC_GetPriorityGrouping> 80009d0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80009d2: 687a ldr r2, [r7, #4] 80009d4: 68b9 ldr r1, [r7, #8] 80009d6: 6978 ldr r0, [r7, #20] 80009d8: f7ff ff90 bl 80008fc 80009dc: 4602 mov r2, r0 80009de: f997 300f ldrsb.w r3, [r7, #15] 80009e2: 4611 mov r1, r2 80009e4: 4618 mov r0, r3 80009e6: f7ff ff5f bl 80008a8 <__NVIC_SetPriority> } 80009ea: bf00 nop 80009ec: 3718 adds r7, #24 80009ee: 46bd mov sp, r7 80009f0: bd80 pop {r7, pc} 080009f2 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80009f2: b580 push {r7, lr} 80009f4: b082 sub sp, #8 80009f6: af00 add r7, sp, #0 80009f8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80009fa: 6878 ldr r0, [r7, #4] 80009fc: f7ff ffb0 bl 8000960 8000a00: 4603 mov r3, r0 } 8000a02: 4618 mov r0, r3 8000a04: 3708 adds r7, #8 8000a06: 46bd mov sp, r7 8000a08: bd80 pop {r7, pc} ... 08000a0c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000a0c: b480 push {r7} 8000a0e: b087 sub sp, #28 8000a10: af00 add r7, sp, #0 8000a12: 6078 str r0, [r7, #4] 8000a14: 6039 str r1, [r7, #0] uint32_t position = 0x00; 8000a16: 2300 movs r3, #0 8000a18: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00; 8000a1a: 2300 movs r3, #0 8000a1c: 60fb str r3, [r7, #12] uint32_t temp = 0x00; 8000a1e: 2300 movs r3, #0 8000a20: 613b str r3, [r7, #16] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0) 8000a22: e160 b.n 8000ce6 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1U << position); 8000a24: 683b ldr r3, [r7, #0] 8000a26: 681a ldr r2, [r3, #0] 8000a28: 2101 movs r1, #1 8000a2a: 697b ldr r3, [r7, #20] 8000a2c: fa01 f303 lsl.w r3, r1, r3 8000a30: 4013 ands r3, r2 8000a32: 60fb str r3, [r7, #12] if (iocurrent) 8000a34: 68fb ldr r3, [r7, #12] 8000a36: 2b00 cmp r3, #0 8000a38: f000 8152 beq.w 8000ce0 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000a3c: 683b ldr r3, [r7, #0] 8000a3e: 685b ldr r3, [r3, #4] 8000a40: f003 0303 and.w r3, r3, #3 8000a44: 2b01 cmp r3, #1 8000a46: d005 beq.n 8000a54 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8000a48: 683b ldr r3, [r7, #0] 8000a4a: 685b ldr r3, [r3, #4] 8000a4c: f003 0303 and.w r3, r3, #3 if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8000a50: 2b02 cmp r3, #2 8000a52: d130 bne.n 8000ab6 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8000a54: 687b ldr r3, [r7, #4] 8000a56: 689b ldr r3, [r3, #8] 8000a58: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); 8000a5a: 697b ldr r3, [r7, #20] 8000a5c: 005b lsls r3, r3, #1 8000a5e: 2203 movs r2, #3 8000a60: fa02 f303 lsl.w r3, r2, r3 8000a64: 43db mvns r3, r3 8000a66: 693a ldr r2, [r7, #16] 8000a68: 4013 ands r3, r2 8000a6a: 613b str r3, [r7, #16] SET_BIT(temp, GPIO_Init->Speed << (position * 2)); 8000a6c: 683b ldr r3, [r7, #0] 8000a6e: 68da ldr r2, [r3, #12] 8000a70: 697b ldr r3, [r7, #20] 8000a72: 005b lsls r3, r3, #1 8000a74: fa02 f303 lsl.w r3, r2, r3 8000a78: 693a ldr r2, [r7, #16] 8000a7a: 4313 orrs r3, r2 8000a7c: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8000a7e: 687b ldr r3, [r7, #4] 8000a80: 693a ldr r2, [r7, #16] 8000a82: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8000a84: 687b ldr r3, [r7, #4] 8000a86: 685b ldr r3, [r3, #4] 8000a88: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; 8000a8a: 2201 movs r2, #1 8000a8c: 697b ldr r3, [r7, #20] 8000a8e: fa02 f303 lsl.w r3, r2, r3 8000a92: 43db mvns r3, r3 8000a94: 693a ldr r2, [r7, #16] 8000a96: 4013 ands r3, r2 8000a98: 613b str r3, [r7, #16] SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8000a9a: 683b ldr r3, [r7, #0] 8000a9c: 685b ldr r3, [r3, #4] 8000a9e: 091b lsrs r3, r3, #4 8000aa0: f003 0201 and.w r2, r3, #1 8000aa4: 697b ldr r3, [r7, #20] 8000aa6: fa02 f303 lsl.w r3, r2, r3 8000aaa: 693a ldr r2, [r7, #16] 8000aac: 4313 orrs r3, r2 8000aae: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8000ab0: 687b ldr r3, [r7, #4] 8000ab2: 693a ldr r2, [r7, #16] 8000ab4: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8000ab6: 683b ldr r3, [r7, #0] 8000ab8: 685b ldr r3, [r3, #4] 8000aba: f003 0303 and.w r3, r3, #3 8000abe: 2b03 cmp r3, #3 8000ac0: d017 beq.n 8000af2 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8000ac2: 687b ldr r3, [r7, #4] 8000ac4: 68db ldr r3, [r3, #12] 8000ac6: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); 8000ac8: 697b ldr r3, [r7, #20] 8000aca: 005b lsls r3, r3, #1 8000acc: 2203 movs r2, #3 8000ace: fa02 f303 lsl.w r3, r2, r3 8000ad2: 43db mvns r3, r3 8000ad4: 693a ldr r2, [r7, #16] 8000ad6: 4013 ands r3, r2 8000ad8: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); 8000ada: 683b ldr r3, [r7, #0] 8000adc: 689a ldr r2, [r3, #8] 8000ade: 697b ldr r3, [r7, #20] 8000ae0: 005b lsls r3, r3, #1 8000ae2: fa02 f303 lsl.w r3, r2, r3 8000ae6: 693a ldr r2, [r7, #16] 8000ae8: 4313 orrs r3, r2 8000aea: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8000aec: 687b ldr r3, [r7, #4] 8000aee: 693a ldr r2, [r7, #16] 8000af0: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8000af2: 683b ldr r3, [r7, #0] 8000af4: 685b ldr r3, [r3, #4] 8000af6: f003 0303 and.w r3, r3, #3 8000afa: 2b02 cmp r3, #2 8000afc: d123 bne.n 8000b46 assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ /* Identify AFRL or AFRH register based on IO position*/ temp = GPIOx->AFR[position >> 3]; 8000afe: 697b ldr r3, [r7, #20] 8000b00: 08da lsrs r2, r3, #3 8000b02: 687b ldr r3, [r7, #4] 8000b04: 3208 adds r2, #8 8000b06: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8000b0a: 613b str r3, [r7, #16] CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); 8000b0c: 697b ldr r3, [r7, #20] 8000b0e: f003 0307 and.w r3, r3, #7 8000b12: 009b lsls r3, r3, #2 8000b14: 220f movs r2, #15 8000b16: fa02 f303 lsl.w r3, r2, r3 8000b1a: 43db mvns r3, r3 8000b1c: 693a ldr r2, [r7, #16] 8000b1e: 4013 ands r3, r2 8000b20: 613b str r3, [r7, #16] SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); 8000b22: 683b ldr r3, [r7, #0] 8000b24: 691a ldr r2, [r3, #16] 8000b26: 697b ldr r3, [r7, #20] 8000b28: f003 0307 and.w r3, r3, #7 8000b2c: 009b lsls r3, r3, #2 8000b2e: fa02 f303 lsl.w r3, r2, r3 8000b32: 693a ldr r2, [r7, #16] 8000b34: 4313 orrs r3, r2 8000b36: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3] = temp; 8000b38: 697b ldr r3, [r7, #20] 8000b3a: 08da lsrs r2, r3, #3 8000b3c: 687b ldr r3, [r7, #4] 8000b3e: 3208 adds r2, #8 8000b40: 6939 ldr r1, [r7, #16] 8000b42: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8000b46: 687b ldr r3, [r7, #4] 8000b48: 681b ldr r3, [r3, #0] 8000b4a: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); 8000b4c: 697b ldr r3, [r7, #20] 8000b4e: 005b lsls r3, r3, #1 8000b50: 2203 movs r2, #3 8000b52: fa02 f303 lsl.w r3, r2, r3 8000b56: 43db mvns r3, r3 8000b58: 693a ldr r2, [r7, #16] 8000b5a: 4013 ands r3, r2 8000b5c: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); 8000b5e: 683b ldr r3, [r7, #0] 8000b60: 685b ldr r3, [r3, #4] 8000b62: f003 0203 and.w r2, r3, #3 8000b66: 697b ldr r3, [r7, #20] 8000b68: 005b lsls r3, r3, #1 8000b6a: fa02 f303 lsl.w r3, r2, r3 8000b6e: 693a ldr r2, [r7, #16] 8000b70: 4313 orrs r3, r2 8000b72: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8000b74: 687b ldr r3, [r7, #4] 8000b76: 693a ldr r2, [r7, #16] 8000b78: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8000b7a: 683b ldr r3, [r7, #0] 8000b7c: 685b ldr r3, [r3, #4] 8000b7e: f403 3340 and.w r3, r3, #196608 @ 0x30000 8000b82: 2b00 cmp r3, #0 8000b84: f000 80ac beq.w 8000ce0 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000b88: 4b5e ldr r3, [pc, #376] @ (8000d04 ) 8000b8a: 6a1b ldr r3, [r3, #32] 8000b8c: 4a5d ldr r2, [pc, #372] @ (8000d04 ) 8000b8e: f043 0301 orr.w r3, r3, #1 8000b92: 6213 str r3, [r2, #32] 8000b94: 4b5b ldr r3, [pc, #364] @ (8000d04 ) 8000b96: 6a1b ldr r3, [r3, #32] 8000b98: f003 0301 and.w r3, r3, #1 8000b9c: 60bb str r3, [r7, #8] 8000b9e: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2]; 8000ba0: 4a59 ldr r2, [pc, #356] @ (8000d08 ) 8000ba2: 697b ldr r3, [r7, #20] 8000ba4: 089b lsrs r3, r3, #2 8000ba6: 3302 adds r3, #2 8000ba8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000bac: 613b str r3, [r7, #16] CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); 8000bae: 697b ldr r3, [r7, #20] 8000bb0: f003 0303 and.w r3, r3, #3 8000bb4: 009b lsls r3, r3, #2 8000bb6: 220f movs r2, #15 8000bb8: fa02 f303 lsl.w r3, r2, r3 8000bbc: 43db mvns r3, r3 8000bbe: 693a ldr r2, [r7, #16] 8000bc0: 4013 ands r3, r2 8000bc2: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); 8000bc4: 687b ldr r3, [r7, #4] 8000bc6: 4a51 ldr r2, [pc, #324] @ (8000d0c ) 8000bc8: 4293 cmp r3, r2 8000bca: d025 beq.n 8000c18 8000bcc: 687b ldr r3, [r7, #4] 8000bce: 4a50 ldr r2, [pc, #320] @ (8000d10 ) 8000bd0: 4293 cmp r3, r2 8000bd2: d01f beq.n 8000c14 8000bd4: 687b ldr r3, [r7, #4] 8000bd6: 4a4f ldr r2, [pc, #316] @ (8000d14 ) 8000bd8: 4293 cmp r3, r2 8000bda: d019 beq.n 8000c10 8000bdc: 687b ldr r3, [r7, #4] 8000bde: 4a4e ldr r2, [pc, #312] @ (8000d18 ) 8000be0: 4293 cmp r3, r2 8000be2: d013 beq.n 8000c0c 8000be4: 687b ldr r3, [r7, #4] 8000be6: 4a4d ldr r2, [pc, #308] @ (8000d1c ) 8000be8: 4293 cmp r3, r2 8000bea: d00d beq.n 8000c08 8000bec: 687b ldr r3, [r7, #4] 8000bee: 4a4c ldr r2, [pc, #304] @ (8000d20 ) 8000bf0: 4293 cmp r3, r2 8000bf2: d007 beq.n 8000c04 8000bf4: 687b ldr r3, [r7, #4] 8000bf6: 4a4b ldr r2, [pc, #300] @ (8000d24 ) 8000bf8: 4293 cmp r3, r2 8000bfa: d101 bne.n 8000c00 8000bfc: 2306 movs r3, #6 8000bfe: e00c b.n 8000c1a 8000c00: 2307 movs r3, #7 8000c02: e00a b.n 8000c1a 8000c04: 2305 movs r3, #5 8000c06: e008 b.n 8000c1a 8000c08: 2304 movs r3, #4 8000c0a: e006 b.n 8000c1a 8000c0c: 2303 movs r3, #3 8000c0e: e004 b.n 8000c1a 8000c10: 2302 movs r3, #2 8000c12: e002 b.n 8000c1a 8000c14: 2301 movs r3, #1 8000c16: e000 b.n 8000c1a 8000c18: 2300 movs r3, #0 8000c1a: 697a ldr r2, [r7, #20] 8000c1c: f002 0203 and.w r2, r2, #3 8000c20: 0092 lsls r2, r2, #2 8000c22: 4093 lsls r3, r2 8000c24: 693a ldr r2, [r7, #16] 8000c26: 4313 orrs r3, r2 8000c28: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2] = temp; 8000c2a: 4937 ldr r1, [pc, #220] @ (8000d08 ) 8000c2c: 697b ldr r3, [r7, #20] 8000c2e: 089b lsrs r3, r3, #2 8000c30: 3302 adds r3, #2 8000c32: 693a ldr r2, [r7, #16] 8000c34: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8000c38: 4b3b ldr r3, [pc, #236] @ (8000d28 ) 8000c3a: 689b ldr r3, [r3, #8] 8000c3c: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000c3e: 68fb ldr r3, [r7, #12] 8000c40: 43db mvns r3, r3 8000c42: 693a ldr r2, [r7, #16] 8000c44: 4013 ands r3, r2 8000c46: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8000c48: 683b ldr r3, [r7, #0] 8000c4a: 685b ldr r3, [r3, #4] 8000c4c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8000c50: 2b00 cmp r3, #0 8000c52: d003 beq.n 8000c5c { SET_BIT(temp, iocurrent); 8000c54: 693a ldr r2, [r7, #16] 8000c56: 68fb ldr r3, [r7, #12] 8000c58: 4313 orrs r3, r2 8000c5a: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 8000c5c: 4a32 ldr r2, [pc, #200] @ (8000d28 ) 8000c5e: 693b ldr r3, [r7, #16] 8000c60: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8000c62: 4b31 ldr r3, [pc, #196] @ (8000d28 ) 8000c64: 68db ldr r3, [r3, #12] 8000c66: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000c68: 68fb ldr r3, [r7, #12] 8000c6a: 43db mvns r3, r3 8000c6c: 693a ldr r2, [r7, #16] 8000c6e: 4013 ands r3, r2 8000c70: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8000c72: 683b ldr r3, [r7, #0] 8000c74: 685b ldr r3, [r3, #4] 8000c76: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8000c7a: 2b00 cmp r3, #0 8000c7c: d003 beq.n 8000c86 { SET_BIT(temp, iocurrent); 8000c7e: 693a ldr r2, [r7, #16] 8000c80: 68fb ldr r3, [r7, #12] 8000c82: 4313 orrs r3, r2 8000c84: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8000c86: 4a28 ldr r2, [pc, #160] @ (8000d28 ) 8000c88: 693b ldr r3, [r7, #16] 8000c8a: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8000c8c: 4b26 ldr r3, [pc, #152] @ (8000d28 ) 8000c8e: 685b ldr r3, [r3, #4] 8000c90: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000c92: 68fb ldr r3, [r7, #12] 8000c94: 43db mvns r3, r3 8000c96: 693a ldr r2, [r7, #16] 8000c98: 4013 ands r3, r2 8000c9a: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8000c9c: 683b ldr r3, [r7, #0] 8000c9e: 685b ldr r3, [r3, #4] 8000ca0: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000ca4: 2b00 cmp r3, #0 8000ca6: d003 beq.n 8000cb0 { SET_BIT(temp, iocurrent); 8000ca8: 693a ldr r2, [r7, #16] 8000caa: 68fb ldr r3, [r7, #12] 8000cac: 4313 orrs r3, r2 8000cae: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8000cb0: 4a1d ldr r2, [pc, #116] @ (8000d28 ) 8000cb2: 693b ldr r3, [r7, #16] 8000cb4: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8000cb6: 4b1c ldr r3, [pc, #112] @ (8000d28 ) 8000cb8: 681b ldr r3, [r3, #0] 8000cba: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000cbc: 68fb ldr r3, [r7, #12] 8000cbe: 43db mvns r3, r3 8000cc0: 693a ldr r2, [r7, #16] 8000cc2: 4013 ands r3, r2 8000cc4: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8000cc6: 683b ldr r3, [r7, #0] 8000cc8: 685b ldr r3, [r3, #4] 8000cca: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000cce: 2b00 cmp r3, #0 8000cd0: d003 beq.n 8000cda { SET_BIT(temp, iocurrent); 8000cd2: 693a ldr r2, [r7, #16] 8000cd4: 68fb ldr r3, [r7, #12] 8000cd6: 4313 orrs r3, r2 8000cd8: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8000cda: 4a13 ldr r2, [pc, #76] @ (8000d28 ) 8000cdc: 693b ldr r3, [r7, #16] 8000cde: 6013 str r3, [r2, #0] } } position++; 8000ce0: 697b ldr r3, [r7, #20] 8000ce2: 3301 adds r3, #1 8000ce4: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0) 8000ce6: 683b ldr r3, [r7, #0] 8000ce8: 681a ldr r2, [r3, #0] 8000cea: 697b ldr r3, [r7, #20] 8000cec: fa22 f303 lsr.w r3, r2, r3 8000cf0: 2b00 cmp r3, #0 8000cf2: f47f ae97 bne.w 8000a24 } } 8000cf6: bf00 nop 8000cf8: bf00 nop 8000cfa: 371c adds r7, #28 8000cfc: 46bd mov sp, r7 8000cfe: bc80 pop {r7} 8000d00: 4770 bx lr 8000d02: bf00 nop 8000d04: 40023800 .word 0x40023800 8000d08: 40010000 .word 0x40010000 8000d0c: 40020000 .word 0x40020000 8000d10: 40020400 .word 0x40020400 8000d14: 40020800 .word 0x40020800 8000d18: 40020c00 .word 0x40020c00 8000d1c: 40021000 .word 0x40021000 8000d20: 40021400 .word 0x40021400 8000d24: 40021800 .word 0x40021800 8000d28: 40010400 .word 0x40010400 08000d2c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8000d2c: b480 push {r7} 8000d2e: b083 sub sp, #12 8000d30: af00 add r7, sp, #0 8000d32: 6078 str r0, [r7, #4] 8000d34: 460b mov r3, r1 8000d36: 807b strh r3, [r7, #2] 8000d38: 4613 mov r3, r2 8000d3a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8000d3c: 787b ldrb r3, [r7, #1] 8000d3e: 2b00 cmp r3, #0 8000d40: d003 beq.n 8000d4a { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8000d42: 887a ldrh r2, [r7, #2] 8000d44: 687b ldr r3, [r7, #4] 8000d46: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; } } 8000d48: e003 b.n 8000d52 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; 8000d4a: 887b ldrh r3, [r7, #2] 8000d4c: 041a lsls r2, r3, #16 8000d4e: 687b ldr r3, [r7, #4] 8000d50: 619a str r2, [r3, #24] } 8000d52: bf00 nop 8000d54: 370c adds r7, #12 8000d56: 46bd mov sp, r7 8000d58: bc80 pop {r7} 8000d5a: 4770 bx lr 08000d5c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000d5c: b580 push {r7, lr} 8000d5e: b088 sub sp, #32 8000d60: af00 add r7, sp, #0 8000d62: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status; uint32_t sysclk_source, pll_config; /* Check the parameters */ if(RCC_OscInitStruct == NULL) 8000d64: 687b ldr r3, [r7, #4] 8000d66: 2b00 cmp r3, #0 8000d68: d101 bne.n 8000d6e { return HAL_ERROR; 8000d6a: 2301 movs r3, #1 8000d6c: e31d b.n 80013aa } assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); 8000d6e: 4b94 ldr r3, [pc, #592] @ (8000fc0 ) 8000d70: 689b ldr r3, [r3, #8] 8000d72: f003 030c and.w r3, r3, #12 8000d76: 61bb str r3, [r7, #24] pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); 8000d78: 4b91 ldr r3, [pc, #580] @ (8000fc0 ) 8000d7a: 689b ldr r3, [r3, #8] 8000d7c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000d80: 617b str r3, [r7, #20] /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000d82: 687b ldr r3, [r7, #4] 8000d84: 681b ldr r3, [r3, #0] 8000d86: f003 0301 and.w r3, r3, #1 8000d8a: 2b00 cmp r3, #0 8000d8c: d07b beq.n 8000e86 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) 8000d8e: 69bb ldr r3, [r7, #24] 8000d90: 2b08 cmp r3, #8 8000d92: d006 beq.n 8000da2 || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) 8000d94: 69bb ldr r3, [r7, #24] 8000d96: 2b0c cmp r3, #12 8000d98: d10f bne.n 8000dba 8000d9a: 697b ldr r3, [r7, #20] 8000d9c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8000da0: d10b bne.n 8000dba { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000da2: 4b87 ldr r3, [pc, #540] @ (8000fc0 ) 8000da4: 681b ldr r3, [r3, #0] 8000da6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000daa: 2b00 cmp r3, #0 8000dac: d06a beq.n 8000e84 8000dae: 687b ldr r3, [r7, #4] 8000db0: 685b ldr r3, [r3, #4] 8000db2: 2b00 cmp r3, #0 8000db4: d166 bne.n 8000e84 { return HAL_ERROR; 8000db6: 2301 movs r3, #1 8000db8: e2f7 b.n 80013aa } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000dba: 687b ldr r3, [r7, #4] 8000dbc: 685b ldr r3, [r3, #4] 8000dbe: 2b01 cmp r3, #1 8000dc0: d106 bne.n 8000dd0 8000dc2: 4b7f ldr r3, [pc, #508] @ (8000fc0 ) 8000dc4: 681b ldr r3, [r3, #0] 8000dc6: 4a7e ldr r2, [pc, #504] @ (8000fc0 ) 8000dc8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000dcc: 6013 str r3, [r2, #0] 8000dce: e02d b.n 8000e2c 8000dd0: 687b ldr r3, [r7, #4] 8000dd2: 685b ldr r3, [r3, #4] 8000dd4: 2b00 cmp r3, #0 8000dd6: d10c bne.n 8000df2 8000dd8: 4b79 ldr r3, [pc, #484] @ (8000fc0 ) 8000dda: 681b ldr r3, [r3, #0] 8000ddc: 4a78 ldr r2, [pc, #480] @ (8000fc0 ) 8000dde: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8000de2: 6013 str r3, [r2, #0] 8000de4: 4b76 ldr r3, [pc, #472] @ (8000fc0 ) 8000de6: 681b ldr r3, [r3, #0] 8000de8: 4a75 ldr r2, [pc, #468] @ (8000fc0 ) 8000dea: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8000dee: 6013 str r3, [r2, #0] 8000df0: e01c b.n 8000e2c 8000df2: 687b ldr r3, [r7, #4] 8000df4: 685b ldr r3, [r3, #4] 8000df6: 2b05 cmp r3, #5 8000df8: d10c bne.n 8000e14 8000dfa: 4b71 ldr r3, [pc, #452] @ (8000fc0 ) 8000dfc: 681b ldr r3, [r3, #0] 8000dfe: 4a70 ldr r2, [pc, #448] @ (8000fc0 ) 8000e00: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8000e04: 6013 str r3, [r2, #0] 8000e06: 4b6e ldr r3, [pc, #440] @ (8000fc0 ) 8000e08: 681b ldr r3, [r3, #0] 8000e0a: 4a6d ldr r2, [pc, #436] @ (8000fc0 ) 8000e0c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000e10: 6013 str r3, [r2, #0] 8000e12: e00b b.n 8000e2c 8000e14: 4b6a ldr r3, [pc, #424] @ (8000fc0 ) 8000e16: 681b ldr r3, [r3, #0] 8000e18: 4a69 ldr r2, [pc, #420] @ (8000fc0 ) 8000e1a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8000e1e: 6013 str r3, [r2, #0] 8000e20: 4b67 ldr r3, [pc, #412] @ (8000fc0 ) 8000e22: 681b ldr r3, [r3, #0] 8000e24: 4a66 ldr r2, [pc, #408] @ (8000fc0 ) 8000e26: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8000e2a: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000e2c: 687b ldr r3, [r7, #4] 8000e2e: 685b ldr r3, [r3, #4] 8000e30: 2b00 cmp r3, #0 8000e32: d013 beq.n 8000e5c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e34: f7ff fcfc bl 8000830 8000e38: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8000e3a: e008 b.n 8000e4e { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000e3c: f7ff fcf8 bl 8000830 8000e40: 4602 mov r2, r0 8000e42: 693b ldr r3, [r7, #16] 8000e44: 1ad3 subs r3, r2, r3 8000e46: 2b64 cmp r3, #100 @ 0x64 8000e48: d901 bls.n 8000e4e { return HAL_TIMEOUT; 8000e4a: 2303 movs r3, #3 8000e4c: e2ad b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8000e4e: 4b5c ldr r3, [pc, #368] @ (8000fc0 ) 8000e50: 681b ldr r3, [r3, #0] 8000e52: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000e56: 2b00 cmp r3, #0 8000e58: d0f0 beq.n 8000e3c 8000e5a: e014 b.n 8000e86 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e5c: f7ff fce8 bl 8000830 8000e60: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8000e62: e008 b.n 8000e76 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000e64: f7ff fce4 bl 8000830 8000e68: 4602 mov r2, r0 8000e6a: 693b ldr r3, [r7, #16] 8000e6c: 1ad3 subs r3, r2, r3 8000e6e: 2b64 cmp r3, #100 @ 0x64 8000e70: d901 bls.n 8000e76 { return HAL_TIMEOUT; 8000e72: 2303 movs r3, #3 8000e74: e299 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8000e76: 4b52 ldr r3, [pc, #328] @ (8000fc0 ) 8000e78: 681b ldr r3, [r3, #0] 8000e7a: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000e7e: 2b00 cmp r3, #0 8000e80: d1f0 bne.n 8000e64 8000e82: e000 b.n 8000e86 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000e84: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000e86: 687b ldr r3, [r7, #4] 8000e88: 681b ldr r3, [r3, #0] 8000e8a: f003 0302 and.w r3, r3, #2 8000e8e: 2b00 cmp r3, #0 8000e90: d05a beq.n 8000f48 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) 8000e92: 69bb ldr r3, [r7, #24] 8000e94: 2b04 cmp r3, #4 8000e96: d005 beq.n 8000ea4 || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) 8000e98: 69bb ldr r3, [r7, #24] 8000e9a: 2b0c cmp r3, #12 8000e9c: d119 bne.n 8000ed2 8000e9e: 697b ldr r3, [r7, #20] 8000ea0: 2b00 cmp r3, #0 8000ea2: d116 bne.n 8000ed2 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000ea4: 4b46 ldr r3, [pc, #280] @ (8000fc0 ) 8000ea6: 681b ldr r3, [r3, #0] 8000ea8: f003 0302 and.w r3, r3, #2 8000eac: 2b00 cmp r3, #0 8000eae: d005 beq.n 8000ebc 8000eb0: 687b ldr r3, [r7, #4] 8000eb2: 68db ldr r3, [r3, #12] 8000eb4: 2b01 cmp r3, #1 8000eb6: d001 beq.n 8000ebc { return HAL_ERROR; 8000eb8: 2301 movs r3, #1 8000eba: e276 b.n 80013aa } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000ebc: 4b40 ldr r3, [pc, #256] @ (8000fc0 ) 8000ebe: 685b ldr r3, [r3, #4] 8000ec0: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 8000ec4: 687b ldr r3, [r7, #4] 8000ec6: 691b ldr r3, [r3, #16] 8000ec8: 021b lsls r3, r3, #8 8000eca: 493d ldr r1, [pc, #244] @ (8000fc0 ) 8000ecc: 4313 orrs r3, r2 8000ece: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000ed0: e03a b.n 8000f48 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000ed2: 687b ldr r3, [r7, #4] 8000ed4: 68db ldr r3, [r3, #12] 8000ed6: 2b00 cmp r3, #0 8000ed8: d020 beq.n 8000f1c { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000eda: 4b3a ldr r3, [pc, #232] @ (8000fc4 ) 8000edc: 2201 movs r2, #1 8000ede: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000ee0: f7ff fca6 bl 8000830 8000ee4: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8000ee6: e008 b.n 8000efa { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000ee8: f7ff fca2 bl 8000830 8000eec: 4602 mov r2, r0 8000eee: 693b ldr r3, [r7, #16] 8000ef0: 1ad3 subs r3, r2, r3 8000ef2: 2b02 cmp r3, #2 8000ef4: d901 bls.n 8000efa { return HAL_TIMEOUT; 8000ef6: 2303 movs r3, #3 8000ef8: e257 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8000efa: 4b31 ldr r3, [pc, #196] @ (8000fc0 ) 8000efc: 681b ldr r3, [r3, #0] 8000efe: f003 0302 and.w r3, r3, #2 8000f02: 2b00 cmp r3, #0 8000f04: d0f0 beq.n 8000ee8 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000f06: 4b2e ldr r3, [pc, #184] @ (8000fc0 ) 8000f08: 685b ldr r3, [r3, #4] 8000f0a: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 8000f0e: 687b ldr r3, [r7, #4] 8000f10: 691b ldr r3, [r3, #16] 8000f12: 021b lsls r3, r3, #8 8000f14: 492a ldr r1, [pc, #168] @ (8000fc0 ) 8000f16: 4313 orrs r3, r2 8000f18: 604b str r3, [r1, #4] 8000f1a: e015 b.n 8000f48 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000f1c: 4b29 ldr r3, [pc, #164] @ (8000fc4 ) 8000f1e: 2200 movs r2, #0 8000f20: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000f22: f7ff fc85 bl 8000830 8000f26: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8000f28: e008 b.n 8000f3c { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000f2a: f7ff fc81 bl 8000830 8000f2e: 4602 mov r2, r0 8000f30: 693b ldr r3, [r7, #16] 8000f32: 1ad3 subs r3, r2, r3 8000f34: 2b02 cmp r3, #2 8000f36: d901 bls.n 8000f3c { return HAL_TIMEOUT; 8000f38: 2303 movs r3, #3 8000f3a: e236 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8000f3c: 4b20 ldr r3, [pc, #128] @ (8000fc0 ) 8000f3e: 681b ldr r3, [r3, #0] 8000f40: f003 0302 and.w r3, r3, #2 8000f44: 2b00 cmp r3, #0 8000f46: d1f0 bne.n 8000f2a } } } } /*----------------------------- MSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) 8000f48: 687b ldr r3, [r7, #4] 8000f4a: 681b ldr r3, [r3, #0] 8000f4c: f003 0310 and.w r3, r3, #16 8000f50: 2b00 cmp r3, #0 8000f52: f000 80b8 beq.w 80010c6 { /* When the MSI is used as system clock it will not be disabled */ if(sysclk_source == RCC_CFGR_SWS_MSI) 8000f56: 69bb ldr r3, [r7, #24] 8000f58: 2b00 cmp r3, #0 8000f5a: d170 bne.n 800103e { if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) 8000f5c: 4b18 ldr r3, [pc, #96] @ (8000fc0 ) 8000f5e: 681b ldr r3, [r3, #0] 8000f60: f403 7300 and.w r3, r3, #512 @ 0x200 8000f64: 2b00 cmp r3, #0 8000f66: d005 beq.n 8000f74 8000f68: 687b ldr r3, [r7, #4] 8000f6a: 699b ldr r3, [r3, #24] 8000f6c: 2b00 cmp r3, #0 8000f6e: d101 bne.n 8000f74 { return HAL_ERROR; 8000f70: 2301 movs r3, #1 8000f72: e21a b.n 80013aa assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) 8000f74: 687b ldr r3, [r7, #4] 8000f76: 6a1a ldr r2, [r3, #32] 8000f78: 4b11 ldr r3, [pc, #68] @ (8000fc0 ) 8000f7a: 685b ldr r3, [r3, #4] 8000f7c: f403 4360 and.w r3, r3, #57344 @ 0xe000 8000f80: 429a cmp r2, r3 8000f82: d921 bls.n 8000fc8 { /* First increase number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 8000f84: 687b ldr r3, [r7, #4] 8000f86: 6a1b ldr r3, [r3, #32] 8000f88: 4618 mov r0, r3 8000f8a: f000 fc09 bl 80017a0 8000f8e: 4603 mov r3, r0 8000f90: 2b00 cmp r3, #0 8000f92: d001 beq.n 8000f98 { return HAL_ERROR; 8000f94: 2301 movs r3, #1 8000f96: e208 b.n 80013aa } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8000f98: 4b09 ldr r3, [pc, #36] @ (8000fc0 ) 8000f9a: 685b ldr r3, [r3, #4] 8000f9c: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8000fa0: 687b ldr r3, [r7, #4] 8000fa2: 6a1b ldr r3, [r3, #32] 8000fa4: 4906 ldr r1, [pc, #24] @ (8000fc0 ) 8000fa6: 4313 orrs r3, r2 8000fa8: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8000faa: 4b05 ldr r3, [pc, #20] @ (8000fc0 ) 8000fac: 685b ldr r3, [r3, #4] 8000fae: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 8000fb2: 687b ldr r3, [r7, #4] 8000fb4: 69db ldr r3, [r3, #28] 8000fb6: 061b lsls r3, r3, #24 8000fb8: 4901 ldr r1, [pc, #4] @ (8000fc0 ) 8000fba: 4313 orrs r3, r2 8000fbc: 604b str r3, [r1, #4] 8000fbe: e020 b.n 8001002 8000fc0: 40023800 .word 0x40023800 8000fc4: 42470000 .word 0x42470000 } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8000fc8: 4b99 ldr r3, [pc, #612] @ (8001230 ) 8000fca: 685b ldr r3, [r3, #4] 8000fcc: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8000fd0: 687b ldr r3, [r7, #4] 8000fd2: 6a1b ldr r3, [r3, #32] 8000fd4: 4996 ldr r1, [pc, #600] @ (8001230 ) 8000fd6: 4313 orrs r3, r2 8000fd8: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8000fda: 4b95 ldr r3, [pc, #596] @ (8001230 ) 8000fdc: 685b ldr r3, [r3, #4] 8000fde: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 8000fe2: 687b ldr r3, [r7, #4] 8000fe4: 69db ldr r3, [r3, #28] 8000fe6: 061b lsls r3, r3, #24 8000fe8: 4991 ldr r1, [pc, #580] @ (8001230 ) 8000fea: 4313 orrs r3, r2 8000fec: 604b str r3, [r1, #4] /* Decrease number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 8000fee: 687b ldr r3, [r7, #4] 8000ff0: 6a1b ldr r3, [r3, #32] 8000ff2: 4618 mov r0, r3 8000ff4: f000 fbd4 bl 80017a0 8000ff8: 4603 mov r3, r0 8000ffa: 2b00 cmp r3, #0 8000ffc: d001 beq.n 8001002 { return HAL_ERROR; 8000ffe: 2301 movs r3, #1 8001000: e1d3 b.n 80013aa } } /* Update the SystemCoreClock global variable */ SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) 8001002: 687b ldr r3, [r7, #4] 8001004: 6a1b ldr r3, [r3, #32] 8001006: 0b5b lsrs r3, r3, #13 8001008: 3301 adds r3, #1 800100a: f44f 4200 mov.w r2, #32768 @ 0x8000 800100e: fa02 f303 lsl.w r3, r2, r3 >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; 8001012: 4a87 ldr r2, [pc, #540] @ (8001230 ) 8001014: 6892 ldr r2, [r2, #8] 8001016: 0912 lsrs r2, r2, #4 8001018: f002 020f and.w r2, r2, #15 800101c: 4985 ldr r1, [pc, #532] @ (8001234 ) 800101e: 5c8a ldrb r2, [r1, r2] 8001020: 40d3 lsrs r3, r2 SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) 8001022: 4a85 ldr r2, [pc, #532] @ (8001238 ) 8001024: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); 8001026: 4b85 ldr r3, [pc, #532] @ (800123c ) 8001028: 681b ldr r3, [r3, #0] 800102a: 4618 mov r0, r3 800102c: f7ff fbb4 bl 8000798 8001030: 4603 mov r3, r0 8001032: 73fb strb r3, [r7, #15] if(status != HAL_OK) 8001034: 7bfb ldrb r3, [r7, #15] 8001036: 2b00 cmp r3, #0 8001038: d045 beq.n 80010c6 { return status; 800103a: 7bfb ldrb r3, [r7, #15] 800103c: e1b5 b.n 80013aa { /* Check MSI State */ assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); /* Check the MSI State */ if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) 800103e: 687b ldr r3, [r7, #4] 8001040: 699b ldr r3, [r3, #24] 8001042: 2b00 cmp r3, #0 8001044: d029 beq.n 800109a { /* Enable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); 8001046: 4b7e ldr r3, [pc, #504] @ (8001240 ) 8001048: 2201 movs r2, #1 800104a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800104c: f7ff fbf0 bl 8000830 8001050: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) 8001052: e008 b.n 8001066 { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 8001054: f7ff fbec bl 8000830 8001058: 4602 mov r2, r0 800105a: 693b ldr r3, [r7, #16] 800105c: 1ad3 subs r3, r2, r3 800105e: 2b02 cmp r3, #2 8001060: d901 bls.n 8001066 { return HAL_TIMEOUT; 8001062: 2303 movs r3, #3 8001064: e1a1 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) 8001066: 4b72 ldr r3, [pc, #456] @ (8001230 ) 8001068: 681b ldr r3, [r3, #0] 800106a: f403 7300 and.w r3, r3, #512 @ 0x200 800106e: 2b00 cmp r3, #0 8001070: d0f0 beq.n 8001054 /* Check MSICalibrationValue and MSIClockRange input parameters */ assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8001072: 4b6f ldr r3, [pc, #444] @ (8001230 ) 8001074: 685b ldr r3, [r3, #4] 8001076: f423 4260 bic.w r2, r3, #57344 @ 0xe000 800107a: 687b ldr r3, [r7, #4] 800107c: 6a1b ldr r3, [r3, #32] 800107e: 496c ldr r1, [pc, #432] @ (8001230 ) 8001080: 4313 orrs r3, r2 8001082: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8001084: 4b6a ldr r3, [pc, #424] @ (8001230 ) 8001086: 685b ldr r3, [r3, #4] 8001088: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000 800108c: 687b ldr r3, [r7, #4] 800108e: 69db ldr r3, [r3, #28] 8001090: 061b lsls r3, r3, #24 8001092: 4967 ldr r1, [pc, #412] @ (8001230 ) 8001094: 4313 orrs r3, r2 8001096: 604b str r3, [r1, #4] 8001098: e015 b.n 80010c6 } else { /* Disable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); 800109a: 4b69 ldr r3, [pc, #420] @ (8001240 ) 800109c: 2200 movs r2, #0 800109e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80010a0: f7ff fbc6 bl 8000830 80010a4: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) 80010a6: e008 b.n 80010ba { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 80010a8: f7ff fbc2 bl 8000830 80010ac: 4602 mov r2, r0 80010ae: 693b ldr r3, [r7, #16] 80010b0: 1ad3 subs r3, r2, r3 80010b2: 2b02 cmp r3, #2 80010b4: d901 bls.n 80010ba { return HAL_TIMEOUT; 80010b6: 2303 movs r3, #3 80010b8: e177 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) 80010ba: 4b5d ldr r3, [pc, #372] @ (8001230 ) 80010bc: 681b ldr r3, [r3, #0] 80010be: f403 7300 and.w r3, r3, #512 @ 0x200 80010c2: 2b00 cmp r3, #0 80010c4: d1f0 bne.n 80010a8 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80010c6: 687b ldr r3, [r7, #4] 80010c8: 681b ldr r3, [r3, #0] 80010ca: f003 0308 and.w r3, r3, #8 80010ce: 2b00 cmp r3, #0 80010d0: d030 beq.n 8001134 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80010d2: 687b ldr r3, [r7, #4] 80010d4: 695b ldr r3, [r3, #20] 80010d6: 2b00 cmp r3, #0 80010d8: d016 beq.n 8001108 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80010da: 4b5a ldr r3, [pc, #360] @ (8001244 ) 80010dc: 2201 movs r2, #1 80010de: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80010e0: f7ff fba6 bl 8000830 80010e4: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80010e6: e008 b.n 80010fa { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 80010e8: f7ff fba2 bl 8000830 80010ec: 4602 mov r2, r0 80010ee: 693b ldr r3, [r7, #16] 80010f0: 1ad3 subs r3, r2, r3 80010f2: 2b02 cmp r3, #2 80010f4: d901 bls.n 80010fa { return HAL_TIMEOUT; 80010f6: 2303 movs r3, #3 80010f8: e157 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80010fa: 4b4d ldr r3, [pc, #308] @ (8001230 ) 80010fc: 6b5b ldr r3, [r3, #52] @ 0x34 80010fe: f003 0302 and.w r3, r3, #2 8001102: 2b00 cmp r3, #0 8001104: d0f0 beq.n 80010e8 8001106: e015 b.n 8001134 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001108: 4b4e ldr r3, [pc, #312] @ (8001244 ) 800110a: 2200 movs r2, #0 800110c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800110e: f7ff fb8f bl 8000830 8001112: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8001114: e008 b.n 8001128 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001116: f7ff fb8b bl 8000830 800111a: 4602 mov r2, r0 800111c: 693b ldr r3, [r7, #16] 800111e: 1ad3 subs r3, r2, r3 8001120: 2b02 cmp r3, #2 8001122: d901 bls.n 8001128 { return HAL_TIMEOUT; 8001124: 2303 movs r3, #3 8001126: e140 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8001128: 4b41 ldr r3, [pc, #260] @ (8001230 ) 800112a: 6b5b ldr r3, [r3, #52] @ 0x34 800112c: f003 0302 and.w r3, r3, #2 8001130: 2b00 cmp r3, #0 8001132: d1f0 bne.n 8001116 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001134: 687b ldr r3, [r7, #4] 8001136: 681b ldr r3, [r3, #0] 8001138: f003 0304 and.w r3, r3, #4 800113c: 2b00 cmp r3, #0 800113e: f000 80b5 beq.w 80012ac { FlagStatus pwrclkchanged = RESET; 8001142: 2300 movs r3, #0 8001144: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8001146: 4b3a ldr r3, [pc, #232] @ (8001230 ) 8001148: 6a5b ldr r3, [r3, #36] @ 0x24 800114a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800114e: 2b00 cmp r3, #0 8001150: d10d bne.n 800116e { __HAL_RCC_PWR_CLK_ENABLE(); 8001152: 4b37 ldr r3, [pc, #220] @ (8001230 ) 8001154: 6a5b ldr r3, [r3, #36] @ 0x24 8001156: 4a36 ldr r2, [pc, #216] @ (8001230 ) 8001158: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800115c: 6253 str r3, [r2, #36] @ 0x24 800115e: 4b34 ldr r3, [pc, #208] @ (8001230 ) 8001160: 6a5b ldr r3, [r3, #36] @ 0x24 8001162: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8001166: 60bb str r3, [r7, #8] 8001168: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800116a: 2301 movs r3, #1 800116c: 77fb strb r3, [r7, #31] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800116e: 4b36 ldr r3, [pc, #216] @ (8001248 ) 8001170: 681b ldr r3, [r3, #0] 8001172: f403 7380 and.w r3, r3, #256 @ 0x100 8001176: 2b00 cmp r3, #0 8001178: d118 bne.n 80011ac { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800117a: 4b33 ldr r3, [pc, #204] @ (8001248 ) 800117c: 681b ldr r3, [r3, #0] 800117e: 4a32 ldr r2, [pc, #200] @ (8001248 ) 8001180: f443 7380 orr.w r3, r3, #256 @ 0x100 8001184: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001186: f7ff fb53 bl 8000830 800118a: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800118c: e008 b.n 80011a0 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800118e: f7ff fb4f bl 8000830 8001192: 4602 mov r2, r0 8001194: 693b ldr r3, [r7, #16] 8001196: 1ad3 subs r3, r2, r3 8001198: 2b64 cmp r3, #100 @ 0x64 800119a: d901 bls.n 80011a0 { return HAL_TIMEOUT; 800119c: 2303 movs r3, #3 800119e: e104 b.n 80013aa while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80011a0: 4b29 ldr r3, [pc, #164] @ (8001248 ) 80011a2: 681b ldr r3, [r3, #0] 80011a4: f403 7380 and.w r3, r3, #256 @ 0x100 80011a8: 2b00 cmp r3, #0 80011aa: d0f0 beq.n 800118e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80011ac: 687b ldr r3, [r7, #4] 80011ae: 689b ldr r3, [r3, #8] 80011b0: 2b01 cmp r3, #1 80011b2: d106 bne.n 80011c2 80011b4: 4b1e ldr r3, [pc, #120] @ (8001230 ) 80011b6: 6b5b ldr r3, [r3, #52] @ 0x34 80011b8: 4a1d ldr r2, [pc, #116] @ (8001230 ) 80011ba: f443 7380 orr.w r3, r3, #256 @ 0x100 80011be: 6353 str r3, [r2, #52] @ 0x34 80011c0: e02d b.n 800121e 80011c2: 687b ldr r3, [r7, #4] 80011c4: 689b ldr r3, [r3, #8] 80011c6: 2b00 cmp r3, #0 80011c8: d10c bne.n 80011e4 80011ca: 4b19 ldr r3, [pc, #100] @ (8001230 ) 80011cc: 6b5b ldr r3, [r3, #52] @ 0x34 80011ce: 4a18 ldr r2, [pc, #96] @ (8001230 ) 80011d0: f423 7380 bic.w r3, r3, #256 @ 0x100 80011d4: 6353 str r3, [r2, #52] @ 0x34 80011d6: 4b16 ldr r3, [pc, #88] @ (8001230 ) 80011d8: 6b5b ldr r3, [r3, #52] @ 0x34 80011da: 4a15 ldr r2, [pc, #84] @ (8001230 ) 80011dc: f423 6380 bic.w r3, r3, #1024 @ 0x400 80011e0: 6353 str r3, [r2, #52] @ 0x34 80011e2: e01c b.n 800121e 80011e4: 687b ldr r3, [r7, #4] 80011e6: 689b ldr r3, [r3, #8] 80011e8: 2b05 cmp r3, #5 80011ea: d10c bne.n 8001206 80011ec: 4b10 ldr r3, [pc, #64] @ (8001230 ) 80011ee: 6b5b ldr r3, [r3, #52] @ 0x34 80011f0: 4a0f ldr r2, [pc, #60] @ (8001230 ) 80011f2: f443 6380 orr.w r3, r3, #1024 @ 0x400 80011f6: 6353 str r3, [r2, #52] @ 0x34 80011f8: 4b0d ldr r3, [pc, #52] @ (8001230 ) 80011fa: 6b5b ldr r3, [r3, #52] @ 0x34 80011fc: 4a0c ldr r2, [pc, #48] @ (8001230 ) 80011fe: f443 7380 orr.w r3, r3, #256 @ 0x100 8001202: 6353 str r3, [r2, #52] @ 0x34 8001204: e00b b.n 800121e 8001206: 4b0a ldr r3, [pc, #40] @ (8001230 ) 8001208: 6b5b ldr r3, [r3, #52] @ 0x34 800120a: 4a09 ldr r2, [pc, #36] @ (8001230 ) 800120c: f423 7380 bic.w r3, r3, #256 @ 0x100 8001210: 6353 str r3, [r2, #52] @ 0x34 8001212: 4b07 ldr r3, [pc, #28] @ (8001230 ) 8001214: 6b5b ldr r3, [r3, #52] @ 0x34 8001216: 4a06 ldr r2, [pc, #24] @ (8001230 ) 8001218: f423 6380 bic.w r3, r3, #1024 @ 0x400 800121c: 6353 str r3, [r2, #52] @ 0x34 /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800121e: 687b ldr r3, [r7, #4] 8001220: 689b ldr r3, [r3, #8] 8001222: 2b00 cmp r3, #0 8001224: d024 beq.n 8001270 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001226: f7ff fb03 bl 8000830 800122a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800122c: e019 b.n 8001262 800122e: bf00 nop 8001230: 40023800 .word 0x40023800 8001234: 080018dc .word 0x080018dc 8001238: 20000000 .word 0x20000000 800123c: 20000004 .word 0x20000004 8001240: 42470020 .word 0x42470020 8001244: 42470680 .word 0x42470680 8001248: 40007000 .word 0x40007000 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 800124c: f7ff faf0 bl 8000830 8001250: 4602 mov r2, r0 8001252: 693b ldr r3, [r7, #16] 8001254: 1ad3 subs r3, r2, r3 8001256: f241 3288 movw r2, #5000 @ 0x1388 800125a: 4293 cmp r3, r2 800125c: d901 bls.n 8001262 { return HAL_TIMEOUT; 800125e: 2303 movs r3, #3 8001260: e0a3 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8001262: 4b54 ldr r3, [pc, #336] @ (80013b4 ) 8001264: 6b5b ldr r3, [r3, #52] @ 0x34 8001266: f403 7300 and.w r3, r3, #512 @ 0x200 800126a: 2b00 cmp r3, #0 800126c: d0ee beq.n 800124c 800126e: e014 b.n 800129a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001270: f7ff fade bl 8000830 8001274: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8001276: e00a b.n 800128e { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001278: f7ff fada bl 8000830 800127c: 4602 mov r2, r0 800127e: 693b ldr r3, [r7, #16] 8001280: 1ad3 subs r3, r2, r3 8001282: f241 3288 movw r2, #5000 @ 0x1388 8001286: 4293 cmp r3, r2 8001288: d901 bls.n 800128e { return HAL_TIMEOUT; 800128a: 2303 movs r3, #3 800128c: e08d b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800128e: 4b49 ldr r3, [pc, #292] @ (80013b4 ) 8001290: 6b5b ldr r3, [r3, #52] @ 0x34 8001292: f403 7300 and.w r3, r3, #512 @ 0x200 8001296: 2b00 cmp r3, #0 8001298: d1ee bne.n 8001278 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 800129a: 7ffb ldrb r3, [r7, #31] 800129c: 2b01 cmp r3, #1 800129e: d105 bne.n 80012ac { __HAL_RCC_PWR_CLK_DISABLE(); 80012a0: 4b44 ldr r3, [pc, #272] @ (80013b4 ) 80012a2: 6a5b ldr r3, [r3, #36] @ 0x24 80012a4: 4a43 ldr r2, [pc, #268] @ (80013b4 ) 80012a6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80012aa: 6253 str r3, [r2, #36] @ 0x24 } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80012ac: 687b ldr r3, [r7, #4] 80012ae: 6a5b ldr r3, [r3, #36] @ 0x24 80012b0: 2b00 cmp r3, #0 80012b2: d079 beq.n 80013a8 { /* Check if the PLL is used as system clock or not */ if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80012b4: 69bb ldr r3, [r7, #24] 80012b6: 2b0c cmp r3, #12 80012b8: d056 beq.n 8001368 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80012ba: 687b ldr r3, [r7, #4] 80012bc: 6a5b ldr r3, [r3, #36] @ 0x24 80012be: 2b02 cmp r3, #2 80012c0: d13b bne.n 800133a assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80012c2: 4b3d ldr r3, [pc, #244] @ (80013b8 ) 80012c4: 2200 movs r2, #0 80012c6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80012c8: f7ff fab2 bl 8000830 80012cc: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80012ce: e008 b.n 80012e2 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80012d0: f7ff faae bl 8000830 80012d4: 4602 mov r2, r0 80012d6: 693b ldr r3, [r7, #16] 80012d8: 1ad3 subs r3, r2, r3 80012da: 2b02 cmp r3, #2 80012dc: d901 bls.n 80012e2 { return HAL_TIMEOUT; 80012de: 2303 movs r3, #3 80012e0: e063 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80012e2: 4b34 ldr r3, [pc, #208] @ (80013b4 ) 80012e4: 681b ldr r3, [r3, #0] 80012e6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80012ea: 2b00 cmp r3, #0 80012ec: d1f0 bne.n 80012d0 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80012ee: 4b31 ldr r3, [pc, #196] @ (80013b4 ) 80012f0: 689b ldr r3, [r3, #8] 80012f2: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000 80012f6: 687b ldr r3, [r7, #4] 80012f8: 6a99 ldr r1, [r3, #40] @ 0x28 80012fa: 687b ldr r3, [r7, #4] 80012fc: 6adb ldr r3, [r3, #44] @ 0x2c 80012fe: 4319 orrs r1, r3 8001300: 687b ldr r3, [r7, #4] 8001302: 6b1b ldr r3, [r3, #48] @ 0x30 8001304: 430b orrs r3, r1 8001306: 492b ldr r1, [pc, #172] @ (80013b4 ) 8001308: 4313 orrs r3, r2 800130a: 608b str r3, [r1, #8] RCC_OscInitStruct->PLL.PLLMUL, RCC_OscInitStruct->PLL.PLLDIV); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800130c: 4b2a ldr r3, [pc, #168] @ (80013b8 ) 800130e: 2201 movs r2, #1 8001310: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001312: f7ff fa8d bl 8000830 8001316: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8001318: e008 b.n 800132c { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 800131a: f7ff fa89 bl 8000830 800131e: 4602 mov r2, r0 8001320: 693b ldr r3, [r7, #16] 8001322: 1ad3 subs r3, r2, r3 8001324: 2b02 cmp r3, #2 8001326: d901 bls.n 800132c { return HAL_TIMEOUT; 8001328: 2303 movs r3, #3 800132a: e03e b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800132c: 4b21 ldr r3, [pc, #132] @ (80013b4 ) 800132e: 681b ldr r3, [r3, #0] 8001330: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001334: 2b00 cmp r3, #0 8001336: d0f0 beq.n 800131a 8001338: e036 b.n 80013a8 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800133a: 4b1f ldr r3, [pc, #124] @ (80013b8 ) 800133c: 2200 movs r2, #0 800133e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001340: f7ff fa76 bl 8000830 8001344: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8001346: e008 b.n 800135a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001348: f7ff fa72 bl 8000830 800134c: 4602 mov r2, r0 800134e: 693b ldr r3, [r7, #16] 8001350: 1ad3 subs r3, r2, r3 8001352: 2b02 cmp r3, #2 8001354: d901 bls.n 800135a { return HAL_TIMEOUT; 8001356: 2303 movs r3, #3 8001358: e027 b.n 80013aa while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800135a: 4b16 ldr r3, [pc, #88] @ (80013b4 ) 800135c: 681b ldr r3, [r3, #0] 800135e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001362: 2b00 cmp r3, #0 8001364: d1f0 bne.n 8001348 8001366: e01f b.n 80013a8 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001368: 687b ldr r3, [r7, #4] 800136a: 6a5b ldr r3, [r3, #36] @ 0x24 800136c: 2b01 cmp r3, #1 800136e: d101 bne.n 8001374 { return HAL_ERROR; 8001370: 2301 movs r3, #1 8001372: e01a b.n 80013aa } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8001374: 4b0f ldr r3, [pc, #60] @ (80013b4 ) 8001376: 689b ldr r3, [r3, #8] 8001378: 617b str r3, [r7, #20] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800137a: 697b ldr r3, [r7, #20] 800137c: f403 3280 and.w r2, r3, #65536 @ 0x10000 8001380: 687b ldr r3, [r7, #4] 8001382: 6a9b ldr r3, [r3, #40] @ 0x28 8001384: 429a cmp r2, r3 8001386: d10d bne.n 80013a4 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || 8001388: 697b ldr r3, [r7, #20] 800138a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000 800138e: 687b ldr r3, [r7, #4] 8001390: 6adb ldr r3, [r3, #44] @ 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001392: 429a cmp r2, r3 8001394: d106 bne.n 80013a4 (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) 8001396: 697b ldr r3, [r7, #20] 8001398: f403 0240 and.w r2, r3, #12582912 @ 0xc00000 800139c: 687b ldr r3, [r7, #4] 800139e: 6b1b ldr r3, [r3, #48] @ 0x30 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || 80013a0: 429a cmp r2, r3 80013a2: d001 beq.n 80013a8 { return HAL_ERROR; 80013a4: 2301 movs r3, #1 80013a6: e000 b.n 80013aa } } } } return HAL_OK; 80013a8: 2300 movs r3, #0 } 80013aa: 4618 mov r0, r3 80013ac: 3720 adds r7, #32 80013ae: 46bd mov sp, r7 80013b0: bd80 pop {r7, pc} 80013b2: bf00 nop 80013b4: 40023800 .word 0x40023800 80013b8: 42470060 .word 0x42470060 080013bc : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80013bc: b580 push {r7, lr} 80013be: b084 sub sp, #16 80013c0: af00 add r7, sp, #0 80013c2: 6078 str r0, [r7, #4] 80013c4: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status; /* Check the parameters */ if(RCC_ClkInitStruct == NULL) 80013c6: 687b ldr r3, [r7, #4] 80013c8: 2b00 cmp r3, #0 80013ca: d101 bne.n 80013d0 { return HAL_ERROR; 80013cc: 2301 movs r3, #1 80013ce: e11a b.n 8001606 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 80013d0: 4b8f ldr r3, [pc, #572] @ (8001610 ) 80013d2: 681b ldr r3, [r3, #0] 80013d4: f003 0301 and.w r3, r3, #1 80013d8: 683a ldr r2, [r7, #0] 80013da: 429a cmp r2, r3 80013dc: d919 bls.n 8001412 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80013de: 683b ldr r3, [r7, #0] 80013e0: 2b01 cmp r3, #1 80013e2: d105 bne.n 80013f0 80013e4: 4b8a ldr r3, [pc, #552] @ (8001610 ) 80013e6: 681b ldr r3, [r3, #0] 80013e8: 4a89 ldr r2, [pc, #548] @ (8001610 ) 80013ea: f043 0304 orr.w r3, r3, #4 80013ee: 6013 str r3, [r2, #0] 80013f0: 4b87 ldr r3, [pc, #540] @ (8001610 ) 80013f2: 681b ldr r3, [r3, #0] 80013f4: f023 0201 bic.w r2, r3, #1 80013f8: 4985 ldr r1, [pc, #532] @ (8001610 ) 80013fa: 683b ldr r3, [r7, #0] 80013fc: 4313 orrs r3, r2 80013fe: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001400: 4b83 ldr r3, [pc, #524] @ (8001610 ) 8001402: 681b ldr r3, [r3, #0] 8001404: f003 0301 and.w r3, r3, #1 8001408: 683a ldr r2, [r7, #0] 800140a: 429a cmp r2, r3 800140c: d001 beq.n 8001412 { return HAL_ERROR; 800140e: 2301 movs r3, #1 8001410: e0f9 b.n 8001606 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8001412: 687b ldr r3, [r7, #4] 8001414: 681b ldr r3, [r3, #0] 8001416: f003 0302 and.w r3, r3, #2 800141a: 2b00 cmp r3, #0 800141c: d008 beq.n 8001430 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800141e: 4b7d ldr r3, [pc, #500] @ (8001614 ) 8001420: 689b ldr r3, [r3, #8] 8001422: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8001426: 687b ldr r3, [r7, #4] 8001428: 689b ldr r3, [r3, #8] 800142a: 497a ldr r1, [pc, #488] @ (8001614 ) 800142c: 4313 orrs r3, r2 800142e: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8001430: 687b ldr r3, [r7, #4] 8001432: 681b ldr r3, [r3, #0] 8001434: f003 0301 and.w r3, r3, #1 8001438: 2b00 cmp r3, #0 800143a: f000 808e beq.w 800155a { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800143e: 687b ldr r3, [r7, #4] 8001440: 685b ldr r3, [r3, #4] 8001442: 2b02 cmp r3, #2 8001444: d107 bne.n 8001456 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8001446: 4b73 ldr r3, [pc, #460] @ (8001614 ) 8001448: 681b ldr r3, [r3, #0] 800144a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800144e: 2b00 cmp r3, #0 8001450: d121 bne.n 8001496 { return HAL_ERROR; 8001452: 2301 movs r3, #1 8001454: e0d7 b.n 8001606 } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001456: 687b ldr r3, [r7, #4] 8001458: 685b ldr r3, [r3, #4] 800145a: 2b03 cmp r3, #3 800145c: d107 bne.n 800146e { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800145e: 4b6d ldr r3, [pc, #436] @ (8001614 ) 8001460: 681b ldr r3, [r3, #0] 8001462: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001466: 2b00 cmp r3, #0 8001468: d115 bne.n 8001496 { return HAL_ERROR; 800146a: 2301 movs r3, #1 800146c: e0cb b.n 8001606 } } /* HSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 800146e: 687b ldr r3, [r7, #4] 8001470: 685b ldr r3, [r3, #4] 8001472: 2b01 cmp r3, #1 8001474: d107 bne.n 8001486 { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8001476: 4b67 ldr r3, [pc, #412] @ (8001614 ) 8001478: 681b ldr r3, [r3, #0] 800147a: f003 0302 and.w r3, r3, #2 800147e: 2b00 cmp r3, #0 8001480: d109 bne.n 8001496 { return HAL_ERROR; 8001482: 2301 movs r3, #1 8001484: e0bf b.n 8001606 } /* MSI is selected as System Clock Source */ else { /* Check the MSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) 8001486: 4b63 ldr r3, [pc, #396] @ (8001614 ) 8001488: 681b ldr r3, [r3, #0] 800148a: f403 7300 and.w r3, r3, #512 @ 0x200 800148e: 2b00 cmp r3, #0 8001490: d101 bne.n 8001496 { return HAL_ERROR; 8001492: 2301 movs r3, #1 8001494: e0b7 b.n 8001606 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8001496: 4b5f ldr r3, [pc, #380] @ (8001614 ) 8001498: 689b ldr r3, [r3, #8] 800149a: f023 0203 bic.w r2, r3, #3 800149e: 687b ldr r3, [r7, #4] 80014a0: 685b ldr r3, [r3, #4] 80014a2: 495c ldr r1, [pc, #368] @ (8001614 ) 80014a4: 4313 orrs r3, r2 80014a6: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 80014a8: f7ff f9c2 bl 8000830 80014ac: 60f8 str r0, [r7, #12] if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80014ae: 687b ldr r3, [r7, #4] 80014b0: 685b ldr r3, [r3, #4] 80014b2: 2b02 cmp r3, #2 80014b4: d112 bne.n 80014dc { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) 80014b6: e00a b.n 80014ce { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80014b8: f7ff f9ba bl 8000830 80014bc: 4602 mov r2, r0 80014be: 68fb ldr r3, [r7, #12] 80014c0: 1ad3 subs r3, r2, r3 80014c2: f241 3288 movw r2, #5000 @ 0x1388 80014c6: 4293 cmp r3, r2 80014c8: d901 bls.n 80014ce { return HAL_TIMEOUT; 80014ca: 2303 movs r3, #3 80014cc: e09b b.n 8001606 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) 80014ce: 4b51 ldr r3, [pc, #324] @ (8001614 ) 80014d0: 689b ldr r3, [r3, #8] 80014d2: f003 030c and.w r3, r3, #12 80014d6: 2b08 cmp r3, #8 80014d8: d1ee bne.n 80014b8 80014da: e03e b.n 800155a } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80014dc: 687b ldr r3, [r7, #4] 80014de: 685b ldr r3, [r3, #4] 80014e0: 2b03 cmp r3, #3 80014e2: d112 bne.n 800150a { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80014e4: e00a b.n 80014fc { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80014e6: f7ff f9a3 bl 8000830 80014ea: 4602 mov r2, r0 80014ec: 68fb ldr r3, [r7, #12] 80014ee: 1ad3 subs r3, r2, r3 80014f0: f241 3288 movw r2, #5000 @ 0x1388 80014f4: 4293 cmp r3, r2 80014f6: d901 bls.n 80014fc { return HAL_TIMEOUT; 80014f8: 2303 movs r3, #3 80014fa: e084 b.n 8001606 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80014fc: 4b45 ldr r3, [pc, #276] @ (8001614 ) 80014fe: 689b ldr r3, [r3, #8] 8001500: f003 030c and.w r3, r3, #12 8001504: 2b0c cmp r3, #12 8001506: d1ee bne.n 80014e6 8001508: e027 b.n 800155a } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 800150a: 687b ldr r3, [r7, #4] 800150c: 685b ldr r3, [r3, #4] 800150e: 2b01 cmp r3, #1 8001510: d11d bne.n 800154e { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) 8001512: e00a b.n 800152a { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8001514: f7ff f98c bl 8000830 8001518: 4602 mov r2, r0 800151a: 68fb ldr r3, [r7, #12] 800151c: 1ad3 subs r3, r2, r3 800151e: f241 3288 movw r2, #5000 @ 0x1388 8001522: 4293 cmp r3, r2 8001524: d901 bls.n 800152a { return HAL_TIMEOUT; 8001526: 2303 movs r3, #3 8001528: e06d b.n 8001606 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) 800152a: 4b3a ldr r3, [pc, #232] @ (8001614 ) 800152c: 689b ldr r3, [r3, #8] 800152e: f003 030c and.w r3, r3, #12 8001532: 2b04 cmp r3, #4 8001534: d1ee bne.n 8001514 8001536: e010 b.n 800155a } else { while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8001538: f7ff f97a bl 8000830 800153c: 4602 mov r2, r0 800153e: 68fb ldr r3, [r7, #12] 8001540: 1ad3 subs r3, r2, r3 8001542: f241 3288 movw r2, #5000 @ 0x1388 8001546: 4293 cmp r3, r2 8001548: d901 bls.n 800154e { return HAL_TIMEOUT; 800154a: 2303 movs r3, #3 800154c: e05b b.n 8001606 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) 800154e: 4b31 ldr r3, [pc, #196] @ (8001614 ) 8001550: 689b ldr r3, [r3, #8] 8001552: f003 030c and.w r3, r3, #12 8001556: 2b00 cmp r3, #0 8001558: d1ee bne.n 8001538 } } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 800155a: 4b2d ldr r3, [pc, #180] @ (8001610 ) 800155c: 681b ldr r3, [r3, #0] 800155e: f003 0301 and.w r3, r3, #1 8001562: 683a ldr r2, [r7, #0] 8001564: 429a cmp r2, r3 8001566: d219 bcs.n 800159c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001568: 683b ldr r3, [r7, #0] 800156a: 2b01 cmp r3, #1 800156c: d105 bne.n 800157a 800156e: 4b28 ldr r3, [pc, #160] @ (8001610 ) 8001570: 681b ldr r3, [r3, #0] 8001572: 4a27 ldr r2, [pc, #156] @ (8001610 ) 8001574: f043 0304 orr.w r3, r3, #4 8001578: 6013 str r3, [r2, #0] 800157a: 4b25 ldr r3, [pc, #148] @ (8001610 ) 800157c: 681b ldr r3, [r3, #0] 800157e: f023 0201 bic.w r2, r3, #1 8001582: 4923 ldr r1, [pc, #140] @ (8001610 ) 8001584: 683b ldr r3, [r7, #0] 8001586: 4313 orrs r3, r2 8001588: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 800158a: 4b21 ldr r3, [pc, #132] @ (8001610 ) 800158c: 681b ldr r3, [r3, #0] 800158e: f003 0301 and.w r3, r3, #1 8001592: 683a ldr r2, [r7, #0] 8001594: 429a cmp r2, r3 8001596: d001 beq.n 800159c { return HAL_ERROR; 8001598: 2301 movs r3, #1 800159a: e034 b.n 8001606 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800159c: 687b ldr r3, [r7, #4] 800159e: 681b ldr r3, [r3, #0] 80015a0: f003 0304 and.w r3, r3, #4 80015a4: 2b00 cmp r3, #0 80015a6: d008 beq.n 80015ba { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 80015a8: 4b1a ldr r3, [pc, #104] @ (8001614 ) 80015aa: 689b ldr r3, [r3, #8] 80015ac: f423 62e0 bic.w r2, r3, #1792 @ 0x700 80015b0: 687b ldr r3, [r7, #4] 80015b2: 68db ldr r3, [r3, #12] 80015b4: 4917 ldr r1, [pc, #92] @ (8001614 ) 80015b6: 4313 orrs r3, r2 80015b8: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80015ba: 687b ldr r3, [r7, #4] 80015bc: 681b ldr r3, [r3, #0] 80015be: f003 0308 and.w r3, r3, #8 80015c2: 2b00 cmp r3, #0 80015c4: d009 beq.n 80015da { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 80015c6: 4b13 ldr r3, [pc, #76] @ (8001614 ) 80015c8: 689b ldr r3, [r3, #8] 80015ca: f423 5260 bic.w r2, r3, #14336 @ 0x3800 80015ce: 687b ldr r3, [r7, #4] 80015d0: 691b ldr r3, [r3, #16] 80015d2: 00db lsls r3, r3, #3 80015d4: 490f ldr r1, [pc, #60] @ (8001614 ) 80015d6: 4313 orrs r3, r2 80015d8: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; 80015da: f000 f823 bl 8001624 80015de: 4602 mov r2, r0 80015e0: 4b0c ldr r3, [pc, #48] @ (8001614 ) 80015e2: 689b ldr r3, [r3, #8] 80015e4: 091b lsrs r3, r3, #4 80015e6: f003 030f and.w r3, r3, #15 80015ea: 490b ldr r1, [pc, #44] @ (8001618 ) 80015ec: 5ccb ldrb r3, [r1, r3] 80015ee: fa22 f303 lsr.w r3, r2, r3 80015f2: 4a0a ldr r2, [pc, #40] @ (800161c ) 80015f4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); 80015f6: 4b0a ldr r3, [pc, #40] @ (8001620 ) 80015f8: 681b ldr r3, [r3, #0] 80015fa: 4618 mov r0, r3 80015fc: f7ff f8cc bl 8000798 8001600: 4603 mov r3, r0 8001602: 72fb strb r3, [r7, #11] return status; 8001604: 7afb ldrb r3, [r7, #11] } 8001606: 4618 mov r0, r3 8001608: 3710 adds r7, #16 800160a: 46bd mov sp, r7 800160c: bd80 pop {r7, pc} 800160e: bf00 nop 8001610: 40023c00 .word 0x40023c00 8001614: 40023800 .word 0x40023800 8001618: 080018dc .word 0x080018dc 800161c: 20000000 .word 0x20000000 8001620: 20000004 .word 0x20000004 08001624 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8001624: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8001628: b08e sub sp, #56 @ 0x38 800162a: af00 add r7, sp, #0 uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; tmpreg = RCC->CFGR; 800162c: 4b58 ldr r3, [pc, #352] @ (8001790 ) 800162e: 689b ldr r3, [r3, #8] 8001630: 62fb str r3, [r7, #44] @ 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8001632: 6afb ldr r3, [r7, #44] @ 0x2c 8001634: f003 030c and.w r3, r3, #12 8001638: 2b0c cmp r3, #12 800163a: d00d beq.n 8001658 800163c: 2b0c cmp r3, #12 800163e: f200 8092 bhi.w 8001766 8001642: 2b04 cmp r3, #4 8001644: d002 beq.n 800164c 8001646: 2b08 cmp r3, #8 8001648: d003 beq.n 8001652 800164a: e08c b.n 8001766 { case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 800164c: 4b51 ldr r3, [pc, #324] @ (8001794 ) 800164e: 633b str r3, [r7, #48] @ 0x30 break; 8001650: e097 b.n 8001782 } case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8001652: 4b51 ldr r3, [pc, #324] @ (8001798 ) 8001654: 633b str r3, [r7, #48] @ 0x30 break; 8001656: e094 b.n 8001782 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; 8001658: 6afb ldr r3, [r7, #44] @ 0x2c 800165a: 0c9b lsrs r3, r3, #18 800165c: f003 020f and.w r2, r3, #15 8001660: 4b4e ldr r3, [pc, #312] @ (800179c ) 8001662: 5c9b ldrb r3, [r3, r2] 8001664: 62bb str r3, [r7, #40] @ 0x28 plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; 8001666: 6afb ldr r3, [r7, #44] @ 0x2c 8001668: 0d9b lsrs r3, r3, #22 800166a: f003 0303 and.w r3, r3, #3 800166e: 3301 adds r3, #1 8001670: 627b str r3, [r7, #36] @ 0x24 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8001672: 4b47 ldr r3, [pc, #284] @ (8001790 ) 8001674: 689b ldr r3, [r3, #8] 8001676: f403 3380 and.w r3, r3, #65536 @ 0x10000 800167a: 2b00 cmp r3, #0 800167c: d021 beq.n 80016c2 { /* HSE used as PLL clock source */ pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); 800167e: 6abb ldr r3, [r7, #40] @ 0x28 8001680: 2200 movs r2, #0 8001682: 61bb str r3, [r7, #24] 8001684: 61fa str r2, [r7, #28] 8001686: 4b44 ldr r3, [pc, #272] @ (8001798 ) 8001688: e9d7 8906 ldrd r8, r9, [r7, #24] 800168c: 464a mov r2, r9 800168e: fb03 f202 mul.w r2, r3, r2 8001692: 2300 movs r3, #0 8001694: 4644 mov r4, r8 8001696: fb04 f303 mul.w r3, r4, r3 800169a: 4413 add r3, r2 800169c: 4a3e ldr r2, [pc, #248] @ (8001798 ) 800169e: 4644 mov r4, r8 80016a0: fba4 0102 umull r0, r1, r4, r2 80016a4: 440b add r3, r1 80016a6: 4619 mov r1, r3 80016a8: 6a7b ldr r3, [r7, #36] @ 0x24 80016aa: 2200 movs r2, #0 80016ac: 613b str r3, [r7, #16] 80016ae: 617a str r2, [r7, #20] 80016b0: e9d7 2304 ldrd r2, r3, [r7, #16] 80016b4: f7fe fd62 bl 800017c <__aeabi_uldivmod> 80016b8: 4602 mov r2, r0 80016ba: 460b mov r3, r1 80016bc: 4613 mov r3, r2 80016be: 637b str r3, [r7, #52] @ 0x34 80016c0: e04e b.n 8001760 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); 80016c2: 6abb ldr r3, [r7, #40] @ 0x28 80016c4: 2200 movs r2, #0 80016c6: 469a mov sl, r3 80016c8: 4693 mov fp, r2 80016ca: 4652 mov r2, sl 80016cc: 465b mov r3, fp 80016ce: f04f 0000 mov.w r0, #0 80016d2: f04f 0100 mov.w r1, #0 80016d6: 0159 lsls r1, r3, #5 80016d8: ea41 61d2 orr.w r1, r1, r2, lsr #27 80016dc: 0150 lsls r0, r2, #5 80016de: 4602 mov r2, r0 80016e0: 460b mov r3, r1 80016e2: ebb2 080a subs.w r8, r2, sl 80016e6: eb63 090b sbc.w r9, r3, fp 80016ea: f04f 0200 mov.w r2, #0 80016ee: f04f 0300 mov.w r3, #0 80016f2: ea4f 1389 mov.w r3, r9, lsl #6 80016f6: ea43 6398 orr.w r3, r3, r8, lsr #26 80016fa: ea4f 1288 mov.w r2, r8, lsl #6 80016fe: ebb2 0408 subs.w r4, r2, r8 8001702: eb63 0509 sbc.w r5, r3, r9 8001706: f04f 0200 mov.w r2, #0 800170a: f04f 0300 mov.w r3, #0 800170e: 00eb lsls r3, r5, #3 8001710: ea43 7354 orr.w r3, r3, r4, lsr #29 8001714: 00e2 lsls r2, r4, #3 8001716: 4614 mov r4, r2 8001718: 461d mov r5, r3 800171a: eb14 030a adds.w r3, r4, sl 800171e: 603b str r3, [r7, #0] 8001720: eb45 030b adc.w r3, r5, fp 8001724: 607b str r3, [r7, #4] 8001726: f04f 0200 mov.w r2, #0 800172a: f04f 0300 mov.w r3, #0 800172e: e9d7 4500 ldrd r4, r5, [r7] 8001732: 4629 mov r1, r5 8001734: 028b lsls r3, r1, #10 8001736: 4620 mov r0, r4 8001738: 4629 mov r1, r5 800173a: 4604 mov r4, r0 800173c: ea43 5394 orr.w r3, r3, r4, lsr #22 8001740: 4601 mov r1, r0 8001742: 028a lsls r2, r1, #10 8001744: 4610 mov r0, r2 8001746: 4619 mov r1, r3 8001748: 6a7b ldr r3, [r7, #36] @ 0x24 800174a: 2200 movs r2, #0 800174c: 60bb str r3, [r7, #8] 800174e: 60fa str r2, [r7, #12] 8001750: e9d7 2302 ldrd r2, r3, [r7, #8] 8001754: f7fe fd12 bl 800017c <__aeabi_uldivmod> 8001758: 4602 mov r2, r0 800175a: 460b mov r3, r1 800175c: 4613 mov r3, r2 800175e: 637b str r3, [r7, #52] @ 0x34 } sysclockfreq = pllvco; 8001760: 6b7b ldr r3, [r7, #52] @ 0x34 8001762: 633b str r3, [r7, #48] @ 0x30 break; 8001764: e00d b.n 8001782 } case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ default: /* MSI used as system clock */ { msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; 8001766: 4b0a ldr r3, [pc, #40] @ (8001790 ) 8001768: 685b ldr r3, [r3, #4] 800176a: 0b5b lsrs r3, r3, #13 800176c: f003 0307 and.w r3, r3, #7 8001770: 623b str r3, [r7, #32] sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); 8001772: 6a3b ldr r3, [r7, #32] 8001774: 3301 adds r3, #1 8001776: f44f 4200 mov.w r2, #32768 @ 0x8000 800177a: fa02 f303 lsl.w r3, r2, r3 800177e: 633b str r3, [r7, #48] @ 0x30 break; 8001780: bf00 nop } } return sysclockfreq; 8001782: 6b3b ldr r3, [r7, #48] @ 0x30 } 8001784: 4618 mov r0, r3 8001786: 3738 adds r7, #56 @ 0x38 8001788: 46bd mov sp, r7 800178a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800178e: bf00 nop 8001790: 40023800 .word 0x40023800 8001794: 00f42400 .word 0x00f42400 8001798: 016e3600 .word 0x016e3600 800179c: 080018d0 .word 0x080018d0 080017a0 : voltage range * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) { 80017a0: b480 push {r7} 80017a2: b087 sub sp, #28 80017a4: af00 add r7, sp, #0 80017a6: 6078 str r0, [r7, #4] uint32_t vos; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ 80017a8: 2300 movs r3, #0 80017aa: 613b str r3, [r7, #16] /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) 80017ac: 4b29 ldr r3, [pc, #164] @ (8001854 ) 80017ae: 689b ldr r3, [r3, #8] 80017b0: f003 03f0 and.w r3, r3, #240 @ 0xf0 80017b4: 2b00 cmp r3, #0 80017b6: d12c bne.n 8001812 { if(__HAL_RCC_PWR_IS_CLK_ENABLED()) 80017b8: 4b26 ldr r3, [pc, #152] @ (8001854 ) 80017ba: 6a5b ldr r3, [r3, #36] @ 0x24 80017bc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80017c0: 2b00 cmp r3, #0 80017c2: d005 beq.n 80017d0 { vos = READ_BIT(PWR->CR, PWR_CR_VOS); 80017c4: 4b24 ldr r3, [pc, #144] @ (8001858 ) 80017c6: 681b ldr r3, [r3, #0] 80017c8: f403 53c0 and.w r3, r3, #6144 @ 0x1800 80017cc: 617b str r3, [r7, #20] 80017ce: e016 b.n 80017fe } else { __HAL_RCC_PWR_CLK_ENABLE(); 80017d0: 4b20 ldr r3, [pc, #128] @ (8001854 ) 80017d2: 6a5b ldr r3, [r3, #36] @ 0x24 80017d4: 4a1f ldr r2, [pc, #124] @ (8001854 ) 80017d6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80017da: 6253 str r3, [r2, #36] @ 0x24 80017dc: 4b1d ldr r3, [pc, #116] @ (8001854 ) 80017de: 6a5b ldr r3, [r3, #36] @ 0x24 80017e0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80017e4: 60fb str r3, [r7, #12] 80017e6: 68fb ldr r3, [r7, #12] vos = READ_BIT(PWR->CR, PWR_CR_VOS); 80017e8: 4b1b ldr r3, [pc, #108] @ (8001858 ) 80017ea: 681b ldr r3, [r3, #0] 80017ec: f403 53c0 and.w r3, r3, #6144 @ 0x1800 80017f0: 617b str r3, [r7, #20] __HAL_RCC_PWR_CLK_DISABLE(); 80017f2: 4b18 ldr r3, [pc, #96] @ (8001854 ) 80017f4: 6a5b ldr r3, [r3, #36] @ 0x24 80017f6: 4a17 ldr r2, [pc, #92] @ (8001854 ) 80017f8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80017fc: 6253 str r3, [r2, #36] @ 0x24 } /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) 80017fe: 697b ldr r3, [r7, #20] 8001800: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800 8001804: d105 bne.n 8001812 8001806: 687b ldr r3, [r7, #4] 8001808: f5b3 4f40 cmp.w r3, #49152 @ 0xc000 800180c: d101 bne.n 8001812 { latency = FLASH_LATENCY_1; /* 1WS */ 800180e: 2301 movs r3, #1 8001810: 613b str r3, [r7, #16] } } __HAL_FLASH_SET_LATENCY(latency); 8001812: 693b ldr r3, [r7, #16] 8001814: 2b01 cmp r3, #1 8001816: d105 bne.n 8001824 8001818: 4b10 ldr r3, [pc, #64] @ (800185c ) 800181a: 681b ldr r3, [r3, #0] 800181c: 4a0f ldr r2, [pc, #60] @ (800185c ) 800181e: f043 0304 orr.w r3, r3, #4 8001822: 6013 str r3, [r2, #0] 8001824: 4b0d ldr r3, [pc, #52] @ (800185c ) 8001826: 681b ldr r3, [r3, #0] 8001828: f023 0201 bic.w r2, r3, #1 800182c: 490b ldr r1, [pc, #44] @ (800185c ) 800182e: 693b ldr r3, [r7, #16] 8001830: 4313 orrs r3, r2 8001832: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != latency) 8001834: 4b09 ldr r3, [pc, #36] @ (800185c ) 8001836: 681b ldr r3, [r3, #0] 8001838: f003 0301 and.w r3, r3, #1 800183c: 693a ldr r2, [r7, #16] 800183e: 429a cmp r2, r3 8001840: d001 beq.n 8001846 { return HAL_ERROR; 8001842: 2301 movs r3, #1 8001844: e000 b.n 8001848 } return HAL_OK; 8001846: 2300 movs r3, #0 } 8001848: 4618 mov r0, r3 800184a: 371c adds r7, #28 800184c: 46bd mov sp, r7 800184e: bc80 pop {r7} 8001850: 4770 bx lr 8001852: bf00 nop 8001854: 40023800 .word 0x40023800 8001858: 40007000 .word 0x40007000 800185c: 40023c00 .word 0x40023c00 08001860 : 8001860: 4603 mov r3, r0 8001862: 4402 add r2, r0 8001864: 4293 cmp r3, r2 8001866: d100 bne.n 800186a 8001868: 4770 bx lr 800186a: f803 1b01 strb.w r1, [r3], #1 800186e: e7f9 b.n 8001864 08001870 <__libc_init_array>: 8001870: b570 push {r4, r5, r6, lr} 8001872: 2600 movs r6, #0 8001874: 4d0c ldr r5, [pc, #48] @ (80018a8 <__libc_init_array+0x38>) 8001876: 4c0d ldr r4, [pc, #52] @ (80018ac <__libc_init_array+0x3c>) 8001878: 1b64 subs r4, r4, r5 800187a: 10a4 asrs r4, r4, #2 800187c: 42a6 cmp r6, r4 800187e: d109 bne.n 8001894 <__libc_init_array+0x24> 8001880: f000 f81a bl 80018b8 <_init> 8001884: 2600 movs r6, #0 8001886: 4d0a ldr r5, [pc, #40] @ (80018b0 <__libc_init_array+0x40>) 8001888: 4c0a ldr r4, [pc, #40] @ (80018b4 <__libc_init_array+0x44>) 800188a: 1b64 subs r4, r4, r5 800188c: 10a4 asrs r4, r4, #2 800188e: 42a6 cmp r6, r4 8001890: d105 bne.n 800189e <__libc_init_array+0x2e> 8001892: bd70 pop {r4, r5, r6, pc} 8001894: f855 3b04 ldr.w r3, [r5], #4 8001898: 4798 blx r3 800189a: 3601 adds r6, #1 800189c: e7ee b.n 800187c <__libc_init_array+0xc> 800189e: f855 3b04 ldr.w r3, [r5], #4 80018a2: 4798 blx r3 80018a4: 3601 adds r6, #1 80018a6: e7f2 b.n 800188e <__libc_init_array+0x1e> 80018a8: 080018f4 .word 0x080018f4 80018ac: 080018f4 .word 0x080018f4 80018b0: 080018f4 .word 0x080018f4 80018b4: 080018f8 .word 0x080018f8 080018b8 <_init>: 80018b8: b5f8 push {r3, r4, r5, r6, r7, lr} 80018ba: bf00 nop 80018bc: bcf8 pop {r3, r4, r5, r6, r7} 80018be: bc08 pop {r3} 80018c0: 469e mov lr, r3 80018c2: 4770 bx lr 080018c4 <_fini>: 80018c4: b5f8 push {r3, r4, r5, r6, r7, lr} 80018c6: bf00 nop 80018c8: bcf8 pop {r3, r4, r5, r6, r7} 80018ca: bc08 pop {r3} 80018cc: 469e mov lr, r3 80018ce: 4770 bx lr