BreizhHardware/TP-STM32-CIPA3
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TP-STM32-CIPA3/TP1_CHENI_LED/Debug/TP1_CHENI_LED.list
Félix MARQUET 2968585301 TP1 Exo 4 (Chenillard)
2025-06-24 09:25:19 +02:00

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TP1_CHENI_LED.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000186c 0800013c 0800013c 0000113c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000001c 080019a8 080019a8 000029a8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080019c4 080019c4 0000300c 2**0
CONTENTS, READONLY
4 .ARM 00000008 080019c4 080019c4 000029c4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080019cc 080019cc 0000300c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080019cc 080019cc 000029cc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 080019d0 080019d0 000029d0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 080019d4 00003000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000020 2000000c 080019e0 0000300c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000002c 080019e0 0000302c 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000300c 2**0
CONTENTS, READONLY
12 .debug_info 00002ee8 00000000 00000000 00003035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00000ea9 00000000 00000000 00005f1d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000410 00000000 00000000 00006dc8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000002e9 00000000 00000000 000071d8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00014382 00000000 00000000 000074c1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00004b03 00000000 00000000 0001b843 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0007f0f5 00000000 00000000 00020346 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 0009f43b 2**0
CONTENTS, READONLY
20 .debug_frame 00000edc 00000000 00000000 0009f480 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000006d 00000000 00000000 000a035c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800013c <__do_global_dtors_aux>:
800013c: b510 push {r4, lr}
800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>)
8000140: 7823 ldrb r3, [r4, #0]
8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16>
8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>)
8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12>
8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>)
800014a: f3af 8000 nop.w
800014e: 2301 movs r3, #1
8000150: 7023 strb r3, [r4, #0]
8000152: bd10 pop {r4, pc}
8000154: 2000000c .word 0x2000000c
8000158: 00000000 .word 0x00000000
800015c: 08001990 .word 0x08001990
08000160 <frame_dummy>:
8000160: b508 push {r3, lr}
8000162: 4b03 ldr r3, [pc, #12] @ (8000170 <frame_dummy+0x10>)
8000164: b11b cbz r3, 800016e <frame_dummy+0xe>
8000166: 4903 ldr r1, [pc, #12] @ (8000174 <frame_dummy+0x14>)
8000168: 4803 ldr r0, [pc, #12] @ (8000178 <frame_dummy+0x18>)
800016a: f3af 8000 nop.w
800016e: bd08 pop {r3, pc}
8000170: 00000000 .word 0x00000000
8000174: 20000010 .word 0x20000010
8000178: 08001990 .word 0x08001990
0800017c <__aeabi_uldivmod>:
800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18>
800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18>
8000180: 2900 cmp r1, #0
8000182: bf08 it eq
8000184: 2800 cmpeq r0, #0
8000186: bf1c itt ne
8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
8000190: f000 b98c b.w 80004ac <__aeabi_idiv0>
8000194: f1ad 0c08 sub.w ip, sp, #8
8000198: e96d ce04 strd ip, lr, [sp, #-16]!
800019c: f000 f806 bl 80001ac <__udivmoddi4>
80001a0: f8dd e004 ldr.w lr, [sp, #4]
80001a4: e9dd 2302 ldrd r2, r3, [sp, #8]
80001a8: b004 add sp, #16
80001aa: 4770 bx lr
080001ac <__udivmoddi4>:
80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001b0: 9d08 ldr r5, [sp, #32]
80001b2: 468e mov lr, r1
80001b4: 4604 mov r4, r0
80001b6: 4688 mov r8, r1
80001b8: 2b00 cmp r3, #0
80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6>
80001bc: 428a cmp r2, r1
80001be: 4617 mov r7, r2
80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc>
80001c2: fab2 f682 clz r6, r2
80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30>
80001c8: f1c6 0320 rsb r3, r6, #32
80001cc: fa01 f806 lsl.w r8, r1, r6
80001d0: fa20 f303 lsr.w r3, r0, r3
80001d4: 40b7 lsls r7, r6
80001d6: ea43 0808 orr.w r8, r3, r8
80001da: 40b4 lsls r4, r6
80001dc: ea4f 4e17 mov.w lr, r7, lsr #16
80001e0: fbb8 f1fe udiv r1, r8, lr
80001e4: fa1f fc87 uxth.w ip, r7
80001e8: fb0e 8811 mls r8, lr, r1, r8
80001ec: fb01 f20c mul.w r2, r1, ip
80001f0: 0c23 lsrs r3, r4, #16
80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16
80001f6: 429a cmp r2, r3
80001f8: d909 bls.n 800020e <__udivmoddi4+0x62>
80001fa: 18fb adds r3, r7, r3
80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e>
8000204: 429a cmp r2, r3
8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e>
800020a: 3902 subs r1, #2
800020c: 443b add r3, r7
800020e: 1a9a subs r2, r3, r2
8000210: fbb2 f0fe udiv r0, r2, lr
8000214: fb0e 2210 mls r2, lr, r0, r2
8000218: fb00 fc0c mul.w ip, r0, ip
800021c: b2a3 uxth r3, r4
800021e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000222: 459c cmp ip, r3
8000224: d909 bls.n 800023a <__udivmoddi4+0x8e>
8000226: 18fb adds r3, r7, r3
8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232>
8000230: 459c cmp ip, r3
8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232>
8000236: 443b add r3, r7
8000238: 3802 subs r0, #2
800023a: ea40 4001 orr.w r0, r0, r1, lsl #16
800023e: 2100 movs r1, #0
8000240: eba3 030c sub.w r3, r3, ip
8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2>
8000246: 2200 movs r2, #0
8000248: 40f3 lsrs r3, r6
800024a: e9c5 3200 strd r3, r2, [r5]
800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000252: 428b cmp r3, r1
8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6>
8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0>
8000258: e9c5 0100 strd r0, r1, [r5]
800025c: 2100 movs r1, #0
800025e: 4608 mov r0, r1
8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2>
8000262: fab3 f183 clz r1, r3
8000266: 2900 cmp r1, #0
8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c>
800026a: 4573 cmp r3, lr
800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8>
800026e: 4282 cmp r2, r0
8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8>
8000274: 1a84 subs r4, r0, r2
8000276: eb6e 0203 sbc.w r2, lr, r3
800027a: 2001 movs r0, #1
800027c: 4690 mov r8, r2
800027e: 2d00 cmp r5, #0
8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2>
8000282: e9c5 4800 strd r4, r8, [r5]
8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2>
8000288: 2a00 cmp r2, #0
800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204>
800028e: fab2 f682 clz r6, r2
8000292: 2e00 cmp r6, #0
8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236>
8000298: 1a8a subs r2, r1, r2
800029a: 2101 movs r1, #1
800029c: 0c03 lsrs r3, r0, #16
800029e: ea4f 4e17 mov.w lr, r7, lsr #16
80002a2: b280 uxth r0, r0
80002a4: b2bc uxth r4, r7
80002a6: fbb2 fcfe udiv ip, r2, lr
80002aa: fb0e 221c mls r2, lr, ip, r2
80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16
80002b2: fb04 f20c mul.w r2, r4, ip
80002b6: 429a cmp r2, r3
80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e>
80002ba: 18fb adds r3, r7, r3
80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c>
80002c2: 429a cmp r2, r3
80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2>
80002c8: 46c4 mov ip, r8
80002ca: 1a9b subs r3, r3, r2
80002cc: fbb3 f2fe udiv r2, r3, lr
80002d0: fb0e 3312 mls r3, lr, r2, r3
80002d4: fb02 f404 mul.w r4, r2, r4
80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16
80002dc: 429c cmp r4, r3
80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144>
80002e0: 18fb adds r3, r7, r3
80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142>
80002e8: 429c cmp r4, r3
80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc>
80002ee: 4602 mov r2, r0
80002f0: 1b1b subs r3, r3, r4
80002f2: ea42 400c orr.w r0, r2, ip, lsl #16
80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98>
80002f8: f1c1 0620 rsb r6, r1, #32
80002fc: 408b lsls r3, r1
80002fe: fa22 f706 lsr.w r7, r2, r6
8000302: 431f orrs r7, r3
8000304: fa2e fa06 lsr.w sl, lr, r6
8000308: ea4f 4917 mov.w r9, r7, lsr #16
800030c: fbba f8f9 udiv r8, sl, r9
8000310: fa0e fe01 lsl.w lr, lr, r1
8000314: fa20 f306 lsr.w r3, r0, r6
8000318: fb09 aa18 mls sl, r9, r8, sl
800031c: fa1f fc87 uxth.w ip, r7
8000320: ea43 030e orr.w r3, r3, lr
8000324: fa00 fe01 lsl.w lr, r0, r1
8000328: fb08 f00c mul.w r0, r8, ip
800032c: 0c1c lsrs r4, r3, #16
800032e: ea44 440a orr.w r4, r4, sl, lsl #16
8000332: 42a0 cmp r0, r4
8000334: fa02 f201 lsl.w r2, r2, r1
8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4>
800033a: 193c adds r4, r7, r4
800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff
8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4>
8000344: 42a0 cmp r0, r4
8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4>
800034a: f1a8 0802 sub.w r8, r8, #2
800034e: 443c add r4, r7
8000350: 1a24 subs r4, r4, r0
8000352: b298 uxth r0, r3
8000354: fbb4 f3f9 udiv r3, r4, r9
8000358: fb09 4413 mls r4, r9, r3, r4
800035c: fb03 fc0c mul.w ip, r3, ip
8000360: ea40 4404 orr.w r4, r0, r4, lsl #16
8000364: 45a4 cmp ip, r4
8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0>
8000368: 193c adds r4, r7, r4
800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff
800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0>
8000372: 45a4 cmp ip, r4
8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0>
8000378: 3b02 subs r3, #2
800037a: 443c add r4, r7
800037c: ea43 4008 orr.w r0, r3, r8, lsl #16
8000380: eba4 040c sub.w r4, r4, ip
8000384: fba0 8c02 umull r8, ip, r0, r2
8000388: 4564 cmp r4, ip
800038a: 4643 mov r3, r8
800038c: 46e1 mov r9, ip
800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae>
8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa>
8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200>
8000394: ebbe 0203 subs.w r2, lr, r3
8000398: eb64 0409 sbc.w r4, r4, r9
800039c: fa04 f606 lsl.w r6, r4, r6
80003a0: fa22 f301 lsr.w r3, r2, r1
80003a4: 431e orrs r6, r3
80003a6: 40cc lsrs r4, r1
80003a8: e9c5 6400 strd r6, r4, [r5]
80003ac: 2100 movs r1, #0
80003ae: e74e b.n 800024e <__udivmoddi4+0xa2>
80003b0: fbb1 fcf2 udiv ip, r1, r2
80003b4: 0c01 lsrs r1, r0, #16
80003b6: ea41 410e orr.w r1, r1, lr, lsl #16
80003ba: b280 uxth r0, r0
80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16
80003c0: 463b mov r3, r7
80003c2: fbb1 f1f7 udiv r1, r1, r7
80003c6: 4638 mov r0, r7
80003c8: 463c mov r4, r7
80003ca: 46b8 mov r8, r7
80003cc: 46be mov lr, r7
80003ce: 2620 movs r6, #32
80003d0: eba2 0208 sub.w r2, r2, r8
80003d4: ea41 410c orr.w r1, r1, ip, lsl #16
80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa>
80003da: 4601 mov r1, r0
80003dc: e717 b.n 800020e <__udivmoddi4+0x62>
80003de: 4610 mov r0, r2
80003e0: e72b b.n 800023a <__udivmoddi4+0x8e>
80003e2: f1c6 0120 rsb r1, r6, #32
80003e6: fa2e fc01 lsr.w ip, lr, r1
80003ea: 40b7 lsls r7, r6
80003ec: fa0e fe06 lsl.w lr, lr, r6
80003f0: fa20 f101 lsr.w r1, r0, r1
80003f4: ea41 010e orr.w r1, r1, lr
80003f8: ea4f 4e17 mov.w lr, r7, lsr #16
80003fc: fbbc f8fe udiv r8, ip, lr
8000400: b2bc uxth r4, r7
8000402: fb0e cc18 mls ip, lr, r8, ip
8000406: fb08 f904 mul.w r9, r8, r4
800040a: 0c0a lsrs r2, r1, #16
800040c: ea42 420c orr.w r2, r2, ip, lsl #16
8000410: 40b0 lsls r0, r6
8000412: 4591 cmp r9, r2
8000414: ea4f 4310 mov.w r3, r0, lsr #16
8000418: b280 uxth r0, r0
800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee>
800041c: 18ba adds r2, r7, r2
800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c>
8000424: 4591 cmp r9, r2
8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc>
8000428: eba2 0209 sub.w r2, r2, r9
800042c: fbb2 f9fe udiv r9, r2, lr
8000430: fb09 f804 mul.w r8, r9, r4
8000434: fb0e 2a19 mls sl, lr, r9, r2
8000438: b28a uxth r2, r1
800043a: ea42 420a orr.w r2, r2, sl, lsl #16
800043e: 4542 cmp r2, r8
8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea>
8000442: 18ba adds r2, r7, r2
8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224>
800044a: 4542 cmp r2, r8
800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224>
800044e: f1a9 0102 sub.w r1, r9, #2
8000452: 443a add r2, r7
8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224>
8000456: 45c6 cmp lr, r8
8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6>
800045a: ebb8 0302 subs.w r3, r8, r2
800045e: eb6c 0c07 sbc.w ip, ip, r7
8000462: 3801 subs r0, #1
8000464: 46e1 mov r9, ip
8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6>
8000468: eba7 0909 sub.w r9, r7, r9
800046c: 444a add r2, r9
800046e: fbb2 f9fe udiv r9, r2, lr
8000472: f1a8 0c02 sub.w ip, r8, #2
8000476: fb09 f804 mul.w r8, r9, r4
800047a: e7db b.n 8000434 <__udivmoddi4+0x288>
800047c: 4603 mov r3, r0
800047e: e77d b.n 800037c <__udivmoddi4+0x1d0>
8000480: 46d0 mov r8, sl
8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4>
8000484: 4608 mov r0, r1
8000486: e6fa b.n 800027e <__udivmoddi4+0xd2>
8000488: 443b add r3, r7
800048a: 3a02 subs r2, #2
800048c: e730 b.n 80002f0 <__udivmoddi4+0x144>
800048e: f1ac 0c02 sub.w ip, ip, #2
8000492: 443b add r3, r7
8000494: e719 b.n 80002ca <__udivmoddi4+0x11e>
8000496: 4649 mov r1, r9
8000498: e79a b.n 80003d0 <__udivmoddi4+0x224>
800049a: eba2 0209 sub.w r2, r2, r9
800049e: fbb2 f9fe udiv r9, r2, lr
80004a2: 46c4 mov ip, r8
80004a4: fb09 f804 mul.w r8, r9, r4
80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288>
80004aa: bf00 nop
080004ac <__aeabi_idiv0>:
80004ac: 4770 bx lr
80004ae: bf00 nop
080004b0 <init_ports_LED>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void init_ports_LED(void){
80004b0: b480 push {r7}
80004b2: b083 sub sp, #12
80004b4: af00 add r7, sp, #0
for (uint8_t i = 0 ; i <= 7 ; i++){
80004b6: 2300 movs r3, #0
80004b8: 71fb strb r3, [r7, #7]
80004ba: e00c b.n 80004d6 <init_ports_LED+0x26>
GPIOB->ODR |= (1<<i);
80004bc: 4b0a ldr r3, [pc, #40] @ (80004e8 <init_ports_LED+0x38>)
80004be: 695b ldr r3, [r3, #20]
80004c0: 79fa ldrb r2, [r7, #7]
80004c2: 2101 movs r1, #1
80004c4: fa01 f202 lsl.w r2, r1, r2
80004c8: 4611 mov r1, r2
80004ca: 4a07 ldr r2, [pc, #28] @ (80004e8 <init_ports_LED+0x38>)
80004cc: 430b orrs r3, r1
80004ce: 6153 str r3, [r2, #20]
for (uint8_t i = 0 ; i <= 7 ; i++){
80004d0: 79fb ldrb r3, [r7, #7]
80004d2: 3301 adds r3, #1
80004d4: 71fb strb r3, [r7, #7]
80004d6: 79fb ldrb r3, [r7, #7]
80004d8: 2b07 cmp r3, #7
80004da: d9ef bls.n 80004bc <init_ports_LED+0xc>
}
}
80004dc: bf00 nop
80004de: bf00 nop
80004e0: 370c adds r7, #12
80004e2: 46bd mov sp, r7
80004e4: bc80 pop {r7}
80004e6: 4770 bx lr
80004e8: 40020400 .word 0x40020400
080004ec <allume_LED>:
void allume_LED(uint8_t i){
80004ec: b480 push {r7}
80004ee: b083 sub sp, #12
80004f0: af00 add r7, sp, #0
80004f2: 4603 mov r3, r0
80004f4: 71fb strb r3, [r7, #7]
if (i<=1){
80004f6: 79fb ldrb r3, [r7, #7]
80004f8: 2b01 cmp r3, #1
80004fa: d80a bhi.n 8000512 <allume_LED+0x26>
GPIOB->ODR |= (1<<i);
80004fc: 4b0d ldr r3, [pc, #52] @ (8000534 <allume_LED+0x48>)
80004fe: 695b ldr r3, [r3, #20]
8000500: 79fa ldrb r2, [r7, #7]
8000502: 2101 movs r1, #1
8000504: fa01 f202 lsl.w r2, r1, r2
8000508: 4611 mov r1, r2
800050a: 4a0a ldr r2, [pc, #40] @ (8000534 <allume_LED+0x48>)
800050c: 430b orrs r3, r1
800050e: 6153 str r3, [r2, #20]
} else {
GPIOB->ODR |= (1<<((i-2)+10));
}
}
8000510: e00a b.n 8000528 <allume_LED+0x3c>
GPIOB->ODR |= (1<<((i-2)+10));
8000512: 4b08 ldr r3, [pc, #32] @ (8000534 <allume_LED+0x48>)
8000514: 695b ldr r3, [r3, #20]
8000516: 79fa ldrb r2, [r7, #7]
8000518: 3208 adds r2, #8
800051a: 2101 movs r1, #1
800051c: fa01 f202 lsl.w r2, r1, r2
8000520: 4611 mov r1, r2
8000522: 4a04 ldr r2, [pc, #16] @ (8000534 <allume_LED+0x48>)
8000524: 430b orrs r3, r1
8000526: 6153 str r3, [r2, #20]
}
8000528: bf00 nop
800052a: 370c adds r7, #12
800052c: 46bd mov sp, r7
800052e: bc80 pop {r7}
8000530: 4770 bx lr
8000532: bf00 nop
8000534: 40020400 .word 0x40020400
08000538 <eteint_LED>:
void eteint_LED(uint8_t i){
8000538: b480 push {r7}
800053a: b083 sub sp, #12
800053c: af00 add r7, sp, #0
800053e: 4603 mov r3, r0
8000540: 71fb strb r3, [r7, #7]
if (i<=1){
8000542: 79fb ldrb r3, [r7, #7]
8000544: 2b01 cmp r3, #1
8000546: d80b bhi.n 8000560 <eteint_LED+0x28>
GPIOB->ODR &= ~(1<<i);
8000548: 4b0e ldr r3, [pc, #56] @ (8000584 <eteint_LED+0x4c>)
800054a: 695b ldr r3, [r3, #20]
800054c: 79fa ldrb r2, [r7, #7]
800054e: 2101 movs r1, #1
8000550: fa01 f202 lsl.w r2, r1, r2
8000554: 43d2 mvns r2, r2
8000556: 4611 mov r1, r2
8000558: 4a0a ldr r2, [pc, #40] @ (8000584 <eteint_LED+0x4c>)
800055a: 400b ands r3, r1
800055c: 6153 str r3, [r2, #20]
} else {
GPIOB->ODR &= ~(1<<((i-2)+10));
}
}
800055e: e00b b.n 8000578 <eteint_LED+0x40>
GPIOB->ODR &= ~(1<<((i-2)+10));
8000560: 4b08 ldr r3, [pc, #32] @ (8000584 <eteint_LED+0x4c>)
8000562: 695b ldr r3, [r3, #20]
8000564: 79fa ldrb r2, [r7, #7]
8000566: 3208 adds r2, #8
8000568: 2101 movs r1, #1
800056a: fa01 f202 lsl.w r2, r1, r2
800056e: 43d2 mvns r2, r2
8000570: 4611 mov r1, r2
8000572: 4a04 ldr r2, [pc, #16] @ (8000584 <eteint_LED+0x4c>)
8000574: 400b ands r3, r1
8000576: 6153 str r3, [r2, #20]
}
8000578: bf00 nop
800057a: 370c adds r7, #12
800057c: 46bd mov sp, r7
800057e: bc80 pop {r7}
8000580: 4770 bx lr
8000582: bf00 nop
8000584: 40020400 .word 0x40020400
08000588 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000588: b580 push {r7, lr}
800058a: b082 sub sp, #8
800058c: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800058e: f000 f934 bl 80007fa <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000592: f000 f82d bl 80005f0 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000596: f000 f873 bl 8000680 <MX_GPIO_Init>
/* USER CODE BEGIN 2 */
init_ports_LED();
800059a: f7ff ff89 bl 80004b0 <init_ports_LED>
uint8_t i;
uint16_t delay_allume = 500;
800059e: f44f 73fa mov.w r3, #500 @ 0x1f4
80005a2: 80bb strh r3, [r7, #4]
uint16_t delay_eteint = 500;
80005a4: f44f 73fa mov.w r3, #500 @ 0x1f4
80005a8: 807b strh r3, [r7, #2]
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
for (i=0 ; i<=7 ; i++){
80005aa: 2300 movs r3, #0
80005ac: 71fb strb r3, [r7, #7]
80005ae: e00a b.n 80005c6 <main+0x3e>
allume_LED(i);
80005b0: 79fb ldrb r3, [r7, #7]
80005b2: 4618 mov r0, r3
80005b4: f7ff ff9a bl 80004ec <allume_LED>
HAL_Delay(delay_allume);
80005b8: 88bb ldrh r3, [r7, #4]
80005ba: 4618 mov r0, r3
80005bc: f000 f98c bl 80008d8 <HAL_Delay>
for (i=0 ; i<=7 ; i++){
80005c0: 79fb ldrb r3, [r7, #7]
80005c2: 3301 adds r3, #1
80005c4: 71fb strb r3, [r7, #7]
80005c6: 79fb ldrb r3, [r7, #7]
80005c8: 2b07 cmp r3, #7
80005ca: d9f1 bls.n 80005b0 <main+0x28>
}
for (i=0 ; i<=7 ; i++){
80005cc: 2300 movs r3, #0
80005ce: 71fb strb r3, [r7, #7]
80005d0: e00a b.n 80005e8 <main+0x60>
eteint_LED(i);
80005d2: 79fb ldrb r3, [r7, #7]
80005d4: 4618 mov r0, r3
80005d6: f7ff ffaf bl 8000538 <eteint_LED>
HAL_Delay(delay_eteint);
80005da: 887b ldrh r3, [r7, #2]
80005dc: 4618 mov r0, r3
80005de: f000 f97b bl 80008d8 <HAL_Delay>
for (i=0 ; i<=7 ; i++){
80005e2: 79fb ldrb r3, [r7, #7]
80005e4: 3301 adds r3, #1
80005e6: 71fb strb r3, [r7, #7]
80005e8: 79fb ldrb r3, [r7, #7]
80005ea: 2b07 cmp r3, #7
80005ec: d9f1 bls.n 80005d2 <main+0x4a>
for (i=0 ; i<=7 ; i++){
80005ee: e7dc b.n 80005aa <main+0x22>
080005f0 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80005f0: b580 push {r7, lr}
80005f2: b092 sub sp, #72 @ 0x48
80005f4: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80005f6: f107 0314 add.w r3, r7, #20
80005fa: 2234 movs r2, #52 @ 0x34
80005fc: 2100 movs r1, #0
80005fe: 4618 mov r0, r3
8000600: f001 f99a bl 8001938 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000604: 463b mov r3, r7
8000606: 2200 movs r2, #0
8000608: 601a str r2, [r3, #0]
800060a: 605a str r2, [r3, #4]
800060c: 609a str r2, [r3, #8]
800060e: 60da str r2, [r3, #12]
8000610: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000612: 4b1a ldr r3, [pc, #104] @ (800067c <SystemClock_Config+0x8c>)
8000614: 681b ldr r3, [r3, #0]
8000616: f423 53c0 bic.w r3, r3, #6144 @ 0x1800
800061a: 4a18 ldr r2, [pc, #96] @ (800067c <SystemClock_Config+0x8c>)
800061c: f443 6300 orr.w r3, r3, #2048 @ 0x800
8000620: 6013 str r3, [r2, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
8000622: 2310 movs r3, #16
8000624: 617b str r3, [r7, #20]
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
8000626: 2301 movs r3, #1
8000628: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.MSICalibrationValue = 0;
800062a: 2300 movs r3, #0
800062c: 633b str r3, [r7, #48] @ 0x30
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
800062e: f44f 4320 mov.w r3, #40960 @ 0xa000
8000632: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000634: 2300 movs r3, #0
8000636: 63bb str r3, [r7, #56] @ 0x38
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000638: f107 0314 add.w r3, r7, #20
800063c: 4618 mov r0, r3
800063e: f000 fbf9 bl 8000e34 <HAL_RCC_OscConfig>
8000642: 4603 mov r3, r0
8000644: 2b00 cmp r3, #0
8000646: d001 beq.n 800064c <SystemClock_Config+0x5c>
{
Error_Handler();
8000648: f000 f84c bl 80006e4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800064c: 230f movs r3, #15
800064e: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
8000650: 2300 movs r3, #0
8000652: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000654: 2300 movs r3, #0
8000656: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000658: 2300 movs r3, #0
800065a: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
800065c: 2300 movs r3, #0
800065e: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000660: 463b mov r3, r7
8000662: 2100 movs r1, #0
8000664: 4618 mov r0, r3
8000666: f000 ff15 bl 8001494 <HAL_RCC_ClockConfig>
800066a: 4603 mov r3, r0
800066c: 2b00 cmp r3, #0
800066e: d001 beq.n 8000674 <SystemClock_Config+0x84>
{
Error_Handler();
8000670: f000 f838 bl 80006e4 <Error_Handler>
}
}
8000674: bf00 nop
8000676: 3748 adds r7, #72 @ 0x48
8000678: 46bd mov sp, r7
800067a: bd80 pop {r7, pc}
800067c: 40007000 .word 0x40007000
08000680 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000680: b580 push {r7, lr}
8000682: b086 sub sp, #24
8000684: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000686: 1d3b adds r3, r7, #4
8000688: 2200 movs r2, #0
800068a: 601a str r2, [r3, #0]
800068c: 605a str r2, [r3, #4]
800068e: 609a str r2, [r3, #8]
8000690: 60da str r2, [r3, #12]
8000692: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOB_CLK_ENABLE();
8000694: 4b11 ldr r3, [pc, #68] @ (80006dc <MX_GPIO_Init+0x5c>)
8000696: 69db ldr r3, [r3, #28]
8000698: 4a10 ldr r2, [pc, #64] @ (80006dc <MX_GPIO_Init+0x5c>)
800069a: f043 0302 orr.w r3, r3, #2
800069e: 61d3 str r3, [r2, #28]
80006a0: 4b0e ldr r3, [pc, #56] @ (80006dc <MX_GPIO_Init+0x5c>)
80006a2: 69db ldr r3, [r3, #28]
80006a4: f003 0302 and.w r3, r3, #2
80006a8: 603b str r3, [r7, #0]
80006aa: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11
80006ac: 2200 movs r2, #0
80006ae: f64f 4103 movw r1, #64515 @ 0xfc03
80006b2: 480b ldr r0, [pc, #44] @ (80006e0 <MX_GPIO_Init+0x60>)
80006b4: f000 fba6 bl 8000e04 <HAL_GPIO_WritePin>
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET);
/*Configure GPIO pins : PB0 PB1 PB10 PB11
PB12 PB13 PB14 PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11
80006b8: f64f 4303 movw r3, #64515 @ 0xfc03
80006bc: 607b str r3, [r7, #4]
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80006be: 2301 movs r3, #1
80006c0: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80006c2: 2300 movs r3, #0
80006c4: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80006c6: 2300 movs r3, #0
80006c8: 613b str r3, [r7, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80006ca: 1d3b adds r3, r7, #4
80006cc: 4619 mov r1, r3
80006ce: 4804 ldr r0, [pc, #16] @ (80006e0 <MX_GPIO_Init+0x60>)
80006d0: f000 fa08 bl 8000ae4 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80006d4: bf00 nop
80006d6: 3718 adds r7, #24
80006d8: 46bd mov sp, r7
80006da: bd80 pop {r7, pc}
80006dc: 40023800 .word 0x40023800
80006e0: 40020400 .word 0x40020400
080006e4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80006e4: b480 push {r7}
80006e6: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80006e8: b672 cpsid i
}
80006ea: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80006ec: bf00 nop
80006ee: e7fd b.n 80006ec <Error_Handler+0x8>
080006f0 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80006f0: b480 push {r7}
80006f2: b085 sub sp, #20
80006f4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_COMP_CLK_ENABLE();
80006f6: 4b14 ldr r3, [pc, #80] @ (8000748 <HAL_MspInit+0x58>)
80006f8: 6a5b ldr r3, [r3, #36] @ 0x24
80006fa: 4a13 ldr r2, [pc, #76] @ (8000748 <HAL_MspInit+0x58>)
80006fc: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000700: 6253 str r3, [r2, #36] @ 0x24
8000702: 4b11 ldr r3, [pc, #68] @ (8000748 <HAL_MspInit+0x58>)
8000704: 6a5b ldr r3, [r3, #36] @ 0x24
8000706: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800070a: 60fb str r3, [r7, #12]
800070c: 68fb ldr r3, [r7, #12]
__HAL_RCC_SYSCFG_CLK_ENABLE();
800070e: 4b0e ldr r3, [pc, #56] @ (8000748 <HAL_MspInit+0x58>)
8000710: 6a1b ldr r3, [r3, #32]
8000712: 4a0d ldr r2, [pc, #52] @ (8000748 <HAL_MspInit+0x58>)
8000714: f043 0301 orr.w r3, r3, #1
8000718: 6213 str r3, [r2, #32]
800071a: 4b0b ldr r3, [pc, #44] @ (8000748 <HAL_MspInit+0x58>)
800071c: 6a1b ldr r3, [r3, #32]
800071e: f003 0301 and.w r3, r3, #1
8000722: 60bb str r3, [r7, #8]
8000724: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8000726: 4b08 ldr r3, [pc, #32] @ (8000748 <HAL_MspInit+0x58>)
8000728: 6a5b ldr r3, [r3, #36] @ 0x24
800072a: 4a07 ldr r2, [pc, #28] @ (8000748 <HAL_MspInit+0x58>)
800072c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000730: 6253 str r3, [r2, #36] @ 0x24
8000732: 4b05 ldr r3, [pc, #20] @ (8000748 <HAL_MspInit+0x58>)
8000734: 6a5b ldr r3, [r3, #36] @ 0x24
8000736: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800073a: 607b str r3, [r7, #4]
800073c: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800073e: bf00 nop
8000740: 3714 adds r7, #20
8000742: 46bd mov sp, r7
8000744: bc80 pop {r7}
8000746: 4770 bx lr
8000748: 40023800 .word 0x40023800
0800074c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800074c: b480 push {r7}
800074e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000750: bf00 nop
8000752: e7fd b.n 8000750 <NMI_Handler+0x4>
08000754 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000754: b480 push {r7}
8000756: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000758: bf00 nop
800075a: e7fd b.n 8000758 <HardFault_Handler+0x4>
0800075c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
800075c: b480 push {r7}
800075e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000760: bf00 nop
8000762: e7fd b.n 8000760 <MemManage_Handler+0x4>
08000764 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000764: b480 push {r7}
8000766: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000768: bf00 nop
800076a: e7fd b.n 8000768 <BusFault_Handler+0x4>
0800076c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
800076c: b480 push {r7}
800076e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000770: bf00 nop
8000772: e7fd b.n 8000770 <UsageFault_Handler+0x4>
08000774 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000774: b480 push {r7}
8000776: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000778: bf00 nop
800077a: 46bd mov sp, r7
800077c: bc80 pop {r7}
800077e: 4770 bx lr
08000780 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000780: b480 push {r7}
8000782: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000784: bf00 nop
8000786: 46bd mov sp, r7
8000788: bc80 pop {r7}
800078a: 4770 bx lr
0800078c <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800078c: b480 push {r7}
800078e: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000790: bf00 nop
8000792: 46bd mov sp, r7
8000794: bc80 pop {r7}
8000796: 4770 bx lr
08000798 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000798: b580 push {r7, lr}
800079a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800079c: f000 f880 bl 80008a0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80007a0: bf00 nop
80007a2: bd80 pop {r7, pc}
080007a4 <SystemInit>:
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
80007a4: b480 push {r7}
80007a6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80007a8: bf00 nop
80007aa: 46bd mov sp, r7
80007ac: bc80 pop {r7}
80007ae: 4770 bx lr
080007b0 <Reset_Handler>:
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
80007b0: f7ff fff8 bl 80007a4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80007b4: 480b ldr r0, [pc, #44] @ (80007e4 <LoopFillZerobss+0xe>)
ldr r1, =_edata
80007b6: 490c ldr r1, [pc, #48] @ (80007e8 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
80007b8: 4a0c ldr r2, [pc, #48] @ (80007ec <LoopFillZerobss+0x16>)
movs r3, #0
80007ba: 2300 movs r3, #0
b LoopCopyDataInit
80007bc: e002 b.n 80007c4 <LoopCopyDataInit>
080007be <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80007be: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80007c0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80007c2: 3304 adds r3, #4
080007c4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80007c4: 18c4 adds r4, r0, r3
cmp r4, r1
80007c6: 428c cmp r4, r1
bcc CopyDataInit
80007c8: d3f9 bcc.n 80007be <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80007ca: 4a09 ldr r2, [pc, #36] @ (80007f0 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
80007cc: 4c09 ldr r4, [pc, #36] @ (80007f4 <LoopFillZerobss+0x1e>)
movs r3, #0
80007ce: 2300 movs r3, #0
b LoopFillZerobss
80007d0: e001 b.n 80007d6 <LoopFillZerobss>
080007d2 <FillZerobss>:
FillZerobss:
str r3, [r2]
80007d2: 6013 str r3, [r2, #0]
adds r2, r2, #4
80007d4: 3204 adds r2, #4
080007d6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80007d6: 42a2 cmp r2, r4
bcc FillZerobss
80007d8: d3fb bcc.n 80007d2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80007da: f001 f8b5 bl 8001948 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80007de: f7ff fed3 bl 8000588 <main>
bx lr
80007e2: 4770 bx lr
ldr r0, =_sdata
80007e4: 20000000 .word 0x20000000
ldr r1, =_edata
80007e8: 2000000c .word 0x2000000c
ldr r2, =_sidata
80007ec: 080019d4 .word 0x080019d4
ldr r2, =_sbss
80007f0: 2000000c .word 0x2000000c
ldr r4, =_ebss
80007f4: 2000002c .word 0x2000002c
080007f8 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80007f8: e7fe b.n 80007f8 <ADC1_IRQHandler>
080007fa <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80007fa: b580 push {r7, lr}
80007fc: b082 sub sp, #8
80007fe: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8000800: 2300 movs r3, #0
8000802: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000804: 2003 movs r0, #3
8000806: f000 f939 bl 8000a7c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
800080a: 200f movs r0, #15
800080c: f000 f80e bl 800082c <HAL_InitTick>
8000810: 4603 mov r3, r0
8000812: 2b00 cmp r3, #0
8000814: d002 beq.n 800081c <HAL_Init+0x22>
{
status = HAL_ERROR;
8000816: 2301 movs r3, #1
8000818: 71fb strb r3, [r7, #7]
800081a: e001 b.n 8000820 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
800081c: f7ff ff68 bl 80006f0 <HAL_MspInit>
}
/* Return function status */
return status;
8000820: 79fb ldrb r3, [r7, #7]
}
8000822: 4618 mov r0, r3
8000824: 3708 adds r7, #8
8000826: 46bd mov sp, r7
8000828: bd80 pop {r7, pc}
...
0800082c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
800082c: b580 push {r7, lr}
800082e: b084 sub sp, #16
8000830: af00 add r7, sp, #0
8000832: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000834: 2300 movs r3, #0
8000836: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8000838: 4b16 ldr r3, [pc, #88] @ (8000894 <HAL_InitTick+0x68>)
800083a: 681b ldr r3, [r3, #0]
800083c: 2b00 cmp r3, #0
800083e: d022 beq.n 8000886 <HAL_InitTick+0x5a>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8000840: 4b15 ldr r3, [pc, #84] @ (8000898 <HAL_InitTick+0x6c>)
8000842: 681a ldr r2, [r3, #0]
8000844: 4b13 ldr r3, [pc, #76] @ (8000894 <HAL_InitTick+0x68>)
8000846: 681b ldr r3, [r3, #0]
8000848: f44f 717a mov.w r1, #1000 @ 0x3e8
800084c: fbb1 f3f3 udiv r3, r1, r3
8000850: fbb2 f3f3 udiv r3, r2, r3
8000854: 4618 mov r0, r3
8000856: f000 f938 bl 8000aca <HAL_SYSTICK_Config>
800085a: 4603 mov r3, r0
800085c: 2b00 cmp r3, #0
800085e: d10f bne.n 8000880 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000860: 687b ldr r3, [r7, #4]
8000862: 2b0f cmp r3, #15
8000864: d809 bhi.n 800087a <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000866: 2200 movs r2, #0
8000868: 6879 ldr r1, [r7, #4]
800086a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
800086e: f000 f910 bl 8000a92 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000872: 4a0a ldr r2, [pc, #40] @ (800089c <HAL_InitTick+0x70>)
8000874: 687b ldr r3, [r7, #4]
8000876: 6013 str r3, [r2, #0]
8000878: e007 b.n 800088a <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
800087a: 2301 movs r3, #1
800087c: 73fb strb r3, [r7, #15]
800087e: e004 b.n 800088a <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8000880: 2301 movs r3, #1
8000882: 73fb strb r3, [r7, #15]
8000884: e001 b.n 800088a <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8000886: 2301 movs r3, #1
8000888: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
800088a: 7bfb ldrb r3, [r7, #15]
}
800088c: 4618 mov r0, r3
800088e: 3710 adds r7, #16
8000890: 46bd mov sp, r7
8000892: bd80 pop {r7, pc}
8000894: 20000008 .word 0x20000008
8000898: 20000000 .word 0x20000000
800089c: 20000004 .word 0x20000004
080008a0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80008a0: b480 push {r7}
80008a2: af00 add r7, sp, #0
uwTick += uwTickFreq;
80008a4: 4b05 ldr r3, [pc, #20] @ (80008bc <HAL_IncTick+0x1c>)
80008a6: 681a ldr r2, [r3, #0]
80008a8: 4b05 ldr r3, [pc, #20] @ (80008c0 <HAL_IncTick+0x20>)
80008aa: 681b ldr r3, [r3, #0]
80008ac: 4413 add r3, r2
80008ae: 4a03 ldr r2, [pc, #12] @ (80008bc <HAL_IncTick+0x1c>)
80008b0: 6013 str r3, [r2, #0]
}
80008b2: bf00 nop
80008b4: 46bd mov sp, r7
80008b6: bc80 pop {r7}
80008b8: 4770 bx lr
80008ba: bf00 nop
80008bc: 20000028 .word 0x20000028
80008c0: 20000008 .word 0x20000008
080008c4 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80008c4: b480 push {r7}
80008c6: af00 add r7, sp, #0
return uwTick;
80008c8: 4b02 ldr r3, [pc, #8] @ (80008d4 <HAL_GetTick+0x10>)
80008ca: 681b ldr r3, [r3, #0]
}
80008cc: 4618 mov r0, r3
80008ce: 46bd mov sp, r7
80008d0: bc80 pop {r7}
80008d2: 4770 bx lr
80008d4: 20000028 .word 0x20000028
080008d8 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80008d8: b580 push {r7, lr}
80008da: b084 sub sp, #16
80008dc: af00 add r7, sp, #0
80008de: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80008e0: f7ff fff0 bl 80008c4 <HAL_GetTick>
80008e4: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80008e6: 687b ldr r3, [r7, #4]
80008e8: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
80008ea: 68fb ldr r3, [r7, #12]
80008ec: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80008f0: d004 beq.n 80008fc <HAL_Delay+0x24>
{
wait += (uint32_t)(uwTickFreq);
80008f2: 4b09 ldr r3, [pc, #36] @ (8000918 <HAL_Delay+0x40>)
80008f4: 681b ldr r3, [r3, #0]
80008f6: 68fa ldr r2, [r7, #12]
80008f8: 4413 add r3, r2
80008fa: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
80008fc: bf00 nop
80008fe: f7ff ffe1 bl 80008c4 <HAL_GetTick>
8000902: 4602 mov r2, r0
8000904: 68bb ldr r3, [r7, #8]
8000906: 1ad3 subs r3, r2, r3
8000908: 68fa ldr r2, [r7, #12]
800090a: 429a cmp r2, r3
800090c: d8f7 bhi.n 80008fe <HAL_Delay+0x26>
{
}
}
800090e: bf00 nop
8000910: bf00 nop
8000912: 3710 adds r7, #16
8000914: 46bd mov sp, r7
8000916: bd80 pop {r7, pc}
8000918: 20000008 .word 0x20000008
0800091c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800091c: b480 push {r7}
800091e: b085 sub sp, #20
8000920: af00 add r7, sp, #0
8000922: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000924: 687b ldr r3, [r7, #4]
8000926: f003 0307 and.w r3, r3, #7
800092a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
800092c: 4b0c ldr r3, [pc, #48] @ (8000960 <__NVIC_SetPriorityGrouping+0x44>)
800092e: 68db ldr r3, [r3, #12]
8000930: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000932: 68ba ldr r2, [r7, #8]
8000934: f64f 03ff movw r3, #63743 @ 0xf8ff
8000938: 4013 ands r3, r2
800093a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800093c: 68fb ldr r3, [r7, #12]
800093e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000940: 68bb ldr r3, [r7, #8]
8000942: 4313 orrs r3, r2
reg_value = (reg_value |
8000944: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8000948: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800094c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800094e: 4a04 ldr r2, [pc, #16] @ (8000960 <__NVIC_SetPriorityGrouping+0x44>)
8000950: 68bb ldr r3, [r7, #8]
8000952: 60d3 str r3, [r2, #12]
}
8000954: bf00 nop
8000956: 3714 adds r7, #20
8000958: 46bd mov sp, r7
800095a: bc80 pop {r7}
800095c: 4770 bx lr
800095e: bf00 nop
8000960: e000ed00 .word 0xe000ed00
08000964 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000964: b480 push {r7}
8000966: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000968: 4b04 ldr r3, [pc, #16] @ (800097c <__NVIC_GetPriorityGrouping+0x18>)
800096a: 68db ldr r3, [r3, #12]
800096c: 0a1b lsrs r3, r3, #8
800096e: f003 0307 and.w r3, r3, #7
}
8000972: 4618 mov r0, r3
8000974: 46bd mov sp, r7
8000976: bc80 pop {r7}
8000978: 4770 bx lr
800097a: bf00 nop
800097c: e000ed00 .word 0xe000ed00
08000980 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000980: b480 push {r7}
8000982: b083 sub sp, #12
8000984: af00 add r7, sp, #0
8000986: 4603 mov r3, r0
8000988: 6039 str r1, [r7, #0]
800098a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800098c: f997 3007 ldrsb.w r3, [r7, #7]
8000990: 2b00 cmp r3, #0
8000992: db0a blt.n 80009aa <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000994: 683b ldr r3, [r7, #0]
8000996: b2da uxtb r2, r3
8000998: 490c ldr r1, [pc, #48] @ (80009cc <__NVIC_SetPriority+0x4c>)
800099a: f997 3007 ldrsb.w r3, [r7, #7]
800099e: 0112 lsls r2, r2, #4
80009a0: b2d2 uxtb r2, r2
80009a2: 440b add r3, r1
80009a4: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80009a8: e00a b.n 80009c0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80009aa: 683b ldr r3, [r7, #0]
80009ac: b2da uxtb r2, r3
80009ae: 4908 ldr r1, [pc, #32] @ (80009d0 <__NVIC_SetPriority+0x50>)
80009b0: 79fb ldrb r3, [r7, #7]
80009b2: f003 030f and.w r3, r3, #15
80009b6: 3b04 subs r3, #4
80009b8: 0112 lsls r2, r2, #4
80009ba: b2d2 uxtb r2, r2
80009bc: 440b add r3, r1
80009be: 761a strb r2, [r3, #24]
}
80009c0: bf00 nop
80009c2: 370c adds r7, #12
80009c4: 46bd mov sp, r7
80009c6: bc80 pop {r7}
80009c8: 4770 bx lr
80009ca: bf00 nop
80009cc: e000e100 .word 0xe000e100
80009d0: e000ed00 .word 0xe000ed00
080009d4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80009d4: b480 push {r7}
80009d6: b089 sub sp, #36 @ 0x24
80009d8: af00 add r7, sp, #0
80009da: 60f8 str r0, [r7, #12]
80009dc: 60b9 str r1, [r7, #8]
80009de: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80009e0: 68fb ldr r3, [r7, #12]
80009e2: f003 0307 and.w r3, r3, #7
80009e6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80009e8: 69fb ldr r3, [r7, #28]
80009ea: f1c3 0307 rsb r3, r3, #7
80009ee: 2b04 cmp r3, #4
80009f0: bf28 it cs
80009f2: 2304 movcs r3, #4
80009f4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80009f6: 69fb ldr r3, [r7, #28]
80009f8: 3304 adds r3, #4
80009fa: 2b06 cmp r3, #6
80009fc: d902 bls.n 8000a04 <NVIC_EncodePriority+0x30>
80009fe: 69fb ldr r3, [r7, #28]
8000a00: 3b03 subs r3, #3
8000a02: e000 b.n 8000a06 <NVIC_EncodePriority+0x32>
8000a04: 2300 movs r3, #0
8000a06: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000a08: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8000a0c: 69bb ldr r3, [r7, #24]
8000a0e: fa02 f303 lsl.w r3, r2, r3
8000a12: 43da mvns r2, r3
8000a14: 68bb ldr r3, [r7, #8]
8000a16: 401a ands r2, r3
8000a18: 697b ldr r3, [r7, #20]
8000a1a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000a1c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8000a20: 697b ldr r3, [r7, #20]
8000a22: fa01 f303 lsl.w r3, r1, r3
8000a26: 43d9 mvns r1, r3
8000a28: 687b ldr r3, [r7, #4]
8000a2a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000a2c: 4313 orrs r3, r2
);
}
8000a2e: 4618 mov r0, r3
8000a30: 3724 adds r7, #36 @ 0x24
8000a32: 46bd mov sp, r7
8000a34: bc80 pop {r7}
8000a36: 4770 bx lr
08000a38 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000a38: b580 push {r7, lr}
8000a3a: b082 sub sp, #8
8000a3c: af00 add r7, sp, #0
8000a3e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000a40: 687b ldr r3, [r7, #4]
8000a42: 3b01 subs r3, #1
8000a44: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8000a48: d301 bcc.n 8000a4e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000a4a: 2301 movs r3, #1
8000a4c: e00f b.n 8000a6e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000a4e: 4a0a ldr r2, [pc, #40] @ (8000a78 <SysTick_Config+0x40>)
8000a50: 687b ldr r3, [r7, #4]
8000a52: 3b01 subs r3, #1
8000a54: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000a56: 210f movs r1, #15
8000a58: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000a5c: f7ff ff90 bl 8000980 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000a60: 4b05 ldr r3, [pc, #20] @ (8000a78 <SysTick_Config+0x40>)
8000a62: 2200 movs r2, #0
8000a64: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000a66: 4b04 ldr r3, [pc, #16] @ (8000a78 <SysTick_Config+0x40>)
8000a68: 2207 movs r2, #7
8000a6a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000a6c: 2300 movs r3, #0
}
8000a6e: 4618 mov r0, r3
8000a70: 3708 adds r7, #8
8000a72: 46bd mov sp, r7
8000a74: bd80 pop {r7, pc}
8000a76: bf00 nop
8000a78: e000e010 .word 0xe000e010
08000a7c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000a7c: b580 push {r7, lr}
8000a7e: b082 sub sp, #8
8000a80: af00 add r7, sp, #0
8000a82: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000a84: 6878 ldr r0, [r7, #4]
8000a86: f7ff ff49 bl 800091c <__NVIC_SetPriorityGrouping>
}
8000a8a: bf00 nop
8000a8c: 3708 adds r7, #8
8000a8e: 46bd mov sp, r7
8000a90: bd80 pop {r7, pc}
08000a92 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000a92: b580 push {r7, lr}
8000a94: b086 sub sp, #24
8000a96: af00 add r7, sp, #0
8000a98: 4603 mov r3, r0
8000a9a: 60b9 str r1, [r7, #8]
8000a9c: 607a str r2, [r7, #4]
8000a9e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8000aa0: 2300 movs r3, #0
8000aa2: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000aa4: f7ff ff5e bl 8000964 <__NVIC_GetPriorityGrouping>
8000aa8: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000aaa: 687a ldr r2, [r7, #4]
8000aac: 68b9 ldr r1, [r7, #8]
8000aae: 6978 ldr r0, [r7, #20]
8000ab0: f7ff ff90 bl 80009d4 <NVIC_EncodePriority>
8000ab4: 4602 mov r2, r0
8000ab6: f997 300f ldrsb.w r3, [r7, #15]
8000aba: 4611 mov r1, r2
8000abc: 4618 mov r0, r3
8000abe: f7ff ff5f bl 8000980 <__NVIC_SetPriority>
}
8000ac2: bf00 nop
8000ac4: 3718 adds r7, #24
8000ac6: 46bd mov sp, r7
8000ac8: bd80 pop {r7, pc}
08000aca <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000aca: b580 push {r7, lr}
8000acc: b082 sub sp, #8
8000ace: af00 add r7, sp, #0
8000ad0: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000ad2: 6878 ldr r0, [r7, #4]
8000ad4: f7ff ffb0 bl 8000a38 <SysTick_Config>
8000ad8: 4603 mov r3, r0
}
8000ada: 4618 mov r0, r3
8000adc: 3708 adds r7, #8
8000ade: 46bd mov sp, r7
8000ae0: bd80 pop {r7, pc}
...
08000ae4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000ae4: b480 push {r7}
8000ae6: b087 sub sp, #28
8000ae8: af00 add r7, sp, #0
8000aea: 6078 str r0, [r7, #4]
8000aec: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
8000aee: 2300 movs r3, #0
8000af0: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
8000af2: 2300 movs r3, #0
8000af4: 60fb str r3, [r7, #12]
uint32_t temp = 0x00;
8000af6: 2300 movs r3, #0
8000af8: 613b str r3, [r7, #16]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0)
8000afa: e160 b.n 8000dbe <HAL_GPIO_Init+0x2da>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
8000afc: 683b ldr r3, [r7, #0]
8000afe: 681a ldr r2, [r3, #0]
8000b00: 2101 movs r1, #1
8000b02: 697b ldr r3, [r7, #20]
8000b04: fa01 f303 lsl.w r3, r1, r3
8000b08: 4013 ands r3, r2
8000b0a: 60fb str r3, [r7, #12]
if (iocurrent)
8000b0c: 68fb ldr r3, [r7, #12]
8000b0e: 2b00 cmp r3, #0
8000b10: f000 8152 beq.w 8000db8 <HAL_GPIO_Init+0x2d4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000b14: 683b ldr r3, [r7, #0]
8000b16: 685b ldr r3, [r3, #4]
8000b18: f003 0303 and.w r3, r3, #3
8000b1c: 2b01 cmp r3, #1
8000b1e: d005 beq.n 8000b2c <HAL_GPIO_Init+0x48>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8000b20: 683b ldr r3, [r7, #0]
8000b22: 685b ldr r3, [r3, #4]
8000b24: f003 0303 and.w r3, r3, #3
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000b28: 2b02 cmp r3, #2
8000b2a: d130 bne.n 8000b8e <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000b2c: 687b ldr r3, [r7, #4]
8000b2e: 689b ldr r3, [r3, #8]
8000b30: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8000b32: 697b ldr r3, [r7, #20]
8000b34: 005b lsls r3, r3, #1
8000b36: 2203 movs r2, #3
8000b38: fa02 f303 lsl.w r3, r2, r3
8000b3c: 43db mvns r3, r3
8000b3e: 693a ldr r2, [r7, #16]
8000b40: 4013 ands r3, r2
8000b42: 613b str r3, [r7, #16]
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
8000b44: 683b ldr r3, [r7, #0]
8000b46: 68da ldr r2, [r3, #12]
8000b48: 697b ldr r3, [r7, #20]
8000b4a: 005b lsls r3, r3, #1
8000b4c: fa02 f303 lsl.w r3, r2, r3
8000b50: 693a ldr r2, [r7, #16]
8000b52: 4313 orrs r3, r2
8000b54: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000b56: 687b ldr r3, [r7, #4]
8000b58: 693a ldr r2, [r7, #16]
8000b5a: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000b5c: 687b ldr r3, [r7, #4]
8000b5e: 685b ldr r3, [r3, #4]
8000b60: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
8000b62: 2201 movs r2, #1
8000b64: 697b ldr r3, [r7, #20]
8000b66: fa02 f303 lsl.w r3, r2, r3
8000b6a: 43db mvns r3, r3
8000b6c: 693a ldr r2, [r7, #16]
8000b6e: 4013 ands r3, r2
8000b70: 613b str r3, [r7, #16]
SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000b72: 683b ldr r3, [r7, #0]
8000b74: 685b ldr r3, [r3, #4]
8000b76: 091b lsrs r3, r3, #4
8000b78: f003 0201 and.w r2, r3, #1
8000b7c: 697b ldr r3, [r7, #20]
8000b7e: fa02 f303 lsl.w r3, r2, r3
8000b82: 693a ldr r2, [r7, #16]
8000b84: 4313 orrs r3, r2
8000b86: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000b88: 687b ldr r3, [r7, #4]
8000b8a: 693a ldr r2, [r7, #16]
8000b8c: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000b8e: 683b ldr r3, [r7, #0]
8000b90: 685b ldr r3, [r3, #4]
8000b92: f003 0303 and.w r3, r3, #3
8000b96: 2b03 cmp r3, #3
8000b98: d017 beq.n 8000bca <HAL_GPIO_Init+0xe6>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000b9a: 687b ldr r3, [r7, #4]
8000b9c: 68db ldr r3, [r3, #12]
8000b9e: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
8000ba0: 697b ldr r3, [r7, #20]
8000ba2: 005b lsls r3, r3, #1
8000ba4: 2203 movs r2, #3
8000ba6: fa02 f303 lsl.w r3, r2, r3
8000baa: 43db mvns r3, r3
8000bac: 693a ldr r2, [r7, #16]
8000bae: 4013 ands r3, r2
8000bb0: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
8000bb2: 683b ldr r3, [r7, #0]
8000bb4: 689a ldr r2, [r3, #8]
8000bb6: 697b ldr r3, [r7, #20]
8000bb8: 005b lsls r3, r3, #1
8000bba: fa02 f303 lsl.w r3, r2, r3
8000bbe: 693a ldr r2, [r7, #16]
8000bc0: 4313 orrs r3, r2
8000bc2: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000bc4: 687b ldr r3, [r7, #4]
8000bc6: 693a ldr r2, [r7, #16]
8000bc8: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000bca: 683b ldr r3, [r7, #0]
8000bcc: 685b ldr r3, [r3, #4]
8000bce: f003 0303 and.w r3, r3, #3
8000bd2: 2b02 cmp r3, #2
8000bd4: d123 bne.n 8000c1e <HAL_GPIO_Init+0x13a>
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
/* Identify AFRL or AFRH register based on IO position*/
temp = GPIOx->AFR[position >> 3];
8000bd6: 697b ldr r3, [r7, #20]
8000bd8: 08da lsrs r2, r3, #3
8000bda: 687b ldr r3, [r7, #4]
8000bdc: 3208 adds r2, #8
8000bde: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000be2: 613b str r3, [r7, #16]
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
8000be4: 697b ldr r3, [r7, #20]
8000be6: f003 0307 and.w r3, r3, #7
8000bea: 009b lsls r3, r3, #2
8000bec: 220f movs r2, #15
8000bee: fa02 f303 lsl.w r3, r2, r3
8000bf2: 43db mvns r3, r3
8000bf4: 693a ldr r2, [r7, #16]
8000bf6: 4013 ands r3, r2
8000bf8: 613b str r3, [r7, #16]
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
8000bfa: 683b ldr r3, [r7, #0]
8000bfc: 691a ldr r2, [r3, #16]
8000bfe: 697b ldr r3, [r7, #20]
8000c00: f003 0307 and.w r3, r3, #7
8000c04: 009b lsls r3, r3, #2
8000c06: fa02 f303 lsl.w r3, r2, r3
8000c0a: 693a ldr r2, [r7, #16]
8000c0c: 4313 orrs r3, r2
8000c0e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3] = temp;
8000c10: 697b ldr r3, [r7, #20]
8000c12: 08da lsrs r2, r3, #3
8000c14: 687b ldr r3, [r7, #4]
8000c16: 3208 adds r2, #8
8000c18: 6939 ldr r1, [r7, #16]
8000c1a: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000c1e: 687b ldr r3, [r7, #4]
8000c20: 681b ldr r3, [r3, #0]
8000c22: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
8000c24: 697b ldr r3, [r7, #20]
8000c26: 005b lsls r3, r3, #1
8000c28: 2203 movs r2, #3
8000c2a: fa02 f303 lsl.w r3, r2, r3
8000c2e: 43db mvns r3, r3
8000c30: 693a ldr r2, [r7, #16]
8000c32: 4013 ands r3, r2
8000c34: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8000c36: 683b ldr r3, [r7, #0]
8000c38: 685b ldr r3, [r3, #4]
8000c3a: f003 0203 and.w r2, r3, #3
8000c3e: 697b ldr r3, [r7, #20]
8000c40: 005b lsls r3, r3, #1
8000c42: fa02 f303 lsl.w r3, r2, r3
8000c46: 693a ldr r2, [r7, #16]
8000c48: 4313 orrs r3, r2
8000c4a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000c4c: 687b ldr r3, [r7, #4]
8000c4e: 693a ldr r2, [r7, #16]
8000c50: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8000c52: 683b ldr r3, [r7, #0]
8000c54: 685b ldr r3, [r3, #4]
8000c56: f403 3340 and.w r3, r3, #196608 @ 0x30000
8000c5a: 2b00 cmp r3, #0
8000c5c: f000 80ac beq.w 8000db8 <HAL_GPIO_Init+0x2d4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000c60: 4b5e ldr r3, [pc, #376] @ (8000ddc <HAL_GPIO_Init+0x2f8>)
8000c62: 6a1b ldr r3, [r3, #32]
8000c64: 4a5d ldr r2, [pc, #372] @ (8000ddc <HAL_GPIO_Init+0x2f8>)
8000c66: f043 0301 orr.w r3, r3, #1
8000c6a: 6213 str r3, [r2, #32]
8000c6c: 4b5b ldr r3, [pc, #364] @ (8000ddc <HAL_GPIO_Init+0x2f8>)
8000c6e: 6a1b ldr r3, [r3, #32]
8000c70: f003 0301 and.w r3, r3, #1
8000c74: 60bb str r3, [r7, #8]
8000c76: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2];
8000c78: 4a59 ldr r2, [pc, #356] @ (8000de0 <HAL_GPIO_Init+0x2fc>)
8000c7a: 697b ldr r3, [r7, #20]
8000c7c: 089b lsrs r3, r3, #2
8000c7e: 3302 adds r3, #2
8000c80: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000c84: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
8000c86: 697b ldr r3, [r7, #20]
8000c88: f003 0303 and.w r3, r3, #3
8000c8c: 009b lsls r3, r3, #2
8000c8e: 220f movs r2, #15
8000c90: fa02 f303 lsl.w r3, r2, r3
8000c94: 43db mvns r3, r3
8000c96: 693a ldr r2, [r7, #16]
8000c98: 4013 ands r3, r2
8000c9a: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8000c9c: 687b ldr r3, [r7, #4]
8000c9e: 4a51 ldr r2, [pc, #324] @ (8000de4 <HAL_GPIO_Init+0x300>)
8000ca0: 4293 cmp r3, r2
8000ca2: d025 beq.n 8000cf0 <HAL_GPIO_Init+0x20c>
8000ca4: 687b ldr r3, [r7, #4]
8000ca6: 4a50 ldr r2, [pc, #320] @ (8000de8 <HAL_GPIO_Init+0x304>)
8000ca8: 4293 cmp r3, r2
8000caa: d01f beq.n 8000cec <HAL_GPIO_Init+0x208>
8000cac: 687b ldr r3, [r7, #4]
8000cae: 4a4f ldr r2, [pc, #316] @ (8000dec <HAL_GPIO_Init+0x308>)
8000cb0: 4293 cmp r3, r2
8000cb2: d019 beq.n 8000ce8 <HAL_GPIO_Init+0x204>
8000cb4: 687b ldr r3, [r7, #4]
8000cb6: 4a4e ldr r2, [pc, #312] @ (8000df0 <HAL_GPIO_Init+0x30c>)
8000cb8: 4293 cmp r3, r2
8000cba: d013 beq.n 8000ce4 <HAL_GPIO_Init+0x200>
8000cbc: 687b ldr r3, [r7, #4]
8000cbe: 4a4d ldr r2, [pc, #308] @ (8000df4 <HAL_GPIO_Init+0x310>)
8000cc0: 4293 cmp r3, r2
8000cc2: d00d beq.n 8000ce0 <HAL_GPIO_Init+0x1fc>
8000cc4: 687b ldr r3, [r7, #4]
8000cc6: 4a4c ldr r2, [pc, #304] @ (8000df8 <HAL_GPIO_Init+0x314>)
8000cc8: 4293 cmp r3, r2
8000cca: d007 beq.n 8000cdc <HAL_GPIO_Init+0x1f8>
8000ccc: 687b ldr r3, [r7, #4]
8000cce: 4a4b ldr r2, [pc, #300] @ (8000dfc <HAL_GPIO_Init+0x318>)
8000cd0: 4293 cmp r3, r2
8000cd2: d101 bne.n 8000cd8 <HAL_GPIO_Init+0x1f4>
8000cd4: 2306 movs r3, #6
8000cd6: e00c b.n 8000cf2 <HAL_GPIO_Init+0x20e>
8000cd8: 2307 movs r3, #7
8000cda: e00a b.n 8000cf2 <HAL_GPIO_Init+0x20e>
8000cdc: 2305 movs r3, #5
8000cde: e008 b.n 8000cf2 <HAL_GPIO_Init+0x20e>
8000ce0: 2304 movs r3, #4
8000ce2: e006 b.n 8000cf2 <HAL_GPIO_Init+0x20e>
8000ce4: 2303 movs r3, #3
8000ce6: e004 b.n 8000cf2 <HAL_GPIO_Init+0x20e>
8000ce8: 2302 movs r3, #2
8000cea: e002 b.n 8000cf2 <HAL_GPIO_Init+0x20e>
8000cec: 2301 movs r3, #1
8000cee: e000 b.n 8000cf2 <HAL_GPIO_Init+0x20e>
8000cf0: 2300 movs r3, #0
8000cf2: 697a ldr r2, [r7, #20]
8000cf4: f002 0203 and.w r2, r2, #3
8000cf8: 0092 lsls r2, r2, #2
8000cfa: 4093 lsls r3, r2
8000cfc: 693a ldr r2, [r7, #16]
8000cfe: 4313 orrs r3, r2
8000d00: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2] = temp;
8000d02: 4937 ldr r1, [pc, #220] @ (8000de0 <HAL_GPIO_Init+0x2fc>)
8000d04: 697b ldr r3, [r7, #20]
8000d06: 089b lsrs r3, r3, #2
8000d08: 3302 adds r3, #2
8000d0a: 693a ldr r2, [r7, #16]
8000d0c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8000d10: 4b3b ldr r3, [pc, #236] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000d12: 689b ldr r3, [r3, #8]
8000d14: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000d16: 68fb ldr r3, [r7, #12]
8000d18: 43db mvns r3, r3
8000d1a: 693a ldr r2, [r7, #16]
8000d1c: 4013 ands r3, r2
8000d1e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8000d20: 683b ldr r3, [r7, #0]
8000d22: 685b ldr r3, [r3, #4]
8000d24: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8000d28: 2b00 cmp r3, #0
8000d2a: d003 beq.n 8000d34 <HAL_GPIO_Init+0x250>
{
SET_BIT(temp, iocurrent);
8000d2c: 693a ldr r2, [r7, #16]
8000d2e: 68fb ldr r3, [r7, #12]
8000d30: 4313 orrs r3, r2
8000d32: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8000d34: 4a32 ldr r2, [pc, #200] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000d36: 693b ldr r3, [r7, #16]
8000d38: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8000d3a: 4b31 ldr r3, [pc, #196] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000d3c: 68db ldr r3, [r3, #12]
8000d3e: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000d40: 68fb ldr r3, [r7, #12]
8000d42: 43db mvns r3, r3
8000d44: 693a ldr r2, [r7, #16]
8000d46: 4013 ands r3, r2
8000d48: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8000d4a: 683b ldr r3, [r7, #0]
8000d4c: 685b ldr r3, [r3, #4]
8000d4e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8000d52: 2b00 cmp r3, #0
8000d54: d003 beq.n 8000d5e <HAL_GPIO_Init+0x27a>
{
SET_BIT(temp, iocurrent);
8000d56: 693a ldr r2, [r7, #16]
8000d58: 68fb ldr r3, [r7, #12]
8000d5a: 4313 orrs r3, r2
8000d5c: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8000d5e: 4a28 ldr r2, [pc, #160] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000d60: 693b ldr r3, [r7, #16]
8000d62: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8000d64: 4b26 ldr r3, [pc, #152] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000d66: 685b ldr r3, [r3, #4]
8000d68: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000d6a: 68fb ldr r3, [r7, #12]
8000d6c: 43db mvns r3, r3
8000d6e: 693a ldr r2, [r7, #16]
8000d70: 4013 ands r3, r2
8000d72: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8000d74: 683b ldr r3, [r7, #0]
8000d76: 685b ldr r3, [r3, #4]
8000d78: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000d7c: 2b00 cmp r3, #0
8000d7e: d003 beq.n 8000d88 <HAL_GPIO_Init+0x2a4>
{
SET_BIT(temp, iocurrent);
8000d80: 693a ldr r2, [r7, #16]
8000d82: 68fb ldr r3, [r7, #12]
8000d84: 4313 orrs r3, r2
8000d86: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8000d88: 4a1d ldr r2, [pc, #116] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000d8a: 693b ldr r3, [r7, #16]
8000d8c: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8000d8e: 4b1c ldr r3, [pc, #112] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000d90: 681b ldr r3, [r3, #0]
8000d92: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000d94: 68fb ldr r3, [r7, #12]
8000d96: 43db mvns r3, r3
8000d98: 693a ldr r2, [r7, #16]
8000d9a: 4013 ands r3, r2
8000d9c: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8000d9e: 683b ldr r3, [r7, #0]
8000da0: 685b ldr r3, [r3, #4]
8000da2: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000da6: 2b00 cmp r3, #0
8000da8: d003 beq.n 8000db2 <HAL_GPIO_Init+0x2ce>
{
SET_BIT(temp, iocurrent);
8000daa: 693a ldr r2, [r7, #16]
8000dac: 68fb ldr r3, [r7, #12]
8000dae: 4313 orrs r3, r2
8000db0: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8000db2: 4a13 ldr r2, [pc, #76] @ (8000e00 <HAL_GPIO_Init+0x31c>)
8000db4: 693b ldr r3, [r7, #16]
8000db6: 6013 str r3, [r2, #0]
}
}
position++;
8000db8: 697b ldr r3, [r7, #20]
8000dba: 3301 adds r3, #1
8000dbc: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0)
8000dbe: 683b ldr r3, [r7, #0]
8000dc0: 681a ldr r2, [r3, #0]
8000dc2: 697b ldr r3, [r7, #20]
8000dc4: fa22 f303 lsr.w r3, r2, r3
8000dc8: 2b00 cmp r3, #0
8000dca: f47f ae97 bne.w 8000afc <HAL_GPIO_Init+0x18>
}
}
8000dce: bf00 nop
8000dd0: bf00 nop
8000dd2: 371c adds r7, #28
8000dd4: 46bd mov sp, r7
8000dd6: bc80 pop {r7}
8000dd8: 4770 bx lr
8000dda: bf00 nop
8000ddc: 40023800 .word 0x40023800
8000de0: 40010000 .word 0x40010000
8000de4: 40020000 .word 0x40020000
8000de8: 40020400 .word 0x40020400
8000dec: 40020800 .word 0x40020800
8000df0: 40020c00 .word 0x40020c00
8000df4: 40021000 .word 0x40021000
8000df8: 40021400 .word 0x40021400
8000dfc: 40021800 .word 0x40021800
8000e00: 40010400 .word 0x40010400
08000e04 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000e04: b480 push {r7}
8000e06: b083 sub sp, #12
8000e08: af00 add r7, sp, #0
8000e0a: 6078 str r0, [r7, #4]
8000e0c: 460b mov r3, r1
8000e0e: 807b strh r3, [r7, #2]
8000e10: 4613 mov r3, r2
8000e12: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8000e14: 787b ldrb r3, [r7, #1]
8000e16: 2b00 cmp r3, #0
8000e18: d003 beq.n 8000e22 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8000e1a: 887a ldrh r2, [r7, #2]
8000e1c: 687b ldr r3, [r7, #4]
8000e1e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
}
}
8000e20: e003 b.n 8000e2a <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
8000e22: 887b ldrh r3, [r7, #2]
8000e24: 041a lsls r2, r3, #16
8000e26: 687b ldr r3, [r7, #4]
8000e28: 619a str r2, [r3, #24]
}
8000e2a: bf00 nop
8000e2c: 370c adds r7, #12
8000e2e: 46bd mov sp, r7
8000e30: bc80 pop {r7}
8000e32: 4770 bx lr
08000e34 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000e34: b580 push {r7, lr}
8000e36: b088 sub sp, #32
8000e38: af00 add r7, sp, #0
8000e3a: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check the parameters */
if(RCC_OscInitStruct == NULL)
8000e3c: 687b ldr r3, [r7, #4]
8000e3e: 2b00 cmp r3, #0
8000e40: d101 bne.n 8000e46 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000e42: 2301 movs r3, #1
8000e44: e31d b.n 8001482 <HAL_RCC_OscConfig+0x64e>
}
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8000e46: 4b94 ldr r3, [pc, #592] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000e48: 689b ldr r3, [r3, #8]
8000e4a: f003 030c and.w r3, r3, #12
8000e4e: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
8000e50: 4b91 ldr r3, [pc, #580] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000e52: 689b ldr r3, [r3, #8]
8000e54: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000e58: 617b str r3, [r7, #20]
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000e5a: 687b ldr r3, [r7, #4]
8000e5c: 681b ldr r3, [r3, #0]
8000e5e: f003 0301 and.w r3, r3, #1
8000e62: 2b00 cmp r3, #0
8000e64: d07b beq.n 8000f5e <HAL_RCC_OscConfig+0x12a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
8000e66: 69bb ldr r3, [r7, #24]
8000e68: 2b08 cmp r3, #8
8000e6a: d006 beq.n 8000e7a <HAL_RCC_OscConfig+0x46>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
8000e6c: 69bb ldr r3, [r7, #24]
8000e6e: 2b0c cmp r3, #12
8000e70: d10f bne.n 8000e92 <HAL_RCC_OscConfig+0x5e>
8000e72: 697b ldr r3, [r7, #20]
8000e74: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000e78: d10b bne.n 8000e92 <HAL_RCC_OscConfig+0x5e>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000e7a: 4b87 ldr r3, [pc, #540] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000e7c: 681b ldr r3, [r3, #0]
8000e7e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000e82: 2b00 cmp r3, #0
8000e84: d06a beq.n 8000f5c <HAL_RCC_OscConfig+0x128>
8000e86: 687b ldr r3, [r7, #4]
8000e88: 685b ldr r3, [r3, #4]
8000e8a: 2b00 cmp r3, #0
8000e8c: d166 bne.n 8000f5c <HAL_RCC_OscConfig+0x128>
{
return HAL_ERROR;
8000e8e: 2301 movs r3, #1
8000e90: e2f7 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000e92: 687b ldr r3, [r7, #4]
8000e94: 685b ldr r3, [r3, #4]
8000e96: 2b01 cmp r3, #1
8000e98: d106 bne.n 8000ea8 <HAL_RCC_OscConfig+0x74>
8000e9a: 4b7f ldr r3, [pc, #508] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000e9c: 681b ldr r3, [r3, #0]
8000e9e: 4a7e ldr r2, [pc, #504] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ea0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000ea4: 6013 str r3, [r2, #0]
8000ea6: e02d b.n 8000f04 <HAL_RCC_OscConfig+0xd0>
8000ea8: 687b ldr r3, [r7, #4]
8000eaa: 685b ldr r3, [r3, #4]
8000eac: 2b00 cmp r3, #0
8000eae: d10c bne.n 8000eca <HAL_RCC_OscConfig+0x96>
8000eb0: 4b79 ldr r3, [pc, #484] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000eb2: 681b ldr r3, [r3, #0]
8000eb4: 4a78 ldr r2, [pc, #480] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000eb6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000eba: 6013 str r3, [r2, #0]
8000ebc: 4b76 ldr r3, [pc, #472] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ebe: 681b ldr r3, [r3, #0]
8000ec0: 4a75 ldr r2, [pc, #468] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ec2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000ec6: 6013 str r3, [r2, #0]
8000ec8: e01c b.n 8000f04 <HAL_RCC_OscConfig+0xd0>
8000eca: 687b ldr r3, [r7, #4]
8000ecc: 685b ldr r3, [r3, #4]
8000ece: 2b05 cmp r3, #5
8000ed0: d10c bne.n 8000eec <HAL_RCC_OscConfig+0xb8>
8000ed2: 4b71 ldr r3, [pc, #452] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ed4: 681b ldr r3, [r3, #0]
8000ed6: 4a70 ldr r2, [pc, #448] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ed8: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8000edc: 6013 str r3, [r2, #0]
8000ede: 4b6e ldr r3, [pc, #440] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ee0: 681b ldr r3, [r3, #0]
8000ee2: 4a6d ldr r2, [pc, #436] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ee4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000ee8: 6013 str r3, [r2, #0]
8000eea: e00b b.n 8000f04 <HAL_RCC_OscConfig+0xd0>
8000eec: 4b6a ldr r3, [pc, #424] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000eee: 681b ldr r3, [r3, #0]
8000ef0: 4a69 ldr r2, [pc, #420] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000ef2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000ef6: 6013 str r3, [r2, #0]
8000ef8: 4b67 ldr r3, [pc, #412] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000efa: 681b ldr r3, [r3, #0]
8000efc: 4a66 ldr r2, [pc, #408] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000efe: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000f02: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000f04: 687b ldr r3, [r7, #4]
8000f06: 685b ldr r3, [r3, #4]
8000f08: 2b00 cmp r3, #0
8000f0a: d013 beq.n 8000f34 <HAL_RCC_OscConfig+0x100>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f0c: f7ff fcda bl 80008c4 <HAL_GetTick>
8000f10: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8000f12: e008 b.n 8000f26 <HAL_RCC_OscConfig+0xf2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000f14: f7ff fcd6 bl 80008c4 <HAL_GetTick>
8000f18: 4602 mov r2, r0
8000f1a: 693b ldr r3, [r7, #16]
8000f1c: 1ad3 subs r3, r2, r3
8000f1e: 2b64 cmp r3, #100 @ 0x64
8000f20: d901 bls.n 8000f26 <HAL_RCC_OscConfig+0xf2>
{
return HAL_TIMEOUT;
8000f22: 2303 movs r3, #3
8000f24: e2ad b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8000f26: 4b5c ldr r3, [pc, #368] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000f28: 681b ldr r3, [r3, #0]
8000f2a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000f2e: 2b00 cmp r3, #0
8000f30: d0f0 beq.n 8000f14 <HAL_RCC_OscConfig+0xe0>
8000f32: e014 b.n 8000f5e <HAL_RCC_OscConfig+0x12a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f34: f7ff fcc6 bl 80008c4 <HAL_GetTick>
8000f38: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8000f3a: e008 b.n 8000f4e <HAL_RCC_OscConfig+0x11a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000f3c: f7ff fcc2 bl 80008c4 <HAL_GetTick>
8000f40: 4602 mov r2, r0
8000f42: 693b ldr r3, [r7, #16]
8000f44: 1ad3 subs r3, r2, r3
8000f46: 2b64 cmp r3, #100 @ 0x64
8000f48: d901 bls.n 8000f4e <HAL_RCC_OscConfig+0x11a>
{
return HAL_TIMEOUT;
8000f4a: 2303 movs r3, #3
8000f4c: e299 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8000f4e: 4b52 ldr r3, [pc, #328] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000f50: 681b ldr r3, [r3, #0]
8000f52: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000f56: 2b00 cmp r3, #0
8000f58: d1f0 bne.n 8000f3c <HAL_RCC_OscConfig+0x108>
8000f5a: e000 b.n 8000f5e <HAL_RCC_OscConfig+0x12a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000f5c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000f5e: 687b ldr r3, [r7, #4]
8000f60: 681b ldr r3, [r3, #0]
8000f62: f003 0302 and.w r3, r3, #2
8000f66: 2b00 cmp r3, #0
8000f68: d05a beq.n 8001020 <HAL_RCC_OscConfig+0x1ec>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
8000f6a: 69bb ldr r3, [r7, #24]
8000f6c: 2b04 cmp r3, #4
8000f6e: d005 beq.n 8000f7c <HAL_RCC_OscConfig+0x148>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
8000f70: 69bb ldr r3, [r7, #24]
8000f72: 2b0c cmp r3, #12
8000f74: d119 bne.n 8000faa <HAL_RCC_OscConfig+0x176>
8000f76: 697b ldr r3, [r7, #20]
8000f78: 2b00 cmp r3, #0
8000f7a: d116 bne.n 8000faa <HAL_RCC_OscConfig+0x176>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000f7c: 4b46 ldr r3, [pc, #280] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000f7e: 681b ldr r3, [r3, #0]
8000f80: f003 0302 and.w r3, r3, #2
8000f84: 2b00 cmp r3, #0
8000f86: d005 beq.n 8000f94 <HAL_RCC_OscConfig+0x160>
8000f88: 687b ldr r3, [r7, #4]
8000f8a: 68db ldr r3, [r3, #12]
8000f8c: 2b01 cmp r3, #1
8000f8e: d001 beq.n 8000f94 <HAL_RCC_OscConfig+0x160>
{
return HAL_ERROR;
8000f90: 2301 movs r3, #1
8000f92: e276 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000f94: 4b40 ldr r3, [pc, #256] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000f96: 685b ldr r3, [r3, #4]
8000f98: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8000f9c: 687b ldr r3, [r7, #4]
8000f9e: 691b ldr r3, [r3, #16]
8000fa0: 021b lsls r3, r3, #8
8000fa2: 493d ldr r1, [pc, #244] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000fa4: 4313 orrs r3, r2
8000fa6: 604b str r3, [r1, #4]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000fa8: e03a b.n 8001020 <HAL_RCC_OscConfig+0x1ec>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000faa: 687b ldr r3, [r7, #4]
8000fac: 68db ldr r3, [r3, #12]
8000fae: 2b00 cmp r3, #0
8000fb0: d020 beq.n 8000ff4 <HAL_RCC_OscConfig+0x1c0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8000fb2: 4b3a ldr r3, [pc, #232] @ (800109c <HAL_RCC_OscConfig+0x268>)
8000fb4: 2201 movs r2, #1
8000fb6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fb8: f7ff fc84 bl 80008c4 <HAL_GetTick>
8000fbc: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8000fbe: e008 b.n 8000fd2 <HAL_RCC_OscConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8000fc0: f7ff fc80 bl 80008c4 <HAL_GetTick>
8000fc4: 4602 mov r2, r0
8000fc6: 693b ldr r3, [r7, #16]
8000fc8: 1ad3 subs r3, r2, r3
8000fca: 2b02 cmp r3, #2
8000fcc: d901 bls.n 8000fd2 <HAL_RCC_OscConfig+0x19e>
{
return HAL_TIMEOUT;
8000fce: 2303 movs r3, #3
8000fd0: e257 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8000fd2: 4b31 ldr r3, [pc, #196] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000fd4: 681b ldr r3, [r3, #0]
8000fd6: f003 0302 and.w r3, r3, #2
8000fda: 2b00 cmp r3, #0
8000fdc: d0f0 beq.n 8000fc0 <HAL_RCC_OscConfig+0x18c>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000fde: 4b2e ldr r3, [pc, #184] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000fe0: 685b ldr r3, [r3, #4]
8000fe2: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8000fe6: 687b ldr r3, [r7, #4]
8000fe8: 691b ldr r3, [r3, #16]
8000fea: 021b lsls r3, r3, #8
8000fec: 492a ldr r1, [pc, #168] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8000fee: 4313 orrs r3, r2
8000ff0: 604b str r3, [r1, #4]
8000ff2: e015 b.n 8001020 <HAL_RCC_OscConfig+0x1ec>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8000ff4: 4b29 ldr r3, [pc, #164] @ (800109c <HAL_RCC_OscConfig+0x268>)
8000ff6: 2200 movs r2, #0
8000ff8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ffa: f7ff fc63 bl 80008c4 <HAL_GetTick>
8000ffe: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001000: e008 b.n 8001014 <HAL_RCC_OscConfig+0x1e0>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001002: f7ff fc5f bl 80008c4 <HAL_GetTick>
8001006: 4602 mov r2, r0
8001008: 693b ldr r3, [r7, #16]
800100a: 1ad3 subs r3, r2, r3
800100c: 2b02 cmp r3, #2
800100e: d901 bls.n 8001014 <HAL_RCC_OscConfig+0x1e0>
{
return HAL_TIMEOUT;
8001010: 2303 movs r3, #3
8001012: e236 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001014: 4b20 ldr r3, [pc, #128] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8001016: 681b ldr r3, [r3, #0]
8001018: f003 0302 and.w r3, r3, #2
800101c: 2b00 cmp r3, #0
800101e: d1f0 bne.n 8001002 <HAL_RCC_OscConfig+0x1ce>
}
}
}
}
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8001020: 687b ldr r3, [r7, #4]
8001022: 681b ldr r3, [r3, #0]
8001024: f003 0310 and.w r3, r3, #16
8001028: 2b00 cmp r3, #0
800102a: f000 80b8 beq.w 800119e <HAL_RCC_OscConfig+0x36a>
{
/* When the MSI is used as system clock it will not be disabled */
if(sysclk_source == RCC_CFGR_SWS_MSI)
800102e: 69bb ldr r3, [r7, #24]
8001030: 2b00 cmp r3, #0
8001032: d170 bne.n 8001116 <HAL_RCC_OscConfig+0x2e2>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001034: 4b18 ldr r3, [pc, #96] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8001036: 681b ldr r3, [r3, #0]
8001038: f403 7300 and.w r3, r3, #512 @ 0x200
800103c: 2b00 cmp r3, #0
800103e: d005 beq.n 800104c <HAL_RCC_OscConfig+0x218>
8001040: 687b ldr r3, [r7, #4]
8001042: 699b ldr r3, [r3, #24]
8001044: 2b00 cmp r3, #0
8001046: d101 bne.n 800104c <HAL_RCC_OscConfig+0x218>
{
return HAL_ERROR;
8001048: 2301 movs r3, #1
800104a: e21a b.n 8001482 <HAL_RCC_OscConfig+0x64e>
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
800104c: 687b ldr r3, [r7, #4]
800104e: 6a1a ldr r2, [r3, #32]
8001050: 4b11 ldr r3, [pc, #68] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8001052: 685b ldr r3, [r3, #4]
8001054: f403 4360 and.w r3, r3, #57344 @ 0xe000
8001058: 429a cmp r2, r3
800105a: d921 bls.n 80010a0 <HAL_RCC_OscConfig+0x26c>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
800105c: 687b ldr r3, [r7, #4]
800105e: 6a1b ldr r3, [r3, #32]
8001060: 4618 mov r0, r3
8001062: f000 fc09 bl 8001878 <RCC_SetFlashLatencyFromMSIRange>
8001066: 4603 mov r3, r0
8001068: 2b00 cmp r3, #0
800106a: d001 beq.n 8001070 <HAL_RCC_OscConfig+0x23c>
{
return HAL_ERROR;
800106c: 2301 movs r3, #1
800106e: e208 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001070: 4b09 ldr r3, [pc, #36] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8001072: 685b ldr r3, [r3, #4]
8001074: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8001078: 687b ldr r3, [r7, #4]
800107a: 6a1b ldr r3, [r3, #32]
800107c: 4906 ldr r1, [pc, #24] @ (8001098 <HAL_RCC_OscConfig+0x264>)
800107e: 4313 orrs r3, r2
8001080: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001082: 4b05 ldr r3, [pc, #20] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8001084: 685b ldr r3, [r3, #4]
8001086: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
800108a: 687b ldr r3, [r7, #4]
800108c: 69db ldr r3, [r3, #28]
800108e: 061b lsls r3, r3, #24
8001090: 4901 ldr r1, [pc, #4] @ (8001098 <HAL_RCC_OscConfig+0x264>)
8001092: 4313 orrs r3, r2
8001094: 604b str r3, [r1, #4]
8001096: e020 b.n 80010da <HAL_RCC_OscConfig+0x2a6>
8001098: 40023800 .word 0x40023800
800109c: 42470000 .word 0x42470000
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80010a0: 4b99 ldr r3, [pc, #612] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80010a2: 685b ldr r3, [r3, #4]
80010a4: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80010a8: 687b ldr r3, [r7, #4]
80010aa: 6a1b ldr r3, [r3, #32]
80010ac: 4996 ldr r1, [pc, #600] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80010ae: 4313 orrs r3, r2
80010b0: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80010b2: 4b95 ldr r3, [pc, #596] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80010b4: 685b ldr r3, [r3, #4]
80010b6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
80010ba: 687b ldr r3, [r7, #4]
80010bc: 69db ldr r3, [r3, #28]
80010be: 061b lsls r3, r3, #24
80010c0: 4991 ldr r1, [pc, #580] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80010c2: 4313 orrs r3, r2
80010c4: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
80010c6: 687b ldr r3, [r7, #4]
80010c8: 6a1b ldr r3, [r3, #32]
80010ca: 4618 mov r0, r3
80010cc: f000 fbd4 bl 8001878 <RCC_SetFlashLatencyFromMSIRange>
80010d0: 4603 mov r3, r0
80010d2: 2b00 cmp r3, #0
80010d4: d001 beq.n 80010da <HAL_RCC_OscConfig+0x2a6>
{
return HAL_ERROR;
80010d6: 2301 movs r3, #1
80010d8: e1d3 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
80010da: 687b ldr r3, [r7, #4]
80010dc: 6a1b ldr r3, [r3, #32]
80010de: 0b5b lsrs r3, r3, #13
80010e0: 3301 adds r3, #1
80010e2: f44f 4200 mov.w r2, #32768 @ 0x8000
80010e6: fa02 f303 lsl.w r3, r2, r3
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
80010ea: 4a87 ldr r2, [pc, #540] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80010ec: 6892 ldr r2, [r2, #8]
80010ee: 0912 lsrs r2, r2, #4
80010f0: f002 020f and.w r2, r2, #15
80010f4: 4985 ldr r1, [pc, #532] @ (800130c <HAL_RCC_OscConfig+0x4d8>)
80010f6: 5c8a ldrb r2, [r1, r2]
80010f8: 40d3 lsrs r3, r2
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
80010fa: 4a85 ldr r2, [pc, #532] @ (8001310 <HAL_RCC_OscConfig+0x4dc>)
80010fc: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
80010fe: 4b85 ldr r3, [pc, #532] @ (8001314 <HAL_RCC_OscConfig+0x4e0>)
8001100: 681b ldr r3, [r3, #0]
8001102: 4618 mov r0, r3
8001104: f7ff fb92 bl 800082c <HAL_InitTick>
8001108: 4603 mov r3, r0
800110a: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
800110c: 7bfb ldrb r3, [r7, #15]
800110e: 2b00 cmp r3, #0
8001110: d045 beq.n 800119e <HAL_RCC_OscConfig+0x36a>
{
return status;
8001112: 7bfb ldrb r3, [r7, #15]
8001114: e1b5 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
{
/* Check MSI State */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8001116: 687b ldr r3, [r7, #4]
8001118: 699b ldr r3, [r3, #24]
800111a: 2b00 cmp r3, #0
800111c: d029 beq.n 8001172 <HAL_RCC_OscConfig+0x33e>
{
/* Enable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
800111e: 4b7e ldr r3, [pc, #504] @ (8001318 <HAL_RCC_OscConfig+0x4e4>)
8001120: 2201 movs r2, #1
8001122: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001124: f7ff fbce bl 80008c4 <HAL_GetTick>
8001128: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800112a: e008 b.n 800113e <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
800112c: f7ff fbca bl 80008c4 <HAL_GetTick>
8001130: 4602 mov r2, r0
8001132: 693b ldr r3, [r7, #16]
8001134: 1ad3 subs r3, r2, r3
8001136: 2b02 cmp r3, #2
8001138: d901 bls.n 800113e <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
800113a: 2303 movs r3, #3
800113c: e1a1 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800113e: 4b72 ldr r3, [pc, #456] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001140: 681b ldr r3, [r3, #0]
8001142: f403 7300 and.w r3, r3, #512 @ 0x200
8001146: 2b00 cmp r3, #0
8001148: d0f0 beq.n 800112c <HAL_RCC_OscConfig+0x2f8>
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800114a: 4b6f ldr r3, [pc, #444] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
800114c: 685b ldr r3, [r3, #4]
800114e: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8001152: 687b ldr r3, [r7, #4]
8001154: 6a1b ldr r3, [r3, #32]
8001156: 496c ldr r1, [pc, #432] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001158: 4313 orrs r3, r2
800115a: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
800115c: 4b6a ldr r3, [pc, #424] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
800115e: 685b ldr r3, [r3, #4]
8001160: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
8001164: 687b ldr r3, [r7, #4]
8001166: 69db ldr r3, [r3, #28]
8001168: 061b lsls r3, r3, #24
800116a: 4967 ldr r1, [pc, #412] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
800116c: 4313 orrs r3, r2
800116e: 604b str r3, [r1, #4]
8001170: e015 b.n 800119e <HAL_RCC_OscConfig+0x36a>
}
else
{
/* Disable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
8001172: 4b69 ldr r3, [pc, #420] @ (8001318 <HAL_RCC_OscConfig+0x4e4>)
8001174: 2200 movs r2, #0
8001176: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001178: f7ff fba4 bl 80008c4 <HAL_GetTick>
800117c: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
800117e: e008 b.n 8001192 <HAL_RCC_OscConfig+0x35e>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8001180: f7ff fba0 bl 80008c4 <HAL_GetTick>
8001184: 4602 mov r2, r0
8001186: 693b ldr r3, [r7, #16]
8001188: 1ad3 subs r3, r2, r3
800118a: 2b02 cmp r3, #2
800118c: d901 bls.n 8001192 <HAL_RCC_OscConfig+0x35e>
{
return HAL_TIMEOUT;
800118e: 2303 movs r3, #3
8001190: e177 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
8001192: 4b5d ldr r3, [pc, #372] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001194: 681b ldr r3, [r3, #0]
8001196: f403 7300 and.w r3, r3, #512 @ 0x200
800119a: 2b00 cmp r3, #0
800119c: d1f0 bne.n 8001180 <HAL_RCC_OscConfig+0x34c>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800119e: 687b ldr r3, [r7, #4]
80011a0: 681b ldr r3, [r3, #0]
80011a2: f003 0308 and.w r3, r3, #8
80011a6: 2b00 cmp r3, #0
80011a8: d030 beq.n 800120c <HAL_RCC_OscConfig+0x3d8>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80011aa: 687b ldr r3, [r7, #4]
80011ac: 695b ldr r3, [r3, #20]
80011ae: 2b00 cmp r3, #0
80011b0: d016 beq.n 80011e0 <HAL_RCC_OscConfig+0x3ac>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80011b2: 4b5a ldr r3, [pc, #360] @ (800131c <HAL_RCC_OscConfig+0x4e8>)
80011b4: 2201 movs r2, #1
80011b6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011b8: f7ff fb84 bl 80008c4 <HAL_GetTick>
80011bc: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
80011be: e008 b.n 80011d2 <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80011c0: f7ff fb80 bl 80008c4 <HAL_GetTick>
80011c4: 4602 mov r2, r0
80011c6: 693b ldr r3, [r7, #16]
80011c8: 1ad3 subs r3, r2, r3
80011ca: 2b02 cmp r3, #2
80011cc: d901 bls.n 80011d2 <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
80011ce: 2303 movs r3, #3
80011d0: e157 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
80011d2: 4b4d ldr r3, [pc, #308] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80011d4: 6b5b ldr r3, [r3, #52] @ 0x34
80011d6: f003 0302 and.w r3, r3, #2
80011da: 2b00 cmp r3, #0
80011dc: d0f0 beq.n 80011c0 <HAL_RCC_OscConfig+0x38c>
80011de: e015 b.n 800120c <HAL_RCC_OscConfig+0x3d8>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80011e0: 4b4e ldr r3, [pc, #312] @ (800131c <HAL_RCC_OscConfig+0x4e8>)
80011e2: 2200 movs r2, #0
80011e4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011e6: f7ff fb6d bl 80008c4 <HAL_GetTick>
80011ea: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
80011ec: e008 b.n 8001200 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80011ee: f7ff fb69 bl 80008c4 <HAL_GetTick>
80011f2: 4602 mov r2, r0
80011f4: 693b ldr r3, [r7, #16]
80011f6: 1ad3 subs r3, r2, r3
80011f8: 2b02 cmp r3, #2
80011fa: d901 bls.n 8001200 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
80011fc: 2303 movs r3, #3
80011fe: e140 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8001200: 4b41 ldr r3, [pc, #260] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001202: 6b5b ldr r3, [r3, #52] @ 0x34
8001204: f003 0302 and.w r3, r3, #2
8001208: 2b00 cmp r3, #0
800120a: d1f0 bne.n 80011ee <HAL_RCC_OscConfig+0x3ba>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800120c: 687b ldr r3, [r7, #4]
800120e: 681b ldr r3, [r3, #0]
8001210: f003 0304 and.w r3, r3, #4
8001214: 2b00 cmp r3, #0
8001216: f000 80b5 beq.w 8001384 <HAL_RCC_OscConfig+0x550>
{
FlagStatus pwrclkchanged = RESET;
800121a: 2300 movs r3, #0
800121c: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800121e: 4b3a ldr r3, [pc, #232] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001220: 6a5b ldr r3, [r3, #36] @ 0x24
8001222: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001226: 2b00 cmp r3, #0
8001228: d10d bne.n 8001246 <HAL_RCC_OscConfig+0x412>
{
__HAL_RCC_PWR_CLK_ENABLE();
800122a: 4b37 ldr r3, [pc, #220] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
800122c: 6a5b ldr r3, [r3, #36] @ 0x24
800122e: 4a36 ldr r2, [pc, #216] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001230: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001234: 6253 str r3, [r2, #36] @ 0x24
8001236: 4b34 ldr r3, [pc, #208] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001238: 6a5b ldr r3, [r3, #36] @ 0x24
800123a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800123e: 60bb str r3, [r7, #8]
8001240: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001242: 2301 movs r3, #1
8001244: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001246: 4b36 ldr r3, [pc, #216] @ (8001320 <HAL_RCC_OscConfig+0x4ec>)
8001248: 681b ldr r3, [r3, #0]
800124a: f403 7380 and.w r3, r3, #256 @ 0x100
800124e: 2b00 cmp r3, #0
8001250: d118 bne.n 8001284 <HAL_RCC_OscConfig+0x450>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001252: 4b33 ldr r3, [pc, #204] @ (8001320 <HAL_RCC_OscConfig+0x4ec>)
8001254: 681b ldr r3, [r3, #0]
8001256: 4a32 ldr r2, [pc, #200] @ (8001320 <HAL_RCC_OscConfig+0x4ec>)
8001258: f443 7380 orr.w r3, r3, #256 @ 0x100
800125c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800125e: f7ff fb31 bl 80008c4 <HAL_GetTick>
8001262: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001264: e008 b.n 8001278 <HAL_RCC_OscConfig+0x444>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001266: f7ff fb2d bl 80008c4 <HAL_GetTick>
800126a: 4602 mov r2, r0
800126c: 693b ldr r3, [r7, #16]
800126e: 1ad3 subs r3, r2, r3
8001270: 2b64 cmp r3, #100 @ 0x64
8001272: d901 bls.n 8001278 <HAL_RCC_OscConfig+0x444>
{
return HAL_TIMEOUT;
8001274: 2303 movs r3, #3
8001276: e104 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001278: 4b29 ldr r3, [pc, #164] @ (8001320 <HAL_RCC_OscConfig+0x4ec>)
800127a: 681b ldr r3, [r3, #0]
800127c: f403 7380 and.w r3, r3, #256 @ 0x100
8001280: 2b00 cmp r3, #0
8001282: d0f0 beq.n 8001266 <HAL_RCC_OscConfig+0x432>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001284: 687b ldr r3, [r7, #4]
8001286: 689b ldr r3, [r3, #8]
8001288: 2b01 cmp r3, #1
800128a: d106 bne.n 800129a <HAL_RCC_OscConfig+0x466>
800128c: 4b1e ldr r3, [pc, #120] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
800128e: 6b5b ldr r3, [r3, #52] @ 0x34
8001290: 4a1d ldr r2, [pc, #116] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
8001292: f443 7380 orr.w r3, r3, #256 @ 0x100
8001296: 6353 str r3, [r2, #52] @ 0x34
8001298: e02d b.n 80012f6 <HAL_RCC_OscConfig+0x4c2>
800129a: 687b ldr r3, [r7, #4]
800129c: 689b ldr r3, [r3, #8]
800129e: 2b00 cmp r3, #0
80012a0: d10c bne.n 80012bc <HAL_RCC_OscConfig+0x488>
80012a2: 4b19 ldr r3, [pc, #100] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012a4: 6b5b ldr r3, [r3, #52] @ 0x34
80012a6: 4a18 ldr r2, [pc, #96] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012a8: f423 7380 bic.w r3, r3, #256 @ 0x100
80012ac: 6353 str r3, [r2, #52] @ 0x34
80012ae: 4b16 ldr r3, [pc, #88] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012b0: 6b5b ldr r3, [r3, #52] @ 0x34
80012b2: 4a15 ldr r2, [pc, #84] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012b4: f423 6380 bic.w r3, r3, #1024 @ 0x400
80012b8: 6353 str r3, [r2, #52] @ 0x34
80012ba: e01c b.n 80012f6 <HAL_RCC_OscConfig+0x4c2>
80012bc: 687b ldr r3, [r7, #4]
80012be: 689b ldr r3, [r3, #8]
80012c0: 2b05 cmp r3, #5
80012c2: d10c bne.n 80012de <HAL_RCC_OscConfig+0x4aa>
80012c4: 4b10 ldr r3, [pc, #64] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012c6: 6b5b ldr r3, [r3, #52] @ 0x34
80012c8: 4a0f ldr r2, [pc, #60] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012ca: f443 6380 orr.w r3, r3, #1024 @ 0x400
80012ce: 6353 str r3, [r2, #52] @ 0x34
80012d0: 4b0d ldr r3, [pc, #52] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012d2: 6b5b ldr r3, [r3, #52] @ 0x34
80012d4: 4a0c ldr r2, [pc, #48] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012d6: f443 7380 orr.w r3, r3, #256 @ 0x100
80012da: 6353 str r3, [r2, #52] @ 0x34
80012dc: e00b b.n 80012f6 <HAL_RCC_OscConfig+0x4c2>
80012de: 4b0a ldr r3, [pc, #40] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012e0: 6b5b ldr r3, [r3, #52] @ 0x34
80012e2: 4a09 ldr r2, [pc, #36] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012e4: f423 7380 bic.w r3, r3, #256 @ 0x100
80012e8: 6353 str r3, [r2, #52] @ 0x34
80012ea: 4b07 ldr r3, [pc, #28] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012ec: 6b5b ldr r3, [r3, #52] @ 0x34
80012ee: 4a06 ldr r2, [pc, #24] @ (8001308 <HAL_RCC_OscConfig+0x4d4>)
80012f0: f423 6380 bic.w r3, r3, #1024 @ 0x400
80012f4: 6353 str r3, [r2, #52] @ 0x34
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
80012f6: 687b ldr r3, [r7, #4]
80012f8: 689b ldr r3, [r3, #8]
80012fa: 2b00 cmp r3, #0
80012fc: d024 beq.n 8001348 <HAL_RCC_OscConfig+0x514>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80012fe: f7ff fae1 bl 80008c4 <HAL_GetTick>
8001302: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8001304: e019 b.n 800133a <HAL_RCC_OscConfig+0x506>
8001306: bf00 nop
8001308: 40023800 .word 0x40023800
800130c: 080019b4 .word 0x080019b4
8001310: 20000000 .word 0x20000000
8001314: 20000004 .word 0x20000004
8001318: 42470020 .word 0x42470020
800131c: 42470680 .word 0x42470680
8001320: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001324: f7ff face bl 80008c4 <HAL_GetTick>
8001328: 4602 mov r2, r0
800132a: 693b ldr r3, [r7, #16]
800132c: 1ad3 subs r3, r2, r3
800132e: f241 3288 movw r2, #5000 @ 0x1388
8001332: 4293 cmp r3, r2
8001334: d901 bls.n 800133a <HAL_RCC_OscConfig+0x506>
{
return HAL_TIMEOUT;
8001336: 2303 movs r3, #3
8001338: e0a3 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
800133a: 4b54 ldr r3, [pc, #336] @ (800148c <HAL_RCC_OscConfig+0x658>)
800133c: 6b5b ldr r3, [r3, #52] @ 0x34
800133e: f403 7300 and.w r3, r3, #512 @ 0x200
8001342: 2b00 cmp r3, #0
8001344: d0ee beq.n 8001324 <HAL_RCC_OscConfig+0x4f0>
8001346: e014 b.n 8001372 <HAL_RCC_OscConfig+0x53e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001348: f7ff fabc bl 80008c4 <HAL_GetTick>
800134c: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
800134e: e00a b.n 8001366 <HAL_RCC_OscConfig+0x532>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001350: f7ff fab8 bl 80008c4 <HAL_GetTick>
8001354: 4602 mov r2, r0
8001356: 693b ldr r3, [r7, #16]
8001358: 1ad3 subs r3, r2, r3
800135a: f241 3288 movw r2, #5000 @ 0x1388
800135e: 4293 cmp r3, r2
8001360: d901 bls.n 8001366 <HAL_RCC_OscConfig+0x532>
{
return HAL_TIMEOUT;
8001362: 2303 movs r3, #3
8001364: e08d b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
8001366: 4b49 ldr r3, [pc, #292] @ (800148c <HAL_RCC_OscConfig+0x658>)
8001368: 6b5b ldr r3, [r3, #52] @ 0x34
800136a: f403 7300 and.w r3, r3, #512 @ 0x200
800136e: 2b00 cmp r3, #0
8001370: d1ee bne.n 8001350 <HAL_RCC_OscConfig+0x51c>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8001372: 7ffb ldrb r3, [r7, #31]
8001374: 2b01 cmp r3, #1
8001376: d105 bne.n 8001384 <HAL_RCC_OscConfig+0x550>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001378: 4b44 ldr r3, [pc, #272] @ (800148c <HAL_RCC_OscConfig+0x658>)
800137a: 6a5b ldr r3, [r3, #36] @ 0x24
800137c: 4a43 ldr r2, [pc, #268] @ (800148c <HAL_RCC_OscConfig+0x658>)
800137e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8001382: 6253 str r3, [r2, #36] @ 0x24
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001384: 687b ldr r3, [r7, #4]
8001386: 6a5b ldr r3, [r3, #36] @ 0x24
8001388: 2b00 cmp r3, #0
800138a: d079 beq.n 8001480 <HAL_RCC_OscConfig+0x64c>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800138c: 69bb ldr r3, [r7, #24]
800138e: 2b0c cmp r3, #12
8001390: d056 beq.n 8001440 <HAL_RCC_OscConfig+0x60c>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001392: 687b ldr r3, [r7, #4]
8001394: 6a5b ldr r3, [r3, #36] @ 0x24
8001396: 2b02 cmp r3, #2
8001398: d13b bne.n 8001412 <HAL_RCC_OscConfig+0x5de>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800139a: 4b3d ldr r3, [pc, #244] @ (8001490 <HAL_RCC_OscConfig+0x65c>)
800139c: 2200 movs r2, #0
800139e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80013a0: f7ff fa90 bl 80008c4 <HAL_GetTick>
80013a4: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80013a6: e008 b.n 80013ba <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80013a8: f7ff fa8c bl 80008c4 <HAL_GetTick>
80013ac: 4602 mov r2, r0
80013ae: 693b ldr r3, [r7, #16]
80013b0: 1ad3 subs r3, r2, r3
80013b2: 2b02 cmp r3, #2
80013b4: d901 bls.n 80013ba <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
80013b6: 2303 movs r3, #3
80013b8: e063 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80013ba: 4b34 ldr r3, [pc, #208] @ (800148c <HAL_RCC_OscConfig+0x658>)
80013bc: 681b ldr r3, [r3, #0]
80013be: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80013c2: 2b00 cmp r3, #0
80013c4: d1f0 bne.n 80013a8 <HAL_RCC_OscConfig+0x574>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80013c6: 4b31 ldr r3, [pc, #196] @ (800148c <HAL_RCC_OscConfig+0x658>)
80013c8: 689b ldr r3, [r3, #8]
80013ca: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000
80013ce: 687b ldr r3, [r7, #4]
80013d0: 6a99 ldr r1, [r3, #40] @ 0x28
80013d2: 687b ldr r3, [r7, #4]
80013d4: 6adb ldr r3, [r3, #44] @ 0x2c
80013d6: 4319 orrs r1, r3
80013d8: 687b ldr r3, [r7, #4]
80013da: 6b1b ldr r3, [r3, #48] @ 0x30
80013dc: 430b orrs r3, r1
80013de: 492b ldr r1, [pc, #172] @ (800148c <HAL_RCC_OscConfig+0x658>)
80013e0: 4313 orrs r3, r2
80013e2: 608b str r3, [r1, #8]
RCC_OscInitStruct->PLL.PLLMUL,
RCC_OscInitStruct->PLL.PLLDIV);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80013e4: 4b2a ldr r3, [pc, #168] @ (8001490 <HAL_RCC_OscConfig+0x65c>)
80013e6: 2201 movs r2, #1
80013e8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80013ea: f7ff fa6b bl 80008c4 <HAL_GetTick>
80013ee: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
80013f0: e008 b.n 8001404 <HAL_RCC_OscConfig+0x5d0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80013f2: f7ff fa67 bl 80008c4 <HAL_GetTick>
80013f6: 4602 mov r2, r0
80013f8: 693b ldr r3, [r7, #16]
80013fa: 1ad3 subs r3, r2, r3
80013fc: 2b02 cmp r3, #2
80013fe: d901 bls.n 8001404 <HAL_RCC_OscConfig+0x5d0>
{
return HAL_TIMEOUT;
8001400: 2303 movs r3, #3
8001402: e03e b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001404: 4b21 ldr r3, [pc, #132] @ (800148c <HAL_RCC_OscConfig+0x658>)
8001406: 681b ldr r3, [r3, #0]
8001408: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800140c: 2b00 cmp r3, #0
800140e: d0f0 beq.n 80013f2 <HAL_RCC_OscConfig+0x5be>
8001410: e036 b.n 8001480 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001412: 4b1f ldr r3, [pc, #124] @ (8001490 <HAL_RCC_OscConfig+0x65c>)
8001414: 2200 movs r2, #0
8001416: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001418: f7ff fa54 bl 80008c4 <HAL_GetTick>
800141c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
800141e: e008 b.n 8001432 <HAL_RCC_OscConfig+0x5fe>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001420: f7ff fa50 bl 80008c4 <HAL_GetTick>
8001424: 4602 mov r2, r0
8001426: 693b ldr r3, [r7, #16]
8001428: 1ad3 subs r3, r2, r3
800142a: 2b02 cmp r3, #2
800142c: d901 bls.n 8001432 <HAL_RCC_OscConfig+0x5fe>
{
return HAL_TIMEOUT;
800142e: 2303 movs r3, #3
8001430: e027 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8001432: 4b16 ldr r3, [pc, #88] @ (800148c <HAL_RCC_OscConfig+0x658>)
8001434: 681b ldr r3, [r3, #0]
8001436: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800143a: 2b00 cmp r3, #0
800143c: d1f0 bne.n 8001420 <HAL_RCC_OscConfig+0x5ec>
800143e: e01f b.n 8001480 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001440: 687b ldr r3, [r7, #4]
8001442: 6a5b ldr r3, [r3, #36] @ 0x24
8001444: 2b01 cmp r3, #1
8001446: d101 bne.n 800144c <HAL_RCC_OscConfig+0x618>
{
return HAL_ERROR;
8001448: 2301 movs r3, #1
800144a: e01a b.n 8001482 <HAL_RCC_OscConfig+0x64e>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800144c: 4b0f ldr r3, [pc, #60] @ (800148c <HAL_RCC_OscConfig+0x658>)
800144e: 689b ldr r3, [r3, #8]
8001450: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001452: 697b ldr r3, [r7, #20]
8001454: f403 3280 and.w r2, r3, #65536 @ 0x10000
8001458: 687b ldr r3, [r7, #4]
800145a: 6a9b ldr r3, [r3, #40] @ 0x28
800145c: 429a cmp r2, r3
800145e: d10d bne.n 800147c <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
8001460: 697b ldr r3, [r7, #20]
8001462: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8001466: 687b ldr r3, [r7, #4]
8001468: 6adb ldr r3, [r3, #44] @ 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800146a: 429a cmp r2, r3
800146c: d106 bne.n 800147c <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
800146e: 697b ldr r3, [r7, #20]
8001470: f403 0240 and.w r2, r3, #12582912 @ 0xc00000
8001474: 687b ldr r3, [r7, #4]
8001476: 6b1b ldr r3, [r3, #48] @ 0x30
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
8001478: 429a cmp r2, r3
800147a: d001 beq.n 8001480 <HAL_RCC_OscConfig+0x64c>
{
return HAL_ERROR;
800147c: 2301 movs r3, #1
800147e: e000 b.n 8001482 <HAL_RCC_OscConfig+0x64e>
}
}
}
}
return HAL_OK;
8001480: 2300 movs r3, #0
}
8001482: 4618 mov r0, r3
8001484: 3720 adds r7, #32
8001486: 46bd mov sp, r7
8001488: bd80 pop {r7, pc}
800148a: bf00 nop
800148c: 40023800 .word 0x40023800
8001490: 42470060 .word 0x42470060
08001494 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001494: b580 push {r7, lr}
8001496: b084 sub sp, #16
8001498: af00 add r7, sp, #0
800149a: 6078 str r0, [r7, #4]
800149c: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status;
/* Check the parameters */
if(RCC_ClkInitStruct == NULL)
800149e: 687b ldr r3, [r7, #4]
80014a0: 2b00 cmp r3, #0
80014a2: d101 bne.n 80014a8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80014a4: 2301 movs r3, #1
80014a6: e11a b.n 80016de <HAL_RCC_ClockConfig+0x24a>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80014a8: 4b8f ldr r3, [pc, #572] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
80014aa: 681b ldr r3, [r3, #0]
80014ac: f003 0301 and.w r3, r3, #1
80014b0: 683a ldr r2, [r7, #0]
80014b2: 429a cmp r2, r3
80014b4: d919 bls.n 80014ea <HAL_RCC_ClockConfig+0x56>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80014b6: 683b ldr r3, [r7, #0]
80014b8: 2b01 cmp r3, #1
80014ba: d105 bne.n 80014c8 <HAL_RCC_ClockConfig+0x34>
80014bc: 4b8a ldr r3, [pc, #552] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
80014be: 681b ldr r3, [r3, #0]
80014c0: 4a89 ldr r2, [pc, #548] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
80014c2: f043 0304 orr.w r3, r3, #4
80014c6: 6013 str r3, [r2, #0]
80014c8: 4b87 ldr r3, [pc, #540] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
80014ca: 681b ldr r3, [r3, #0]
80014cc: f023 0201 bic.w r2, r3, #1
80014d0: 4985 ldr r1, [pc, #532] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
80014d2: 683b ldr r3, [r7, #0]
80014d4: 4313 orrs r3, r2
80014d6: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80014d8: 4b83 ldr r3, [pc, #524] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
80014da: 681b ldr r3, [r3, #0]
80014dc: f003 0301 and.w r3, r3, #1
80014e0: 683a ldr r2, [r7, #0]
80014e2: 429a cmp r2, r3
80014e4: d001 beq.n 80014ea <HAL_RCC_ClockConfig+0x56>
{
return HAL_ERROR;
80014e6: 2301 movs r3, #1
80014e8: e0f9 b.n 80016de <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80014ea: 687b ldr r3, [r7, #4]
80014ec: 681b ldr r3, [r3, #0]
80014ee: f003 0302 and.w r3, r3, #2
80014f2: 2b00 cmp r3, #0
80014f4: d008 beq.n 8001508 <HAL_RCC_ClockConfig+0x74>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80014f6: 4b7d ldr r3, [pc, #500] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
80014f8: 689b ldr r3, [r3, #8]
80014fa: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80014fe: 687b ldr r3, [r7, #4]
8001500: 689b ldr r3, [r3, #8]
8001502: 497a ldr r1, [pc, #488] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001504: 4313 orrs r3, r2
8001506: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001508: 687b ldr r3, [r7, #4]
800150a: 681b ldr r3, [r3, #0]
800150c: f003 0301 and.w r3, r3, #1
8001510: 2b00 cmp r3, #0
8001512: f000 808e beq.w 8001632 <HAL_RCC_ClockConfig+0x19e>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001516: 687b ldr r3, [r7, #4]
8001518: 685b ldr r3, [r3, #4]
800151a: 2b02 cmp r3, #2
800151c: d107 bne.n 800152e <HAL_RCC_ClockConfig+0x9a>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
800151e: 4b73 ldr r3, [pc, #460] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001520: 681b ldr r3, [r3, #0]
8001522: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001526: 2b00 cmp r3, #0
8001528: d121 bne.n 800156e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800152a: 2301 movs r3, #1
800152c: e0d7 b.n 80016de <HAL_RCC_ClockConfig+0x24a>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800152e: 687b ldr r3, [r7, #4]
8001530: 685b ldr r3, [r3, #4]
8001532: 2b03 cmp r3, #3
8001534: d107 bne.n 8001546 <HAL_RCC_ClockConfig+0xb2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001536: 4b6d ldr r3, [pc, #436] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001538: 681b ldr r3, [r3, #0]
800153a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800153e: 2b00 cmp r3, #0
8001540: d115 bne.n 800156e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8001542: 2301 movs r3, #1
8001544: e0cb b.n 80016de <HAL_RCC_ClockConfig+0x24a>
}
}
/* HSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8001546: 687b ldr r3, [r7, #4]
8001548: 685b ldr r3, [r3, #4]
800154a: 2b01 cmp r3, #1
800154c: d107 bne.n 800155e <HAL_RCC_ClockConfig+0xca>
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
800154e: 4b67 ldr r3, [pc, #412] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001550: 681b ldr r3, [r3, #0]
8001552: f003 0302 and.w r3, r3, #2
8001556: 2b00 cmp r3, #0
8001558: d109 bne.n 800156e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800155a: 2301 movs r3, #1
800155c: e0bf b.n 80016de <HAL_RCC_ClockConfig+0x24a>
}
/* MSI is selected as System Clock Source */
else
{
/* Check the MSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800155e: 4b63 ldr r3, [pc, #396] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001560: 681b ldr r3, [r3, #0]
8001562: f403 7300 and.w r3, r3, #512 @ 0x200
8001566: 2b00 cmp r3, #0
8001568: d101 bne.n 800156e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800156a: 2301 movs r3, #1
800156c: e0b7 b.n 80016de <HAL_RCC_ClockConfig+0x24a>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800156e: 4b5f ldr r3, [pc, #380] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001570: 689b ldr r3, [r3, #8]
8001572: f023 0203 bic.w r2, r3, #3
8001576: 687b ldr r3, [r7, #4]
8001578: 685b ldr r3, [r3, #4]
800157a: 495c ldr r1, [pc, #368] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
800157c: 4313 orrs r3, r2
800157e: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001580: f7ff f9a0 bl 80008c4 <HAL_GetTick>
8001584: 60f8 str r0, [r7, #12]
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001586: 687b ldr r3, [r7, #4]
8001588: 685b ldr r3, [r3, #4]
800158a: 2b02 cmp r3, #2
800158c: d112 bne.n 80015b4 <HAL_RCC_ClockConfig+0x120>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
800158e: e00a b.n 80015a6 <HAL_RCC_ClockConfig+0x112>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001590: f7ff f998 bl 80008c4 <HAL_GetTick>
8001594: 4602 mov r2, r0
8001596: 68fb ldr r3, [r7, #12]
8001598: 1ad3 subs r3, r2, r3
800159a: f241 3288 movw r2, #5000 @ 0x1388
800159e: 4293 cmp r3, r2
80015a0: d901 bls.n 80015a6 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
80015a2: 2303 movs r3, #3
80015a4: e09b b.n 80016de <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
80015a6: 4b51 ldr r3, [pc, #324] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
80015a8: 689b ldr r3, [r3, #8]
80015aa: f003 030c and.w r3, r3, #12
80015ae: 2b08 cmp r3, #8
80015b0: d1ee bne.n 8001590 <HAL_RCC_ClockConfig+0xfc>
80015b2: e03e b.n 8001632 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80015b4: 687b ldr r3, [r7, #4]
80015b6: 685b ldr r3, [r3, #4]
80015b8: 2b03 cmp r3, #3
80015ba: d112 bne.n 80015e2 <HAL_RCC_ClockConfig+0x14e>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80015bc: e00a b.n 80015d4 <HAL_RCC_ClockConfig+0x140>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80015be: f7ff f981 bl 80008c4 <HAL_GetTick>
80015c2: 4602 mov r2, r0
80015c4: 68fb ldr r3, [r7, #12]
80015c6: 1ad3 subs r3, r2, r3
80015c8: f241 3288 movw r2, #5000 @ 0x1388
80015cc: 4293 cmp r3, r2
80015ce: d901 bls.n 80015d4 <HAL_RCC_ClockConfig+0x140>
{
return HAL_TIMEOUT;
80015d0: 2303 movs r3, #3
80015d2: e084 b.n 80016de <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80015d4: 4b45 ldr r3, [pc, #276] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
80015d6: 689b ldr r3, [r3, #8]
80015d8: f003 030c and.w r3, r3, #12
80015dc: 2b0c cmp r3, #12
80015de: d1ee bne.n 80015be <HAL_RCC_ClockConfig+0x12a>
80015e0: e027 b.n 8001632 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
80015e2: 687b ldr r3, [r7, #4]
80015e4: 685b ldr r3, [r3, #4]
80015e6: 2b01 cmp r3, #1
80015e8: d11d bne.n 8001626 <HAL_RCC_ClockConfig+0x192>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
80015ea: e00a b.n 8001602 <HAL_RCC_ClockConfig+0x16e>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80015ec: f7ff f96a bl 80008c4 <HAL_GetTick>
80015f0: 4602 mov r2, r0
80015f2: 68fb ldr r3, [r7, #12]
80015f4: 1ad3 subs r3, r2, r3
80015f6: f241 3288 movw r2, #5000 @ 0x1388
80015fa: 4293 cmp r3, r2
80015fc: d901 bls.n 8001602 <HAL_RCC_ClockConfig+0x16e>
{
return HAL_TIMEOUT;
80015fe: 2303 movs r3, #3
8001600: e06d b.n 80016de <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
8001602: 4b3a ldr r3, [pc, #232] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001604: 689b ldr r3, [r3, #8]
8001606: f003 030c and.w r3, r3, #12
800160a: 2b04 cmp r3, #4
800160c: d1ee bne.n 80015ec <HAL_RCC_ClockConfig+0x158>
800160e: e010 b.n 8001632 <HAL_RCC_ClockConfig+0x19e>
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001610: f7ff f958 bl 80008c4 <HAL_GetTick>
8001614: 4602 mov r2, r0
8001616: 68fb ldr r3, [r7, #12]
8001618: 1ad3 subs r3, r2, r3
800161a: f241 3288 movw r2, #5000 @ 0x1388
800161e: 4293 cmp r3, r2
8001620: d901 bls.n 8001626 <HAL_RCC_ClockConfig+0x192>
{
return HAL_TIMEOUT;
8001622: 2303 movs r3, #3
8001624: e05b b.n 80016de <HAL_RCC_ClockConfig+0x24a>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
8001626: 4b31 ldr r3, [pc, #196] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001628: 689b ldr r3, [r3, #8]
800162a: f003 030c and.w r3, r3, #12
800162e: 2b00 cmp r3, #0
8001630: d1ee bne.n 8001610 <HAL_RCC_ClockConfig+0x17c>
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001632: 4b2d ldr r3, [pc, #180] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
8001634: 681b ldr r3, [r3, #0]
8001636: f003 0301 and.w r3, r3, #1
800163a: 683a ldr r2, [r7, #0]
800163c: 429a cmp r2, r3
800163e: d219 bcs.n 8001674 <HAL_RCC_ClockConfig+0x1e0>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001640: 683b ldr r3, [r7, #0]
8001642: 2b01 cmp r3, #1
8001644: d105 bne.n 8001652 <HAL_RCC_ClockConfig+0x1be>
8001646: 4b28 ldr r3, [pc, #160] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
8001648: 681b ldr r3, [r3, #0]
800164a: 4a27 ldr r2, [pc, #156] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
800164c: f043 0304 orr.w r3, r3, #4
8001650: 6013 str r3, [r2, #0]
8001652: 4b25 ldr r3, [pc, #148] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
8001654: 681b ldr r3, [r3, #0]
8001656: f023 0201 bic.w r2, r3, #1
800165a: 4923 ldr r1, [pc, #140] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
800165c: 683b ldr r3, [r7, #0]
800165e: 4313 orrs r3, r2
8001660: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001662: 4b21 ldr r3, [pc, #132] @ (80016e8 <HAL_RCC_ClockConfig+0x254>)
8001664: 681b ldr r3, [r3, #0]
8001666: f003 0301 and.w r3, r3, #1
800166a: 683a ldr r2, [r7, #0]
800166c: 429a cmp r2, r3
800166e: d001 beq.n 8001674 <HAL_RCC_ClockConfig+0x1e0>
{
return HAL_ERROR;
8001670: 2301 movs r3, #1
8001672: e034 b.n 80016de <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001674: 687b ldr r3, [r7, #4]
8001676: 681b ldr r3, [r3, #0]
8001678: f003 0304 and.w r3, r3, #4
800167c: 2b00 cmp r3, #0
800167e: d008 beq.n 8001692 <HAL_RCC_ClockConfig+0x1fe>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001680: 4b1a ldr r3, [pc, #104] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
8001682: 689b ldr r3, [r3, #8]
8001684: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8001688: 687b ldr r3, [r7, #4]
800168a: 68db ldr r3, [r3, #12]
800168c: 4917 ldr r1, [pc, #92] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
800168e: 4313 orrs r3, r2
8001690: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001692: 687b ldr r3, [r7, #4]
8001694: 681b ldr r3, [r3, #0]
8001696: f003 0308 and.w r3, r3, #8
800169a: 2b00 cmp r3, #0
800169c: d009 beq.n 80016b2 <HAL_RCC_ClockConfig+0x21e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
800169e: 4b13 ldr r3, [pc, #76] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
80016a0: 689b ldr r3, [r3, #8]
80016a2: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80016a6: 687b ldr r3, [r7, #4]
80016a8: 691b ldr r3, [r3, #16]
80016aa: 00db lsls r3, r3, #3
80016ac: 490f ldr r1, [pc, #60] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
80016ae: 4313 orrs r3, r2
80016b0: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
80016b2: f000 f823 bl 80016fc <HAL_RCC_GetSysClockFreq>
80016b6: 4602 mov r2, r0
80016b8: 4b0c ldr r3, [pc, #48] @ (80016ec <HAL_RCC_ClockConfig+0x258>)
80016ba: 689b ldr r3, [r3, #8]
80016bc: 091b lsrs r3, r3, #4
80016be: f003 030f and.w r3, r3, #15
80016c2: 490b ldr r1, [pc, #44] @ (80016f0 <HAL_RCC_ClockConfig+0x25c>)
80016c4: 5ccb ldrb r3, [r1, r3]
80016c6: fa22 f303 lsr.w r3, r2, r3
80016ca: 4a0a ldr r2, [pc, #40] @ (80016f4 <HAL_RCC_ClockConfig+0x260>)
80016cc: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
80016ce: 4b0a ldr r3, [pc, #40] @ (80016f8 <HAL_RCC_ClockConfig+0x264>)
80016d0: 681b ldr r3, [r3, #0]
80016d2: 4618 mov r0, r3
80016d4: f7ff f8aa bl 800082c <HAL_InitTick>
80016d8: 4603 mov r3, r0
80016da: 72fb strb r3, [r7, #11]
return status;
80016dc: 7afb ldrb r3, [r7, #11]
}
80016de: 4618 mov r0, r3
80016e0: 3710 adds r7, #16
80016e2: 46bd mov sp, r7
80016e4: bd80 pop {r7, pc}
80016e6: bf00 nop
80016e8: 40023c00 .word 0x40023c00
80016ec: 40023800 .word 0x40023800
80016f0: 080019b4 .word 0x080019b4
80016f4: 20000000 .word 0x20000000
80016f8: 20000004 .word 0x20000004
080016fc <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80016fc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001700: b08e sub sp, #56 @ 0x38
8001702: af00 add r7, sp, #0
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
tmpreg = RCC->CFGR;
8001704: 4b58 ldr r3, [pc, #352] @ (8001868 <HAL_RCC_GetSysClockFreq+0x16c>)
8001706: 689b ldr r3, [r3, #8]
8001708: 62fb str r3, [r7, #44] @ 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800170a: 6afb ldr r3, [r7, #44] @ 0x2c
800170c: f003 030c and.w r3, r3, #12
8001710: 2b0c cmp r3, #12
8001712: d00d beq.n 8001730 <HAL_RCC_GetSysClockFreq+0x34>
8001714: 2b0c cmp r3, #12
8001716: f200 8092 bhi.w 800183e <HAL_RCC_GetSysClockFreq+0x142>
800171a: 2b04 cmp r3, #4
800171c: d002 beq.n 8001724 <HAL_RCC_GetSysClockFreq+0x28>
800171e: 2b08 cmp r3, #8
8001720: d003 beq.n 800172a <HAL_RCC_GetSysClockFreq+0x2e>
8001722: e08c b.n 800183e <HAL_RCC_GetSysClockFreq+0x142>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001724: 4b51 ldr r3, [pc, #324] @ (800186c <HAL_RCC_GetSysClockFreq+0x170>)
8001726: 633b str r3, [r7, #48] @ 0x30
break;
8001728: e097 b.n 800185a <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
800172a: 4b51 ldr r3, [pc, #324] @ (8001870 <HAL_RCC_GetSysClockFreq+0x174>)
800172c: 633b str r3, [r7, #48] @ 0x30
break;
800172e: e094 b.n 800185a <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
8001730: 6afb ldr r3, [r7, #44] @ 0x2c
8001732: 0c9b lsrs r3, r3, #18
8001734: f003 020f and.w r2, r3, #15
8001738: 4b4e ldr r3, [pc, #312] @ (8001874 <HAL_RCC_GetSysClockFreq+0x178>)
800173a: 5c9b ldrb r3, [r3, r2]
800173c: 62bb str r3, [r7, #40] @ 0x28
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
800173e: 6afb ldr r3, [r7, #44] @ 0x2c
8001740: 0d9b lsrs r3, r3, #22
8001742: f003 0303 and.w r3, r3, #3
8001746: 3301 adds r3, #1
8001748: 627b str r3, [r7, #36] @ 0x24
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
800174a: 4b47 ldr r3, [pc, #284] @ (8001868 <HAL_RCC_GetSysClockFreq+0x16c>)
800174c: 689b ldr r3, [r3, #8]
800174e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001752: 2b00 cmp r3, #0
8001754: d021 beq.n 800179a <HAL_RCC_GetSysClockFreq+0x9e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
8001756: 6abb ldr r3, [r7, #40] @ 0x28
8001758: 2200 movs r2, #0
800175a: 61bb str r3, [r7, #24]
800175c: 61fa str r2, [r7, #28]
800175e: 4b44 ldr r3, [pc, #272] @ (8001870 <HAL_RCC_GetSysClockFreq+0x174>)
8001760: e9d7 8906 ldrd r8, r9, [r7, #24]
8001764: 464a mov r2, r9
8001766: fb03 f202 mul.w r2, r3, r2
800176a: 2300 movs r3, #0
800176c: 4644 mov r4, r8
800176e: fb04 f303 mul.w r3, r4, r3
8001772: 4413 add r3, r2
8001774: 4a3e ldr r2, [pc, #248] @ (8001870 <HAL_RCC_GetSysClockFreq+0x174>)
8001776: 4644 mov r4, r8
8001778: fba4 0102 umull r0, r1, r4, r2
800177c: 440b add r3, r1
800177e: 4619 mov r1, r3
8001780: 6a7b ldr r3, [r7, #36] @ 0x24
8001782: 2200 movs r2, #0
8001784: 613b str r3, [r7, #16]
8001786: 617a str r2, [r7, #20]
8001788: e9d7 2304 ldrd r2, r3, [r7, #16]
800178c: f7fe fcf6 bl 800017c <__aeabi_uldivmod>
8001790: 4602 mov r2, r0
8001792: 460b mov r3, r1
8001794: 4613 mov r3, r2
8001796: 637b str r3, [r7, #52] @ 0x34
8001798: e04e b.n 8001838 <HAL_RCC_GetSysClockFreq+0x13c>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
800179a: 6abb ldr r3, [r7, #40] @ 0x28
800179c: 2200 movs r2, #0
800179e: 469a mov sl, r3
80017a0: 4693 mov fp, r2
80017a2: 4652 mov r2, sl
80017a4: 465b mov r3, fp
80017a6: f04f 0000 mov.w r0, #0
80017aa: f04f 0100 mov.w r1, #0
80017ae: 0159 lsls r1, r3, #5
80017b0: ea41 61d2 orr.w r1, r1, r2, lsr #27
80017b4: 0150 lsls r0, r2, #5
80017b6: 4602 mov r2, r0
80017b8: 460b mov r3, r1
80017ba: ebb2 080a subs.w r8, r2, sl
80017be: eb63 090b sbc.w r9, r3, fp
80017c2: f04f 0200 mov.w r2, #0
80017c6: f04f 0300 mov.w r3, #0
80017ca: ea4f 1389 mov.w r3, r9, lsl #6
80017ce: ea43 6398 orr.w r3, r3, r8, lsr #26
80017d2: ea4f 1288 mov.w r2, r8, lsl #6
80017d6: ebb2 0408 subs.w r4, r2, r8
80017da: eb63 0509 sbc.w r5, r3, r9
80017de: f04f 0200 mov.w r2, #0
80017e2: f04f 0300 mov.w r3, #0
80017e6: 00eb lsls r3, r5, #3
80017e8: ea43 7354 orr.w r3, r3, r4, lsr #29
80017ec: 00e2 lsls r2, r4, #3
80017ee: 4614 mov r4, r2
80017f0: 461d mov r5, r3
80017f2: eb14 030a adds.w r3, r4, sl
80017f6: 603b str r3, [r7, #0]
80017f8: eb45 030b adc.w r3, r5, fp
80017fc: 607b str r3, [r7, #4]
80017fe: f04f 0200 mov.w r2, #0
8001802: f04f 0300 mov.w r3, #0
8001806: e9d7 4500 ldrd r4, r5, [r7]
800180a: 4629 mov r1, r5
800180c: 028b lsls r3, r1, #10
800180e: 4620 mov r0, r4
8001810: 4629 mov r1, r5
8001812: 4604 mov r4, r0
8001814: ea43 5394 orr.w r3, r3, r4, lsr #22
8001818: 4601 mov r1, r0
800181a: 028a lsls r2, r1, #10
800181c: 4610 mov r0, r2
800181e: 4619 mov r1, r3
8001820: 6a7b ldr r3, [r7, #36] @ 0x24
8001822: 2200 movs r2, #0
8001824: 60bb str r3, [r7, #8]
8001826: 60fa str r2, [r7, #12]
8001828: e9d7 2302 ldrd r2, r3, [r7, #8]
800182c: f7fe fca6 bl 800017c <__aeabi_uldivmod>
8001830: 4602 mov r2, r0
8001832: 460b mov r3, r1
8001834: 4613 mov r3, r2
8001836: 637b str r3, [r7, #52] @ 0x34
}
sysclockfreq = pllvco;
8001838: 6b7b ldr r3, [r7, #52] @ 0x34
800183a: 633b str r3, [r7, #48] @ 0x30
break;
800183c: e00d b.n 800185a <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
default: /* MSI used as system clock */
{
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
800183e: 4b0a ldr r3, [pc, #40] @ (8001868 <HAL_RCC_GetSysClockFreq+0x16c>)
8001840: 685b ldr r3, [r3, #4]
8001842: 0b5b lsrs r3, r3, #13
8001844: f003 0307 and.w r3, r3, #7
8001848: 623b str r3, [r7, #32]
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
800184a: 6a3b ldr r3, [r7, #32]
800184c: 3301 adds r3, #1
800184e: f44f 4200 mov.w r2, #32768 @ 0x8000
8001852: fa02 f303 lsl.w r3, r2, r3
8001856: 633b str r3, [r7, #48] @ 0x30
break;
8001858: bf00 nop
}
}
return sysclockfreq;
800185a: 6b3b ldr r3, [r7, #48] @ 0x30
}
800185c: 4618 mov r0, r3
800185e: 3738 adds r7, #56 @ 0x38
8001860: 46bd mov sp, r7
8001862: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001866: bf00 nop
8001868: 40023800 .word 0x40023800
800186c: 00f42400 .word 0x00f42400
8001870: 016e3600 .word 0x016e3600
8001874: 080019a8 .word 0x080019a8
08001878 <RCC_SetFlashLatencyFromMSIRange>:
voltage range
* @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
8001878: b480 push {r7}
800187a: b087 sub sp, #28
800187c: af00 add r7, sp, #0
800187e: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8001880: 2300 movs r3, #0
8001882: 613b str r3, [r7, #16]
/* HCLK can reach 4 MHz only if AHB prescaler = 1 */
if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
8001884: 4b29 ldr r3, [pc, #164] @ (800192c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001886: 689b ldr r3, [r3, #8]
8001888: f003 03f0 and.w r3, r3, #240 @ 0xf0
800188c: 2b00 cmp r3, #0
800188e: d12c bne.n 80018ea <RCC_SetFlashLatencyFromMSIRange+0x72>
{
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8001890: 4b26 ldr r3, [pc, #152] @ (800192c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001892: 6a5b ldr r3, [r3, #36] @ 0x24
8001894: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001898: 2b00 cmp r3, #0
800189a: d005 beq.n 80018a8 <RCC_SetFlashLatencyFromMSIRange+0x30>
{
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
800189c: 4b24 ldr r3, [pc, #144] @ (8001930 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
800189e: 681b ldr r3, [r3, #0]
80018a0: f403 53c0 and.w r3, r3, #6144 @ 0x1800
80018a4: 617b str r3, [r7, #20]
80018a6: e016 b.n 80018d6 <RCC_SetFlashLatencyFromMSIRange+0x5e>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
80018a8: 4b20 ldr r3, [pc, #128] @ (800192c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80018aa: 6a5b ldr r3, [r3, #36] @ 0x24
80018ac: 4a1f ldr r2, [pc, #124] @ (800192c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80018ae: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80018b2: 6253 str r3, [r2, #36] @ 0x24
80018b4: 4b1d ldr r3, [pc, #116] @ (800192c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80018b6: 6a5b ldr r3, [r3, #36] @ 0x24
80018b8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80018bc: 60fb str r3, [r7, #12]
80018be: 68fb ldr r3, [r7, #12]
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
80018c0: 4b1b ldr r3, [pc, #108] @ (8001930 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80018c2: 681b ldr r3, [r3, #0]
80018c4: f403 53c0 and.w r3, r3, #6144 @ 0x1800
80018c8: 617b str r3, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
80018ca: 4b18 ldr r3, [pc, #96] @ (800192c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80018cc: 6a5b ldr r3, [r3, #36] @ 0x24
80018ce: 4a17 ldr r2, [pc, #92] @ (800192c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80018d0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80018d4: 6253 str r3, [r2, #36] @ 0x24
}
/* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
80018d6: 697b ldr r3, [r7, #20]
80018d8: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800
80018dc: d105 bne.n 80018ea <RCC_SetFlashLatencyFromMSIRange+0x72>
80018de: 687b ldr r3, [r7, #4]
80018e0: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
80018e4: d101 bne.n 80018ea <RCC_SetFlashLatencyFromMSIRange+0x72>
{
latency = FLASH_LATENCY_1; /* 1WS */
80018e6: 2301 movs r3, #1
80018e8: 613b str r3, [r7, #16]
}
}
__HAL_FLASH_SET_LATENCY(latency);
80018ea: 693b ldr r3, [r7, #16]
80018ec: 2b01 cmp r3, #1
80018ee: d105 bne.n 80018fc <RCC_SetFlashLatencyFromMSIRange+0x84>
80018f0: 4b10 ldr r3, [pc, #64] @ (8001934 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80018f2: 681b ldr r3, [r3, #0]
80018f4: 4a0f ldr r2, [pc, #60] @ (8001934 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80018f6: f043 0304 orr.w r3, r3, #4
80018fa: 6013 str r3, [r2, #0]
80018fc: 4b0d ldr r3, [pc, #52] @ (8001934 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80018fe: 681b ldr r3, [r3, #0]
8001900: f023 0201 bic.w r2, r3, #1
8001904: 490b ldr r1, [pc, #44] @ (8001934 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001906: 693b ldr r3, [r7, #16]
8001908: 4313 orrs r3, r2
800190a: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
800190c: 4b09 ldr r3, [pc, #36] @ (8001934 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
800190e: 681b ldr r3, [r3, #0]
8001910: f003 0301 and.w r3, r3, #1
8001914: 693a ldr r2, [r7, #16]
8001916: 429a cmp r2, r3
8001918: d001 beq.n 800191e <RCC_SetFlashLatencyFromMSIRange+0xa6>
{
return HAL_ERROR;
800191a: 2301 movs r3, #1
800191c: e000 b.n 8001920 <RCC_SetFlashLatencyFromMSIRange+0xa8>
}
return HAL_OK;
800191e: 2300 movs r3, #0
}
8001920: 4618 mov r0, r3
8001922: 371c adds r7, #28
8001924: 46bd mov sp, r7
8001926: bc80 pop {r7}
8001928: 4770 bx lr
800192a: bf00 nop
800192c: 40023800 .word 0x40023800
8001930: 40007000 .word 0x40007000
8001934: 40023c00 .word 0x40023c00
08001938 <memset>:
8001938: 4603 mov r3, r0
800193a: 4402 add r2, r0
800193c: 4293 cmp r3, r2
800193e: d100 bne.n 8001942 <memset+0xa>
8001940: 4770 bx lr
8001942: f803 1b01 strb.w r1, [r3], #1
8001946: e7f9 b.n 800193c <memset+0x4>
08001948 <__libc_init_array>:
8001948: b570 push {r4, r5, r6, lr}
800194a: 2600 movs r6, #0
800194c: 4d0c ldr r5, [pc, #48] @ (8001980 <__libc_init_array+0x38>)
800194e: 4c0d ldr r4, [pc, #52] @ (8001984 <__libc_init_array+0x3c>)
8001950: 1b64 subs r4, r4, r5
8001952: 10a4 asrs r4, r4, #2
8001954: 42a6 cmp r6, r4
8001956: d109 bne.n 800196c <__libc_init_array+0x24>
8001958: f000 f81a bl 8001990 <_init>
800195c: 2600 movs r6, #0
800195e: 4d0a ldr r5, [pc, #40] @ (8001988 <__libc_init_array+0x40>)
8001960: 4c0a ldr r4, [pc, #40] @ (800198c <__libc_init_array+0x44>)
8001962: 1b64 subs r4, r4, r5
8001964: 10a4 asrs r4, r4, #2
8001966: 42a6 cmp r6, r4
8001968: d105 bne.n 8001976 <__libc_init_array+0x2e>
800196a: bd70 pop {r4, r5, r6, pc}
800196c: f855 3b04 ldr.w r3, [r5], #4
8001970: 4798 blx r3
8001972: 3601 adds r6, #1
8001974: e7ee b.n 8001954 <__libc_init_array+0xc>
8001976: f855 3b04 ldr.w r3, [r5], #4
800197a: 4798 blx r3
800197c: 3601 adds r6, #1
800197e: e7f2 b.n 8001966 <__libc_init_array+0x1e>
8001980: 080019cc .word 0x080019cc
8001984: 080019cc .word 0x080019cc
8001988: 080019cc .word 0x080019cc
800198c: 080019d0 .word 0x080019d0
08001990 <_init>:
8001990: b5f8 push {r3, r4, r5, r6, r7, lr}
8001992: bf00 nop
8001994: bcf8 pop {r3, r4, r5, r6, r7}
8001996: bc08 pop {r3}
8001998: 469e mov lr, r3
800199a: 4770 bx lr
0800199c <_fini>:
800199c: b5f8 push {r3, r4, r5, r6, r7, lr}
800199e: bf00 nop
80019a0: bcf8 pop {r3, r4, r5, r6, r7}
80019a2: bc08 pop {r3}
80019a4: 469e mov lr, r3
80019a6: 4770 bx lr
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