BreizhHardware/TP-STM32-CIPA3
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TP-STM32-CIPA3/TP4_INIT_TFT/Debug/TP3_PWM_MOTOR.list

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TP3_PWM_MOTOR.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000036c8 08000140 08000140 00001140 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000002c 08003808 08003808 00004808 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08003834 08003834 00005010 2**0
CONTENTS, READONLY
4 .ARM 00000008 08003834 08003834 00004834 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800383c 0800383c 00005010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800383c 0800383c 0000483c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08003840 08003840 00004840 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000010 20000000 08003844 00005000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000fc 20000010 08003854 00005010 2**2
ALLOC
10 ._user_heap_stack 00000604 2000010c 08003854 0000510c 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 00005010 2**0
CONTENTS, READONLY
12 .debug_info 00009912 00000000 00000000 00005039 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000019e3 00000000 00000000 0000e94b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000aa0 00000000 00000000 00010330 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000812 00000000 00000000 00010dd0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000155f9 00000000 00000000 000115e2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000aade 00000000 00000000 00026bdb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000886db 00000000 00000000 000316b9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000b9d94 2**0
CONTENTS, READONLY
20 .debug_frame 00002cec 00000000 00000000 000b9dd8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000070 00000000 00000000 000bcac4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000140 <__do_global_dtors_aux>:
8000140: b510 push {r4, lr}
8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>)
8000144: 7823 ldrb r3, [r4, #0]
8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16>
8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>)
800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12>
800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>)
800014e: f3af 8000 nop.w
8000152: 2301 movs r3, #1
8000154: 7023 strb r3, [r4, #0]
8000156: bd10 pop {r4, pc}
8000158: 20000010 .word 0x20000010
800015c: 00000000 .word 0x00000000
8000160: 080037f0 .word 0x080037f0
08000164 <frame_dummy>:
8000164: b508 push {r3, lr}
8000166: 4b03 ldr r3, [pc, #12] @ (8000174 <frame_dummy+0x10>)
8000168: b11b cbz r3, 8000172 <frame_dummy+0xe>
800016a: 4903 ldr r1, [pc, #12] @ (8000178 <frame_dummy+0x14>)
800016c: 4803 ldr r0, [pc, #12] @ (800017c <frame_dummy+0x18>)
800016e: f3af 8000 nop.w
8000172: bd08 pop {r3, pc}
8000174: 00000000 .word 0x00000000
8000178: 20000014 .word 0x20000014
800017c: 080037f0 .word 0x080037f0
08000180 <__aeabi_dmul>:
8000180: b570 push {r4, r5, r6, lr}
8000182: f04f 0cff mov.w ip, #255 @ 0xff
8000186: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
800018a: ea1c 5411 ands.w r4, ip, r1, lsr #20
800018e: bf1d ittte ne
8000190: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000194: ea94 0f0c teqne r4, ip
8000198: ea95 0f0c teqne r5, ip
800019c: f000 f8de bleq 800035c <__aeabi_dmul+0x1dc>
80001a0: 442c add r4, r5
80001a2: ea81 0603 eor.w r6, r1, r3
80001a6: ea21 514c bic.w r1, r1, ip, lsl #21
80001aa: ea23 534c bic.w r3, r3, ip, lsl #21
80001ae: ea50 3501 orrs.w r5, r0, r1, lsl #12
80001b2: bf18 it ne
80001b4: ea52 3503 orrsne.w r5, r2, r3, lsl #12
80001b8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80001bc: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80001c0: d038 beq.n 8000234 <__aeabi_dmul+0xb4>
80001c2: fba0 ce02 umull ip, lr, r0, r2
80001c6: f04f 0500 mov.w r5, #0
80001ca: fbe1 e502 umlal lr, r5, r1, r2
80001ce: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
80001d2: fbe0 e503 umlal lr, r5, r0, r3
80001d6: f04f 0600 mov.w r6, #0
80001da: fbe1 5603 umlal r5, r6, r1, r3
80001de: f09c 0f00 teq ip, #0
80001e2: bf18 it ne
80001e4: f04e 0e01 orrne.w lr, lr, #1
80001e8: f1a4 04ff sub.w r4, r4, #255 @ 0xff
80001ec: f5b6 7f00 cmp.w r6, #512 @ 0x200
80001f0: f564 7440 sbc.w r4, r4, #768 @ 0x300
80001f4: d204 bcs.n 8000200 <__aeabi_dmul+0x80>
80001f6: ea5f 0e4e movs.w lr, lr, lsl #1
80001fa: 416d adcs r5, r5
80001fc: eb46 0606 adc.w r6, r6, r6
8000200: ea42 21c6 orr.w r1, r2, r6, lsl #11
8000204: ea41 5155 orr.w r1, r1, r5, lsr #21
8000208: ea4f 20c5 mov.w r0, r5, lsl #11
800020c: ea40 505e orr.w r0, r0, lr, lsr #21
8000210: ea4f 2ece mov.w lr, lr, lsl #11
8000214: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
8000218: bf88 it hi
800021a: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
800021e: d81e bhi.n 800025e <__aeabi_dmul+0xde>
8000220: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
8000224: bf08 it eq
8000226: ea5f 0e50 movseq.w lr, r0, lsr #1
800022a: f150 0000 adcs.w r0, r0, #0
800022e: eb41 5104 adc.w r1, r1, r4, lsl #20
8000232: bd70 pop {r4, r5, r6, pc}
8000234: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
8000238: ea46 0101 orr.w r1, r6, r1
800023c: ea40 0002 orr.w r0, r0, r2
8000240: ea81 0103 eor.w r1, r1, r3
8000244: ebb4 045c subs.w r4, r4, ip, lsr #1
8000248: bfc2 ittt gt
800024a: ebd4 050c rsbsgt r5, r4, ip
800024e: ea41 5104 orrgt.w r1, r1, r4, lsl #20
8000252: bd70 popgt {r4, r5, r6, pc}
8000254: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000258: f04f 0e00 mov.w lr, #0
800025c: 3c01 subs r4, #1
800025e: f300 80ab bgt.w 80003b8 <__aeabi_dmul+0x238>
8000262: f114 0f36 cmn.w r4, #54 @ 0x36
8000266: bfde ittt le
8000268: 2000 movle r0, #0
800026a: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
800026e: bd70 pople {r4, r5, r6, pc}
8000270: f1c4 0400 rsb r4, r4, #0
8000274: 3c20 subs r4, #32
8000276: da35 bge.n 80002e4 <__aeabi_dmul+0x164>
8000278: 340c adds r4, #12
800027a: dc1b bgt.n 80002b4 <__aeabi_dmul+0x134>
800027c: f104 0414 add.w r4, r4, #20
8000280: f1c4 0520 rsb r5, r4, #32
8000284: fa00 f305 lsl.w r3, r0, r5
8000288: fa20 f004 lsr.w r0, r0, r4
800028c: fa01 f205 lsl.w r2, r1, r5
8000290: ea40 0002 orr.w r0, r0, r2
8000294: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000298: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
800029c: eb10 70d3 adds.w r0, r0, r3, lsr #31
80002a0: fa21 f604 lsr.w r6, r1, r4
80002a4: eb42 0106 adc.w r1, r2, r6
80002a8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002ac: bf08 it eq
80002ae: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002b2: bd70 pop {r4, r5, r6, pc}
80002b4: f1c4 040c rsb r4, r4, #12
80002b8: f1c4 0520 rsb r5, r4, #32
80002bc: fa00 f304 lsl.w r3, r0, r4
80002c0: fa20 f005 lsr.w r0, r0, r5
80002c4: fa01 f204 lsl.w r2, r1, r4
80002c8: ea40 0002 orr.w r0, r0, r2
80002cc: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80002d0: eb10 70d3 adds.w r0, r0, r3, lsr #31
80002d4: f141 0100 adc.w r1, r1, #0
80002d8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
80002dc: bf08 it eq
80002de: ea20 70d3 biceq.w r0, r0, r3, lsr #31
80002e2: bd70 pop {r4, r5, r6, pc}
80002e4: f1c4 0520 rsb r5, r4, #32
80002e8: fa00 f205 lsl.w r2, r0, r5
80002ec: ea4e 0e02 orr.w lr, lr, r2
80002f0: fa20 f304 lsr.w r3, r0, r4
80002f4: fa01 f205 lsl.w r2, r1, r5
80002f8: ea43 0302 orr.w r3, r3, r2
80002fc: fa21 f004 lsr.w r0, r1, r4
8000300: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000304: fa21 f204 lsr.w r2, r1, r4
8000308: ea20 0002 bic.w r0, r0, r2
800030c: eb00 70d3 add.w r0, r0, r3, lsr #31
8000310: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000314: bf08 it eq
8000316: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800031a: bd70 pop {r4, r5, r6, pc}
800031c: f094 0f00 teq r4, #0
8000320: d10f bne.n 8000342 <__aeabi_dmul+0x1c2>
8000322: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
8000326: 0040 lsls r0, r0, #1
8000328: eb41 0101 adc.w r1, r1, r1
800032c: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000330: bf08 it eq
8000332: 3c01 subeq r4, #1
8000334: d0f7 beq.n 8000326 <__aeabi_dmul+0x1a6>
8000336: ea41 0106 orr.w r1, r1, r6
800033a: f095 0f00 teq r5, #0
800033e: bf18 it ne
8000340: 4770 bxne lr
8000342: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
8000346: 0052 lsls r2, r2, #1
8000348: eb43 0303 adc.w r3, r3, r3
800034c: f413 1f80 tst.w r3, #1048576 @ 0x100000
8000350: bf08 it eq
8000352: 3d01 subeq r5, #1
8000354: d0f7 beq.n 8000346 <__aeabi_dmul+0x1c6>
8000356: ea43 0306 orr.w r3, r3, r6
800035a: 4770 bx lr
800035c: ea94 0f0c teq r4, ip
8000360: ea0c 5513 and.w r5, ip, r3, lsr #20
8000364: bf18 it ne
8000366: ea95 0f0c teqne r5, ip
800036a: d00c beq.n 8000386 <__aeabi_dmul+0x206>
800036c: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000370: bf18 it ne
8000372: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000376: d1d1 bne.n 800031c <__aeabi_dmul+0x19c>
8000378: ea81 0103 eor.w r1, r1, r3
800037c: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000380: f04f 0000 mov.w r0, #0
8000384: bd70 pop {r4, r5, r6, pc}
8000386: ea50 0641 orrs.w r6, r0, r1, lsl #1
800038a: bf06 itte eq
800038c: 4610 moveq r0, r2
800038e: 4619 moveq r1, r3
8000390: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000394: d019 beq.n 80003ca <__aeabi_dmul+0x24a>
8000396: ea94 0f0c teq r4, ip
800039a: d102 bne.n 80003a2 <__aeabi_dmul+0x222>
800039c: ea50 3601 orrs.w r6, r0, r1, lsl #12
80003a0: d113 bne.n 80003ca <__aeabi_dmul+0x24a>
80003a2: ea95 0f0c teq r5, ip
80003a6: d105 bne.n 80003b4 <__aeabi_dmul+0x234>
80003a8: ea52 3603 orrs.w r6, r2, r3, lsl #12
80003ac: bf1c itt ne
80003ae: 4610 movne r0, r2
80003b0: 4619 movne r1, r3
80003b2: d10a bne.n 80003ca <__aeabi_dmul+0x24a>
80003b4: ea81 0103 eor.w r1, r1, r3
80003b8: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80003bc: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80003c0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80003c4: f04f 0000 mov.w r0, #0
80003c8: bd70 pop {r4, r5, r6, pc}
80003ca: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
80003ce: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
80003d2: bd70 pop {r4, r5, r6, pc}
080003d4 <__aeabi_drsub>:
80003d4: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
80003d8: e002 b.n 80003e0 <__adddf3>
80003da: bf00 nop
080003dc <__aeabi_dsub>:
80003dc: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
080003e0 <__adddf3>:
80003e0: b530 push {r4, r5, lr}
80003e2: ea4f 0441 mov.w r4, r1, lsl #1
80003e6: ea4f 0543 mov.w r5, r3, lsl #1
80003ea: ea94 0f05 teq r4, r5
80003ee: bf08 it eq
80003f0: ea90 0f02 teqeq r0, r2
80003f4: bf1f itttt ne
80003f6: ea54 0c00 orrsne.w ip, r4, r0
80003fa: ea55 0c02 orrsne.w ip, r5, r2
80003fe: ea7f 5c64 mvnsne.w ip, r4, asr #21
8000402: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000406: f000 80e2 beq.w 80005ce <__adddf3+0x1ee>
800040a: ea4f 5454 mov.w r4, r4, lsr #21
800040e: ebd4 5555 rsbs r5, r4, r5, lsr #21
8000412: bfb8 it lt
8000414: 426d neglt r5, r5
8000416: dd0c ble.n 8000432 <__adddf3+0x52>
8000418: 442c add r4, r5
800041a: ea80 0202 eor.w r2, r0, r2
800041e: ea81 0303 eor.w r3, r1, r3
8000422: ea82 0000 eor.w r0, r2, r0
8000426: ea83 0101 eor.w r1, r3, r1
800042a: ea80 0202 eor.w r2, r0, r2
800042e: ea81 0303 eor.w r3, r1, r3
8000432: 2d36 cmp r5, #54 @ 0x36
8000434: bf88 it hi
8000436: bd30 pophi {r4, r5, pc}
8000438: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
800043c: ea4f 3101 mov.w r1, r1, lsl #12
8000440: f44f 1c80 mov.w ip, #1048576 @ 0x100000
8000444: ea4c 3111 orr.w r1, ip, r1, lsr #12
8000448: d002 beq.n 8000450 <__adddf3+0x70>
800044a: 4240 negs r0, r0
800044c: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000450: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000454: ea4f 3303 mov.w r3, r3, lsl #12
8000458: ea4c 3313 orr.w r3, ip, r3, lsr #12
800045c: d002 beq.n 8000464 <__adddf3+0x84>
800045e: 4252 negs r2, r2
8000460: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000464: ea94 0f05 teq r4, r5
8000468: f000 80a7 beq.w 80005ba <__adddf3+0x1da>
800046c: f1a4 0401 sub.w r4, r4, #1
8000470: f1d5 0e20 rsbs lr, r5, #32
8000474: db0d blt.n 8000492 <__adddf3+0xb2>
8000476: fa02 fc0e lsl.w ip, r2, lr
800047a: fa22 f205 lsr.w r2, r2, r5
800047e: 1880 adds r0, r0, r2
8000480: f141 0100 adc.w r1, r1, #0
8000484: fa03 f20e lsl.w r2, r3, lr
8000488: 1880 adds r0, r0, r2
800048a: fa43 f305 asr.w r3, r3, r5
800048e: 4159 adcs r1, r3
8000490: e00e b.n 80004b0 <__adddf3+0xd0>
8000492: f1a5 0520 sub.w r5, r5, #32
8000496: f10e 0e20 add.w lr, lr, #32
800049a: 2a01 cmp r2, #1
800049c: fa03 fc0e lsl.w ip, r3, lr
80004a0: bf28 it cs
80004a2: f04c 0c02 orrcs.w ip, ip, #2
80004a6: fa43 f305 asr.w r3, r3, r5
80004aa: 18c0 adds r0, r0, r3
80004ac: eb51 71e3 adcs.w r1, r1, r3, asr #31
80004b0: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80004b4: d507 bpl.n 80004c6 <__adddf3+0xe6>
80004b6: f04f 0e00 mov.w lr, #0
80004ba: f1dc 0c00 rsbs ip, ip, #0
80004be: eb7e 0000 sbcs.w r0, lr, r0
80004c2: eb6e 0101 sbc.w r1, lr, r1
80004c6: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
80004ca: d31b bcc.n 8000504 <__adddf3+0x124>
80004cc: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
80004d0: d30c bcc.n 80004ec <__adddf3+0x10c>
80004d2: 0849 lsrs r1, r1, #1
80004d4: ea5f 0030 movs.w r0, r0, rrx
80004d8: ea4f 0c3c mov.w ip, ip, rrx
80004dc: f104 0401 add.w r4, r4, #1
80004e0: ea4f 5244 mov.w r2, r4, lsl #21
80004e4: f512 0f80 cmn.w r2, #4194304 @ 0x400000
80004e8: f080 809a bcs.w 8000620 <__adddf3+0x240>
80004ec: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
80004f0: bf08 it eq
80004f2: ea5f 0c50 movseq.w ip, r0, lsr #1
80004f6: f150 0000 adcs.w r0, r0, #0
80004fa: eb41 5104 adc.w r1, r1, r4, lsl #20
80004fe: ea41 0105 orr.w r1, r1, r5
8000502: bd30 pop {r4, r5, pc}
8000504: ea5f 0c4c movs.w ip, ip, lsl #1
8000508: 4140 adcs r0, r0
800050a: eb41 0101 adc.w r1, r1, r1
800050e: 3c01 subs r4, #1
8000510: bf28 it cs
8000512: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
8000516: d2e9 bcs.n 80004ec <__adddf3+0x10c>
8000518: f091 0f00 teq r1, #0
800051c: bf04 itt eq
800051e: 4601 moveq r1, r0
8000520: 2000 moveq r0, #0
8000522: fab1 f381 clz r3, r1
8000526: bf08 it eq
8000528: 3320 addeq r3, #32
800052a: f1a3 030b sub.w r3, r3, #11
800052e: f1b3 0220 subs.w r2, r3, #32
8000532: da0c bge.n 800054e <__adddf3+0x16e>
8000534: 320c adds r2, #12
8000536: dd08 ble.n 800054a <__adddf3+0x16a>
8000538: f102 0c14 add.w ip, r2, #20
800053c: f1c2 020c rsb r2, r2, #12
8000540: fa01 f00c lsl.w r0, r1, ip
8000544: fa21 f102 lsr.w r1, r1, r2
8000548: e00c b.n 8000564 <__adddf3+0x184>
800054a: f102 0214 add.w r2, r2, #20
800054e: bfd8 it le
8000550: f1c2 0c20 rsble ip, r2, #32
8000554: fa01 f102 lsl.w r1, r1, r2
8000558: fa20 fc0c lsr.w ip, r0, ip
800055c: bfdc itt le
800055e: ea41 010c orrle.w r1, r1, ip
8000562: 4090 lslle r0, r2
8000564: 1ae4 subs r4, r4, r3
8000566: bfa2 ittt ge
8000568: eb01 5104 addge.w r1, r1, r4, lsl #20
800056c: 4329 orrge r1, r5
800056e: bd30 popge {r4, r5, pc}
8000570: ea6f 0404 mvn.w r4, r4
8000574: 3c1f subs r4, #31
8000576: da1c bge.n 80005b2 <__adddf3+0x1d2>
8000578: 340c adds r4, #12
800057a: dc0e bgt.n 800059a <__adddf3+0x1ba>
800057c: f104 0414 add.w r4, r4, #20
8000580: f1c4 0220 rsb r2, r4, #32
8000584: fa20 f004 lsr.w r0, r0, r4
8000588: fa01 f302 lsl.w r3, r1, r2
800058c: ea40 0003 orr.w r0, r0, r3
8000590: fa21 f304 lsr.w r3, r1, r4
8000594: ea45 0103 orr.w r1, r5, r3
8000598: bd30 pop {r4, r5, pc}
800059a: f1c4 040c rsb r4, r4, #12
800059e: f1c4 0220 rsb r2, r4, #32
80005a2: fa20 f002 lsr.w r0, r0, r2
80005a6: fa01 f304 lsl.w r3, r1, r4
80005aa: ea40 0003 orr.w r0, r0, r3
80005ae: 4629 mov r1, r5
80005b0: bd30 pop {r4, r5, pc}
80005b2: fa21 f004 lsr.w r0, r1, r4
80005b6: 4629 mov r1, r5
80005b8: bd30 pop {r4, r5, pc}
80005ba: f094 0f00 teq r4, #0
80005be: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
80005c2: bf06 itte eq
80005c4: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
80005c8: 3401 addeq r4, #1
80005ca: 3d01 subne r5, #1
80005cc: e74e b.n 800046c <__adddf3+0x8c>
80005ce: ea7f 5c64 mvns.w ip, r4, asr #21
80005d2: bf18 it ne
80005d4: ea7f 5c65 mvnsne.w ip, r5, asr #21
80005d8: d029 beq.n 800062e <__adddf3+0x24e>
80005da: ea94 0f05 teq r4, r5
80005de: bf08 it eq
80005e0: ea90 0f02 teqeq r0, r2
80005e4: d005 beq.n 80005f2 <__adddf3+0x212>
80005e6: ea54 0c00 orrs.w ip, r4, r0
80005ea: bf04 itt eq
80005ec: 4619 moveq r1, r3
80005ee: 4610 moveq r0, r2
80005f0: bd30 pop {r4, r5, pc}
80005f2: ea91 0f03 teq r1, r3
80005f6: bf1e ittt ne
80005f8: 2100 movne r1, #0
80005fa: 2000 movne r0, #0
80005fc: bd30 popne {r4, r5, pc}
80005fe: ea5f 5c54 movs.w ip, r4, lsr #21
8000602: d105 bne.n 8000610 <__adddf3+0x230>
8000604: 0040 lsls r0, r0, #1
8000606: 4149 adcs r1, r1
8000608: bf28 it cs
800060a: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
800060e: bd30 pop {r4, r5, pc}
8000610: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
8000614: bf3c itt cc
8000616: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
800061a: bd30 popcc {r4, r5, pc}
800061c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000620: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
8000624: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
8000628: f04f 0000 mov.w r0, #0
800062c: bd30 pop {r4, r5, pc}
800062e: ea7f 5c64 mvns.w ip, r4, asr #21
8000632: bf1a itte ne
8000634: 4619 movne r1, r3
8000636: 4610 movne r0, r2
8000638: ea7f 5c65 mvnseq.w ip, r5, asr #21
800063c: bf1c itt ne
800063e: 460b movne r3, r1
8000640: 4602 movne r2, r0
8000642: ea50 3401 orrs.w r4, r0, r1, lsl #12
8000646: bf06 itte eq
8000648: ea52 3503 orrseq.w r5, r2, r3, lsl #12
800064c: ea91 0f03 teqeq r1, r3
8000650: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000654: bd30 pop {r4, r5, pc}
8000656: bf00 nop
08000658 <__aeabi_ui2d>:
8000658: f090 0f00 teq r0, #0
800065c: bf04 itt eq
800065e: 2100 moveq r1, #0
8000660: 4770 bxeq lr
8000662: b530 push {r4, r5, lr}
8000664: f44f 6480 mov.w r4, #1024 @ 0x400
8000668: f104 0432 add.w r4, r4, #50 @ 0x32
800066c: f04f 0500 mov.w r5, #0
8000670: f04f 0100 mov.w r1, #0
8000674: e750 b.n 8000518 <__adddf3+0x138>
8000676: bf00 nop
08000678 <__aeabi_i2d>:
8000678: f090 0f00 teq r0, #0
800067c: bf04 itt eq
800067e: 2100 moveq r1, #0
8000680: 4770 bxeq lr
8000682: b530 push {r4, r5, lr}
8000684: f44f 6480 mov.w r4, #1024 @ 0x400
8000688: f104 0432 add.w r4, r4, #50 @ 0x32
800068c: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
8000690: bf48 it mi
8000692: 4240 negmi r0, r0
8000694: f04f 0100 mov.w r1, #0
8000698: e73e b.n 8000518 <__adddf3+0x138>
800069a: bf00 nop
0800069c <__aeabi_f2d>:
800069c: 0042 lsls r2, r0, #1
800069e: ea4f 01e2 mov.w r1, r2, asr #3
80006a2: ea4f 0131 mov.w r1, r1, rrx
80006a6: ea4f 7002 mov.w r0, r2, lsl #28
80006aa: bf1f itttt ne
80006ac: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
80006b0: f093 4f7f teqne r3, #4278190080 @ 0xff000000
80006b4: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
80006b8: 4770 bxne lr
80006ba: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
80006be: bf08 it eq
80006c0: 4770 bxeq lr
80006c2: f093 4f7f teq r3, #4278190080 @ 0xff000000
80006c6: bf04 itt eq
80006c8: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
80006cc: 4770 bxeq lr
80006ce: b530 push {r4, r5, lr}
80006d0: f44f 7460 mov.w r4, #896 @ 0x380
80006d4: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80006d8: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
80006dc: e71c b.n 8000518 <__adddf3+0x138>
80006de: bf00 nop
080006e0 <__aeabi_ul2d>:
80006e0: ea50 0201 orrs.w r2, r0, r1
80006e4: bf08 it eq
80006e6: 4770 bxeq lr
80006e8: b530 push {r4, r5, lr}
80006ea: f04f 0500 mov.w r5, #0
80006ee: e00a b.n 8000706 <__aeabi_l2d+0x16>
080006f0 <__aeabi_l2d>:
80006f0: ea50 0201 orrs.w r2, r0, r1
80006f4: bf08 it eq
80006f6: 4770 bxeq lr
80006f8: b530 push {r4, r5, lr}
80006fa: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80006fe: d502 bpl.n 8000706 <__aeabi_l2d+0x16>
8000700: 4240 negs r0, r0
8000702: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000706: f44f 6480 mov.w r4, #1024 @ 0x400
800070a: f104 0432 add.w r4, r4, #50 @ 0x32
800070e: ea5f 5c91 movs.w ip, r1, lsr #22
8000712: f43f aed8 beq.w 80004c6 <__adddf3+0xe6>
8000716: f04f 0203 mov.w r2, #3
800071a: ea5f 0cdc movs.w ip, ip, lsr #3
800071e: bf18 it ne
8000720: 3203 addne r2, #3
8000722: ea5f 0cdc movs.w ip, ip, lsr #3
8000726: bf18 it ne
8000728: 3203 addne r2, #3
800072a: eb02 02dc add.w r2, r2, ip, lsr #3
800072e: f1c2 0320 rsb r3, r2, #32
8000732: fa00 fc03 lsl.w ip, r0, r3
8000736: fa20 f002 lsr.w r0, r0, r2
800073a: fa01 fe03 lsl.w lr, r1, r3
800073e: ea40 000e orr.w r0, r0, lr
8000742: fa21 f102 lsr.w r1, r1, r2
8000746: 4414 add r4, r2
8000748: e6bd b.n 80004c6 <__adddf3+0xe6>
800074a: bf00 nop
0800074c <__aeabi_d2uiz>:
800074c: 004a lsls r2, r1, #1
800074e: d211 bcs.n 8000774 <__aeabi_d2uiz+0x28>
8000750: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000754: d211 bcs.n 800077a <__aeabi_d2uiz+0x2e>
8000756: d50d bpl.n 8000774 <__aeabi_d2uiz+0x28>
8000758: f46f 7378 mvn.w r3, #992 @ 0x3e0
800075c: ebb3 5262 subs.w r2, r3, r2, asr #21
8000760: d40e bmi.n 8000780 <__aeabi_d2uiz+0x34>
8000762: ea4f 23c1 mov.w r3, r1, lsl #11
8000766: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
800076a: ea43 5350 orr.w r3, r3, r0, lsr #21
800076e: fa23 f002 lsr.w r0, r3, r2
8000772: 4770 bx lr
8000774: f04f 0000 mov.w r0, #0
8000778: 4770 bx lr
800077a: ea50 3001 orrs.w r0, r0, r1, lsl #12
800077e: d102 bne.n 8000786 <__aeabi_d2uiz+0x3a>
8000780: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000784: 4770 bx lr
8000786: f04f 0000 mov.w r0, #0
800078a: 4770 bx lr
0800078c <__aeabi_uldivmod>:
800078c: b953 cbnz r3, 80007a4 <__aeabi_uldivmod+0x18>
800078e: b94a cbnz r2, 80007a4 <__aeabi_uldivmod+0x18>
8000790: 2900 cmp r1, #0
8000792: bf08 it eq
8000794: 2800 cmpeq r0, #0
8000796: bf1c itt ne
8000798: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
800079c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
80007a0: f000 b98c b.w 8000abc <__aeabi_idiv0>
80007a4: f1ad 0c08 sub.w ip, sp, #8
80007a8: e96d ce04 strd ip, lr, [sp, #-16]!
80007ac: f000 f806 bl 80007bc <__udivmoddi4>
80007b0: f8dd e004 ldr.w lr, [sp, #4]
80007b4: e9dd 2302 ldrd r2, r3, [sp, #8]
80007b8: b004 add sp, #16
80007ba: 4770 bx lr
080007bc <__udivmoddi4>:
80007bc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80007c0: 9d08 ldr r5, [sp, #32]
80007c2: 468e mov lr, r1
80007c4: 4604 mov r4, r0
80007c6: 4688 mov r8, r1
80007c8: 2b00 cmp r3, #0
80007ca: d14a bne.n 8000862 <__udivmoddi4+0xa6>
80007cc: 428a cmp r2, r1
80007ce: 4617 mov r7, r2
80007d0: d962 bls.n 8000898 <__udivmoddi4+0xdc>
80007d2: fab2 f682 clz r6, r2
80007d6: b14e cbz r6, 80007ec <__udivmoddi4+0x30>
80007d8: f1c6 0320 rsb r3, r6, #32
80007dc: fa01 f806 lsl.w r8, r1, r6
80007e0: fa20 f303 lsr.w r3, r0, r3
80007e4: 40b7 lsls r7, r6
80007e6: ea43 0808 orr.w r8, r3, r8
80007ea: 40b4 lsls r4, r6
80007ec: ea4f 4e17 mov.w lr, r7, lsr #16
80007f0: fbb8 f1fe udiv r1, r8, lr
80007f4: fa1f fc87 uxth.w ip, r7
80007f8: fb0e 8811 mls r8, lr, r1, r8
80007fc: fb01 f20c mul.w r2, r1, ip
8000800: 0c23 lsrs r3, r4, #16
8000802: ea43 4308 orr.w r3, r3, r8, lsl #16
8000806: 429a cmp r2, r3
8000808: d909 bls.n 800081e <__udivmoddi4+0x62>
800080a: 18fb adds r3, r7, r3
800080c: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000810: f080 80eb bcs.w 80009ea <__udivmoddi4+0x22e>
8000814: 429a cmp r2, r3
8000816: f240 80e8 bls.w 80009ea <__udivmoddi4+0x22e>
800081a: 3902 subs r1, #2
800081c: 443b add r3, r7
800081e: 1a9a subs r2, r3, r2
8000820: fbb2 f0fe udiv r0, r2, lr
8000824: fb0e 2210 mls r2, lr, r0, r2
8000828: fb00 fc0c mul.w ip, r0, ip
800082c: b2a3 uxth r3, r4
800082e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000832: 459c cmp ip, r3
8000834: d909 bls.n 800084a <__udivmoddi4+0x8e>
8000836: 18fb adds r3, r7, r3
8000838: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
800083c: f080 80d7 bcs.w 80009ee <__udivmoddi4+0x232>
8000840: 459c cmp ip, r3
8000842: f240 80d4 bls.w 80009ee <__udivmoddi4+0x232>
8000846: 443b add r3, r7
8000848: 3802 subs r0, #2
800084a: ea40 4001 orr.w r0, r0, r1, lsl #16
800084e: 2100 movs r1, #0
8000850: eba3 030c sub.w r3, r3, ip
8000854: b11d cbz r5, 800085e <__udivmoddi4+0xa2>
8000856: 2200 movs r2, #0
8000858: 40f3 lsrs r3, r6
800085a: e9c5 3200 strd r3, r2, [r5]
800085e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000862: 428b cmp r3, r1
8000864: d905 bls.n 8000872 <__udivmoddi4+0xb6>
8000866: b10d cbz r5, 800086c <__udivmoddi4+0xb0>
8000868: e9c5 0100 strd r0, r1, [r5]
800086c: 2100 movs r1, #0
800086e: 4608 mov r0, r1
8000870: e7f5 b.n 800085e <__udivmoddi4+0xa2>
8000872: fab3 f183 clz r1, r3
8000876: 2900 cmp r1, #0
8000878: d146 bne.n 8000908 <__udivmoddi4+0x14c>
800087a: 4573 cmp r3, lr
800087c: d302 bcc.n 8000884 <__udivmoddi4+0xc8>
800087e: 4282 cmp r2, r0
8000880: f200 8108 bhi.w 8000a94 <__udivmoddi4+0x2d8>
8000884: 1a84 subs r4, r0, r2
8000886: eb6e 0203 sbc.w r2, lr, r3
800088a: 2001 movs r0, #1
800088c: 4690 mov r8, r2
800088e: 2d00 cmp r5, #0
8000890: d0e5 beq.n 800085e <__udivmoddi4+0xa2>
8000892: e9c5 4800 strd r4, r8, [r5]
8000896: e7e2 b.n 800085e <__udivmoddi4+0xa2>
8000898: 2a00 cmp r2, #0
800089a: f000 8091 beq.w 80009c0 <__udivmoddi4+0x204>
800089e: fab2 f682 clz r6, r2
80008a2: 2e00 cmp r6, #0
80008a4: f040 80a5 bne.w 80009f2 <__udivmoddi4+0x236>
80008a8: 1a8a subs r2, r1, r2
80008aa: 2101 movs r1, #1
80008ac: 0c03 lsrs r3, r0, #16
80008ae: ea4f 4e17 mov.w lr, r7, lsr #16
80008b2: b280 uxth r0, r0
80008b4: b2bc uxth r4, r7
80008b6: fbb2 fcfe udiv ip, r2, lr
80008ba: fb0e 221c mls r2, lr, ip, r2
80008be: ea43 4302 orr.w r3, r3, r2, lsl #16
80008c2: fb04 f20c mul.w r2, r4, ip
80008c6: 429a cmp r2, r3
80008c8: d907 bls.n 80008da <__udivmoddi4+0x11e>
80008ca: 18fb adds r3, r7, r3
80008cc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
80008d0: d202 bcs.n 80008d8 <__udivmoddi4+0x11c>
80008d2: 429a cmp r2, r3
80008d4: f200 80e3 bhi.w 8000a9e <__udivmoddi4+0x2e2>
80008d8: 46c4 mov ip, r8
80008da: 1a9b subs r3, r3, r2
80008dc: fbb3 f2fe udiv r2, r3, lr
80008e0: fb0e 3312 mls r3, lr, r2, r3
80008e4: fb02 f404 mul.w r4, r2, r4
80008e8: ea40 4303 orr.w r3, r0, r3, lsl #16
80008ec: 429c cmp r4, r3
80008ee: d907 bls.n 8000900 <__udivmoddi4+0x144>
80008f0: 18fb adds r3, r7, r3
80008f2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
80008f6: d202 bcs.n 80008fe <__udivmoddi4+0x142>
80008f8: 429c cmp r4, r3
80008fa: f200 80cd bhi.w 8000a98 <__udivmoddi4+0x2dc>
80008fe: 4602 mov r2, r0
8000900: 1b1b subs r3, r3, r4
8000902: ea42 400c orr.w r0, r2, ip, lsl #16
8000906: e7a5 b.n 8000854 <__udivmoddi4+0x98>
8000908: f1c1 0620 rsb r6, r1, #32
800090c: 408b lsls r3, r1
800090e: fa22 f706 lsr.w r7, r2, r6
8000912: 431f orrs r7, r3
8000914: fa2e fa06 lsr.w sl, lr, r6
8000918: ea4f 4917 mov.w r9, r7, lsr #16
800091c: fbba f8f9 udiv r8, sl, r9
8000920: fa0e fe01 lsl.w lr, lr, r1
8000924: fa20 f306 lsr.w r3, r0, r6
8000928: fb09 aa18 mls sl, r9, r8, sl
800092c: fa1f fc87 uxth.w ip, r7
8000930: ea43 030e orr.w r3, r3, lr
8000934: fa00 fe01 lsl.w lr, r0, r1
8000938: fb08 f00c mul.w r0, r8, ip
800093c: 0c1c lsrs r4, r3, #16
800093e: ea44 440a orr.w r4, r4, sl, lsl #16
8000942: 42a0 cmp r0, r4
8000944: fa02 f201 lsl.w r2, r2, r1
8000948: d90a bls.n 8000960 <__udivmoddi4+0x1a4>
800094a: 193c adds r4, r7, r4
800094c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff
8000950: f080 809e bcs.w 8000a90 <__udivmoddi4+0x2d4>
8000954: 42a0 cmp r0, r4
8000956: f240 809b bls.w 8000a90 <__udivmoddi4+0x2d4>
800095a: f1a8 0802 sub.w r8, r8, #2
800095e: 443c add r4, r7
8000960: 1a24 subs r4, r4, r0
8000962: b298 uxth r0, r3
8000964: fbb4 f3f9 udiv r3, r4, r9
8000968: fb09 4413 mls r4, r9, r3, r4
800096c: fb03 fc0c mul.w ip, r3, ip
8000970: ea40 4404 orr.w r4, r0, r4, lsl #16
8000974: 45a4 cmp ip, r4
8000976: d909 bls.n 800098c <__udivmoddi4+0x1d0>
8000978: 193c adds r4, r7, r4
800097a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff
800097e: f080 8085 bcs.w 8000a8c <__udivmoddi4+0x2d0>
8000982: 45a4 cmp ip, r4
8000984: f240 8082 bls.w 8000a8c <__udivmoddi4+0x2d0>
8000988: 3b02 subs r3, #2
800098a: 443c add r4, r7
800098c: ea43 4008 orr.w r0, r3, r8, lsl #16
8000990: eba4 040c sub.w r4, r4, ip
8000994: fba0 8c02 umull r8, ip, r0, r2
8000998: 4564 cmp r4, ip
800099a: 4643 mov r3, r8
800099c: 46e1 mov r9, ip
800099e: d364 bcc.n 8000a6a <__udivmoddi4+0x2ae>
80009a0: d061 beq.n 8000a66 <__udivmoddi4+0x2aa>
80009a2: b15d cbz r5, 80009bc <__udivmoddi4+0x200>
80009a4: ebbe 0203 subs.w r2, lr, r3
80009a8: eb64 0409 sbc.w r4, r4, r9
80009ac: fa04 f606 lsl.w r6, r4, r6
80009b0: fa22 f301 lsr.w r3, r2, r1
80009b4: 431e orrs r6, r3
80009b6: 40cc lsrs r4, r1
80009b8: e9c5 6400 strd r6, r4, [r5]
80009bc: 2100 movs r1, #0
80009be: e74e b.n 800085e <__udivmoddi4+0xa2>
80009c0: fbb1 fcf2 udiv ip, r1, r2
80009c4: 0c01 lsrs r1, r0, #16
80009c6: ea41 410e orr.w r1, r1, lr, lsl #16
80009ca: b280 uxth r0, r0
80009cc: ea40 4201 orr.w r2, r0, r1, lsl #16
80009d0: 463b mov r3, r7
80009d2: fbb1 f1f7 udiv r1, r1, r7
80009d6: 4638 mov r0, r7
80009d8: 463c mov r4, r7
80009da: 46b8 mov r8, r7
80009dc: 46be mov lr, r7
80009de: 2620 movs r6, #32
80009e0: eba2 0208 sub.w r2, r2, r8
80009e4: ea41 410c orr.w r1, r1, ip, lsl #16
80009e8: e765 b.n 80008b6 <__udivmoddi4+0xfa>
80009ea: 4601 mov r1, r0
80009ec: e717 b.n 800081e <__udivmoddi4+0x62>
80009ee: 4610 mov r0, r2
80009f0: e72b b.n 800084a <__udivmoddi4+0x8e>
80009f2: f1c6 0120 rsb r1, r6, #32
80009f6: fa2e fc01 lsr.w ip, lr, r1
80009fa: 40b7 lsls r7, r6
80009fc: fa0e fe06 lsl.w lr, lr, r6
8000a00: fa20 f101 lsr.w r1, r0, r1
8000a04: ea41 010e orr.w r1, r1, lr
8000a08: ea4f 4e17 mov.w lr, r7, lsr #16
8000a0c: fbbc f8fe udiv r8, ip, lr
8000a10: b2bc uxth r4, r7
8000a12: fb0e cc18 mls ip, lr, r8, ip
8000a16: fb08 f904 mul.w r9, r8, r4
8000a1a: 0c0a lsrs r2, r1, #16
8000a1c: ea42 420c orr.w r2, r2, ip, lsl #16
8000a20: 40b0 lsls r0, r6
8000a22: 4591 cmp r9, r2
8000a24: ea4f 4310 mov.w r3, r0, lsr #16
8000a28: b280 uxth r0, r0
8000a2a: d93e bls.n 8000aaa <__udivmoddi4+0x2ee>
8000a2c: 18ba adds r2, r7, r2
8000a2e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000a32: d201 bcs.n 8000a38 <__udivmoddi4+0x27c>
8000a34: 4591 cmp r9, r2
8000a36: d81f bhi.n 8000a78 <__udivmoddi4+0x2bc>
8000a38: eba2 0209 sub.w r2, r2, r9
8000a3c: fbb2 f9fe udiv r9, r2, lr
8000a40: fb09 f804 mul.w r8, r9, r4
8000a44: fb0e 2a19 mls sl, lr, r9, r2
8000a48: b28a uxth r2, r1
8000a4a: ea42 420a orr.w r2, r2, sl, lsl #16
8000a4e: 4542 cmp r2, r8
8000a50: d229 bcs.n 8000aa6 <__udivmoddi4+0x2ea>
8000a52: 18ba adds r2, r7, r2
8000a54: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000a58: d2c2 bcs.n 80009e0 <__udivmoddi4+0x224>
8000a5a: 4542 cmp r2, r8
8000a5c: d2c0 bcs.n 80009e0 <__udivmoddi4+0x224>
8000a5e: f1a9 0102 sub.w r1, r9, #2
8000a62: 443a add r2, r7
8000a64: e7bc b.n 80009e0 <__udivmoddi4+0x224>
8000a66: 45c6 cmp lr, r8
8000a68: d29b bcs.n 80009a2 <__udivmoddi4+0x1e6>
8000a6a: ebb8 0302 subs.w r3, r8, r2
8000a6e: eb6c 0c07 sbc.w ip, ip, r7
8000a72: 3801 subs r0, #1
8000a74: 46e1 mov r9, ip
8000a76: e794 b.n 80009a2 <__udivmoddi4+0x1e6>
8000a78: eba7 0909 sub.w r9, r7, r9
8000a7c: 444a add r2, r9
8000a7e: fbb2 f9fe udiv r9, r2, lr
8000a82: f1a8 0c02 sub.w ip, r8, #2
8000a86: fb09 f804 mul.w r8, r9, r4
8000a8a: e7db b.n 8000a44 <__udivmoddi4+0x288>
8000a8c: 4603 mov r3, r0
8000a8e: e77d b.n 800098c <__udivmoddi4+0x1d0>
8000a90: 46d0 mov r8, sl
8000a92: e765 b.n 8000960 <__udivmoddi4+0x1a4>
8000a94: 4608 mov r0, r1
8000a96: e6fa b.n 800088e <__udivmoddi4+0xd2>
8000a98: 443b add r3, r7
8000a9a: 3a02 subs r2, #2
8000a9c: e730 b.n 8000900 <__udivmoddi4+0x144>
8000a9e: f1ac 0c02 sub.w ip, ip, #2
8000aa2: 443b add r3, r7
8000aa4: e719 b.n 80008da <__udivmoddi4+0x11e>
8000aa6: 4649 mov r1, r9
8000aa8: e79a b.n 80009e0 <__udivmoddi4+0x224>
8000aaa: eba2 0209 sub.w r2, r2, r9
8000aae: fbb2 f9fe udiv r9, r2, lr
8000ab2: 46c4 mov ip, r8
8000ab4: fb09 f804 mul.w r8, r9, r4
8000ab8: e7c4 b.n 8000a44 <__udivmoddi4+0x288>
8000aba: bf00 nop
08000abc <__aeabi_idiv0>:
8000abc: 4770 bx lr
8000abe: bf00 nop
08000ac0 <affiche>:
/* USER CODE BEGIN 0 */
volatile uint8_t angle = 0;
volatile uint8_t sens = 1;
void affiche(uint8_t nombre_entier, uint8_t nombre_decimal) {
8000ac0: b580 push {r7, lr}
8000ac2: b084 sub sp, #16
8000ac4: af00 add r7, sp, #0
8000ac6: 4603 mov r3, r0
8000ac8: 460a mov r2, r1
8000aca: 71fb strb r3, [r7, #7]
8000acc: 4613 mov r3, r2
8000ace: 71bb strb r3, [r7, #6]
uint8_t compt_uni_ent;
uint8_t compt_diz_ent;
uint8_t compt_uni_deci;
uint8_t compt_diz_deci;
compt_uni_ent = nombre_entier % 10;
8000ad0: 79fa ldrb r2, [r7, #7]
8000ad2: 4b1c ldr r3, [pc, #112] @ (8000b44 <affiche+0x84>)
8000ad4: fba3 1302 umull r1, r3, r3, r2
8000ad8: 08d9 lsrs r1, r3, #3
8000ada: 460b mov r3, r1
8000adc: 009b lsls r3, r3, #2
8000ade: 440b add r3, r1
8000ae0: 005b lsls r3, r3, #1
8000ae2: 1ad3 subs r3, r2, r3
8000ae4: 73fb strb r3, [r7, #15]
compt_diz_ent = nombre_entier / 10;
8000ae6: 79fb ldrb r3, [r7, #7]
8000ae8: 4a16 ldr r2, [pc, #88] @ (8000b44 <affiche+0x84>)
8000aea: fba2 2303 umull r2, r3, r2, r3
8000aee: 08db lsrs r3, r3, #3
8000af0: 73bb strb r3, [r7, #14]
compt_uni_deci = nombre_decimal % 10;
8000af2: 79ba ldrb r2, [r7, #6]
8000af4: 4b13 ldr r3, [pc, #76] @ (8000b44 <affiche+0x84>)
8000af6: fba3 1302 umull r1, r3, r3, r2
8000afa: 08d9 lsrs r1, r3, #3
8000afc: 460b mov r3, r1
8000afe: 009b lsls r3, r3, #2
8000b00: 440b add r3, r1
8000b02: 005b lsls r3, r3, #1
8000b04: 1ad3 subs r3, r2, r3
8000b06: 737b strb r3, [r7, #13]
compt_diz_deci = nombre_decimal / 10;
8000b08: 79bb ldrb r3, [r7, #6]
8000b0a: 4a0e ldr r2, [pc, #56] @ (8000b44 <affiche+0x84>)
8000b0c: fba2 2303 umull r2, r3, r2, r3
8000b10: 08db lsrs r3, r3, #3
8000b12: 733b strb r3, [r7, #12]
MAX7219_DisplayChar(1, compt_diz_ent);
8000b14: 7bbb ldrb r3, [r7, #14]
8000b16: 4619 mov r1, r3
8000b18: 2001 movs r0, #1
8000b1a: f000 fc17 bl 800134c <MAX7219_DisplayChar>
MAX7219_DisplayChar(2, compt_uni_ent);
8000b1e: 7bfb ldrb r3, [r7, #15]
8000b20: 4619 mov r1, r3
8000b22: 2002 movs r0, #2
8000b24: f000 fc12 bl 800134c <MAX7219_DisplayChar>
MAX7219_DisplayChar(3, compt_diz_deci);
8000b28: 7b3b ldrb r3, [r7, #12]
8000b2a: 4619 mov r1, r3
8000b2c: 2003 movs r0, #3
8000b2e: f000 fc0d bl 800134c <MAX7219_DisplayChar>
MAX7219_DisplayChar(4, compt_uni_deci);
8000b32: 7b7b ldrb r3, [r7, #13]
8000b34: 4619 mov r1, r3
8000b36: 2004 movs r0, #4
8000b38: f000 fc08 bl 800134c <MAX7219_DisplayChar>
}
8000b3c: bf00 nop
8000b3e: 3710 adds r7, #16
8000b40: 46bd mov sp, r7
8000b42: bd80 pop {r7, pc}
8000b44: cccccccd .word 0xcccccccd
08000b48 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b48: b580 push {r7, lr}
8000b4a: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b4c: f000 fc44 bl 80013d8 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b50: f000 f81a bl 8000b88 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b54: f000 f960 bl 8000e18 <MX_GPIO_Init>
MX_SPI1_Init();
8000b58: f000 f85c bl 8000c14 <MX_SPI1_Init>
MX_TIM2_Init();
8000b5c: f000 f890 bl 8000c80 <MX_TIM2_Init>
MX_TIM3_Init();
8000b60: f000 f8da bl 8000d18 <MX_TIM3_Init>
/* USER CODE BEGIN 2 */
MAX7219_Init();
8000b64: f000 fba5 bl 80012b2 <MAX7219_Init>
HAL_TIM_Base_Start_IT(&htim2);
8000b68: 4805 ldr r0, [pc, #20] @ (8000b80 <main+0x38>)
8000b6a: f001 ffe7 bl 8002b3c <HAL_TIM_Base_Start_IT>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_2);
8000b6e: 2104 movs r1, #4
8000b70: 4804 ldr r0, [pc, #16] @ (8000b84 <main+0x3c>)
8000b72: f002 f87d bl 8002c70 <HAL_TIM_PWM_Start>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
MAX7219_Clear();
8000b76: f000 fbd3 bl 8001320 <MAX7219_Clear>
while (1)
8000b7a: bf00 nop
8000b7c: e7fd b.n 8000b7a <main+0x32>
8000b7e: bf00 nop
8000b80: 20000084 .word 0x20000084
8000b84: 200000c4 .word 0x200000c4
08000b88 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000b88: b580 push {r7, lr}
8000b8a: b092 sub sp, #72 @ 0x48
8000b8c: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000b8e: f107 0314 add.w r3, r7, #20
8000b92: 2234 movs r2, #52 @ 0x34
8000b94: 2100 movs r1, #0
8000b96: 4618 mov r0, r3
8000b98: f002 fdfe bl 8003798 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000b9c: 463b mov r3, r7
8000b9e: 2200 movs r2, #0
8000ba0: 601a str r2, [r3, #0]
8000ba2: 605a str r2, [r3, #4]
8000ba4: 609a str r2, [r3, #8]
8000ba6: 60da str r2, [r3, #12]
8000ba8: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000baa: 4b19 ldr r3, [pc, #100] @ (8000c10 <SystemClock_Config+0x88>)
8000bac: 681b ldr r3, [r3, #0]
8000bae: f423 53c0 bic.w r3, r3, #6144 @ 0x1800
8000bb2: 4a17 ldr r2, [pc, #92] @ (8000c10 <SystemClock_Config+0x88>)
8000bb4: f443 6300 orr.w r3, r3, #2048 @ 0x800
8000bb8: 6013 str r3, [r2, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000bba: 2302 movs r3, #2
8000bbc: 617b str r3, [r7, #20]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000bbe: 2301 movs r3, #1
8000bc0: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000bc2: 2310 movs r3, #16
8000bc4: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000bc6: 2300 movs r3, #0
8000bc8: 63bb str r3, [r7, #56] @ 0x38
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000bca: f107 0314 add.w r3, r7, #20
8000bce: 4618 mov r0, r3
8000bd0: f000 ff48 bl 8001a64 <HAL_RCC_OscConfig>
8000bd4: 4603 mov r3, r0
8000bd6: 2b00 cmp r3, #0
8000bd8: d001 beq.n 8000bde <SystemClock_Config+0x56>
{
Error_Handler();
8000bda: f000 f9e5 bl 8000fa8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000bde: 230f movs r3, #15
8000be0: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
8000be2: 2301 movs r3, #1
8000be4: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000be6: 2300 movs r3, #0
8000be8: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000bea: 2300 movs r3, #0
8000bec: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000bee: 2300 movs r3, #0
8000bf0: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000bf2: 463b mov r3, r7
8000bf4: 2100 movs r1, #0
8000bf6: 4618 mov r0, r3
8000bf8: f001 fa64 bl 80020c4 <HAL_RCC_ClockConfig>
8000bfc: 4603 mov r3, r0
8000bfe: 2b00 cmp r3, #0
8000c00: d001 beq.n 8000c06 <SystemClock_Config+0x7e>
{
Error_Handler();
8000c02: f000 f9d1 bl 8000fa8 <Error_Handler>
}
}
8000c06: bf00 nop
8000c08: 3748 adds r7, #72 @ 0x48
8000c0a: 46bd mov sp, r7
8000c0c: bd80 pop {r7, pc}
8000c0e: bf00 nop
8000c10: 40007000 .word 0x40007000
08000c14 <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
8000c14: b580 push {r7, lr}
8000c16: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
8000c18: 4b17 ldr r3, [pc, #92] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c1a: 4a18 ldr r2, [pc, #96] @ (8000c7c <MX_SPI1_Init+0x68>)
8000c1c: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
8000c1e: 4b16 ldr r3, [pc, #88] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c20: f44f 7282 mov.w r2, #260 @ 0x104
8000c24: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
8000c26: 4b14 ldr r3, [pc, #80] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c28: 2200 movs r2, #0
8000c2a: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
8000c2c: 4b12 ldr r3, [pc, #72] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c2e: 2200 movs r2, #0
8000c30: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
8000c32: 4b11 ldr r3, [pc, #68] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c34: 2200 movs r2, #0
8000c36: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
8000c38: 4b0f ldr r3, [pc, #60] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c3a: 2200 movs r2, #0
8000c3c: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
8000c3e: 4b0e ldr r3, [pc, #56] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c40: f44f 7200 mov.w r2, #512 @ 0x200
8000c44: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8000c46: 4b0c ldr r3, [pc, #48] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c48: 2200 movs r2, #0
8000c4a: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000c4c: 4b0a ldr r3, [pc, #40] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c4e: 2200 movs r2, #0
8000c50: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000c52: 4b09 ldr r3, [pc, #36] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c54: 2200 movs r2, #0
8000c56: 625a str r2, [r3, #36] @ 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000c58: 4b07 ldr r3, [pc, #28] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c5a: 2200 movs r2, #0
8000c5c: 629a str r2, [r3, #40] @ 0x28
hspi1.Init.CRCPolynomial = 10;
8000c5e: 4b06 ldr r3, [pc, #24] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c60: 220a movs r2, #10
8000c62: 62da str r2, [r3, #44] @ 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000c64: 4804 ldr r0, [pc, #16] @ (8000c78 <MX_SPI1_Init+0x64>)
8000c66: f001 fc7f bl 8002568 <HAL_SPI_Init>
8000c6a: 4603 mov r3, r0
8000c6c: 2b00 cmp r3, #0
8000c6e: d001 beq.n 8000c74 <MX_SPI1_Init+0x60>
{
Error_Handler();
8000c70: f000 f99a bl 8000fa8 <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
8000c74: bf00 nop
8000c76: bd80 pop {r7, pc}
8000c78: 2000002c .word 0x2000002c
8000c7c: 40013000 .word 0x40013000
08000c80 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8000c80: b580 push {r7, lr}
8000c82: b086 sub sp, #24
8000c84: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000c86: f107 0308 add.w r3, r7, #8
8000c8a: 2200 movs r2, #0
8000c8c: 601a str r2, [r3, #0]
8000c8e: 605a str r2, [r3, #4]
8000c90: 609a str r2, [r3, #8]
8000c92: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000c94: 463b mov r3, r7
8000c96: 2200 movs r2, #0
8000c98: 601a str r2, [r3, #0]
8000c9a: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000c9c: 4b1d ldr r3, [pc, #116] @ (8000d14 <MX_TIM2_Init+0x94>)
8000c9e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8000ca2: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 167-1;
8000ca4: 4b1b ldr r3, [pc, #108] @ (8000d14 <MX_TIM2_Init+0x94>)
8000ca6: 22a6 movs r2, #166 @ 0xa6
8000ca8: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000caa: 4b1a ldr r3, [pc, #104] @ (8000d14 <MX_TIM2_Init+0x94>)
8000cac: 2200 movs r2, #0
8000cae: 609a str r2, [r3, #8]
htim2.Init.Period = 16000-1;
8000cb0: 4b18 ldr r3, [pc, #96] @ (8000d14 <MX_TIM2_Init+0x94>)
8000cb2: f643 627f movw r2, #15999 @ 0x3e7f
8000cb6: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000cb8: 4b16 ldr r3, [pc, #88] @ (8000d14 <MX_TIM2_Init+0x94>)
8000cba: 2200 movs r2, #0
8000cbc: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
8000cbe: 4b15 ldr r3, [pc, #84] @ (8000d14 <MX_TIM2_Init+0x94>)
8000cc0: 2280 movs r2, #128 @ 0x80
8000cc2: 615a str r2, [r3, #20]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8000cc4: 4813 ldr r0, [pc, #76] @ (8000d14 <MX_TIM2_Init+0x94>)
8000cc6: f001 fef9 bl 8002abc <HAL_TIM_Base_Init>
8000cca: 4603 mov r3, r0
8000ccc: 2b00 cmp r3, #0
8000cce: d001 beq.n 8000cd4 <MX_TIM2_Init+0x54>
{
Error_Handler();
8000cd0: f000 f96a bl 8000fa8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000cd4: f44f 5380 mov.w r3, #4096 @ 0x1000
8000cd8: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8000cda: f107 0308 add.w r3, r7, #8
8000cde: 4619 mov r1, r3
8000ce0: 480c ldr r0, [pc, #48] @ (8000d14 <MX_TIM2_Init+0x94>)
8000ce2: f002 f9e9 bl 80030b8 <HAL_TIM_ConfigClockSource>
8000ce6: 4603 mov r3, r0
8000ce8: 2b00 cmp r3, #0
8000cea: d001 beq.n 8000cf0 <MX_TIM2_Init+0x70>
{
Error_Handler();
8000cec: f000 f95c bl 8000fa8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000cf0: 2300 movs r3, #0
8000cf2: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000cf4: 2300 movs r3, #0
8000cf6: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000cf8: 463b mov r3, r7
8000cfa: 4619 mov r1, r3
8000cfc: 4805 ldr r0, [pc, #20] @ (8000d14 <MX_TIM2_Init+0x94>)
8000cfe: f002 fced bl 80036dc <HAL_TIMEx_MasterConfigSynchronization>
8000d02: 4603 mov r3, r0
8000d04: 2b00 cmp r3, #0
8000d06: d001 beq.n 8000d0c <MX_TIM2_Init+0x8c>
{
Error_Handler();
8000d08: f000 f94e bl 8000fa8 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
8000d0c: bf00 nop
8000d0e: 3718 adds r7, #24
8000d10: 46bd mov sp, r7
8000d12: bd80 pop {r7, pc}
8000d14: 20000084 .word 0x20000084
08000d18 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
8000d18: b580 push {r7, lr}
8000d1a: b08a sub sp, #40 @ 0x28
8000d1c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000d1e: f107 0318 add.w r3, r7, #24
8000d22: 2200 movs r2, #0
8000d24: 601a str r2, [r3, #0]
8000d26: 605a str r2, [r3, #4]
8000d28: 609a str r2, [r3, #8]
8000d2a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000d2c: f107 0310 add.w r3, r7, #16
8000d30: 2200 movs r2, #0
8000d32: 601a str r2, [r3, #0]
8000d34: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000d36: 463b mov r3, r7
8000d38: 2200 movs r2, #0
8000d3a: 601a str r2, [r3, #0]
8000d3c: 605a str r2, [r3, #4]
8000d3e: 609a str r2, [r3, #8]
8000d40: 60da str r2, [r3, #12]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8000d42: 4b33 ldr r3, [pc, #204] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d44: 4a33 ldr r2, [pc, #204] @ (8000e14 <MX_TIM3_Init+0xfc>)
8000d46: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 20-1;
8000d48: 4b31 ldr r3, [pc, #196] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d4a: 2213 movs r2, #19
8000d4c: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8000d4e: 4b30 ldr r3, [pc, #192] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d50: 2200 movs r2, #0
8000d52: 609a str r2, [r3, #8]
htim3.Init.Period = 16000-1;
8000d54: 4b2e ldr r3, [pc, #184] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d56: f643 627f movw r2, #15999 @ 0x3e7f
8000d5a: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000d5c: 4b2c ldr r3, [pc, #176] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d5e: 2200 movs r2, #0
8000d60: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
8000d62: 4b2b ldr r3, [pc, #172] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d64: 2280 movs r2, #128 @ 0x80
8000d66: 615a str r2, [r3, #20]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8000d68: 4829 ldr r0, [pc, #164] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d6a: f001 fea7 bl 8002abc <HAL_TIM_Base_Init>
8000d6e: 4603 mov r3, r0
8000d70: 2b00 cmp r3, #0
8000d72: d001 beq.n 8000d78 <MX_TIM3_Init+0x60>
{
Error_Handler();
8000d74: f000 f918 bl 8000fa8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000d78: f44f 5380 mov.w r3, #4096 @ 0x1000
8000d7c: 61bb str r3, [r7, #24]
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
8000d7e: f107 0318 add.w r3, r7, #24
8000d82: 4619 mov r1, r3
8000d84: 4822 ldr r0, [pc, #136] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d86: f002 f997 bl 80030b8 <HAL_TIM_ConfigClockSource>
8000d8a: 4603 mov r3, r0
8000d8c: 2b00 cmp r3, #0
8000d8e: d001 beq.n 8000d94 <MX_TIM3_Init+0x7c>
{
Error_Handler();
8000d90: f000 f90a bl 8000fa8 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8000d94: 481e ldr r0, [pc, #120] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000d96: f001 ff23 bl 8002be0 <HAL_TIM_PWM_Init>
8000d9a: 4603 mov r3, r0
8000d9c: 2b00 cmp r3, #0
8000d9e: d001 beq.n 8000da4 <MX_TIM3_Init+0x8c>
{
Error_Handler();
8000da0: f000 f902 bl 8000fa8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000da4: 2300 movs r3, #0
8000da6: 613b str r3, [r7, #16]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000da8: 2300 movs r3, #0
8000daa: 617b str r3, [r7, #20]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8000dac: f107 0310 add.w r3, r7, #16
8000db0: 4619 mov r1, r3
8000db2: 4817 ldr r0, [pc, #92] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000db4: f002 fc92 bl 80036dc <HAL_TIMEx_MasterConfigSynchronization>
8000db8: 4603 mov r3, r0
8000dba: 2b00 cmp r3, #0
8000dbc: d001 beq.n 8000dc2 <MX_TIM3_Init+0xaa>
{
Error_Handler();
8000dbe: f000 f8f3 bl 8000fa8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000dc2: 2360 movs r3, #96 @ 0x60
8000dc4: 603b str r3, [r7, #0]
sConfigOC.Pulse = 80-1;
8000dc6: 234f movs r3, #79 @ 0x4f
8000dc8: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000dca: 2300 movs r3, #0
8000dcc: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000dce: 2300 movs r3, #0
8000dd0: 60fb str r3, [r7, #12]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000dd2: 463b mov r3, r7
8000dd4: 2200 movs r2, #0
8000dd6: 4619 mov r1, r3
8000dd8: 480d ldr r0, [pc, #52] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000dda: f002 f8ab bl 8002f34 <HAL_TIM_PWM_ConfigChannel>
8000dde: 4603 mov r3, r0
8000de0: 2b00 cmp r3, #0
8000de2: d001 beq.n 8000de8 <MX_TIM3_Init+0xd0>
{
Error_Handler();
8000de4: f000 f8e0 bl 8000fa8 <Error_Handler>
}
sConfigOC.Pulse = 0;
8000de8: 2300 movs r3, #0
8000dea: 607b str r3, [r7, #4]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8000dec: 463b mov r3, r7
8000dee: 2204 movs r2, #4
8000df0: 4619 mov r1, r3
8000df2: 4807 ldr r0, [pc, #28] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000df4: f002 f89e bl 8002f34 <HAL_TIM_PWM_ConfigChannel>
8000df8: 4603 mov r3, r0
8000dfa: 2b00 cmp r3, #0
8000dfc: d001 beq.n 8000e02 <MX_TIM3_Init+0xea>
{
Error_Handler();
8000dfe: f000 f8d3 bl 8000fa8 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
8000e02: 4803 ldr r0, [pc, #12] @ (8000e10 <MX_TIM3_Init+0xf8>)
8000e04: f000 f988 bl 8001118 <HAL_TIM_MspPostInit>
}
8000e08: bf00 nop
8000e0a: 3728 adds r7, #40 @ 0x28
8000e0c: 46bd mov sp, r7
8000e0e: bd80 pop {r7, pc}
8000e10: 200000c4 .word 0x200000c4
8000e14: 40000400 .word 0x40000400
08000e18 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000e18: b580 push {r7, lr}
8000e1a: b088 sub sp, #32
8000e1c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000e1e: f107 030c add.w r3, r7, #12
8000e22: 2200 movs r2, #0
8000e24: 601a str r2, [r3, #0]
8000e26: 605a str r2, [r3, #4]
8000e28: 609a str r2, [r3, #8]
8000e2a: 60da str r2, [r3, #12]
8000e2c: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000e2e: 4b28 ldr r3, [pc, #160] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e30: 69db ldr r3, [r3, #28]
8000e32: 4a27 ldr r2, [pc, #156] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e34: f043 0304 orr.w r3, r3, #4
8000e38: 61d3 str r3, [r2, #28]
8000e3a: 4b25 ldr r3, [pc, #148] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e3c: 69db ldr r3, [r3, #28]
8000e3e: f003 0304 and.w r3, r3, #4
8000e42: 60bb str r3, [r7, #8]
8000e44: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000e46: 4b22 ldr r3, [pc, #136] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e48: 69db ldr r3, [r3, #28]
8000e4a: 4a21 ldr r2, [pc, #132] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e4c: f043 0301 orr.w r3, r3, #1
8000e50: 61d3 str r3, [r2, #28]
8000e52: 4b1f ldr r3, [pc, #124] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e54: 69db ldr r3, [r3, #28]
8000e56: f003 0301 and.w r3, r3, #1
8000e5a: 607b str r3, [r7, #4]
8000e5c: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000e5e: 4b1c ldr r3, [pc, #112] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e60: 69db ldr r3, [r3, #28]
8000e62: 4a1b ldr r2, [pc, #108] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e64: f043 0302 orr.w r3, r3, #2
8000e68: 61d3 str r3, [r2, #28]
8000e6a: 4b19 ldr r3, [pc, #100] @ (8000ed0 <MX_GPIO_Init+0xb8>)
8000e6c: 69db ldr r3, [r3, #28]
8000e6e: f003 0302 and.w r3, r3, #2
8000e72: 603b str r3, [r7, #0]
8000e74: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET);
8000e76: 2200 movs r2, #0
8000e78: 2101 movs r1, #1
8000e7a: 4816 ldr r0, [pc, #88] @ (8000ed4 <MX_GPIO_Init+0xbc>)
8000e7c: f000 fdb8 bl 80019f0 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PC0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000e80: 2301 movs r3, #1
8000e82: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000e84: 2301 movs r3, #1
8000e86: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e88: 2300 movs r3, #0
8000e8a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e8c: 2300 movs r3, #0
8000e8e: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000e90: f107 030c add.w r3, r7, #12
8000e94: 4619 mov r1, r3
8000e96: 480f ldr r0, [pc, #60] @ (8000ed4 <MX_GPIO_Init+0xbc>)
8000e98: f000 fc1a bl 80016d0 <HAL_GPIO_Init>
/*Configure GPIO pins : PA11 PA12 */
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
8000e9c: f44f 53c0 mov.w r3, #6144 @ 0x1800
8000ea0: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000ea2: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000ea6: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ea8: 2300 movs r3, #0
8000eaa: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000eac: f107 030c add.w r3, r7, #12
8000eb0: 4619 mov r1, r3
8000eb2: 4809 ldr r0, [pc, #36] @ (8000ed8 <MX_GPIO_Init+0xc0>)
8000eb4: f000 fc0c bl 80016d0 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
8000eb8: 2200 movs r2, #0
8000eba: 2100 movs r1, #0
8000ebc: 2028 movs r0, #40 @ 0x28
8000ebe: f000 fbd0 bl 8001662 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
8000ec2: 2028 movs r0, #40 @ 0x28
8000ec4: f000 fbe9 bl 800169a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000ec8: bf00 nop
8000eca: 3720 adds r7, #32
8000ecc: 46bd mov sp, r7
8000ece: bd80 pop {r7, pc}
8000ed0: 40023800 .word 0x40023800
8000ed4: 40020800 .word 0x40020800
8000ed8: 40020000 .word 0x40020000
8000edc: 00000000 .word 0x00000000
08000ee0 <HAL_TIM_PeriodElapsedCallback>:
/* USER CODE BEGIN 4 */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
8000ee0: b590 push {r4, r7, lr}
8000ee2: b083 sub sp, #12
8000ee4: af00 add r7, sp, #0
8000ee6: 6078 str r0, [r7, #4]
if (htim->Instance == TIM2) {
8000ee8: 687b ldr r3, [r7, #4]
8000eea: 681b ldr r3, [r3, #0]
8000eec: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8000ef0: d147 bne.n 8000f82 <HAL_TIM_PeriodElapsedCallback+0xa2>
if (sens) {
8000ef2: 4b29 ldr r3, [pc, #164] @ (8000f98 <HAL_TIM_PeriodElapsedCallback+0xb8>)
8000ef4: 781b ldrb r3, [r3, #0]
8000ef6: b2db uxtb r3, r3
8000ef8: 2b00 cmp r3, #0
8000efa: d00f beq.n 8000f1c <HAL_TIM_PeriodElapsedCallback+0x3c>
angle++;
8000efc: 4b27 ldr r3, [pc, #156] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000efe: 781b ldrb r3, [r3, #0]
8000f00: b2db uxtb r3, r3
8000f02: 3301 adds r3, #1
8000f04: b2da uxtb r2, r3
8000f06: 4b25 ldr r3, [pc, #148] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000f08: 701a strb r2, [r3, #0]
if (angle >= 90) {
8000f0a: 4b24 ldr r3, [pc, #144] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000f0c: 781b ldrb r3, [r3, #0]
8000f0e: b2db uxtb r3, r3
8000f10: 2b59 cmp r3, #89 @ 0x59
8000f12: d912 bls.n 8000f3a <HAL_TIM_PeriodElapsedCallback+0x5a>
sens = 0;
8000f14: 4b20 ldr r3, [pc, #128] @ (8000f98 <HAL_TIM_PeriodElapsedCallback+0xb8>)
8000f16: 2200 movs r2, #0
8000f18: 701a strb r2, [r3, #0]
8000f1a: e00e b.n 8000f3a <HAL_TIM_PeriodElapsedCallback+0x5a>
}
} else {
angle--;
8000f1c: 4b1f ldr r3, [pc, #124] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000f1e: 781b ldrb r3, [r3, #0]
8000f20: b2db uxtb r3, r3
8000f22: 3b01 subs r3, #1
8000f24: b2da uxtb r2, r3
8000f26: 4b1d ldr r3, [pc, #116] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000f28: 701a strb r2, [r3, #0]
if (angle <= 0) {
8000f2a: 4b1c ldr r3, [pc, #112] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000f2c: 781b ldrb r3, [r3, #0]
8000f2e: b2db uxtb r3, r3
8000f30: 2b00 cmp r3, #0
8000f32: d102 bne.n 8000f3a <HAL_TIM_PeriodElapsedCallback+0x5a>
sens = 1;
8000f34: 4b18 ldr r3, [pc, #96] @ (8000f98 <HAL_TIM_PeriodElapsedCallback+0xb8>)
8000f36: 2201 movs r2, #1
8000f38: 701a strb r2, [r3, #0]
}
}
affiche(angle, 0);
8000f3a: 4b18 ldr r3, [pc, #96] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000f3c: 781b ldrb r3, [r3, #0]
8000f3e: b2db uxtb r3, r3
8000f40: 2100 movs r1, #0
8000f42: 4618 mov r0, r3
8000f44: f7ff fdbc bl 8000ac0 <affiche>
TIM3->CCR2 = 800 + angle * 8.9;
8000f48: 4b14 ldr r3, [pc, #80] @ (8000f9c <HAL_TIM_PeriodElapsedCallback+0xbc>)
8000f4a: 781b ldrb r3, [r3, #0]
8000f4c: b2db uxtb r3, r3
8000f4e: 4618 mov r0, r3
8000f50: f7ff fb92 bl 8000678 <__aeabi_i2d>
8000f54: a30e add r3, pc, #56 @ (adr r3, 8000f90 <HAL_TIM_PeriodElapsedCallback+0xb0>)
8000f56: e9d3 2300 ldrd r2, r3, [r3]
8000f5a: f7ff f911 bl 8000180 <__aeabi_dmul>
8000f5e: 4602 mov r2, r0
8000f60: 460b mov r3, r1
8000f62: 4610 mov r0, r2
8000f64: 4619 mov r1, r3
8000f66: f04f 0200 mov.w r2, #0
8000f6a: 4b0d ldr r3, [pc, #52] @ (8000fa0 <HAL_TIM_PeriodElapsedCallback+0xc0>)
8000f6c: f7ff fa38 bl 80003e0 <__adddf3>
8000f70: 4602 mov r2, r0
8000f72: 460b mov r3, r1
8000f74: 4c0b ldr r4, [pc, #44] @ (8000fa4 <HAL_TIM_PeriodElapsedCallback+0xc4>)
8000f76: 4610 mov r0, r2
8000f78: 4619 mov r1, r3
8000f7a: f7ff fbe7 bl 800074c <__aeabi_d2uiz>
8000f7e: 4603 mov r3, r0
8000f80: 63a3 str r3, [r4, #56] @ 0x38
//__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_2, 800 + angle * 8.9);
}
}
8000f82: bf00 nop
8000f84: 370c adds r7, #12
8000f86: 46bd mov sp, r7
8000f88: bd90 pop {r4, r7, pc}
8000f8a: bf00 nop
8000f8c: f3af 8000 nop.w
8000f90: cccccccd .word 0xcccccccd
8000f94: 4021cccc .word 0x4021cccc
8000f98: 20000000 .word 0x20000000
8000f9c: 20000104 .word 0x20000104
8000fa0: 40890000 .word 0x40890000
8000fa4: 40000400 .word 0x40000400
08000fa8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000fa8: b480 push {r7}
8000faa: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000fac: b672 cpsid i
}
8000fae: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000fb0: bf00 nop
8000fb2: e7fd b.n 8000fb0 <Error_Handler+0x8>
08000fb4 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000fb4: b480 push {r7}
8000fb6: b085 sub sp, #20
8000fb8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_COMP_CLK_ENABLE();
8000fba: 4b14 ldr r3, [pc, #80] @ (800100c <HAL_MspInit+0x58>)
8000fbc: 6a5b ldr r3, [r3, #36] @ 0x24
8000fbe: 4a13 ldr r2, [pc, #76] @ (800100c <HAL_MspInit+0x58>)
8000fc0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000fc4: 6253 str r3, [r2, #36] @ 0x24
8000fc6: 4b11 ldr r3, [pc, #68] @ (800100c <HAL_MspInit+0x58>)
8000fc8: 6a5b ldr r3, [r3, #36] @ 0x24
8000fca: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8000fce: 60fb str r3, [r7, #12]
8000fd0: 68fb ldr r3, [r7, #12]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000fd2: 4b0e ldr r3, [pc, #56] @ (800100c <HAL_MspInit+0x58>)
8000fd4: 6a1b ldr r3, [r3, #32]
8000fd6: 4a0d ldr r2, [pc, #52] @ (800100c <HAL_MspInit+0x58>)
8000fd8: f043 0301 orr.w r3, r3, #1
8000fdc: 6213 str r3, [r2, #32]
8000fde: 4b0b ldr r3, [pc, #44] @ (800100c <HAL_MspInit+0x58>)
8000fe0: 6a1b ldr r3, [r3, #32]
8000fe2: f003 0301 and.w r3, r3, #1
8000fe6: 60bb str r3, [r7, #8]
8000fe8: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
8000fea: 4b08 ldr r3, [pc, #32] @ (800100c <HAL_MspInit+0x58>)
8000fec: 6a5b ldr r3, [r3, #36] @ 0x24
8000fee: 4a07 ldr r2, [pc, #28] @ (800100c <HAL_MspInit+0x58>)
8000ff0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000ff4: 6253 str r3, [r2, #36] @ 0x24
8000ff6: 4b05 ldr r3, [pc, #20] @ (800100c <HAL_MspInit+0x58>)
8000ff8: 6a5b ldr r3, [r3, #36] @ 0x24
8000ffa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000ffe: 607b str r3, [r7, #4]
8001000: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001002: bf00 nop
8001004: 3714 adds r7, #20
8001006: 46bd mov sp, r7
8001008: bc80 pop {r7}
800100a: 4770 bx lr
800100c: 40023800 .word 0x40023800
08001010 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8001010: b580 push {r7, lr}
8001012: b08a sub sp, #40 @ 0x28
8001014: af00 add r7, sp, #0
8001016: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001018: f107 0314 add.w r3, r7, #20
800101c: 2200 movs r2, #0
800101e: 601a str r2, [r3, #0]
8001020: 605a str r2, [r3, #4]
8001022: 609a str r2, [r3, #8]
8001024: 60da str r2, [r3, #12]
8001026: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
8001028: 687b ldr r3, [r7, #4]
800102a: 681b ldr r3, [r3, #0]
800102c: 4a17 ldr r2, [pc, #92] @ (800108c <HAL_SPI_MspInit+0x7c>)
800102e: 4293 cmp r3, r2
8001030: d127 bne.n 8001082 <HAL_SPI_MspInit+0x72>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8001032: 4b17 ldr r3, [pc, #92] @ (8001090 <HAL_SPI_MspInit+0x80>)
8001034: 6a1b ldr r3, [r3, #32]
8001036: 4a16 ldr r2, [pc, #88] @ (8001090 <HAL_SPI_MspInit+0x80>)
8001038: f443 5380 orr.w r3, r3, #4096 @ 0x1000
800103c: 6213 str r3, [r2, #32]
800103e: 4b14 ldr r3, [pc, #80] @ (8001090 <HAL_SPI_MspInit+0x80>)
8001040: 6a1b ldr r3, [r3, #32]
8001042: f403 5380 and.w r3, r3, #4096 @ 0x1000
8001046: 613b str r3, [r7, #16]
8001048: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800104a: 4b11 ldr r3, [pc, #68] @ (8001090 <HAL_SPI_MspInit+0x80>)
800104c: 69db ldr r3, [r3, #28]
800104e: 4a10 ldr r2, [pc, #64] @ (8001090 <HAL_SPI_MspInit+0x80>)
8001050: f043 0301 orr.w r3, r3, #1
8001054: 61d3 str r3, [r2, #28]
8001056: 4b0e ldr r3, [pc, #56] @ (8001090 <HAL_SPI_MspInit+0x80>)
8001058: 69db ldr r3, [r3, #28]
800105a: f003 0301 and.w r3, r3, #1
800105e: 60fb str r3, [r7, #12]
8001060: 68fb ldr r3, [r7, #12]
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
8001062: 23e0 movs r3, #224 @ 0xe0
8001064: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001066: 2302 movs r3, #2
8001068: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800106a: 2300 movs r3, #0
800106c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800106e: 2303 movs r3, #3
8001070: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8001072: 2305 movs r3, #5
8001074: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001076: f107 0314 add.w r3, r7, #20
800107a: 4619 mov r1, r3
800107c: 4805 ldr r0, [pc, #20] @ (8001094 <HAL_SPI_MspInit+0x84>)
800107e: f000 fb27 bl 80016d0 <HAL_GPIO_Init>
/* USER CODE END SPI1_MspInit 1 */
}
}
8001082: bf00 nop
8001084: 3728 adds r7, #40 @ 0x28
8001086: 46bd mov sp, r7
8001088: bd80 pop {r7, pc}
800108a: bf00 nop
800108c: 40013000 .word 0x40013000
8001090: 40023800 .word 0x40023800
8001094: 40020000 .word 0x40020000
08001098 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001098: b580 push {r7, lr}
800109a: b084 sub sp, #16
800109c: af00 add r7, sp, #0
800109e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
80010a0: 687b ldr r3, [r7, #4]
80010a2: 681b ldr r3, [r3, #0]
80010a4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80010a8: d114 bne.n 80010d4 <HAL_TIM_Base_MspInit+0x3c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
80010aa: 4b19 ldr r3, [pc, #100] @ (8001110 <HAL_TIM_Base_MspInit+0x78>)
80010ac: 6a5b ldr r3, [r3, #36] @ 0x24
80010ae: 4a18 ldr r2, [pc, #96] @ (8001110 <HAL_TIM_Base_MspInit+0x78>)
80010b0: f043 0301 orr.w r3, r3, #1
80010b4: 6253 str r3, [r2, #36] @ 0x24
80010b6: 4b16 ldr r3, [pc, #88] @ (8001110 <HAL_TIM_Base_MspInit+0x78>)
80010b8: 6a5b ldr r3, [r3, #36] @ 0x24
80010ba: f003 0301 and.w r3, r3, #1
80010be: 60fb str r3, [r7, #12]
80010c0: 68fb ldr r3, [r7, #12]
/* TIM2 interrupt Init */
HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
80010c2: 2200 movs r2, #0
80010c4: 2100 movs r1, #0
80010c6: 201c movs r0, #28
80010c8: f000 facb bl 8001662 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM2_IRQn);
80010cc: 201c movs r0, #28
80010ce: f000 fae4 bl 800169a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
80010d2: e018 b.n 8001106 <HAL_TIM_Base_MspInit+0x6e>
else if(htim_base->Instance==TIM3)
80010d4: 687b ldr r3, [r7, #4]
80010d6: 681b ldr r3, [r3, #0]
80010d8: 4a0e ldr r2, [pc, #56] @ (8001114 <HAL_TIM_Base_MspInit+0x7c>)
80010da: 4293 cmp r3, r2
80010dc: d113 bne.n 8001106 <HAL_TIM_Base_MspInit+0x6e>
__HAL_RCC_TIM3_CLK_ENABLE();
80010de: 4b0c ldr r3, [pc, #48] @ (8001110 <HAL_TIM_Base_MspInit+0x78>)
80010e0: 6a5b ldr r3, [r3, #36] @ 0x24
80010e2: 4a0b ldr r2, [pc, #44] @ (8001110 <HAL_TIM_Base_MspInit+0x78>)
80010e4: f043 0302 orr.w r3, r3, #2
80010e8: 6253 str r3, [r2, #36] @ 0x24
80010ea: 4b09 ldr r3, [pc, #36] @ (8001110 <HAL_TIM_Base_MspInit+0x78>)
80010ec: 6a5b ldr r3, [r3, #36] @ 0x24
80010ee: f003 0302 and.w r3, r3, #2
80010f2: 60bb str r3, [r7, #8]
80010f4: 68bb ldr r3, [r7, #8]
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
80010f6: 2200 movs r2, #0
80010f8: 2100 movs r1, #0
80010fa: 201d movs r0, #29
80010fc: f000 fab1 bl 8001662 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM3_IRQn);
8001100: 201d movs r0, #29
8001102: f000 faca bl 800169a <HAL_NVIC_EnableIRQ>
}
8001106: bf00 nop
8001108: 3710 adds r7, #16
800110a: 46bd mov sp, r7
800110c: bd80 pop {r7, pc}
800110e: bf00 nop
8001110: 40023800 .word 0x40023800
8001114: 40000400 .word 0x40000400
08001118 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001118: b580 push {r7, lr}
800111a: b08a sub sp, #40 @ 0x28
800111c: af00 add r7, sp, #0
800111e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001120: f107 0314 add.w r3, r7, #20
8001124: 2200 movs r2, #0
8001126: 601a str r2, [r3, #0]
8001128: 605a str r2, [r3, #4]
800112a: 609a str r2, [r3, #8]
800112c: 60da str r2, [r3, #12]
800112e: 611a str r2, [r3, #16]
if(htim->Instance==TIM3)
8001130: 687b ldr r3, [r7, #4]
8001132: 681b ldr r3, [r3, #0]
8001134: 4a1f ldr r2, [pc, #124] @ (80011b4 <HAL_TIM_MspPostInit+0x9c>)
8001136: 4293 cmp r3, r2
8001138: d137 bne.n 80011aa <HAL_TIM_MspPostInit+0x92>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOC_CLK_ENABLE();
800113a: 4b1f ldr r3, [pc, #124] @ (80011b8 <HAL_TIM_MspPostInit+0xa0>)
800113c: 69db ldr r3, [r3, #28]
800113e: 4a1e ldr r2, [pc, #120] @ (80011b8 <HAL_TIM_MspPostInit+0xa0>)
8001140: f043 0304 orr.w r3, r3, #4
8001144: 61d3 str r3, [r2, #28]
8001146: 4b1c ldr r3, [pc, #112] @ (80011b8 <HAL_TIM_MspPostInit+0xa0>)
8001148: 69db ldr r3, [r3, #28]
800114a: f003 0304 and.w r3, r3, #4
800114e: 613b str r3, [r7, #16]
8001150: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001152: 4b19 ldr r3, [pc, #100] @ (80011b8 <HAL_TIM_MspPostInit+0xa0>)
8001154: 69db ldr r3, [r3, #28]
8001156: 4a18 ldr r2, [pc, #96] @ (80011b8 <HAL_TIM_MspPostInit+0xa0>)
8001158: f043 0302 orr.w r3, r3, #2
800115c: 61d3 str r3, [r2, #28]
800115e: 4b16 ldr r3, [pc, #88] @ (80011b8 <HAL_TIM_MspPostInit+0xa0>)
8001160: 69db ldr r3, [r3, #28]
8001162: f003 0302 and.w r3, r3, #2
8001166: 60fb str r3, [r7, #12]
8001168: 68fb ldr r3, [r7, #12]
/**TIM3 GPIO Configuration
PC6 ------> TIM3_CH1
PB5 ------> TIM3_CH2
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
800116a: 2340 movs r3, #64 @ 0x40
800116c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800116e: 2302 movs r3, #2
8001170: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001172: 2300 movs r3, #0
8001174: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001176: 2300 movs r3, #0
8001178: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
800117a: 2302 movs r3, #2
800117c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800117e: f107 0314 add.w r3, r7, #20
8001182: 4619 mov r1, r3
8001184: 480d ldr r0, [pc, #52] @ (80011bc <HAL_TIM_MspPostInit+0xa4>)
8001186: f000 faa3 bl 80016d0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_5;
800118a: 2320 movs r3, #32
800118c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800118e: 2302 movs r3, #2
8001190: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001192: 2300 movs r3, #0
8001194: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001196: 2300 movs r3, #0
8001198: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
800119a: 2302 movs r3, #2
800119c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800119e: f107 0314 add.w r3, r7, #20
80011a2: 4619 mov r1, r3
80011a4: 4806 ldr r0, [pc, #24] @ (80011c0 <HAL_TIM_MspPostInit+0xa8>)
80011a6: f000 fa93 bl 80016d0 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
80011aa: bf00 nop
80011ac: 3728 adds r7, #40 @ 0x28
80011ae: 46bd mov sp, r7
80011b0: bd80 pop {r7, pc}
80011b2: bf00 nop
80011b4: 40000400 .word 0x40000400
80011b8: 40023800 .word 0x40023800
80011bc: 40020800 .word 0x40020800
80011c0: 40020400 .word 0x40020400
080011c4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80011c4: b480 push {r7}
80011c6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80011c8: bf00 nop
80011ca: e7fd b.n 80011c8 <NMI_Handler+0x4>
080011cc <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80011cc: b480 push {r7}
80011ce: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80011d0: bf00 nop
80011d2: e7fd b.n 80011d0 <HardFault_Handler+0x4>
080011d4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80011d4: b480 push {r7}
80011d6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80011d8: bf00 nop
80011da: e7fd b.n 80011d8 <MemManage_Handler+0x4>
080011dc <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80011dc: b480 push {r7}
80011de: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80011e0: bf00 nop
80011e2: e7fd b.n 80011e0 <BusFault_Handler+0x4>
080011e4 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80011e4: b480 push {r7}
80011e6: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80011e8: bf00 nop
80011ea: e7fd b.n 80011e8 <UsageFault_Handler+0x4>
080011ec <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80011ec: b480 push {r7}
80011ee: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
80011f0: bf00 nop
80011f2: 46bd mov sp, r7
80011f4: bc80 pop {r7}
80011f6: 4770 bx lr
080011f8 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80011f8: b480 push {r7}
80011fa: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80011fc: bf00 nop
80011fe: 46bd mov sp, r7
8001200: bc80 pop {r7}
8001202: 4770 bx lr
08001204 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001204: b480 push {r7}
8001206: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001208: bf00 nop
800120a: 46bd mov sp, r7
800120c: bc80 pop {r7}
800120e: 4770 bx lr
08001210 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001210: b580 push {r7, lr}
8001212: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001214: f000 f932 bl 800147c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001218: bf00 nop
800121a: bd80 pop {r7, pc}
0800121c <TIM2_IRQHandler>:
/**
* @brief This function handles TIM2 global interrupt.
*/
void TIM2_IRQHandler(void)
{
800121c: b580 push {r7, lr}
800121e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_IRQn 0 */
/* USER CODE END TIM2_IRQn 0 */
HAL_TIM_IRQHandler(&htim2);
8001220: 4802 ldr r0, [pc, #8] @ (800122c <TIM2_IRQHandler+0x10>)
8001222: f001 fdbb bl 8002d9c <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM2_IRQn 1 */
/* USER CODE END TIM2_IRQn 1 */
}
8001226: bf00 nop
8001228: bd80 pop {r7, pc}
800122a: bf00 nop
800122c: 20000084 .word 0x20000084
08001230 <TIM3_IRQHandler>:
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
8001230: b580 push {r7, lr}
8001232: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
HAL_TIM_IRQHandler(&htim3);
8001234: 4802 ldr r0, [pc, #8] @ (8001240 <TIM3_IRQHandler+0x10>)
8001236: f001 fdb1 bl 8002d9c <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM3_IRQn 1 */
/* USER CODE END TIM3_IRQn 1 */
}
800123a: bf00 nop
800123c: bd80 pop {r7, pc}
800123e: bf00 nop
8001240: 200000c4 .word 0x200000c4
08001244 <EXTI15_10_IRQHandler>:
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
8001244: b580 push {r7, lr}
8001246: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
8001248: f44f 6000 mov.w r0, #2048 @ 0x800
800124c: f000 fbe8 bl 8001a20 <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
8001250: f44f 5080 mov.w r0, #4096 @ 0x1000
8001254: f000 fbe4 bl 8001a20 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
8001258: bf00 nop
800125a: bd80 pop {r7, pc}
0800125c <SystemInit>:
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
800125c: b480 push {r7}
800125e: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001260: bf00 nop
8001262: 46bd mov sp, r7
8001264: bc80 pop {r7}
8001266: 4770 bx lr
08001268 <Reset_Handler>:
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8001268: f7ff fff8 bl 800125c <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
800126c: 480b ldr r0, [pc, #44] @ (800129c <LoopFillZerobss+0xe>)
ldr r1, =_edata
800126e: 490c ldr r1, [pc, #48] @ (80012a0 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8001270: 4a0c ldr r2, [pc, #48] @ (80012a4 <LoopFillZerobss+0x16>)
movs r3, #0
8001272: 2300 movs r3, #0
b LoopCopyDataInit
8001274: e002 b.n 800127c <LoopCopyDataInit>
08001276 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001276: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001278: 50c4 str r4, [r0, r3]
adds r3, r3, #4
800127a: 3304 adds r3, #4
0800127c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
800127c: 18c4 adds r4, r0, r3
cmp r4, r1
800127e: 428c cmp r4, r1
bcc CopyDataInit
8001280: d3f9 bcc.n 8001276 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001282: 4a09 ldr r2, [pc, #36] @ (80012a8 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8001284: 4c09 ldr r4, [pc, #36] @ (80012ac <LoopFillZerobss+0x1e>)
movs r3, #0
8001286: 2300 movs r3, #0
b LoopFillZerobss
8001288: e001 b.n 800128e <LoopFillZerobss>
0800128a <FillZerobss>:
FillZerobss:
str r3, [r2]
800128a: 6013 str r3, [r2, #0]
adds r2, r2, #4
800128c: 3204 adds r2, #4
0800128e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800128e: 42a2 cmp r2, r4
bcc FillZerobss
8001290: d3fb bcc.n 800128a <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001292: f002 fa89 bl 80037a8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001296: f7ff fc57 bl 8000b48 <main>
bx lr
800129a: 4770 bx lr
ldr r0, =_sdata
800129c: 20000000 .word 0x20000000
ldr r1, =_edata
80012a0: 20000010 .word 0x20000010
ldr r2, =_sidata
80012a4: 08003844 .word 0x08003844
ldr r2, =_sbss
80012a8: 20000010 .word 0x20000010
ldr r4, =_ebss
80012ac: 2000010c .word 0x2000010c
080012b0 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80012b0: e7fe b.n 80012b0 <ADC1_IRQHandler>
080012b2 <MAX7219_Init>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Init (void)
{
80012b2: b580 push {r7, lr}
80012b4: af00 add r7, sp, #0
// configure "LOAD" as output
MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits
80012b6: 2107 movs r1, #7
80012b8: 200b movs r0, #11
80012ba: f000 f85d bl 8001378 <MAX7219_Write>
MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits
80012be: 2100 movs r1, #0
80012c0: 2009 movs r0, #9
80012c2: f000 f859 bl 8001378 <MAX7219_Write>
MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown)
80012c6: f000 f809 bl 80012dc <MAX7219_ShutdownStop>
MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode)
80012ca: f000 f80f bl 80012ec <MAX7219_DisplayTestStop>
MAX7219_Clear(); // clear all digits
80012ce: f000 f827 bl 8001320 <MAX7219_Clear>
MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity
80012d2: 200f movs r0, #15
80012d4: f000 f812 bl 80012fc <MAX7219_SetBrightness>
}
80012d8: bf00 nop
80012da: bd80 pop {r7, pc}
080012dc <MAX7219_ShutdownStop>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_ShutdownStop (void)
{
80012dc: b580 push {r7, lr}
80012de: af00 add r7, sp, #0
MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode
80012e0: 2101 movs r1, #1
80012e2: 200c movs r0, #12
80012e4: f000 f848 bl 8001378 <MAX7219_Write>
}
80012e8: bf00 nop
80012ea: bd80 pop {r7, pc}
080012ec <MAX7219_DisplayTestStop>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_DisplayTestStop (void)
{
80012ec: b580 push {r7, lr}
80012ee: af00 add r7, sp, #0
MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode
80012f0: 2100 movs r1, #0
80012f2: 200f movs r0, #15
80012f4: f000 f840 bl 8001378 <MAX7219_Write>
}
80012f8: bf00 nop
80012fa: bd80 pop {r7, pc}
080012fc <MAX7219_SetBrightness>:
* Arguments : brightness (0-15)
* Returns : none
*********************************************************************************************************
*/
void MAX7219_SetBrightness (char brightness)
{
80012fc: b580 push {r7, lr}
80012fe: b082 sub sp, #8
8001300: af00 add r7, sp, #0
8001302: 4603 mov r3, r0
8001304: 71fb strb r3, [r7, #7]
brightness &= 0x0f; // mask off extra bits
8001306: 79fb ldrb r3, [r7, #7]
8001308: f003 030f and.w r3, r3, #15
800130c: 71fb strb r3, [r7, #7]
MAX7219_Write(REG_INTENSITY, brightness); // set brightness
800130e: 79fb ldrb r3, [r7, #7]
8001310: 4619 mov r1, r3
8001312: 200a movs r0, #10
8001314: f000 f830 bl 8001378 <MAX7219_Write>
}
8001318: bf00 nop
800131a: 3708 adds r7, #8
800131c: 46bd mov sp, r7
800131e: bd80 pop {r7, pc}
08001320 <MAX7219_Clear>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Clear (void)
{
8001320: b580 push {r7, lr}
8001322: b082 sub sp, #8
8001324: af00 add r7, sp, #0
char i;
for (i=0; i < 8; i++)
8001326: 2300 movs r3, #0
8001328: 71fb strb r3, [r7, #7]
800132a: e007 b.n 800133c <MAX7219_Clear+0x1c>
MAX7219_Write(i, 0x00); // turn all segments off
800132c: 79fb ldrb r3, [r7, #7]
800132e: 2100 movs r1, #0
8001330: 4618 mov r0, r3
8001332: f000 f821 bl 8001378 <MAX7219_Write>
for (i=0; i < 8; i++)
8001336: 79fb ldrb r3, [r7, #7]
8001338: 3301 adds r3, #1
800133a: 71fb strb r3, [r7, #7]
800133c: 79fb ldrb r3, [r7, #7]
800133e: 2b07 cmp r3, #7
8001340: d9f4 bls.n 800132c <MAX7219_Clear+0xc>
}
8001342: bf00 nop
8001344: bf00 nop
8001346: 3708 adds r7, #8
8001348: 46bd mov sp, r7
800134a: bd80 pop {r7, pc}
0800134c <MAX7219_DisplayChar>:
* character = character to display (0-9, A-Z)
* Returns : none
*********************************************************************************************************
*/
void MAX7219_DisplayChar(char digit, char character)
{
800134c: b580 push {r7, lr}
800134e: b082 sub sp, #8
8001350: af00 add r7, sp, #0
8001352: 4603 mov r3, r0
8001354: 460a mov r2, r1
8001356: 71fb strb r3, [r7, #7]
8001358: 4613 mov r3, r2
800135a: 71bb strb r3, [r7, #6]
//MAX7219_Write(digit, MAX7219_LookupCode(character));
MAX7219_Write(digit, conv_7seg[character]);
800135c: 79bb ldrb r3, [r7, #6]
800135e: 4a05 ldr r2, [pc, #20] @ (8001374 <MAX7219_DisplayChar+0x28>)
8001360: 5cd2 ldrb r2, [r2, r3]
8001362: 79fb ldrb r3, [r7, #7]
8001364: 4611 mov r1, r2
8001366: 4618 mov r0, r3
8001368: f000 f806 bl 8001378 <MAX7219_Write>
}
800136c: bf00 nop
800136e: 3708 adds r7, #8
8001370: 46bd mov sp, r7
8001372: bd80 pop {r7, pc}
8001374: 08003824 .word 0x08003824
08001378 <MAX7219_Write>:
* dataout = data to write to MAX7219
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Write (unsigned char reg_number, unsigned char dataout)
{
8001378: b580 push {r7, lr}
800137a: b082 sub sp, #8
800137c: af00 add r7, sp, #0
800137e: 4603 mov r3, r0
8001380: 460a mov r2, r1
8001382: 71fb strb r3, [r7, #7]
8001384: 4613 mov r3, r2
8001386: 71bb strb r3, [r7, #6]
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin
8001388: 4b09 ldr r3, [pc, #36] @ (80013b0 <MAX7219_Write+0x38>)
800138a: f44f 3280 mov.w r2, #65536 @ 0x10000
800138e: 619a str r2, [r3, #24]
MAX7219_SendByte(reg_number); // write register number to MAX7219
8001390: 79fb ldrb r3, [r7, #7]
8001392: 4618 mov r0, r3
8001394: f000 f80e bl 80013b4 <MAX7219_SendByte>
MAX7219_SendByte(dataout); // write data to MAX7219
8001398: 79bb ldrb r3, [r7, #6]
800139a: 4618 mov r0, r3
800139c: f000 f80a bl 80013b4 <MAX7219_SendByte>
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data
80013a0: 4b03 ldr r3, [pc, #12] @ (80013b0 <MAX7219_Write+0x38>)
80013a2: 2201 movs r2, #1
80013a4: 619a str r2, [r3, #24]
}
80013a6: bf00 nop
80013a8: 3708 adds r7, #8
80013aa: 46bd mov sp, r7
80013ac: bd80 pop {r7, pc}
80013ae: bf00 nop
80013b0: 40020800 .word 0x40020800
080013b4 <MAX7219_SendByte>:
* Returns : none
*********************************************************************************************************
*/
static void MAX7219_SendByte (unsigned char dataout)
{
80013b4: b580 push {r7, lr}
80013b6: b082 sub sp, #8
80013b8: af00 add r7, sp, #0
80013ba: 4603 mov r3, r0
80013bc: 71fb strb r3, [r7, #7]
HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000);
80013be: 1df9 adds r1, r7, #7
80013c0: f44f 737a mov.w r3, #1000 @ 0x3e8
80013c4: 2201 movs r2, #1
80013c6: 4803 ldr r0, [pc, #12] @ (80013d4 <MAX7219_SendByte+0x20>)
80013c8: f001 f957 bl 800267a <HAL_SPI_Transmit>
}
80013cc: bf00 nop
80013ce: 3708 adds r7, #8
80013d0: 46bd mov sp, r7
80013d2: bd80 pop {r7, pc}
80013d4: 2000002c .word 0x2000002c
080013d8 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80013d8: b580 push {r7, lr}
80013da: b082 sub sp, #8
80013dc: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
80013de: 2300 movs r3, #0
80013e0: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80013e2: 2003 movs r0, #3
80013e4: f000 f932 bl 800164c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
80013e8: 200f movs r0, #15
80013ea: f000 f80d bl 8001408 <HAL_InitTick>
80013ee: 4603 mov r3, r0
80013f0: 2b00 cmp r3, #0
80013f2: d002 beq.n 80013fa <HAL_Init+0x22>
{
status = HAL_ERROR;
80013f4: 2301 movs r3, #1
80013f6: 71fb strb r3, [r7, #7]
80013f8: e001 b.n 80013fe <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
80013fa: f7ff fddb bl 8000fb4 <HAL_MspInit>
}
/* Return function status */
return status;
80013fe: 79fb ldrb r3, [r7, #7]
}
8001400: 4618 mov r0, r3
8001402: 3708 adds r7, #8
8001404: 46bd mov sp, r7
8001406: bd80 pop {r7, pc}
08001408 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001408: b580 push {r7, lr}
800140a: b084 sub sp, #16
800140c: af00 add r7, sp, #0
800140e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001410: 2300 movs r3, #0
8001412: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8001414: 4b16 ldr r3, [pc, #88] @ (8001470 <HAL_InitTick+0x68>)
8001416: 681b ldr r3, [r3, #0]
8001418: 2b00 cmp r3, #0
800141a: d022 beq.n 8001462 <HAL_InitTick+0x5a>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
800141c: 4b15 ldr r3, [pc, #84] @ (8001474 <HAL_InitTick+0x6c>)
800141e: 681a ldr r2, [r3, #0]
8001420: 4b13 ldr r3, [pc, #76] @ (8001470 <HAL_InitTick+0x68>)
8001422: 681b ldr r3, [r3, #0]
8001424: f44f 717a mov.w r1, #1000 @ 0x3e8
8001428: fbb1 f3f3 udiv r3, r1, r3
800142c: fbb2 f3f3 udiv r3, r2, r3
8001430: 4618 mov r0, r3
8001432: f000 f940 bl 80016b6 <HAL_SYSTICK_Config>
8001436: 4603 mov r3, r0
8001438: 2b00 cmp r3, #0
800143a: d10f bne.n 800145c <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800143c: 687b ldr r3, [r7, #4]
800143e: 2b0f cmp r3, #15
8001440: d809 bhi.n 8001456 <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001442: 2200 movs r2, #0
8001444: 6879 ldr r1, [r7, #4]
8001446: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
800144a: f000 f90a bl 8001662 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800144e: 4a0a ldr r2, [pc, #40] @ (8001478 <HAL_InitTick+0x70>)
8001450: 687b ldr r3, [r7, #4]
8001452: 6013 str r3, [r2, #0]
8001454: e007 b.n 8001466 <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8001456: 2301 movs r3, #1
8001458: 73fb strb r3, [r7, #15]
800145a: e004 b.n 8001466 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
800145c: 2301 movs r3, #1
800145e: 73fb strb r3, [r7, #15]
8001460: e001 b.n 8001466 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001462: 2301 movs r3, #1
8001464: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001466: 7bfb ldrb r3, [r7, #15]
}
8001468: 4618 mov r0, r3
800146a: 3710 adds r7, #16
800146c: 46bd mov sp, r7
800146e: bd80 pop {r7, pc}
8001470: 2000000c .word 0x2000000c
8001474: 20000004 .word 0x20000004
8001478: 20000008 .word 0x20000008
0800147c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
800147c: b480 push {r7}
800147e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001480: 4b05 ldr r3, [pc, #20] @ (8001498 <HAL_IncTick+0x1c>)
8001482: 681a ldr r2, [r3, #0]
8001484: 4b05 ldr r3, [pc, #20] @ (800149c <HAL_IncTick+0x20>)
8001486: 681b ldr r3, [r3, #0]
8001488: 4413 add r3, r2
800148a: 4a03 ldr r2, [pc, #12] @ (8001498 <HAL_IncTick+0x1c>)
800148c: 6013 str r3, [r2, #0]
}
800148e: bf00 nop
8001490: 46bd mov sp, r7
8001492: bc80 pop {r7}
8001494: 4770 bx lr
8001496: bf00 nop
8001498: 20000108 .word 0x20000108
800149c: 2000000c .word 0x2000000c
080014a0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80014a0: b480 push {r7}
80014a2: af00 add r7, sp, #0
return uwTick;
80014a4: 4b02 ldr r3, [pc, #8] @ (80014b0 <HAL_GetTick+0x10>)
80014a6: 681b ldr r3, [r3, #0]
}
80014a8: 4618 mov r0, r3
80014aa: 46bd mov sp, r7
80014ac: bc80 pop {r7}
80014ae: 4770 bx lr
80014b0: 20000108 .word 0x20000108
080014b4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80014b4: b480 push {r7}
80014b6: b085 sub sp, #20
80014b8: af00 add r7, sp, #0
80014ba: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80014bc: 687b ldr r3, [r7, #4]
80014be: f003 0307 and.w r3, r3, #7
80014c2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80014c4: 4b0c ldr r3, [pc, #48] @ (80014f8 <__NVIC_SetPriorityGrouping+0x44>)
80014c6: 68db ldr r3, [r3, #12]
80014c8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80014ca: 68ba ldr r2, [r7, #8]
80014cc: f64f 03ff movw r3, #63743 @ 0xf8ff
80014d0: 4013 ands r3, r2
80014d2: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80014d4: 68fb ldr r3, [r7, #12]
80014d6: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80014d8: 68bb ldr r3, [r7, #8]
80014da: 4313 orrs r3, r2
reg_value = (reg_value |
80014dc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80014e0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80014e4: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80014e6: 4a04 ldr r2, [pc, #16] @ (80014f8 <__NVIC_SetPriorityGrouping+0x44>)
80014e8: 68bb ldr r3, [r7, #8]
80014ea: 60d3 str r3, [r2, #12]
}
80014ec: bf00 nop
80014ee: 3714 adds r7, #20
80014f0: 46bd mov sp, r7
80014f2: bc80 pop {r7}
80014f4: 4770 bx lr
80014f6: bf00 nop
80014f8: e000ed00 .word 0xe000ed00
080014fc <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80014fc: b480 push {r7}
80014fe: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001500: 4b04 ldr r3, [pc, #16] @ (8001514 <__NVIC_GetPriorityGrouping+0x18>)
8001502: 68db ldr r3, [r3, #12]
8001504: 0a1b lsrs r3, r3, #8
8001506: f003 0307 and.w r3, r3, #7
}
800150a: 4618 mov r0, r3
800150c: 46bd mov sp, r7
800150e: bc80 pop {r7}
8001510: 4770 bx lr
8001512: bf00 nop
8001514: e000ed00 .word 0xe000ed00
08001518 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001518: b480 push {r7}
800151a: b083 sub sp, #12
800151c: af00 add r7, sp, #0
800151e: 4603 mov r3, r0
8001520: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8001522: f997 3007 ldrsb.w r3, [r7, #7]
8001526: 2b00 cmp r3, #0
8001528: db0b blt.n 8001542 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800152a: 79fb ldrb r3, [r7, #7]
800152c: f003 021f and.w r2, r3, #31
8001530: 4906 ldr r1, [pc, #24] @ (800154c <__NVIC_EnableIRQ+0x34>)
8001532: f997 3007 ldrsb.w r3, [r7, #7]
8001536: 095b lsrs r3, r3, #5
8001538: 2001 movs r0, #1
800153a: fa00 f202 lsl.w r2, r0, r2
800153e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8001542: bf00 nop
8001544: 370c adds r7, #12
8001546: 46bd mov sp, r7
8001548: bc80 pop {r7}
800154a: 4770 bx lr
800154c: e000e100 .word 0xe000e100
08001550 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001550: b480 push {r7}
8001552: b083 sub sp, #12
8001554: af00 add r7, sp, #0
8001556: 4603 mov r3, r0
8001558: 6039 str r1, [r7, #0]
800155a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800155c: f997 3007 ldrsb.w r3, [r7, #7]
8001560: 2b00 cmp r3, #0
8001562: db0a blt.n 800157a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001564: 683b ldr r3, [r7, #0]
8001566: b2da uxtb r2, r3
8001568: 490c ldr r1, [pc, #48] @ (800159c <__NVIC_SetPriority+0x4c>)
800156a: f997 3007 ldrsb.w r3, [r7, #7]
800156e: 0112 lsls r2, r2, #4
8001570: b2d2 uxtb r2, r2
8001572: 440b add r3, r1
8001574: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001578: e00a b.n 8001590 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800157a: 683b ldr r3, [r7, #0]
800157c: b2da uxtb r2, r3
800157e: 4908 ldr r1, [pc, #32] @ (80015a0 <__NVIC_SetPriority+0x50>)
8001580: 79fb ldrb r3, [r7, #7]
8001582: f003 030f and.w r3, r3, #15
8001586: 3b04 subs r3, #4
8001588: 0112 lsls r2, r2, #4
800158a: b2d2 uxtb r2, r2
800158c: 440b add r3, r1
800158e: 761a strb r2, [r3, #24]
}
8001590: bf00 nop
8001592: 370c adds r7, #12
8001594: 46bd mov sp, r7
8001596: bc80 pop {r7}
8001598: 4770 bx lr
800159a: bf00 nop
800159c: e000e100 .word 0xe000e100
80015a0: e000ed00 .word 0xe000ed00
080015a4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80015a4: b480 push {r7}
80015a6: b089 sub sp, #36 @ 0x24
80015a8: af00 add r7, sp, #0
80015aa: 60f8 str r0, [r7, #12]
80015ac: 60b9 str r1, [r7, #8]
80015ae: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80015b0: 68fb ldr r3, [r7, #12]
80015b2: f003 0307 and.w r3, r3, #7
80015b6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80015b8: 69fb ldr r3, [r7, #28]
80015ba: f1c3 0307 rsb r3, r3, #7
80015be: 2b04 cmp r3, #4
80015c0: bf28 it cs
80015c2: 2304 movcs r3, #4
80015c4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80015c6: 69fb ldr r3, [r7, #28]
80015c8: 3304 adds r3, #4
80015ca: 2b06 cmp r3, #6
80015cc: d902 bls.n 80015d4 <NVIC_EncodePriority+0x30>
80015ce: 69fb ldr r3, [r7, #28]
80015d0: 3b03 subs r3, #3
80015d2: e000 b.n 80015d6 <NVIC_EncodePriority+0x32>
80015d4: 2300 movs r3, #0
80015d6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80015d8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80015dc: 69bb ldr r3, [r7, #24]
80015de: fa02 f303 lsl.w r3, r2, r3
80015e2: 43da mvns r2, r3
80015e4: 68bb ldr r3, [r7, #8]
80015e6: 401a ands r2, r3
80015e8: 697b ldr r3, [r7, #20]
80015ea: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80015ec: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
80015f0: 697b ldr r3, [r7, #20]
80015f2: fa01 f303 lsl.w r3, r1, r3
80015f6: 43d9 mvns r1, r3
80015f8: 687b ldr r3, [r7, #4]
80015fa: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80015fc: 4313 orrs r3, r2
);
}
80015fe: 4618 mov r0, r3
8001600: 3724 adds r7, #36 @ 0x24
8001602: 46bd mov sp, r7
8001604: bc80 pop {r7}
8001606: 4770 bx lr
08001608 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001608: b580 push {r7, lr}
800160a: b082 sub sp, #8
800160c: af00 add r7, sp, #0
800160e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001610: 687b ldr r3, [r7, #4]
8001612: 3b01 subs r3, #1
8001614: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8001618: d301 bcc.n 800161e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
800161a: 2301 movs r3, #1
800161c: e00f b.n 800163e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800161e: 4a0a ldr r2, [pc, #40] @ (8001648 <SysTick_Config+0x40>)
8001620: 687b ldr r3, [r7, #4]
8001622: 3b01 subs r3, #1
8001624: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001626: 210f movs r1, #15
8001628: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
800162c: f7ff ff90 bl 8001550 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001630: 4b05 ldr r3, [pc, #20] @ (8001648 <SysTick_Config+0x40>)
8001632: 2200 movs r2, #0
8001634: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001636: 4b04 ldr r3, [pc, #16] @ (8001648 <SysTick_Config+0x40>)
8001638: 2207 movs r2, #7
800163a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
800163c: 2300 movs r3, #0
}
800163e: 4618 mov r0, r3
8001640: 3708 adds r7, #8
8001642: 46bd mov sp, r7
8001644: bd80 pop {r7, pc}
8001646: bf00 nop
8001648: e000e010 .word 0xe000e010
0800164c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800164c: b580 push {r7, lr}
800164e: b082 sub sp, #8
8001650: af00 add r7, sp, #0
8001652: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001654: 6878 ldr r0, [r7, #4]
8001656: f7ff ff2d bl 80014b4 <__NVIC_SetPriorityGrouping>
}
800165a: bf00 nop
800165c: 3708 adds r7, #8
800165e: 46bd mov sp, r7
8001660: bd80 pop {r7, pc}
08001662 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001662: b580 push {r7, lr}
8001664: b086 sub sp, #24
8001666: af00 add r7, sp, #0
8001668: 4603 mov r3, r0
800166a: 60b9 str r1, [r7, #8]
800166c: 607a str r2, [r7, #4]
800166e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8001670: 2300 movs r3, #0
8001672: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001674: f7ff ff42 bl 80014fc <__NVIC_GetPriorityGrouping>
8001678: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800167a: 687a ldr r2, [r7, #4]
800167c: 68b9 ldr r1, [r7, #8]
800167e: 6978 ldr r0, [r7, #20]
8001680: f7ff ff90 bl 80015a4 <NVIC_EncodePriority>
8001684: 4602 mov r2, r0
8001686: f997 300f ldrsb.w r3, [r7, #15]
800168a: 4611 mov r1, r2
800168c: 4618 mov r0, r3
800168e: f7ff ff5f bl 8001550 <__NVIC_SetPriority>
}
8001692: bf00 nop
8001694: 3718 adds r7, #24
8001696: 46bd mov sp, r7
8001698: bd80 pop {r7, pc}
0800169a <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800169a: b580 push {r7, lr}
800169c: b082 sub sp, #8
800169e: af00 add r7, sp, #0
80016a0: 4603 mov r3, r0
80016a2: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80016a4: f997 3007 ldrsb.w r3, [r7, #7]
80016a8: 4618 mov r0, r3
80016aa: f7ff ff35 bl 8001518 <__NVIC_EnableIRQ>
}
80016ae: bf00 nop
80016b0: 3708 adds r7, #8
80016b2: 46bd mov sp, r7
80016b4: bd80 pop {r7, pc}
080016b6 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80016b6: b580 push {r7, lr}
80016b8: b082 sub sp, #8
80016ba: af00 add r7, sp, #0
80016bc: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80016be: 6878 ldr r0, [r7, #4]
80016c0: f7ff ffa2 bl 8001608 <SysTick_Config>
80016c4: 4603 mov r3, r0
}
80016c6: 4618 mov r0, r3
80016c8: 3708 adds r7, #8
80016ca: 46bd mov sp, r7
80016cc: bd80 pop {r7, pc}
...
080016d0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80016d0: b480 push {r7}
80016d2: b087 sub sp, #28
80016d4: af00 add r7, sp, #0
80016d6: 6078 str r0, [r7, #4]
80016d8: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
80016da: 2300 movs r3, #0
80016dc: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
80016de: 2300 movs r3, #0
80016e0: 60fb str r3, [r7, #12]
uint32_t temp = 0x00;
80016e2: 2300 movs r3, #0
80016e4: 613b str r3, [r7, #16]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0)
80016e6: e160 b.n 80019aa <HAL_GPIO_Init+0x2da>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
80016e8: 683b ldr r3, [r7, #0]
80016ea: 681a ldr r2, [r3, #0]
80016ec: 2101 movs r1, #1
80016ee: 697b ldr r3, [r7, #20]
80016f0: fa01 f303 lsl.w r3, r1, r3
80016f4: 4013 ands r3, r2
80016f6: 60fb str r3, [r7, #12]
if (iocurrent)
80016f8: 68fb ldr r3, [r7, #12]
80016fa: 2b00 cmp r3, #0
80016fc: f000 8152 beq.w 80019a4 <HAL_GPIO_Init+0x2d4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001700: 683b ldr r3, [r7, #0]
8001702: 685b ldr r3, [r3, #4]
8001704: f003 0303 and.w r3, r3, #3
8001708: 2b01 cmp r3, #1
800170a: d005 beq.n 8001718 <HAL_GPIO_Init+0x48>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
800170c: 683b ldr r3, [r7, #0]
800170e: 685b ldr r3, [r3, #4]
8001710: f003 0303 and.w r3, r3, #3
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001714: 2b02 cmp r3, #2
8001716: d130 bne.n 800177a <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001718: 687b ldr r3, [r7, #4]
800171a: 689b ldr r3, [r3, #8]
800171c: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
800171e: 697b ldr r3, [r7, #20]
8001720: 005b lsls r3, r3, #1
8001722: 2203 movs r2, #3
8001724: fa02 f303 lsl.w r3, r2, r3
8001728: 43db mvns r3, r3
800172a: 693a ldr r2, [r7, #16]
800172c: 4013 ands r3, r2
800172e: 613b str r3, [r7, #16]
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
8001730: 683b ldr r3, [r7, #0]
8001732: 68da ldr r2, [r3, #12]
8001734: 697b ldr r3, [r7, #20]
8001736: 005b lsls r3, r3, #1
8001738: fa02 f303 lsl.w r3, r2, r3
800173c: 693a ldr r2, [r7, #16]
800173e: 4313 orrs r3, r2
8001740: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001742: 687b ldr r3, [r7, #4]
8001744: 693a ldr r2, [r7, #16]
8001746: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001748: 687b ldr r3, [r7, #4]
800174a: 685b ldr r3, [r3, #4]
800174c: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
800174e: 2201 movs r2, #1
8001750: 697b ldr r3, [r7, #20]
8001752: fa02 f303 lsl.w r3, r2, r3
8001756: 43db mvns r3, r3
8001758: 693a ldr r2, [r7, #16]
800175a: 4013 ands r3, r2
800175c: 613b str r3, [r7, #16]
SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800175e: 683b ldr r3, [r7, #0]
8001760: 685b ldr r3, [r3, #4]
8001762: 091b lsrs r3, r3, #4
8001764: f003 0201 and.w r2, r3, #1
8001768: 697b ldr r3, [r7, #20]
800176a: fa02 f303 lsl.w r3, r2, r3
800176e: 693a ldr r2, [r7, #16]
8001770: 4313 orrs r3, r2
8001772: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001774: 687b ldr r3, [r7, #4]
8001776: 693a ldr r2, [r7, #16]
8001778: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
800177a: 683b ldr r3, [r7, #0]
800177c: 685b ldr r3, [r3, #4]
800177e: f003 0303 and.w r3, r3, #3
8001782: 2b03 cmp r3, #3
8001784: d017 beq.n 80017b6 <HAL_GPIO_Init+0xe6>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001786: 687b ldr r3, [r7, #4]
8001788: 68db ldr r3, [r3, #12]
800178a: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
800178c: 697b ldr r3, [r7, #20]
800178e: 005b lsls r3, r3, #1
8001790: 2203 movs r2, #3
8001792: fa02 f303 lsl.w r3, r2, r3
8001796: 43db mvns r3, r3
8001798: 693a ldr r2, [r7, #16]
800179a: 4013 ands r3, r2
800179c: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
800179e: 683b ldr r3, [r7, #0]
80017a0: 689a ldr r2, [r3, #8]
80017a2: 697b ldr r3, [r7, #20]
80017a4: 005b lsls r3, r3, #1
80017a6: fa02 f303 lsl.w r3, r2, r3
80017aa: 693a ldr r2, [r7, #16]
80017ac: 4313 orrs r3, r2
80017ae: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80017b0: 687b ldr r3, [r7, #4]
80017b2: 693a ldr r2, [r7, #16]
80017b4: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80017b6: 683b ldr r3, [r7, #0]
80017b8: 685b ldr r3, [r3, #4]
80017ba: f003 0303 and.w r3, r3, #3
80017be: 2b02 cmp r3, #2
80017c0: d123 bne.n 800180a <HAL_GPIO_Init+0x13a>
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
/* Identify AFRL or AFRH register based on IO position*/
temp = GPIOx->AFR[position >> 3];
80017c2: 697b ldr r3, [r7, #20]
80017c4: 08da lsrs r2, r3, #3
80017c6: 687b ldr r3, [r7, #4]
80017c8: 3208 adds r2, #8
80017ca: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80017ce: 613b str r3, [r7, #16]
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
80017d0: 697b ldr r3, [r7, #20]
80017d2: f003 0307 and.w r3, r3, #7
80017d6: 009b lsls r3, r3, #2
80017d8: 220f movs r2, #15
80017da: fa02 f303 lsl.w r3, r2, r3
80017de: 43db mvns r3, r3
80017e0: 693a ldr r2, [r7, #16]
80017e2: 4013 ands r3, r2
80017e4: 613b str r3, [r7, #16]
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
80017e6: 683b ldr r3, [r7, #0]
80017e8: 691a ldr r2, [r3, #16]
80017ea: 697b ldr r3, [r7, #20]
80017ec: f003 0307 and.w r3, r3, #7
80017f0: 009b lsls r3, r3, #2
80017f2: fa02 f303 lsl.w r3, r2, r3
80017f6: 693a ldr r2, [r7, #16]
80017f8: 4313 orrs r3, r2
80017fa: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3] = temp;
80017fc: 697b ldr r3, [r7, #20]
80017fe: 08da lsrs r2, r3, #3
8001800: 687b ldr r3, [r7, #4]
8001802: 3208 adds r2, #8
8001804: 6939 ldr r1, [r7, #16]
8001806: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800180a: 687b ldr r3, [r7, #4]
800180c: 681b ldr r3, [r3, #0]
800180e: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
8001810: 697b ldr r3, [r7, #20]
8001812: 005b lsls r3, r3, #1
8001814: 2203 movs r2, #3
8001816: fa02 f303 lsl.w r3, r2, r3
800181a: 43db mvns r3, r3
800181c: 693a ldr r2, [r7, #16]
800181e: 4013 ands r3, r2
8001820: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8001822: 683b ldr r3, [r7, #0]
8001824: 685b ldr r3, [r3, #4]
8001826: f003 0203 and.w r2, r3, #3
800182a: 697b ldr r3, [r7, #20]
800182c: 005b lsls r3, r3, #1
800182e: fa02 f303 lsl.w r3, r2, r3
8001832: 693a ldr r2, [r7, #16]
8001834: 4313 orrs r3, r2
8001836: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001838: 687b ldr r3, [r7, #4]
800183a: 693a ldr r2, [r7, #16]
800183c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
800183e: 683b ldr r3, [r7, #0]
8001840: 685b ldr r3, [r3, #4]
8001842: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001846: 2b00 cmp r3, #0
8001848: f000 80ac beq.w 80019a4 <HAL_GPIO_Init+0x2d4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800184c: 4b5e ldr r3, [pc, #376] @ (80019c8 <HAL_GPIO_Init+0x2f8>)
800184e: 6a1b ldr r3, [r3, #32]
8001850: 4a5d ldr r2, [pc, #372] @ (80019c8 <HAL_GPIO_Init+0x2f8>)
8001852: f043 0301 orr.w r3, r3, #1
8001856: 6213 str r3, [r2, #32]
8001858: 4b5b ldr r3, [pc, #364] @ (80019c8 <HAL_GPIO_Init+0x2f8>)
800185a: 6a1b ldr r3, [r3, #32]
800185c: f003 0301 and.w r3, r3, #1
8001860: 60bb str r3, [r7, #8]
8001862: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2];
8001864: 4a59 ldr r2, [pc, #356] @ (80019cc <HAL_GPIO_Init+0x2fc>)
8001866: 697b ldr r3, [r7, #20]
8001868: 089b lsrs r3, r3, #2
800186a: 3302 adds r3, #2
800186c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001870: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
8001872: 697b ldr r3, [r7, #20]
8001874: f003 0303 and.w r3, r3, #3
8001878: 009b lsls r3, r3, #2
800187a: 220f movs r2, #15
800187c: fa02 f303 lsl.w r3, r2, r3
8001880: 43db mvns r3, r3
8001882: 693a ldr r2, [r7, #16]
8001884: 4013 ands r3, r2
8001886: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8001888: 687b ldr r3, [r7, #4]
800188a: 4a51 ldr r2, [pc, #324] @ (80019d0 <HAL_GPIO_Init+0x300>)
800188c: 4293 cmp r3, r2
800188e: d025 beq.n 80018dc <HAL_GPIO_Init+0x20c>
8001890: 687b ldr r3, [r7, #4]
8001892: 4a50 ldr r2, [pc, #320] @ (80019d4 <HAL_GPIO_Init+0x304>)
8001894: 4293 cmp r3, r2
8001896: d01f beq.n 80018d8 <HAL_GPIO_Init+0x208>
8001898: 687b ldr r3, [r7, #4]
800189a: 4a4f ldr r2, [pc, #316] @ (80019d8 <HAL_GPIO_Init+0x308>)
800189c: 4293 cmp r3, r2
800189e: d019 beq.n 80018d4 <HAL_GPIO_Init+0x204>
80018a0: 687b ldr r3, [r7, #4]
80018a2: 4a4e ldr r2, [pc, #312] @ (80019dc <HAL_GPIO_Init+0x30c>)
80018a4: 4293 cmp r3, r2
80018a6: d013 beq.n 80018d0 <HAL_GPIO_Init+0x200>
80018a8: 687b ldr r3, [r7, #4]
80018aa: 4a4d ldr r2, [pc, #308] @ (80019e0 <HAL_GPIO_Init+0x310>)
80018ac: 4293 cmp r3, r2
80018ae: d00d beq.n 80018cc <HAL_GPIO_Init+0x1fc>
80018b0: 687b ldr r3, [r7, #4]
80018b2: 4a4c ldr r2, [pc, #304] @ (80019e4 <HAL_GPIO_Init+0x314>)
80018b4: 4293 cmp r3, r2
80018b6: d007 beq.n 80018c8 <HAL_GPIO_Init+0x1f8>
80018b8: 687b ldr r3, [r7, #4]
80018ba: 4a4b ldr r2, [pc, #300] @ (80019e8 <HAL_GPIO_Init+0x318>)
80018bc: 4293 cmp r3, r2
80018be: d101 bne.n 80018c4 <HAL_GPIO_Init+0x1f4>
80018c0: 2306 movs r3, #6
80018c2: e00c b.n 80018de <HAL_GPIO_Init+0x20e>
80018c4: 2307 movs r3, #7
80018c6: e00a b.n 80018de <HAL_GPIO_Init+0x20e>
80018c8: 2305 movs r3, #5
80018ca: e008 b.n 80018de <HAL_GPIO_Init+0x20e>
80018cc: 2304 movs r3, #4
80018ce: e006 b.n 80018de <HAL_GPIO_Init+0x20e>
80018d0: 2303 movs r3, #3
80018d2: e004 b.n 80018de <HAL_GPIO_Init+0x20e>
80018d4: 2302 movs r3, #2
80018d6: e002 b.n 80018de <HAL_GPIO_Init+0x20e>
80018d8: 2301 movs r3, #1
80018da: e000 b.n 80018de <HAL_GPIO_Init+0x20e>
80018dc: 2300 movs r3, #0
80018de: 697a ldr r2, [r7, #20]
80018e0: f002 0203 and.w r2, r2, #3
80018e4: 0092 lsls r2, r2, #2
80018e6: 4093 lsls r3, r2
80018e8: 693a ldr r2, [r7, #16]
80018ea: 4313 orrs r3, r2
80018ec: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2] = temp;
80018ee: 4937 ldr r1, [pc, #220] @ (80019cc <HAL_GPIO_Init+0x2fc>)
80018f0: 697b ldr r3, [r7, #20]
80018f2: 089b lsrs r3, r3, #2
80018f4: 3302 adds r3, #2
80018f6: 693a ldr r2, [r7, #16]
80018f8: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80018fc: 4b3b ldr r3, [pc, #236] @ (80019ec <HAL_GPIO_Init+0x31c>)
80018fe: 689b ldr r3, [r3, #8]
8001900: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8001902: 68fb ldr r3, [r7, #12]
8001904: 43db mvns r3, r3
8001906: 693a ldr r2, [r7, #16]
8001908: 4013 ands r3, r2
800190a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
800190c: 683b ldr r3, [r7, #0]
800190e: 685b ldr r3, [r3, #4]
8001910: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001914: 2b00 cmp r3, #0
8001916: d003 beq.n 8001920 <HAL_GPIO_Init+0x250>
{
SET_BIT(temp, iocurrent);
8001918: 693a ldr r2, [r7, #16]
800191a: 68fb ldr r3, [r7, #12]
800191c: 4313 orrs r3, r2
800191e: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8001920: 4a32 ldr r2, [pc, #200] @ (80019ec <HAL_GPIO_Init+0x31c>)
8001922: 693b ldr r3, [r7, #16]
8001924: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001926: 4b31 ldr r3, [pc, #196] @ (80019ec <HAL_GPIO_Init+0x31c>)
8001928: 68db ldr r3, [r3, #12]
800192a: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
800192c: 68fb ldr r3, [r7, #12]
800192e: 43db mvns r3, r3
8001930: 693a ldr r2, [r7, #16]
8001932: 4013 ands r3, r2
8001934: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001936: 683b ldr r3, [r7, #0]
8001938: 685b ldr r3, [r3, #4]
800193a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800193e: 2b00 cmp r3, #0
8001940: d003 beq.n 800194a <HAL_GPIO_Init+0x27a>
{
SET_BIT(temp, iocurrent);
8001942: 693a ldr r2, [r7, #16]
8001944: 68fb ldr r3, [r7, #12]
8001946: 4313 orrs r3, r2
8001948: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
800194a: 4a28 ldr r2, [pc, #160] @ (80019ec <HAL_GPIO_Init+0x31c>)
800194c: 693b ldr r3, [r7, #16]
800194e: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001950: 4b26 ldr r3, [pc, #152] @ (80019ec <HAL_GPIO_Init+0x31c>)
8001952: 685b ldr r3, [r3, #4]
8001954: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8001956: 68fb ldr r3, [r7, #12]
8001958: 43db mvns r3, r3
800195a: 693a ldr r2, [r7, #16]
800195c: 4013 ands r3, r2
800195e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8001960: 683b ldr r3, [r7, #0]
8001962: 685b ldr r3, [r3, #4]
8001964: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001968: 2b00 cmp r3, #0
800196a: d003 beq.n 8001974 <HAL_GPIO_Init+0x2a4>
{
SET_BIT(temp, iocurrent);
800196c: 693a ldr r2, [r7, #16]
800196e: 68fb ldr r3, [r7, #12]
8001970: 4313 orrs r3, r2
8001972: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8001974: 4a1d ldr r2, [pc, #116] @ (80019ec <HAL_GPIO_Init+0x31c>)
8001976: 693b ldr r3, [r7, #16]
8001978: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
800197a: 4b1c ldr r3, [pc, #112] @ (80019ec <HAL_GPIO_Init+0x31c>)
800197c: 681b ldr r3, [r3, #0]
800197e: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8001980: 68fb ldr r3, [r7, #12]
8001982: 43db mvns r3, r3
8001984: 693a ldr r2, [r7, #16]
8001986: 4013 ands r3, r2
8001988: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
800198a: 683b ldr r3, [r7, #0]
800198c: 685b ldr r3, [r3, #4]
800198e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001992: 2b00 cmp r3, #0
8001994: d003 beq.n 800199e <HAL_GPIO_Init+0x2ce>
{
SET_BIT(temp, iocurrent);
8001996: 693a ldr r2, [r7, #16]
8001998: 68fb ldr r3, [r7, #12]
800199a: 4313 orrs r3, r2
800199c: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
800199e: 4a13 ldr r2, [pc, #76] @ (80019ec <HAL_GPIO_Init+0x31c>)
80019a0: 693b ldr r3, [r7, #16]
80019a2: 6013 str r3, [r2, #0]
}
}
position++;
80019a4: 697b ldr r3, [r7, #20]
80019a6: 3301 adds r3, #1
80019a8: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0)
80019aa: 683b ldr r3, [r7, #0]
80019ac: 681a ldr r2, [r3, #0]
80019ae: 697b ldr r3, [r7, #20]
80019b0: fa22 f303 lsr.w r3, r2, r3
80019b4: 2b00 cmp r3, #0
80019b6: f47f ae97 bne.w 80016e8 <HAL_GPIO_Init+0x18>
}
}
80019ba: bf00 nop
80019bc: bf00 nop
80019be: 371c adds r7, #28
80019c0: 46bd mov sp, r7
80019c2: bc80 pop {r7}
80019c4: 4770 bx lr
80019c6: bf00 nop
80019c8: 40023800 .word 0x40023800
80019cc: 40010000 .word 0x40010000
80019d0: 40020000 .word 0x40020000
80019d4: 40020400 .word 0x40020400
80019d8: 40020800 .word 0x40020800
80019dc: 40020c00 .word 0x40020c00
80019e0: 40021000 .word 0x40021000
80019e4: 40021400 .word 0x40021400
80019e8: 40021800 .word 0x40021800
80019ec: 40010400 .word 0x40010400
080019f0 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80019f0: b480 push {r7}
80019f2: b083 sub sp, #12
80019f4: af00 add r7, sp, #0
80019f6: 6078 str r0, [r7, #4]
80019f8: 460b mov r3, r1
80019fa: 807b strh r3, [r7, #2]
80019fc: 4613 mov r3, r2
80019fe: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001a00: 787b ldrb r3, [r7, #1]
8001a02: 2b00 cmp r3, #0
8001a04: d003 beq.n 8001a0e <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001a06: 887a ldrh r2, [r7, #2]
8001a08: 687b ldr r3, [r7, #4]
8001a0a: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
}
}
8001a0c: e003 b.n 8001a16 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
8001a0e: 887b ldrh r3, [r7, #2]
8001a10: 041a lsls r2, r3, #16
8001a12: 687b ldr r3, [r7, #4]
8001a14: 619a str r2, [r3, #24]
}
8001a16: bf00 nop
8001a18: 370c adds r7, #12
8001a1a: 46bd mov sp, r7
8001a1c: bc80 pop {r7}
8001a1e: 4770 bx lr
08001a20 <HAL_GPIO_EXTI_IRQHandler>:
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
8001a20: b580 push {r7, lr}
8001a22: b082 sub sp, #8
8001a24: af00 add r7, sp, #0
8001a26: 4603 mov r3, r0
8001a28: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
8001a2a: 4b08 ldr r3, [pc, #32] @ (8001a4c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8001a2c: 695a ldr r2, [r3, #20]
8001a2e: 88fb ldrh r3, [r7, #6]
8001a30: 4013 ands r3, r2
8001a32: 2b00 cmp r3, #0
8001a34: d006 beq.n 8001a44 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8001a36: 4a05 ldr r2, [pc, #20] @ (8001a4c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8001a38: 88fb ldrh r3, [r7, #6]
8001a3a: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8001a3c: 88fb ldrh r3, [r7, #6]
8001a3e: 4618 mov r0, r3
8001a40: f000 f806 bl 8001a50 <HAL_GPIO_EXTI_Callback>
}
}
8001a44: bf00 nop
8001a46: 3708 adds r7, #8
8001a48: 46bd mov sp, r7
8001a4a: bd80 pop {r7, pc}
8001a4c: 40010400 .word 0x40010400
08001a50 <HAL_GPIO_EXTI_Callback>:
* @brief EXTI line detection callbacks.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8001a50: b480 push {r7}
8001a52: b083 sub sp, #12
8001a54: af00 add r7, sp, #0
8001a56: 4603 mov r3, r0
8001a58: 80fb strh r3, [r7, #6]
UNUSED(GPIO_Pin);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
8001a5a: bf00 nop
8001a5c: 370c adds r7, #12
8001a5e: 46bd mov sp, r7
8001a60: bc80 pop {r7}
8001a62: 4770 bx lr
08001a64 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001a64: b580 push {r7, lr}
8001a66: b088 sub sp, #32
8001a68: af00 add r7, sp, #0
8001a6a: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check the parameters */
if(RCC_OscInitStruct == NULL)
8001a6c: 687b ldr r3, [r7, #4]
8001a6e: 2b00 cmp r3, #0
8001a70: d101 bne.n 8001a76 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8001a72: 2301 movs r3, #1
8001a74: e31d b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
}
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8001a76: 4b94 ldr r3, [pc, #592] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001a78: 689b ldr r3, [r3, #8]
8001a7a: f003 030c and.w r3, r3, #12
8001a7e: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
8001a80: 4b91 ldr r3, [pc, #580] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001a82: 689b ldr r3, [r3, #8]
8001a84: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001a88: 617b str r3, [r7, #20]
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001a8a: 687b ldr r3, [r7, #4]
8001a8c: 681b ldr r3, [r3, #0]
8001a8e: f003 0301 and.w r3, r3, #1
8001a92: 2b00 cmp r3, #0
8001a94: d07b beq.n 8001b8e <HAL_RCC_OscConfig+0x12a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
8001a96: 69bb ldr r3, [r7, #24]
8001a98: 2b08 cmp r3, #8
8001a9a: d006 beq.n 8001aaa <HAL_RCC_OscConfig+0x46>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
8001a9c: 69bb ldr r3, [r7, #24]
8001a9e: 2b0c cmp r3, #12
8001aa0: d10f bne.n 8001ac2 <HAL_RCC_OscConfig+0x5e>
8001aa2: 697b ldr r3, [r7, #20]
8001aa4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001aa8: d10b bne.n 8001ac2 <HAL_RCC_OscConfig+0x5e>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001aaa: 4b87 ldr r3, [pc, #540] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001aac: 681b ldr r3, [r3, #0]
8001aae: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001ab2: 2b00 cmp r3, #0
8001ab4: d06a beq.n 8001b8c <HAL_RCC_OscConfig+0x128>
8001ab6: 687b ldr r3, [r7, #4]
8001ab8: 685b ldr r3, [r3, #4]
8001aba: 2b00 cmp r3, #0
8001abc: d166 bne.n 8001b8c <HAL_RCC_OscConfig+0x128>
{
return HAL_ERROR;
8001abe: 2301 movs r3, #1
8001ac0: e2f7 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001ac2: 687b ldr r3, [r7, #4]
8001ac4: 685b ldr r3, [r3, #4]
8001ac6: 2b01 cmp r3, #1
8001ac8: d106 bne.n 8001ad8 <HAL_RCC_OscConfig+0x74>
8001aca: 4b7f ldr r3, [pc, #508] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001acc: 681b ldr r3, [r3, #0]
8001ace: 4a7e ldr r2, [pc, #504] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001ad0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001ad4: 6013 str r3, [r2, #0]
8001ad6: e02d b.n 8001b34 <HAL_RCC_OscConfig+0xd0>
8001ad8: 687b ldr r3, [r7, #4]
8001ada: 685b ldr r3, [r3, #4]
8001adc: 2b00 cmp r3, #0
8001ade: d10c bne.n 8001afa <HAL_RCC_OscConfig+0x96>
8001ae0: 4b79 ldr r3, [pc, #484] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001ae2: 681b ldr r3, [r3, #0]
8001ae4: 4a78 ldr r2, [pc, #480] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001ae6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001aea: 6013 str r3, [r2, #0]
8001aec: 4b76 ldr r3, [pc, #472] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001aee: 681b ldr r3, [r3, #0]
8001af0: 4a75 ldr r2, [pc, #468] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001af2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001af6: 6013 str r3, [r2, #0]
8001af8: e01c b.n 8001b34 <HAL_RCC_OscConfig+0xd0>
8001afa: 687b ldr r3, [r7, #4]
8001afc: 685b ldr r3, [r3, #4]
8001afe: 2b05 cmp r3, #5
8001b00: d10c bne.n 8001b1c <HAL_RCC_OscConfig+0xb8>
8001b02: 4b71 ldr r3, [pc, #452] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b04: 681b ldr r3, [r3, #0]
8001b06: 4a70 ldr r2, [pc, #448] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b08: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8001b0c: 6013 str r3, [r2, #0]
8001b0e: 4b6e ldr r3, [pc, #440] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b10: 681b ldr r3, [r3, #0]
8001b12: 4a6d ldr r2, [pc, #436] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b14: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001b18: 6013 str r3, [r2, #0]
8001b1a: e00b b.n 8001b34 <HAL_RCC_OscConfig+0xd0>
8001b1c: 4b6a ldr r3, [pc, #424] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b1e: 681b ldr r3, [r3, #0]
8001b20: 4a69 ldr r2, [pc, #420] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b22: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001b26: 6013 str r3, [r2, #0]
8001b28: 4b67 ldr r3, [pc, #412] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b2a: 681b ldr r3, [r3, #0]
8001b2c: 4a66 ldr r2, [pc, #408] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b2e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001b32: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001b34: 687b ldr r3, [r7, #4]
8001b36: 685b ldr r3, [r3, #4]
8001b38: 2b00 cmp r3, #0
8001b3a: d013 beq.n 8001b64 <HAL_RCC_OscConfig+0x100>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001b3c: f7ff fcb0 bl 80014a0 <HAL_GetTick>
8001b40: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8001b42: e008 b.n 8001b56 <HAL_RCC_OscConfig+0xf2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001b44: f7ff fcac bl 80014a0 <HAL_GetTick>
8001b48: 4602 mov r2, r0
8001b4a: 693b ldr r3, [r7, #16]
8001b4c: 1ad3 subs r3, r2, r3
8001b4e: 2b64 cmp r3, #100 @ 0x64
8001b50: d901 bls.n 8001b56 <HAL_RCC_OscConfig+0xf2>
{
return HAL_TIMEOUT;
8001b52: 2303 movs r3, #3
8001b54: e2ad b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8001b56: 4b5c ldr r3, [pc, #368] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b58: 681b ldr r3, [r3, #0]
8001b5a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001b5e: 2b00 cmp r3, #0
8001b60: d0f0 beq.n 8001b44 <HAL_RCC_OscConfig+0xe0>
8001b62: e014 b.n 8001b8e <HAL_RCC_OscConfig+0x12a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001b64: f7ff fc9c bl 80014a0 <HAL_GetTick>
8001b68: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8001b6a: e008 b.n 8001b7e <HAL_RCC_OscConfig+0x11a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001b6c: f7ff fc98 bl 80014a0 <HAL_GetTick>
8001b70: 4602 mov r2, r0
8001b72: 693b ldr r3, [r7, #16]
8001b74: 1ad3 subs r3, r2, r3
8001b76: 2b64 cmp r3, #100 @ 0x64
8001b78: d901 bls.n 8001b7e <HAL_RCC_OscConfig+0x11a>
{
return HAL_TIMEOUT;
8001b7a: 2303 movs r3, #3
8001b7c: e299 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8001b7e: 4b52 ldr r3, [pc, #328] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001b80: 681b ldr r3, [r3, #0]
8001b82: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001b86: 2b00 cmp r3, #0
8001b88: d1f0 bne.n 8001b6c <HAL_RCC_OscConfig+0x108>
8001b8a: e000 b.n 8001b8e <HAL_RCC_OscConfig+0x12a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001b8c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 681b ldr r3, [r3, #0]
8001b92: f003 0302 and.w r3, r3, #2
8001b96: 2b00 cmp r3, #0
8001b98: d05a beq.n 8001c50 <HAL_RCC_OscConfig+0x1ec>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
8001b9a: 69bb ldr r3, [r7, #24]
8001b9c: 2b04 cmp r3, #4
8001b9e: d005 beq.n 8001bac <HAL_RCC_OscConfig+0x148>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
8001ba0: 69bb ldr r3, [r7, #24]
8001ba2: 2b0c cmp r3, #12
8001ba4: d119 bne.n 8001bda <HAL_RCC_OscConfig+0x176>
8001ba6: 697b ldr r3, [r7, #20]
8001ba8: 2b00 cmp r3, #0
8001baa: d116 bne.n 8001bda <HAL_RCC_OscConfig+0x176>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001bac: 4b46 ldr r3, [pc, #280] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001bae: 681b ldr r3, [r3, #0]
8001bb0: f003 0302 and.w r3, r3, #2
8001bb4: 2b00 cmp r3, #0
8001bb6: d005 beq.n 8001bc4 <HAL_RCC_OscConfig+0x160>
8001bb8: 687b ldr r3, [r7, #4]
8001bba: 68db ldr r3, [r3, #12]
8001bbc: 2b01 cmp r3, #1
8001bbe: d001 beq.n 8001bc4 <HAL_RCC_OscConfig+0x160>
{
return HAL_ERROR;
8001bc0: 2301 movs r3, #1
8001bc2: e276 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001bc4: 4b40 ldr r3, [pc, #256] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001bc6: 685b ldr r3, [r3, #4]
8001bc8: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8001bcc: 687b ldr r3, [r7, #4]
8001bce: 691b ldr r3, [r3, #16]
8001bd0: 021b lsls r3, r3, #8
8001bd2: 493d ldr r1, [pc, #244] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001bd4: 4313 orrs r3, r2
8001bd6: 604b str r3, [r1, #4]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001bd8: e03a b.n 8001c50 <HAL_RCC_OscConfig+0x1ec>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8001bda: 687b ldr r3, [r7, #4]
8001bdc: 68db ldr r3, [r3, #12]
8001bde: 2b00 cmp r3, #0
8001be0: d020 beq.n 8001c24 <HAL_RCC_OscConfig+0x1c0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001be2: 4b3a ldr r3, [pc, #232] @ (8001ccc <HAL_RCC_OscConfig+0x268>)
8001be4: 2201 movs r2, #1
8001be6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001be8: f7ff fc5a bl 80014a0 <HAL_GetTick>
8001bec: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8001bee: e008 b.n 8001c02 <HAL_RCC_OscConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001bf0: f7ff fc56 bl 80014a0 <HAL_GetTick>
8001bf4: 4602 mov r2, r0
8001bf6: 693b ldr r3, [r7, #16]
8001bf8: 1ad3 subs r3, r2, r3
8001bfa: 2b02 cmp r3, #2
8001bfc: d901 bls.n 8001c02 <HAL_RCC_OscConfig+0x19e>
{
return HAL_TIMEOUT;
8001bfe: 2303 movs r3, #3
8001c00: e257 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8001c02: 4b31 ldr r3, [pc, #196] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001c04: 681b ldr r3, [r3, #0]
8001c06: f003 0302 and.w r3, r3, #2
8001c0a: 2b00 cmp r3, #0
8001c0c: d0f0 beq.n 8001bf0 <HAL_RCC_OscConfig+0x18c>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001c0e: 4b2e ldr r3, [pc, #184] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001c10: 685b ldr r3, [r3, #4]
8001c12: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8001c16: 687b ldr r3, [r7, #4]
8001c18: 691b ldr r3, [r3, #16]
8001c1a: 021b lsls r3, r3, #8
8001c1c: 492a ldr r1, [pc, #168] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001c1e: 4313 orrs r3, r2
8001c20: 604b str r3, [r1, #4]
8001c22: e015 b.n 8001c50 <HAL_RCC_OscConfig+0x1ec>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001c24: 4b29 ldr r3, [pc, #164] @ (8001ccc <HAL_RCC_OscConfig+0x268>)
8001c26: 2200 movs r2, #0
8001c28: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001c2a: f7ff fc39 bl 80014a0 <HAL_GetTick>
8001c2e: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001c30: e008 b.n 8001c44 <HAL_RCC_OscConfig+0x1e0>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001c32: f7ff fc35 bl 80014a0 <HAL_GetTick>
8001c36: 4602 mov r2, r0
8001c38: 693b ldr r3, [r7, #16]
8001c3a: 1ad3 subs r3, r2, r3
8001c3c: 2b02 cmp r3, #2
8001c3e: d901 bls.n 8001c44 <HAL_RCC_OscConfig+0x1e0>
{
return HAL_TIMEOUT;
8001c40: 2303 movs r3, #3
8001c42: e236 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001c44: 4b20 ldr r3, [pc, #128] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001c46: 681b ldr r3, [r3, #0]
8001c48: f003 0302 and.w r3, r3, #2
8001c4c: 2b00 cmp r3, #0
8001c4e: d1f0 bne.n 8001c32 <HAL_RCC_OscConfig+0x1ce>
}
}
}
}
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8001c50: 687b ldr r3, [r7, #4]
8001c52: 681b ldr r3, [r3, #0]
8001c54: f003 0310 and.w r3, r3, #16
8001c58: 2b00 cmp r3, #0
8001c5a: f000 80b8 beq.w 8001dce <HAL_RCC_OscConfig+0x36a>
{
/* When the MSI is used as system clock it will not be disabled */
if(sysclk_source == RCC_CFGR_SWS_MSI)
8001c5e: 69bb ldr r3, [r7, #24]
8001c60: 2b00 cmp r3, #0
8001c62: d170 bne.n 8001d46 <HAL_RCC_OscConfig+0x2e2>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001c64: 4b18 ldr r3, [pc, #96] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001c66: 681b ldr r3, [r3, #0]
8001c68: f403 7300 and.w r3, r3, #512 @ 0x200
8001c6c: 2b00 cmp r3, #0
8001c6e: d005 beq.n 8001c7c <HAL_RCC_OscConfig+0x218>
8001c70: 687b ldr r3, [r7, #4]
8001c72: 699b ldr r3, [r3, #24]
8001c74: 2b00 cmp r3, #0
8001c76: d101 bne.n 8001c7c <HAL_RCC_OscConfig+0x218>
{
return HAL_ERROR;
8001c78: 2301 movs r3, #1
8001c7a: e21a b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8001c7c: 687b ldr r3, [r7, #4]
8001c7e: 6a1a ldr r2, [r3, #32]
8001c80: 4b11 ldr r3, [pc, #68] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001c82: 685b ldr r3, [r3, #4]
8001c84: f403 4360 and.w r3, r3, #57344 @ 0xe000
8001c88: 429a cmp r2, r3
8001c8a: d921 bls.n 8001cd0 <HAL_RCC_OscConfig+0x26c>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8001c8c: 687b ldr r3, [r7, #4]
8001c8e: 6a1b ldr r3, [r3, #32]
8001c90: 4618 mov r0, r3
8001c92: f000 fc09 bl 80024a8 <RCC_SetFlashLatencyFromMSIRange>
8001c96: 4603 mov r3, r0
8001c98: 2b00 cmp r3, #0
8001c9a: d001 beq.n 8001ca0 <HAL_RCC_OscConfig+0x23c>
{
return HAL_ERROR;
8001c9c: 2301 movs r3, #1
8001c9e: e208 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001ca0: 4b09 ldr r3, [pc, #36] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001ca2: 685b ldr r3, [r3, #4]
8001ca4: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8001ca8: 687b ldr r3, [r7, #4]
8001caa: 6a1b ldr r3, [r3, #32]
8001cac: 4906 ldr r1, [pc, #24] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001cae: 4313 orrs r3, r2
8001cb0: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001cb2: 4b05 ldr r3, [pc, #20] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001cb4: 685b ldr r3, [r3, #4]
8001cb6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
8001cba: 687b ldr r3, [r7, #4]
8001cbc: 69db ldr r3, [r3, #28]
8001cbe: 061b lsls r3, r3, #24
8001cc0: 4901 ldr r1, [pc, #4] @ (8001cc8 <HAL_RCC_OscConfig+0x264>)
8001cc2: 4313 orrs r3, r2
8001cc4: 604b str r3, [r1, #4]
8001cc6: e020 b.n 8001d0a <HAL_RCC_OscConfig+0x2a6>
8001cc8: 40023800 .word 0x40023800
8001ccc: 42470000 .word 0x42470000
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001cd0: 4b99 ldr r3, [pc, #612] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001cd2: 685b ldr r3, [r3, #4]
8001cd4: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8001cd8: 687b ldr r3, [r7, #4]
8001cda: 6a1b ldr r3, [r3, #32]
8001cdc: 4996 ldr r1, [pc, #600] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001cde: 4313 orrs r3, r2
8001ce0: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001ce2: 4b95 ldr r3, [pc, #596] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ce4: 685b ldr r3, [r3, #4]
8001ce6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
8001cea: 687b ldr r3, [r7, #4]
8001cec: 69db ldr r3, [r3, #28]
8001cee: 061b lsls r3, r3, #24
8001cf0: 4991 ldr r1, [pc, #580] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001cf2: 4313 orrs r3, r2
8001cf4: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8001cf6: 687b ldr r3, [r7, #4]
8001cf8: 6a1b ldr r3, [r3, #32]
8001cfa: 4618 mov r0, r3
8001cfc: f000 fbd4 bl 80024a8 <RCC_SetFlashLatencyFromMSIRange>
8001d00: 4603 mov r3, r0
8001d02: 2b00 cmp r3, #0
8001d04: d001 beq.n 8001d0a <HAL_RCC_OscConfig+0x2a6>
{
return HAL_ERROR;
8001d06: 2301 movs r3, #1
8001d08: e1d3 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
8001d0a: 687b ldr r3, [r7, #4]
8001d0c: 6a1b ldr r3, [r3, #32]
8001d0e: 0b5b lsrs r3, r3, #13
8001d10: 3301 adds r3, #1
8001d12: f44f 4200 mov.w r2, #32768 @ 0x8000
8001d16: fa02 f303 lsl.w r3, r2, r3
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
8001d1a: 4a87 ldr r2, [pc, #540] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001d1c: 6892 ldr r2, [r2, #8]
8001d1e: 0912 lsrs r2, r2, #4
8001d20: f002 020f and.w r2, r2, #15
8001d24: 4985 ldr r1, [pc, #532] @ (8001f3c <HAL_RCC_OscConfig+0x4d8>)
8001d26: 5c8a ldrb r2, [r1, r2]
8001d28: 40d3 lsrs r3, r2
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
8001d2a: 4a85 ldr r2, [pc, #532] @ (8001f40 <HAL_RCC_OscConfig+0x4dc>)
8001d2c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8001d2e: 4b85 ldr r3, [pc, #532] @ (8001f44 <HAL_RCC_OscConfig+0x4e0>)
8001d30: 681b ldr r3, [r3, #0]
8001d32: 4618 mov r0, r3
8001d34: f7ff fb68 bl 8001408 <HAL_InitTick>
8001d38: 4603 mov r3, r0
8001d3a: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
8001d3c: 7bfb ldrb r3, [r7, #15]
8001d3e: 2b00 cmp r3, #0
8001d40: d045 beq.n 8001dce <HAL_RCC_OscConfig+0x36a>
{
return status;
8001d42: 7bfb ldrb r3, [r7, #15]
8001d44: e1b5 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
{
/* Check MSI State */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8001d46: 687b ldr r3, [r7, #4]
8001d48: 699b ldr r3, [r3, #24]
8001d4a: 2b00 cmp r3, #0
8001d4c: d029 beq.n 8001da2 <HAL_RCC_OscConfig+0x33e>
{
/* Enable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
8001d4e: 4b7e ldr r3, [pc, #504] @ (8001f48 <HAL_RCC_OscConfig+0x4e4>)
8001d50: 2201 movs r2, #1
8001d52: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001d54: f7ff fba4 bl 80014a0 <HAL_GetTick>
8001d58: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
8001d5a: e008 b.n 8001d6e <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8001d5c: f7ff fba0 bl 80014a0 <HAL_GetTick>
8001d60: 4602 mov r2, r0
8001d62: 693b ldr r3, [r7, #16]
8001d64: 1ad3 subs r3, r2, r3
8001d66: 2b02 cmp r3, #2
8001d68: d901 bls.n 8001d6e <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
8001d6a: 2303 movs r3, #3
8001d6c: e1a1 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
8001d6e: 4b72 ldr r3, [pc, #456] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001d70: 681b ldr r3, [r3, #0]
8001d72: f403 7300 and.w r3, r3, #512 @ 0x200
8001d76: 2b00 cmp r3, #0
8001d78: d0f0 beq.n 8001d5c <HAL_RCC_OscConfig+0x2f8>
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8001d7a: 4b6f ldr r3, [pc, #444] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001d7c: 685b ldr r3, [r3, #4]
8001d7e: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8001d82: 687b ldr r3, [r7, #4]
8001d84: 6a1b ldr r3, [r3, #32]
8001d86: 496c ldr r1, [pc, #432] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001d88: 4313 orrs r3, r2
8001d8a: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001d8c: 4b6a ldr r3, [pc, #424] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001d8e: 685b ldr r3, [r3, #4]
8001d90: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
8001d94: 687b ldr r3, [r7, #4]
8001d96: 69db ldr r3, [r3, #28]
8001d98: 061b lsls r3, r3, #24
8001d9a: 4967 ldr r1, [pc, #412] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001d9c: 4313 orrs r3, r2
8001d9e: 604b str r3, [r1, #4]
8001da0: e015 b.n 8001dce <HAL_RCC_OscConfig+0x36a>
}
else
{
/* Disable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
8001da2: 4b69 ldr r3, [pc, #420] @ (8001f48 <HAL_RCC_OscConfig+0x4e4>)
8001da4: 2200 movs r2, #0
8001da6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001da8: f7ff fb7a bl 80014a0 <HAL_GetTick>
8001dac: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
8001dae: e008 b.n 8001dc2 <HAL_RCC_OscConfig+0x35e>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8001db0: f7ff fb76 bl 80014a0 <HAL_GetTick>
8001db4: 4602 mov r2, r0
8001db6: 693b ldr r3, [r7, #16]
8001db8: 1ad3 subs r3, r2, r3
8001dba: 2b02 cmp r3, #2
8001dbc: d901 bls.n 8001dc2 <HAL_RCC_OscConfig+0x35e>
{
return HAL_TIMEOUT;
8001dbe: 2303 movs r3, #3
8001dc0: e177 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
8001dc2: 4b5d ldr r3, [pc, #372] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001dc4: 681b ldr r3, [r3, #0]
8001dc6: f403 7300 and.w r3, r3, #512 @ 0x200
8001dca: 2b00 cmp r3, #0
8001dcc: d1f0 bne.n 8001db0 <HAL_RCC_OscConfig+0x34c>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001dce: 687b ldr r3, [r7, #4]
8001dd0: 681b ldr r3, [r3, #0]
8001dd2: f003 0308 and.w r3, r3, #8
8001dd6: 2b00 cmp r3, #0
8001dd8: d030 beq.n 8001e3c <HAL_RCC_OscConfig+0x3d8>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8001dda: 687b ldr r3, [r7, #4]
8001ddc: 695b ldr r3, [r3, #20]
8001dde: 2b00 cmp r3, #0
8001de0: d016 beq.n 8001e10 <HAL_RCC_OscConfig+0x3ac>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001de2: 4b5a ldr r3, [pc, #360] @ (8001f4c <HAL_RCC_OscConfig+0x4e8>)
8001de4: 2201 movs r2, #1
8001de6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001de8: f7ff fb5a bl 80014a0 <HAL_GetTick>
8001dec: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
8001dee: e008 b.n 8001e02 <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001df0: f7ff fb56 bl 80014a0 <HAL_GetTick>
8001df4: 4602 mov r2, r0
8001df6: 693b ldr r3, [r7, #16]
8001df8: 1ad3 subs r3, r2, r3
8001dfa: 2b02 cmp r3, #2
8001dfc: d901 bls.n 8001e02 <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
8001dfe: 2303 movs r3, #3
8001e00: e157 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
8001e02: 4b4d ldr r3, [pc, #308] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001e04: 6b5b ldr r3, [r3, #52] @ 0x34
8001e06: f003 0302 and.w r3, r3, #2
8001e0a: 2b00 cmp r3, #0
8001e0c: d0f0 beq.n 8001df0 <HAL_RCC_OscConfig+0x38c>
8001e0e: e015 b.n 8001e3c <HAL_RCC_OscConfig+0x3d8>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001e10: 4b4e ldr r3, [pc, #312] @ (8001f4c <HAL_RCC_OscConfig+0x4e8>)
8001e12: 2200 movs r2, #0
8001e14: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001e16: f7ff fb43 bl 80014a0 <HAL_GetTick>
8001e1a: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8001e1c: e008 b.n 8001e30 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001e1e: f7ff fb3f bl 80014a0 <HAL_GetTick>
8001e22: 4602 mov r2, r0
8001e24: 693b ldr r3, [r7, #16]
8001e26: 1ad3 subs r3, r2, r3
8001e28: 2b02 cmp r3, #2
8001e2a: d901 bls.n 8001e30 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
8001e2c: 2303 movs r3, #3
8001e2e: e140 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8001e30: 4b41 ldr r3, [pc, #260] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001e32: 6b5b ldr r3, [r3, #52] @ 0x34
8001e34: f003 0302 and.w r3, r3, #2
8001e38: 2b00 cmp r3, #0
8001e3a: d1f0 bne.n 8001e1e <HAL_RCC_OscConfig+0x3ba>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001e3c: 687b ldr r3, [r7, #4]
8001e3e: 681b ldr r3, [r3, #0]
8001e40: f003 0304 and.w r3, r3, #4
8001e44: 2b00 cmp r3, #0
8001e46: f000 80b5 beq.w 8001fb4 <HAL_RCC_OscConfig+0x550>
{
FlagStatus pwrclkchanged = RESET;
8001e4a: 2300 movs r3, #0
8001e4c: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001e4e: 4b3a ldr r3, [pc, #232] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001e50: 6a5b ldr r3, [r3, #36] @ 0x24
8001e52: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001e56: 2b00 cmp r3, #0
8001e58: d10d bne.n 8001e76 <HAL_RCC_OscConfig+0x412>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001e5a: 4b37 ldr r3, [pc, #220] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001e5c: 6a5b ldr r3, [r3, #36] @ 0x24
8001e5e: 4a36 ldr r2, [pc, #216] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001e60: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001e64: 6253 str r3, [r2, #36] @ 0x24
8001e66: 4b34 ldr r3, [pc, #208] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001e68: 6a5b ldr r3, [r3, #36] @ 0x24
8001e6a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001e6e: 60bb str r3, [r7, #8]
8001e70: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001e72: 2301 movs r3, #1
8001e74: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001e76: 4b36 ldr r3, [pc, #216] @ (8001f50 <HAL_RCC_OscConfig+0x4ec>)
8001e78: 681b ldr r3, [r3, #0]
8001e7a: f403 7380 and.w r3, r3, #256 @ 0x100
8001e7e: 2b00 cmp r3, #0
8001e80: d118 bne.n 8001eb4 <HAL_RCC_OscConfig+0x450>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001e82: 4b33 ldr r3, [pc, #204] @ (8001f50 <HAL_RCC_OscConfig+0x4ec>)
8001e84: 681b ldr r3, [r3, #0]
8001e86: 4a32 ldr r2, [pc, #200] @ (8001f50 <HAL_RCC_OscConfig+0x4ec>)
8001e88: f443 7380 orr.w r3, r3, #256 @ 0x100
8001e8c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001e8e: f7ff fb07 bl 80014a0 <HAL_GetTick>
8001e92: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001e94: e008 b.n 8001ea8 <HAL_RCC_OscConfig+0x444>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001e96: f7ff fb03 bl 80014a0 <HAL_GetTick>
8001e9a: 4602 mov r2, r0
8001e9c: 693b ldr r3, [r7, #16]
8001e9e: 1ad3 subs r3, r2, r3
8001ea0: 2b64 cmp r3, #100 @ 0x64
8001ea2: d901 bls.n 8001ea8 <HAL_RCC_OscConfig+0x444>
{
return HAL_TIMEOUT;
8001ea4: 2303 movs r3, #3
8001ea6: e104 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001ea8: 4b29 ldr r3, [pc, #164] @ (8001f50 <HAL_RCC_OscConfig+0x4ec>)
8001eaa: 681b ldr r3, [r3, #0]
8001eac: f403 7380 and.w r3, r3, #256 @ 0x100
8001eb0: 2b00 cmp r3, #0
8001eb2: d0f0 beq.n 8001e96 <HAL_RCC_OscConfig+0x432>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 689b ldr r3, [r3, #8]
8001eb8: 2b01 cmp r3, #1
8001eba: d106 bne.n 8001eca <HAL_RCC_OscConfig+0x466>
8001ebc: 4b1e ldr r3, [pc, #120] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ebe: 6b5b ldr r3, [r3, #52] @ 0x34
8001ec0: 4a1d ldr r2, [pc, #116] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ec2: f443 7380 orr.w r3, r3, #256 @ 0x100
8001ec6: 6353 str r3, [r2, #52] @ 0x34
8001ec8: e02d b.n 8001f26 <HAL_RCC_OscConfig+0x4c2>
8001eca: 687b ldr r3, [r7, #4]
8001ecc: 689b ldr r3, [r3, #8]
8001ece: 2b00 cmp r3, #0
8001ed0: d10c bne.n 8001eec <HAL_RCC_OscConfig+0x488>
8001ed2: 4b19 ldr r3, [pc, #100] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ed4: 6b5b ldr r3, [r3, #52] @ 0x34
8001ed6: 4a18 ldr r2, [pc, #96] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ed8: f423 7380 bic.w r3, r3, #256 @ 0x100
8001edc: 6353 str r3, [r2, #52] @ 0x34
8001ede: 4b16 ldr r3, [pc, #88] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ee0: 6b5b ldr r3, [r3, #52] @ 0x34
8001ee2: 4a15 ldr r2, [pc, #84] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ee4: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001ee8: 6353 str r3, [r2, #52] @ 0x34
8001eea: e01c b.n 8001f26 <HAL_RCC_OscConfig+0x4c2>
8001eec: 687b ldr r3, [r7, #4]
8001eee: 689b ldr r3, [r3, #8]
8001ef0: 2b05 cmp r3, #5
8001ef2: d10c bne.n 8001f0e <HAL_RCC_OscConfig+0x4aa>
8001ef4: 4b10 ldr r3, [pc, #64] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001ef6: 6b5b ldr r3, [r3, #52] @ 0x34
8001ef8: 4a0f ldr r2, [pc, #60] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001efa: f443 6380 orr.w r3, r3, #1024 @ 0x400
8001efe: 6353 str r3, [r2, #52] @ 0x34
8001f00: 4b0d ldr r3, [pc, #52] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001f02: 6b5b ldr r3, [r3, #52] @ 0x34
8001f04: 4a0c ldr r2, [pc, #48] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001f06: f443 7380 orr.w r3, r3, #256 @ 0x100
8001f0a: 6353 str r3, [r2, #52] @ 0x34
8001f0c: e00b b.n 8001f26 <HAL_RCC_OscConfig+0x4c2>
8001f0e: 4b0a ldr r3, [pc, #40] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001f10: 6b5b ldr r3, [r3, #52] @ 0x34
8001f12: 4a09 ldr r2, [pc, #36] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001f14: f423 7380 bic.w r3, r3, #256 @ 0x100
8001f18: 6353 str r3, [r2, #52] @ 0x34
8001f1a: 4b07 ldr r3, [pc, #28] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001f1c: 6b5b ldr r3, [r3, #52] @ 0x34
8001f1e: 4a06 ldr r2, [pc, #24] @ (8001f38 <HAL_RCC_OscConfig+0x4d4>)
8001f20: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001f24: 6353 str r3, [r2, #52] @ 0x34
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001f26: 687b ldr r3, [r7, #4]
8001f28: 689b ldr r3, [r3, #8]
8001f2a: 2b00 cmp r3, #0
8001f2c: d024 beq.n 8001f78 <HAL_RCC_OscConfig+0x514>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001f2e: f7ff fab7 bl 80014a0 <HAL_GetTick>
8001f32: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8001f34: e019 b.n 8001f6a <HAL_RCC_OscConfig+0x506>
8001f36: bf00 nop
8001f38: 40023800 .word 0x40023800
8001f3c: 08003814 .word 0x08003814
8001f40: 20000004 .word 0x20000004
8001f44: 20000008 .word 0x20000008
8001f48: 42470020 .word 0x42470020
8001f4c: 42470680 .word 0x42470680
8001f50: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001f54: f7ff faa4 bl 80014a0 <HAL_GetTick>
8001f58: 4602 mov r2, r0
8001f5a: 693b ldr r3, [r7, #16]
8001f5c: 1ad3 subs r3, r2, r3
8001f5e: f241 3288 movw r2, #5000 @ 0x1388
8001f62: 4293 cmp r3, r2
8001f64: d901 bls.n 8001f6a <HAL_RCC_OscConfig+0x506>
{
return HAL_TIMEOUT;
8001f66: 2303 movs r3, #3
8001f68: e0a3 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8001f6a: 4b54 ldr r3, [pc, #336] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8001f6c: 6b5b ldr r3, [r3, #52] @ 0x34
8001f6e: f403 7300 and.w r3, r3, #512 @ 0x200
8001f72: 2b00 cmp r3, #0
8001f74: d0ee beq.n 8001f54 <HAL_RCC_OscConfig+0x4f0>
8001f76: e014 b.n 8001fa2 <HAL_RCC_OscConfig+0x53e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001f78: f7ff fa92 bl 80014a0 <HAL_GetTick>
8001f7c: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
8001f7e: e00a b.n 8001f96 <HAL_RCC_OscConfig+0x532>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001f80: f7ff fa8e bl 80014a0 <HAL_GetTick>
8001f84: 4602 mov r2, r0
8001f86: 693b ldr r3, [r7, #16]
8001f88: 1ad3 subs r3, r2, r3
8001f8a: f241 3288 movw r2, #5000 @ 0x1388
8001f8e: 4293 cmp r3, r2
8001f90: d901 bls.n 8001f96 <HAL_RCC_OscConfig+0x532>
{
return HAL_TIMEOUT;
8001f92: 2303 movs r3, #3
8001f94: e08d b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
8001f96: 4b49 ldr r3, [pc, #292] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8001f98: 6b5b ldr r3, [r3, #52] @ 0x34
8001f9a: f403 7300 and.w r3, r3, #512 @ 0x200
8001f9e: 2b00 cmp r3, #0
8001fa0: d1ee bne.n 8001f80 <HAL_RCC_OscConfig+0x51c>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8001fa2: 7ffb ldrb r3, [r7, #31]
8001fa4: 2b01 cmp r3, #1
8001fa6: d105 bne.n 8001fb4 <HAL_RCC_OscConfig+0x550>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001fa8: 4b44 ldr r3, [pc, #272] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8001faa: 6a5b ldr r3, [r3, #36] @ 0x24
8001fac: 4a43 ldr r2, [pc, #268] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8001fae: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8001fb2: 6253 str r3, [r2, #36] @ 0x24
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001fb4: 687b ldr r3, [r7, #4]
8001fb6: 6a5b ldr r3, [r3, #36] @ 0x24
8001fb8: 2b00 cmp r3, #0
8001fba: d079 beq.n 80020b0 <HAL_RCC_OscConfig+0x64c>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001fbc: 69bb ldr r3, [r7, #24]
8001fbe: 2b0c cmp r3, #12
8001fc0: d056 beq.n 8002070 <HAL_RCC_OscConfig+0x60c>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001fc2: 687b ldr r3, [r7, #4]
8001fc4: 6a5b ldr r3, [r3, #36] @ 0x24
8001fc6: 2b02 cmp r3, #2
8001fc8: d13b bne.n 8002042 <HAL_RCC_OscConfig+0x5de>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001fca: 4b3d ldr r3, [pc, #244] @ (80020c0 <HAL_RCC_OscConfig+0x65c>)
8001fcc: 2200 movs r2, #0
8001fce: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001fd0: f7ff fa66 bl 80014a0 <HAL_GetTick>
8001fd4: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8001fd6: e008 b.n 8001fea <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001fd8: f7ff fa62 bl 80014a0 <HAL_GetTick>
8001fdc: 4602 mov r2, r0
8001fde: 693b ldr r3, [r7, #16]
8001fe0: 1ad3 subs r3, r2, r3
8001fe2: 2b02 cmp r3, #2
8001fe4: d901 bls.n 8001fea <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8001fe6: 2303 movs r3, #3
8001fe8: e063 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8001fea: 4b34 ldr r3, [pc, #208] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8001fec: 681b ldr r3, [r3, #0]
8001fee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001ff2: 2b00 cmp r3, #0
8001ff4: d1f0 bne.n 8001fd8 <HAL_RCC_OscConfig+0x574>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001ff6: 4b31 ldr r3, [pc, #196] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8001ff8: 689b ldr r3, [r3, #8]
8001ffa: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000
8001ffe: 687b ldr r3, [r7, #4]
8002000: 6a99 ldr r1, [r3, #40] @ 0x28
8002002: 687b ldr r3, [r7, #4]
8002004: 6adb ldr r3, [r3, #44] @ 0x2c
8002006: 4319 orrs r1, r3
8002008: 687b ldr r3, [r7, #4]
800200a: 6b1b ldr r3, [r3, #48] @ 0x30
800200c: 430b orrs r3, r1
800200e: 492b ldr r1, [pc, #172] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8002010: 4313 orrs r3, r2
8002012: 608b str r3, [r1, #8]
RCC_OscInitStruct->PLL.PLLMUL,
RCC_OscInitStruct->PLL.PLLDIV);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002014: 4b2a ldr r3, [pc, #168] @ (80020c0 <HAL_RCC_OscConfig+0x65c>)
8002016: 2201 movs r2, #1
8002018: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800201a: f7ff fa41 bl 80014a0 <HAL_GetTick>
800201e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8002020: e008 b.n 8002034 <HAL_RCC_OscConfig+0x5d0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002022: f7ff fa3d bl 80014a0 <HAL_GetTick>
8002026: 4602 mov r2, r0
8002028: 693b ldr r3, [r7, #16]
800202a: 1ad3 subs r3, r2, r3
800202c: 2b02 cmp r3, #2
800202e: d901 bls.n 8002034 <HAL_RCC_OscConfig+0x5d0>
{
return HAL_TIMEOUT;
8002030: 2303 movs r3, #3
8002032: e03e b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8002034: 4b21 ldr r3, [pc, #132] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8002036: 681b ldr r3, [r3, #0]
8002038: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800203c: 2b00 cmp r3, #0
800203e: d0f0 beq.n 8002022 <HAL_RCC_OscConfig+0x5be>
8002040: e036 b.n 80020b0 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002042: 4b1f ldr r3, [pc, #124] @ (80020c0 <HAL_RCC_OscConfig+0x65c>)
8002044: 2200 movs r2, #0
8002046: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002048: f7ff fa2a bl 80014a0 <HAL_GetTick>
800204c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
800204e: e008 b.n 8002062 <HAL_RCC_OscConfig+0x5fe>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002050: f7ff fa26 bl 80014a0 <HAL_GetTick>
8002054: 4602 mov r2, r0
8002056: 693b ldr r3, [r7, #16]
8002058: 1ad3 subs r3, r2, r3
800205a: 2b02 cmp r3, #2
800205c: d901 bls.n 8002062 <HAL_RCC_OscConfig+0x5fe>
{
return HAL_TIMEOUT;
800205e: 2303 movs r3, #3
8002060: e027 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8002062: 4b16 ldr r3, [pc, #88] @ (80020bc <HAL_RCC_OscConfig+0x658>)
8002064: 681b ldr r3, [r3, #0]
8002066: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800206a: 2b00 cmp r3, #0
800206c: d1f0 bne.n 8002050 <HAL_RCC_OscConfig+0x5ec>
800206e: e01f b.n 80020b0 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002070: 687b ldr r3, [r7, #4]
8002072: 6a5b ldr r3, [r3, #36] @ 0x24
8002074: 2b01 cmp r3, #1
8002076: d101 bne.n 800207c <HAL_RCC_OscConfig+0x618>
{
return HAL_ERROR;
8002078: 2301 movs r3, #1
800207a: e01a b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800207c: 4b0f ldr r3, [pc, #60] @ (80020bc <HAL_RCC_OscConfig+0x658>)
800207e: 689b ldr r3, [r3, #8]
8002080: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002082: 697b ldr r3, [r7, #20]
8002084: f403 3280 and.w r2, r3, #65536 @ 0x10000
8002088: 687b ldr r3, [r7, #4]
800208a: 6a9b ldr r3, [r3, #40] @ 0x28
800208c: 429a cmp r2, r3
800208e: d10d bne.n 80020ac <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
8002090: 697b ldr r3, [r7, #20]
8002092: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8002096: 687b ldr r3, [r7, #4]
8002098: 6adb ldr r3, [r3, #44] @ 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800209a: 429a cmp r2, r3
800209c: d106 bne.n 80020ac <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
800209e: 697b ldr r3, [r7, #20]
80020a0: f403 0240 and.w r2, r3, #12582912 @ 0xc00000
80020a4: 687b ldr r3, [r7, #4]
80020a6: 6b1b ldr r3, [r3, #48] @ 0x30
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
80020a8: 429a cmp r2, r3
80020aa: d001 beq.n 80020b0 <HAL_RCC_OscConfig+0x64c>
{
return HAL_ERROR;
80020ac: 2301 movs r3, #1
80020ae: e000 b.n 80020b2 <HAL_RCC_OscConfig+0x64e>
}
}
}
}
return HAL_OK;
80020b0: 2300 movs r3, #0
}
80020b2: 4618 mov r0, r3
80020b4: 3720 adds r7, #32
80020b6: 46bd mov sp, r7
80020b8: bd80 pop {r7, pc}
80020ba: bf00 nop
80020bc: 40023800 .word 0x40023800
80020c0: 42470060 .word 0x42470060
080020c4 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80020c4: b580 push {r7, lr}
80020c6: b084 sub sp, #16
80020c8: af00 add r7, sp, #0
80020ca: 6078 str r0, [r7, #4]
80020cc: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status;
/* Check the parameters */
if(RCC_ClkInitStruct == NULL)
80020ce: 687b ldr r3, [r7, #4]
80020d0: 2b00 cmp r3, #0
80020d2: d101 bne.n 80020d8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80020d4: 2301 movs r3, #1
80020d6: e11a b.n 800230e <HAL_RCC_ClockConfig+0x24a>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80020d8: 4b8f ldr r3, [pc, #572] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
80020da: 681b ldr r3, [r3, #0]
80020dc: f003 0301 and.w r3, r3, #1
80020e0: 683a ldr r2, [r7, #0]
80020e2: 429a cmp r2, r3
80020e4: d919 bls.n 800211a <HAL_RCC_ClockConfig+0x56>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80020e6: 683b ldr r3, [r7, #0]
80020e8: 2b01 cmp r3, #1
80020ea: d105 bne.n 80020f8 <HAL_RCC_ClockConfig+0x34>
80020ec: 4b8a ldr r3, [pc, #552] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
80020ee: 681b ldr r3, [r3, #0]
80020f0: 4a89 ldr r2, [pc, #548] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
80020f2: f043 0304 orr.w r3, r3, #4
80020f6: 6013 str r3, [r2, #0]
80020f8: 4b87 ldr r3, [pc, #540] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
80020fa: 681b ldr r3, [r3, #0]
80020fc: f023 0201 bic.w r2, r3, #1
8002100: 4985 ldr r1, [pc, #532] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
8002102: 683b ldr r3, [r7, #0]
8002104: 4313 orrs r3, r2
8002106: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002108: 4b83 ldr r3, [pc, #524] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
800210a: 681b ldr r3, [r3, #0]
800210c: f003 0301 and.w r3, r3, #1
8002110: 683a ldr r2, [r7, #0]
8002112: 429a cmp r2, r3
8002114: d001 beq.n 800211a <HAL_RCC_ClockConfig+0x56>
{
return HAL_ERROR;
8002116: 2301 movs r3, #1
8002118: e0f9 b.n 800230e <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800211a: 687b ldr r3, [r7, #4]
800211c: 681b ldr r3, [r3, #0]
800211e: f003 0302 and.w r3, r3, #2
8002122: 2b00 cmp r3, #0
8002124: d008 beq.n 8002138 <HAL_RCC_ClockConfig+0x74>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002126: 4b7d ldr r3, [pc, #500] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002128: 689b ldr r3, [r3, #8]
800212a: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800212e: 687b ldr r3, [r7, #4]
8002130: 689b ldr r3, [r3, #8]
8002132: 497a ldr r1, [pc, #488] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002134: 4313 orrs r3, r2
8002136: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002138: 687b ldr r3, [r7, #4]
800213a: 681b ldr r3, [r3, #0]
800213c: f003 0301 and.w r3, r3, #1
8002140: 2b00 cmp r3, #0
8002142: f000 808e beq.w 8002262 <HAL_RCC_ClockConfig+0x19e>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002146: 687b ldr r3, [r7, #4]
8002148: 685b ldr r3, [r3, #4]
800214a: 2b02 cmp r3, #2
800214c: d107 bne.n 800215e <HAL_RCC_ClockConfig+0x9a>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
800214e: 4b73 ldr r3, [pc, #460] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002150: 681b ldr r3, [r3, #0]
8002152: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002156: 2b00 cmp r3, #0
8002158: d121 bne.n 800219e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800215a: 2301 movs r3, #1
800215c: e0d7 b.n 800230e <HAL_RCC_ClockConfig+0x24a>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800215e: 687b ldr r3, [r7, #4]
8002160: 685b ldr r3, [r3, #4]
8002162: 2b03 cmp r3, #3
8002164: d107 bne.n 8002176 <HAL_RCC_ClockConfig+0xb2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8002166: 4b6d ldr r3, [pc, #436] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002168: 681b ldr r3, [r3, #0]
800216a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800216e: 2b00 cmp r3, #0
8002170: d115 bne.n 800219e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8002172: 2301 movs r3, #1
8002174: e0cb b.n 800230e <HAL_RCC_ClockConfig+0x24a>
}
}
/* HSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8002176: 687b ldr r3, [r7, #4]
8002178: 685b ldr r3, [r3, #4]
800217a: 2b01 cmp r3, #1
800217c: d107 bne.n 800218e <HAL_RCC_ClockConfig+0xca>
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
800217e: 4b67 ldr r3, [pc, #412] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002180: 681b ldr r3, [r3, #0]
8002182: f003 0302 and.w r3, r3, #2
8002186: 2b00 cmp r3, #0
8002188: d109 bne.n 800219e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800218a: 2301 movs r3, #1
800218c: e0bf b.n 800230e <HAL_RCC_ClockConfig+0x24a>
}
/* MSI is selected as System Clock Source */
else
{
/* Check the MSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800218e: 4b63 ldr r3, [pc, #396] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002190: 681b ldr r3, [r3, #0]
8002192: f403 7300 and.w r3, r3, #512 @ 0x200
8002196: 2b00 cmp r3, #0
8002198: d101 bne.n 800219e <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800219a: 2301 movs r3, #1
800219c: e0b7 b.n 800230e <HAL_RCC_ClockConfig+0x24a>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800219e: 4b5f ldr r3, [pc, #380] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80021a0: 689b ldr r3, [r3, #8]
80021a2: f023 0203 bic.w r2, r3, #3
80021a6: 687b ldr r3, [r7, #4]
80021a8: 685b ldr r3, [r3, #4]
80021aa: 495c ldr r1, [pc, #368] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80021ac: 4313 orrs r3, r2
80021ae: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
80021b0: f7ff f976 bl 80014a0 <HAL_GetTick>
80021b4: 60f8 str r0, [r7, #12]
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80021b6: 687b ldr r3, [r7, #4]
80021b8: 685b ldr r3, [r3, #4]
80021ba: 2b02 cmp r3, #2
80021bc: d112 bne.n 80021e4 <HAL_RCC_ClockConfig+0x120>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
80021be: e00a b.n 80021d6 <HAL_RCC_ClockConfig+0x112>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80021c0: f7ff f96e bl 80014a0 <HAL_GetTick>
80021c4: 4602 mov r2, r0
80021c6: 68fb ldr r3, [r7, #12]
80021c8: 1ad3 subs r3, r2, r3
80021ca: f241 3288 movw r2, #5000 @ 0x1388
80021ce: 4293 cmp r3, r2
80021d0: d901 bls.n 80021d6 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
80021d2: 2303 movs r3, #3
80021d4: e09b b.n 800230e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
80021d6: 4b51 ldr r3, [pc, #324] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80021d8: 689b ldr r3, [r3, #8]
80021da: f003 030c and.w r3, r3, #12
80021de: 2b08 cmp r3, #8
80021e0: d1ee bne.n 80021c0 <HAL_RCC_ClockConfig+0xfc>
80021e2: e03e b.n 8002262 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80021e4: 687b ldr r3, [r7, #4]
80021e6: 685b ldr r3, [r3, #4]
80021e8: 2b03 cmp r3, #3
80021ea: d112 bne.n 8002212 <HAL_RCC_ClockConfig+0x14e>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80021ec: e00a b.n 8002204 <HAL_RCC_ClockConfig+0x140>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80021ee: f7ff f957 bl 80014a0 <HAL_GetTick>
80021f2: 4602 mov r2, r0
80021f4: 68fb ldr r3, [r7, #12]
80021f6: 1ad3 subs r3, r2, r3
80021f8: f241 3288 movw r2, #5000 @ 0x1388
80021fc: 4293 cmp r3, r2
80021fe: d901 bls.n 8002204 <HAL_RCC_ClockConfig+0x140>
{
return HAL_TIMEOUT;
8002200: 2303 movs r3, #3
8002202: e084 b.n 800230e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8002204: 4b45 ldr r3, [pc, #276] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002206: 689b ldr r3, [r3, #8]
8002208: f003 030c and.w r3, r3, #12
800220c: 2b0c cmp r3, #12
800220e: d1ee bne.n 80021ee <HAL_RCC_ClockConfig+0x12a>
8002210: e027 b.n 8002262 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8002212: 687b ldr r3, [r7, #4]
8002214: 685b ldr r3, [r3, #4]
8002216: 2b01 cmp r3, #1
8002218: d11d bne.n 8002256 <HAL_RCC_ClockConfig+0x192>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
800221a: e00a b.n 8002232 <HAL_RCC_ClockConfig+0x16e>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
800221c: f7ff f940 bl 80014a0 <HAL_GetTick>
8002220: 4602 mov r2, r0
8002222: 68fb ldr r3, [r7, #12]
8002224: 1ad3 subs r3, r2, r3
8002226: f241 3288 movw r2, #5000 @ 0x1388
800222a: 4293 cmp r3, r2
800222c: d901 bls.n 8002232 <HAL_RCC_ClockConfig+0x16e>
{
return HAL_TIMEOUT;
800222e: 2303 movs r3, #3
8002230: e06d b.n 800230e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
8002232: 4b3a ldr r3, [pc, #232] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002234: 689b ldr r3, [r3, #8]
8002236: f003 030c and.w r3, r3, #12
800223a: 2b04 cmp r3, #4
800223c: d1ee bne.n 800221c <HAL_RCC_ClockConfig+0x158>
800223e: e010 b.n 8002262 <HAL_RCC_ClockConfig+0x19e>
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8002240: f7ff f92e bl 80014a0 <HAL_GetTick>
8002244: 4602 mov r2, r0
8002246: 68fb ldr r3, [r7, #12]
8002248: 1ad3 subs r3, r2, r3
800224a: f241 3288 movw r2, #5000 @ 0x1388
800224e: 4293 cmp r3, r2
8002250: d901 bls.n 8002256 <HAL_RCC_ClockConfig+0x192>
{
return HAL_TIMEOUT;
8002252: 2303 movs r3, #3
8002254: e05b b.n 800230e <HAL_RCC_ClockConfig+0x24a>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
8002256: 4b31 ldr r3, [pc, #196] @ (800231c <HAL_RCC_ClockConfig+0x258>)
8002258: 689b ldr r3, [r3, #8]
800225a: f003 030c and.w r3, r3, #12
800225e: 2b00 cmp r3, #0
8002260: d1ee bne.n 8002240 <HAL_RCC_ClockConfig+0x17c>
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8002262: 4b2d ldr r3, [pc, #180] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
8002264: 681b ldr r3, [r3, #0]
8002266: f003 0301 and.w r3, r3, #1
800226a: 683a ldr r2, [r7, #0]
800226c: 429a cmp r2, r3
800226e: d219 bcs.n 80022a4 <HAL_RCC_ClockConfig+0x1e0>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002270: 683b ldr r3, [r7, #0]
8002272: 2b01 cmp r3, #1
8002274: d105 bne.n 8002282 <HAL_RCC_ClockConfig+0x1be>
8002276: 4b28 ldr r3, [pc, #160] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
8002278: 681b ldr r3, [r3, #0]
800227a: 4a27 ldr r2, [pc, #156] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
800227c: f043 0304 orr.w r3, r3, #4
8002280: 6013 str r3, [r2, #0]
8002282: 4b25 ldr r3, [pc, #148] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
8002284: 681b ldr r3, [r3, #0]
8002286: f023 0201 bic.w r2, r3, #1
800228a: 4923 ldr r1, [pc, #140] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
800228c: 683b ldr r3, [r7, #0]
800228e: 4313 orrs r3, r2
8002290: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002292: 4b21 ldr r3, [pc, #132] @ (8002318 <HAL_RCC_ClockConfig+0x254>)
8002294: 681b ldr r3, [r3, #0]
8002296: f003 0301 and.w r3, r3, #1
800229a: 683a ldr r2, [r7, #0]
800229c: 429a cmp r2, r3
800229e: d001 beq.n 80022a4 <HAL_RCC_ClockConfig+0x1e0>
{
return HAL_ERROR;
80022a0: 2301 movs r3, #1
80022a2: e034 b.n 800230e <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80022a4: 687b ldr r3, [r7, #4]
80022a6: 681b ldr r3, [r3, #0]
80022a8: f003 0304 and.w r3, r3, #4
80022ac: 2b00 cmp r3, #0
80022ae: d008 beq.n 80022c2 <HAL_RCC_ClockConfig+0x1fe>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80022b0: 4b1a ldr r3, [pc, #104] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80022b2: 689b ldr r3, [r3, #8]
80022b4: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80022b8: 687b ldr r3, [r7, #4]
80022ba: 68db ldr r3, [r3, #12]
80022bc: 4917 ldr r1, [pc, #92] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80022be: 4313 orrs r3, r2
80022c0: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80022c2: 687b ldr r3, [r7, #4]
80022c4: 681b ldr r3, [r3, #0]
80022c6: f003 0308 and.w r3, r3, #8
80022ca: 2b00 cmp r3, #0
80022cc: d009 beq.n 80022e2 <HAL_RCC_ClockConfig+0x21e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80022ce: 4b13 ldr r3, [pc, #76] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80022d0: 689b ldr r3, [r3, #8]
80022d2: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80022d6: 687b ldr r3, [r7, #4]
80022d8: 691b ldr r3, [r3, #16]
80022da: 00db lsls r3, r3, #3
80022dc: 490f ldr r1, [pc, #60] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80022de: 4313 orrs r3, r2
80022e0: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
80022e2: f000 f823 bl 800232c <HAL_RCC_GetSysClockFreq>
80022e6: 4602 mov r2, r0
80022e8: 4b0c ldr r3, [pc, #48] @ (800231c <HAL_RCC_ClockConfig+0x258>)
80022ea: 689b ldr r3, [r3, #8]
80022ec: 091b lsrs r3, r3, #4
80022ee: f003 030f and.w r3, r3, #15
80022f2: 490b ldr r1, [pc, #44] @ (8002320 <HAL_RCC_ClockConfig+0x25c>)
80022f4: 5ccb ldrb r3, [r1, r3]
80022f6: fa22 f303 lsr.w r3, r2, r3
80022fa: 4a0a ldr r2, [pc, #40] @ (8002324 <HAL_RCC_ClockConfig+0x260>)
80022fc: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
80022fe: 4b0a ldr r3, [pc, #40] @ (8002328 <HAL_RCC_ClockConfig+0x264>)
8002300: 681b ldr r3, [r3, #0]
8002302: 4618 mov r0, r3
8002304: f7ff f880 bl 8001408 <HAL_InitTick>
8002308: 4603 mov r3, r0
800230a: 72fb strb r3, [r7, #11]
return status;
800230c: 7afb ldrb r3, [r7, #11]
}
800230e: 4618 mov r0, r3
8002310: 3710 adds r7, #16
8002312: 46bd mov sp, r7
8002314: bd80 pop {r7, pc}
8002316: bf00 nop
8002318: 40023c00 .word 0x40023c00
800231c: 40023800 .word 0x40023800
8002320: 08003814 .word 0x08003814
8002324: 20000004 .word 0x20000004
8002328: 20000008 .word 0x20000008
0800232c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800232c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002330: b08e sub sp, #56 @ 0x38
8002332: af00 add r7, sp, #0
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
tmpreg = RCC->CFGR;
8002334: 4b58 ldr r3, [pc, #352] @ (8002498 <HAL_RCC_GetSysClockFreq+0x16c>)
8002336: 689b ldr r3, [r3, #8]
8002338: 62fb str r3, [r7, #44] @ 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800233a: 6afb ldr r3, [r7, #44] @ 0x2c
800233c: f003 030c and.w r3, r3, #12
8002340: 2b0c cmp r3, #12
8002342: d00d beq.n 8002360 <HAL_RCC_GetSysClockFreq+0x34>
8002344: 2b0c cmp r3, #12
8002346: f200 8092 bhi.w 800246e <HAL_RCC_GetSysClockFreq+0x142>
800234a: 2b04 cmp r3, #4
800234c: d002 beq.n 8002354 <HAL_RCC_GetSysClockFreq+0x28>
800234e: 2b08 cmp r3, #8
8002350: d003 beq.n 800235a <HAL_RCC_GetSysClockFreq+0x2e>
8002352: e08c b.n 800246e <HAL_RCC_GetSysClockFreq+0x142>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8002354: 4b51 ldr r3, [pc, #324] @ (800249c <HAL_RCC_GetSysClockFreq+0x170>)
8002356: 633b str r3, [r7, #48] @ 0x30
break;
8002358: e097 b.n 800248a <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
800235a: 4b51 ldr r3, [pc, #324] @ (80024a0 <HAL_RCC_GetSysClockFreq+0x174>)
800235c: 633b str r3, [r7, #48] @ 0x30
break;
800235e: e094 b.n 800248a <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
8002360: 6afb ldr r3, [r7, #44] @ 0x2c
8002362: 0c9b lsrs r3, r3, #18
8002364: f003 020f and.w r2, r3, #15
8002368: 4b4e ldr r3, [pc, #312] @ (80024a4 <HAL_RCC_GetSysClockFreq+0x178>)
800236a: 5c9b ldrb r3, [r3, r2]
800236c: 62bb str r3, [r7, #40] @ 0x28
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
800236e: 6afb ldr r3, [r7, #44] @ 0x2c
8002370: 0d9b lsrs r3, r3, #22
8002372: f003 0303 and.w r3, r3, #3
8002376: 3301 adds r3, #1
8002378: 627b str r3, [r7, #36] @ 0x24
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
800237a: 4b47 ldr r3, [pc, #284] @ (8002498 <HAL_RCC_GetSysClockFreq+0x16c>)
800237c: 689b ldr r3, [r3, #8]
800237e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002382: 2b00 cmp r3, #0
8002384: d021 beq.n 80023ca <HAL_RCC_GetSysClockFreq+0x9e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
8002386: 6abb ldr r3, [r7, #40] @ 0x28
8002388: 2200 movs r2, #0
800238a: 61bb str r3, [r7, #24]
800238c: 61fa str r2, [r7, #28]
800238e: 4b44 ldr r3, [pc, #272] @ (80024a0 <HAL_RCC_GetSysClockFreq+0x174>)
8002390: e9d7 8906 ldrd r8, r9, [r7, #24]
8002394: 464a mov r2, r9
8002396: fb03 f202 mul.w r2, r3, r2
800239a: 2300 movs r3, #0
800239c: 4644 mov r4, r8
800239e: fb04 f303 mul.w r3, r4, r3
80023a2: 4413 add r3, r2
80023a4: 4a3e ldr r2, [pc, #248] @ (80024a0 <HAL_RCC_GetSysClockFreq+0x174>)
80023a6: 4644 mov r4, r8
80023a8: fba4 0102 umull r0, r1, r4, r2
80023ac: 440b add r3, r1
80023ae: 4619 mov r1, r3
80023b0: 6a7b ldr r3, [r7, #36] @ 0x24
80023b2: 2200 movs r2, #0
80023b4: 613b str r3, [r7, #16]
80023b6: 617a str r2, [r7, #20]
80023b8: e9d7 2304 ldrd r2, r3, [r7, #16]
80023bc: f7fe f9e6 bl 800078c <__aeabi_uldivmod>
80023c0: 4602 mov r2, r0
80023c2: 460b mov r3, r1
80023c4: 4613 mov r3, r2
80023c6: 637b str r3, [r7, #52] @ 0x34
80023c8: e04e b.n 8002468 <HAL_RCC_GetSysClockFreq+0x13c>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
80023ca: 6abb ldr r3, [r7, #40] @ 0x28
80023cc: 2200 movs r2, #0
80023ce: 469a mov sl, r3
80023d0: 4693 mov fp, r2
80023d2: 4652 mov r2, sl
80023d4: 465b mov r3, fp
80023d6: f04f 0000 mov.w r0, #0
80023da: f04f 0100 mov.w r1, #0
80023de: 0159 lsls r1, r3, #5
80023e0: ea41 61d2 orr.w r1, r1, r2, lsr #27
80023e4: 0150 lsls r0, r2, #5
80023e6: 4602 mov r2, r0
80023e8: 460b mov r3, r1
80023ea: ebb2 080a subs.w r8, r2, sl
80023ee: eb63 090b sbc.w r9, r3, fp
80023f2: f04f 0200 mov.w r2, #0
80023f6: f04f 0300 mov.w r3, #0
80023fa: ea4f 1389 mov.w r3, r9, lsl #6
80023fe: ea43 6398 orr.w r3, r3, r8, lsr #26
8002402: ea4f 1288 mov.w r2, r8, lsl #6
8002406: ebb2 0408 subs.w r4, r2, r8
800240a: eb63 0509 sbc.w r5, r3, r9
800240e: f04f 0200 mov.w r2, #0
8002412: f04f 0300 mov.w r3, #0
8002416: 00eb lsls r3, r5, #3
8002418: ea43 7354 orr.w r3, r3, r4, lsr #29
800241c: 00e2 lsls r2, r4, #3
800241e: 4614 mov r4, r2
8002420: 461d mov r5, r3
8002422: eb14 030a adds.w r3, r4, sl
8002426: 603b str r3, [r7, #0]
8002428: eb45 030b adc.w r3, r5, fp
800242c: 607b str r3, [r7, #4]
800242e: f04f 0200 mov.w r2, #0
8002432: f04f 0300 mov.w r3, #0
8002436: e9d7 4500 ldrd r4, r5, [r7]
800243a: 4629 mov r1, r5
800243c: 028b lsls r3, r1, #10
800243e: 4620 mov r0, r4
8002440: 4629 mov r1, r5
8002442: 4604 mov r4, r0
8002444: ea43 5394 orr.w r3, r3, r4, lsr #22
8002448: 4601 mov r1, r0
800244a: 028a lsls r2, r1, #10
800244c: 4610 mov r0, r2
800244e: 4619 mov r1, r3
8002450: 6a7b ldr r3, [r7, #36] @ 0x24
8002452: 2200 movs r2, #0
8002454: 60bb str r3, [r7, #8]
8002456: 60fa str r2, [r7, #12]
8002458: e9d7 2302 ldrd r2, r3, [r7, #8]
800245c: f7fe f996 bl 800078c <__aeabi_uldivmod>
8002460: 4602 mov r2, r0
8002462: 460b mov r3, r1
8002464: 4613 mov r3, r2
8002466: 637b str r3, [r7, #52] @ 0x34
}
sysclockfreq = pllvco;
8002468: 6b7b ldr r3, [r7, #52] @ 0x34
800246a: 633b str r3, [r7, #48] @ 0x30
break;
800246c: e00d b.n 800248a <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
default: /* MSI used as system clock */
{
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
800246e: 4b0a ldr r3, [pc, #40] @ (8002498 <HAL_RCC_GetSysClockFreq+0x16c>)
8002470: 685b ldr r3, [r3, #4]
8002472: 0b5b lsrs r3, r3, #13
8002474: f003 0307 and.w r3, r3, #7
8002478: 623b str r3, [r7, #32]
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
800247a: 6a3b ldr r3, [r7, #32]
800247c: 3301 adds r3, #1
800247e: f44f 4200 mov.w r2, #32768 @ 0x8000
8002482: fa02 f303 lsl.w r3, r2, r3
8002486: 633b str r3, [r7, #48] @ 0x30
break;
8002488: bf00 nop
}
}
return sysclockfreq;
800248a: 6b3b ldr r3, [r7, #48] @ 0x30
}
800248c: 4618 mov r0, r3
800248e: 3738 adds r7, #56 @ 0x38
8002490: 46bd mov sp, r7
8002492: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8002496: bf00 nop
8002498: 40023800 .word 0x40023800
800249c: 00f42400 .word 0x00f42400
80024a0: 016e3600 .word 0x016e3600
80024a4: 08003808 .word 0x08003808
080024a8 <RCC_SetFlashLatencyFromMSIRange>:
voltage range
* @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
80024a8: b480 push {r7}
80024aa: b087 sub sp, #28
80024ac: af00 add r7, sp, #0
80024ae: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
80024b0: 2300 movs r3, #0
80024b2: 613b str r3, [r7, #16]
/* HCLK can reach 4 MHz only if AHB prescaler = 1 */
if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
80024b4: 4b29 ldr r3, [pc, #164] @ (800255c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80024b6: 689b ldr r3, [r3, #8]
80024b8: f003 03f0 and.w r3, r3, #240 @ 0xf0
80024bc: 2b00 cmp r3, #0
80024be: d12c bne.n 800251a <RCC_SetFlashLatencyFromMSIRange+0x72>
{
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
80024c0: 4b26 ldr r3, [pc, #152] @ (800255c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80024c2: 6a5b ldr r3, [r3, #36] @ 0x24
80024c4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80024c8: 2b00 cmp r3, #0
80024ca: d005 beq.n 80024d8 <RCC_SetFlashLatencyFromMSIRange+0x30>
{
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
80024cc: 4b24 ldr r3, [pc, #144] @ (8002560 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80024ce: 681b ldr r3, [r3, #0]
80024d0: f403 53c0 and.w r3, r3, #6144 @ 0x1800
80024d4: 617b str r3, [r7, #20]
80024d6: e016 b.n 8002506 <RCC_SetFlashLatencyFromMSIRange+0x5e>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
80024d8: 4b20 ldr r3, [pc, #128] @ (800255c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80024da: 6a5b ldr r3, [r3, #36] @ 0x24
80024dc: 4a1f ldr r2, [pc, #124] @ (800255c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80024de: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80024e2: 6253 str r3, [r2, #36] @ 0x24
80024e4: 4b1d ldr r3, [pc, #116] @ (800255c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80024e6: 6a5b ldr r3, [r3, #36] @ 0x24
80024e8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80024ec: 60fb str r3, [r7, #12]
80024ee: 68fb ldr r3, [r7, #12]
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
80024f0: 4b1b ldr r3, [pc, #108] @ (8002560 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80024f2: 681b ldr r3, [r3, #0]
80024f4: f403 53c0 and.w r3, r3, #6144 @ 0x1800
80024f8: 617b str r3, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
80024fa: 4b18 ldr r3, [pc, #96] @ (800255c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80024fc: 6a5b ldr r3, [r3, #36] @ 0x24
80024fe: 4a17 ldr r2, [pc, #92] @ (800255c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8002500: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002504: 6253 str r3, [r2, #36] @ 0x24
}
/* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
8002506: 697b ldr r3, [r7, #20]
8002508: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800
800250c: d105 bne.n 800251a <RCC_SetFlashLatencyFromMSIRange+0x72>
800250e: 687b ldr r3, [r7, #4]
8002510: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8002514: d101 bne.n 800251a <RCC_SetFlashLatencyFromMSIRange+0x72>
{
latency = FLASH_LATENCY_1; /* 1WS */
8002516: 2301 movs r3, #1
8002518: 613b str r3, [r7, #16]
}
}
__HAL_FLASH_SET_LATENCY(latency);
800251a: 693b ldr r3, [r7, #16]
800251c: 2b01 cmp r3, #1
800251e: d105 bne.n 800252c <RCC_SetFlashLatencyFromMSIRange+0x84>
8002520: 4b10 ldr r3, [pc, #64] @ (8002564 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002522: 681b ldr r3, [r3, #0]
8002524: 4a0f ldr r2, [pc, #60] @ (8002564 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002526: f043 0304 orr.w r3, r3, #4
800252a: 6013 str r3, [r2, #0]
800252c: 4b0d ldr r3, [pc, #52] @ (8002564 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
800252e: 681b ldr r3, [r3, #0]
8002530: f023 0201 bic.w r2, r3, #1
8002534: 490b ldr r1, [pc, #44] @ (8002564 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8002536: 693b ldr r3, [r7, #16]
8002538: 4313 orrs r3, r2
800253a: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
800253c: 4b09 ldr r3, [pc, #36] @ (8002564 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
800253e: 681b ldr r3, [r3, #0]
8002540: f003 0301 and.w r3, r3, #1
8002544: 693a ldr r2, [r7, #16]
8002546: 429a cmp r2, r3
8002548: d001 beq.n 800254e <RCC_SetFlashLatencyFromMSIRange+0xa6>
{
return HAL_ERROR;
800254a: 2301 movs r3, #1
800254c: e000 b.n 8002550 <RCC_SetFlashLatencyFromMSIRange+0xa8>
}
return HAL_OK;
800254e: 2300 movs r3, #0
}
8002550: 4618 mov r0, r3
8002552: 371c adds r7, #28
8002554: 46bd mov sp, r7
8002556: bc80 pop {r7}
8002558: 4770 bx lr
800255a: bf00 nop
800255c: 40023800 .word 0x40023800
8002560: 40007000 .word 0x40007000
8002564: 40023c00 .word 0x40023c00
08002568 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8002568: b580 push {r7, lr}
800256a: b082 sub sp, #8
800256c: af00 add r7, sp, #0
800256e: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
8002570: 687b ldr r3, [r7, #4]
8002572: 2b00 cmp r3, #0
8002574: d101 bne.n 800257a <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8002576: 2301 movs r3, #1
8002578: e07b b.n 8002672 <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
/* TI mode is not supported on all devices in stm32l1xx series.
TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
800257a: 687b ldr r3, [r7, #4]
800257c: 6a5b ldr r3, [r3, #36] @ 0x24
800257e: 2b00 cmp r3, #0
8002580: d108 bne.n 8002594 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8002582: 687b ldr r3, [r7, #4]
8002584: 685b ldr r3, [r3, #4]
8002586: f5b3 7f82 cmp.w r3, #260 @ 0x104
800258a: d009 beq.n 80025a0 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
800258c: 687b ldr r3, [r7, #4]
800258e: 2200 movs r2, #0
8002590: 61da str r2, [r3, #28]
8002592: e005 b.n 80025a0 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8002594: 687b ldr r3, [r7, #4]
8002596: 2200 movs r2, #0
8002598: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
800259a: 687b ldr r3, [r7, #4]
800259c: 2200 movs r2, #0
800259e: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80025a0: 687b ldr r3, [r7, #4]
80025a2: 2200 movs r2, #0
80025a4: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
80025a6: 687b ldr r3, [r7, #4]
80025a8: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
80025ac: b2db uxtb r3, r3
80025ae: 2b00 cmp r3, #0
80025b0: d106 bne.n 80025c0 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
80025b2: 687b ldr r3, [r7, #4]
80025b4: 2200 movs r2, #0
80025b6: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
80025ba: 6878 ldr r0, [r7, #4]
80025bc: f7fe fd28 bl 8001010 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
80025c0: 687b ldr r3, [r7, #4]
80025c2: 2202 movs r2, #2
80025c4: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80025c8: 687b ldr r3, [r7, #4]
80025ca: 681b ldr r3, [r3, #0]
80025cc: 681a ldr r2, [r3, #0]
80025ce: 687b ldr r3, [r7, #4]
80025d0: 681b ldr r3, [r3, #0]
80025d2: f022 0240 bic.w r2, r2, #64 @ 0x40
80025d6: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
80025d8: 687b ldr r3, [r7, #4]
80025da: 685b ldr r3, [r3, #4]
80025dc: f403 7282 and.w r2, r3, #260 @ 0x104
80025e0: 687b ldr r3, [r7, #4]
80025e2: 689b ldr r3, [r3, #8]
80025e4: f403 4304 and.w r3, r3, #33792 @ 0x8400
80025e8: 431a orrs r2, r3
80025ea: 687b ldr r3, [r7, #4]
80025ec: 68db ldr r3, [r3, #12]
80025ee: f403 6300 and.w r3, r3, #2048 @ 0x800
80025f2: 431a orrs r2, r3
80025f4: 687b ldr r3, [r7, #4]
80025f6: 691b ldr r3, [r3, #16]
80025f8: f003 0302 and.w r3, r3, #2
80025fc: 431a orrs r2, r3
80025fe: 687b ldr r3, [r7, #4]
8002600: 695b ldr r3, [r3, #20]
8002602: f003 0301 and.w r3, r3, #1
8002606: 431a orrs r2, r3
8002608: 687b ldr r3, [r7, #4]
800260a: 699b ldr r3, [r3, #24]
800260c: f403 7300 and.w r3, r3, #512 @ 0x200
8002610: 431a orrs r2, r3
8002612: 687b ldr r3, [r7, #4]
8002614: 69db ldr r3, [r3, #28]
8002616: f003 0338 and.w r3, r3, #56 @ 0x38
800261a: 431a orrs r2, r3
800261c: 687b ldr r3, [r7, #4]
800261e: 6a1b ldr r3, [r3, #32]
8002620: f003 0380 and.w r3, r3, #128 @ 0x80
8002624: ea42 0103 orr.w r1, r2, r3
8002628: 687b ldr r3, [r7, #4]
800262a: 6a9b ldr r3, [r3, #40] @ 0x28
800262c: f403 5200 and.w r2, r3, #8192 @ 0x2000
8002630: 687b ldr r3, [r7, #4]
8002632: 681b ldr r3, [r3, #0]
8002634: 430a orrs r2, r1
8002636: 601a str r2, [r3, #0]
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
#if defined(SPI_CR2_FRF)
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
8002638: 687b ldr r3, [r7, #4]
800263a: 699b ldr r3, [r3, #24]
800263c: 0c1b lsrs r3, r3, #16
800263e: f003 0104 and.w r1, r3, #4
8002642: 687b ldr r3, [r7, #4]
8002644: 6a5b ldr r3, [r3, #36] @ 0x24
8002646: f003 0210 and.w r2, r3, #16
800264a: 687b ldr r3, [r7, #4]
800264c: 681b ldr r3, [r3, #0]
800264e: 430a orrs r2, r1
8002650: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8002652: 687b ldr r3, [r7, #4]
8002654: 681b ldr r3, [r3, #0]
8002656: 69da ldr r2, [r3, #28]
8002658: 687b ldr r3, [r7, #4]
800265a: 681b ldr r3, [r3, #0]
800265c: f422 6200 bic.w r2, r2, #2048 @ 0x800
8002660: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8002662: 687b ldr r3, [r7, #4]
8002664: 2200 movs r2, #0
8002666: 655a str r2, [r3, #84] @ 0x54
hspi->State = HAL_SPI_STATE_READY;
8002668: 687b ldr r3, [r7, #4]
800266a: 2201 movs r2, #1
800266c: f883 2051 strb.w r2, [r3, #81] @ 0x51
return HAL_OK;
8002670: 2300 movs r3, #0
}
8002672: 4618 mov r0, r3
8002674: 3708 adds r7, #8
8002676: 46bd mov sp, r7
8002678: bd80 pop {r7, pc}
0800267a <HAL_SPI_Transmit>:
* @param Size amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration in ms
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800267a: b580 push {r7, lr}
800267c: b088 sub sp, #32
800267e: af00 add r7, sp, #0
8002680: 60f8 str r0, [r7, #12]
8002682: 60b9 str r1, [r7, #8]
8002684: 603b str r3, [r7, #0]
8002686: 4613 mov r3, r2
8002688: 80fb strh r3, [r7, #6]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800268a: f7fe ff09 bl 80014a0 <HAL_GetTick>
800268e: 61f8 str r0, [r7, #28]
initial_TxXferCount = Size;
8002690: 88fb ldrh r3, [r7, #6]
8002692: 837b strh r3, [r7, #26]
if (hspi->State != HAL_SPI_STATE_READY)
8002694: 68fb ldr r3, [r7, #12]
8002696: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
800269a: b2db uxtb r3, r3
800269c: 2b01 cmp r3, #1
800269e: d001 beq.n 80026a4 <HAL_SPI_Transmit+0x2a>
{
return HAL_BUSY;
80026a0: 2302 movs r3, #2
80026a2: e12a b.n 80028fa <HAL_SPI_Transmit+0x280>
}
if ((pData == NULL) || (Size == 0U))
80026a4: 68bb ldr r3, [r7, #8]
80026a6: 2b00 cmp r3, #0
80026a8: d002 beq.n 80026b0 <HAL_SPI_Transmit+0x36>
80026aa: 88fb ldrh r3, [r7, #6]
80026ac: 2b00 cmp r3, #0
80026ae: d101 bne.n 80026b4 <HAL_SPI_Transmit+0x3a>
{
return HAL_ERROR;
80026b0: 2301 movs r3, #1
80026b2: e122 b.n 80028fa <HAL_SPI_Transmit+0x280>
}
/* Process Locked */
__HAL_LOCK(hspi);
80026b4: 68fb ldr r3, [r7, #12]
80026b6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
80026ba: 2b01 cmp r3, #1
80026bc: d101 bne.n 80026c2 <HAL_SPI_Transmit+0x48>
80026be: 2302 movs r3, #2
80026c0: e11b b.n 80028fa <HAL_SPI_Transmit+0x280>
80026c2: 68fb ldr r3, [r7, #12]
80026c4: 2201 movs r2, #1
80026c6: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
80026ca: 68fb ldr r3, [r7, #12]
80026cc: 2203 movs r2, #3
80026ce: f883 2051 strb.w r2, [r3, #81] @ 0x51
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
80026d2: 68fb ldr r3, [r7, #12]
80026d4: 2200 movs r2, #0
80026d6: 655a str r2, [r3, #84] @ 0x54
hspi->pTxBuffPtr = (const uint8_t *)pData;
80026d8: 68fb ldr r3, [r7, #12]
80026da: 68ba ldr r2, [r7, #8]
80026dc: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferSize = Size;
80026de: 68fb ldr r3, [r7, #12]
80026e0: 88fa ldrh r2, [r7, #6]
80026e2: 869a strh r2, [r3, #52] @ 0x34
hspi->TxXferCount = Size;
80026e4: 68fb ldr r3, [r7, #12]
80026e6: 88fa ldrh r2, [r7, #6]
80026e8: 86da strh r2, [r3, #54] @ 0x36
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
80026ea: 68fb ldr r3, [r7, #12]
80026ec: 2200 movs r2, #0
80026ee: 639a str r2, [r3, #56] @ 0x38
hspi->RxXferSize = 0U;
80026f0: 68fb ldr r3, [r7, #12]
80026f2: 2200 movs r2, #0
80026f4: 879a strh r2, [r3, #60] @ 0x3c
hspi->RxXferCount = 0U;
80026f6: 68fb ldr r3, [r7, #12]
80026f8: 2200 movs r2, #0
80026fa: 87da strh r2, [r3, #62] @ 0x3e
hspi->TxISR = NULL;
80026fc: 68fb ldr r3, [r7, #12]
80026fe: 2200 movs r2, #0
8002700: 645a str r2, [r3, #68] @ 0x44
hspi->RxISR = NULL;
8002702: 68fb ldr r3, [r7, #12]
8002704: 2200 movs r2, #0
8002706: 641a str r2, [r3, #64] @ 0x40
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
8002708: 68fb ldr r3, [r7, #12]
800270a: 689b ldr r3, [r3, #8]
800270c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8002710: d10f bne.n 8002732 <HAL_SPI_Transmit+0xb8>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
8002712: 68fb ldr r3, [r7, #12]
8002714: 681b ldr r3, [r3, #0]
8002716: 681a ldr r2, [r3, #0]
8002718: 68fb ldr r3, [r7, #12]
800271a: 681b ldr r3, [r3, #0]
800271c: f022 0240 bic.w r2, r2, #64 @ 0x40
8002720: 601a str r2, [r3, #0]
SPI_1LINE_TX(hspi);
8002722: 68fb ldr r3, [r7, #12]
8002724: 681b ldr r3, [r3, #0]
8002726: 681a ldr r2, [r3, #0]
8002728: 68fb ldr r3, [r7, #12]
800272a: 681b ldr r3, [r3, #0]
800272c: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8002730: 601a str r2, [r3, #0]
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8002732: 68fb ldr r3, [r7, #12]
8002734: 681b ldr r3, [r3, #0]
8002736: 681b ldr r3, [r3, #0]
8002738: f003 0340 and.w r3, r3, #64 @ 0x40
800273c: 2b40 cmp r3, #64 @ 0x40
800273e: d007 beq.n 8002750 <HAL_SPI_Transmit+0xd6>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8002740: 68fb ldr r3, [r7, #12]
8002742: 681b ldr r3, [r3, #0]
8002744: 681a ldr r2, [r3, #0]
8002746: 68fb ldr r3, [r7, #12]
8002748: 681b ldr r3, [r3, #0]
800274a: f042 0240 orr.w r2, r2, #64 @ 0x40
800274e: 601a str r2, [r3, #0]
}
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
8002750: 68fb ldr r3, [r7, #12]
8002752: 68db ldr r3, [r3, #12]
8002754: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8002758: d152 bne.n 8002800 <HAL_SPI_Transmit+0x186>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800275a: 68fb ldr r3, [r7, #12]
800275c: 685b ldr r3, [r3, #4]
800275e: 2b00 cmp r3, #0
8002760: d002 beq.n 8002768 <HAL_SPI_Transmit+0xee>
8002762: 8b7b ldrh r3, [r7, #26]
8002764: 2b01 cmp r3, #1
8002766: d145 bne.n 80027f4 <HAL_SPI_Transmit+0x17a>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
8002768: 68fb ldr r3, [r7, #12]
800276a: 6b1b ldr r3, [r3, #48] @ 0x30
800276c: 881a ldrh r2, [r3, #0]
800276e: 68fb ldr r3, [r7, #12]
8002770: 681b ldr r3, [r3, #0]
8002772: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002774: 68fb ldr r3, [r7, #12]
8002776: 6b1b ldr r3, [r3, #48] @ 0x30
8002778: 1c9a adds r2, r3, #2
800277a: 68fb ldr r3, [r7, #12]
800277c: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
800277e: 68fb ldr r3, [r7, #12]
8002780: 8edb ldrh r3, [r3, #54] @ 0x36
8002782: b29b uxth r3, r3
8002784: 3b01 subs r3, #1
8002786: b29a uxth r2, r3
8002788: 68fb ldr r3, [r7, #12]
800278a: 86da strh r2, [r3, #54] @ 0x36
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
800278c: e032 b.n 80027f4 <HAL_SPI_Transmit+0x17a>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
800278e: 68fb ldr r3, [r7, #12]
8002790: 681b ldr r3, [r3, #0]
8002792: 689b ldr r3, [r3, #8]
8002794: f003 0302 and.w r3, r3, #2
8002798: 2b02 cmp r3, #2
800279a: d112 bne.n 80027c2 <HAL_SPI_Transmit+0x148>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
800279c: 68fb ldr r3, [r7, #12]
800279e: 6b1b ldr r3, [r3, #48] @ 0x30
80027a0: 881a ldrh r2, [r3, #0]
80027a2: 68fb ldr r3, [r7, #12]
80027a4: 681b ldr r3, [r3, #0]
80027a6: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
80027a8: 68fb ldr r3, [r7, #12]
80027aa: 6b1b ldr r3, [r3, #48] @ 0x30
80027ac: 1c9a adds r2, r3, #2
80027ae: 68fb ldr r3, [r7, #12]
80027b0: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
80027b2: 68fb ldr r3, [r7, #12]
80027b4: 8edb ldrh r3, [r3, #54] @ 0x36
80027b6: b29b uxth r3, r3
80027b8: 3b01 subs r3, #1
80027ba: b29a uxth r2, r3
80027bc: 68fb ldr r3, [r7, #12]
80027be: 86da strh r2, [r3, #54] @ 0x36
80027c0: e018 b.n 80027f4 <HAL_SPI_Transmit+0x17a>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
80027c2: f7fe fe6d bl 80014a0 <HAL_GetTick>
80027c6: 4602 mov r2, r0
80027c8: 69fb ldr r3, [r7, #28]
80027ca: 1ad3 subs r3, r2, r3
80027cc: 683a ldr r2, [r7, #0]
80027ce: 429a cmp r2, r3
80027d0: d803 bhi.n 80027da <HAL_SPI_Transmit+0x160>
80027d2: 683b ldr r3, [r7, #0]
80027d4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80027d8: d102 bne.n 80027e0 <HAL_SPI_Transmit+0x166>
80027da: 683b ldr r3, [r7, #0]
80027dc: 2b00 cmp r3, #0
80027de: d109 bne.n 80027f4 <HAL_SPI_Transmit+0x17a>
{
hspi->State = HAL_SPI_STATE_READY;
80027e0: 68fb ldr r3, [r7, #12]
80027e2: 2201 movs r2, #1
80027e4: f883 2051 strb.w r2, [r3, #81] @ 0x51
__HAL_UNLOCK(hspi);
80027e8: 68fb ldr r3, [r7, #12]
80027ea: 2200 movs r2, #0
80027ec: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
80027f0: 2303 movs r3, #3
80027f2: e082 b.n 80028fa <HAL_SPI_Transmit+0x280>
while (hspi->TxXferCount > 0U)
80027f4: 68fb ldr r3, [r7, #12]
80027f6: 8edb ldrh r3, [r3, #54] @ 0x36
80027f8: b29b uxth r3, r3
80027fa: 2b00 cmp r3, #0
80027fc: d1c7 bne.n 800278e <HAL_SPI_Transmit+0x114>
80027fe: e053 b.n 80028a8 <HAL_SPI_Transmit+0x22e>
}
}
/* Transmit data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8002800: 68fb ldr r3, [r7, #12]
8002802: 685b ldr r3, [r3, #4]
8002804: 2b00 cmp r3, #0
8002806: d002 beq.n 800280e <HAL_SPI_Transmit+0x194>
8002808: 8b7b ldrh r3, [r7, #26]
800280a: 2b01 cmp r3, #1
800280c: d147 bne.n 800289e <HAL_SPI_Transmit+0x224>
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
800280e: 68fb ldr r3, [r7, #12]
8002810: 6b1a ldr r2, [r3, #48] @ 0x30
8002812: 68fb ldr r3, [r7, #12]
8002814: 681b ldr r3, [r3, #0]
8002816: 330c adds r3, #12
8002818: 7812 ldrb r2, [r2, #0]
800281a: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
800281c: 68fb ldr r3, [r7, #12]
800281e: 6b1b ldr r3, [r3, #48] @ 0x30
8002820: 1c5a adds r2, r3, #1
8002822: 68fb ldr r3, [r7, #12]
8002824: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
8002826: 68fb ldr r3, [r7, #12]
8002828: 8edb ldrh r3, [r3, #54] @ 0x36
800282a: b29b uxth r3, r3
800282c: 3b01 subs r3, #1
800282e: b29a uxth r2, r3
8002830: 68fb ldr r3, [r7, #12]
8002832: 86da strh r2, [r3, #54] @ 0x36
}
while (hspi->TxXferCount > 0U)
8002834: e033 b.n 800289e <HAL_SPI_Transmit+0x224>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
8002836: 68fb ldr r3, [r7, #12]
8002838: 681b ldr r3, [r3, #0]
800283a: 689b ldr r3, [r3, #8]
800283c: f003 0302 and.w r3, r3, #2
8002840: 2b02 cmp r3, #2
8002842: d113 bne.n 800286c <HAL_SPI_Transmit+0x1f2>
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
8002844: 68fb ldr r3, [r7, #12]
8002846: 6b1a ldr r2, [r3, #48] @ 0x30
8002848: 68fb ldr r3, [r7, #12]
800284a: 681b ldr r3, [r3, #0]
800284c: 330c adds r3, #12
800284e: 7812 ldrb r2, [r2, #0]
8002850: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
8002852: 68fb ldr r3, [r7, #12]
8002854: 6b1b ldr r3, [r3, #48] @ 0x30
8002856: 1c5a adds r2, r3, #1
8002858: 68fb ldr r3, [r7, #12]
800285a: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
800285c: 68fb ldr r3, [r7, #12]
800285e: 8edb ldrh r3, [r3, #54] @ 0x36
8002860: b29b uxth r3, r3
8002862: 3b01 subs r3, #1
8002864: b29a uxth r2, r3
8002866: 68fb ldr r3, [r7, #12]
8002868: 86da strh r2, [r3, #54] @ 0x36
800286a: e018 b.n 800289e <HAL_SPI_Transmit+0x224>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
800286c: f7fe fe18 bl 80014a0 <HAL_GetTick>
8002870: 4602 mov r2, r0
8002872: 69fb ldr r3, [r7, #28]
8002874: 1ad3 subs r3, r2, r3
8002876: 683a ldr r2, [r7, #0]
8002878: 429a cmp r2, r3
800287a: d803 bhi.n 8002884 <HAL_SPI_Transmit+0x20a>
800287c: 683b ldr r3, [r7, #0]
800287e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002882: d102 bne.n 800288a <HAL_SPI_Transmit+0x210>
8002884: 683b ldr r3, [r7, #0]
8002886: 2b00 cmp r3, #0
8002888: d109 bne.n 800289e <HAL_SPI_Transmit+0x224>
{
hspi->State = HAL_SPI_STATE_READY;
800288a: 68fb ldr r3, [r7, #12]
800288c: 2201 movs r2, #1
800288e: f883 2051 strb.w r2, [r3, #81] @ 0x51
__HAL_UNLOCK(hspi);
8002892: 68fb ldr r3, [r7, #12]
8002894: 2200 movs r2, #0
8002896: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
800289a: 2303 movs r3, #3
800289c: e02d b.n 80028fa <HAL_SPI_Transmit+0x280>
while (hspi->TxXferCount > 0U)
800289e: 68fb ldr r3, [r7, #12]
80028a0: 8edb ldrh r3, [r3, #54] @ 0x36
80028a2: b29b uxth r3, r3
80028a4: 2b00 cmp r3, #0
80028a6: d1c6 bne.n 8002836 <HAL_SPI_Transmit+0x1bc>
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
80028a8: 69fa ldr r2, [r7, #28]
80028aa: 6839 ldr r1, [r7, #0]
80028ac: 68f8 ldr r0, [r7, #12]
80028ae: f000 f8b1 bl 8002a14 <SPI_EndRxTxTransaction>
80028b2: 4603 mov r3, r0
80028b4: 2b00 cmp r3, #0
80028b6: d002 beq.n 80028be <HAL_SPI_Transmit+0x244>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
80028b8: 68fb ldr r3, [r7, #12]
80028ba: 2220 movs r2, #32
80028bc: 655a str r2, [r3, #84] @ 0x54
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
80028be: 68fb ldr r3, [r7, #12]
80028c0: 689b ldr r3, [r3, #8]
80028c2: 2b00 cmp r3, #0
80028c4: d10a bne.n 80028dc <HAL_SPI_Transmit+0x262>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
80028c6: 2300 movs r3, #0
80028c8: 617b str r3, [r7, #20]
80028ca: 68fb ldr r3, [r7, #12]
80028cc: 681b ldr r3, [r3, #0]
80028ce: 68db ldr r3, [r3, #12]
80028d0: 617b str r3, [r7, #20]
80028d2: 68fb ldr r3, [r7, #12]
80028d4: 681b ldr r3, [r3, #0]
80028d6: 689b ldr r3, [r3, #8]
80028d8: 617b str r3, [r7, #20]
80028da: 697b ldr r3, [r7, #20]
}
hspi->State = HAL_SPI_STATE_READY;
80028dc: 68fb ldr r3, [r7, #12]
80028de: 2201 movs r2, #1
80028e0: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80028e4: 68fb ldr r3, [r7, #12]
80028e6: 2200 movs r2, #0
80028e8: f883 2050 strb.w r2, [r3, #80] @ 0x50
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
80028ec: 68fb ldr r3, [r7, #12]
80028ee: 6d5b ldr r3, [r3, #84] @ 0x54
80028f0: 2b00 cmp r3, #0
80028f2: d001 beq.n 80028f8 <HAL_SPI_Transmit+0x27e>
{
return HAL_ERROR;
80028f4: 2301 movs r3, #1
80028f6: e000 b.n 80028fa <HAL_SPI_Transmit+0x280>
}
else
{
return HAL_OK;
80028f8: 2300 movs r3, #0
}
}
80028fa: 4618 mov r0, r3
80028fc: 3720 adds r7, #32
80028fe: 46bd mov sp, r7
8002900: bd80 pop {r7, pc}
...
08002904 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8002904: b580 push {r7, lr}
8002906: b088 sub sp, #32
8002908: af00 add r7, sp, #0
800290a: 60f8 str r0, [r7, #12]
800290c: 60b9 str r1, [r7, #8]
800290e: 603b str r3, [r7, #0]
8002910: 4613 mov r3, r2
8002912: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8002914: f7fe fdc4 bl 80014a0 <HAL_GetTick>
8002918: 4602 mov r2, r0
800291a: 6abb ldr r3, [r7, #40] @ 0x28
800291c: 1a9b subs r3, r3, r2
800291e: 683a ldr r2, [r7, #0]
8002920: 4413 add r3, r2
8002922: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
8002924: f7fe fdbc bl 80014a0 <HAL_GetTick>
8002928: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
800292a: 4b39 ldr r3, [pc, #228] @ (8002a10 <SPI_WaitFlagStateUntilTimeout+0x10c>)
800292c: 681b ldr r3, [r3, #0]
800292e: 015b lsls r3, r3, #5
8002930: 0d1b lsrs r3, r3, #20
8002932: 69fa ldr r2, [r7, #28]
8002934: fb02 f303 mul.w r3, r2, r3
8002938: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
800293a: e054 b.n 80029e6 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
800293c: 683b ldr r3, [r7, #0]
800293e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002942: d050 beq.n 80029e6 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
8002944: f7fe fdac bl 80014a0 <HAL_GetTick>
8002948: 4602 mov r2, r0
800294a: 69bb ldr r3, [r7, #24]
800294c: 1ad3 subs r3, r2, r3
800294e: 69fa ldr r2, [r7, #28]
8002950: 429a cmp r2, r3
8002952: d902 bls.n 800295a <SPI_WaitFlagStateUntilTimeout+0x56>
8002954: 69fb ldr r3, [r7, #28]
8002956: 2b00 cmp r3, #0
8002958: d13d bne.n 80029d6 <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
800295a: 68fb ldr r3, [r7, #12]
800295c: 681b ldr r3, [r3, #0]
800295e: 685a ldr r2, [r3, #4]
8002960: 68fb ldr r3, [r7, #12]
8002962: 681b ldr r3, [r3, #0]
8002964: f022 02e0 bic.w r2, r2, #224 @ 0xe0
8002968: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
800296a: 68fb ldr r3, [r7, #12]
800296c: 685b ldr r3, [r3, #4]
800296e: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002972: d111 bne.n 8002998 <SPI_WaitFlagStateUntilTimeout+0x94>
8002974: 68fb ldr r3, [r7, #12]
8002976: 689b ldr r3, [r3, #8]
8002978: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800297c: d004 beq.n 8002988 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800297e: 68fb ldr r3, [r7, #12]
8002980: 689b ldr r3, [r3, #8]
8002982: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002986: d107 bne.n 8002998 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8002988: 68fb ldr r3, [r7, #12]
800298a: 681b ldr r3, [r3, #0]
800298c: 681a ldr r2, [r3, #0]
800298e: 68fb ldr r3, [r7, #12]
8002990: 681b ldr r3, [r3, #0]
8002992: f022 0240 bic.w r2, r2, #64 @ 0x40
8002996: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8002998: 68fb ldr r3, [r7, #12]
800299a: 6a9b ldr r3, [r3, #40] @ 0x28
800299c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80029a0: d10f bne.n 80029c2 <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
80029a2: 68fb ldr r3, [r7, #12]
80029a4: 681b ldr r3, [r3, #0]
80029a6: 681a ldr r2, [r3, #0]
80029a8: 68fb ldr r3, [r7, #12]
80029aa: 681b ldr r3, [r3, #0]
80029ac: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80029b0: 601a str r2, [r3, #0]
80029b2: 68fb ldr r3, [r7, #12]
80029b4: 681b ldr r3, [r3, #0]
80029b6: 681a ldr r2, [r3, #0]
80029b8: 68fb ldr r3, [r7, #12]
80029ba: 681b ldr r3, [r3, #0]
80029bc: f442 5200 orr.w r2, r2, #8192 @ 0x2000
80029c0: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
80029c2: 68fb ldr r3, [r7, #12]
80029c4: 2201 movs r2, #1
80029c6: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80029ca: 68fb ldr r3, [r7, #12]
80029cc: 2200 movs r2, #0
80029ce: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
80029d2: 2303 movs r3, #3
80029d4: e017 b.n 8002a06 <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
80029d6: 697b ldr r3, [r7, #20]
80029d8: 2b00 cmp r3, #0
80029da: d101 bne.n 80029e0 <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
80029dc: 2300 movs r3, #0
80029de: 61fb str r3, [r7, #28]
}
count--;
80029e0: 697b ldr r3, [r7, #20]
80029e2: 3b01 subs r3, #1
80029e4: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
80029e6: 68fb ldr r3, [r7, #12]
80029e8: 681b ldr r3, [r3, #0]
80029ea: 689a ldr r2, [r3, #8]
80029ec: 68bb ldr r3, [r7, #8]
80029ee: 4013 ands r3, r2
80029f0: 68ba ldr r2, [r7, #8]
80029f2: 429a cmp r2, r3
80029f4: bf0c ite eq
80029f6: 2301 moveq r3, #1
80029f8: 2300 movne r3, #0
80029fa: b2db uxtb r3, r3
80029fc: 461a mov r2, r3
80029fe: 79fb ldrb r3, [r7, #7]
8002a00: 429a cmp r2, r3
8002a02: d19b bne.n 800293c <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
8002a04: 2300 movs r3, #0
}
8002a06: 4618 mov r0, r3
8002a08: 3720 adds r7, #32
8002a0a: 46bd mov sp, r7
8002a0c: bd80 pop {r7, pc}
8002a0e: bf00 nop
8002a10: 20000004 .word 0x20000004
08002a14 <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
8002a14: b580 push {r7, lr}
8002a16: b088 sub sp, #32
8002a18: af02 add r7, sp, #8
8002a1a: 60f8 str r0, [r7, #12]
8002a1c: 60b9 str r1, [r7, #8]
8002a1e: 607a str r2, [r7, #4]
/* Wait until TXE flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK)
8002a20: 687b ldr r3, [r7, #4]
8002a22: 9300 str r3, [sp, #0]
8002a24: 68bb ldr r3, [r7, #8]
8002a26: 2201 movs r2, #1
8002a28: 2102 movs r1, #2
8002a2a: 68f8 ldr r0, [r7, #12]
8002a2c: f7ff ff6a bl 8002904 <SPI_WaitFlagStateUntilTimeout>
8002a30: 4603 mov r3, r0
8002a32: 2b00 cmp r3, #0
8002a34: d007 beq.n 8002a46 <SPI_EndRxTxTransaction+0x32>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002a36: 68fb ldr r3, [r7, #12]
8002a38: 6d5b ldr r3, [r3, #84] @ 0x54
8002a3a: f043 0220 orr.w r2, r3, #32
8002a3e: 68fb ldr r3, [r7, #12]
8002a40: 655a str r2, [r3, #84] @ 0x54
return HAL_TIMEOUT;
8002a42: 2303 movs r3, #3
8002a44: e032 b.n 8002aac <SPI_EndRxTxTransaction+0x98>
}
/* Timeout in us */
__IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
8002a46: 4b1b ldr r3, [pc, #108] @ (8002ab4 <SPI_EndRxTxTransaction+0xa0>)
8002a48: 681b ldr r3, [r3, #0]
8002a4a: 4a1b ldr r2, [pc, #108] @ (8002ab8 <SPI_EndRxTxTransaction+0xa4>)
8002a4c: fba2 2303 umull r2, r3, r2, r3
8002a50: 0d5b lsrs r3, r3, #21
8002a52: f44f 727a mov.w r2, #1000 @ 0x3e8
8002a56: fb02 f303 mul.w r3, r2, r3
8002a5a: 617b str r3, [r7, #20]
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
if (hspi->Init.Mode == SPI_MODE_MASTER)
8002a5c: 68fb ldr r3, [r7, #12]
8002a5e: 685b ldr r3, [r3, #4]
8002a60: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002a64: d112 bne.n 8002a8c <SPI_EndRxTxTransaction+0x78>
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8002a66: 687b ldr r3, [r7, #4]
8002a68: 9300 str r3, [sp, #0]
8002a6a: 68bb ldr r3, [r7, #8]
8002a6c: 2200 movs r2, #0
8002a6e: 2180 movs r1, #128 @ 0x80
8002a70: 68f8 ldr r0, [r7, #12]
8002a72: f7ff ff47 bl 8002904 <SPI_WaitFlagStateUntilTimeout>
8002a76: 4603 mov r3, r0
8002a78: 2b00 cmp r3, #0
8002a7a: d016 beq.n 8002aaa <SPI_EndRxTxTransaction+0x96>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002a7c: 68fb ldr r3, [r7, #12]
8002a7e: 6d5b ldr r3, [r3, #84] @ 0x54
8002a80: f043 0220 orr.w r2, r3, #32
8002a84: 68fb ldr r3, [r7, #12]
8002a86: 655a str r2, [r3, #84] @ 0x54
return HAL_TIMEOUT;
8002a88: 2303 movs r3, #3
8002a8a: e00f b.n 8002aac <SPI_EndRxTxTransaction+0x98>
* User have to calculate the timeout value to fit with the time of 1 byte transfer.
* This time is directly link with the SPI clock from Master device.
*/
do
{
if (count == 0U)
8002a8c: 697b ldr r3, [r7, #20]
8002a8e: 2b00 cmp r3, #0
8002a90: d00a beq.n 8002aa8 <SPI_EndRxTxTransaction+0x94>
{
break;
}
count--;
8002a92: 697b ldr r3, [r7, #20]
8002a94: 3b01 subs r3, #1
8002a96: 617b str r3, [r7, #20]
} while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
8002a98: 68fb ldr r3, [r7, #12]
8002a9a: 681b ldr r3, [r3, #0]
8002a9c: 689b ldr r3, [r3, #8]
8002a9e: f003 0380 and.w r3, r3, #128 @ 0x80
8002aa2: 2b80 cmp r3, #128 @ 0x80
8002aa4: d0f2 beq.n 8002a8c <SPI_EndRxTxTransaction+0x78>
8002aa6: e000 b.n 8002aaa <SPI_EndRxTxTransaction+0x96>
break;
8002aa8: bf00 nop
}
return HAL_OK;
8002aaa: 2300 movs r3, #0
}
8002aac: 4618 mov r0, r3
8002aae: 3718 adds r7, #24
8002ab0: 46bd mov sp, r7
8002ab2: bd80 pop {r7, pc}
8002ab4: 20000004 .word 0x20000004
8002ab8: 165e9f81 .word 0x165e9f81
08002abc <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8002abc: b580 push {r7, lr}
8002abe: b082 sub sp, #8
8002ac0: af00 add r7, sp, #0
8002ac2: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002ac4: 687b ldr r3, [r7, #4]
8002ac6: 2b00 cmp r3, #0
8002ac8: d101 bne.n 8002ace <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8002aca: 2301 movs r3, #1
8002acc: e031 b.n 8002b32 <HAL_TIM_Base_Init+0x76>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002ace: 687b ldr r3, [r7, #4]
8002ad0: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8002ad4: b2db uxtb r3, r3
8002ad6: 2b00 cmp r3, #0
8002ad8: d106 bne.n 8002ae8 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002ada: 687b ldr r3, [r7, #4]
8002adc: 2200 movs r2, #0
8002ade: f883 2038 strb.w r2, [r3, #56] @ 0x38
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8002ae2: 6878 ldr r0, [r7, #4]
8002ae4: f7fe fad8 bl 8001098 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002ae8: 687b ldr r3, [r7, #4]
8002aea: 2202 movs r2, #2
8002aec: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002af0: 687b ldr r3, [r7, #4]
8002af2: 681a ldr r2, [r3, #0]
8002af4: 687b ldr r3, [r7, #4]
8002af6: 3304 adds r3, #4
8002af8: 4619 mov r1, r3
8002afa: 4610 mov r0, r2
8002afc: f000 fbc8 bl 8003290 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002b00: 687b ldr r3, [r7, #4]
8002b02: 2201 movs r2, #1
8002b04: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002b08: 687b ldr r3, [r7, #4]
8002b0a: 2201 movs r2, #1
8002b0c: f883 203a strb.w r2, [r3, #58] @ 0x3a
8002b10: 687b ldr r3, [r7, #4]
8002b12: 2201 movs r2, #1
8002b14: f883 203b strb.w r2, [r3, #59] @ 0x3b
8002b18: 687b ldr r3, [r7, #4]
8002b1a: 2201 movs r2, #1
8002b1c: f883 203c strb.w r2, [r3, #60] @ 0x3c
8002b20: 687b ldr r3, [r7, #4]
8002b22: 2201 movs r2, #1
8002b24: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002b28: 687b ldr r3, [r7, #4]
8002b2a: 2201 movs r2, #1
8002b2c: f883 2039 strb.w r2, [r3, #57] @ 0x39
return HAL_OK;
8002b30: 2300 movs r3, #0
}
8002b32: 4618 mov r0, r3
8002b34: 3708 adds r7, #8
8002b36: 46bd mov sp, r7
8002b38: bd80 pop {r7, pc}
...
08002b3c <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8002b3c: b480 push {r7}
8002b3e: b085 sub sp, #20
8002b40: af00 add r7, sp, #0
8002b42: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8002b44: 687b ldr r3, [r7, #4]
8002b46: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8002b4a: b2db uxtb r3, r3
8002b4c: 2b01 cmp r3, #1
8002b4e: d001 beq.n 8002b54 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8002b50: 2301 movs r3, #1
8002b52: e03a b.n 8002bca <HAL_TIM_Base_Start_IT+0x8e>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002b54: 687b ldr r3, [r7, #4]
8002b56: 2202 movs r2, #2
8002b58: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8002b5c: 687b ldr r3, [r7, #4]
8002b5e: 681b ldr r3, [r3, #0]
8002b60: 68da ldr r2, [r3, #12]
8002b62: 687b ldr r3, [r7, #4]
8002b64: 681b ldr r3, [r3, #0]
8002b66: f042 0201 orr.w r2, r2, #1
8002b6a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002b6c: 687b ldr r3, [r7, #4]
8002b6e: 681b ldr r3, [r3, #0]
8002b70: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002b74: d00e beq.n 8002b94 <HAL_TIM_Base_Start_IT+0x58>
8002b76: 687b ldr r3, [r7, #4]
8002b78: 681b ldr r3, [r3, #0]
8002b7a: 4a16 ldr r2, [pc, #88] @ (8002bd4 <HAL_TIM_Base_Start_IT+0x98>)
8002b7c: 4293 cmp r3, r2
8002b7e: d009 beq.n 8002b94 <HAL_TIM_Base_Start_IT+0x58>
8002b80: 687b ldr r3, [r7, #4]
8002b82: 681b ldr r3, [r3, #0]
8002b84: 4a14 ldr r2, [pc, #80] @ (8002bd8 <HAL_TIM_Base_Start_IT+0x9c>)
8002b86: 4293 cmp r3, r2
8002b88: d004 beq.n 8002b94 <HAL_TIM_Base_Start_IT+0x58>
8002b8a: 687b ldr r3, [r7, #4]
8002b8c: 681b ldr r3, [r3, #0]
8002b8e: 4a13 ldr r2, [pc, #76] @ (8002bdc <HAL_TIM_Base_Start_IT+0xa0>)
8002b90: 4293 cmp r3, r2
8002b92: d111 bne.n 8002bb8 <HAL_TIM_Base_Start_IT+0x7c>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8002b94: 687b ldr r3, [r7, #4]
8002b96: 681b ldr r3, [r3, #0]
8002b98: 689b ldr r3, [r3, #8]
8002b9a: f003 0307 and.w r3, r3, #7
8002b9e: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002ba0: 68fb ldr r3, [r7, #12]
8002ba2: 2b06 cmp r3, #6
8002ba4: d010 beq.n 8002bc8 <HAL_TIM_Base_Start_IT+0x8c>
{
__HAL_TIM_ENABLE(htim);
8002ba6: 687b ldr r3, [r7, #4]
8002ba8: 681b ldr r3, [r3, #0]
8002baa: 681a ldr r2, [r3, #0]
8002bac: 687b ldr r3, [r7, #4]
8002bae: 681b ldr r3, [r3, #0]
8002bb0: f042 0201 orr.w r2, r2, #1
8002bb4: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002bb6: e007 b.n 8002bc8 <HAL_TIM_Base_Start_IT+0x8c>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002bb8: 687b ldr r3, [r7, #4]
8002bba: 681b ldr r3, [r3, #0]
8002bbc: 681a ldr r2, [r3, #0]
8002bbe: 687b ldr r3, [r7, #4]
8002bc0: 681b ldr r3, [r3, #0]
8002bc2: f042 0201 orr.w r2, r2, #1
8002bc6: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8002bc8: 2300 movs r3, #0
}
8002bca: 4618 mov r0, r3
8002bcc: 3714 adds r7, #20
8002bce: 46bd mov sp, r7
8002bd0: bc80 pop {r7}
8002bd2: 4770 bx lr
8002bd4: 40000400 .word 0x40000400
8002bd8: 40000800 .word 0x40000800
8002bdc: 40010800 .word 0x40010800
08002be0 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8002be0: b580 push {r7, lr}
8002be2: b082 sub sp, #8
8002be4: af00 add r7, sp, #0
8002be6: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002be8: 687b ldr r3, [r7, #4]
8002bea: 2b00 cmp r3, #0
8002bec: d101 bne.n 8002bf2 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8002bee: 2301 movs r3, #1
8002bf0: e031 b.n 8002c56 <HAL_TIM_PWM_Init+0x76>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8002bf2: 687b ldr r3, [r7, #4]
8002bf4: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8002bf8: b2db uxtb r3, r3
8002bfa: 2b00 cmp r3, #0
8002bfc: d106 bne.n 8002c0c <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002bfe: 687b ldr r3, [r7, #4]
8002c00: 2200 movs r2, #0
8002c02: f883 2038 strb.w r2, [r3, #56] @ 0x38
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8002c06: 6878 ldr r0, [r7, #4]
8002c08: f000 f829 bl 8002c5e <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002c0c: 687b ldr r3, [r7, #4]
8002c0e: 2202 movs r2, #2
8002c10: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002c14: 687b ldr r3, [r7, #4]
8002c16: 681a ldr r2, [r3, #0]
8002c18: 687b ldr r3, [r7, #4]
8002c1a: 3304 adds r3, #4
8002c1c: 4619 mov r1, r3
8002c1e: 4610 mov r0, r2
8002c20: f000 fb36 bl 8003290 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002c24: 687b ldr r3, [r7, #4]
8002c26: 2201 movs r2, #1
8002c28: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002c2c: 687b ldr r3, [r7, #4]
8002c2e: 2201 movs r2, #1
8002c30: f883 203a strb.w r2, [r3, #58] @ 0x3a
8002c34: 687b ldr r3, [r7, #4]
8002c36: 2201 movs r2, #1
8002c38: f883 203b strb.w r2, [r3, #59] @ 0x3b
8002c3c: 687b ldr r3, [r7, #4]
8002c3e: 2201 movs r2, #1
8002c40: f883 203c strb.w r2, [r3, #60] @ 0x3c
8002c44: 687b ldr r3, [r7, #4]
8002c46: 2201 movs r2, #1
8002c48: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002c4c: 687b ldr r3, [r7, #4]
8002c4e: 2201 movs r2, #1
8002c50: f883 2039 strb.w r2, [r3, #57] @ 0x39
return HAL_OK;
8002c54: 2300 movs r3, #0
}
8002c56: 4618 mov r0, r3
8002c58: 3708 adds r7, #8
8002c5a: 46bd mov sp, r7
8002c5c: bd80 pop {r7, pc}
08002c5e <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8002c5e: b480 push {r7}
8002c60: b083 sub sp, #12
8002c62: af00 add r7, sp, #0
8002c64: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8002c66: bf00 nop
8002c68: 370c adds r7, #12
8002c6a: 46bd mov sp, r7
8002c6c: bc80 pop {r7}
8002c6e: 4770 bx lr
08002c70 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8002c70: b580 push {r7, lr}
8002c72: b084 sub sp, #16
8002c74: af00 add r7, sp, #0
8002c76: 6078 str r0, [r7, #4]
8002c78: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8002c7a: 683b ldr r3, [r7, #0]
8002c7c: 2b00 cmp r3, #0
8002c7e: d109 bne.n 8002c94 <HAL_TIM_PWM_Start+0x24>
8002c80: 687b ldr r3, [r7, #4]
8002c82: f893 303a ldrb.w r3, [r3, #58] @ 0x3a
8002c86: b2db uxtb r3, r3
8002c88: 2b01 cmp r3, #1
8002c8a: bf14 ite ne
8002c8c: 2301 movne r3, #1
8002c8e: 2300 moveq r3, #0
8002c90: b2db uxtb r3, r3
8002c92: e022 b.n 8002cda <HAL_TIM_PWM_Start+0x6a>
8002c94: 683b ldr r3, [r7, #0]
8002c96: 2b04 cmp r3, #4
8002c98: d109 bne.n 8002cae <HAL_TIM_PWM_Start+0x3e>
8002c9a: 687b ldr r3, [r7, #4]
8002c9c: f893 303b ldrb.w r3, [r3, #59] @ 0x3b
8002ca0: b2db uxtb r3, r3
8002ca2: 2b01 cmp r3, #1
8002ca4: bf14 ite ne
8002ca6: 2301 movne r3, #1
8002ca8: 2300 moveq r3, #0
8002caa: b2db uxtb r3, r3
8002cac: e015 b.n 8002cda <HAL_TIM_PWM_Start+0x6a>
8002cae: 683b ldr r3, [r7, #0]
8002cb0: 2b08 cmp r3, #8
8002cb2: d109 bne.n 8002cc8 <HAL_TIM_PWM_Start+0x58>
8002cb4: 687b ldr r3, [r7, #4]
8002cb6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8002cba: b2db uxtb r3, r3
8002cbc: 2b01 cmp r3, #1
8002cbe: bf14 ite ne
8002cc0: 2301 movne r3, #1
8002cc2: 2300 moveq r3, #0
8002cc4: b2db uxtb r3, r3
8002cc6: e008 b.n 8002cda <HAL_TIM_PWM_Start+0x6a>
8002cc8: 687b ldr r3, [r7, #4]
8002cca: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8002cce: b2db uxtb r3, r3
8002cd0: 2b01 cmp r3, #1
8002cd2: bf14 ite ne
8002cd4: 2301 movne r3, #1
8002cd6: 2300 moveq r3, #0
8002cd8: b2db uxtb r3, r3
8002cda: 2b00 cmp r3, #0
8002cdc: d001 beq.n 8002ce2 <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
8002cde: 2301 movs r3, #1
8002ce0: e051 b.n 8002d86 <HAL_TIM_PWM_Start+0x116>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8002ce2: 683b ldr r3, [r7, #0]
8002ce4: 2b00 cmp r3, #0
8002ce6: d104 bne.n 8002cf2 <HAL_TIM_PWM_Start+0x82>
8002ce8: 687b ldr r3, [r7, #4]
8002cea: 2202 movs r2, #2
8002cec: f883 203a strb.w r2, [r3, #58] @ 0x3a
8002cf0: e013 b.n 8002d1a <HAL_TIM_PWM_Start+0xaa>
8002cf2: 683b ldr r3, [r7, #0]
8002cf4: 2b04 cmp r3, #4
8002cf6: d104 bne.n 8002d02 <HAL_TIM_PWM_Start+0x92>
8002cf8: 687b ldr r3, [r7, #4]
8002cfa: 2202 movs r2, #2
8002cfc: f883 203b strb.w r2, [r3, #59] @ 0x3b
8002d00: e00b b.n 8002d1a <HAL_TIM_PWM_Start+0xaa>
8002d02: 683b ldr r3, [r7, #0]
8002d04: 2b08 cmp r3, #8
8002d06: d104 bne.n 8002d12 <HAL_TIM_PWM_Start+0xa2>
8002d08: 687b ldr r3, [r7, #4]
8002d0a: 2202 movs r2, #2
8002d0c: f883 203c strb.w r2, [r3, #60] @ 0x3c
8002d10: e003 b.n 8002d1a <HAL_TIM_PWM_Start+0xaa>
8002d12: 687b ldr r3, [r7, #4]
8002d14: 2202 movs r2, #2
8002d16: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8002d1a: 687b ldr r3, [r7, #4]
8002d1c: 681b ldr r3, [r3, #0]
8002d1e: 2201 movs r2, #1
8002d20: 6839 ldr r1, [r7, #0]
8002d22: 4618 mov r0, r3
8002d24: f000 fcb5 bl 8003692 <TIM_CCxChannelCmd>
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002d28: 687b ldr r3, [r7, #4]
8002d2a: 681b ldr r3, [r3, #0]
8002d2c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002d30: d00e beq.n 8002d50 <HAL_TIM_PWM_Start+0xe0>
8002d32: 687b ldr r3, [r7, #4]
8002d34: 681b ldr r3, [r3, #0]
8002d36: 4a16 ldr r2, [pc, #88] @ (8002d90 <HAL_TIM_PWM_Start+0x120>)
8002d38: 4293 cmp r3, r2
8002d3a: d009 beq.n 8002d50 <HAL_TIM_PWM_Start+0xe0>
8002d3c: 687b ldr r3, [r7, #4]
8002d3e: 681b ldr r3, [r3, #0]
8002d40: 4a14 ldr r2, [pc, #80] @ (8002d94 <HAL_TIM_PWM_Start+0x124>)
8002d42: 4293 cmp r3, r2
8002d44: d004 beq.n 8002d50 <HAL_TIM_PWM_Start+0xe0>
8002d46: 687b ldr r3, [r7, #4]
8002d48: 681b ldr r3, [r3, #0]
8002d4a: 4a13 ldr r2, [pc, #76] @ (8002d98 <HAL_TIM_PWM_Start+0x128>)
8002d4c: 4293 cmp r3, r2
8002d4e: d111 bne.n 8002d74 <HAL_TIM_PWM_Start+0x104>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8002d50: 687b ldr r3, [r7, #4]
8002d52: 681b ldr r3, [r3, #0]
8002d54: 689b ldr r3, [r3, #8]
8002d56: f003 0307 and.w r3, r3, #7
8002d5a: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002d5c: 68fb ldr r3, [r7, #12]
8002d5e: 2b06 cmp r3, #6
8002d60: d010 beq.n 8002d84 <HAL_TIM_PWM_Start+0x114>
{
__HAL_TIM_ENABLE(htim);
8002d62: 687b ldr r3, [r7, #4]
8002d64: 681b ldr r3, [r3, #0]
8002d66: 681a ldr r2, [r3, #0]
8002d68: 687b ldr r3, [r7, #4]
8002d6a: 681b ldr r3, [r3, #0]
8002d6c: f042 0201 orr.w r2, r2, #1
8002d70: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8002d72: e007 b.n 8002d84 <HAL_TIM_PWM_Start+0x114>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8002d74: 687b ldr r3, [r7, #4]
8002d76: 681b ldr r3, [r3, #0]
8002d78: 681a ldr r2, [r3, #0]
8002d7a: 687b ldr r3, [r7, #4]
8002d7c: 681b ldr r3, [r3, #0]
8002d7e: f042 0201 orr.w r2, r2, #1
8002d82: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8002d84: 2300 movs r3, #0
}
8002d86: 4618 mov r0, r3
8002d88: 3710 adds r7, #16
8002d8a: 46bd mov sp, r7
8002d8c: bd80 pop {r7, pc}
8002d8e: bf00 nop
8002d90: 40000400 .word 0x40000400
8002d94: 40000800 .word 0x40000800
8002d98: 40010800 .word 0x40010800
08002d9c <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8002d9c: b580 push {r7, lr}
8002d9e: b084 sub sp, #16
8002da0: af00 add r7, sp, #0
8002da2: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8002da4: 687b ldr r3, [r7, #4]
8002da6: 681b ldr r3, [r3, #0]
8002da8: 68db ldr r3, [r3, #12]
8002daa: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8002dac: 687b ldr r3, [r7, #4]
8002dae: 681b ldr r3, [r3, #0]
8002db0: 691b ldr r3, [r3, #16]
8002db2: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8002db4: 68bb ldr r3, [r7, #8]
8002db6: f003 0302 and.w r3, r3, #2
8002dba: 2b00 cmp r3, #0
8002dbc: d020 beq.n 8002e00 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8002dbe: 68fb ldr r3, [r7, #12]
8002dc0: f003 0302 and.w r3, r3, #2
8002dc4: 2b00 cmp r3, #0
8002dc6: d01b beq.n 8002e00 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8002dc8: 687b ldr r3, [r7, #4]
8002dca: 681b ldr r3, [r3, #0]
8002dcc: f06f 0202 mvn.w r2, #2
8002dd0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8002dd2: 687b ldr r3, [r7, #4]
8002dd4: 2201 movs r2, #1
8002dd6: 761a strb r2, [r3, #24]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8002dd8: 687b ldr r3, [r7, #4]
8002dda: 681b ldr r3, [r3, #0]
8002ddc: 699b ldr r3, [r3, #24]
8002dde: f003 0303 and.w r3, r3, #3
8002de2: 2b00 cmp r3, #0
8002de4: d003 beq.n 8002dee <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002de6: 6878 ldr r0, [r7, #4]
8002de8: f000 fa36 bl 8003258 <HAL_TIM_IC_CaptureCallback>
8002dec: e005 b.n 8002dfa <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002dee: 6878 ldr r0, [r7, #4]
8002df0: f000 fa29 bl 8003246 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002df4: 6878 ldr r0, [r7, #4]
8002df6: f000 fa38 bl 800326a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002dfa: 687b ldr r3, [r7, #4]
8002dfc: 2200 movs r2, #0
8002dfe: 761a strb r2, [r3, #24]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8002e00: 68bb ldr r3, [r7, #8]
8002e02: f003 0304 and.w r3, r3, #4
8002e06: 2b00 cmp r3, #0
8002e08: d020 beq.n 8002e4c <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
8002e0a: 68fb ldr r3, [r7, #12]
8002e0c: f003 0304 and.w r3, r3, #4
8002e10: 2b00 cmp r3, #0
8002e12: d01b beq.n 8002e4c <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8002e14: 687b ldr r3, [r7, #4]
8002e16: 681b ldr r3, [r3, #0]
8002e18: f06f 0204 mvn.w r2, #4
8002e1c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8002e1e: 687b ldr r3, [r7, #4]
8002e20: 2202 movs r2, #2
8002e22: 761a strb r2, [r3, #24]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8002e24: 687b ldr r3, [r7, #4]
8002e26: 681b ldr r3, [r3, #0]
8002e28: 699b ldr r3, [r3, #24]
8002e2a: f403 7340 and.w r3, r3, #768 @ 0x300
8002e2e: 2b00 cmp r3, #0
8002e30: d003 beq.n 8002e3a <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002e32: 6878 ldr r0, [r7, #4]
8002e34: f000 fa10 bl 8003258 <HAL_TIM_IC_CaptureCallback>
8002e38: e005 b.n 8002e46 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002e3a: 6878 ldr r0, [r7, #4]
8002e3c: f000 fa03 bl 8003246 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002e40: 6878 ldr r0, [r7, #4]
8002e42: f000 fa12 bl 800326a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002e46: 687b ldr r3, [r7, #4]
8002e48: 2200 movs r2, #0
8002e4a: 761a strb r2, [r3, #24]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
8002e4c: 68bb ldr r3, [r7, #8]
8002e4e: f003 0308 and.w r3, r3, #8
8002e52: 2b00 cmp r3, #0
8002e54: d020 beq.n 8002e98 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8002e56: 68fb ldr r3, [r7, #12]
8002e58: f003 0308 and.w r3, r3, #8
8002e5c: 2b00 cmp r3, #0
8002e5e: d01b beq.n 8002e98 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8002e60: 687b ldr r3, [r7, #4]
8002e62: 681b ldr r3, [r3, #0]
8002e64: f06f 0208 mvn.w r2, #8
8002e68: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8002e6a: 687b ldr r3, [r7, #4]
8002e6c: 2204 movs r2, #4
8002e6e: 761a strb r2, [r3, #24]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8002e70: 687b ldr r3, [r7, #4]
8002e72: 681b ldr r3, [r3, #0]
8002e74: 69db ldr r3, [r3, #28]
8002e76: f003 0303 and.w r3, r3, #3
8002e7a: 2b00 cmp r3, #0
8002e7c: d003 beq.n 8002e86 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002e7e: 6878 ldr r0, [r7, #4]
8002e80: f000 f9ea bl 8003258 <HAL_TIM_IC_CaptureCallback>
8002e84: e005 b.n 8002e92 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002e86: 6878 ldr r0, [r7, #4]
8002e88: f000 f9dd bl 8003246 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002e8c: 6878 ldr r0, [r7, #4]
8002e8e: f000 f9ec bl 800326a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002e92: 687b ldr r3, [r7, #4]
8002e94: 2200 movs r2, #0
8002e96: 761a strb r2, [r3, #24]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8002e98: 68bb ldr r3, [r7, #8]
8002e9a: f003 0310 and.w r3, r3, #16
8002e9e: 2b00 cmp r3, #0
8002ea0: d020 beq.n 8002ee4 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8002ea2: 68fb ldr r3, [r7, #12]
8002ea4: f003 0310 and.w r3, r3, #16
8002ea8: 2b00 cmp r3, #0
8002eaa: d01b beq.n 8002ee4 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8002eac: 687b ldr r3, [r7, #4]
8002eae: 681b ldr r3, [r3, #0]
8002eb0: f06f 0210 mvn.w r2, #16
8002eb4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8002eb6: 687b ldr r3, [r7, #4]
8002eb8: 2208 movs r2, #8
8002eba: 761a strb r2, [r3, #24]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8002ebc: 687b ldr r3, [r7, #4]
8002ebe: 681b ldr r3, [r3, #0]
8002ec0: 69db ldr r3, [r3, #28]
8002ec2: f403 7340 and.w r3, r3, #768 @ 0x300
8002ec6: 2b00 cmp r3, #0
8002ec8: d003 beq.n 8002ed2 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8002eca: 6878 ldr r0, [r7, #4]
8002ecc: f000 f9c4 bl 8003258 <HAL_TIM_IC_CaptureCallback>
8002ed0: e005 b.n 8002ede <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8002ed2: 6878 ldr r0, [r7, #4]
8002ed4: f000 f9b7 bl 8003246 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8002ed8: 6878 ldr r0, [r7, #4]
8002eda: f000 f9c6 bl 800326a <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8002ede: 687b ldr r3, [r7, #4]
8002ee0: 2200 movs r2, #0
8002ee2: 761a strb r2, [r3, #24]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8002ee4: 68bb ldr r3, [r7, #8]
8002ee6: f003 0301 and.w r3, r3, #1
8002eea: 2b00 cmp r3, #0
8002eec: d00c beq.n 8002f08 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8002eee: 68fb ldr r3, [r7, #12]
8002ef0: f003 0301 and.w r3, r3, #1
8002ef4: 2b00 cmp r3, #0
8002ef6: d007 beq.n 8002f08 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8002ef8: 687b ldr r3, [r7, #4]
8002efa: 681b ldr r3, [r3, #0]
8002efc: f06f 0201 mvn.w r2, #1
8002f00: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8002f02: 6878 ldr r0, [r7, #4]
8002f04: f7fd ffec bl 8000ee0 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8002f08: 68bb ldr r3, [r7, #8]
8002f0a: f003 0340 and.w r3, r3, #64 @ 0x40
8002f0e: 2b00 cmp r3, #0
8002f10: d00c beq.n 8002f2c <HAL_TIM_IRQHandler+0x190>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8002f12: 68fb ldr r3, [r7, #12]
8002f14: f003 0340 and.w r3, r3, #64 @ 0x40
8002f18: 2b00 cmp r3, #0
8002f1a: d007 beq.n 8002f2c <HAL_TIM_IRQHandler+0x190>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8002f1c: 687b ldr r3, [r7, #4]
8002f1e: 681b ldr r3, [r3, #0]
8002f20: f06f 0240 mvn.w r2, #64 @ 0x40
8002f24: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8002f26: 6878 ldr r0, [r7, #4]
8002f28: f000 f9a8 bl 800327c <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8002f2c: bf00 nop
8002f2e: 3710 adds r7, #16
8002f30: 46bd mov sp, r7
8002f32: bd80 pop {r7, pc}
08002f34 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002f34: b580 push {r7, lr}
8002f36: b086 sub sp, #24
8002f38: af00 add r7, sp, #0
8002f3a: 60f8 str r0, [r7, #12]
8002f3c: 60b9 str r1, [r7, #8]
8002f3e: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002f40: 2300 movs r3, #0
8002f42: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8002f44: 68fb ldr r3, [r7, #12]
8002f46: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8002f4a: 2b01 cmp r3, #1
8002f4c: d101 bne.n 8002f52 <HAL_TIM_PWM_ConfigChannel+0x1e>
8002f4e: 2302 movs r3, #2
8002f50: e0ae b.n 80030b0 <HAL_TIM_PWM_ConfigChannel+0x17c>
8002f52: 68fb ldr r3, [r7, #12]
8002f54: 2201 movs r2, #1
8002f56: f883 2038 strb.w r2, [r3, #56] @ 0x38
switch (Channel)
8002f5a: 687b ldr r3, [r7, #4]
8002f5c: 2b0c cmp r3, #12
8002f5e: f200 809f bhi.w 80030a0 <HAL_TIM_PWM_ConfigChannel+0x16c>
8002f62: a201 add r2, pc, #4 @ (adr r2, 8002f68 <HAL_TIM_PWM_ConfigChannel+0x34>)
8002f64: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8002f68: 08002f9d .word 0x08002f9d
8002f6c: 080030a1 .word 0x080030a1
8002f70: 080030a1 .word 0x080030a1
8002f74: 080030a1 .word 0x080030a1
8002f78: 08002fdd .word 0x08002fdd
8002f7c: 080030a1 .word 0x080030a1
8002f80: 080030a1 .word 0x080030a1
8002f84: 080030a1 .word 0x080030a1
8002f88: 0800301f .word 0x0800301f
8002f8c: 080030a1 .word 0x080030a1
8002f90: 080030a1 .word 0x080030a1
8002f94: 080030a1 .word 0x080030a1
8002f98: 0800305f .word 0x0800305f
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8002f9c: 68fb ldr r3, [r7, #12]
8002f9e: 681b ldr r3, [r3, #0]
8002fa0: 68b9 ldr r1, [r7, #8]
8002fa2: 4618 mov r0, r3
8002fa4: f000 f9ea bl 800337c <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8002fa8: 68fb ldr r3, [r7, #12]
8002faa: 681b ldr r3, [r3, #0]
8002fac: 699a ldr r2, [r3, #24]
8002fae: 68fb ldr r3, [r7, #12]
8002fb0: 681b ldr r3, [r3, #0]
8002fb2: f042 0208 orr.w r2, r2, #8
8002fb6: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8002fb8: 68fb ldr r3, [r7, #12]
8002fba: 681b ldr r3, [r3, #0]
8002fbc: 699a ldr r2, [r3, #24]
8002fbe: 68fb ldr r3, [r7, #12]
8002fc0: 681b ldr r3, [r3, #0]
8002fc2: f022 0204 bic.w r2, r2, #4
8002fc6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8002fc8: 68fb ldr r3, [r7, #12]
8002fca: 681b ldr r3, [r3, #0]
8002fcc: 6999 ldr r1, [r3, #24]
8002fce: 68bb ldr r3, [r7, #8]
8002fd0: 68da ldr r2, [r3, #12]
8002fd2: 68fb ldr r3, [r7, #12]
8002fd4: 681b ldr r3, [r3, #0]
8002fd6: 430a orrs r2, r1
8002fd8: 619a str r2, [r3, #24]
break;
8002fda: e064 b.n 80030a6 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8002fdc: 68fb ldr r3, [r7, #12]
8002fde: 681b ldr r3, [r3, #0]
8002fe0: 68b9 ldr r1, [r7, #8]
8002fe2: 4618 mov r0, r3
8002fe4: f000 fa06 bl 80033f4 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8002fe8: 68fb ldr r3, [r7, #12]
8002fea: 681b ldr r3, [r3, #0]
8002fec: 699a ldr r2, [r3, #24]
8002fee: 68fb ldr r3, [r7, #12]
8002ff0: 681b ldr r3, [r3, #0]
8002ff2: f442 6200 orr.w r2, r2, #2048 @ 0x800
8002ff6: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8002ff8: 68fb ldr r3, [r7, #12]
8002ffa: 681b ldr r3, [r3, #0]
8002ffc: 699a ldr r2, [r3, #24]
8002ffe: 68fb ldr r3, [r7, #12]
8003000: 681b ldr r3, [r3, #0]
8003002: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003006: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8003008: 68fb ldr r3, [r7, #12]
800300a: 681b ldr r3, [r3, #0]
800300c: 6999 ldr r1, [r3, #24]
800300e: 68bb ldr r3, [r7, #8]
8003010: 68db ldr r3, [r3, #12]
8003012: 021a lsls r2, r3, #8
8003014: 68fb ldr r3, [r7, #12]
8003016: 681b ldr r3, [r3, #0]
8003018: 430a orrs r2, r1
800301a: 619a str r2, [r3, #24]
break;
800301c: e043 b.n 80030a6 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800301e: 68fb ldr r3, [r7, #12]
8003020: 681b ldr r3, [r3, #0]
8003022: 68b9 ldr r1, [r7, #8]
8003024: 4618 mov r0, r3
8003026: f000 fa23 bl 8003470 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800302a: 68fb ldr r3, [r7, #12]
800302c: 681b ldr r3, [r3, #0]
800302e: 69da ldr r2, [r3, #28]
8003030: 68fb ldr r3, [r7, #12]
8003032: 681b ldr r3, [r3, #0]
8003034: f042 0208 orr.w r2, r2, #8
8003038: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800303a: 68fb ldr r3, [r7, #12]
800303c: 681b ldr r3, [r3, #0]
800303e: 69da ldr r2, [r3, #28]
8003040: 68fb ldr r3, [r7, #12]
8003042: 681b ldr r3, [r3, #0]
8003044: f022 0204 bic.w r2, r2, #4
8003048: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800304a: 68fb ldr r3, [r7, #12]
800304c: 681b ldr r3, [r3, #0]
800304e: 69d9 ldr r1, [r3, #28]
8003050: 68bb ldr r3, [r7, #8]
8003052: 68da ldr r2, [r3, #12]
8003054: 68fb ldr r3, [r7, #12]
8003056: 681b ldr r3, [r3, #0]
8003058: 430a orrs r2, r1
800305a: 61da str r2, [r3, #28]
break;
800305c: e023 b.n 80030a6 <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800305e: 68fb ldr r3, [r7, #12]
8003060: 681b ldr r3, [r3, #0]
8003062: 68b9 ldr r1, [r7, #8]
8003064: 4618 mov r0, r3
8003066: f000 fa40 bl 80034ea <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800306a: 68fb ldr r3, [r7, #12]
800306c: 681b ldr r3, [r3, #0]
800306e: 69da ldr r2, [r3, #28]
8003070: 68fb ldr r3, [r7, #12]
8003072: 681b ldr r3, [r3, #0]
8003074: f442 6200 orr.w r2, r2, #2048 @ 0x800
8003078: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800307a: 68fb ldr r3, [r7, #12]
800307c: 681b ldr r3, [r3, #0]
800307e: 69da ldr r2, [r3, #28]
8003080: 68fb ldr r3, [r7, #12]
8003082: 681b ldr r3, [r3, #0]
8003084: f422 6280 bic.w r2, r2, #1024 @ 0x400
8003088: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800308a: 68fb ldr r3, [r7, #12]
800308c: 681b ldr r3, [r3, #0]
800308e: 69d9 ldr r1, [r3, #28]
8003090: 68bb ldr r3, [r7, #8]
8003092: 68db ldr r3, [r3, #12]
8003094: 021a lsls r2, r3, #8
8003096: 68fb ldr r3, [r7, #12]
8003098: 681b ldr r3, [r3, #0]
800309a: 430a orrs r2, r1
800309c: 61da str r2, [r3, #28]
break;
800309e: e002 b.n 80030a6 <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
80030a0: 2301 movs r3, #1
80030a2: 75fb strb r3, [r7, #23]
break;
80030a4: bf00 nop
}
__HAL_UNLOCK(htim);
80030a6: 68fb ldr r3, [r7, #12]
80030a8: 2200 movs r2, #0
80030aa: f883 2038 strb.w r2, [r3, #56] @ 0x38
return status;
80030ae: 7dfb ldrb r3, [r7, #23]
}
80030b0: 4618 mov r0, r3
80030b2: 3718 adds r7, #24
80030b4: 46bd mov sp, r7
80030b6: bd80 pop {r7, pc}
080030b8 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
80030b8: b580 push {r7, lr}
80030ba: b084 sub sp, #16
80030bc: af00 add r7, sp, #0
80030be: 6078 str r0, [r7, #4]
80030c0: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
80030c2: 2300 movs r3, #0
80030c4: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
80030c6: 687b ldr r3, [r7, #4]
80030c8: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
80030cc: 2b01 cmp r3, #1
80030ce: d101 bne.n 80030d4 <HAL_TIM_ConfigClockSource+0x1c>
80030d0: 2302 movs r3, #2
80030d2: e0b4 b.n 800323e <HAL_TIM_ConfigClockSource+0x186>
80030d4: 687b ldr r3, [r7, #4]
80030d6: 2201 movs r2, #1
80030d8: f883 2038 strb.w r2, [r3, #56] @ 0x38
htim->State = HAL_TIM_STATE_BUSY;
80030dc: 687b ldr r3, [r7, #4]
80030de: 2202 movs r2, #2
80030e0: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80030e4: 687b ldr r3, [r7, #4]
80030e6: 681b ldr r3, [r3, #0]
80030e8: 689b ldr r3, [r3, #8]
80030ea: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
80030ec: 68bb ldr r3, [r7, #8]
80030ee: f023 0377 bic.w r3, r3, #119 @ 0x77
80030f2: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80030f4: 68bb ldr r3, [r7, #8]
80030f6: f423 437f bic.w r3, r3, #65280 @ 0xff00
80030fa: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
80030fc: 687b ldr r3, [r7, #4]
80030fe: 681b ldr r3, [r3, #0]
8003100: 68ba ldr r2, [r7, #8]
8003102: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8003104: 683b ldr r3, [r7, #0]
8003106: 681b ldr r3, [r3, #0]
8003108: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800310c: d03e beq.n 800318c <HAL_TIM_ConfigClockSource+0xd4>
800310e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003112: f200 8087 bhi.w 8003224 <HAL_TIM_ConfigClockSource+0x16c>
8003116: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800311a: f000 8086 beq.w 800322a <HAL_TIM_ConfigClockSource+0x172>
800311e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8003122: d87f bhi.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
8003124: 2b70 cmp r3, #112 @ 0x70
8003126: d01a beq.n 800315e <HAL_TIM_ConfigClockSource+0xa6>
8003128: 2b70 cmp r3, #112 @ 0x70
800312a: d87b bhi.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
800312c: 2b60 cmp r3, #96 @ 0x60
800312e: d050 beq.n 80031d2 <HAL_TIM_ConfigClockSource+0x11a>
8003130: 2b60 cmp r3, #96 @ 0x60
8003132: d877 bhi.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
8003134: 2b50 cmp r3, #80 @ 0x50
8003136: d03c beq.n 80031b2 <HAL_TIM_ConfigClockSource+0xfa>
8003138: 2b50 cmp r3, #80 @ 0x50
800313a: d873 bhi.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
800313c: 2b40 cmp r3, #64 @ 0x40
800313e: d058 beq.n 80031f2 <HAL_TIM_ConfigClockSource+0x13a>
8003140: 2b40 cmp r3, #64 @ 0x40
8003142: d86f bhi.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
8003144: 2b30 cmp r3, #48 @ 0x30
8003146: d064 beq.n 8003212 <HAL_TIM_ConfigClockSource+0x15a>
8003148: 2b30 cmp r3, #48 @ 0x30
800314a: d86b bhi.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
800314c: 2b20 cmp r3, #32
800314e: d060 beq.n 8003212 <HAL_TIM_ConfigClockSource+0x15a>
8003150: 2b20 cmp r3, #32
8003152: d867 bhi.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
8003154: 2b00 cmp r3, #0
8003156: d05c beq.n 8003212 <HAL_TIM_ConfigClockSource+0x15a>
8003158: 2b10 cmp r3, #16
800315a: d05a beq.n 8003212 <HAL_TIM_ConfigClockSource+0x15a>
800315c: e062 b.n 8003224 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
800315e: 687b ldr r3, [r7, #4]
8003160: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8003162: 683b ldr r3, [r7, #0]
8003164: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8003166: 683b ldr r3, [r7, #0]
8003168: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800316a: 683b ldr r3, [r7, #0]
800316c: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
800316e: f000 fa71 bl 8003654 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8003172: 687b ldr r3, [r7, #4]
8003174: 681b ldr r3, [r3, #0]
8003176: 689b ldr r3, [r3, #8]
8003178: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800317a: 68bb ldr r3, [r7, #8]
800317c: f043 0377 orr.w r3, r3, #119 @ 0x77
8003180: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8003182: 687b ldr r3, [r7, #4]
8003184: 681b ldr r3, [r3, #0]
8003186: 68ba ldr r2, [r7, #8]
8003188: 609a str r2, [r3, #8]
break;
800318a: e04f b.n 800322c <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
800318c: 687b ldr r3, [r7, #4]
800318e: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8003190: 683b ldr r3, [r7, #0]
8003192: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8003194: 683b ldr r3, [r7, #0]
8003196: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8003198: 683b ldr r3, [r7, #0]
800319a: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
800319c: f000 fa5a bl 8003654 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
80031a0: 687b ldr r3, [r7, #4]
80031a2: 681b ldr r3, [r3, #0]
80031a4: 689a ldr r2, [r3, #8]
80031a6: 687b ldr r3, [r7, #4]
80031a8: 681b ldr r3, [r3, #0]
80031aa: f442 4280 orr.w r2, r2, #16384 @ 0x4000
80031ae: 609a str r2, [r3, #8]
break;
80031b0: e03c b.n 800322c <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80031b2: 687b ldr r3, [r7, #4]
80031b4: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80031b6: 683b ldr r3, [r7, #0]
80031b8: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80031ba: 683b ldr r3, [r7, #0]
80031bc: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80031be: 461a mov r2, r3
80031c0: f000 f9d1 bl 8003566 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80031c4: 687b ldr r3, [r7, #4]
80031c6: 681b ldr r3, [r3, #0]
80031c8: 2150 movs r1, #80 @ 0x50
80031ca: 4618 mov r0, r3
80031cc: f000 fa28 bl 8003620 <TIM_ITRx_SetConfig>
break;
80031d0: e02c b.n 800322c <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
80031d2: 687b ldr r3, [r7, #4]
80031d4: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80031d6: 683b ldr r3, [r7, #0]
80031d8: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80031da: 683b ldr r3, [r7, #0]
80031dc: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
80031de: 461a mov r2, r3
80031e0: f000 f9ef bl 80035c2 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80031e4: 687b ldr r3, [r7, #4]
80031e6: 681b ldr r3, [r3, #0]
80031e8: 2160 movs r1, #96 @ 0x60
80031ea: 4618 mov r0, r3
80031ec: f000 fa18 bl 8003620 <TIM_ITRx_SetConfig>
break;
80031f0: e01c b.n 800322c <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80031f2: 687b ldr r3, [r7, #4]
80031f4: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80031f6: 683b ldr r3, [r7, #0]
80031f8: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80031fa: 683b ldr r3, [r7, #0]
80031fc: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80031fe: 461a mov r2, r3
8003200: f000 f9b1 bl 8003566 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8003204: 687b ldr r3, [r7, #4]
8003206: 681b ldr r3, [r3, #0]
8003208: 2140 movs r1, #64 @ 0x40
800320a: 4618 mov r0, r3
800320c: f000 fa08 bl 8003620 <TIM_ITRx_SetConfig>
break;
8003210: e00c b.n 800322c <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8003212: 687b ldr r3, [r7, #4]
8003214: 681a ldr r2, [r3, #0]
8003216: 683b ldr r3, [r7, #0]
8003218: 681b ldr r3, [r3, #0]
800321a: 4619 mov r1, r3
800321c: 4610 mov r0, r2
800321e: f000 f9ff bl 8003620 <TIM_ITRx_SetConfig>
break;
8003222: e003 b.n 800322c <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
8003224: 2301 movs r3, #1
8003226: 73fb strb r3, [r7, #15]
break;
8003228: e000 b.n 800322c <HAL_TIM_ConfigClockSource+0x174>
break;
800322a: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800322c: 687b ldr r3, [r7, #4]
800322e: 2201 movs r2, #1
8003230: f883 2039 strb.w r2, [r3, #57] @ 0x39
__HAL_UNLOCK(htim);
8003234: 687b ldr r3, [r7, #4]
8003236: 2200 movs r2, #0
8003238: f883 2038 strb.w r2, [r3, #56] @ 0x38
return status;
800323c: 7bfb ldrb r3, [r7, #15]
}
800323e: 4618 mov r0, r3
8003240: 3710 adds r7, #16
8003242: 46bd mov sp, r7
8003244: bd80 pop {r7, pc}
08003246 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8003246: b480 push {r7}
8003248: b083 sub sp, #12
800324a: af00 add r7, sp, #0
800324c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800324e: bf00 nop
8003250: 370c adds r7, #12
8003252: 46bd mov sp, r7
8003254: bc80 pop {r7}
8003256: 4770 bx lr
08003258 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8003258: b480 push {r7}
800325a: b083 sub sp, #12
800325c: af00 add r7, sp, #0
800325e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8003260: bf00 nop
8003262: 370c adds r7, #12
8003264: 46bd mov sp, r7
8003266: bc80 pop {r7}
8003268: 4770 bx lr
0800326a <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800326a: b480 push {r7}
800326c: b083 sub sp, #12
800326e: af00 add r7, sp, #0
8003270: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8003272: bf00 nop
8003274: 370c adds r7, #12
8003276: 46bd mov sp, r7
8003278: bc80 pop {r7}
800327a: 4770 bx lr
0800327c <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800327c: b480 push {r7}
800327e: b083 sub sp, #12
8003280: af00 add r7, sp, #0
8003282: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8003284: bf00 nop
8003286: 370c adds r7, #12
8003288: 46bd mov sp, r7
800328a: bc80 pop {r7}
800328c: 4770 bx lr
...
08003290 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8003290: b480 push {r7}
8003292: b085 sub sp, #20
8003294: af00 add r7, sp, #0
8003296: 6078 str r0, [r7, #4]
8003298: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800329a: 687b ldr r3, [r7, #4]
800329c: 681b ldr r3, [r3, #0]
800329e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80032a0: 687b ldr r3, [r7, #4]
80032a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80032a6: d00f beq.n 80032c8 <TIM_Base_SetConfig+0x38>
80032a8: 687b ldr r3, [r7, #4]
80032aa: 4a2e ldr r2, [pc, #184] @ (8003364 <TIM_Base_SetConfig+0xd4>)
80032ac: 4293 cmp r3, r2
80032ae: d00b beq.n 80032c8 <TIM_Base_SetConfig+0x38>
80032b0: 687b ldr r3, [r7, #4]
80032b2: 4a2d ldr r2, [pc, #180] @ (8003368 <TIM_Base_SetConfig+0xd8>)
80032b4: 4293 cmp r3, r2
80032b6: d007 beq.n 80032c8 <TIM_Base_SetConfig+0x38>
80032b8: 687b ldr r3, [r7, #4]
80032ba: 4a2c ldr r2, [pc, #176] @ (800336c <TIM_Base_SetConfig+0xdc>)
80032bc: 4293 cmp r3, r2
80032be: d003 beq.n 80032c8 <TIM_Base_SetConfig+0x38>
80032c0: 687b ldr r3, [r7, #4]
80032c2: 4a2b ldr r2, [pc, #172] @ (8003370 <TIM_Base_SetConfig+0xe0>)
80032c4: 4293 cmp r3, r2
80032c6: d108 bne.n 80032da <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80032c8: 68fb ldr r3, [r7, #12]
80032ca: f023 0370 bic.w r3, r3, #112 @ 0x70
80032ce: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80032d0: 683b ldr r3, [r7, #0]
80032d2: 685b ldr r3, [r3, #4]
80032d4: 68fa ldr r2, [r7, #12]
80032d6: 4313 orrs r3, r2
80032d8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80032da: 687b ldr r3, [r7, #4]
80032dc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80032e0: d017 beq.n 8003312 <TIM_Base_SetConfig+0x82>
80032e2: 687b ldr r3, [r7, #4]
80032e4: 4a1f ldr r2, [pc, #124] @ (8003364 <TIM_Base_SetConfig+0xd4>)
80032e6: 4293 cmp r3, r2
80032e8: d013 beq.n 8003312 <TIM_Base_SetConfig+0x82>
80032ea: 687b ldr r3, [r7, #4]
80032ec: 4a1e ldr r2, [pc, #120] @ (8003368 <TIM_Base_SetConfig+0xd8>)
80032ee: 4293 cmp r3, r2
80032f0: d00f beq.n 8003312 <TIM_Base_SetConfig+0x82>
80032f2: 687b ldr r3, [r7, #4]
80032f4: 4a1d ldr r2, [pc, #116] @ (800336c <TIM_Base_SetConfig+0xdc>)
80032f6: 4293 cmp r3, r2
80032f8: d00b beq.n 8003312 <TIM_Base_SetConfig+0x82>
80032fa: 687b ldr r3, [r7, #4]
80032fc: 4a1c ldr r2, [pc, #112] @ (8003370 <TIM_Base_SetConfig+0xe0>)
80032fe: 4293 cmp r3, r2
8003300: d007 beq.n 8003312 <TIM_Base_SetConfig+0x82>
8003302: 687b ldr r3, [r7, #4]
8003304: 4a1b ldr r2, [pc, #108] @ (8003374 <TIM_Base_SetConfig+0xe4>)
8003306: 4293 cmp r3, r2
8003308: d003 beq.n 8003312 <TIM_Base_SetConfig+0x82>
800330a: 687b ldr r3, [r7, #4]
800330c: 4a1a ldr r2, [pc, #104] @ (8003378 <TIM_Base_SetConfig+0xe8>)
800330e: 4293 cmp r3, r2
8003310: d108 bne.n 8003324 <TIM_Base_SetConfig+0x94>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8003312: 68fb ldr r3, [r7, #12]
8003314: f423 7340 bic.w r3, r3, #768 @ 0x300
8003318: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800331a: 683b ldr r3, [r7, #0]
800331c: 68db ldr r3, [r3, #12]
800331e: 68fa ldr r2, [r7, #12]
8003320: 4313 orrs r3, r2
8003322: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003324: 68fb ldr r3, [r7, #12]
8003326: f023 0280 bic.w r2, r3, #128 @ 0x80
800332a: 683b ldr r3, [r7, #0]
800332c: 691b ldr r3, [r3, #16]
800332e: 4313 orrs r3, r2
8003330: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8003332: 683b ldr r3, [r7, #0]
8003334: 689a ldr r2, [r3, #8]
8003336: 687b ldr r3, [r7, #4]
8003338: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
800333a: 683b ldr r3, [r7, #0]
800333c: 681a ldr r2, [r3, #0]
800333e: 687b ldr r3, [r7, #4]
8003340: 629a str r2, [r3, #40] @ 0x28
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
8003342: 687b ldr r3, [r7, #4]
8003344: 681b ldr r3, [r3, #0]
8003346: f043 0204 orr.w r2, r3, #4
800334a: 687b ldr r3, [r7, #4]
800334c: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800334e: 687b ldr r3, [r7, #4]
8003350: 2201 movs r2, #1
8003352: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
8003354: 687b ldr r3, [r7, #4]
8003356: 68fa ldr r2, [r7, #12]
8003358: 601a str r2, [r3, #0]
}
800335a: bf00 nop
800335c: 3714 adds r7, #20
800335e: 46bd mov sp, r7
8003360: bc80 pop {r7}
8003362: 4770 bx lr
8003364: 40000400 .word 0x40000400
8003368: 40000800 .word 0x40000800
800336c: 40000c00 .word 0x40000c00
8003370: 40010800 .word 0x40010800
8003374: 40010c00 .word 0x40010c00
8003378: 40011000 .word 0x40011000
0800337c <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800337c: b480 push {r7}
800337e: b087 sub sp, #28
8003380: af00 add r7, sp, #0
8003382: 6078 str r0, [r7, #4]
8003384: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003386: 687b ldr r3, [r7, #4]
8003388: 6a1b ldr r3, [r3, #32]
800338a: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
800338c: 687b ldr r3, [r7, #4]
800338e: 6a1b ldr r3, [r3, #32]
8003390: f023 0201 bic.w r2, r3, #1
8003394: 687b ldr r3, [r7, #4]
8003396: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003398: 687b ldr r3, [r7, #4]
800339a: 685b ldr r3, [r3, #4]
800339c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800339e: 687b ldr r3, [r7, #4]
80033a0: 699b ldr r3, [r3, #24]
80033a2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
80033a4: 68fb ldr r3, [r7, #12]
80033a6: f023 0370 bic.w r3, r3, #112 @ 0x70
80033aa: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
80033ac: 68fb ldr r3, [r7, #12]
80033ae: f023 0303 bic.w r3, r3, #3
80033b2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80033b4: 683b ldr r3, [r7, #0]
80033b6: 681b ldr r3, [r3, #0]
80033b8: 68fa ldr r2, [r7, #12]
80033ba: 4313 orrs r3, r2
80033bc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
80033be: 697b ldr r3, [r7, #20]
80033c0: f023 0302 bic.w r3, r3, #2
80033c4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
80033c6: 683b ldr r3, [r7, #0]
80033c8: 689b ldr r3, [r3, #8]
80033ca: 697a ldr r2, [r7, #20]
80033cc: 4313 orrs r3, r2
80033ce: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80033d0: 687b ldr r3, [r7, #4]
80033d2: 693a ldr r2, [r7, #16]
80033d4: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80033d6: 687b ldr r3, [r7, #4]
80033d8: 68fa ldr r2, [r7, #12]
80033da: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80033dc: 683b ldr r3, [r7, #0]
80033de: 685a ldr r2, [r3, #4]
80033e0: 687b ldr r3, [r7, #4]
80033e2: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80033e4: 687b ldr r3, [r7, #4]
80033e6: 697a ldr r2, [r7, #20]
80033e8: 621a str r2, [r3, #32]
}
80033ea: bf00 nop
80033ec: 371c adds r7, #28
80033ee: 46bd mov sp, r7
80033f0: bc80 pop {r7}
80033f2: 4770 bx lr
080033f4 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80033f4: b480 push {r7}
80033f6: b087 sub sp, #28
80033f8: af00 add r7, sp, #0
80033fa: 6078 str r0, [r7, #4]
80033fc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80033fe: 687b ldr r3, [r7, #4]
8003400: 6a1b ldr r3, [r3, #32]
8003402: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8003404: 687b ldr r3, [r7, #4]
8003406: 6a1b ldr r3, [r3, #32]
8003408: f023 0210 bic.w r2, r3, #16
800340c: 687b ldr r3, [r7, #4]
800340e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003410: 687b ldr r3, [r7, #4]
8003412: 685b ldr r3, [r3, #4]
8003414: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8003416: 687b ldr r3, [r7, #4]
8003418: 699b ldr r3, [r3, #24]
800341a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
800341c: 68fb ldr r3, [r7, #12]
800341e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8003422: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8003424: 68fb ldr r3, [r7, #12]
8003426: f423 7340 bic.w r3, r3, #768 @ 0x300
800342a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800342c: 683b ldr r3, [r7, #0]
800342e: 681b ldr r3, [r3, #0]
8003430: 021b lsls r3, r3, #8
8003432: 68fa ldr r2, [r7, #12]
8003434: 4313 orrs r3, r2
8003436: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8003438: 697b ldr r3, [r7, #20]
800343a: f023 0320 bic.w r3, r3, #32
800343e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8003440: 683b ldr r3, [r7, #0]
8003442: 689b ldr r3, [r3, #8]
8003444: 011b lsls r3, r3, #4
8003446: 697a ldr r2, [r7, #20]
8003448: 4313 orrs r3, r2
800344a: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800344c: 687b ldr r3, [r7, #4]
800344e: 693a ldr r2, [r7, #16]
8003450: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8003452: 687b ldr r3, [r7, #4]
8003454: 68fa ldr r2, [r7, #12]
8003456: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8003458: 683b ldr r3, [r7, #0]
800345a: 685a ldr r2, [r3, #4]
800345c: 687b ldr r3, [r7, #4]
800345e: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003460: 687b ldr r3, [r7, #4]
8003462: 697a ldr r2, [r7, #20]
8003464: 621a str r2, [r3, #32]
}
8003466: bf00 nop
8003468: 371c adds r7, #28
800346a: 46bd mov sp, r7
800346c: bc80 pop {r7}
800346e: 4770 bx lr
08003470 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8003470: b480 push {r7}
8003472: b087 sub sp, #28
8003474: af00 add r7, sp, #0
8003476: 6078 str r0, [r7, #4]
8003478: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800347a: 687b ldr r3, [r7, #4]
800347c: 6a1b ldr r3, [r3, #32]
800347e: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8003480: 687b ldr r3, [r7, #4]
8003482: 6a1b ldr r3, [r3, #32]
8003484: f423 7280 bic.w r2, r3, #256 @ 0x100
8003488: 687b ldr r3, [r7, #4]
800348a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800348c: 687b ldr r3, [r7, #4]
800348e: 685b ldr r3, [r3, #4]
8003490: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8003492: 687b ldr r3, [r7, #4]
8003494: 69db ldr r3, [r3, #28]
8003496: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8003498: 68fb ldr r3, [r7, #12]
800349a: f023 0370 bic.w r3, r3, #112 @ 0x70
800349e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80034a0: 68fb ldr r3, [r7, #12]
80034a2: f023 0303 bic.w r3, r3, #3
80034a6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80034a8: 683b ldr r3, [r7, #0]
80034aa: 681b ldr r3, [r3, #0]
80034ac: 68fa ldr r2, [r7, #12]
80034ae: 4313 orrs r3, r2
80034b0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80034b2: 697b ldr r3, [r7, #20]
80034b4: f423 7300 bic.w r3, r3, #512 @ 0x200
80034b8: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
80034ba: 683b ldr r3, [r7, #0]
80034bc: 689b ldr r3, [r3, #8]
80034be: 021b lsls r3, r3, #8
80034c0: 697a ldr r2, [r7, #20]
80034c2: 4313 orrs r3, r2
80034c4: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80034c6: 687b ldr r3, [r7, #4]
80034c8: 693a ldr r2, [r7, #16]
80034ca: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80034cc: 687b ldr r3, [r7, #4]
80034ce: 68fa ldr r2, [r7, #12]
80034d0: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
80034d2: 683b ldr r3, [r7, #0]
80034d4: 685a ldr r2, [r3, #4]
80034d6: 687b ldr r3, [r7, #4]
80034d8: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80034da: 687b ldr r3, [r7, #4]
80034dc: 697a ldr r2, [r7, #20]
80034de: 621a str r2, [r3, #32]
}
80034e0: bf00 nop
80034e2: 371c adds r7, #28
80034e4: 46bd mov sp, r7
80034e6: bc80 pop {r7}
80034e8: 4770 bx lr
080034ea <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80034ea: b480 push {r7}
80034ec: b087 sub sp, #28
80034ee: af00 add r7, sp, #0
80034f0: 6078 str r0, [r7, #4]
80034f2: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80034f4: 687b ldr r3, [r7, #4]
80034f6: 6a1b ldr r3, [r3, #32]
80034f8: 617b str r3, [r7, #20]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
80034fa: 687b ldr r3, [r7, #4]
80034fc: 6a1b ldr r3, [r3, #32]
80034fe: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8003502: 687b ldr r3, [r7, #4]
8003504: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003506: 687b ldr r3, [r7, #4]
8003508: 685b ldr r3, [r3, #4]
800350a: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800350c: 687b ldr r3, [r7, #4]
800350e: 69db ldr r3, [r3, #28]
8003510: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8003512: 68fb ldr r3, [r7, #12]
8003514: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8003518: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
800351a: 68fb ldr r3, [r7, #12]
800351c: f423 7340 bic.w r3, r3, #768 @ 0x300
8003520: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8003522: 683b ldr r3, [r7, #0]
8003524: 681b ldr r3, [r3, #0]
8003526: 021b lsls r3, r3, #8
8003528: 68fa ldr r2, [r7, #12]
800352a: 4313 orrs r3, r2
800352c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800352e: 697b ldr r3, [r7, #20]
8003530: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8003534: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8003536: 683b ldr r3, [r7, #0]
8003538: 689b ldr r3, [r3, #8]
800353a: 031b lsls r3, r3, #12
800353c: 697a ldr r2, [r7, #20]
800353e: 4313 orrs r3, r2
8003540: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003542: 687b ldr r3, [r7, #4]
8003544: 693a ldr r2, [r7, #16]
8003546: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8003548: 687b ldr r3, [r7, #4]
800354a: 68fa ldr r2, [r7, #12]
800354c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
800354e: 683b ldr r3, [r7, #0]
8003550: 685a ldr r2, [r3, #4]
8003552: 687b ldr r3, [r7, #4]
8003554: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003556: 687b ldr r3, [r7, #4]
8003558: 697a ldr r2, [r7, #20]
800355a: 621a str r2, [r3, #32]
}
800355c: bf00 nop
800355e: 371c adds r7, #28
8003560: 46bd mov sp, r7
8003562: bc80 pop {r7}
8003564: 4770 bx lr
08003566 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003566: b480 push {r7}
8003568: b087 sub sp, #28
800356a: af00 add r7, sp, #0
800356c: 60f8 str r0, [r7, #12]
800356e: 60b9 str r1, [r7, #8]
8003570: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8003572: 68fb ldr r3, [r7, #12]
8003574: 6a1b ldr r3, [r3, #32]
8003576: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8003578: 68fb ldr r3, [r7, #12]
800357a: 6a1b ldr r3, [r3, #32]
800357c: f023 0201 bic.w r2, r3, #1
8003580: 68fb ldr r3, [r7, #12]
8003582: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003584: 68fb ldr r3, [r7, #12]
8003586: 699b ldr r3, [r3, #24]
8003588: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800358a: 693b ldr r3, [r7, #16]
800358c: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8003590: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8003592: 687b ldr r3, [r7, #4]
8003594: 011b lsls r3, r3, #4
8003596: 693a ldr r2, [r7, #16]
8003598: 4313 orrs r3, r2
800359a: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800359c: 697b ldr r3, [r7, #20]
800359e: f023 030a bic.w r3, r3, #10
80035a2: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
80035a4: 697a ldr r2, [r7, #20]
80035a6: 68bb ldr r3, [r7, #8]
80035a8: 4313 orrs r3, r2
80035aa: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
80035ac: 68fb ldr r3, [r7, #12]
80035ae: 693a ldr r2, [r7, #16]
80035b0: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80035b2: 68fb ldr r3, [r7, #12]
80035b4: 697a ldr r2, [r7, #20]
80035b6: 621a str r2, [r3, #32]
}
80035b8: bf00 nop
80035ba: 371c adds r7, #28
80035bc: 46bd mov sp, r7
80035be: bc80 pop {r7}
80035c0: 4770 bx lr
080035c2 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80035c2: b480 push {r7}
80035c4: b087 sub sp, #28
80035c6: af00 add r7, sp, #0
80035c8: 60f8 str r0, [r7, #12]
80035ca: 60b9 str r1, [r7, #8]
80035cc: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
80035ce: 68fb ldr r3, [r7, #12]
80035d0: 6a1b ldr r3, [r3, #32]
80035d2: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
80035d4: 68fb ldr r3, [r7, #12]
80035d6: 6a1b ldr r3, [r3, #32]
80035d8: f023 0210 bic.w r2, r3, #16
80035dc: 68fb ldr r3, [r7, #12]
80035de: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80035e0: 68fb ldr r3, [r7, #12]
80035e2: 699b ldr r3, [r3, #24]
80035e4: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80035e6: 693b ldr r3, [r7, #16]
80035e8: f423 4370 bic.w r3, r3, #61440 @ 0xf000
80035ec: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
80035ee: 687b ldr r3, [r7, #4]
80035f0: 031b lsls r3, r3, #12
80035f2: 693a ldr r2, [r7, #16]
80035f4: 4313 orrs r3, r2
80035f6: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80035f8: 697b ldr r3, [r7, #20]
80035fa: f023 03a0 bic.w r3, r3, #160 @ 0xa0
80035fe: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8003600: 68bb ldr r3, [r7, #8]
8003602: 011b lsls r3, r3, #4
8003604: 697a ldr r2, [r7, #20]
8003606: 4313 orrs r3, r2
8003608: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800360a: 68fb ldr r3, [r7, #12]
800360c: 693a ldr r2, [r7, #16]
800360e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8003610: 68fb ldr r3, [r7, #12]
8003612: 697a ldr r2, [r7, #20]
8003614: 621a str r2, [r3, #32]
}
8003616: bf00 nop
8003618: 371c adds r7, #28
800361a: 46bd mov sp, r7
800361c: bc80 pop {r7}
800361e: 4770 bx lr
08003620 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8003620: b480 push {r7}
8003622: b085 sub sp, #20
8003624: af00 add r7, sp, #0
8003626: 6078 str r0, [r7, #4]
8003628: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
800362a: 687b ldr r3, [r7, #4]
800362c: 689b ldr r3, [r3, #8]
800362e: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8003630: 68fb ldr r3, [r7, #12]
8003632: f023 0370 bic.w r3, r3, #112 @ 0x70
8003636: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8003638: 683a ldr r2, [r7, #0]
800363a: 68fb ldr r3, [r7, #12]
800363c: 4313 orrs r3, r2
800363e: f043 0307 orr.w r3, r3, #7
8003642: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8003644: 687b ldr r3, [r7, #4]
8003646: 68fa ldr r2, [r7, #12]
8003648: 609a str r2, [r3, #8]
}
800364a: bf00 nop
800364c: 3714 adds r7, #20
800364e: 46bd mov sp, r7
8003650: bc80 pop {r7}
8003652: 4770 bx lr
08003654 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8003654: b480 push {r7}
8003656: b087 sub sp, #28
8003658: af00 add r7, sp, #0
800365a: 60f8 str r0, [r7, #12]
800365c: 60b9 str r1, [r7, #8]
800365e: 607a str r2, [r7, #4]
8003660: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8003662: 68fb ldr r3, [r7, #12]
8003664: 689b ldr r3, [r3, #8]
8003666: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8003668: 697b ldr r3, [r7, #20]
800366a: f423 437f bic.w r3, r3, #65280 @ 0xff00
800366e: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8003670: 683b ldr r3, [r7, #0]
8003672: 021a lsls r2, r3, #8
8003674: 687b ldr r3, [r7, #4]
8003676: 431a orrs r2, r3
8003678: 68bb ldr r3, [r7, #8]
800367a: 4313 orrs r3, r2
800367c: 697a ldr r2, [r7, #20]
800367e: 4313 orrs r3, r2
8003680: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8003682: 68fb ldr r3, [r7, #12]
8003684: 697a ldr r2, [r7, #20]
8003686: 609a str r2, [r3, #8]
}
8003688: bf00 nop
800368a: 371c adds r7, #28
800368c: 46bd mov sp, r7
800368e: bc80 pop {r7}
8003690: 4770 bx lr
08003692 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8003692: b480 push {r7}
8003694: b087 sub sp, #28
8003696: af00 add r7, sp, #0
8003698: 60f8 str r0, [r7, #12]
800369a: 60b9 str r1, [r7, #8]
800369c: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
800369e: 68bb ldr r3, [r7, #8]
80036a0: f003 031f and.w r3, r3, #31
80036a4: 2201 movs r2, #1
80036a6: fa02 f303 lsl.w r3, r2, r3
80036aa: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
80036ac: 68fb ldr r3, [r7, #12]
80036ae: 6a1a ldr r2, [r3, #32]
80036b0: 697b ldr r3, [r7, #20]
80036b2: 43db mvns r3, r3
80036b4: 401a ands r2, r3
80036b6: 68fb ldr r3, [r7, #12]
80036b8: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
80036ba: 68fb ldr r3, [r7, #12]
80036bc: 6a1a ldr r2, [r3, #32]
80036be: 68bb ldr r3, [r7, #8]
80036c0: f003 031f and.w r3, r3, #31
80036c4: 6879 ldr r1, [r7, #4]
80036c6: fa01 f303 lsl.w r3, r1, r3
80036ca: 431a orrs r2, r3
80036cc: 68fb ldr r3, [r7, #12]
80036ce: 621a str r2, [r3, #32]
}
80036d0: bf00 nop
80036d2: 371c adds r7, #28
80036d4: 46bd mov sp, r7
80036d6: bc80 pop {r7}
80036d8: 4770 bx lr
...
080036dc <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
80036dc: b480 push {r7}
80036de: b085 sub sp, #20
80036e0: af00 add r7, sp, #0
80036e2: 6078 str r0, [r7, #4]
80036e4: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80036e6: 687b ldr r3, [r7, #4]
80036e8: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
80036ec: 2b01 cmp r3, #1
80036ee: d101 bne.n 80036f4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
80036f0: 2302 movs r3, #2
80036f2: e046 b.n 8003782 <HAL_TIMEx_MasterConfigSynchronization+0xa6>
80036f4: 687b ldr r3, [r7, #4]
80036f6: 2201 movs r2, #1
80036f8: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80036fc: 687b ldr r3, [r7, #4]
80036fe: 2202 movs r2, #2
8003700: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8003704: 687b ldr r3, [r7, #4]
8003706: 681b ldr r3, [r3, #0]
8003708: 685b ldr r3, [r3, #4]
800370a: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800370c: 687b ldr r3, [r7, #4]
800370e: 681b ldr r3, [r3, #0]
8003710: 689b ldr r3, [r3, #8]
8003712: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8003714: 68fb ldr r3, [r7, #12]
8003716: f023 0370 bic.w r3, r3, #112 @ 0x70
800371a: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800371c: 683b ldr r3, [r7, #0]
800371e: 681b ldr r3, [r3, #0]
8003720: 68fa ldr r2, [r7, #12]
8003722: 4313 orrs r3, r2
8003724: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8003726: 687b ldr r3, [r7, #4]
8003728: 681b ldr r3, [r3, #0]
800372a: 68fa ldr r2, [r7, #12]
800372c: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800372e: 687b ldr r3, [r7, #4]
8003730: 681b ldr r3, [r3, #0]
8003732: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8003736: d00e beq.n 8003756 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8003738: 687b ldr r3, [r7, #4]
800373a: 681b ldr r3, [r3, #0]
800373c: 4a13 ldr r2, [pc, #76] @ (800378c <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
800373e: 4293 cmp r3, r2
8003740: d009 beq.n 8003756 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8003742: 687b ldr r3, [r7, #4]
8003744: 681b ldr r3, [r3, #0]
8003746: 4a12 ldr r2, [pc, #72] @ (8003790 <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8003748: 4293 cmp r3, r2
800374a: d004 beq.n 8003756 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
800374c: 687b ldr r3, [r7, #4]
800374e: 681b ldr r3, [r3, #0]
8003750: 4a10 ldr r2, [pc, #64] @ (8003794 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8003752: 4293 cmp r3, r2
8003754: d10c bne.n 8003770 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8003756: 68bb ldr r3, [r7, #8]
8003758: f023 0380 bic.w r3, r3, #128 @ 0x80
800375c: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800375e: 683b ldr r3, [r7, #0]
8003760: 685b ldr r3, [r3, #4]
8003762: 68ba ldr r2, [r7, #8]
8003764: 4313 orrs r3, r2
8003766: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8003768: 687b ldr r3, [r7, #4]
800376a: 681b ldr r3, [r3, #0]
800376c: 68ba ldr r2, [r7, #8]
800376e: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8003770: 687b ldr r3, [r7, #4]
8003772: 2201 movs r2, #1
8003774: f883 2039 strb.w r2, [r3, #57] @ 0x39
__HAL_UNLOCK(htim);
8003778: 687b ldr r3, [r7, #4]
800377a: 2200 movs r2, #0
800377c: f883 2038 strb.w r2, [r3, #56] @ 0x38
return HAL_OK;
8003780: 2300 movs r3, #0
}
8003782: 4618 mov r0, r3
8003784: 3714 adds r7, #20
8003786: 46bd mov sp, r7
8003788: bc80 pop {r7}
800378a: 4770 bx lr
800378c: 40000400 .word 0x40000400
8003790: 40000800 .word 0x40000800
8003794: 40010800 .word 0x40010800
08003798 <memset>:
8003798: 4603 mov r3, r0
800379a: 4402 add r2, r0
800379c: 4293 cmp r3, r2
800379e: d100 bne.n 80037a2 <memset+0xa>
80037a0: 4770 bx lr
80037a2: f803 1b01 strb.w r1, [r3], #1
80037a6: e7f9 b.n 800379c <memset+0x4>
080037a8 <__libc_init_array>:
80037a8: b570 push {r4, r5, r6, lr}
80037aa: 2600 movs r6, #0
80037ac: 4d0c ldr r5, [pc, #48] @ (80037e0 <__libc_init_array+0x38>)
80037ae: 4c0d ldr r4, [pc, #52] @ (80037e4 <__libc_init_array+0x3c>)
80037b0: 1b64 subs r4, r4, r5
80037b2: 10a4 asrs r4, r4, #2
80037b4: 42a6 cmp r6, r4
80037b6: d109 bne.n 80037cc <__libc_init_array+0x24>
80037b8: f000 f81a bl 80037f0 <_init>
80037bc: 2600 movs r6, #0
80037be: 4d0a ldr r5, [pc, #40] @ (80037e8 <__libc_init_array+0x40>)
80037c0: 4c0a ldr r4, [pc, #40] @ (80037ec <__libc_init_array+0x44>)
80037c2: 1b64 subs r4, r4, r5
80037c4: 10a4 asrs r4, r4, #2
80037c6: 42a6 cmp r6, r4
80037c8: d105 bne.n 80037d6 <__libc_init_array+0x2e>
80037ca: bd70 pop {r4, r5, r6, pc}
80037cc: f855 3b04 ldr.w r3, [r5], #4
80037d0: 4798 blx r3
80037d2: 3601 adds r6, #1
80037d4: e7ee b.n 80037b4 <__libc_init_array+0xc>
80037d6: f855 3b04 ldr.w r3, [r5], #4
80037da: 4798 blx r3
80037dc: 3601 adds r6, #1
80037de: e7f2 b.n 80037c6 <__libc_init_array+0x1e>
80037e0: 0800383c .word 0x0800383c
80037e4: 0800383c .word 0x0800383c
80037e8: 0800383c .word 0x0800383c
80037ec: 08003840 .word 0x08003840
080037f0 <_init>:
80037f0: b5f8 push {r3, r4, r5, r6, r7, lr}
80037f2: bf00 nop
80037f4: bcf8 pop {r3, r4, r5, r6, r7}
80037f6: bc08 pop {r3}
80037f8: 469e mov lr, r3
80037fa: 4770 bx lr
080037fc <_fini>:
80037fc: b5f8 push {r3, r4, r5, r6, r7, lr}
80037fe: bf00 nop
8003800: bcf8 pop {r3, r4, r5, r6, r7}
8003802: bc08 pop {r3}
8003804: 469e mov lr, r3
8003806: 4770 bx lr
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