BreizhHardware/TP-STM32-CIPA3
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TP-STM32-CIPA3/TP5_TEMP/Debug/TP5_TEMP.list

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TP5_TEMP.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003f4c 08000140 08000140 00001140 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000860 0800408c 0800408c 0000508c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080048ec 080048ec 0000600c 2**0
CONTENTS, READONLY
4 .ARM 00000008 080048ec 080048ec 000058ec 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080048f4 080048f4 0000600c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080048f4 080048f4 000058f4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 080048f8 080048f8 000058f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 080048fc 00006000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000cc 2000000c 08004908 0000600c 2**2
ALLOC
10 ._user_heap_stack 00000600 200000d8 08004908 000060d8 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000600c 2**0
CONTENTS, READONLY
12 .debug_info 00007879 00000000 00000000 00006035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001970 00000000 00000000 0000d8ae 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000007e0 00000000 00000000 0000f220 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000005e4 00000000 00000000 0000fa00 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00015783 00000000 00000000 0000ffe4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00008d64 00000000 00000000 00025767 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00088159 00000000 00000000 0002e4cb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000b6624 2**0
CONTENTS, READONLY
20 .debug_frame 000020c0 00000000 00000000 000b6668 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000068 00000000 00000000 000b8728 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000140 <__do_global_dtors_aux>:
8000140: b510 push {r4, lr}
8000142: 4c05 ldr r4, [pc, #20] @ (8000158 <__do_global_dtors_aux+0x18>)
8000144: 7823 ldrb r3, [r4, #0]
8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16>
8000148: 4b04 ldr r3, [pc, #16] @ (800015c <__do_global_dtors_aux+0x1c>)
800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12>
800014c: 4804 ldr r0, [pc, #16] @ (8000160 <__do_global_dtors_aux+0x20>)
800014e: f3af 8000 nop.w
8000152: 2301 movs r3, #1
8000154: 7023 strb r3, [r4, #0]
8000156: bd10 pop {r4, pc}
8000158: 2000000c .word 0x2000000c
800015c: 00000000 .word 0x00000000
8000160: 08004074 .word 0x08004074
08000164 <frame_dummy>:
8000164: b508 push {r3, lr}
8000166: 4b03 ldr r3, [pc, #12] @ (8000174 <frame_dummy+0x10>)
8000168: b11b cbz r3, 8000172 <frame_dummy+0xe>
800016a: 4903 ldr r1, [pc, #12] @ (8000178 <frame_dummy+0x14>)
800016c: 4803 ldr r0, [pc, #12] @ (800017c <frame_dummy+0x18>)
800016e: f3af 8000 nop.w
8000172: bd08 pop {r3, pc}
8000174: 00000000 .word 0x00000000
8000178: 20000010 .word 0x20000010
800017c: 08004074 .word 0x08004074
08000180 <__aeabi_drsub>:
8000180: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
8000184: e002 b.n 800018c <__adddf3>
8000186: bf00 nop
08000188 <__aeabi_dsub>:
8000188: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
0800018c <__adddf3>:
800018c: b530 push {r4, r5, lr}
800018e: ea4f 0441 mov.w r4, r1, lsl #1
8000192: ea4f 0543 mov.w r5, r3, lsl #1
8000196: ea94 0f05 teq r4, r5
800019a: bf08 it eq
800019c: ea90 0f02 teqeq r0, r2
80001a0: bf1f itttt ne
80001a2: ea54 0c00 orrsne.w ip, r4, r0
80001a6: ea55 0c02 orrsne.w ip, r5, r2
80001aa: ea7f 5c64 mvnsne.w ip, r4, asr #21
80001ae: ea7f 5c65 mvnsne.w ip, r5, asr #21
80001b2: f000 80e2 beq.w 800037a <__adddf3+0x1ee>
80001b6: ea4f 5454 mov.w r4, r4, lsr #21
80001ba: ebd4 5555 rsbs r5, r4, r5, lsr #21
80001be: bfb8 it lt
80001c0: 426d neglt r5, r5
80001c2: dd0c ble.n 80001de <__adddf3+0x52>
80001c4: 442c add r4, r5
80001c6: ea80 0202 eor.w r2, r0, r2
80001ca: ea81 0303 eor.w r3, r1, r3
80001ce: ea82 0000 eor.w r0, r2, r0
80001d2: ea83 0101 eor.w r1, r3, r1
80001d6: ea80 0202 eor.w r2, r0, r2
80001da: ea81 0303 eor.w r3, r1, r3
80001de: 2d36 cmp r5, #54 @ 0x36
80001e0: bf88 it hi
80001e2: bd30 pophi {r4, r5, pc}
80001e4: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80001e8: ea4f 3101 mov.w r1, r1, lsl #12
80001ec: f44f 1c80 mov.w ip, #1048576 @ 0x100000
80001f0: ea4c 3111 orr.w r1, ip, r1, lsr #12
80001f4: d002 beq.n 80001fc <__adddf3+0x70>
80001f6: 4240 negs r0, r0
80001f8: eb61 0141 sbc.w r1, r1, r1, lsl #1
80001fc: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
8000200: ea4f 3303 mov.w r3, r3, lsl #12
8000204: ea4c 3313 orr.w r3, ip, r3, lsr #12
8000208: d002 beq.n 8000210 <__adddf3+0x84>
800020a: 4252 negs r2, r2
800020c: eb63 0343 sbc.w r3, r3, r3, lsl #1
8000210: ea94 0f05 teq r4, r5
8000214: f000 80a7 beq.w 8000366 <__adddf3+0x1da>
8000218: f1a4 0401 sub.w r4, r4, #1
800021c: f1d5 0e20 rsbs lr, r5, #32
8000220: db0d blt.n 800023e <__adddf3+0xb2>
8000222: fa02 fc0e lsl.w ip, r2, lr
8000226: fa22 f205 lsr.w r2, r2, r5
800022a: 1880 adds r0, r0, r2
800022c: f141 0100 adc.w r1, r1, #0
8000230: fa03 f20e lsl.w r2, r3, lr
8000234: 1880 adds r0, r0, r2
8000236: fa43 f305 asr.w r3, r3, r5
800023a: 4159 adcs r1, r3
800023c: e00e b.n 800025c <__adddf3+0xd0>
800023e: f1a5 0520 sub.w r5, r5, #32
8000242: f10e 0e20 add.w lr, lr, #32
8000246: 2a01 cmp r2, #1
8000248: fa03 fc0e lsl.w ip, r3, lr
800024c: bf28 it cs
800024e: f04c 0c02 orrcs.w ip, ip, #2
8000252: fa43 f305 asr.w r3, r3, r5
8000256: 18c0 adds r0, r0, r3
8000258: eb51 71e3 adcs.w r1, r1, r3, asr #31
800025c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000260: d507 bpl.n 8000272 <__adddf3+0xe6>
8000262: f04f 0e00 mov.w lr, #0
8000266: f1dc 0c00 rsbs ip, ip, #0
800026a: eb7e 0000 sbcs.w r0, lr, r0
800026e: eb6e 0101 sbc.w r1, lr, r1
8000272: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
8000276: d31b bcc.n 80002b0 <__adddf3+0x124>
8000278: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
800027c: d30c bcc.n 8000298 <__adddf3+0x10c>
800027e: 0849 lsrs r1, r1, #1
8000280: ea5f 0030 movs.w r0, r0, rrx
8000284: ea4f 0c3c mov.w ip, ip, rrx
8000288: f104 0401 add.w r4, r4, #1
800028c: ea4f 5244 mov.w r2, r4, lsl #21
8000290: f512 0f80 cmn.w r2, #4194304 @ 0x400000
8000294: f080 809a bcs.w 80003cc <__adddf3+0x240>
8000298: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
800029c: bf08 it eq
800029e: ea5f 0c50 movseq.w ip, r0, lsr #1
80002a2: f150 0000 adcs.w r0, r0, #0
80002a6: eb41 5104 adc.w r1, r1, r4, lsl #20
80002aa: ea41 0105 orr.w r1, r1, r5
80002ae: bd30 pop {r4, r5, pc}
80002b0: ea5f 0c4c movs.w ip, ip, lsl #1
80002b4: 4140 adcs r0, r0
80002b6: eb41 0101 adc.w r1, r1, r1
80002ba: 3c01 subs r4, #1
80002bc: bf28 it cs
80002be: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
80002c2: d2e9 bcs.n 8000298 <__adddf3+0x10c>
80002c4: f091 0f00 teq r1, #0
80002c8: bf04 itt eq
80002ca: 4601 moveq r1, r0
80002cc: 2000 moveq r0, #0
80002ce: fab1 f381 clz r3, r1
80002d2: bf08 it eq
80002d4: 3320 addeq r3, #32
80002d6: f1a3 030b sub.w r3, r3, #11
80002da: f1b3 0220 subs.w r2, r3, #32
80002de: da0c bge.n 80002fa <__adddf3+0x16e>
80002e0: 320c adds r2, #12
80002e2: dd08 ble.n 80002f6 <__adddf3+0x16a>
80002e4: f102 0c14 add.w ip, r2, #20
80002e8: f1c2 020c rsb r2, r2, #12
80002ec: fa01 f00c lsl.w r0, r1, ip
80002f0: fa21 f102 lsr.w r1, r1, r2
80002f4: e00c b.n 8000310 <__adddf3+0x184>
80002f6: f102 0214 add.w r2, r2, #20
80002fa: bfd8 it le
80002fc: f1c2 0c20 rsble ip, r2, #32
8000300: fa01 f102 lsl.w r1, r1, r2
8000304: fa20 fc0c lsr.w ip, r0, ip
8000308: bfdc itt le
800030a: ea41 010c orrle.w r1, r1, ip
800030e: 4090 lslle r0, r2
8000310: 1ae4 subs r4, r4, r3
8000312: bfa2 ittt ge
8000314: eb01 5104 addge.w r1, r1, r4, lsl #20
8000318: 4329 orrge r1, r5
800031a: bd30 popge {r4, r5, pc}
800031c: ea6f 0404 mvn.w r4, r4
8000320: 3c1f subs r4, #31
8000322: da1c bge.n 800035e <__adddf3+0x1d2>
8000324: 340c adds r4, #12
8000326: dc0e bgt.n 8000346 <__adddf3+0x1ba>
8000328: f104 0414 add.w r4, r4, #20
800032c: f1c4 0220 rsb r2, r4, #32
8000330: fa20 f004 lsr.w r0, r0, r4
8000334: fa01 f302 lsl.w r3, r1, r2
8000338: ea40 0003 orr.w r0, r0, r3
800033c: fa21 f304 lsr.w r3, r1, r4
8000340: ea45 0103 orr.w r1, r5, r3
8000344: bd30 pop {r4, r5, pc}
8000346: f1c4 040c rsb r4, r4, #12
800034a: f1c4 0220 rsb r2, r4, #32
800034e: fa20 f002 lsr.w r0, r0, r2
8000352: fa01 f304 lsl.w r3, r1, r4
8000356: ea40 0003 orr.w r0, r0, r3
800035a: 4629 mov r1, r5
800035c: bd30 pop {r4, r5, pc}
800035e: fa21 f004 lsr.w r0, r1, r4
8000362: 4629 mov r1, r5
8000364: bd30 pop {r4, r5, pc}
8000366: f094 0f00 teq r4, #0
800036a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
800036e: bf06 itte eq
8000370: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
8000374: 3401 addeq r4, #1
8000376: 3d01 subne r5, #1
8000378: e74e b.n 8000218 <__adddf3+0x8c>
800037a: ea7f 5c64 mvns.w ip, r4, asr #21
800037e: bf18 it ne
8000380: ea7f 5c65 mvnsne.w ip, r5, asr #21
8000384: d029 beq.n 80003da <__adddf3+0x24e>
8000386: ea94 0f05 teq r4, r5
800038a: bf08 it eq
800038c: ea90 0f02 teqeq r0, r2
8000390: d005 beq.n 800039e <__adddf3+0x212>
8000392: ea54 0c00 orrs.w ip, r4, r0
8000396: bf04 itt eq
8000398: 4619 moveq r1, r3
800039a: 4610 moveq r0, r2
800039c: bd30 pop {r4, r5, pc}
800039e: ea91 0f03 teq r1, r3
80003a2: bf1e ittt ne
80003a4: 2100 movne r1, #0
80003a6: 2000 movne r0, #0
80003a8: bd30 popne {r4, r5, pc}
80003aa: ea5f 5c54 movs.w ip, r4, lsr #21
80003ae: d105 bne.n 80003bc <__adddf3+0x230>
80003b0: 0040 lsls r0, r0, #1
80003b2: 4149 adcs r1, r1
80003b4: bf28 it cs
80003b6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
80003ba: bd30 pop {r4, r5, pc}
80003bc: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
80003c0: bf3c itt cc
80003c2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
80003c6: bd30 popcc {r4, r5, pc}
80003c8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
80003cc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
80003d0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
80003d4: f04f 0000 mov.w r0, #0
80003d8: bd30 pop {r4, r5, pc}
80003da: ea7f 5c64 mvns.w ip, r4, asr #21
80003de: bf1a itte ne
80003e0: 4619 movne r1, r3
80003e2: 4610 movne r0, r2
80003e4: ea7f 5c65 mvnseq.w ip, r5, asr #21
80003e8: bf1c itt ne
80003ea: 460b movne r3, r1
80003ec: 4602 movne r2, r0
80003ee: ea50 3401 orrs.w r4, r0, r1, lsl #12
80003f2: bf06 itte eq
80003f4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
80003f8: ea91 0f03 teqeq r1, r3
80003fc: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
8000400: bd30 pop {r4, r5, pc}
8000402: bf00 nop
08000404 <__aeabi_ui2d>:
8000404: f090 0f00 teq r0, #0
8000408: bf04 itt eq
800040a: 2100 moveq r1, #0
800040c: 4770 bxeq lr
800040e: b530 push {r4, r5, lr}
8000410: f44f 6480 mov.w r4, #1024 @ 0x400
8000414: f104 0432 add.w r4, r4, #50 @ 0x32
8000418: f04f 0500 mov.w r5, #0
800041c: f04f 0100 mov.w r1, #0
8000420: e750 b.n 80002c4 <__adddf3+0x138>
8000422: bf00 nop
08000424 <__aeabi_i2d>:
8000424: f090 0f00 teq r0, #0
8000428: bf04 itt eq
800042a: 2100 moveq r1, #0
800042c: 4770 bxeq lr
800042e: b530 push {r4, r5, lr}
8000430: f44f 6480 mov.w r4, #1024 @ 0x400
8000434: f104 0432 add.w r4, r4, #50 @ 0x32
8000438: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
800043c: bf48 it mi
800043e: 4240 negmi r0, r0
8000440: f04f 0100 mov.w r1, #0
8000444: e73e b.n 80002c4 <__adddf3+0x138>
8000446: bf00 nop
08000448 <__aeabi_f2d>:
8000448: 0042 lsls r2, r0, #1
800044a: ea4f 01e2 mov.w r1, r2, asr #3
800044e: ea4f 0131 mov.w r1, r1, rrx
8000452: ea4f 7002 mov.w r0, r2, lsl #28
8000456: bf1f itttt ne
8000458: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
800045c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
8000460: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
8000464: 4770 bxne lr
8000466: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
800046a: bf08 it eq
800046c: 4770 bxeq lr
800046e: f093 4f7f teq r3, #4278190080 @ 0xff000000
8000472: bf04 itt eq
8000474: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
8000478: 4770 bxeq lr
800047a: b530 push {r4, r5, lr}
800047c: f44f 7460 mov.w r4, #896 @ 0x380
8000480: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
8000484: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000488: e71c b.n 80002c4 <__adddf3+0x138>
800048a: bf00 nop
0800048c <__aeabi_ul2d>:
800048c: ea50 0201 orrs.w r2, r0, r1
8000490: bf08 it eq
8000492: 4770 bxeq lr
8000494: b530 push {r4, r5, lr}
8000496: f04f 0500 mov.w r5, #0
800049a: e00a b.n 80004b2 <__aeabi_l2d+0x16>
0800049c <__aeabi_l2d>:
800049c: ea50 0201 orrs.w r2, r0, r1
80004a0: bf08 it eq
80004a2: 4770 bxeq lr
80004a4: b530 push {r4, r5, lr}
80004a6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
80004aa: d502 bpl.n 80004b2 <__aeabi_l2d+0x16>
80004ac: 4240 negs r0, r0
80004ae: eb61 0141 sbc.w r1, r1, r1, lsl #1
80004b2: f44f 6480 mov.w r4, #1024 @ 0x400
80004b6: f104 0432 add.w r4, r4, #50 @ 0x32
80004ba: ea5f 5c91 movs.w ip, r1, lsr #22
80004be: f43f aed8 beq.w 8000272 <__adddf3+0xe6>
80004c2: f04f 0203 mov.w r2, #3
80004c6: ea5f 0cdc movs.w ip, ip, lsr #3
80004ca: bf18 it ne
80004cc: 3203 addne r2, #3
80004ce: ea5f 0cdc movs.w ip, ip, lsr #3
80004d2: bf18 it ne
80004d4: 3203 addne r2, #3
80004d6: eb02 02dc add.w r2, r2, ip, lsr #3
80004da: f1c2 0320 rsb r3, r2, #32
80004de: fa00 fc03 lsl.w ip, r0, r3
80004e2: fa20 f002 lsr.w r0, r0, r2
80004e6: fa01 fe03 lsl.w lr, r1, r3
80004ea: ea40 000e orr.w r0, r0, lr
80004ee: fa21 f102 lsr.w r1, r1, r2
80004f2: 4414 add r4, r2
80004f4: e6bd b.n 8000272 <__adddf3+0xe6>
80004f6: bf00 nop
080004f8 <__aeabi_dmul>:
80004f8: b570 push {r4, r5, r6, lr}
80004fa: f04f 0cff mov.w ip, #255 @ 0xff
80004fe: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000502: ea1c 5411 ands.w r4, ip, r1, lsr #20
8000506: bf1d ittte ne
8000508: ea1c 5513 andsne.w r5, ip, r3, lsr #20
800050c: ea94 0f0c teqne r4, ip
8000510: ea95 0f0c teqne r5, ip
8000514: f000 f8de bleq 80006d4 <__aeabi_dmul+0x1dc>
8000518: 442c add r4, r5
800051a: ea81 0603 eor.w r6, r1, r3
800051e: ea21 514c bic.w r1, r1, ip, lsl #21
8000522: ea23 534c bic.w r3, r3, ip, lsl #21
8000526: ea50 3501 orrs.w r5, r0, r1, lsl #12
800052a: bf18 it ne
800052c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
8000530: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
8000534: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8000538: d038 beq.n 80005ac <__aeabi_dmul+0xb4>
800053a: fba0 ce02 umull ip, lr, r0, r2
800053e: f04f 0500 mov.w r5, #0
8000542: fbe1 e502 umlal lr, r5, r1, r2
8000546: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
800054a: fbe0 e503 umlal lr, r5, r0, r3
800054e: f04f 0600 mov.w r6, #0
8000552: fbe1 5603 umlal r5, r6, r1, r3
8000556: f09c 0f00 teq ip, #0
800055a: bf18 it ne
800055c: f04e 0e01 orrne.w lr, lr, #1
8000560: f1a4 04ff sub.w r4, r4, #255 @ 0xff
8000564: f5b6 7f00 cmp.w r6, #512 @ 0x200
8000568: f564 7440 sbc.w r4, r4, #768 @ 0x300
800056c: d204 bcs.n 8000578 <__aeabi_dmul+0x80>
800056e: ea5f 0e4e movs.w lr, lr, lsl #1
8000572: 416d adcs r5, r5
8000574: eb46 0606 adc.w r6, r6, r6
8000578: ea42 21c6 orr.w r1, r2, r6, lsl #11
800057c: ea41 5155 orr.w r1, r1, r5, lsr #21
8000580: ea4f 20c5 mov.w r0, r5, lsl #11
8000584: ea40 505e orr.w r0, r0, lr, lsr #21
8000588: ea4f 2ece mov.w lr, lr, lsl #11
800058c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
8000590: bf88 it hi
8000592: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
8000596: d81e bhi.n 80005d6 <__aeabi_dmul+0xde>
8000598: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
800059c: bf08 it eq
800059e: ea5f 0e50 movseq.w lr, r0, lsr #1
80005a2: f150 0000 adcs.w r0, r0, #0
80005a6: eb41 5104 adc.w r1, r1, r4, lsl #20
80005aa: bd70 pop {r4, r5, r6, pc}
80005ac: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
80005b0: ea46 0101 orr.w r1, r6, r1
80005b4: ea40 0002 orr.w r0, r0, r2
80005b8: ea81 0103 eor.w r1, r1, r3
80005bc: ebb4 045c subs.w r4, r4, ip, lsr #1
80005c0: bfc2 ittt gt
80005c2: ebd4 050c rsbsgt r5, r4, ip
80005c6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80005ca: bd70 popgt {r4, r5, r6, pc}
80005cc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80005d0: f04f 0e00 mov.w lr, #0
80005d4: 3c01 subs r4, #1
80005d6: f300 80ab bgt.w 8000730 <__aeabi_dmul+0x238>
80005da: f114 0f36 cmn.w r4, #54 @ 0x36
80005de: bfde ittt le
80005e0: 2000 movle r0, #0
80005e2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
80005e6: bd70 pople {r4, r5, r6, pc}
80005e8: f1c4 0400 rsb r4, r4, #0
80005ec: 3c20 subs r4, #32
80005ee: da35 bge.n 800065c <__aeabi_dmul+0x164>
80005f0: 340c adds r4, #12
80005f2: dc1b bgt.n 800062c <__aeabi_dmul+0x134>
80005f4: f104 0414 add.w r4, r4, #20
80005f8: f1c4 0520 rsb r5, r4, #32
80005fc: fa00 f305 lsl.w r3, r0, r5
8000600: fa20 f004 lsr.w r0, r0, r4
8000604: fa01 f205 lsl.w r2, r1, r5
8000608: ea40 0002 orr.w r0, r0, r2
800060c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
8000610: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000614: eb10 70d3 adds.w r0, r0, r3, lsr #31
8000618: fa21 f604 lsr.w r6, r1, r4
800061c: eb42 0106 adc.w r1, r2, r6
8000620: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000624: bf08 it eq
8000626: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800062a: bd70 pop {r4, r5, r6, pc}
800062c: f1c4 040c rsb r4, r4, #12
8000630: f1c4 0520 rsb r5, r4, #32
8000634: fa00 f304 lsl.w r3, r0, r4
8000638: fa20 f005 lsr.w r0, r0, r5
800063c: fa01 f204 lsl.w r2, r1, r4
8000640: ea40 0002 orr.w r0, r0, r2
8000644: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000648: eb10 70d3 adds.w r0, r0, r3, lsr #31
800064c: f141 0100 adc.w r1, r1, #0
8000650: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
8000654: bf08 it eq
8000656: ea20 70d3 biceq.w r0, r0, r3, lsr #31
800065a: bd70 pop {r4, r5, r6, pc}
800065c: f1c4 0520 rsb r5, r4, #32
8000660: fa00 f205 lsl.w r2, r0, r5
8000664: ea4e 0e02 orr.w lr, lr, r2
8000668: fa20 f304 lsr.w r3, r0, r4
800066c: fa01 f205 lsl.w r2, r1, r5
8000670: ea43 0302 orr.w r3, r3, r2
8000674: fa21 f004 lsr.w r0, r1, r4
8000678: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
800067c: fa21 f204 lsr.w r2, r1, r4
8000680: ea20 0002 bic.w r0, r0, r2
8000684: eb00 70d3 add.w r0, r0, r3, lsr #31
8000688: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
800068c: bf08 it eq
800068e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
8000692: bd70 pop {r4, r5, r6, pc}
8000694: f094 0f00 teq r4, #0
8000698: d10f bne.n 80006ba <__aeabi_dmul+0x1c2>
800069a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
800069e: 0040 lsls r0, r0, #1
80006a0: eb41 0101 adc.w r1, r1, r1
80006a4: f411 1f80 tst.w r1, #1048576 @ 0x100000
80006a8: bf08 it eq
80006aa: 3c01 subeq r4, #1
80006ac: d0f7 beq.n 800069e <__aeabi_dmul+0x1a6>
80006ae: ea41 0106 orr.w r1, r1, r6
80006b2: f095 0f00 teq r5, #0
80006b6: bf18 it ne
80006b8: 4770 bxne lr
80006ba: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
80006be: 0052 lsls r2, r2, #1
80006c0: eb43 0303 adc.w r3, r3, r3
80006c4: f413 1f80 tst.w r3, #1048576 @ 0x100000
80006c8: bf08 it eq
80006ca: 3d01 subeq r5, #1
80006cc: d0f7 beq.n 80006be <__aeabi_dmul+0x1c6>
80006ce: ea43 0306 orr.w r3, r3, r6
80006d2: 4770 bx lr
80006d4: ea94 0f0c teq r4, ip
80006d8: ea0c 5513 and.w r5, ip, r3, lsr #20
80006dc: bf18 it ne
80006de: ea95 0f0c teqne r5, ip
80006e2: d00c beq.n 80006fe <__aeabi_dmul+0x206>
80006e4: ea50 0641 orrs.w r6, r0, r1, lsl #1
80006e8: bf18 it ne
80006ea: ea52 0643 orrsne.w r6, r2, r3, lsl #1
80006ee: d1d1 bne.n 8000694 <__aeabi_dmul+0x19c>
80006f0: ea81 0103 eor.w r1, r1, r3
80006f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
80006f8: f04f 0000 mov.w r0, #0
80006fc: bd70 pop {r4, r5, r6, pc}
80006fe: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000702: bf06 itte eq
8000704: 4610 moveq r0, r2
8000706: 4619 moveq r1, r3
8000708: ea52 0643 orrsne.w r6, r2, r3, lsl #1
800070c: d019 beq.n 8000742 <__aeabi_dmul+0x24a>
800070e: ea94 0f0c teq r4, ip
8000712: d102 bne.n 800071a <__aeabi_dmul+0x222>
8000714: ea50 3601 orrs.w r6, r0, r1, lsl #12
8000718: d113 bne.n 8000742 <__aeabi_dmul+0x24a>
800071a: ea95 0f0c teq r5, ip
800071e: d105 bne.n 800072c <__aeabi_dmul+0x234>
8000720: ea52 3603 orrs.w r6, r2, r3, lsl #12
8000724: bf1c itt ne
8000726: 4610 movne r0, r2
8000728: 4619 movne r1, r3
800072a: d10a bne.n 8000742 <__aeabi_dmul+0x24a>
800072c: ea81 0103 eor.w r1, r1, r3
8000730: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000734: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000738: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
800073c: f04f 0000 mov.w r0, #0
8000740: bd70 pop {r4, r5, r6, pc}
8000742: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
8000746: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
800074a: bd70 pop {r4, r5, r6, pc}
0800074c <__aeabi_ddiv>:
800074c: b570 push {r4, r5, r6, lr}
800074e: f04f 0cff mov.w ip, #255 @ 0xff
8000752: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
8000756: ea1c 5411 ands.w r4, ip, r1, lsr #20
800075a: bf1d ittte ne
800075c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
8000760: ea94 0f0c teqne r4, ip
8000764: ea95 0f0c teqne r5, ip
8000768: f000 f8a7 bleq 80008ba <__aeabi_ddiv+0x16e>
800076c: eba4 0405 sub.w r4, r4, r5
8000770: ea81 0e03 eor.w lr, r1, r3
8000774: ea52 3503 orrs.w r5, r2, r3, lsl #12
8000778: ea4f 3101 mov.w r1, r1, lsl #12
800077c: f000 8088 beq.w 8000890 <__aeabi_ddiv+0x144>
8000780: ea4f 3303 mov.w r3, r3, lsl #12
8000784: f04f 5580 mov.w r5, #268435456 @ 0x10000000
8000788: ea45 1313 orr.w r3, r5, r3, lsr #4
800078c: ea43 6312 orr.w r3, r3, r2, lsr #24
8000790: ea4f 2202 mov.w r2, r2, lsl #8
8000794: ea45 1511 orr.w r5, r5, r1, lsr #4
8000798: ea45 6510 orr.w r5, r5, r0, lsr #24
800079c: ea4f 2600 mov.w r6, r0, lsl #8
80007a0: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
80007a4: 429d cmp r5, r3
80007a6: bf08 it eq
80007a8: 4296 cmpeq r6, r2
80007aa: f144 04fd adc.w r4, r4, #253 @ 0xfd
80007ae: f504 7440 add.w r4, r4, #768 @ 0x300
80007b2: d202 bcs.n 80007ba <__aeabi_ddiv+0x6e>
80007b4: 085b lsrs r3, r3, #1
80007b6: ea4f 0232 mov.w r2, r2, rrx
80007ba: 1ab6 subs r6, r6, r2
80007bc: eb65 0503 sbc.w r5, r5, r3
80007c0: 085b lsrs r3, r3, #1
80007c2: ea4f 0232 mov.w r2, r2, rrx
80007c6: f44f 1080 mov.w r0, #1048576 @ 0x100000
80007ca: f44f 2c00 mov.w ip, #524288 @ 0x80000
80007ce: ebb6 0e02 subs.w lr, r6, r2
80007d2: eb75 0e03 sbcs.w lr, r5, r3
80007d6: bf22 ittt cs
80007d8: 1ab6 subcs r6, r6, r2
80007da: 4675 movcs r5, lr
80007dc: ea40 000c orrcs.w r0, r0, ip
80007e0: 085b lsrs r3, r3, #1
80007e2: ea4f 0232 mov.w r2, r2, rrx
80007e6: ebb6 0e02 subs.w lr, r6, r2
80007ea: eb75 0e03 sbcs.w lr, r5, r3
80007ee: bf22 ittt cs
80007f0: 1ab6 subcs r6, r6, r2
80007f2: 4675 movcs r5, lr
80007f4: ea40 005c orrcs.w r0, r0, ip, lsr #1
80007f8: 085b lsrs r3, r3, #1
80007fa: ea4f 0232 mov.w r2, r2, rrx
80007fe: ebb6 0e02 subs.w lr, r6, r2
8000802: eb75 0e03 sbcs.w lr, r5, r3
8000806: bf22 ittt cs
8000808: 1ab6 subcs r6, r6, r2
800080a: 4675 movcs r5, lr
800080c: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000810: 085b lsrs r3, r3, #1
8000812: ea4f 0232 mov.w r2, r2, rrx
8000816: ebb6 0e02 subs.w lr, r6, r2
800081a: eb75 0e03 sbcs.w lr, r5, r3
800081e: bf22 ittt cs
8000820: 1ab6 subcs r6, r6, r2
8000822: 4675 movcs r5, lr
8000824: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000828: ea55 0e06 orrs.w lr, r5, r6
800082c: d018 beq.n 8000860 <__aeabi_ddiv+0x114>
800082e: ea4f 1505 mov.w r5, r5, lsl #4
8000832: ea45 7516 orr.w r5, r5, r6, lsr #28
8000836: ea4f 1606 mov.w r6, r6, lsl #4
800083a: ea4f 03c3 mov.w r3, r3, lsl #3
800083e: ea43 7352 orr.w r3, r3, r2, lsr #29
8000842: ea4f 02c2 mov.w r2, r2, lsl #3
8000846: ea5f 1c1c movs.w ip, ip, lsr #4
800084a: d1c0 bne.n 80007ce <__aeabi_ddiv+0x82>
800084c: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000850: d10b bne.n 800086a <__aeabi_ddiv+0x11e>
8000852: ea41 0100 orr.w r1, r1, r0
8000856: f04f 0000 mov.w r0, #0
800085a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
800085e: e7b6 b.n 80007ce <__aeabi_ddiv+0x82>
8000860: f411 1f80 tst.w r1, #1048576 @ 0x100000
8000864: bf04 itt eq
8000866: 4301 orreq r1, r0
8000868: 2000 moveq r0, #0
800086a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
800086e: bf88 it hi
8000870: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
8000874: f63f aeaf bhi.w 80005d6 <__aeabi_dmul+0xde>
8000878: ebb5 0c03 subs.w ip, r5, r3
800087c: bf04 itt eq
800087e: ebb6 0c02 subseq.w ip, r6, r2
8000882: ea5f 0c50 movseq.w ip, r0, lsr #1
8000886: f150 0000 adcs.w r0, r0, #0
800088a: eb41 5104 adc.w r1, r1, r4, lsl #20
800088e: bd70 pop {r4, r5, r6, pc}
8000890: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
8000894: ea4e 3111 orr.w r1, lr, r1, lsr #12
8000898: eb14 045c adds.w r4, r4, ip, lsr #1
800089c: bfc2 ittt gt
800089e: ebd4 050c rsbsgt r5, r4, ip
80008a2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
80008a6: bd70 popgt {r4, r5, r6, pc}
80008a8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
80008ac: f04f 0e00 mov.w lr, #0
80008b0: 3c01 subs r4, #1
80008b2: e690 b.n 80005d6 <__aeabi_dmul+0xde>
80008b4: ea45 0e06 orr.w lr, r5, r6
80008b8: e68d b.n 80005d6 <__aeabi_dmul+0xde>
80008ba: ea0c 5513 and.w r5, ip, r3, lsr #20
80008be: ea94 0f0c teq r4, ip
80008c2: bf08 it eq
80008c4: ea95 0f0c teqeq r5, ip
80008c8: f43f af3b beq.w 8000742 <__aeabi_dmul+0x24a>
80008cc: ea94 0f0c teq r4, ip
80008d0: d10a bne.n 80008e8 <__aeabi_ddiv+0x19c>
80008d2: ea50 3401 orrs.w r4, r0, r1, lsl #12
80008d6: f47f af34 bne.w 8000742 <__aeabi_dmul+0x24a>
80008da: ea95 0f0c teq r5, ip
80008de: f47f af25 bne.w 800072c <__aeabi_dmul+0x234>
80008e2: 4610 mov r0, r2
80008e4: 4619 mov r1, r3
80008e6: e72c b.n 8000742 <__aeabi_dmul+0x24a>
80008e8: ea95 0f0c teq r5, ip
80008ec: d106 bne.n 80008fc <__aeabi_ddiv+0x1b0>
80008ee: ea52 3503 orrs.w r5, r2, r3, lsl #12
80008f2: f43f aefd beq.w 80006f0 <__aeabi_dmul+0x1f8>
80008f6: 4610 mov r0, r2
80008f8: 4619 mov r1, r3
80008fa: e722 b.n 8000742 <__aeabi_dmul+0x24a>
80008fc: ea50 0641 orrs.w r6, r0, r1, lsl #1
8000900: bf18 it ne
8000902: ea52 0643 orrsne.w r6, r2, r3, lsl #1
8000906: f47f aec5 bne.w 8000694 <__aeabi_dmul+0x19c>
800090a: ea50 0441 orrs.w r4, r0, r1, lsl #1
800090e: f47f af0d bne.w 800072c <__aeabi_dmul+0x234>
8000912: ea52 0543 orrs.w r5, r2, r3, lsl #1
8000916: f47f aeeb bne.w 80006f0 <__aeabi_dmul+0x1f8>
800091a: e712 b.n 8000742 <__aeabi_dmul+0x24a>
0800091c <__aeabi_d2uiz>:
800091c: 004a lsls r2, r1, #1
800091e: d211 bcs.n 8000944 <__aeabi_d2uiz+0x28>
8000920: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
8000924: d211 bcs.n 800094a <__aeabi_d2uiz+0x2e>
8000926: d50d bpl.n 8000944 <__aeabi_d2uiz+0x28>
8000928: f46f 7378 mvn.w r3, #992 @ 0x3e0
800092c: ebb3 5262 subs.w r2, r3, r2, asr #21
8000930: d40e bmi.n 8000950 <__aeabi_d2uiz+0x34>
8000932: ea4f 23c1 mov.w r3, r1, lsl #11
8000936: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
800093a: ea43 5350 orr.w r3, r3, r0, lsr #21
800093e: fa23 f002 lsr.w r0, r3, r2
8000942: 4770 bx lr
8000944: f04f 0000 mov.w r0, #0
8000948: 4770 bx lr
800094a: ea50 3001 orrs.w r0, r0, r1, lsl #12
800094e: d102 bne.n 8000956 <__aeabi_d2uiz+0x3a>
8000950: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000954: 4770 bx lr
8000956: f04f 0000 mov.w r0, #0
800095a: 4770 bx lr
0800095c <__aeabi_frsub>:
800095c: f080 4000 eor.w r0, r0, #2147483648 @ 0x80000000
8000960: e002 b.n 8000968 <__addsf3>
8000962: bf00 nop
08000964 <__aeabi_fsub>:
8000964: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
08000968 <__addsf3>:
8000968: 0042 lsls r2, r0, #1
800096a: bf1f itttt ne
800096c: ea5f 0341 movsne.w r3, r1, lsl #1
8000970: ea92 0f03 teqne r2, r3
8000974: ea7f 6c22 mvnsne.w ip, r2, asr #24
8000978: ea7f 6c23 mvnsne.w ip, r3, asr #24
800097c: d06a beq.n 8000a54 <__addsf3+0xec>
800097e: ea4f 6212 mov.w r2, r2, lsr #24
8000982: ebd2 6313 rsbs r3, r2, r3, lsr #24
8000986: bfc1 itttt gt
8000988: 18d2 addgt r2, r2, r3
800098a: 4041 eorgt r1, r0
800098c: 4048 eorgt r0, r1
800098e: 4041 eorgt r1, r0
8000990: bfb8 it lt
8000992: 425b neglt r3, r3
8000994: 2b19 cmp r3, #25
8000996: bf88 it hi
8000998: 4770 bxhi lr
800099a: f010 4f00 tst.w r0, #2147483648 @ 0x80000000
800099e: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
80009a2: f020 407f bic.w r0, r0, #4278190080 @ 0xff000000
80009a6: bf18 it ne
80009a8: 4240 negne r0, r0
80009aa: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
80009ae: f441 0100 orr.w r1, r1, #8388608 @ 0x800000
80009b2: f021 417f bic.w r1, r1, #4278190080 @ 0xff000000
80009b6: bf18 it ne
80009b8: 4249 negne r1, r1
80009ba: ea92 0f03 teq r2, r3
80009be: d03f beq.n 8000a40 <__addsf3+0xd8>
80009c0: f1a2 0201 sub.w r2, r2, #1
80009c4: fa41 fc03 asr.w ip, r1, r3
80009c8: eb10 000c adds.w r0, r0, ip
80009cc: f1c3 0320 rsb r3, r3, #32
80009d0: fa01 f103 lsl.w r1, r1, r3
80009d4: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
80009d8: d502 bpl.n 80009e0 <__addsf3+0x78>
80009da: 4249 negs r1, r1
80009dc: eb60 0040 sbc.w r0, r0, r0, lsl #1
80009e0: f5b0 0f00 cmp.w r0, #8388608 @ 0x800000
80009e4: d313 bcc.n 8000a0e <__addsf3+0xa6>
80009e6: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000
80009ea: d306 bcc.n 80009fa <__addsf3+0x92>
80009ec: 0840 lsrs r0, r0, #1
80009ee: ea4f 0131 mov.w r1, r1, rrx
80009f2: f102 0201 add.w r2, r2, #1
80009f6: 2afe cmp r2, #254 @ 0xfe
80009f8: d251 bcs.n 8000a9e <__addsf3+0x136>
80009fa: f1b1 4f00 cmp.w r1, #2147483648 @ 0x80000000
80009fe: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000a02: bf08 it eq
8000a04: f020 0001 biceq.w r0, r0, #1
8000a08: ea40 0003 orr.w r0, r0, r3
8000a0c: 4770 bx lr
8000a0e: 0049 lsls r1, r1, #1
8000a10: eb40 0000 adc.w r0, r0, r0
8000a14: 3a01 subs r2, #1
8000a16: bf28 it cs
8000a18: f5b0 0f00 cmpcs.w r0, #8388608 @ 0x800000
8000a1c: d2ed bcs.n 80009fa <__addsf3+0x92>
8000a1e: fab0 fc80 clz ip, r0
8000a22: f1ac 0c08 sub.w ip, ip, #8
8000a26: ebb2 020c subs.w r2, r2, ip
8000a2a: fa00 f00c lsl.w r0, r0, ip
8000a2e: bfaa itet ge
8000a30: eb00 50c2 addge.w r0, r0, r2, lsl #23
8000a34: 4252 neglt r2, r2
8000a36: 4318 orrge r0, r3
8000a38: bfbc itt lt
8000a3a: 40d0 lsrlt r0, r2
8000a3c: 4318 orrlt r0, r3
8000a3e: 4770 bx lr
8000a40: f092 0f00 teq r2, #0
8000a44: f481 0100 eor.w r1, r1, #8388608 @ 0x800000
8000a48: bf06 itte eq
8000a4a: f480 0000 eoreq.w r0, r0, #8388608 @ 0x800000
8000a4e: 3201 addeq r2, #1
8000a50: 3b01 subne r3, #1
8000a52: e7b5 b.n 80009c0 <__addsf3+0x58>
8000a54: ea4f 0341 mov.w r3, r1, lsl #1
8000a58: ea7f 6c22 mvns.w ip, r2, asr #24
8000a5c: bf18 it ne
8000a5e: ea7f 6c23 mvnsne.w ip, r3, asr #24
8000a62: d021 beq.n 8000aa8 <__addsf3+0x140>
8000a64: ea92 0f03 teq r2, r3
8000a68: d004 beq.n 8000a74 <__addsf3+0x10c>
8000a6a: f092 0f00 teq r2, #0
8000a6e: bf08 it eq
8000a70: 4608 moveq r0, r1
8000a72: 4770 bx lr
8000a74: ea90 0f01 teq r0, r1
8000a78: bf1c itt ne
8000a7a: 2000 movne r0, #0
8000a7c: 4770 bxne lr
8000a7e: f012 4f7f tst.w r2, #4278190080 @ 0xff000000
8000a82: d104 bne.n 8000a8e <__addsf3+0x126>
8000a84: 0040 lsls r0, r0, #1
8000a86: bf28 it cs
8000a88: f040 4000 orrcs.w r0, r0, #2147483648 @ 0x80000000
8000a8c: 4770 bx lr
8000a8e: f112 7200 adds.w r2, r2, #33554432 @ 0x2000000
8000a92: bf3c itt cc
8000a94: f500 0000 addcc.w r0, r0, #8388608 @ 0x800000
8000a98: 4770 bxcc lr
8000a9a: f000 4300 and.w r3, r0, #2147483648 @ 0x80000000
8000a9e: f043 40fe orr.w r0, r3, #2130706432 @ 0x7f000000
8000aa2: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000aa6: 4770 bx lr
8000aa8: ea7f 6222 mvns.w r2, r2, asr #24
8000aac: bf16 itet ne
8000aae: 4608 movne r0, r1
8000ab0: ea7f 6323 mvnseq.w r3, r3, asr #24
8000ab4: 4601 movne r1, r0
8000ab6: 0242 lsls r2, r0, #9
8000ab8: bf06 itte eq
8000aba: ea5f 2341 movseq.w r3, r1, lsl #9
8000abe: ea90 0f01 teqeq r0, r1
8000ac2: f440 0080 orrne.w r0, r0, #4194304 @ 0x400000
8000ac6: 4770 bx lr
08000ac8 <__aeabi_ui2f>:
8000ac8: f04f 0300 mov.w r3, #0
8000acc: e004 b.n 8000ad8 <__aeabi_i2f+0x8>
8000ace: bf00 nop
08000ad0 <__aeabi_i2f>:
8000ad0: f010 4300 ands.w r3, r0, #2147483648 @ 0x80000000
8000ad4: bf48 it mi
8000ad6: 4240 negmi r0, r0
8000ad8: ea5f 0c00 movs.w ip, r0
8000adc: bf08 it eq
8000ade: 4770 bxeq lr
8000ae0: f043 4396 orr.w r3, r3, #1258291200 @ 0x4b000000
8000ae4: 4601 mov r1, r0
8000ae6: f04f 0000 mov.w r0, #0
8000aea: e01c b.n 8000b26 <__aeabi_l2f+0x2a>
08000aec <__aeabi_ul2f>:
8000aec: ea50 0201 orrs.w r2, r0, r1
8000af0: bf08 it eq
8000af2: 4770 bxeq lr
8000af4: f04f 0300 mov.w r3, #0
8000af8: e00a b.n 8000b10 <__aeabi_l2f+0x14>
8000afa: bf00 nop
08000afc <__aeabi_l2f>:
8000afc: ea50 0201 orrs.w r2, r0, r1
8000b00: bf08 it eq
8000b02: 4770 bxeq lr
8000b04: f011 4300 ands.w r3, r1, #2147483648 @ 0x80000000
8000b08: d502 bpl.n 8000b10 <__aeabi_l2f+0x14>
8000b0a: 4240 negs r0, r0
8000b0c: eb61 0141 sbc.w r1, r1, r1, lsl #1
8000b10: ea5f 0c01 movs.w ip, r1
8000b14: bf02 ittt eq
8000b16: 4684 moveq ip, r0
8000b18: 4601 moveq r1, r0
8000b1a: 2000 moveq r0, #0
8000b1c: f043 43b6 orr.w r3, r3, #1526726656 @ 0x5b000000
8000b20: bf08 it eq
8000b22: f1a3 5380 subeq.w r3, r3, #268435456 @ 0x10000000
8000b26: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000
8000b2a: fabc f28c clz r2, ip
8000b2e: 3a08 subs r2, #8
8000b30: eba3 53c2 sub.w r3, r3, r2, lsl #23
8000b34: db10 blt.n 8000b58 <__aeabi_l2f+0x5c>
8000b36: fa01 fc02 lsl.w ip, r1, r2
8000b3a: 4463 add r3, ip
8000b3c: fa00 fc02 lsl.w ip, r0, r2
8000b40: f1c2 0220 rsb r2, r2, #32
8000b44: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
8000b48: fa20 f202 lsr.w r2, r0, r2
8000b4c: eb43 0002 adc.w r0, r3, r2
8000b50: bf08 it eq
8000b52: f020 0001 biceq.w r0, r0, #1
8000b56: 4770 bx lr
8000b58: f102 0220 add.w r2, r2, #32
8000b5c: fa01 fc02 lsl.w ip, r1, r2
8000b60: f1c2 0220 rsb r2, r2, #32
8000b64: ea50 004c orrs.w r0, r0, ip, lsl #1
8000b68: fa21 f202 lsr.w r2, r1, r2
8000b6c: eb43 0002 adc.w r0, r3, r2
8000b70: bf08 it eq
8000b72: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000b76: 4770 bx lr
08000b78 <__aeabi_fmul>:
8000b78: f04f 0cff mov.w ip, #255 @ 0xff
8000b7c: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000b80: bf1e ittt ne
8000b82: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000b86: ea92 0f0c teqne r2, ip
8000b8a: ea93 0f0c teqne r3, ip
8000b8e: d06f beq.n 8000c70 <__aeabi_fmul+0xf8>
8000b90: 441a add r2, r3
8000b92: ea80 0c01 eor.w ip, r0, r1
8000b96: 0240 lsls r0, r0, #9
8000b98: bf18 it ne
8000b9a: ea5f 2141 movsne.w r1, r1, lsl #9
8000b9e: d01e beq.n 8000bde <__aeabi_fmul+0x66>
8000ba0: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8000ba4: ea43 1050 orr.w r0, r3, r0, lsr #5
8000ba8: ea43 1151 orr.w r1, r3, r1, lsr #5
8000bac: fba0 3101 umull r3, r1, r0, r1
8000bb0: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000bb4: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000
8000bb8: bf3e ittt cc
8000bba: 0049 lslcc r1, r1, #1
8000bbc: ea41 71d3 orrcc.w r1, r1, r3, lsr #31
8000bc0: 005b lslcc r3, r3, #1
8000bc2: ea40 0001 orr.w r0, r0, r1
8000bc6: f162 027f sbc.w r2, r2, #127 @ 0x7f
8000bca: 2afd cmp r2, #253 @ 0xfd
8000bcc: d81d bhi.n 8000c0a <__aeabi_fmul+0x92>
8000bce: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8000bd2: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000bd6: bf08 it eq
8000bd8: f020 0001 biceq.w r0, r0, #1
8000bdc: 4770 bx lr
8000bde: f090 0f00 teq r0, #0
8000be2: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000be6: bf08 it eq
8000be8: 0249 lsleq r1, r1, #9
8000bea: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000bee: ea40 2051 orr.w r0, r0, r1, lsr #9
8000bf2: 3a7f subs r2, #127 @ 0x7f
8000bf4: bfc2 ittt gt
8000bf6: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000bfa: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000bfe: 4770 bxgt lr
8000c00: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000c04: f04f 0300 mov.w r3, #0
8000c08: 3a01 subs r2, #1
8000c0a: dc5d bgt.n 8000cc8 <__aeabi_fmul+0x150>
8000c0c: f112 0f19 cmn.w r2, #25
8000c10: bfdc itt le
8000c12: f000 4000 andle.w r0, r0, #2147483648 @ 0x80000000
8000c16: 4770 bxle lr
8000c18: f1c2 0200 rsb r2, r2, #0
8000c1c: 0041 lsls r1, r0, #1
8000c1e: fa21 f102 lsr.w r1, r1, r2
8000c22: f1c2 0220 rsb r2, r2, #32
8000c26: fa00 fc02 lsl.w ip, r0, r2
8000c2a: ea5f 0031 movs.w r0, r1, rrx
8000c2e: f140 0000 adc.w r0, r0, #0
8000c32: ea53 034c orrs.w r3, r3, ip, lsl #1
8000c36: bf08 it eq
8000c38: ea20 70dc biceq.w r0, r0, ip, lsr #31
8000c3c: 4770 bx lr
8000c3e: f092 0f00 teq r2, #0
8000c42: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000c46: bf02 ittt eq
8000c48: 0040 lsleq r0, r0, #1
8000c4a: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000c4e: 3a01 subeq r2, #1
8000c50: d0f9 beq.n 8000c46 <__aeabi_fmul+0xce>
8000c52: ea40 000c orr.w r0, r0, ip
8000c56: f093 0f00 teq r3, #0
8000c5a: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000c5e: bf02 ittt eq
8000c60: 0049 lsleq r1, r1, #1
8000c62: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000c66: 3b01 subeq r3, #1
8000c68: d0f9 beq.n 8000c5e <__aeabi_fmul+0xe6>
8000c6a: ea41 010c orr.w r1, r1, ip
8000c6e: e78f b.n 8000b90 <__aeabi_fmul+0x18>
8000c70: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000c74: ea92 0f0c teq r2, ip
8000c78: bf18 it ne
8000c7a: ea93 0f0c teqne r3, ip
8000c7e: d00a beq.n 8000c96 <__aeabi_fmul+0x11e>
8000c80: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000c84: bf18 it ne
8000c86: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000c8a: d1d8 bne.n 8000c3e <__aeabi_fmul+0xc6>
8000c8c: ea80 0001 eor.w r0, r0, r1
8000c90: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000c94: 4770 bx lr
8000c96: f090 0f00 teq r0, #0
8000c9a: bf17 itett ne
8000c9c: f090 4f00 teqne r0, #2147483648 @ 0x80000000
8000ca0: 4608 moveq r0, r1
8000ca2: f091 0f00 teqne r1, #0
8000ca6: f091 4f00 teqne r1, #2147483648 @ 0x80000000
8000caa: d014 beq.n 8000cd6 <__aeabi_fmul+0x15e>
8000cac: ea92 0f0c teq r2, ip
8000cb0: d101 bne.n 8000cb6 <__aeabi_fmul+0x13e>
8000cb2: 0242 lsls r2, r0, #9
8000cb4: d10f bne.n 8000cd6 <__aeabi_fmul+0x15e>
8000cb6: ea93 0f0c teq r3, ip
8000cba: d103 bne.n 8000cc4 <__aeabi_fmul+0x14c>
8000cbc: 024b lsls r3, r1, #9
8000cbe: bf18 it ne
8000cc0: 4608 movne r0, r1
8000cc2: d108 bne.n 8000cd6 <__aeabi_fmul+0x15e>
8000cc4: ea80 0001 eor.w r0, r0, r1
8000cc8: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000
8000ccc: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000cd0: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000cd4: 4770 bx lr
8000cd6: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
8000cda: f440 0040 orr.w r0, r0, #12582912 @ 0xc00000
8000cde: 4770 bx lr
08000ce0 <__aeabi_fdiv>:
8000ce0: f04f 0cff mov.w ip, #255 @ 0xff
8000ce4: ea1c 52d0 ands.w r2, ip, r0, lsr #23
8000ce8: bf1e ittt ne
8000cea: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
8000cee: ea92 0f0c teqne r2, ip
8000cf2: ea93 0f0c teqne r3, ip
8000cf6: d069 beq.n 8000dcc <__aeabi_fdiv+0xec>
8000cf8: eba2 0203 sub.w r2, r2, r3
8000cfc: ea80 0c01 eor.w ip, r0, r1
8000d00: 0249 lsls r1, r1, #9
8000d02: ea4f 2040 mov.w r0, r0, lsl #9
8000d06: d037 beq.n 8000d78 <__aeabi_fdiv+0x98>
8000d08: f04f 5380 mov.w r3, #268435456 @ 0x10000000
8000d0c: ea43 1111 orr.w r1, r3, r1, lsr #4
8000d10: ea43 1310 orr.w r3, r3, r0, lsr #4
8000d14: f00c 4000 and.w r0, ip, #2147483648 @ 0x80000000
8000d18: 428b cmp r3, r1
8000d1a: bf38 it cc
8000d1c: 005b lslcc r3, r3, #1
8000d1e: f142 027d adc.w r2, r2, #125 @ 0x7d
8000d22: f44f 0c00 mov.w ip, #8388608 @ 0x800000
8000d26: 428b cmp r3, r1
8000d28: bf24 itt cs
8000d2a: 1a5b subcs r3, r3, r1
8000d2c: ea40 000c orrcs.w r0, r0, ip
8000d30: ebb3 0f51 cmp.w r3, r1, lsr #1
8000d34: bf24 itt cs
8000d36: eba3 0351 subcs.w r3, r3, r1, lsr #1
8000d3a: ea40 005c orrcs.w r0, r0, ip, lsr #1
8000d3e: ebb3 0f91 cmp.w r3, r1, lsr #2
8000d42: bf24 itt cs
8000d44: eba3 0391 subcs.w r3, r3, r1, lsr #2
8000d48: ea40 009c orrcs.w r0, r0, ip, lsr #2
8000d4c: ebb3 0fd1 cmp.w r3, r1, lsr #3
8000d50: bf24 itt cs
8000d52: eba3 03d1 subcs.w r3, r3, r1, lsr #3
8000d56: ea40 00dc orrcs.w r0, r0, ip, lsr #3
8000d5a: 011b lsls r3, r3, #4
8000d5c: bf18 it ne
8000d5e: ea5f 1c1c movsne.w ip, ip, lsr #4
8000d62: d1e0 bne.n 8000d26 <__aeabi_fdiv+0x46>
8000d64: 2afd cmp r2, #253 @ 0xfd
8000d66: f63f af50 bhi.w 8000c0a <__aeabi_fmul+0x92>
8000d6a: 428b cmp r3, r1
8000d6c: eb40 50c2 adc.w r0, r0, r2, lsl #23
8000d70: bf08 it eq
8000d72: f020 0001 biceq.w r0, r0, #1
8000d76: 4770 bx lr
8000d78: f00c 4c00 and.w ip, ip, #2147483648 @ 0x80000000
8000d7c: ea4c 2050 orr.w r0, ip, r0, lsr #9
8000d80: 327f adds r2, #127 @ 0x7f
8000d82: bfc2 ittt gt
8000d84: f1d2 03ff rsbsgt r3, r2, #255 @ 0xff
8000d88: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
8000d8c: 4770 bxgt lr
8000d8e: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
8000d92: f04f 0300 mov.w r3, #0
8000d96: 3a01 subs r2, #1
8000d98: e737 b.n 8000c0a <__aeabi_fmul+0x92>
8000d9a: f092 0f00 teq r2, #0
8000d9e: f000 4c00 and.w ip, r0, #2147483648 @ 0x80000000
8000da2: bf02 ittt eq
8000da4: 0040 lsleq r0, r0, #1
8000da6: f410 0f00 tsteq.w r0, #8388608 @ 0x800000
8000daa: 3a01 subeq r2, #1
8000dac: d0f9 beq.n 8000da2 <__aeabi_fdiv+0xc2>
8000dae: ea40 000c orr.w r0, r0, ip
8000db2: f093 0f00 teq r3, #0
8000db6: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
8000dba: bf02 ittt eq
8000dbc: 0049 lsleq r1, r1, #1
8000dbe: f411 0f00 tsteq.w r1, #8388608 @ 0x800000
8000dc2: 3b01 subeq r3, #1
8000dc4: d0f9 beq.n 8000dba <__aeabi_fdiv+0xda>
8000dc6: ea41 010c orr.w r1, r1, ip
8000dca: e795 b.n 8000cf8 <__aeabi_fdiv+0x18>
8000dcc: ea0c 53d1 and.w r3, ip, r1, lsr #23
8000dd0: ea92 0f0c teq r2, ip
8000dd4: d108 bne.n 8000de8 <__aeabi_fdiv+0x108>
8000dd6: 0242 lsls r2, r0, #9
8000dd8: f47f af7d bne.w 8000cd6 <__aeabi_fmul+0x15e>
8000ddc: ea93 0f0c teq r3, ip
8000de0: f47f af70 bne.w 8000cc4 <__aeabi_fmul+0x14c>
8000de4: 4608 mov r0, r1
8000de6: e776 b.n 8000cd6 <__aeabi_fmul+0x15e>
8000de8: ea93 0f0c teq r3, ip
8000dec: d104 bne.n 8000df8 <__aeabi_fdiv+0x118>
8000dee: 024b lsls r3, r1, #9
8000df0: f43f af4c beq.w 8000c8c <__aeabi_fmul+0x114>
8000df4: 4608 mov r0, r1
8000df6: e76e b.n 8000cd6 <__aeabi_fmul+0x15e>
8000df8: f030 4c00 bics.w ip, r0, #2147483648 @ 0x80000000
8000dfc: bf18 it ne
8000dfe: f031 4c00 bicsne.w ip, r1, #2147483648 @ 0x80000000
8000e02: d1ca bne.n 8000d9a <__aeabi_fdiv+0xba>
8000e04: f030 4200 bics.w r2, r0, #2147483648 @ 0x80000000
8000e08: f47f af5c bne.w 8000cc4 <__aeabi_fmul+0x14c>
8000e0c: f031 4300 bics.w r3, r1, #2147483648 @ 0x80000000
8000e10: f47f af3c bne.w 8000c8c <__aeabi_fmul+0x114>
8000e14: e75f b.n 8000cd6 <__aeabi_fmul+0x15e>
8000e16: bf00 nop
08000e18 <__aeabi_f2uiz>:
8000e18: 0042 lsls r2, r0, #1
8000e1a: d20e bcs.n 8000e3a <__aeabi_f2uiz+0x22>
8000e1c: f1b2 4ffe cmp.w r2, #2130706432 @ 0x7f000000
8000e20: d30b bcc.n 8000e3a <__aeabi_f2uiz+0x22>
8000e22: f04f 039e mov.w r3, #158 @ 0x9e
8000e26: ebb3 6212 subs.w r2, r3, r2, lsr #24
8000e2a: d409 bmi.n 8000e40 <__aeabi_f2uiz+0x28>
8000e2c: ea4f 2300 mov.w r3, r0, lsl #8
8000e30: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000e34: fa23 f002 lsr.w r0, r3, r2
8000e38: 4770 bx lr
8000e3a: f04f 0000 mov.w r0, #0
8000e3e: 4770 bx lr
8000e40: f112 0f61 cmn.w r2, #97 @ 0x61
8000e44: d101 bne.n 8000e4a <__aeabi_f2uiz+0x32>
8000e46: 0242 lsls r2, r0, #9
8000e48: d102 bne.n 8000e50 <__aeabi_f2uiz+0x38>
8000e4a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000e4e: 4770 bx lr
8000e50: f04f 0000 mov.w r0, #0
8000e54: 4770 bx lr
8000e56: bf00 nop
08000e58 <__aeabi_uldivmod>:
8000e58: b953 cbnz r3, 8000e70 <__aeabi_uldivmod+0x18>
8000e5a: b94a cbnz r2, 8000e70 <__aeabi_uldivmod+0x18>
8000e5c: 2900 cmp r1, #0
8000e5e: bf08 it eq
8000e60: 2800 cmpeq r0, #0
8000e62: bf1c itt ne
8000e64: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
8000e68: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
8000e6c: f000 b98c b.w 8001188 <__aeabi_idiv0>
8000e70: f1ad 0c08 sub.w ip, sp, #8
8000e74: e96d ce04 strd ip, lr, [sp, #-16]!
8000e78: f000 f806 bl 8000e88 <__udivmoddi4>
8000e7c: f8dd e004 ldr.w lr, [sp, #4]
8000e80: e9dd 2302 ldrd r2, r3, [sp, #8]
8000e84: b004 add sp, #16
8000e86: 4770 bx lr
08000e88 <__udivmoddi4>:
8000e88: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000e8c: 9d08 ldr r5, [sp, #32]
8000e8e: 468e mov lr, r1
8000e90: 4604 mov r4, r0
8000e92: 4688 mov r8, r1
8000e94: 2b00 cmp r3, #0
8000e96: d14a bne.n 8000f2e <__udivmoddi4+0xa6>
8000e98: 428a cmp r2, r1
8000e9a: 4617 mov r7, r2
8000e9c: d962 bls.n 8000f64 <__udivmoddi4+0xdc>
8000e9e: fab2 f682 clz r6, r2
8000ea2: b14e cbz r6, 8000eb8 <__udivmoddi4+0x30>
8000ea4: f1c6 0320 rsb r3, r6, #32
8000ea8: fa01 f806 lsl.w r8, r1, r6
8000eac: fa20 f303 lsr.w r3, r0, r3
8000eb0: 40b7 lsls r7, r6
8000eb2: ea43 0808 orr.w r8, r3, r8
8000eb6: 40b4 lsls r4, r6
8000eb8: ea4f 4e17 mov.w lr, r7, lsr #16
8000ebc: fbb8 f1fe udiv r1, r8, lr
8000ec0: fa1f fc87 uxth.w ip, r7
8000ec4: fb0e 8811 mls r8, lr, r1, r8
8000ec8: fb01 f20c mul.w r2, r1, ip
8000ecc: 0c23 lsrs r3, r4, #16
8000ece: ea43 4308 orr.w r3, r3, r8, lsl #16
8000ed2: 429a cmp r2, r3
8000ed4: d909 bls.n 8000eea <__udivmoddi4+0x62>
8000ed6: 18fb adds r3, r7, r3
8000ed8: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000edc: f080 80eb bcs.w 80010b6 <__udivmoddi4+0x22e>
8000ee0: 429a cmp r2, r3
8000ee2: f240 80e8 bls.w 80010b6 <__udivmoddi4+0x22e>
8000ee6: 3902 subs r1, #2
8000ee8: 443b add r3, r7
8000eea: 1a9a subs r2, r3, r2
8000eec: fbb2 f0fe udiv r0, r2, lr
8000ef0: fb0e 2210 mls r2, lr, r0, r2
8000ef4: fb00 fc0c mul.w ip, r0, ip
8000ef8: b2a3 uxth r3, r4
8000efa: ea43 4302 orr.w r3, r3, r2, lsl #16
8000efe: 459c cmp ip, r3
8000f00: d909 bls.n 8000f16 <__udivmoddi4+0x8e>
8000f02: 18fb adds r3, r7, r3
8000f04: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
8000f08: f080 80d7 bcs.w 80010ba <__udivmoddi4+0x232>
8000f0c: 459c cmp ip, r3
8000f0e: f240 80d4 bls.w 80010ba <__udivmoddi4+0x232>
8000f12: 443b add r3, r7
8000f14: 3802 subs r0, #2
8000f16: ea40 4001 orr.w r0, r0, r1, lsl #16
8000f1a: 2100 movs r1, #0
8000f1c: eba3 030c sub.w r3, r3, ip
8000f20: b11d cbz r5, 8000f2a <__udivmoddi4+0xa2>
8000f22: 2200 movs r2, #0
8000f24: 40f3 lsrs r3, r6
8000f26: e9c5 3200 strd r3, r2, [r5]
8000f2a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000f2e: 428b cmp r3, r1
8000f30: d905 bls.n 8000f3e <__udivmoddi4+0xb6>
8000f32: b10d cbz r5, 8000f38 <__udivmoddi4+0xb0>
8000f34: e9c5 0100 strd r0, r1, [r5]
8000f38: 2100 movs r1, #0
8000f3a: 4608 mov r0, r1
8000f3c: e7f5 b.n 8000f2a <__udivmoddi4+0xa2>
8000f3e: fab3 f183 clz r1, r3
8000f42: 2900 cmp r1, #0
8000f44: d146 bne.n 8000fd4 <__udivmoddi4+0x14c>
8000f46: 4573 cmp r3, lr
8000f48: d302 bcc.n 8000f50 <__udivmoddi4+0xc8>
8000f4a: 4282 cmp r2, r0
8000f4c: f200 8108 bhi.w 8001160 <__udivmoddi4+0x2d8>
8000f50: 1a84 subs r4, r0, r2
8000f52: eb6e 0203 sbc.w r2, lr, r3
8000f56: 2001 movs r0, #1
8000f58: 4690 mov r8, r2
8000f5a: 2d00 cmp r5, #0
8000f5c: d0e5 beq.n 8000f2a <__udivmoddi4+0xa2>
8000f5e: e9c5 4800 strd r4, r8, [r5]
8000f62: e7e2 b.n 8000f2a <__udivmoddi4+0xa2>
8000f64: 2a00 cmp r2, #0
8000f66: f000 8091 beq.w 800108c <__udivmoddi4+0x204>
8000f6a: fab2 f682 clz r6, r2
8000f6e: 2e00 cmp r6, #0
8000f70: f040 80a5 bne.w 80010be <__udivmoddi4+0x236>
8000f74: 1a8a subs r2, r1, r2
8000f76: 2101 movs r1, #1
8000f78: 0c03 lsrs r3, r0, #16
8000f7a: ea4f 4e17 mov.w lr, r7, lsr #16
8000f7e: b280 uxth r0, r0
8000f80: b2bc uxth r4, r7
8000f82: fbb2 fcfe udiv ip, r2, lr
8000f86: fb0e 221c mls r2, lr, ip, r2
8000f8a: ea43 4302 orr.w r3, r3, r2, lsl #16
8000f8e: fb04 f20c mul.w r2, r4, ip
8000f92: 429a cmp r2, r3
8000f94: d907 bls.n 8000fa6 <__udivmoddi4+0x11e>
8000f96: 18fb adds r3, r7, r3
8000f98: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
8000f9c: d202 bcs.n 8000fa4 <__udivmoddi4+0x11c>
8000f9e: 429a cmp r2, r3
8000fa0: f200 80e3 bhi.w 800116a <__udivmoddi4+0x2e2>
8000fa4: 46c4 mov ip, r8
8000fa6: 1a9b subs r3, r3, r2
8000fa8: fbb3 f2fe udiv r2, r3, lr
8000fac: fb0e 3312 mls r3, lr, r2, r3
8000fb0: fb02 f404 mul.w r4, r2, r4
8000fb4: ea40 4303 orr.w r3, r0, r3, lsl #16
8000fb8: 429c cmp r4, r3
8000fba: d907 bls.n 8000fcc <__udivmoddi4+0x144>
8000fbc: 18fb adds r3, r7, r3
8000fbe: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
8000fc2: d202 bcs.n 8000fca <__udivmoddi4+0x142>
8000fc4: 429c cmp r4, r3
8000fc6: f200 80cd bhi.w 8001164 <__udivmoddi4+0x2dc>
8000fca: 4602 mov r2, r0
8000fcc: 1b1b subs r3, r3, r4
8000fce: ea42 400c orr.w r0, r2, ip, lsl #16
8000fd2: e7a5 b.n 8000f20 <__udivmoddi4+0x98>
8000fd4: f1c1 0620 rsb r6, r1, #32
8000fd8: 408b lsls r3, r1
8000fda: fa22 f706 lsr.w r7, r2, r6
8000fde: 431f orrs r7, r3
8000fe0: fa2e fa06 lsr.w sl, lr, r6
8000fe4: ea4f 4917 mov.w r9, r7, lsr #16
8000fe8: fbba f8f9 udiv r8, sl, r9
8000fec: fa0e fe01 lsl.w lr, lr, r1
8000ff0: fa20 f306 lsr.w r3, r0, r6
8000ff4: fb09 aa18 mls sl, r9, r8, sl
8000ff8: fa1f fc87 uxth.w ip, r7
8000ffc: ea43 030e orr.w r3, r3, lr
8001000: fa00 fe01 lsl.w lr, r0, r1
8001004: fb08 f00c mul.w r0, r8, ip
8001008: 0c1c lsrs r4, r3, #16
800100a: ea44 440a orr.w r4, r4, sl, lsl #16
800100e: 42a0 cmp r0, r4
8001010: fa02 f201 lsl.w r2, r2, r1
8001014: d90a bls.n 800102c <__udivmoddi4+0x1a4>
8001016: 193c adds r4, r7, r4
8001018: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff
800101c: f080 809e bcs.w 800115c <__udivmoddi4+0x2d4>
8001020: 42a0 cmp r0, r4
8001022: f240 809b bls.w 800115c <__udivmoddi4+0x2d4>
8001026: f1a8 0802 sub.w r8, r8, #2
800102a: 443c add r4, r7
800102c: 1a24 subs r4, r4, r0
800102e: b298 uxth r0, r3
8001030: fbb4 f3f9 udiv r3, r4, r9
8001034: fb09 4413 mls r4, r9, r3, r4
8001038: fb03 fc0c mul.w ip, r3, ip
800103c: ea40 4404 orr.w r4, r0, r4, lsl #16
8001040: 45a4 cmp ip, r4
8001042: d909 bls.n 8001058 <__udivmoddi4+0x1d0>
8001044: 193c adds r4, r7, r4
8001046: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff
800104a: f080 8085 bcs.w 8001158 <__udivmoddi4+0x2d0>
800104e: 45a4 cmp ip, r4
8001050: f240 8082 bls.w 8001158 <__udivmoddi4+0x2d0>
8001054: 3b02 subs r3, #2
8001056: 443c add r4, r7
8001058: ea43 4008 orr.w r0, r3, r8, lsl #16
800105c: eba4 040c sub.w r4, r4, ip
8001060: fba0 8c02 umull r8, ip, r0, r2
8001064: 4564 cmp r4, ip
8001066: 4643 mov r3, r8
8001068: 46e1 mov r9, ip
800106a: d364 bcc.n 8001136 <__udivmoddi4+0x2ae>
800106c: d061 beq.n 8001132 <__udivmoddi4+0x2aa>
800106e: b15d cbz r5, 8001088 <__udivmoddi4+0x200>
8001070: ebbe 0203 subs.w r2, lr, r3
8001074: eb64 0409 sbc.w r4, r4, r9
8001078: fa04 f606 lsl.w r6, r4, r6
800107c: fa22 f301 lsr.w r3, r2, r1
8001080: 431e orrs r6, r3
8001082: 40cc lsrs r4, r1
8001084: e9c5 6400 strd r6, r4, [r5]
8001088: 2100 movs r1, #0
800108a: e74e b.n 8000f2a <__udivmoddi4+0xa2>
800108c: fbb1 fcf2 udiv ip, r1, r2
8001090: 0c01 lsrs r1, r0, #16
8001092: ea41 410e orr.w r1, r1, lr, lsl #16
8001096: b280 uxth r0, r0
8001098: ea40 4201 orr.w r2, r0, r1, lsl #16
800109c: 463b mov r3, r7
800109e: fbb1 f1f7 udiv r1, r1, r7
80010a2: 4638 mov r0, r7
80010a4: 463c mov r4, r7
80010a6: 46b8 mov r8, r7
80010a8: 46be mov lr, r7
80010aa: 2620 movs r6, #32
80010ac: eba2 0208 sub.w r2, r2, r8
80010b0: ea41 410c orr.w r1, r1, ip, lsl #16
80010b4: e765 b.n 8000f82 <__udivmoddi4+0xfa>
80010b6: 4601 mov r1, r0
80010b8: e717 b.n 8000eea <__udivmoddi4+0x62>
80010ba: 4610 mov r0, r2
80010bc: e72b b.n 8000f16 <__udivmoddi4+0x8e>
80010be: f1c6 0120 rsb r1, r6, #32
80010c2: fa2e fc01 lsr.w ip, lr, r1
80010c6: 40b7 lsls r7, r6
80010c8: fa0e fe06 lsl.w lr, lr, r6
80010cc: fa20 f101 lsr.w r1, r0, r1
80010d0: ea41 010e orr.w r1, r1, lr
80010d4: ea4f 4e17 mov.w lr, r7, lsr #16
80010d8: fbbc f8fe udiv r8, ip, lr
80010dc: b2bc uxth r4, r7
80010de: fb0e cc18 mls ip, lr, r8, ip
80010e2: fb08 f904 mul.w r9, r8, r4
80010e6: 0c0a lsrs r2, r1, #16
80010e8: ea42 420c orr.w r2, r2, ip, lsl #16
80010ec: 40b0 lsls r0, r6
80010ee: 4591 cmp r9, r2
80010f0: ea4f 4310 mov.w r3, r0, lsr #16
80010f4: b280 uxth r0, r0
80010f6: d93e bls.n 8001176 <__udivmoddi4+0x2ee>
80010f8: 18ba adds r2, r7, r2
80010fa: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
80010fe: d201 bcs.n 8001104 <__udivmoddi4+0x27c>
8001100: 4591 cmp r9, r2
8001102: d81f bhi.n 8001144 <__udivmoddi4+0x2bc>
8001104: eba2 0209 sub.w r2, r2, r9
8001108: fbb2 f9fe udiv r9, r2, lr
800110c: fb09 f804 mul.w r8, r9, r4
8001110: fb0e 2a19 mls sl, lr, r9, r2
8001114: b28a uxth r2, r1
8001116: ea42 420a orr.w r2, r2, sl, lsl #16
800111a: 4542 cmp r2, r8
800111c: d229 bcs.n 8001172 <__udivmoddi4+0x2ea>
800111e: 18ba adds r2, r7, r2
8001120: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8001124: d2c2 bcs.n 80010ac <__udivmoddi4+0x224>
8001126: 4542 cmp r2, r8
8001128: d2c0 bcs.n 80010ac <__udivmoddi4+0x224>
800112a: f1a9 0102 sub.w r1, r9, #2
800112e: 443a add r2, r7
8001130: e7bc b.n 80010ac <__udivmoddi4+0x224>
8001132: 45c6 cmp lr, r8
8001134: d29b bcs.n 800106e <__udivmoddi4+0x1e6>
8001136: ebb8 0302 subs.w r3, r8, r2
800113a: eb6c 0c07 sbc.w ip, ip, r7
800113e: 3801 subs r0, #1
8001140: 46e1 mov r9, ip
8001142: e794 b.n 800106e <__udivmoddi4+0x1e6>
8001144: eba7 0909 sub.w r9, r7, r9
8001148: 444a add r2, r9
800114a: fbb2 f9fe udiv r9, r2, lr
800114e: f1a8 0c02 sub.w ip, r8, #2
8001152: fb09 f804 mul.w r8, r9, r4
8001156: e7db b.n 8001110 <__udivmoddi4+0x288>
8001158: 4603 mov r3, r0
800115a: e77d b.n 8001058 <__udivmoddi4+0x1d0>
800115c: 46d0 mov r8, sl
800115e: e765 b.n 800102c <__udivmoddi4+0x1a4>
8001160: 4608 mov r0, r1
8001162: e6fa b.n 8000f5a <__udivmoddi4+0xd2>
8001164: 443b add r3, r7
8001166: 3a02 subs r2, #2
8001168: e730 b.n 8000fcc <__udivmoddi4+0x144>
800116a: f1ac 0c02 sub.w ip, ip, #2
800116e: 443b add r3, r7
8001170: e719 b.n 8000fa6 <__udivmoddi4+0x11e>
8001172: 4649 mov r1, r9
8001174: e79a b.n 80010ac <__udivmoddi4+0x224>
8001176: eba2 0209 sub.w r2, r2, r9
800117a: fbb2 f9fe udiv r9, r2, lr
800117e: 46c4 mov ip, r8
8001180: fb09 f804 mul.w r8, r9, r4
8001184: e7c4 b.n 8001110 <__udivmoddi4+0x288>
8001186: bf00 nop
08001188 <__aeabi_idiv0>:
8001188: 4770 bx lr
800118a: bf00 nop
0800118c <affiche_nombre>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void affiche_nombre(uint32_t nombre, uint8_t col, uint8_t ligne) {
800118c: b580 push {r7, lr}
800118e: b086 sub sp, #24
8001190: af02 add r7, sp, #8
8001192: 6078 str r0, [r7, #4]
8001194: 460b mov r3, r1
8001196: 70fb strb r3, [r7, #3]
8001198: 4613 mov r3, r2
800119a: 70bb strb r3, [r7, #2]
if (nombre < 0 || nombre > 9999) {
800119c: 687b ldr r3, [r7, #4]
800119e: f242 720f movw r2, #9999 @ 0x270f
80011a2: 4293 cmp r3, r2
80011a4: f200 8093 bhi.w 80012ce <affiche_nombre+0x142>
return;
}
uint8_t mil = nombre / 1000;
80011a8: 687b ldr r3, [r7, #4]
80011aa: 4a4b ldr r2, [pc, #300] @ (80012d8 <affiche_nombre+0x14c>)
80011ac: fba2 2303 umull r2, r3, r2, r3
80011b0: 099b lsrs r3, r3, #6
80011b2: 73fb strb r3, [r7, #15]
uint8_t cen = (nombre / 100) % 10;
80011b4: 687b ldr r3, [r7, #4]
80011b6: 4a49 ldr r2, [pc, #292] @ (80012dc <affiche_nombre+0x150>)
80011b8: fba2 2303 umull r2, r3, r2, r3
80011bc: 0959 lsrs r1, r3, #5
80011be: 4b48 ldr r3, [pc, #288] @ (80012e0 <affiche_nombre+0x154>)
80011c0: fba3 2301 umull r2, r3, r3, r1
80011c4: 08da lsrs r2, r3, #3
80011c6: 4613 mov r3, r2
80011c8: 009b lsls r3, r3, #2
80011ca: 4413 add r3, r2
80011cc: 005b lsls r3, r3, #1
80011ce: 1aca subs r2, r1, r3
80011d0: 4613 mov r3, r2
80011d2: 73bb strb r3, [r7, #14]
uint8_t diz = (nombre / 10) % 10;
80011d4: 687b ldr r3, [r7, #4]
80011d6: 4a42 ldr r2, [pc, #264] @ (80012e0 <affiche_nombre+0x154>)
80011d8: fba2 2303 umull r2, r3, r2, r3
80011dc: 08d9 lsrs r1, r3, #3
80011de: 4b40 ldr r3, [pc, #256] @ (80012e0 <affiche_nombre+0x154>)
80011e0: fba3 2301 umull r2, r3, r3, r1
80011e4: 08da lsrs r2, r3, #3
80011e6: 4613 mov r3, r2
80011e8: 009b lsls r3, r3, #2
80011ea: 4413 add r3, r2
80011ec: 005b lsls r3, r3, #1
80011ee: 1aca subs r2, r1, r3
80011f0: 4613 mov r3, r2
80011f2: 737b strb r3, [r7, #13]
uint8_t uni = nombre % 10;
80011f4: 6879 ldr r1, [r7, #4]
80011f6: 4b3a ldr r3, [pc, #232] @ (80012e0 <affiche_nombre+0x154>)
80011f8: fba3 2301 umull r2, r3, r3, r1
80011fc: 08da lsrs r2, r3, #3
80011fe: 4613 mov r3, r2
8001200: 009b lsls r3, r3, #2
8001202: 4413 add r3, r2
8001204: 005b lsls r3, r3, #1
8001206: 1aca subs r2, r1, r3
8001208: 4613 mov r3, r2
800120a: 733b strb r3, [r7, #12]
displayChar_TFT(col, ligne, mil + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
800120c: 78fb ldrb r3, [r7, #3]
800120e: b298 uxth r0, r3
8001210: 78bb ldrb r3, [r7, #2]
8001212: b299 uxth r1, r3
8001214: 7bfb ldrb r3, [r7, #15]
8001216: 3330 adds r3, #48 @ 0x30
8001218: b2da uxtb r2, r3
800121a: 2302 movs r3, #2
800121c: 9301 str r3, [sp, #4]
800121e: 2300 movs r3, #0
8001220: 9300 str r3, [sp, #0]
8001222: f64f 73e0 movw r3, #65504 @ 0xffe0
8001226: f002 fd7b bl 8003d20 <displayChar_TFT>
displayChar_TFT(col + 12, ligne, cen + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
800122a: 78fb ldrb r3, [r7, #3]
800122c: b29b uxth r3, r3
800122e: 330c adds r3, #12
8001230: b298 uxth r0, r3
8001232: 78bb ldrb r3, [r7, #2]
8001234: b299 uxth r1, r3
8001236: 7bbb ldrb r3, [r7, #14]
8001238: 3330 adds r3, #48 @ 0x30
800123a: b2da uxtb r2, r3
800123c: 2302 movs r3, #2
800123e: 9301 str r3, [sp, #4]
8001240: 2300 movs r3, #0
8001242: 9300 str r3, [sp, #0]
8001244: f64f 73e0 movw r3, #65504 @ 0xffe0
8001248: f002 fd6a bl 8003d20 <displayChar_TFT>
displayChar_TFT(col + 24, ligne, diz + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
800124c: 78fb ldrb r3, [r7, #3]
800124e: b29b uxth r3, r3
8001250: 3318 adds r3, #24
8001252: b298 uxth r0, r3
8001254: 78bb ldrb r3, [r7, #2]
8001256: b299 uxth r1, r3
8001258: 7b7b ldrb r3, [r7, #13]
800125a: 3330 adds r3, #48 @ 0x30
800125c: b2da uxtb r2, r3
800125e: 2302 movs r3, #2
8001260: 9301 str r3, [sp, #4]
8001262: 2300 movs r3, #0
8001264: 9300 str r3, [sp, #0]
8001266: f64f 73e0 movw r3, #65504 @ 0xffe0
800126a: f002 fd59 bl 8003d20 <displayChar_TFT>
displayChar_TFT(col + 36, ligne, uni + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
800126e: 78fb ldrb r3, [r7, #3]
8001270: b29b uxth r3, r3
8001272: 3324 adds r3, #36 @ 0x24
8001274: b298 uxth r0, r3
8001276: 78bb ldrb r3, [r7, #2]
8001278: b299 uxth r1, r3
800127a: 7b3b ldrb r3, [r7, #12]
800127c: 3330 adds r3, #48 @ 0x30
800127e: b2da uxtb r2, r3
8001280: 2302 movs r3, #2
8001282: 9301 str r3, [sp, #4]
8001284: 2300 movs r3, #0
8001286: 9300 str r3, [sp, #0]
8001288: f64f 73e0 movw r3, #65504 @ 0xffe0
800128c: f002 fd48 bl 8003d20 <displayChar_TFT>
displayChar_TFT(col + 48, ligne, ' ', ST7735_YELLOW, ST7735_BLACK, 2);
8001290: 78fb ldrb r3, [r7, #3]
8001292: b29b uxth r3, r3
8001294: 3330 adds r3, #48 @ 0x30
8001296: b298 uxth r0, r3
8001298: 78bb ldrb r3, [r7, #2]
800129a: b299 uxth r1, r3
800129c: 2302 movs r3, #2
800129e: 9301 str r3, [sp, #4]
80012a0: 2300 movs r3, #0
80012a2: 9300 str r3, [sp, #0]
80012a4: f64f 73e0 movw r3, #65504 @ 0xffe0
80012a8: 2220 movs r2, #32
80012aa: f002 fd39 bl 8003d20 <displayChar_TFT>
displayChar_TFT(col + 60, ligne, 'C', ST7735_YELLOW, ST7735_BLACK, 2);
80012ae: 78fb ldrb r3, [r7, #3]
80012b0: b29b uxth r3, r3
80012b2: 333c adds r3, #60 @ 0x3c
80012b4: b298 uxth r0, r3
80012b6: 78bb ldrb r3, [r7, #2]
80012b8: b299 uxth r1, r3
80012ba: 2302 movs r3, #2
80012bc: 9301 str r3, [sp, #4]
80012be: 2300 movs r3, #0
80012c0: 9300 str r3, [sp, #0]
80012c2: f64f 73e0 movw r3, #65504 @ 0xffe0
80012c6: 2243 movs r2, #67 @ 0x43
80012c8: f002 fd2a bl 8003d20 <displayChar_TFT>
80012cc: e000 b.n 80012d0 <affiche_nombre+0x144>
return;
80012ce: bf00 nop
}
80012d0: 3710 adds r7, #16
80012d2: 46bd mov sp, r7
80012d4: bd80 pop {r7, pc}
80012d6: bf00 nop
80012d8: 10624dd3 .word 0x10624dd3
80012dc: 51eb851f .word 0x51eb851f
80012e0: cccccccd .word 0xcccccccd
80012e4: 00000000 .word 0x00000000
080012e8 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80012e8: b590 push {r4, r7, lr}
80012ea: b087 sub sp, #28
80012ec: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80012ee: f000 fb91 bl 8001a14 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80012f2: f000 f89b bl 800142c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80012f6: f000 f96d bl 80015d4 <MX_GPIO_Init>
MX_SPI1_Init();
80012fa: f000 f935 bl 8001568 <MX_SPI1_Init>
MX_ADC_Init();
80012fe: f000 f8db bl 80014b8 <MX_ADC_Init>
/* USER CODE BEGIN 2 */
MAX7219_Init();
8001302: f000 fb0a bl 800191a <MAX7219_Init>
init_TFT();
8001306: f002 fc01 bl 8003b0c <init_TFT>
MAX7219_Clear();
800130a: f000 fb3d bl 8001988 <MAX7219_Clear>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
const uint16_t TS_CAL1 = *(uint16_t*)0x1FF800FA;
800130e: 4b40 ldr r3, [pc, #256] @ (8001410 <main+0x128>)
8001310: 881b ldrh r3, [r3, #0]
8001312: 82fb strh r3, [r7, #22]
const uint16_t TS_CAL2 = *(uint16_t*)0x1FF800FE;
8001314: 4b3f ldr r3, [pc, #252] @ (8001414 <main+0x12c>)
8001316: 881b ldrh r3, [r3, #0]
8001318: 82bb strh r3, [r7, #20]
const uint16_t VREFINT_CAL = *(uint16_t*)0x1FF800F8;
800131a: 4b3f ldr r3, [pc, #252] @ (8001418 <main+0x130>)
800131c: 881b ldrh r3, [r3, #0]
800131e: 827b strh r3, [r7, #18]
const int32_t vrefint_value = 1210;
8001320: f240 43ba movw r3, #1210 @ 0x4ba
8001324: 60fb str r3, [r7, #12]
float vdda_div_3 = (float)VREFINT_CAL / vrefint_value;
8001326: 8a7b ldrh r3, [r7, #18]
8001328: 4618 mov r0, r3
800132a: f7ff fbcd bl 8000ac8 <__aeabi_ui2f>
800132e: 4604 mov r4, r0
8001330: 68f8 ldr r0, [r7, #12]
8001332: f7ff fbcd bl 8000ad0 <__aeabi_i2f>
8001336: 4603 mov r3, r0
8001338: 4619 mov r1, r3
800133a: 4620 mov r0, r4
800133c: f7ff fcd0 bl 8000ce0 <__aeabi_fdiv>
8001340: 4603 mov r3, r0
8001342: 60bb str r3, [r7, #8]
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
HAL_ADC_Start(&hadc);
8001344: 4835 ldr r0, [pc, #212] @ (800141c <main+0x134>)
8001346: f000 fd3b bl 8001dc0 <HAL_ADC_Start>
HAL_ADC_PollForConversion(&hadc, 1000);
800134a: f44f 717a mov.w r1, #1000 @ 0x3e8
800134e: 4833 ldr r0, [pc, #204] @ (800141c <main+0x134>)
8001350: f000 fdc2 bl 8001ed8 <HAL_ADC_PollForConversion>
uint32_t temp_value = (HAL_ADC_GetValue(&hadc) / 4096.0) * 3300;
8001354: 4831 ldr r0, [pc, #196] @ (800141c <main+0x134>)
8001356: f000 fe4f bl 8001ff8 <HAL_ADC_GetValue>
800135a: 4603 mov r3, r0
800135c: 4618 mov r0, r3
800135e: f7ff f851 bl 8000404 <__aeabi_ui2d>
8001362: f04f 0200 mov.w r2, #0
8001366: 4b2e ldr r3, [pc, #184] @ (8001420 <main+0x138>)
8001368: f7ff f9f0 bl 800074c <__aeabi_ddiv>
800136c: 4602 mov r2, r0
800136e: 460b mov r3, r1
8001370: 4610 mov r0, r2
8001372: 4619 mov r1, r3
8001374: a324 add r3, pc, #144 @ (adr r3, 8001408 <main+0x120>)
8001376: e9d3 2300 ldrd r2, r3, [r3]
800137a: f7ff f8bd bl 80004f8 <__aeabi_dmul>
800137e: 4602 mov r2, r0
8001380: 460b mov r3, r1
8001382: 4610 mov r0, r2
8001384: 4619 mov r1, r3
8001386: f7ff fac9 bl 800091c <__aeabi_d2uiz>
800138a: 4603 mov r3, r0
800138c: 607b str r3, [r7, #4]
HAL_ADC_Stop(&hadc);
800138e: 4823 ldr r0, [pc, #140] @ (800141c <main+0x134>)
8001390: f000 fd76 bl 8001e80 <HAL_ADC_Stop>
float temperature = 80 * (temp_value * vdda_div_3 - TS_CAL1) / (TS_CAL2 - TS_CAL1) + 30;
8001394: 6878 ldr r0, [r7, #4]
8001396: f7ff fb97 bl 8000ac8 <__aeabi_ui2f>
800139a: 4603 mov r3, r0
800139c: 68b9 ldr r1, [r7, #8]
800139e: 4618 mov r0, r3
80013a0: f7ff fbea bl 8000b78 <__aeabi_fmul>
80013a4: 4603 mov r3, r0
80013a6: 461c mov r4, r3
80013a8: 8afb ldrh r3, [r7, #22]
80013aa: 4618 mov r0, r3
80013ac: f7ff fb90 bl 8000ad0 <__aeabi_i2f>
80013b0: 4603 mov r3, r0
80013b2: 4619 mov r1, r3
80013b4: 4620 mov r0, r4
80013b6: f7ff fad5 bl 8000964 <__aeabi_fsub>
80013ba: 4603 mov r3, r0
80013bc: 4919 ldr r1, [pc, #100] @ (8001424 <main+0x13c>)
80013be: 4618 mov r0, r3
80013c0: f7ff fbda bl 8000b78 <__aeabi_fmul>
80013c4: 4603 mov r3, r0
80013c6: 461c mov r4, r3
80013c8: 8aba ldrh r2, [r7, #20]
80013ca: 8afb ldrh r3, [r7, #22]
80013cc: 1ad3 subs r3, r2, r3
80013ce: 4618 mov r0, r3
80013d0: f7ff fb7e bl 8000ad0 <__aeabi_i2f>
80013d4: 4603 mov r3, r0
80013d6: 4619 mov r1, r3
80013d8: 4620 mov r0, r4
80013da: f7ff fc81 bl 8000ce0 <__aeabi_fdiv>
80013de: 4603 mov r3, r0
80013e0: 4911 ldr r1, [pc, #68] @ (8001428 <main+0x140>)
80013e2: 4618 mov r0, r3
80013e4: f7ff fac0 bl 8000968 <__addsf3>
80013e8: 4603 mov r3, r0
80013ea: 603b str r3, [r7, #0]
affiche_nombre((uint32_t)(temperature), 10, 80);
80013ec: 6838 ldr r0, [r7, #0]
80013ee: f7ff fd13 bl 8000e18 <__aeabi_f2uiz>
80013f2: 4603 mov r3, r0
80013f4: 2250 movs r2, #80 @ 0x50
80013f6: 210a movs r1, #10
80013f8: 4618 mov r0, r3
80013fa: f7ff fec7 bl 800118c <affiche_nombre>
{
80013fe: bf00 nop
8001400: e7a0 b.n 8001344 <main+0x5c>
8001402: bf00 nop
8001404: f3af 8000 nop.w
8001408: 00000000 .word 0x00000000
800140c: 40a9c800 .word 0x40a9c800
8001410: 1ff800fa .word 0x1ff800fa
8001414: 1ff800fe .word 0x1ff800fe
8001418: 1ff800f8 .word 0x1ff800f8
800141c: 20000028 .word 0x20000028
8001420: 40b00000 .word 0x40b00000
8001424: 42a00000 .word 0x42a00000
8001428: 41f00000 .word 0x41f00000
0800142c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800142c: b580 push {r7, lr}
800142e: b092 sub sp, #72 @ 0x48
8001430: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8001432: f107 0314 add.w r3, r7, #20
8001436: 2234 movs r2, #52 @ 0x34
8001438: 2100 movs r1, #0
800143a: 4618 mov r0, r3
800143c: f002 fdee bl 800401c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8001440: 463b mov r3, r7
8001442: 2200 movs r2, #0
8001444: 601a str r2, [r3, #0]
8001446: 605a str r2, [r3, #4]
8001448: 609a str r2, [r3, #8]
800144a: 60da str r2, [r3, #12]
800144c: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
800144e: 4b19 ldr r3, [pc, #100] @ (80014b4 <SystemClock_Config+0x88>)
8001450: 681b ldr r3, [r3, #0]
8001452: f423 53c0 bic.w r3, r3, #6144 @ 0x1800
8001456: 4a17 ldr r2, [pc, #92] @ (80014b4 <SystemClock_Config+0x88>)
8001458: f443 6300 orr.w r3, r3, #2048 @ 0x800
800145c: 6013 str r3, [r2, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800145e: 2302 movs r3, #2
8001460: 617b str r3, [r7, #20]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8001462: 2301 movs r3, #1
8001464: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8001466: 2310 movs r3, #16
8001468: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
800146a: 2300 movs r3, #0
800146c: 63bb str r3, [r7, #56] @ 0x38
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800146e: f107 0314 add.w r3, r7, #20
8001472: 4618 mov r0, r3
8001474: f001 fa62 bl 800293c <HAL_RCC_OscConfig>
8001478: 4603 mov r3, r0
800147a: 2b00 cmp r3, #0
800147c: d001 beq.n 8001482 <SystemClock_Config+0x56>
{
Error_Handler();
800147e: f000 f93d bl 80016fc <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8001482: 230f movs r3, #15
8001484: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
8001486: 2301 movs r3, #1
8001488: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800148a: 2300 movs r3, #0
800148c: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800148e: 2300 movs r3, #0
8001490: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8001492: 2300 movs r3, #0
8001494: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8001496: 463b mov r3, r7
8001498: 2100 movs r1, #0
800149a: 4618 mov r0, r3
800149c: f001 fd7e bl 8002f9c <HAL_RCC_ClockConfig>
80014a0: 4603 mov r3, r0
80014a2: 2b00 cmp r3, #0
80014a4: d001 beq.n 80014aa <SystemClock_Config+0x7e>
{
Error_Handler();
80014a6: f000 f929 bl 80016fc <Error_Handler>
}
}
80014aa: bf00 nop
80014ac: 3748 adds r7, #72 @ 0x48
80014ae: 46bd mov sp, r7
80014b0: bd80 pop {r7, pc}
80014b2: bf00 nop
80014b4: 40007000 .word 0x40007000
080014b8 <MX_ADC_Init>:
* @brief ADC Initialization Function
* @param None
* @retval None
*/
static void MX_ADC_Init(void)
{
80014b8: b580 push {r7, lr}
80014ba: b084 sub sp, #16
80014bc: af00 add r7, sp, #0
/* USER CODE BEGIN ADC_Init 0 */
/* USER CODE END ADC_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80014be: 1d3b adds r3, r7, #4
80014c0: 2200 movs r2, #0
80014c2: 601a str r2, [r3, #0]
80014c4: 605a str r2, [r3, #4]
80014c6: 609a str r2, [r3, #8]
/* USER CODE END ADC_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc.Instance = ADC1;
80014c8: 4b25 ldr r3, [pc, #148] @ (8001560 <MX_ADC_Init+0xa8>)
80014ca: 4a26 ldr r2, [pc, #152] @ (8001564 <MX_ADC_Init+0xac>)
80014cc: 601a str r2, [r3, #0]
hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
80014ce: 4b24 ldr r3, [pc, #144] @ (8001560 <MX_ADC_Init+0xa8>)
80014d0: 2200 movs r2, #0
80014d2: 605a str r2, [r3, #4]
hadc.Init.Resolution = ADC_RESOLUTION_12B;
80014d4: 4b22 ldr r3, [pc, #136] @ (8001560 <MX_ADC_Init+0xa8>)
80014d6: 2200 movs r2, #0
80014d8: 609a str r2, [r3, #8]
hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80014da: 4b21 ldr r3, [pc, #132] @ (8001560 <MX_ADC_Init+0xa8>)
80014dc: 2200 movs r2, #0
80014de: 60da str r2, [r3, #12]
hadc.Init.ScanConvMode = ADC_SCAN_DISABLE;
80014e0: 4b1f ldr r3, [pc, #124] @ (8001560 <MX_ADC_Init+0xa8>)
80014e2: 2200 movs r2, #0
80014e4: 611a str r2, [r3, #16]
hadc.Init.EOCSelection = ADC_EOC_SEQ_CONV;
80014e6: 4b1e ldr r3, [pc, #120] @ (8001560 <MX_ADC_Init+0xa8>)
80014e8: 2200 movs r2, #0
80014ea: 615a str r2, [r3, #20]
hadc.Init.LowPowerAutoWait = ADC_AUTOWAIT_DISABLE;
80014ec: 4b1c ldr r3, [pc, #112] @ (8001560 <MX_ADC_Init+0xa8>)
80014ee: 2200 movs r2, #0
80014f0: 619a str r2, [r3, #24]
hadc.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_DISABLE;
80014f2: 4b1b ldr r3, [pc, #108] @ (8001560 <MX_ADC_Init+0xa8>)
80014f4: 2200 movs r2, #0
80014f6: 61da str r2, [r3, #28]
hadc.Init.ChannelsBank = ADC_CHANNELS_BANK_A;
80014f8: 4b19 ldr r3, [pc, #100] @ (8001560 <MX_ADC_Init+0xa8>)
80014fa: 2200 movs r2, #0
80014fc: 621a str r2, [r3, #32]
hadc.Init.ContinuousConvMode = DISABLE;
80014fe: 4b18 ldr r3, [pc, #96] @ (8001560 <MX_ADC_Init+0xa8>)
8001500: 2200 movs r2, #0
8001502: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc.Init.NbrOfConversion = 1;
8001506: 4b16 ldr r3, [pc, #88] @ (8001560 <MX_ADC_Init+0xa8>)
8001508: 2201 movs r2, #1
800150a: 629a str r2, [r3, #40] @ 0x28
hadc.Init.DiscontinuousConvMode = DISABLE;
800150c: 4b14 ldr r3, [pc, #80] @ (8001560 <MX_ADC_Init+0xa8>)
800150e: 2200 movs r2, #0
8001510: f883 202c strb.w r2, [r3, #44] @ 0x2c
hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001514: 4b12 ldr r3, [pc, #72] @ (8001560 <MX_ADC_Init+0xa8>)
8001516: 2210 movs r2, #16
8001518: 635a str r2, [r3, #52] @ 0x34
hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800151a: 4b11 ldr r3, [pc, #68] @ (8001560 <MX_ADC_Init+0xa8>)
800151c: 2200 movs r2, #0
800151e: 639a str r2, [r3, #56] @ 0x38
hadc.Init.DMAContinuousRequests = DISABLE;
8001520: 4b0f ldr r3, [pc, #60] @ (8001560 <MX_ADC_Init+0xa8>)
8001522: 2200 movs r2, #0
8001524: f883 203c strb.w r2, [r3, #60] @ 0x3c
if (HAL_ADC_Init(&hadc) != HAL_OK)
8001528: 480d ldr r0, [pc, #52] @ (8001560 <MX_ADC_Init+0xa8>)
800152a: f000 fb03 bl 8001b34 <HAL_ADC_Init>
800152e: 4603 mov r3, r0
8001530: 2b00 cmp r3, #0
8001532: d001 beq.n 8001538 <MX_ADC_Init+0x80>
{
Error_Handler();
8001534: f000 f8e2 bl 80016fc <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
8001538: 2310 movs r3, #16
800153a: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
800153c: 2301 movs r3, #1
800153e: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_4CYCLES;
8001540: 2300 movs r3, #0
8001542: 60fb str r3, [r7, #12]
if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
8001544: 1d3b adds r3, r7, #4
8001546: 4619 mov r1, r3
8001548: 4805 ldr r0, [pc, #20] @ (8001560 <MX_ADC_Init+0xa8>)
800154a: f000 fd61 bl 8002010 <HAL_ADC_ConfigChannel>
800154e: 4603 mov r3, r0
8001550: 2b00 cmp r3, #0
8001552: d001 beq.n 8001558 <MX_ADC_Init+0xa0>
{
Error_Handler();
8001554: f000 f8d2 bl 80016fc <Error_Handler>
}
/* USER CODE BEGIN ADC_Init 2 */
/* USER CODE END ADC_Init 2 */
}
8001558: bf00 nop
800155a: 3710 adds r7, #16
800155c: 46bd mov sp, r7
800155e: bd80 pop {r7, pc}
8001560: 20000028 .word 0x20000028
8001564: 40012400 .word 0x40012400
08001568 <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
8001568: b580 push {r7, lr}
800156a: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
800156c: 4b17 ldr r3, [pc, #92] @ (80015cc <MX_SPI1_Init+0x64>)
800156e: 4a18 ldr r2, [pc, #96] @ (80015d0 <MX_SPI1_Init+0x68>)
8001570: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
8001572: 4b16 ldr r3, [pc, #88] @ (80015cc <MX_SPI1_Init+0x64>)
8001574: f44f 7282 mov.w r2, #260 @ 0x104
8001578: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
800157a: 4b14 ldr r3, [pc, #80] @ (80015cc <MX_SPI1_Init+0x64>)
800157c: 2200 movs r2, #0
800157e: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
8001580: 4b12 ldr r3, [pc, #72] @ (80015cc <MX_SPI1_Init+0x64>)
8001582: 2200 movs r2, #0
8001584: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
8001586: 4b11 ldr r3, [pc, #68] @ (80015cc <MX_SPI1_Init+0x64>)
8001588: 2200 movs r2, #0
800158a: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
800158c: 4b0f ldr r3, [pc, #60] @ (80015cc <MX_SPI1_Init+0x64>)
800158e: 2200 movs r2, #0
8001590: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
8001592: 4b0e ldr r3, [pc, #56] @ (80015cc <MX_SPI1_Init+0x64>)
8001594: f44f 7200 mov.w r2, #512 @ 0x200
8001598: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
800159a: 4b0c ldr r3, [pc, #48] @ (80015cc <MX_SPI1_Init+0x64>)
800159c: 2200 movs r2, #0
800159e: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
80015a0: 4b0a ldr r3, [pc, #40] @ (80015cc <MX_SPI1_Init+0x64>)
80015a2: 2200 movs r2, #0
80015a4: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
80015a6: 4b09 ldr r3, [pc, #36] @ (80015cc <MX_SPI1_Init+0x64>)
80015a8: 2200 movs r2, #0
80015aa: 625a str r2, [r3, #36] @ 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80015ac: 4b07 ldr r3, [pc, #28] @ (80015cc <MX_SPI1_Init+0x64>)
80015ae: 2200 movs r2, #0
80015b0: 629a str r2, [r3, #40] @ 0x28
hspi1.Init.CRCPolynomial = 10;
80015b2: 4b06 ldr r3, [pc, #24] @ (80015cc <MX_SPI1_Init+0x64>)
80015b4: 220a movs r2, #10
80015b6: 62da str r2, [r3, #44] @ 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
80015b8: 4804 ldr r0, [pc, #16] @ (80015cc <MX_SPI1_Init+0x64>)
80015ba: f001 ff41 bl 8003440 <HAL_SPI_Init>
80015be: 4603 mov r3, r0
80015c0: 2b00 cmp r3, #0
80015c2: d001 beq.n 80015c8 <MX_SPI1_Init+0x60>
{
Error_Handler();
80015c4: f000 f89a bl 80016fc <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
80015c8: bf00 nop
80015ca: bd80 pop {r7, pc}
80015cc: 2000007c .word 0x2000007c
80015d0: 40013000 .word 0x40013000
080015d4 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80015d4: b580 push {r7, lr}
80015d6: b08a sub sp, #40 @ 0x28
80015d8: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80015da: f107 0314 add.w r3, r7, #20
80015de: 2200 movs r2, #0
80015e0: 601a str r2, [r3, #0]
80015e2: 605a str r2, [r3, #4]
80015e4: 609a str r2, [r3, #8]
80015e6: 60da str r2, [r3, #12]
80015e8: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80015ea: 4b40 ldr r3, [pc, #256] @ (80016ec <MX_GPIO_Init+0x118>)
80015ec: 69db ldr r3, [r3, #28]
80015ee: 4a3f ldr r2, [pc, #252] @ (80016ec <MX_GPIO_Init+0x118>)
80015f0: f043 0304 orr.w r3, r3, #4
80015f4: 61d3 str r3, [r2, #28]
80015f6: 4b3d ldr r3, [pc, #244] @ (80016ec <MX_GPIO_Init+0x118>)
80015f8: 69db ldr r3, [r3, #28]
80015fa: f003 0304 and.w r3, r3, #4
80015fe: 613b str r3, [r7, #16]
8001600: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001602: 4b3a ldr r3, [pc, #232] @ (80016ec <MX_GPIO_Init+0x118>)
8001604: 69db ldr r3, [r3, #28]
8001606: 4a39 ldr r2, [pc, #228] @ (80016ec <MX_GPIO_Init+0x118>)
8001608: f043 0301 orr.w r3, r3, #1
800160c: 61d3 str r3, [r2, #28]
800160e: 4b37 ldr r3, [pc, #220] @ (80016ec <MX_GPIO_Init+0x118>)
8001610: 69db ldr r3, [r3, #28]
8001612: f003 0301 and.w r3, r3, #1
8001616: 60fb str r3, [r7, #12]
8001618: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
800161a: 4b34 ldr r3, [pc, #208] @ (80016ec <MX_GPIO_Init+0x118>)
800161c: 69db ldr r3, [r3, #28]
800161e: 4a33 ldr r2, [pc, #204] @ (80016ec <MX_GPIO_Init+0x118>)
8001620: f043 0302 orr.w r3, r3, #2
8001624: 61d3 str r3, [r2, #28]
8001626: 4b31 ldr r3, [pc, #196] @ (80016ec <MX_GPIO_Init+0x118>)
8001628: 69db ldr r3, [r3, #28]
800162a: f003 0302 and.w r3, r3, #2
800162e: 60bb str r3, [r7, #8]
8001630: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001632: 4b2e ldr r3, [pc, #184] @ (80016ec <MX_GPIO_Init+0x118>)
8001634: 69db ldr r3, [r3, #28]
8001636: 4a2d ldr r2, [pc, #180] @ (80016ec <MX_GPIO_Init+0x118>)
8001638: f043 0308 orr.w r3, r3, #8
800163c: 61d3 str r3, [r2, #28]
800163e: 4b2b ldr r3, [pc, #172] @ (80016ec <MX_GPIO_Init+0x118>)
8001640: 69db ldr r3, [r3, #28]
8001642: f003 0308 and.w r3, r3, #8
8001646: 607b str r3, [r7, #4]
8001648: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET);
800164a: 2200 movs r2, #0
800164c: 2101 movs r1, #1
800164e: 4828 ldr r0, [pc, #160] @ (80016f0 <MX_GPIO_Init+0x11c>)
8001650: f001 f95c bl 800290c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_SET);
8001654: 2201 movs r2, #1
8001656: 210e movs r1, #14
8001658: 4825 ldr r0, [pc, #148] @ (80016f0 <MX_GPIO_Init+0x11c>)
800165a: f001 f957 bl 800290c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET);
800165e: 2201 movs r2, #1
8001660: 2104 movs r1, #4
8001662: 4824 ldr r0, [pc, #144] @ (80016f4 <MX_GPIO_Init+0x120>)
8001664: f001 f952 bl 800290c <HAL_GPIO_WritePin>
/*Configure GPIO pins : PC0 PC1 PC2 PC3 */
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
8001668: 230f movs r3, #15
800166a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800166c: 2301 movs r3, #1
800166e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001670: 2300 movs r3, #0
8001672: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001674: 2300 movs r3, #0
8001676: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001678: f107 0314 add.w r3, r7, #20
800167c: 4619 mov r1, r3
800167e: 481c ldr r0, [pc, #112] @ (80016f0 <MX_GPIO_Init+0x11c>)
8001680: f000 ffb4 bl 80025ec <HAL_GPIO_Init>
/*Configure GPIO pin : PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_15;
8001684: f44f 4300 mov.w r3, #32768 @ 0x8000
8001688: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800168a: 2302 movs r3, #2
800168c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800168e: 2300 movs r3, #0
8001690: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001692: 2300 movs r3, #0
8001694: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF3_TIM11;
8001696: 2303 movs r3, #3
8001698: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800169a: f107 0314 add.w r3, r7, #20
800169e: 4619 mov r1, r3
80016a0: 4815 ldr r0, [pc, #84] @ (80016f8 <MX_GPIO_Init+0x124>)
80016a2: f000 ffa3 bl 80025ec <HAL_GPIO_Init>
/*Configure GPIO pin : PD2 */
GPIO_InitStruct.Pin = GPIO_PIN_2;
80016a6: 2304 movs r3, #4
80016a8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80016aa: 2301 movs r3, #1
80016ac: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016ae: 2300 movs r3, #0
80016b0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80016b2: 2300 movs r3, #0
80016b4: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80016b6: f107 0314 add.w r3, r7, #20
80016ba: 4619 mov r1, r3
80016bc: 480d ldr r0, [pc, #52] @ (80016f4 <MX_GPIO_Init+0x120>)
80016be: f000 ff95 bl 80025ec <HAL_GPIO_Init>
/*Configure GPIO pin : PB7 */
GPIO_InitStruct.Pin = GPIO_PIN_7;
80016c2: 2380 movs r3, #128 @ 0x80
80016c4: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80016c6: 2302 movs r3, #2
80016c8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016ca: 2300 movs r3, #0
80016cc: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80016ce: 2300 movs r3, #0
80016d0: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
80016d2: 2302 movs r3, #2
80016d4: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80016d6: f107 0314 add.w r3, r7, #20
80016da: 4619 mov r1, r3
80016dc: 4806 ldr r0, [pc, #24] @ (80016f8 <MX_GPIO_Init+0x124>)
80016de: f000 ff85 bl 80025ec <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80016e2: bf00 nop
80016e4: 3728 adds r7, #40 @ 0x28
80016e6: 46bd mov sp, r7
80016e8: bd80 pop {r7, pc}
80016ea: bf00 nop
80016ec: 40023800 .word 0x40023800
80016f0: 40020800 .word 0x40020800
80016f4: 40020c00 .word 0x40020c00
80016f8: 40020400 .word 0x40020400
080016fc <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80016fc: b480 push {r7}
80016fe: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8001700: b672 cpsid i
}
8001702: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001704: bf00 nop
8001706: e7fd b.n 8001704 <Error_Handler+0x8>
08001708 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001708: b480 push {r7}
800170a: b085 sub sp, #20
800170c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_COMP_CLK_ENABLE();
800170e: 4b14 ldr r3, [pc, #80] @ (8001760 <HAL_MspInit+0x58>)
8001710: 6a5b ldr r3, [r3, #36] @ 0x24
8001712: 4a13 ldr r2, [pc, #76] @ (8001760 <HAL_MspInit+0x58>)
8001714: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8001718: 6253 str r3, [r2, #36] @ 0x24
800171a: 4b11 ldr r3, [pc, #68] @ (8001760 <HAL_MspInit+0x58>)
800171c: 6a5b ldr r3, [r3, #36] @ 0x24
800171e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8001722: 60fb str r3, [r7, #12]
8001724: 68fb ldr r3, [r7, #12]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001726: 4b0e ldr r3, [pc, #56] @ (8001760 <HAL_MspInit+0x58>)
8001728: 6a1b ldr r3, [r3, #32]
800172a: 4a0d ldr r2, [pc, #52] @ (8001760 <HAL_MspInit+0x58>)
800172c: f043 0301 orr.w r3, r3, #1
8001730: 6213 str r3, [r2, #32]
8001732: 4b0b ldr r3, [pc, #44] @ (8001760 <HAL_MspInit+0x58>)
8001734: 6a1b ldr r3, [r3, #32]
8001736: f003 0301 and.w r3, r3, #1
800173a: 60bb str r3, [r7, #8]
800173c: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
800173e: 4b08 ldr r3, [pc, #32] @ (8001760 <HAL_MspInit+0x58>)
8001740: 6a5b ldr r3, [r3, #36] @ 0x24
8001742: 4a07 ldr r2, [pc, #28] @ (8001760 <HAL_MspInit+0x58>)
8001744: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001748: 6253 str r3, [r2, #36] @ 0x24
800174a: 4b05 ldr r3, [pc, #20] @ (8001760 <HAL_MspInit+0x58>)
800174c: 6a5b ldr r3, [r3, #36] @ 0x24
800174e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001752: 607b str r3, [r7, #4]
8001754: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001756: bf00 nop
8001758: 3714 adds r7, #20
800175a: 46bd mov sp, r7
800175c: bc80 pop {r7}
800175e: 4770 bx lr
8001760: 40023800 .word 0x40023800
08001764 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8001764: b580 push {r7, lr}
8001766: b08a sub sp, #40 @ 0x28
8001768: af00 add r7, sp, #0
800176a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800176c: f107 0314 add.w r3, r7, #20
8001770: 2200 movs r2, #0
8001772: 601a str r2, [r3, #0]
8001774: 605a str r2, [r3, #4]
8001776: 609a str r2, [r3, #8]
8001778: 60da str r2, [r3, #12]
800177a: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
800177c: 687b ldr r3, [r7, #4]
800177e: 681b ldr r3, [r3, #0]
8001780: 4a15 ldr r2, [pc, #84] @ (80017d8 <HAL_ADC_MspInit+0x74>)
8001782: 4293 cmp r3, r2
8001784: d123 bne.n 80017ce <HAL_ADC_MspInit+0x6a>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8001786: 4b15 ldr r3, [pc, #84] @ (80017dc <HAL_ADC_MspInit+0x78>)
8001788: 6a1b ldr r3, [r3, #32]
800178a: 4a14 ldr r2, [pc, #80] @ (80017dc <HAL_ADC_MspInit+0x78>)
800178c: f443 7300 orr.w r3, r3, #512 @ 0x200
8001790: 6213 str r3, [r2, #32]
8001792: 4b12 ldr r3, [pc, #72] @ (80017dc <HAL_ADC_MspInit+0x78>)
8001794: 6a1b ldr r3, [r3, #32]
8001796: f403 7300 and.w r3, r3, #512 @ 0x200
800179a: 613b str r3, [r7, #16]
800179c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800179e: 4b0f ldr r3, [pc, #60] @ (80017dc <HAL_ADC_MspInit+0x78>)
80017a0: 69db ldr r3, [r3, #28]
80017a2: 4a0e ldr r2, [pc, #56] @ (80017dc <HAL_ADC_MspInit+0x78>)
80017a4: f043 0301 orr.w r3, r3, #1
80017a8: 61d3 str r3, [r2, #28]
80017aa: 4b0c ldr r3, [pc, #48] @ (80017dc <HAL_ADC_MspInit+0x78>)
80017ac: 69db ldr r3, [r3, #28]
80017ae: f003 0301 and.w r3, r3, #1
80017b2: 60fb str r3, [r7, #12]
80017b4: 68fb ldr r3, [r7, #12]
/**ADC GPIO Configuration
PA0-WKUP1 ------> ADC_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
80017b6: 2301 movs r3, #1
80017b8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80017ba: 2303 movs r3, #3
80017bc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80017be: 2300 movs r3, #0
80017c0: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80017c2: f107 0314 add.w r3, r7, #20
80017c6: 4619 mov r1, r3
80017c8: 4805 ldr r0, [pc, #20] @ (80017e0 <HAL_ADC_MspInit+0x7c>)
80017ca: f000 ff0f bl 80025ec <HAL_GPIO_Init>
/* USER CODE END ADC1_MspInit 1 */
}
}
80017ce: bf00 nop
80017d0: 3728 adds r7, #40 @ 0x28
80017d2: 46bd mov sp, r7
80017d4: bd80 pop {r7, pc}
80017d6: bf00 nop
80017d8: 40012400 .word 0x40012400
80017dc: 40023800 .word 0x40023800
80017e0: 40020000 .word 0x40020000
080017e4 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80017e4: b580 push {r7, lr}
80017e6: b08a sub sp, #40 @ 0x28
80017e8: af00 add r7, sp, #0
80017ea: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80017ec: f107 0314 add.w r3, r7, #20
80017f0: 2200 movs r2, #0
80017f2: 601a str r2, [r3, #0]
80017f4: 605a str r2, [r3, #4]
80017f6: 609a str r2, [r3, #8]
80017f8: 60da str r2, [r3, #12]
80017fa: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
80017fc: 687b ldr r3, [r7, #4]
80017fe: 681b ldr r3, [r3, #0]
8001800: 4a17 ldr r2, [pc, #92] @ (8001860 <HAL_SPI_MspInit+0x7c>)
8001802: 4293 cmp r3, r2
8001804: d127 bne.n 8001856 <HAL_SPI_MspInit+0x72>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8001806: 4b17 ldr r3, [pc, #92] @ (8001864 <HAL_SPI_MspInit+0x80>)
8001808: 6a1b ldr r3, [r3, #32]
800180a: 4a16 ldr r2, [pc, #88] @ (8001864 <HAL_SPI_MspInit+0x80>)
800180c: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8001810: 6213 str r3, [r2, #32]
8001812: 4b14 ldr r3, [pc, #80] @ (8001864 <HAL_SPI_MspInit+0x80>)
8001814: 6a1b ldr r3, [r3, #32]
8001816: f403 5380 and.w r3, r3, #4096 @ 0x1000
800181a: 613b str r3, [r7, #16]
800181c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800181e: 4b11 ldr r3, [pc, #68] @ (8001864 <HAL_SPI_MspInit+0x80>)
8001820: 69db ldr r3, [r3, #28]
8001822: 4a10 ldr r2, [pc, #64] @ (8001864 <HAL_SPI_MspInit+0x80>)
8001824: f043 0301 orr.w r3, r3, #1
8001828: 61d3 str r3, [r2, #28]
800182a: 4b0e ldr r3, [pc, #56] @ (8001864 <HAL_SPI_MspInit+0x80>)
800182c: 69db ldr r3, [r3, #28]
800182e: f003 0301 and.w r3, r3, #1
8001832: 60fb str r3, [r7, #12]
8001834: 68fb ldr r3, [r7, #12]
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
8001836: 23e0 movs r3, #224 @ 0xe0
8001838: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800183a: 2302 movs r3, #2
800183c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800183e: 2300 movs r3, #0
8001840: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001842: 2303 movs r3, #3
8001844: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8001846: 2305 movs r3, #5
8001848: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800184a: f107 0314 add.w r3, r7, #20
800184e: 4619 mov r1, r3
8001850: 4805 ldr r0, [pc, #20] @ (8001868 <HAL_SPI_MspInit+0x84>)
8001852: f000 fecb bl 80025ec <HAL_GPIO_Init>
/* USER CODE END SPI1_MspInit 1 */
}
}
8001856: bf00 nop
8001858: 3728 adds r7, #40 @ 0x28
800185a: 46bd mov sp, r7
800185c: bd80 pop {r7, pc}
800185e: bf00 nop
8001860: 40013000 .word 0x40013000
8001864: 40023800 .word 0x40023800
8001868: 40020000 .word 0x40020000
0800186c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800186c: b480 push {r7}
800186e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001870: bf00 nop
8001872: e7fd b.n 8001870 <NMI_Handler+0x4>
08001874 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001874: b480 push {r7}
8001876: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001878: bf00 nop
800187a: e7fd b.n 8001878 <HardFault_Handler+0x4>
0800187c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
800187c: b480 push {r7}
800187e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001880: bf00 nop
8001882: e7fd b.n 8001880 <MemManage_Handler+0x4>
08001884 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001884: b480 push {r7}
8001886: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001888: bf00 nop
800188a: e7fd b.n 8001888 <BusFault_Handler+0x4>
0800188c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
800188c: b480 push {r7}
800188e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001890: bf00 nop
8001892: e7fd b.n 8001890 <UsageFault_Handler+0x4>
08001894 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001894: b480 push {r7}
8001896: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8001898: bf00 nop
800189a: 46bd mov sp, r7
800189c: bc80 pop {r7}
800189e: 4770 bx lr
080018a0 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80018a0: b480 push {r7}
80018a2: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80018a4: bf00 nop
80018a6: 46bd mov sp, r7
80018a8: bc80 pop {r7}
80018aa: 4770 bx lr
080018ac <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80018ac: b480 push {r7}
80018ae: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80018b0: bf00 nop
80018b2: 46bd mov sp, r7
80018b4: bc80 pop {r7}
80018b6: 4770 bx lr
080018b8 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80018b8: b580 push {r7, lr}
80018ba: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80018bc: f000 f8fc bl 8001ab8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80018c0: bf00 nop
80018c2: bd80 pop {r7, pc}
080018c4 <SystemInit>:
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
80018c4: b480 push {r7}
80018c6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80018c8: bf00 nop
80018ca: 46bd mov sp, r7
80018cc: bc80 pop {r7}
80018ce: 4770 bx lr
080018d0 <Reset_Handler>:
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
80018d0: f7ff fff8 bl 80018c4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80018d4: 480b ldr r0, [pc, #44] @ (8001904 <LoopFillZerobss+0xe>)
ldr r1, =_edata
80018d6: 490c ldr r1, [pc, #48] @ (8001908 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
80018d8: 4a0c ldr r2, [pc, #48] @ (800190c <LoopFillZerobss+0x16>)
movs r3, #0
80018da: 2300 movs r3, #0
b LoopCopyDataInit
80018dc: e002 b.n 80018e4 <LoopCopyDataInit>
080018de <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80018de: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80018e0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80018e2: 3304 adds r3, #4
080018e4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80018e4: 18c4 adds r4, r0, r3
cmp r4, r1
80018e6: 428c cmp r4, r1
bcc CopyDataInit
80018e8: d3f9 bcc.n 80018de <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80018ea: 4a09 ldr r2, [pc, #36] @ (8001910 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
80018ec: 4c09 ldr r4, [pc, #36] @ (8001914 <LoopFillZerobss+0x1e>)
movs r3, #0
80018ee: 2300 movs r3, #0
b LoopFillZerobss
80018f0: e001 b.n 80018f6 <LoopFillZerobss>
080018f2 <FillZerobss>:
FillZerobss:
str r3, [r2]
80018f2: 6013 str r3, [r2, #0]
adds r2, r2, #4
80018f4: 3204 adds r2, #4
080018f6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80018f6: 42a2 cmp r2, r4
bcc FillZerobss
80018f8: d3fb bcc.n 80018f2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80018fa: f002 fb97 bl 800402c <__libc_init_array>
/* Call the application's entry point.*/
bl main
80018fe: f7ff fcf3 bl 80012e8 <main>
bx lr
8001902: 4770 bx lr
ldr r0, =_sdata
8001904: 20000000 .word 0x20000000
ldr r1, =_edata
8001908: 2000000c .word 0x2000000c
ldr r2, =_sidata
800190c: 080048fc .word 0x080048fc
ldr r2, =_sbss
8001910: 2000000c .word 0x2000000c
ldr r4, =_ebss
8001914: 200000d8 .word 0x200000d8
08001918 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001918: e7fe b.n 8001918 <ADC1_IRQHandler>
0800191a <MAX7219_Init>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Init (void)
{
800191a: b580 push {r7, lr}
800191c: af00 add r7, sp, #0
// configure "LOAD" as output
MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits
800191e: 2107 movs r1, #7
8001920: 200b movs r0, #11
8001922: f000 f847 bl 80019b4 <MAX7219_Write>
MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits
8001926: 2100 movs r1, #0
8001928: 2009 movs r0, #9
800192a: f000 f843 bl 80019b4 <MAX7219_Write>
MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown)
800192e: f000 f809 bl 8001944 <MAX7219_ShutdownStop>
MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode)
8001932: f000 f80f bl 8001954 <MAX7219_DisplayTestStop>
MAX7219_Clear(); // clear all digits
8001936: f000 f827 bl 8001988 <MAX7219_Clear>
MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity
800193a: 200f movs r0, #15
800193c: f000 f812 bl 8001964 <MAX7219_SetBrightness>
}
8001940: bf00 nop
8001942: bd80 pop {r7, pc}
08001944 <MAX7219_ShutdownStop>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_ShutdownStop (void)
{
8001944: b580 push {r7, lr}
8001946: af00 add r7, sp, #0
MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode
8001948: 2101 movs r1, #1
800194a: 200c movs r0, #12
800194c: f000 f832 bl 80019b4 <MAX7219_Write>
}
8001950: bf00 nop
8001952: bd80 pop {r7, pc}
08001954 <MAX7219_DisplayTestStop>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_DisplayTestStop (void)
{
8001954: b580 push {r7, lr}
8001956: af00 add r7, sp, #0
MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode
8001958: 2100 movs r1, #0
800195a: 200f movs r0, #15
800195c: f000 f82a bl 80019b4 <MAX7219_Write>
}
8001960: bf00 nop
8001962: bd80 pop {r7, pc}
08001964 <MAX7219_SetBrightness>:
* Arguments : brightness (0-15)
* Returns : none
*********************************************************************************************************
*/
void MAX7219_SetBrightness (char brightness)
{
8001964: b580 push {r7, lr}
8001966: b082 sub sp, #8
8001968: af00 add r7, sp, #0
800196a: 4603 mov r3, r0
800196c: 71fb strb r3, [r7, #7]
brightness &= 0x0f; // mask off extra bits
800196e: 79fb ldrb r3, [r7, #7]
8001970: f003 030f and.w r3, r3, #15
8001974: 71fb strb r3, [r7, #7]
MAX7219_Write(REG_INTENSITY, brightness); // set brightness
8001976: 79fb ldrb r3, [r7, #7]
8001978: 4619 mov r1, r3
800197a: 200a movs r0, #10
800197c: f000 f81a bl 80019b4 <MAX7219_Write>
}
8001980: bf00 nop
8001982: 3708 adds r7, #8
8001984: 46bd mov sp, r7
8001986: bd80 pop {r7, pc}
08001988 <MAX7219_Clear>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Clear (void)
{
8001988: b580 push {r7, lr}
800198a: b082 sub sp, #8
800198c: af00 add r7, sp, #0
char i;
for (i=0; i < 8; i++)
800198e: 2300 movs r3, #0
8001990: 71fb strb r3, [r7, #7]
8001992: e007 b.n 80019a4 <MAX7219_Clear+0x1c>
MAX7219_Write(i, 0x00); // turn all segments off
8001994: 79fb ldrb r3, [r7, #7]
8001996: 2100 movs r1, #0
8001998: 4618 mov r0, r3
800199a: f000 f80b bl 80019b4 <MAX7219_Write>
for (i=0; i < 8; i++)
800199e: 79fb ldrb r3, [r7, #7]
80019a0: 3301 adds r3, #1
80019a2: 71fb strb r3, [r7, #7]
80019a4: 79fb ldrb r3, [r7, #7]
80019a6: 2b07 cmp r3, #7
80019a8: d9f4 bls.n 8001994 <MAX7219_Clear+0xc>
}
80019aa: bf00 nop
80019ac: bf00 nop
80019ae: 3708 adds r7, #8
80019b0: 46bd mov sp, r7
80019b2: bd80 pop {r7, pc}
080019b4 <MAX7219_Write>:
* dataout = data to write to MAX7219
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Write (unsigned char reg_number, unsigned char dataout)
{
80019b4: b580 push {r7, lr}
80019b6: b082 sub sp, #8
80019b8: af00 add r7, sp, #0
80019ba: 4603 mov r3, r0
80019bc: 460a mov r2, r1
80019be: 71fb strb r3, [r7, #7]
80019c0: 4613 mov r3, r2
80019c2: 71bb strb r3, [r7, #6]
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin
80019c4: 4b09 ldr r3, [pc, #36] @ (80019ec <MAX7219_Write+0x38>)
80019c6: f44f 3280 mov.w r2, #65536 @ 0x10000
80019ca: 619a str r2, [r3, #24]
MAX7219_SendByte(reg_number); // write register number to MAX7219
80019cc: 79fb ldrb r3, [r7, #7]
80019ce: 4618 mov r0, r3
80019d0: f000 f80e bl 80019f0 <MAX7219_SendByte>
MAX7219_SendByte(dataout); // write data to MAX7219
80019d4: 79bb ldrb r3, [r7, #6]
80019d6: 4618 mov r0, r3
80019d8: f000 f80a bl 80019f0 <MAX7219_SendByte>
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data
80019dc: 4b03 ldr r3, [pc, #12] @ (80019ec <MAX7219_Write+0x38>)
80019de: 2201 movs r2, #1
80019e0: 619a str r2, [r3, #24]
}
80019e2: bf00 nop
80019e4: 3708 adds r7, #8
80019e6: 46bd mov sp, r7
80019e8: bd80 pop {r7, pc}
80019ea: bf00 nop
80019ec: 40020800 .word 0x40020800
080019f0 <MAX7219_SendByte>:
* Returns : none
*********************************************************************************************************
*/
static void MAX7219_SendByte (unsigned char dataout)
{
80019f0: b580 push {r7, lr}
80019f2: b082 sub sp, #8
80019f4: af00 add r7, sp, #0
80019f6: 4603 mov r3, r0
80019f8: 71fb strb r3, [r7, #7]
HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000);
80019fa: 1df9 adds r1, r7, #7
80019fc: f44f 737a mov.w r3, #1000 @ 0x3e8
8001a00: 2201 movs r2, #1
8001a02: 4803 ldr r0, [pc, #12] @ (8001a10 <MAX7219_SendByte+0x20>)
8001a04: f001 fda5 bl 8003552 <HAL_SPI_Transmit>
}
8001a08: bf00 nop
8001a0a: 3708 adds r7, #8
8001a0c: 46bd mov sp, r7
8001a0e: bd80 pop {r7, pc}
8001a10: 2000007c .word 0x2000007c
08001a14 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001a14: b580 push {r7, lr}
8001a16: b082 sub sp, #8
8001a18: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001a1a: 2300 movs r3, #0
8001a1c: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001a1e: 2003 movs r0, #3
8001a20: f000 fdb0 bl 8002584 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001a24: 200f movs r0, #15
8001a26: f000 f80d bl 8001a44 <HAL_InitTick>
8001a2a: 4603 mov r3, r0
8001a2c: 2b00 cmp r3, #0
8001a2e: d002 beq.n 8001a36 <HAL_Init+0x22>
{
status = HAL_ERROR;
8001a30: 2301 movs r3, #1
8001a32: 71fb strb r3, [r7, #7]
8001a34: e001 b.n 8001a3a <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001a36: f7ff fe67 bl 8001708 <HAL_MspInit>
}
/* Return function status */
return status;
8001a3a: 79fb ldrb r3, [r7, #7]
}
8001a3c: 4618 mov r0, r3
8001a3e: 3708 adds r7, #8
8001a40: 46bd mov sp, r7
8001a42: bd80 pop {r7, pc}
08001a44 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001a44: b580 push {r7, lr}
8001a46: b084 sub sp, #16
8001a48: af00 add r7, sp, #0
8001a4a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001a4c: 2300 movs r3, #0
8001a4e: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8001a50: 4b16 ldr r3, [pc, #88] @ (8001aac <HAL_InitTick+0x68>)
8001a52: 681b ldr r3, [r3, #0]
8001a54: 2b00 cmp r3, #0
8001a56: d022 beq.n 8001a9e <HAL_InitTick+0x5a>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8001a58: 4b15 ldr r3, [pc, #84] @ (8001ab0 <HAL_InitTick+0x6c>)
8001a5a: 681a ldr r2, [r3, #0]
8001a5c: 4b13 ldr r3, [pc, #76] @ (8001aac <HAL_InitTick+0x68>)
8001a5e: 681b ldr r3, [r3, #0]
8001a60: f44f 717a mov.w r1, #1000 @ 0x3e8
8001a64: fbb1 f3f3 udiv r3, r1, r3
8001a68: fbb2 f3f3 udiv r3, r2, r3
8001a6c: 4618 mov r0, r3
8001a6e: f000 fdb0 bl 80025d2 <HAL_SYSTICK_Config>
8001a72: 4603 mov r3, r0
8001a74: 2b00 cmp r3, #0
8001a76: d10f bne.n 8001a98 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001a78: 687b ldr r3, [r7, #4]
8001a7a: 2b0f cmp r3, #15
8001a7c: d809 bhi.n 8001a92 <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001a7e: 2200 movs r2, #0
8001a80: 6879 ldr r1, [r7, #4]
8001a82: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8001a86: f000 fd88 bl 800259a <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001a8a: 4a0a ldr r2, [pc, #40] @ (8001ab4 <HAL_InitTick+0x70>)
8001a8c: 687b ldr r3, [r7, #4]
8001a8e: 6013 str r3, [r2, #0]
8001a90: e007 b.n 8001aa2 <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8001a92: 2301 movs r3, #1
8001a94: 73fb strb r3, [r7, #15]
8001a96: e004 b.n 8001aa2 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001a98: 2301 movs r3, #1
8001a9a: 73fb strb r3, [r7, #15]
8001a9c: e001 b.n 8001aa2 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001a9e: 2301 movs r3, #1
8001aa0: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001aa2: 7bfb ldrb r3, [r7, #15]
}
8001aa4: 4618 mov r0, r3
8001aa6: 3710 adds r7, #16
8001aa8: 46bd mov sp, r7
8001aaa: bd80 pop {r7, pc}
8001aac: 20000008 .word 0x20000008
8001ab0: 20000000 .word 0x20000000
8001ab4: 20000004 .word 0x20000004
08001ab8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001ab8: b480 push {r7}
8001aba: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001abc: 4b05 ldr r3, [pc, #20] @ (8001ad4 <HAL_IncTick+0x1c>)
8001abe: 681a ldr r2, [r3, #0]
8001ac0: 4b05 ldr r3, [pc, #20] @ (8001ad8 <HAL_IncTick+0x20>)
8001ac2: 681b ldr r3, [r3, #0]
8001ac4: 4413 add r3, r2
8001ac6: 4a03 ldr r2, [pc, #12] @ (8001ad4 <HAL_IncTick+0x1c>)
8001ac8: 6013 str r3, [r2, #0]
}
8001aca: bf00 nop
8001acc: 46bd mov sp, r7
8001ace: bc80 pop {r7}
8001ad0: 4770 bx lr
8001ad2: bf00 nop
8001ad4: 200000d4 .word 0x200000d4
8001ad8: 20000008 .word 0x20000008
08001adc <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001adc: b480 push {r7}
8001ade: af00 add r7, sp, #0
return uwTick;
8001ae0: 4b02 ldr r3, [pc, #8] @ (8001aec <HAL_GetTick+0x10>)
8001ae2: 681b ldr r3, [r3, #0]
}
8001ae4: 4618 mov r0, r3
8001ae6: 46bd mov sp, r7
8001ae8: bc80 pop {r7}
8001aea: 4770 bx lr
8001aec: 200000d4 .word 0x200000d4
08001af0 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001af0: b580 push {r7, lr}
8001af2: b084 sub sp, #16
8001af4: af00 add r7, sp, #0
8001af6: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001af8: f7ff fff0 bl 8001adc <HAL_GetTick>
8001afc: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001afe: 687b ldr r3, [r7, #4]
8001b00: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
8001b02: 68fb ldr r3, [r7, #12]
8001b04: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001b08: d004 beq.n 8001b14 <HAL_Delay+0x24>
{
wait += (uint32_t)(uwTickFreq);
8001b0a: 4b09 ldr r3, [pc, #36] @ (8001b30 <HAL_Delay+0x40>)
8001b0c: 681b ldr r3, [r3, #0]
8001b0e: 68fa ldr r2, [r7, #12]
8001b10: 4413 add r3, r2
8001b12: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8001b14: bf00 nop
8001b16: f7ff ffe1 bl 8001adc <HAL_GetTick>
8001b1a: 4602 mov r2, r0
8001b1c: 68bb ldr r3, [r7, #8]
8001b1e: 1ad3 subs r3, r2, r3
8001b20: 68fa ldr r2, [r7, #12]
8001b22: 429a cmp r2, r3
8001b24: d8f7 bhi.n 8001b16 <HAL_Delay+0x26>
{
}
}
8001b26: bf00 nop
8001b28: bf00 nop
8001b2a: 3710 adds r7, #16
8001b2c: 46bd mov sp, r7
8001b2e: bd80 pop {r7, pc}
8001b30: 20000008 .word 0x20000008
08001b34 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8001b34: b580 push {r7, lr}
8001b36: b08e sub sp, #56 @ 0x38
8001b38: af00 add r7, sp, #0
8001b3a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001b3c: 2300 movs r3, #0
8001b3e: f887 3037 strb.w r3, [r7, #55] @ 0x37
uint32_t tmp_cr1 = 0;
8001b42: 2300 movs r3, #0
8001b44: 633b str r3, [r7, #48] @ 0x30
uint32_t tmp_cr2 = 0;
8001b46: 2300 movs r3, #0
8001b48: 62fb str r3, [r7, #44] @ 0x2c
/* Check ADC handle */
if(hadc == NULL)
8001b4a: 687b ldr r3, [r7, #4]
8001b4c: 2b00 cmp r3, #0
8001b4e: d101 bne.n 8001b54 <HAL_ADC_Init+0x20>
{
return HAL_ERROR;
8001b50: 2301 movs r3, #1
8001b52: e127 b.n 8001da4 <HAL_ADC_Init+0x270>
assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8001b54: 687b ldr r3, [r7, #4]
8001b56: 691b ldr r3, [r3, #16]
8001b58: 2b00 cmp r3, #0
/* Refer to header of this file for more details on clock enabling */
/* procedure. */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 6cdb ldr r3, [r3, #76] @ 0x4c
8001b5e: 2b00 cmp r3, #0
8001b60: d115 bne.n 8001b8e <HAL_ADC_Init+0x5a>
{
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8001b62: 687b ldr r3, [r7, #4]
8001b64: 2200 movs r2, #0
8001b66: 651a str r2, [r3, #80] @ 0x50
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8001b68: 687b ldr r3, [r7, #4]
8001b6a: 2200 movs r2, #0
8001b6c: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Enable SYSCFG clock to control the routing Interface (RI) */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001b70: 4b8e ldr r3, [pc, #568] @ (8001dac <HAL_ADC_Init+0x278>)
8001b72: 6a1b ldr r3, [r3, #32]
8001b74: 4a8d ldr r2, [pc, #564] @ (8001dac <HAL_ADC_Init+0x278>)
8001b76: f043 0301 orr.w r3, r3, #1
8001b7a: 6213 str r3, [r2, #32]
8001b7c: 4b8b ldr r3, [pc, #556] @ (8001dac <HAL_ADC_Init+0x278>)
8001b7e: 6a1b ldr r3, [r3, #32]
8001b80: f003 0301 and.w r3, r3, #1
8001b84: 60bb str r3, [r7, #8]
8001b86: 68bb ldr r3, [r7, #8]
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8001b88: 6878 ldr r0, [r7, #4]
8001b8a: f7ff fdeb bl 8001764 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 6cdb ldr r3, [r3, #76] @ 0x4c
8001b92: f003 0310 and.w r3, r3, #16
8001b96: 2b00 cmp r3, #0
8001b98: f040 80ff bne.w 8001d9a <HAL_ADC_Init+0x266>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001b9c: 687b ldr r3, [r7, #4]
8001b9e: 6cdb ldr r3, [r3, #76] @ 0x4c
8001ba0: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8001ba4: f023 0302 bic.w r3, r3, #2
8001ba8: f043 0202 orr.w r2, r3, #2
8001bac: 687b ldr r3, [r7, #4]
8001bae: 64da str r2, [r3, #76] @ 0x4c
/* Set ADC parameters */
/* Configuration of common ADC clock: clock source HSI with selectable */
/* prescaler */
MODIFY_REG(ADC->CCR ,
8001bb0: 4b7f ldr r3, [pc, #508] @ (8001db0 <HAL_ADC_Init+0x27c>)
8001bb2: 685b ldr r3, [r3, #4]
8001bb4: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8001bb8: 687b ldr r3, [r7, #4]
8001bba: 685b ldr r3, [r3, #4]
8001bbc: 497c ldr r1, [pc, #496] @ (8001db0 <HAL_ADC_Init+0x27c>)
8001bbe: 4313 orrs r3, r2
8001bc0: 604b str r3, [r1, #4]
/* - external trigger polarity */
/* - End of conversion selection */
/* - DMA continuous request */
/* - Channels bank (Banks availability depends on devices categories) */
/* - continuous conversion mode */
tmp_cr2 |= (hadc->Init.DataAlign |
8001bc2: 687b ldr r3, [r7, #4]
8001bc4: 68da ldr r2, [r3, #12]
hadc->Init.EOCSelection |
8001bc6: 687b ldr r3, [r7, #4]
8001bc8: 695b ldr r3, [r3, #20]
tmp_cr2 |= (hadc->Init.DataAlign |
8001bca: 431a orrs r2, r3
ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
8001bcc: 687b ldr r3, [r7, #4]
8001bce: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8001bd2: 4619 mov r1, r3
8001bd4: f44f 7300 mov.w r3, #512 @ 0x200
8001bd8: 623b str r3, [r7, #32]
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001bda: 6a3b ldr r3, [r7, #32]
8001bdc: fa93 f3a3 rbit r3, r3
8001be0: 61fb str r3, [r7, #28]
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8001be2: 69fb ldr r3, [r7, #28]
8001be4: fab3 f383 clz r3, r3
8001be8: b2db uxtb r3, r3
8001bea: fa01 f303 lsl.w r3, r1, r3
hadc->Init.EOCSelection |
8001bee: 431a orrs r2, r3
hadc->Init.ChannelsBank |
8001bf0: 687b ldr r3, [r7, #4]
8001bf2: 6a1b ldr r3, [r3, #32]
ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
8001bf4: 431a orrs r2, r3
ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
8001bf6: 687b ldr r3, [r7, #4]
8001bf8: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8001bfc: 4619 mov r1, r3
8001bfe: 2302 movs r3, #2
8001c00: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001c02: 6abb ldr r3, [r7, #40] @ 0x28
8001c04: fa93 f3a3 rbit r3, r3
8001c08: 627b str r3, [r7, #36] @ 0x24
return result;
8001c0a: 6a7b ldr r3, [r7, #36] @ 0x24
8001c0c: fab3 f383 clz r3, r3
8001c10: b2db uxtb r3, r3
8001c12: fa01 f303 lsl.w r3, r1, r3
hadc->Init.ChannelsBank |
8001c16: 4313 orrs r3, r2
tmp_cr2 |= (hadc->Init.DataAlign |
8001c18: 6afa ldr r2, [r7, #44] @ 0x2c
8001c1a: 4313 orrs r3, r2
8001c1c: 62fb str r3, [r7, #44] @ 0x2c
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8001c1e: 687b ldr r3, [r7, #4]
8001c20: 6b5b ldr r3, [r3, #52] @ 0x34
8001c22: 2b10 cmp r3, #16
8001c24: d007 beq.n 8001c36 <HAL_ADC_Init+0x102>
{
tmp_cr2 |= ( hadc->Init.ExternalTrigConv |
8001c26: 687b ldr r3, [r7, #4]
8001c28: 6b5a ldr r2, [r3, #52] @ 0x34
hadc->Init.ExternalTrigConvEdge );
8001c2a: 687b ldr r3, [r7, #4]
8001c2c: 6b9b ldr r3, [r3, #56] @ 0x38
tmp_cr2 |= ( hadc->Init.ExternalTrigConv |
8001c2e: 4313 orrs r3, r2
8001c30: 6afa ldr r2, [r7, #44] @ 0x2c
8001c32: 4313 orrs r3, r2
8001c34: 62fb str r3, [r7, #44] @ 0x2c
/* - resolution */
/* - auto power off (LowPowerAutoPowerOff mode) */
/* - scan mode */
/* - discontinuous mode disable/enable */
/* - discontinuous mode number of conversions */
if (ADC_IS_ENABLE(hadc) == RESET)
8001c36: 687b ldr r3, [r7, #4]
8001c38: 681b ldr r3, [r3, #0]
8001c3a: 681b ldr r3, [r3, #0]
8001c3c: f003 0340 and.w r3, r3, #64 @ 0x40
8001c40: 2b40 cmp r3, #64 @ 0x40
8001c42: d04f beq.n 8001ce4 <HAL_ADC_Init+0x1b0>
{
tmp_cr2 |= hadc->Init.LowPowerAutoWait;
8001c44: 687b ldr r3, [r7, #4]
8001c46: 699b ldr r3, [r3, #24]
8001c48: 6afa ldr r2, [r7, #44] @ 0x2c
8001c4a: 4313 orrs r3, r2
8001c4c: 62fb str r3, [r7, #44] @ 0x2c
tmp_cr1 |= (hadc->Init.Resolution |
8001c4e: 687b ldr r3, [r7, #4]
8001c50: 689a ldr r2, [r3, #8]
hadc->Init.LowPowerAutoPowerOff |
8001c52: 687b ldr r3, [r7, #4]
8001c54: 69db ldr r3, [r3, #28]
tmp_cr1 |= (hadc->Init.Resolution |
8001c56: 4313 orrs r3, r2
ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) );
8001c58: 687a ldr r2, [r7, #4]
8001c5a: 6912 ldr r2, [r2, #16]
8001c5c: f5b2 7f80 cmp.w r2, #256 @ 0x100
8001c60: d003 beq.n 8001c6a <HAL_ADC_Init+0x136>
8001c62: 687a ldr r2, [r7, #4]
8001c64: 6912 ldr r2, [r2, #16]
8001c66: 2a01 cmp r2, #1
8001c68: d102 bne.n 8001c70 <HAL_ADC_Init+0x13c>
8001c6a: f44f 7280 mov.w r2, #256 @ 0x100
8001c6e: e000 b.n 8001c72 <HAL_ADC_Init+0x13e>
8001c70: 2200 movs r2, #0
hadc->Init.LowPowerAutoPowerOff |
8001c72: 4313 orrs r3, r2
tmp_cr1 |= (hadc->Init.Resolution |
8001c74: 6b3a ldr r2, [r7, #48] @ 0x30
8001c76: 4313 orrs r3, r2
8001c78: 633b str r3, [r7, #48] @ 0x30
/* Enable discontinuous mode only if continuous mode is disabled */
/* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
/* discontinuous is set anyway, but has no effect on ADC HW. */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8001c7a: 687b ldr r3, [r7, #4]
8001c7c: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
8001c80: 2b01 cmp r3, #1
8001c82: d125 bne.n 8001cd0 <HAL_ADC_Init+0x19c>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8001c84: 687b ldr r3, [r7, #4]
8001c86: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8001c8a: 2b00 cmp r3, #0
8001c8c: d114 bne.n 8001cb8 <HAL_ADC_Init+0x184>
{
/* Enable the selected ADC regular discontinuous mode */
/* Set the number of channels to be converted in discontinuous mode */
SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
8001c8e: 687b ldr r3, [r7, #4]
8001c90: 6b1b ldr r3, [r3, #48] @ 0x30
8001c92: 3b01 subs r3, #1
8001c94: f44f 4260 mov.w r2, #57344 @ 0xe000
8001c98: 61ba str r2, [r7, #24]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001c9a: 69ba ldr r2, [r7, #24]
8001c9c: fa92 f2a2 rbit r2, r2
8001ca0: 617a str r2, [r7, #20]
return result;
8001ca2: 697a ldr r2, [r7, #20]
8001ca4: fab2 f282 clz r2, r2
8001ca8: b2d2 uxtb r2, r2
8001caa: 4093 lsls r3, r2
8001cac: f443 6300 orr.w r3, r3, #2048 @ 0x800
8001cb0: 6b3a ldr r2, [r7, #48] @ 0x30
8001cb2: 4313 orrs r3, r2
8001cb4: 633b str r3, [r7, #48] @ 0x30
8001cb6: e00b b.n 8001cd0 <HAL_ADC_Init+0x19c>
{
/* ADC regular group settings continuous and sequencer discontinuous*/
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8001cb8: 687b ldr r3, [r7, #4]
8001cba: 6cdb ldr r3, [r3, #76] @ 0x4c
8001cbc: f043 0220 orr.w r2, r3, #32
8001cc0: 687b ldr r3, [r7, #4]
8001cc2: 64da str r2, [r3, #76] @ 0x4c
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001cc4: 687b ldr r3, [r7, #4]
8001cc6: 6d1b ldr r3, [r3, #80] @ 0x50
8001cc8: f043 0201 orr.w r2, r3, #1
8001ccc: 687b ldr r3, [r7, #4]
8001cce: 651a str r2, [r3, #80] @ 0x50
else
{
/* do nothing */
}
/* Update ADC configuration register CR1 with previous settings */
MODIFY_REG(hadc->Instance->CR1,
8001cd0: 687b ldr r3, [r7, #4]
8001cd2: 681b ldr r3, [r3, #0]
8001cd4: 685a ldr r2, [r3, #4]
8001cd6: 4b37 ldr r3, [pc, #220] @ (8001db4 <HAL_ADC_Init+0x280>)
8001cd8: 4013 ands r3, r2
8001cda: 687a ldr r2, [r7, #4]
8001cdc: 6812 ldr r2, [r2, #0]
8001cde: 6b39 ldr r1, [r7, #48] @ 0x30
8001ce0: 430b orrs r3, r1
8001ce2: 6053 str r3, [r2, #4]
ADC_CR1_SCAN ,
tmp_cr1 );
}
/* Update ADC configuration register CR2 with previous settings */
MODIFY_REG(hadc->Instance->CR2 ,
8001ce4: 687b ldr r3, [r7, #4]
8001ce6: 681b ldr r3, [r3, #0]
8001ce8: 689a ldr r2, [r3, #8]
8001cea: 4b33 ldr r3, [pc, #204] @ (8001db8 <HAL_ADC_Init+0x284>)
8001cec: 4013 ands r3, r2
8001cee: 687a ldr r2, [r7, #4]
8001cf0: 6812 ldr r2, [r2, #0]
8001cf2: 6af9 ldr r1, [r7, #44] @ 0x2c
8001cf4: 430b orrs r3, r1
8001cf6: 6093 str r3, [r2, #8]
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
/* conversions is forced to 0x00 for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion" */
if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
8001cf8: 687b ldr r3, [r7, #4]
8001cfa: 691b ldr r3, [r3, #16]
8001cfc: f5b3 7f80 cmp.w r3, #256 @ 0x100
8001d00: d003 beq.n 8001d0a <HAL_ADC_Init+0x1d6>
8001d02: 687b ldr r3, [r7, #4]
8001d04: 691b ldr r3, [r3, #16]
8001d06: 2b01 cmp r3, #1
8001d08: d119 bne.n 8001d3e <HAL_ADC_Init+0x20a>
{
MODIFY_REG(hadc->Instance->SQR1 ,
8001d0a: 687b ldr r3, [r7, #4]
8001d0c: 681b ldr r3, [r3, #0]
8001d0e: 6b1b ldr r3, [r3, #48] @ 0x30
8001d10: f023 71f8 bic.w r1, r3, #32505856 @ 0x1f00000
8001d14: 687b ldr r3, [r7, #4]
8001d16: 6a9b ldr r3, [r3, #40] @ 0x28
8001d18: 3b01 subs r3, #1
8001d1a: f04f 72f8 mov.w r2, #32505856 @ 0x1f00000
8001d1e: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001d20: 693a ldr r2, [r7, #16]
8001d22: fa92 f2a2 rbit r2, r2
8001d26: 60fa str r2, [r7, #12]
return result;
8001d28: 68fa ldr r2, [r7, #12]
8001d2a: fab2 f282 clz r2, r2
8001d2e: b2d2 uxtb r2, r2
8001d30: fa03 f202 lsl.w r2, r3, r2
8001d34: 687b ldr r3, [r7, #4]
8001d36: 681b ldr r3, [r3, #0]
8001d38: 430a orrs r2, r1
8001d3a: 631a str r2, [r3, #48] @ 0x30
8001d3c: e007 b.n 8001d4e <HAL_ADC_Init+0x21a>
ADC_SQR1_L ,
ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) );
}
else
{
MODIFY_REG(hadc->Instance->SQR1,
8001d3e: 687b ldr r3, [r7, #4]
8001d40: 681b ldr r3, [r3, #0]
8001d42: 6b1a ldr r2, [r3, #48] @ 0x30
8001d44: 687b ldr r3, [r7, #4]
8001d46: 681b ldr r3, [r3, #0]
8001d48: f022 72f8 bic.w r2, r2, #32505856 @ 0x1f00000
8001d4c: 631a str r2, [r3, #48] @ 0x30
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CR2 (excluding execution control bits ADON, */
/* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */
if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON |
8001d4e: 687b ldr r3, [r7, #4]
8001d50: 681b ldr r3, [r3, #0]
8001d52: 689a ldr r2, [r3, #8]
8001d54: 4b19 ldr r3, [pc, #100] @ (8001dbc <HAL_ADC_Init+0x288>)
8001d56: 4013 ands r3, r2
8001d58: 6afa ldr r2, [r7, #44] @ 0x2c
8001d5a: 429a cmp r2, r3
8001d5c: d10b bne.n 8001d76 <HAL_ADC_Init+0x242>
ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL ))
== tmp_cr2)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001d5e: 687b ldr r3, [r7, #4]
8001d60: 2200 movs r2, #0
8001d62: 651a str r2, [r3, #80] @ 0x50
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001d64: 687b ldr r3, [r7, #4]
8001d66: 6cdb ldr r3, [r3, #76] @ 0x4c
8001d68: f023 0303 bic.w r3, r3, #3
8001d6c: f043 0201 orr.w r2, r3, #1
8001d70: 687b ldr r3, [r7, #4]
8001d72: 64da str r2, [r3, #76] @ 0x4c
8001d74: e014 b.n 8001da0 <HAL_ADC_Init+0x26c>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8001d76: 687b ldr r3, [r7, #4]
8001d78: 6cdb ldr r3, [r3, #76] @ 0x4c
8001d7a: f023 0312 bic.w r3, r3, #18
8001d7e: f043 0210 orr.w r2, r3, #16
8001d82: 687b ldr r3, [r7, #4]
8001d84: 64da str r2, [r3, #76] @ 0x4c
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001d86: 687b ldr r3, [r7, #4]
8001d88: 6d1b ldr r3, [r3, #80] @ 0x50
8001d8a: f043 0201 orr.w r2, r3, #1
8001d8e: 687b ldr r3, [r7, #4]
8001d90: 651a str r2, [r3, #80] @ 0x50
tmp_hal_status = HAL_ERROR;
8001d92: 2301 movs r3, #1
8001d94: f887 3037 strb.w r3, [r7, #55] @ 0x37
8001d98: e002 b.n 8001da0 <HAL_ADC_Init+0x26c>
}
}
else
{
tmp_hal_status = HAL_ERROR;
8001d9a: 2301 movs r3, #1
8001d9c: f887 3037 strb.w r3, [r7, #55] @ 0x37
}
/* Return function status */
return tmp_hal_status;
8001da0: f897 3037 ldrb.w r3, [r7, #55] @ 0x37
}
8001da4: 4618 mov r0, r3
8001da6: 3738 adds r7, #56 @ 0x38
8001da8: 46bd mov sp, r7
8001daa: bd80 pop {r7, pc}
8001dac: 40023800 .word 0x40023800
8001db0: 40012700 .word 0x40012700
8001db4: fcfc16ff .word 0xfcfc16ff
8001db8: c0fff189 .word 0xc0fff189
8001dbc: bf80fffe .word 0xbf80fffe
08001dc0 <HAL_ADC_Start>:
* Interruptions enabled in this function: None.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
8001dc0: b580 push {r7, lr}
8001dc2: b084 sub sp, #16
8001dc4: af00 add r7, sp, #0
8001dc6: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001dc8: 2300 movs r3, #0
8001dca: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
8001dcc: 687b ldr r3, [r7, #4]
8001dce: f893 3048 ldrb.w r3, [r3, #72] @ 0x48
8001dd2: 2b01 cmp r3, #1
8001dd4: d101 bne.n 8001dda <HAL_ADC_Start+0x1a>
8001dd6: 2302 movs r3, #2
8001dd8: e04e b.n 8001e78 <HAL_ADC_Start+0xb8>
8001dda: 687b ldr r3, [r7, #4]
8001ddc: 2201 movs r2, #1
8001dde: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
8001de2: 6878 ldr r0, [r7, #4]
8001de4: f000 fa80 bl 80022e8 <ADC_Enable>
8001de8: 4603 mov r3, r0
8001dea: 73fb strb r3, [r7, #15]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
8001dec: 7bfb ldrb r3, [r7, #15]
8001dee: 2b00 cmp r3, #0
8001df0: d141 bne.n 8001e76 <HAL_ADC_Start+0xb6>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
8001df2: 687b ldr r3, [r7, #4]
8001df4: 6cdb ldr r3, [r3, #76] @ 0x4c
8001df6: f423 63e0 bic.w r3, r3, #1792 @ 0x700
8001dfa: f023 0301 bic.w r3, r3, #1
8001dfe: f443 7280 orr.w r2, r3, #256 @ 0x100
8001e02: 687b ldr r3, [r7, #4]
8001e04: 64da str r2, [r3, #76] @ 0x4c
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8001e06: 687b ldr r3, [r7, #4]
8001e08: 681b ldr r3, [r3, #0]
8001e0a: 685b ldr r3, [r3, #4]
8001e0c: f403 6380 and.w r3, r3, #1024 @ 0x400
8001e10: 2b00 cmp r3, #0
8001e12: d007 beq.n 8001e24 <HAL_ADC_Start+0x64>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8001e14: 687b ldr r3, [r7, #4]
8001e16: 6cdb ldr r3, [r3, #76] @ 0x4c
8001e18: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8001e1c: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8001e20: 687b ldr r3, [r7, #4]
8001e22: 64da str r2, [r3, #76] @ 0x4c
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8001e24: 687b ldr r3, [r7, #4]
8001e26: 6cdb ldr r3, [r3, #76] @ 0x4c
8001e28: f403 5380 and.w r3, r3, #4096 @ 0x1000
8001e2c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8001e30: d106 bne.n 8001e40 <HAL_ADC_Start+0x80>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8001e32: 687b ldr r3, [r7, #4]
8001e34: 6d1b ldr r3, [r3, #80] @ 0x50
8001e36: f023 0206 bic.w r2, r3, #6
8001e3a: 687b ldr r3, [r7, #4]
8001e3c: 651a str r2, [r3, #80] @ 0x50
8001e3e: e002 b.n 8001e46 <HAL_ADC_Start+0x86>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8001e40: 687b ldr r3, [r7, #4]
8001e42: 2200 movs r2, #0
8001e44: 651a str r2, [r3, #80] @ 0x50
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8001e46: 687b ldr r3, [r7, #4]
8001e48: 2200 movs r2, #0
8001e4a: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
8001e4e: 687b ldr r3, [r7, #4]
8001e50: 681b ldr r3, [r3, #0]
8001e52: f06f 0222 mvn.w r2, #34 @ 0x22
8001e56: 601a str r2, [r3, #0]
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
8001e58: 687b ldr r3, [r7, #4]
8001e5a: 681b ldr r3, [r3, #0]
8001e5c: 689b ldr r3, [r3, #8]
8001e5e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
8001e62: 2b00 cmp r3, #0
8001e64: d107 bne.n 8001e76 <HAL_ADC_Start+0xb6>
{
/* Start ADC conversion on regular group */
SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
8001e66: 687b ldr r3, [r7, #4]
8001e68: 681b ldr r3, [r3, #0]
8001e6a: 689a ldr r2, [r3, #8]
8001e6c: 687b ldr r3, [r7, #4]
8001e6e: 681b ldr r3, [r3, #0]
8001e70: f042 4280 orr.w r2, r2, #1073741824 @ 0x40000000
8001e74: 609a str r2, [r3, #8]
}
}
/* Return function status */
return tmp_hal_status;
8001e76: 7bfb ldrb r3, [r7, #15]
}
8001e78: 4618 mov r0, r3
8001e7a: 3710 adds r7, #16
8001e7c: 46bd mov sp, r7
8001e7e: bd80 pop {r7, pc}
08001e80 <HAL_ADC_Stop>:
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
{
8001e80: b580 push {r7, lr}
8001e82: b084 sub sp, #16
8001e84: af00 add r7, sp, #0
8001e86: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001e88: 2300 movs r3, #0
8001e8a: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
8001e8c: 687b ldr r3, [r7, #4]
8001e8e: f893 3048 ldrb.w r3, [r3, #72] @ 0x48
8001e92: 2b01 cmp r3, #1
8001e94: d101 bne.n 8001e9a <HAL_ADC_Stop+0x1a>
8001e96: 2302 movs r3, #2
8001e98: e01a b.n 8001ed0 <HAL_ADC_Stop+0x50>
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 2201 movs r2, #1
8001e9e: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Stop potential conversion on going, on regular and injected groups */
/* Disable ADC peripheral */
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
8001ea2: 6878 ldr r0, [r7, #4]
8001ea4: f000 fa7c bl 80023a0 <ADC_ConversionStop_Disable>
8001ea8: 4603 mov r3, r0
8001eaa: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
8001eac: 7bfb ldrb r3, [r7, #15]
8001eae: 2b00 cmp r3, #0
8001eb0: d109 bne.n 8001ec6 <HAL_ADC_Stop+0x46>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001eb2: 687b ldr r3, [r7, #4]
8001eb4: 6cdb ldr r3, [r3, #76] @ 0x4c
8001eb6: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8001eba: f023 0301 bic.w r3, r3, #1
8001ebe: f043 0201 orr.w r2, r3, #1
8001ec2: 687b ldr r3, [r7, #4]
8001ec4: 64da str r2, [r3, #76] @ 0x4c
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8001ec6: 687b ldr r3, [r7, #4]
8001ec8: 2200 movs r2, #0
8001eca: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Return function status */
return tmp_hal_status;
8001ece: 7bfb ldrb r3, [r7, #15]
}
8001ed0: 4618 mov r0, r3
8001ed2: 3710 adds r7, #16
8001ed4: 46bd mov sp, r7
8001ed6: bd80 pop {r7, pc}
08001ed8 <HAL_ADC_PollForConversion>:
* @param hadc ADC handle
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
8001ed8: b580 push {r7, lr}
8001eda: b084 sub sp, #16
8001edc: af00 add r7, sp, #0
8001ede: 6078 str r0, [r7, #4]
8001ee0: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8001ee2: 2300 movs r3, #0
8001ee4: 60fb str r3, [r7, #12]
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8001ee6: 687b ldr r3, [r7, #4]
8001ee8: 681b ldr r3, [r3, #0]
8001eea: 689b ldr r3, [r3, #8]
8001eec: f403 6380 and.w r3, r3, #1024 @ 0x400
8001ef0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8001ef4: d113 bne.n 8001f1e <HAL_ADC_PollForConversion+0x46>
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
8001ef6: 687b ldr r3, [r7, #4]
8001ef8: 681b ldr r3, [r3, #0]
8001efa: 689b ldr r3, [r3, #8]
8001efc: f403 7380 and.w r3, r3, #256 @ 0x100
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8001f00: f5b3 7f80 cmp.w r3, #256 @ 0x100
8001f04: d10b bne.n 8001f1e <HAL_ADC_PollForConversion+0x46>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8001f06: 687b ldr r3, [r7, #4]
8001f08: 6cdb ldr r3, [r3, #76] @ 0x4c
8001f0a: f043 0220 orr.w r2, r3, #32
8001f0e: 687b ldr r3, [r7, #4]
8001f10: 64da str r2, [r3, #76] @ 0x4c
/* Process unlocked */
__HAL_UNLOCK(hadc);
8001f12: 687b ldr r3, [r7, #4]
8001f14: 2200 movs r2, #0
8001f16: f883 2048 strb.w r2, [r3, #72] @ 0x48
return HAL_ERROR;
8001f1a: 2301 movs r3, #1
8001f1c: e068 b.n 8001ff0 <HAL_ADC_PollForConversion+0x118>
}
/* Get tick count */
tickstart = HAL_GetTick();
8001f1e: f7ff fddd bl 8001adc <HAL_GetTick>
8001f22: 60f8 str r0, [r7, #12]
/* Wait until End of Conversion flag is raised */
while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
8001f24: e021 b.n 8001f6a <HAL_ADC_PollForConversion+0x92>
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
8001f26: 683b ldr r3, [r7, #0]
8001f28: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001f2c: d01d beq.n 8001f6a <HAL_ADC_PollForConversion+0x92>
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
8001f2e: 683b ldr r3, [r7, #0]
8001f30: 2b00 cmp r3, #0
8001f32: d007 beq.n 8001f44 <HAL_ADC_PollForConversion+0x6c>
8001f34: f7ff fdd2 bl 8001adc <HAL_GetTick>
8001f38: 4602 mov r2, r0
8001f3a: 68fb ldr r3, [r7, #12]
8001f3c: 1ad3 subs r3, r2, r3
8001f3e: 683a ldr r2, [r7, #0]
8001f40: 429a cmp r2, r3
8001f42: d212 bcs.n 8001f6a <HAL_ADC_PollForConversion+0x92>
{
/* New check to avoid false timeout detection in case of preemption */
if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
8001f44: 687b ldr r3, [r7, #4]
8001f46: 681b ldr r3, [r3, #0]
8001f48: 681b ldr r3, [r3, #0]
8001f4a: f003 0302 and.w r3, r3, #2
8001f4e: 2b00 cmp r3, #0
8001f50: d10b bne.n 8001f6a <HAL_ADC_PollForConversion+0x92>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
8001f52: 687b ldr r3, [r7, #4]
8001f54: 6cdb ldr r3, [r3, #76] @ 0x4c
8001f56: f043 0204 orr.w r2, r3, #4
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 64da str r2, [r3, #76] @ 0x4c
/* Process unlocked */
__HAL_UNLOCK(hadc);
8001f5e: 687b ldr r3, [r7, #4]
8001f60: 2200 movs r2, #0
8001f62: f883 2048 strb.w r2, [r3, #72] @ 0x48
return HAL_TIMEOUT;
8001f66: 2303 movs r3, #3
8001f68: e042 b.n 8001ff0 <HAL_ADC_PollForConversion+0x118>
while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
8001f6a: 687b ldr r3, [r7, #4]
8001f6c: 681b ldr r3, [r3, #0]
8001f6e: 681b ldr r3, [r3, #0]
8001f70: f003 0302 and.w r3, r3, #2
8001f74: 2b00 cmp r3, #0
8001f76: d0d6 beq.n 8001f26 <HAL_ADC_PollForConversion+0x4e>
}
/* Clear end of conversion flag of regular group if low power feature */
/* "Auto Wait" is disabled, to not interfere with this feature until data */
/* register is read using function HAL_ADC_GetValue(). */
if (hadc->Init.LowPowerAutoWait == DISABLE)
8001f78: 687b ldr r3, [r7, #4]
8001f7a: 699b ldr r3, [r3, #24]
8001f7c: 2b00 cmp r3, #0
8001f7e: d104 bne.n 8001f8a <HAL_ADC_PollForConversion+0xb2>
{
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
8001f80: 687b ldr r3, [r7, #4]
8001f82: 681b ldr r3, [r3, #0]
8001f84: f06f 0212 mvn.w r2, #18
8001f88: 601a str r2, [r3, #0]
}
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8001f8a: 687b ldr r3, [r7, #4]
8001f8c: 6cdb ldr r3, [r3, #76] @ 0x4c
8001f8e: f443 7200 orr.w r2, r3, #512 @ 0x200
8001f92: 687b ldr r3, [r7, #4]
8001f94: 64da str r2, [r3, #76] @ 0x4c
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32L1, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001f96: 687b ldr r3, [r7, #4]
8001f98: 681b ldr r3, [r3, #0]
8001f9a: 689b ldr r3, [r3, #8]
8001f9c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
8001fa0: 2b00 cmp r3, #0
8001fa2: d124 bne.n 8001fee <HAL_ADC_PollForConversion+0x116>
(hadc->Init.ContinuousConvMode == DISABLE) &&
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001faa: 2b00 cmp r3, #0
8001fac: d11f bne.n 8001fee <HAL_ADC_PollForConversion+0x116>
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8001fae: 687b ldr r3, [r7, #4]
8001fb0: 681b ldr r3, [r3, #0]
8001fb2: 6b1b ldr r3, [r3, #48] @ 0x30
8001fb4: f003 73f8 and.w r3, r3, #32505856 @ 0x1f00000
(hadc->Init.ContinuousConvMode == DISABLE) &&
8001fb8: 2b00 cmp r3, #0
8001fba: d006 beq.n 8001fca <HAL_ADC_PollForConversion+0xf2>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
8001fbc: 687b ldr r3, [r7, #4]
8001fbe: 681b ldr r3, [r3, #0]
8001fc0: 689b ldr r3, [r3, #8]
8001fc2: f403 6380 and.w r3, r3, #1024 @ 0x400
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8001fc6: 2b00 cmp r3, #0
8001fc8: d111 bne.n 8001fee <HAL_ADC_PollForConversion+0x116>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8001fca: 687b ldr r3, [r7, #4]
8001fcc: 6cdb ldr r3, [r3, #76] @ 0x4c
8001fce: f423 7280 bic.w r2, r3, #256 @ 0x100
8001fd2: 687b ldr r3, [r7, #4]
8001fd4: 64da str r2, [r3, #76] @ 0x4c
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8001fd6: 687b ldr r3, [r7, #4]
8001fd8: 6cdb ldr r3, [r3, #76] @ 0x4c
8001fda: f403 5380 and.w r3, r3, #4096 @ 0x1000
8001fde: 2b00 cmp r3, #0
8001fe0: d105 bne.n 8001fee <HAL_ADC_PollForConversion+0x116>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8001fe2: 687b ldr r3, [r7, #4]
8001fe4: 6cdb ldr r3, [r3, #76] @ 0x4c
8001fe6: f043 0201 orr.w r2, r3, #1
8001fea: 687b ldr r3, [r7, #4]
8001fec: 64da str r2, [r3, #76] @ 0x4c
}
}
/* Return ADC state */
return HAL_OK;
8001fee: 2300 movs r3, #0
}
8001ff0: 4618 mov r0, r3
8001ff2: 3710 adds r7, #16
8001ff4: 46bd mov sp, r7
8001ff6: bd80 pop {r7, pc}
08001ff8 <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
8001ff8: b480 push {r7}
8001ffa: b083 sub sp, #12
8001ffc: af00 add r7, sp, #0
8001ffe: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
8002000: 687b ldr r3, [r7, #4]
8002002: 681b ldr r3, [r3, #0]
8002004: 6d9b ldr r3, [r3, #88] @ 0x58
}
8002006: 4618 mov r0, r3
8002008: 370c adds r7, #12
800200a: 46bd mov sp, r7
800200c: bc80 pop {r7}
800200e: 4770 bx lr
08002010 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8002010: b480 push {r7}
8002012: b085 sub sp, #20
8002014: af00 add r7, sp, #0
8002016: 6078 str r0, [r7, #4]
8002018: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800201a: 2300 movs r3, #0
800201c: 73fb strb r3, [r7, #15]
__IO uint32_t wait_loop_index = 0;
800201e: 2300 movs r3, #0
8002020: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8002022: 687b ldr r3, [r7, #4]
8002024: f893 3048 ldrb.w r3, [r3, #72] @ 0x48
8002028: 2b01 cmp r3, #1
800202a: d101 bne.n 8002030 <HAL_ADC_ConfigChannel+0x20>
800202c: 2302 movs r3, #2
800202e: e14f b.n 80022d0 <HAL_ADC_ConfigChannel+0x2c0>
8002030: 687b ldr r3, [r7, #4]
8002032: 2201 movs r2, #1
8002034: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Regular sequence configuration */
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
8002038: 683b ldr r3, [r7, #0]
800203a: 685b ldr r3, [r3, #4]
800203c: 2b06 cmp r3, #6
800203e: d81c bhi.n 800207a <HAL_ADC_ConfigChannel+0x6a>
{
MODIFY_REG(hadc->Instance->SQR5,
8002040: 687b ldr r3, [r7, #4]
8002042: 681b ldr r3, [r3, #0]
8002044: 6c19 ldr r1, [r3, #64] @ 0x40
8002046: 683b ldr r3, [r7, #0]
8002048: 685a ldr r2, [r3, #4]
800204a: 4613 mov r3, r2
800204c: 009b lsls r3, r3, #2
800204e: 4413 add r3, r2
8002050: 3b05 subs r3, #5
8002052: 221f movs r2, #31
8002054: fa02 f303 lsl.w r3, r2, r3
8002058: 43db mvns r3, r3
800205a: 4019 ands r1, r3
800205c: 683b ldr r3, [r7, #0]
800205e: 6818 ldr r0, [r3, #0]
8002060: 683b ldr r3, [r7, #0]
8002062: 685a ldr r2, [r3, #4]
8002064: 4613 mov r3, r2
8002066: 009b lsls r3, r3, #2
8002068: 4413 add r3, r2
800206a: 3b05 subs r3, #5
800206c: fa00 f203 lsl.w r2, r0, r3
8002070: 687b ldr r3, [r7, #4]
8002072: 681b ldr r3, [r3, #0]
8002074: 430a orrs r2, r1
8002076: 641a str r2, [r3, #64] @ 0x40
8002078: e07e b.n 8002178 <HAL_ADC_ConfigChannel+0x168>
ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
800207a: 683b ldr r3, [r7, #0]
800207c: 685b ldr r3, [r3, #4]
800207e: 2b0c cmp r3, #12
8002080: d81c bhi.n 80020bc <HAL_ADC_ConfigChannel+0xac>
{
MODIFY_REG(hadc->Instance->SQR4,
8002082: 687b ldr r3, [r7, #4]
8002084: 681b ldr r3, [r3, #0]
8002086: 6bd9 ldr r1, [r3, #60] @ 0x3c
8002088: 683b ldr r3, [r7, #0]
800208a: 685a ldr r2, [r3, #4]
800208c: 4613 mov r3, r2
800208e: 009b lsls r3, r3, #2
8002090: 4413 add r3, r2
8002092: 3b23 subs r3, #35 @ 0x23
8002094: 221f movs r2, #31
8002096: fa02 f303 lsl.w r3, r2, r3
800209a: 43db mvns r3, r3
800209c: 4019 ands r1, r3
800209e: 683b ldr r3, [r7, #0]
80020a0: 6818 ldr r0, [r3, #0]
80020a2: 683b ldr r3, [r7, #0]
80020a4: 685a ldr r2, [r3, #4]
80020a6: 4613 mov r3, r2
80020a8: 009b lsls r3, r3, #2
80020aa: 4413 add r3, r2
80020ac: 3b23 subs r3, #35 @ 0x23
80020ae: fa00 f203 lsl.w r2, r0, r3
80020b2: 687b ldr r3, [r7, #4]
80020b4: 681b ldr r3, [r3, #0]
80020b6: 430a orrs r2, r1
80020b8: 63da str r2, [r3, #60] @ 0x3c
80020ba: e05d b.n 8002178 <HAL_ADC_ConfigChannel+0x168>
ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 13 to 18 */
else if (sConfig->Rank < 19)
80020bc: 683b ldr r3, [r7, #0]
80020be: 685b ldr r3, [r3, #4]
80020c0: 2b12 cmp r3, #18
80020c2: d81c bhi.n 80020fe <HAL_ADC_ConfigChannel+0xee>
{
MODIFY_REG(hadc->Instance->SQR3,
80020c4: 687b ldr r3, [r7, #4]
80020c6: 681b ldr r3, [r3, #0]
80020c8: 6b99 ldr r1, [r3, #56] @ 0x38
80020ca: 683b ldr r3, [r7, #0]
80020cc: 685a ldr r2, [r3, #4]
80020ce: 4613 mov r3, r2
80020d0: 009b lsls r3, r3, #2
80020d2: 4413 add r3, r2
80020d4: 3b41 subs r3, #65 @ 0x41
80020d6: 221f movs r2, #31
80020d8: fa02 f303 lsl.w r3, r2, r3
80020dc: 43db mvns r3, r3
80020de: 4019 ands r1, r3
80020e0: 683b ldr r3, [r7, #0]
80020e2: 6818 ldr r0, [r3, #0]
80020e4: 683b ldr r3, [r7, #0]
80020e6: 685a ldr r2, [r3, #4]
80020e8: 4613 mov r3, r2
80020ea: 009b lsls r3, r3, #2
80020ec: 4413 add r3, r2
80020ee: 3b41 subs r3, #65 @ 0x41
80020f0: fa00 f203 lsl.w r2, r0, r3
80020f4: 687b ldr r3, [r7, #4]
80020f6: 681b ldr r3, [r3, #0]
80020f8: 430a orrs r2, r1
80020fa: 639a str r2, [r3, #56] @ 0x38
80020fc: e03c b.n 8002178 <HAL_ADC_ConfigChannel+0x168>
ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 19 to 24 */
else if (sConfig->Rank < 25)
80020fe: 683b ldr r3, [r7, #0]
8002100: 685b ldr r3, [r3, #4]
8002102: 2b18 cmp r3, #24
8002104: d81c bhi.n 8002140 <HAL_ADC_ConfigChannel+0x130>
{
MODIFY_REG(hadc->Instance->SQR2,
8002106: 687b ldr r3, [r7, #4]
8002108: 681b ldr r3, [r3, #0]
800210a: 6b59 ldr r1, [r3, #52] @ 0x34
800210c: 683b ldr r3, [r7, #0]
800210e: 685a ldr r2, [r3, #4]
8002110: 4613 mov r3, r2
8002112: 009b lsls r3, r3, #2
8002114: 4413 add r3, r2
8002116: 3b5f subs r3, #95 @ 0x5f
8002118: 221f movs r2, #31
800211a: fa02 f303 lsl.w r3, r2, r3
800211e: 43db mvns r3, r3
8002120: 4019 ands r1, r3
8002122: 683b ldr r3, [r7, #0]
8002124: 6818 ldr r0, [r3, #0]
8002126: 683b ldr r3, [r7, #0]
8002128: 685a ldr r2, [r3, #4]
800212a: 4613 mov r3, r2
800212c: 009b lsls r3, r3, #2
800212e: 4413 add r3, r2
8002130: 3b5f subs r3, #95 @ 0x5f
8002132: fa00 f203 lsl.w r2, r0, r3
8002136: 687b ldr r3, [r7, #4]
8002138: 681b ldr r3, [r3, #0]
800213a: 430a orrs r2, r1
800213c: 635a str r2, [r3, #52] @ 0x34
800213e: e01b b.n 8002178 <HAL_ADC_ConfigChannel+0x168>
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 25 to 28 */
else
{
MODIFY_REG(hadc->Instance->SQR1,
8002140: 687b ldr r3, [r7, #4]
8002142: 681b ldr r3, [r3, #0]
8002144: 6b19 ldr r1, [r3, #48] @ 0x30
8002146: 683b ldr r3, [r7, #0]
8002148: 685a ldr r2, [r3, #4]
800214a: 4613 mov r3, r2
800214c: 009b lsls r3, r3, #2
800214e: 4413 add r3, r2
8002150: 3b7d subs r3, #125 @ 0x7d
8002152: 221f movs r2, #31
8002154: fa02 f303 lsl.w r3, r2, r3
8002158: 43db mvns r3, r3
800215a: 4019 ands r1, r3
800215c: 683b ldr r3, [r7, #0]
800215e: 6818 ldr r0, [r3, #0]
8002160: 683b ldr r3, [r7, #0]
8002162: 685a ldr r2, [r3, #4]
8002164: 4613 mov r3, r2
8002166: 009b lsls r3, r3, #2
8002168: 4413 add r3, r2
800216a: 3b7d subs r3, #125 @ 0x7d
800216c: fa00 f203 lsl.w r2, r0, r3
8002170: 687b ldr r3, [r7, #4]
8002172: 681b ldr r3, [r3, #0]
8002174: 430a orrs r2, r1
8002176: 631a str r2, [r3, #48] @ 0x30
}
/* Channel sampling time configuration */
/* For channels 0 to 9 */
if (sConfig->Channel < ADC_CHANNEL_10)
8002178: 683b ldr r3, [r7, #0]
800217a: 681b ldr r3, [r3, #0]
800217c: 2b09 cmp r3, #9
800217e: d81a bhi.n 80021b6 <HAL_ADC_ConfigChannel+0x1a6>
{
MODIFY_REG(hadc->Instance->SMPR3,
8002180: 687b ldr r3, [r7, #4]
8002182: 681b ldr r3, [r3, #0]
8002184: 6959 ldr r1, [r3, #20]
8002186: 683b ldr r3, [r7, #0]
8002188: 681a ldr r2, [r3, #0]
800218a: 4613 mov r3, r2
800218c: 005b lsls r3, r3, #1
800218e: 4413 add r3, r2
8002190: 2207 movs r2, #7
8002192: fa02 f303 lsl.w r3, r2, r3
8002196: 43db mvns r3, r3
8002198: 4019 ands r1, r3
800219a: 683b ldr r3, [r7, #0]
800219c: 6898 ldr r0, [r3, #8]
800219e: 683b ldr r3, [r7, #0]
80021a0: 681a ldr r2, [r3, #0]
80021a2: 4613 mov r3, r2
80021a4: 005b lsls r3, r3, #1
80021a6: 4413 add r3, r2
80021a8: fa00 f203 lsl.w r2, r0, r3
80021ac: 687b ldr r3, [r7, #4]
80021ae: 681b ldr r3, [r3, #0]
80021b0: 430a orrs r2, r1
80021b2: 615a str r2, [r3, #20]
80021b4: e05d b.n 8002272 <HAL_ADC_ConfigChannel+0x262>
ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
}
/* For channels 10 to 19 */
else if (sConfig->Channel < ADC_CHANNEL_20)
80021b6: 683b ldr r3, [r7, #0]
80021b8: 681b ldr r3, [r3, #0]
80021ba: 2b13 cmp r3, #19
80021bc: d81c bhi.n 80021f8 <HAL_ADC_ConfigChannel+0x1e8>
{
MODIFY_REG(hadc->Instance->SMPR2,
80021be: 687b ldr r3, [r7, #4]
80021c0: 681b ldr r3, [r3, #0]
80021c2: 6919 ldr r1, [r3, #16]
80021c4: 683b ldr r3, [r7, #0]
80021c6: 681a ldr r2, [r3, #0]
80021c8: 4613 mov r3, r2
80021ca: 005b lsls r3, r3, #1
80021cc: 4413 add r3, r2
80021ce: 3b1e subs r3, #30
80021d0: 2207 movs r2, #7
80021d2: fa02 f303 lsl.w r3, r2, r3
80021d6: 43db mvns r3, r3
80021d8: 4019 ands r1, r3
80021da: 683b ldr r3, [r7, #0]
80021dc: 6898 ldr r0, [r3, #8]
80021de: 683b ldr r3, [r7, #0]
80021e0: 681a ldr r2, [r3, #0]
80021e2: 4613 mov r3, r2
80021e4: 005b lsls r3, r3, #1
80021e6: 4413 add r3, r2
80021e8: 3b1e subs r3, #30
80021ea: fa00 f203 lsl.w r2, r0, r3
80021ee: 687b ldr r3, [r7, #4]
80021f0: 681b ldr r3, [r3, #0]
80021f2: 430a orrs r2, r1
80021f4: 611a str r2, [r3, #16]
80021f6: e03c b.n 8002272 <HAL_ADC_ConfigChannel+0x262>
ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
/* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
/* For channels 20 to 29 for devices Cat4, Cat.5 */
else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
80021f8: 683b ldr r3, [r7, #0]
80021fa: 681b ldr r3, [r3, #0]
80021fc: 2b1d cmp r3, #29
80021fe: d81c bhi.n 800223a <HAL_ADC_ConfigChannel+0x22a>
{
MODIFY_REG(hadc->Instance->SMPR1,
8002200: 687b ldr r3, [r7, #4]
8002202: 681b ldr r3, [r3, #0]
8002204: 68d9 ldr r1, [r3, #12]
8002206: 683b ldr r3, [r7, #0]
8002208: 681a ldr r2, [r3, #0]
800220a: 4613 mov r3, r2
800220c: 005b lsls r3, r3, #1
800220e: 4413 add r3, r2
8002210: 3b3c subs r3, #60 @ 0x3c
8002212: 2207 movs r2, #7
8002214: fa02 f303 lsl.w r3, r2, r3
8002218: 43db mvns r3, r3
800221a: 4019 ands r1, r3
800221c: 683b ldr r3, [r7, #0]
800221e: 6898 ldr r0, [r3, #8]
8002220: 683b ldr r3, [r7, #0]
8002222: 681a ldr r2, [r3, #0]
8002224: 4613 mov r3, r2
8002226: 005b lsls r3, r3, #1
8002228: 4413 add r3, r2
800222a: 3b3c subs r3, #60 @ 0x3c
800222c: fa00 f203 lsl.w r2, r0, r3
8002230: 687b ldr r3, [r7, #4]
8002232: 681b ldr r3, [r3, #0]
8002234: 430a orrs r2, r1
8002236: 60da str r2, [r3, #12]
8002238: e01b b.n 8002272 <HAL_ADC_ConfigChannel+0x262>
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
/* For channels 30 to 31 for devices Cat4, Cat.5 */
else
{
ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
800223a: 687b ldr r3, [r7, #4]
800223c: 681b ldr r3, [r3, #0]
800223e: 6dd9 ldr r1, [r3, #92] @ 0x5c
8002240: 683b ldr r3, [r7, #0]
8002242: 681a ldr r2, [r3, #0]
8002244: 4613 mov r3, r2
8002246: 005b lsls r3, r3, #1
8002248: 4413 add r3, r2
800224a: 3b5a subs r3, #90 @ 0x5a
800224c: 2207 movs r2, #7
800224e: fa02 f303 lsl.w r3, r2, r3
8002252: 43db mvns r3, r3
8002254: 4019 ands r1, r3
8002256: 683b ldr r3, [r7, #0]
8002258: 6898 ldr r0, [r3, #8]
800225a: 683b ldr r3, [r7, #0]
800225c: 681a ldr r2, [r3, #0]
800225e: 4613 mov r3, r2
8002260: 005b lsls r3, r3, #1
8002262: 4413 add r3, r2
8002264: 3b5a subs r3, #90 @ 0x5a
8002266: fa00 f203 lsl.w r2, r0, r3
800226a: 687b ldr r3, [r7, #4]
800226c: 681b ldr r3, [r3, #0]
800226e: 430a orrs r2, r1
8002270: 65da str r2, [r3, #92] @ 0x5c
}
/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
/* and VREFINT measurement path. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
8002272: 683b ldr r3, [r7, #0]
8002274: 681b ldr r3, [r3, #0]
8002276: 2b10 cmp r3, #16
8002278: d003 beq.n 8002282 <HAL_ADC_ConfigChannel+0x272>
(sConfig->Channel == ADC_CHANNEL_VREFINT) )
800227a: 683b ldr r3, [r7, #0]
800227c: 681b ldr r3, [r3, #0]
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
800227e: 2b11 cmp r3, #17
8002280: d121 bne.n 80022c6 <HAL_ADC_ConfigChannel+0x2b6>
{
if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET)
8002282: 4b16 ldr r3, [pc, #88] @ (80022dc <HAL_ADC_ConfigChannel+0x2cc>)
8002284: 685b ldr r3, [r3, #4]
8002286: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800228a: 2b00 cmp r3, #0
800228c: d11b bne.n 80022c6 <HAL_ADC_ConfigChannel+0x2b6>
{
SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
800228e: 4b13 ldr r3, [pc, #76] @ (80022dc <HAL_ADC_ConfigChannel+0x2cc>)
8002290: 685b ldr r3, [r3, #4]
8002292: 4a12 ldr r2, [pc, #72] @ (80022dc <HAL_ADC_ConfigChannel+0x2cc>)
8002294: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8002298: 6053 str r3, [r2, #4]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
800229a: 683b ldr r3, [r7, #0]
800229c: 681b ldr r3, [r3, #0]
800229e: 2b10 cmp r3, #16
80022a0: d111 bne.n 80022c6 <HAL_ADC_ConfigChannel+0x2b6>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
80022a2: 4b0f ldr r3, [pc, #60] @ (80022e0 <HAL_ADC_ConfigChannel+0x2d0>)
80022a4: 681b ldr r3, [r3, #0]
80022a6: 4a0f ldr r2, [pc, #60] @ (80022e4 <HAL_ADC_ConfigChannel+0x2d4>)
80022a8: fba2 2303 umull r2, r3, r2, r3
80022ac: 0c9a lsrs r2, r3, #18
80022ae: 4613 mov r3, r2
80022b0: 009b lsls r3, r3, #2
80022b2: 4413 add r3, r2
80022b4: 005b lsls r3, r3, #1
80022b6: 60bb str r3, [r7, #8]
while(wait_loop_index != 0)
80022b8: e002 b.n 80022c0 <HAL_ADC_ConfigChannel+0x2b0>
{
wait_loop_index--;
80022ba: 68bb ldr r3, [r7, #8]
80022bc: 3b01 subs r3, #1
80022be: 60bb str r3, [r7, #8]
while(wait_loop_index != 0)
80022c0: 68bb ldr r3, [r7, #8]
80022c2: 2b00 cmp r3, #0
80022c4: d1f9 bne.n 80022ba <HAL_ADC_ConfigChannel+0x2aa>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80022c6: 687b ldr r3, [r7, #4]
80022c8: 2200 movs r2, #0
80022ca: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Return function status */
return tmp_hal_status;
80022ce: 7bfb ldrb r3, [r7, #15]
}
80022d0: 4618 mov r0, r3
80022d2: 3714 adds r7, #20
80022d4: 46bd mov sp, r7
80022d6: bc80 pop {r7}
80022d8: 4770 bx lr
80022da: bf00 nop
80022dc: 40012700 .word 0x40012700
80022e0: 20000000 .word 0x20000000
80022e4: 431bde83 .word 0x431bde83
080022e8 <ADC_Enable>:
* "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
80022e8: b580 push {r7, lr}
80022ea: b084 sub sp, #16
80022ec: af00 add r7, sp, #0
80022ee: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
80022f0: 2300 movs r3, #0
80022f2: 60fb str r3, [r7, #12]
__IO uint32_t wait_loop_index = 0;
80022f4: 2300 movs r3, #0
80022f6: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (ADC_IS_ENABLE(hadc) == RESET)
80022f8: 687b ldr r3, [r7, #4]
80022fa: 681b ldr r3, [r3, #0]
80022fc: 681b ldr r3, [r3, #0]
80022fe: f003 0340 and.w r3, r3, #64 @ 0x40
8002302: 2b40 cmp r3, #64 @ 0x40
8002304: d043 beq.n 800238e <ADC_Enable+0xa6>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
8002306: 687b ldr r3, [r7, #4]
8002308: 681b ldr r3, [r3, #0]
800230a: 689a ldr r2, [r3, #8]
800230c: 687b ldr r3, [r7, #4]
800230e: 681b ldr r3, [r3, #0]
8002310: f042 0201 orr.w r2, r2, #1
8002314: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
8002316: 4b20 ldr r3, [pc, #128] @ (8002398 <ADC_Enable+0xb0>)
8002318: 681b ldr r3, [r3, #0]
800231a: 4a20 ldr r2, [pc, #128] @ (800239c <ADC_Enable+0xb4>)
800231c: fba2 2303 umull r2, r3, r2, r3
8002320: 0c9a lsrs r2, r3, #18
8002322: 4613 mov r3, r2
8002324: 005b lsls r3, r3, #1
8002326: 4413 add r3, r2
8002328: 60bb str r3, [r7, #8]
while(wait_loop_index != 0)
800232a: e002 b.n 8002332 <ADC_Enable+0x4a>
{
wait_loop_index--;
800232c: 68bb ldr r3, [r7, #8]
800232e: 3b01 subs r3, #1
8002330: 60bb str r3, [r7, #8]
while(wait_loop_index != 0)
8002332: 68bb ldr r3, [r7, #8]
8002334: 2b00 cmp r3, #0
8002336: d1f9 bne.n 800232c <ADC_Enable+0x44>
}
/* Get tick count */
tickstart = HAL_GetTick();
8002338: f7ff fbd0 bl 8001adc <HAL_GetTick>
800233c: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively enabled */
while(ADC_IS_ENABLE(hadc) == RESET)
800233e: e01f b.n 8002380 <ADC_Enable+0x98>
{
if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
8002340: f7ff fbcc bl 8001adc <HAL_GetTick>
8002344: 4602 mov r2, r0
8002346: 68fb ldr r3, [r7, #12]
8002348: 1ad3 subs r3, r2, r3
800234a: 2b02 cmp r3, #2
800234c: d918 bls.n 8002380 <ADC_Enable+0x98>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) == RESET)
800234e: 687b ldr r3, [r7, #4]
8002350: 681b ldr r3, [r3, #0]
8002352: 681b ldr r3, [r3, #0]
8002354: f003 0340 and.w r3, r3, #64 @ 0x40
8002358: 2b40 cmp r3, #64 @ 0x40
800235a: d011 beq.n 8002380 <ADC_Enable+0x98>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800235c: 687b ldr r3, [r7, #4]
800235e: 6cdb ldr r3, [r3, #76] @ 0x4c
8002360: f043 0210 orr.w r2, r3, #16
8002364: 687b ldr r3, [r7, #4]
8002366: 64da str r2, [r3, #76] @ 0x4c
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002368: 687b ldr r3, [r7, #4]
800236a: 6d1b ldr r3, [r3, #80] @ 0x50
800236c: f043 0201 orr.w r2, r3, #1
8002370: 687b ldr r3, [r7, #4]
8002372: 651a str r2, [r3, #80] @ 0x50
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002374: 687b ldr r3, [r7, #4]
8002376: 2200 movs r2, #0
8002378: f883 2048 strb.w r2, [r3, #72] @ 0x48
return HAL_ERROR;
800237c: 2301 movs r3, #1
800237e: e007 b.n 8002390 <ADC_Enable+0xa8>
while(ADC_IS_ENABLE(hadc) == RESET)
8002380: 687b ldr r3, [r7, #4]
8002382: 681b ldr r3, [r3, #0]
8002384: 681b ldr r3, [r3, #0]
8002386: f003 0340 and.w r3, r3, #64 @ 0x40
800238a: 2b40 cmp r3, #64 @ 0x40
800238c: d1d8 bne.n 8002340 <ADC_Enable+0x58>
}
}
}
/* Return HAL status */
return HAL_OK;
800238e: 2300 movs r3, #0
}
8002390: 4618 mov r0, r3
8002392: 3710 adds r7, #16
8002394: 46bd mov sp, r7
8002396: bd80 pop {r7, pc}
8002398: 20000000 .word 0x20000000
800239c: 431bde83 .word 0x431bde83
080023a0 <ADC_ConversionStop_Disable>:
* stopped to disable the ADC.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
80023a0: b580 push {r7, lr}
80023a2: b084 sub sp, #16
80023a4: af00 add r7, sp, #0
80023a6: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
80023a8: 2300 movs r3, #0
80023aa: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
80023ac: 687b ldr r3, [r7, #4]
80023ae: 681b ldr r3, [r3, #0]
80023b0: 681b ldr r3, [r3, #0]
80023b2: f003 0340 and.w r3, r3, #64 @ 0x40
80023b6: 2b40 cmp r3, #64 @ 0x40
80023b8: d12e bne.n 8002418 <ADC_ConversionStop_Disable+0x78>
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
80023ba: 687b ldr r3, [r7, #4]
80023bc: 681b ldr r3, [r3, #0]
80023be: 689a ldr r2, [r3, #8]
80023c0: 687b ldr r3, [r7, #4]
80023c2: 681b ldr r3, [r3, #0]
80023c4: f022 0201 bic.w r2, r2, #1
80023c8: 609a str r2, [r3, #8]
/* Get tick count */
tickstart = HAL_GetTick();
80023ca: f7ff fb87 bl 8001adc <HAL_GetTick>
80023ce: 60f8 str r0, [r7, #12]
/* Wait for ADC effectively disabled */
while(ADC_IS_ENABLE(hadc) != RESET)
80023d0: e01b b.n 800240a <ADC_ConversionStop_Disable+0x6a>
{
if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
80023d2: f7ff fb83 bl 8001adc <HAL_GetTick>
80023d6: 4602 mov r2, r0
80023d8: 68fb ldr r3, [r7, #12]
80023da: 1ad3 subs r3, r2, r3
80023dc: 2b02 cmp r3, #2
80023de: d914 bls.n 800240a <ADC_ConversionStop_Disable+0x6a>
{
/* New check to avoid false timeout detection in case of preemption */
if(ADC_IS_ENABLE(hadc) != RESET)
80023e0: 687b ldr r3, [r7, #4]
80023e2: 681b ldr r3, [r3, #0]
80023e4: 681b ldr r3, [r3, #0]
80023e6: f003 0340 and.w r3, r3, #64 @ 0x40
80023ea: 2b40 cmp r3, #64 @ 0x40
80023ec: d10d bne.n 800240a <ADC_ConversionStop_Disable+0x6a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80023ee: 687b ldr r3, [r7, #4]
80023f0: 6cdb ldr r3, [r3, #76] @ 0x4c
80023f2: f043 0210 orr.w r2, r3, #16
80023f6: 687b ldr r3, [r7, #4]
80023f8: 64da str r2, [r3, #76] @ 0x4c
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80023fa: 687b ldr r3, [r7, #4]
80023fc: 6d1b ldr r3, [r3, #80] @ 0x50
80023fe: f043 0201 orr.w r2, r3, #1
8002402: 687b ldr r3, [r7, #4]
8002404: 651a str r2, [r3, #80] @ 0x50
return HAL_ERROR;
8002406: 2301 movs r3, #1
8002408: e007 b.n 800241a <ADC_ConversionStop_Disable+0x7a>
while(ADC_IS_ENABLE(hadc) != RESET)
800240a: 687b ldr r3, [r7, #4]
800240c: 681b ldr r3, [r3, #0]
800240e: 681b ldr r3, [r3, #0]
8002410: f003 0340 and.w r3, r3, #64 @ 0x40
8002414: 2b40 cmp r3, #64 @ 0x40
8002416: d0dc beq.n 80023d2 <ADC_ConversionStop_Disable+0x32>
}
}
}
/* Return HAL status */
return HAL_OK;
8002418: 2300 movs r3, #0
}
800241a: 4618 mov r0, r3
800241c: 3710 adds r7, #16
800241e: 46bd mov sp, r7
8002420: bd80 pop {r7, pc}
...
08002424 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002424: b480 push {r7}
8002426: b085 sub sp, #20
8002428: af00 add r7, sp, #0
800242a: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800242c: 687b ldr r3, [r7, #4]
800242e: f003 0307 and.w r3, r3, #7
8002432: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002434: 4b0c ldr r3, [pc, #48] @ (8002468 <__NVIC_SetPriorityGrouping+0x44>)
8002436: 68db ldr r3, [r3, #12]
8002438: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800243a: 68ba ldr r2, [r7, #8]
800243c: f64f 03ff movw r3, #63743 @ 0xf8ff
8002440: 4013 ands r3, r2
8002442: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8002444: 68fb ldr r3, [r7, #12]
8002446: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8002448: 68bb ldr r3, [r7, #8]
800244a: 4313 orrs r3, r2
reg_value = (reg_value |
800244c: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8002450: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002454: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8002456: 4a04 ldr r2, [pc, #16] @ (8002468 <__NVIC_SetPriorityGrouping+0x44>)
8002458: 68bb ldr r3, [r7, #8]
800245a: 60d3 str r3, [r2, #12]
}
800245c: bf00 nop
800245e: 3714 adds r7, #20
8002460: 46bd mov sp, r7
8002462: bc80 pop {r7}
8002464: 4770 bx lr
8002466: bf00 nop
8002468: e000ed00 .word 0xe000ed00
0800246c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800246c: b480 push {r7}
800246e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8002470: 4b04 ldr r3, [pc, #16] @ (8002484 <__NVIC_GetPriorityGrouping+0x18>)
8002472: 68db ldr r3, [r3, #12]
8002474: 0a1b lsrs r3, r3, #8
8002476: f003 0307 and.w r3, r3, #7
}
800247a: 4618 mov r0, r3
800247c: 46bd mov sp, r7
800247e: bc80 pop {r7}
8002480: 4770 bx lr
8002482: bf00 nop
8002484: e000ed00 .word 0xe000ed00
08002488 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8002488: b480 push {r7}
800248a: b083 sub sp, #12
800248c: af00 add r7, sp, #0
800248e: 4603 mov r3, r0
8002490: 6039 str r1, [r7, #0]
8002492: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002494: f997 3007 ldrsb.w r3, [r7, #7]
8002498: 2b00 cmp r3, #0
800249a: db0a blt.n 80024b2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800249c: 683b ldr r3, [r7, #0]
800249e: b2da uxtb r2, r3
80024a0: 490c ldr r1, [pc, #48] @ (80024d4 <__NVIC_SetPriority+0x4c>)
80024a2: f997 3007 ldrsb.w r3, [r7, #7]
80024a6: 0112 lsls r2, r2, #4
80024a8: b2d2 uxtb r2, r2
80024aa: 440b add r3, r1
80024ac: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80024b0: e00a b.n 80024c8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80024b2: 683b ldr r3, [r7, #0]
80024b4: b2da uxtb r2, r3
80024b6: 4908 ldr r1, [pc, #32] @ (80024d8 <__NVIC_SetPriority+0x50>)
80024b8: 79fb ldrb r3, [r7, #7]
80024ba: f003 030f and.w r3, r3, #15
80024be: 3b04 subs r3, #4
80024c0: 0112 lsls r2, r2, #4
80024c2: b2d2 uxtb r2, r2
80024c4: 440b add r3, r1
80024c6: 761a strb r2, [r3, #24]
}
80024c8: bf00 nop
80024ca: 370c adds r7, #12
80024cc: 46bd mov sp, r7
80024ce: bc80 pop {r7}
80024d0: 4770 bx lr
80024d2: bf00 nop
80024d4: e000e100 .word 0xe000e100
80024d8: e000ed00 .word 0xe000ed00
080024dc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80024dc: b480 push {r7}
80024de: b089 sub sp, #36 @ 0x24
80024e0: af00 add r7, sp, #0
80024e2: 60f8 str r0, [r7, #12]
80024e4: 60b9 str r1, [r7, #8]
80024e6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80024e8: 68fb ldr r3, [r7, #12]
80024ea: f003 0307 and.w r3, r3, #7
80024ee: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80024f0: 69fb ldr r3, [r7, #28]
80024f2: f1c3 0307 rsb r3, r3, #7
80024f6: 2b04 cmp r3, #4
80024f8: bf28 it cs
80024fa: 2304 movcs r3, #4
80024fc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80024fe: 69fb ldr r3, [r7, #28]
8002500: 3304 adds r3, #4
8002502: 2b06 cmp r3, #6
8002504: d902 bls.n 800250c <NVIC_EncodePriority+0x30>
8002506: 69fb ldr r3, [r7, #28]
8002508: 3b03 subs r3, #3
800250a: e000 b.n 800250e <NVIC_EncodePriority+0x32>
800250c: 2300 movs r3, #0
800250e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002510: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8002514: 69bb ldr r3, [r7, #24]
8002516: fa02 f303 lsl.w r3, r2, r3
800251a: 43da mvns r2, r3
800251c: 68bb ldr r3, [r7, #8]
800251e: 401a ands r2, r3
8002520: 697b ldr r3, [r7, #20]
8002522: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8002524: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8002528: 697b ldr r3, [r7, #20]
800252a: fa01 f303 lsl.w r3, r1, r3
800252e: 43d9 mvns r1, r3
8002530: 687b ldr r3, [r7, #4]
8002532: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002534: 4313 orrs r3, r2
);
}
8002536: 4618 mov r0, r3
8002538: 3724 adds r7, #36 @ 0x24
800253a: 46bd mov sp, r7
800253c: bc80 pop {r7}
800253e: 4770 bx lr
08002540 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8002540: b580 push {r7, lr}
8002542: b082 sub sp, #8
8002544: af00 add r7, sp, #0
8002546: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002548: 687b ldr r3, [r7, #4]
800254a: 3b01 subs r3, #1
800254c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8002550: d301 bcc.n 8002556 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8002552: 2301 movs r3, #1
8002554: e00f b.n 8002576 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002556: 4a0a ldr r2, [pc, #40] @ (8002580 <SysTick_Config+0x40>)
8002558: 687b ldr r3, [r7, #4]
800255a: 3b01 subs r3, #1
800255c: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800255e: 210f movs r1, #15
8002560: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8002564: f7ff ff90 bl 8002488 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002568: 4b05 ldr r3, [pc, #20] @ (8002580 <SysTick_Config+0x40>)
800256a: 2200 movs r2, #0
800256c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800256e: 4b04 ldr r3, [pc, #16] @ (8002580 <SysTick_Config+0x40>)
8002570: 2207 movs r2, #7
8002572: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8002574: 2300 movs r3, #0
}
8002576: 4618 mov r0, r3
8002578: 3708 adds r7, #8
800257a: 46bd mov sp, r7
800257c: bd80 pop {r7, pc}
800257e: bf00 nop
8002580: e000e010 .word 0xe000e010
08002584 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002584: b580 push {r7, lr}
8002586: b082 sub sp, #8
8002588: af00 add r7, sp, #0
800258a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800258c: 6878 ldr r0, [r7, #4]
800258e: f7ff ff49 bl 8002424 <__NVIC_SetPriorityGrouping>
}
8002592: bf00 nop
8002594: 3708 adds r7, #8
8002596: 46bd mov sp, r7
8002598: bd80 pop {r7, pc}
0800259a <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
800259a: b580 push {r7, lr}
800259c: b086 sub sp, #24
800259e: af00 add r7, sp, #0
80025a0: 4603 mov r3, r0
80025a2: 60b9 str r1, [r7, #8]
80025a4: 607a str r2, [r7, #4]
80025a6: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
80025a8: 2300 movs r3, #0
80025aa: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80025ac: f7ff ff5e bl 800246c <__NVIC_GetPriorityGrouping>
80025b0: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80025b2: 687a ldr r2, [r7, #4]
80025b4: 68b9 ldr r1, [r7, #8]
80025b6: 6978 ldr r0, [r7, #20]
80025b8: f7ff ff90 bl 80024dc <NVIC_EncodePriority>
80025bc: 4602 mov r2, r0
80025be: f997 300f ldrsb.w r3, [r7, #15]
80025c2: 4611 mov r1, r2
80025c4: 4618 mov r0, r3
80025c6: f7ff ff5f bl 8002488 <__NVIC_SetPriority>
}
80025ca: bf00 nop
80025cc: 3718 adds r7, #24
80025ce: 46bd mov sp, r7
80025d0: bd80 pop {r7, pc}
080025d2 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80025d2: b580 push {r7, lr}
80025d4: b082 sub sp, #8
80025d6: af00 add r7, sp, #0
80025d8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
80025da: 6878 ldr r0, [r7, #4]
80025dc: f7ff ffb0 bl 8002540 <SysTick_Config>
80025e0: 4603 mov r3, r0
}
80025e2: 4618 mov r0, r3
80025e4: 3708 adds r7, #8
80025e6: 46bd mov sp, r7
80025e8: bd80 pop {r7, pc}
...
080025ec <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80025ec: b480 push {r7}
80025ee: b087 sub sp, #28
80025f0: af00 add r7, sp, #0
80025f2: 6078 str r0, [r7, #4]
80025f4: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
80025f6: 2300 movs r3, #0
80025f8: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
80025fa: 2300 movs r3, #0
80025fc: 60fb str r3, [r7, #12]
uint32_t temp = 0x00;
80025fe: 2300 movs r3, #0
8002600: 613b str r3, [r7, #16]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0)
8002602: e160 b.n 80028c6 <HAL_GPIO_Init+0x2da>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
8002604: 683b ldr r3, [r7, #0]
8002606: 681a ldr r2, [r3, #0]
8002608: 2101 movs r1, #1
800260a: 697b ldr r3, [r7, #20]
800260c: fa01 f303 lsl.w r3, r1, r3
8002610: 4013 ands r3, r2
8002612: 60fb str r3, [r7, #12]
if (iocurrent)
8002614: 68fb ldr r3, [r7, #12]
8002616: 2b00 cmp r3, #0
8002618: f000 8152 beq.w 80028c0 <HAL_GPIO_Init+0x2d4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
800261c: 683b ldr r3, [r7, #0]
800261e: 685b ldr r3, [r3, #4]
8002620: f003 0303 and.w r3, r3, #3
8002624: 2b01 cmp r3, #1
8002626: d005 beq.n 8002634 <HAL_GPIO_Init+0x48>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8002628: 683b ldr r3, [r7, #0]
800262a: 685b ldr r3, [r3, #4]
800262c: f003 0303 and.w r3, r3, #3
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8002630: 2b02 cmp r3, #2
8002632: d130 bne.n 8002696 <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8002634: 687b ldr r3, [r7, #4]
8002636: 689b ldr r3, [r3, #8]
8002638: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
800263a: 697b ldr r3, [r7, #20]
800263c: 005b lsls r3, r3, #1
800263e: 2203 movs r2, #3
8002640: fa02 f303 lsl.w r3, r2, r3
8002644: 43db mvns r3, r3
8002646: 693a ldr r2, [r7, #16]
8002648: 4013 ands r3, r2
800264a: 613b str r3, [r7, #16]
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
800264c: 683b ldr r3, [r7, #0]
800264e: 68da ldr r2, [r3, #12]
8002650: 697b ldr r3, [r7, #20]
8002652: 005b lsls r3, r3, #1
8002654: fa02 f303 lsl.w r3, r2, r3
8002658: 693a ldr r2, [r7, #16]
800265a: 4313 orrs r3, r2
800265c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800265e: 687b ldr r3, [r7, #4]
8002660: 693a ldr r2, [r7, #16]
8002662: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8002664: 687b ldr r3, [r7, #4]
8002666: 685b ldr r3, [r3, #4]
8002668: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
800266a: 2201 movs r2, #1
800266c: 697b ldr r3, [r7, #20]
800266e: fa02 f303 lsl.w r3, r2, r3
8002672: 43db mvns r3, r3
8002674: 693a ldr r2, [r7, #16]
8002676: 4013 ands r3, r2
8002678: 613b str r3, [r7, #16]
SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800267a: 683b ldr r3, [r7, #0]
800267c: 685b ldr r3, [r3, #4]
800267e: 091b lsrs r3, r3, #4
8002680: f003 0201 and.w r2, r3, #1
8002684: 697b ldr r3, [r7, #20]
8002686: fa02 f303 lsl.w r3, r2, r3
800268a: 693a ldr r2, [r7, #16]
800268c: 4313 orrs r3, r2
800268e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8002690: 687b ldr r3, [r7, #4]
8002692: 693a ldr r2, [r7, #16]
8002694: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8002696: 683b ldr r3, [r7, #0]
8002698: 685b ldr r3, [r3, #4]
800269a: f003 0303 and.w r3, r3, #3
800269e: 2b03 cmp r3, #3
80026a0: d017 beq.n 80026d2 <HAL_GPIO_Init+0xe6>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80026a2: 687b ldr r3, [r7, #4]
80026a4: 68db ldr r3, [r3, #12]
80026a6: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
80026a8: 697b ldr r3, [r7, #20]
80026aa: 005b lsls r3, r3, #1
80026ac: 2203 movs r2, #3
80026ae: fa02 f303 lsl.w r3, r2, r3
80026b2: 43db mvns r3, r3
80026b4: 693a ldr r2, [r7, #16]
80026b6: 4013 ands r3, r2
80026b8: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
80026ba: 683b ldr r3, [r7, #0]
80026bc: 689a ldr r2, [r3, #8]
80026be: 697b ldr r3, [r7, #20]
80026c0: 005b lsls r3, r3, #1
80026c2: fa02 f303 lsl.w r3, r2, r3
80026c6: 693a ldr r2, [r7, #16]
80026c8: 4313 orrs r3, r2
80026ca: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80026cc: 687b ldr r3, [r7, #4]
80026ce: 693a ldr r2, [r7, #16]
80026d0: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80026d2: 683b ldr r3, [r7, #0]
80026d4: 685b ldr r3, [r3, #4]
80026d6: f003 0303 and.w r3, r3, #3
80026da: 2b02 cmp r3, #2
80026dc: d123 bne.n 8002726 <HAL_GPIO_Init+0x13a>
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
/* Identify AFRL or AFRH register based on IO position*/
temp = GPIOx->AFR[position >> 3];
80026de: 697b ldr r3, [r7, #20]
80026e0: 08da lsrs r2, r3, #3
80026e2: 687b ldr r3, [r7, #4]
80026e4: 3208 adds r2, #8
80026e6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80026ea: 613b str r3, [r7, #16]
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
80026ec: 697b ldr r3, [r7, #20]
80026ee: f003 0307 and.w r3, r3, #7
80026f2: 009b lsls r3, r3, #2
80026f4: 220f movs r2, #15
80026f6: fa02 f303 lsl.w r3, r2, r3
80026fa: 43db mvns r3, r3
80026fc: 693a ldr r2, [r7, #16]
80026fe: 4013 ands r3, r2
8002700: 613b str r3, [r7, #16]
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
8002702: 683b ldr r3, [r7, #0]
8002704: 691a ldr r2, [r3, #16]
8002706: 697b ldr r3, [r7, #20]
8002708: f003 0307 and.w r3, r3, #7
800270c: 009b lsls r3, r3, #2
800270e: fa02 f303 lsl.w r3, r2, r3
8002712: 693a ldr r2, [r7, #16]
8002714: 4313 orrs r3, r2
8002716: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3] = temp;
8002718: 697b ldr r3, [r7, #20]
800271a: 08da lsrs r2, r3, #3
800271c: 687b ldr r3, [r7, #4]
800271e: 3208 adds r2, #8
8002720: 6939 ldr r1, [r7, #16]
8002722: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8002726: 687b ldr r3, [r7, #4]
8002728: 681b ldr r3, [r3, #0]
800272a: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
800272c: 697b ldr r3, [r7, #20]
800272e: 005b lsls r3, r3, #1
8002730: 2203 movs r2, #3
8002732: fa02 f303 lsl.w r3, r2, r3
8002736: 43db mvns r3, r3
8002738: 693a ldr r2, [r7, #16]
800273a: 4013 ands r3, r2
800273c: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
800273e: 683b ldr r3, [r7, #0]
8002740: 685b ldr r3, [r3, #4]
8002742: f003 0203 and.w r2, r3, #3
8002746: 697b ldr r3, [r7, #20]
8002748: 005b lsls r3, r3, #1
800274a: fa02 f303 lsl.w r3, r2, r3
800274e: 693a ldr r2, [r7, #16]
8002750: 4313 orrs r3, r2
8002752: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8002754: 687b ldr r3, [r7, #4]
8002756: 693a ldr r2, [r7, #16]
8002758: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
800275a: 683b ldr r3, [r7, #0]
800275c: 685b ldr r3, [r3, #4]
800275e: f403 3340 and.w r3, r3, #196608 @ 0x30000
8002762: 2b00 cmp r3, #0
8002764: f000 80ac beq.w 80028c0 <HAL_GPIO_Init+0x2d4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8002768: 4b5e ldr r3, [pc, #376] @ (80028e4 <HAL_GPIO_Init+0x2f8>)
800276a: 6a1b ldr r3, [r3, #32]
800276c: 4a5d ldr r2, [pc, #372] @ (80028e4 <HAL_GPIO_Init+0x2f8>)
800276e: f043 0301 orr.w r3, r3, #1
8002772: 6213 str r3, [r2, #32]
8002774: 4b5b ldr r3, [pc, #364] @ (80028e4 <HAL_GPIO_Init+0x2f8>)
8002776: 6a1b ldr r3, [r3, #32]
8002778: f003 0301 and.w r3, r3, #1
800277c: 60bb str r3, [r7, #8]
800277e: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2];
8002780: 4a59 ldr r2, [pc, #356] @ (80028e8 <HAL_GPIO_Init+0x2fc>)
8002782: 697b ldr r3, [r7, #20]
8002784: 089b lsrs r3, r3, #2
8002786: 3302 adds r3, #2
8002788: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800278c: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
800278e: 697b ldr r3, [r7, #20]
8002790: f003 0303 and.w r3, r3, #3
8002794: 009b lsls r3, r3, #2
8002796: 220f movs r2, #15
8002798: fa02 f303 lsl.w r3, r2, r3
800279c: 43db mvns r3, r3
800279e: 693a ldr r2, [r7, #16]
80027a0: 4013 ands r3, r2
80027a2: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
80027a4: 687b ldr r3, [r7, #4]
80027a6: 4a51 ldr r2, [pc, #324] @ (80028ec <HAL_GPIO_Init+0x300>)
80027a8: 4293 cmp r3, r2
80027aa: d025 beq.n 80027f8 <HAL_GPIO_Init+0x20c>
80027ac: 687b ldr r3, [r7, #4]
80027ae: 4a50 ldr r2, [pc, #320] @ (80028f0 <HAL_GPIO_Init+0x304>)
80027b0: 4293 cmp r3, r2
80027b2: d01f beq.n 80027f4 <HAL_GPIO_Init+0x208>
80027b4: 687b ldr r3, [r7, #4]
80027b6: 4a4f ldr r2, [pc, #316] @ (80028f4 <HAL_GPIO_Init+0x308>)
80027b8: 4293 cmp r3, r2
80027ba: d019 beq.n 80027f0 <HAL_GPIO_Init+0x204>
80027bc: 687b ldr r3, [r7, #4]
80027be: 4a4e ldr r2, [pc, #312] @ (80028f8 <HAL_GPIO_Init+0x30c>)
80027c0: 4293 cmp r3, r2
80027c2: d013 beq.n 80027ec <HAL_GPIO_Init+0x200>
80027c4: 687b ldr r3, [r7, #4]
80027c6: 4a4d ldr r2, [pc, #308] @ (80028fc <HAL_GPIO_Init+0x310>)
80027c8: 4293 cmp r3, r2
80027ca: d00d beq.n 80027e8 <HAL_GPIO_Init+0x1fc>
80027cc: 687b ldr r3, [r7, #4]
80027ce: 4a4c ldr r2, [pc, #304] @ (8002900 <HAL_GPIO_Init+0x314>)
80027d0: 4293 cmp r3, r2
80027d2: d007 beq.n 80027e4 <HAL_GPIO_Init+0x1f8>
80027d4: 687b ldr r3, [r7, #4]
80027d6: 4a4b ldr r2, [pc, #300] @ (8002904 <HAL_GPIO_Init+0x318>)
80027d8: 4293 cmp r3, r2
80027da: d101 bne.n 80027e0 <HAL_GPIO_Init+0x1f4>
80027dc: 2306 movs r3, #6
80027de: e00c b.n 80027fa <HAL_GPIO_Init+0x20e>
80027e0: 2307 movs r3, #7
80027e2: e00a b.n 80027fa <HAL_GPIO_Init+0x20e>
80027e4: 2305 movs r3, #5
80027e6: e008 b.n 80027fa <HAL_GPIO_Init+0x20e>
80027e8: 2304 movs r3, #4
80027ea: e006 b.n 80027fa <HAL_GPIO_Init+0x20e>
80027ec: 2303 movs r3, #3
80027ee: e004 b.n 80027fa <HAL_GPIO_Init+0x20e>
80027f0: 2302 movs r3, #2
80027f2: e002 b.n 80027fa <HAL_GPIO_Init+0x20e>
80027f4: 2301 movs r3, #1
80027f6: e000 b.n 80027fa <HAL_GPIO_Init+0x20e>
80027f8: 2300 movs r3, #0
80027fa: 697a ldr r2, [r7, #20]
80027fc: f002 0203 and.w r2, r2, #3
8002800: 0092 lsls r2, r2, #2
8002802: 4093 lsls r3, r2
8002804: 693a ldr r2, [r7, #16]
8002806: 4313 orrs r3, r2
8002808: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2] = temp;
800280a: 4937 ldr r1, [pc, #220] @ (80028e8 <HAL_GPIO_Init+0x2fc>)
800280c: 697b ldr r3, [r7, #20]
800280e: 089b lsrs r3, r3, #2
8002810: 3302 adds r3, #2
8002812: 693a ldr r2, [r7, #16]
8002814: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8002818: 4b3b ldr r3, [pc, #236] @ (8002908 <HAL_GPIO_Init+0x31c>)
800281a: 689b ldr r3, [r3, #8]
800281c: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
800281e: 68fb ldr r3, [r7, #12]
8002820: 43db mvns r3, r3
8002822: 693a ldr r2, [r7, #16]
8002824: 4013 ands r3, r2
8002826: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8002828: 683b ldr r3, [r7, #0]
800282a: 685b ldr r3, [r3, #4]
800282c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8002830: 2b00 cmp r3, #0
8002832: d003 beq.n 800283c <HAL_GPIO_Init+0x250>
{
SET_BIT(temp, iocurrent);
8002834: 693a ldr r2, [r7, #16]
8002836: 68fb ldr r3, [r7, #12]
8002838: 4313 orrs r3, r2
800283a: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
800283c: 4a32 ldr r2, [pc, #200] @ (8002908 <HAL_GPIO_Init+0x31c>)
800283e: 693b ldr r3, [r7, #16]
8002840: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8002842: 4b31 ldr r3, [pc, #196] @ (8002908 <HAL_GPIO_Init+0x31c>)
8002844: 68db ldr r3, [r3, #12]
8002846: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8002848: 68fb ldr r3, [r7, #12]
800284a: 43db mvns r3, r3
800284c: 693a ldr r2, [r7, #16]
800284e: 4013 ands r3, r2
8002850: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8002852: 683b ldr r3, [r7, #0]
8002854: 685b ldr r3, [r3, #4]
8002856: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800285a: 2b00 cmp r3, #0
800285c: d003 beq.n 8002866 <HAL_GPIO_Init+0x27a>
{
SET_BIT(temp, iocurrent);
800285e: 693a ldr r2, [r7, #16]
8002860: 68fb ldr r3, [r7, #12]
8002862: 4313 orrs r3, r2
8002864: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8002866: 4a28 ldr r2, [pc, #160] @ (8002908 <HAL_GPIO_Init+0x31c>)
8002868: 693b ldr r3, [r7, #16]
800286a: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
800286c: 4b26 ldr r3, [pc, #152] @ (8002908 <HAL_GPIO_Init+0x31c>)
800286e: 685b ldr r3, [r3, #4]
8002870: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8002872: 68fb ldr r3, [r7, #12]
8002874: 43db mvns r3, r3
8002876: 693a ldr r2, [r7, #16]
8002878: 4013 ands r3, r2
800287a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
800287c: 683b ldr r3, [r7, #0]
800287e: 685b ldr r3, [r3, #4]
8002880: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002884: 2b00 cmp r3, #0
8002886: d003 beq.n 8002890 <HAL_GPIO_Init+0x2a4>
{
SET_BIT(temp, iocurrent);
8002888: 693a ldr r2, [r7, #16]
800288a: 68fb ldr r3, [r7, #12]
800288c: 4313 orrs r3, r2
800288e: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8002890: 4a1d ldr r2, [pc, #116] @ (8002908 <HAL_GPIO_Init+0x31c>)
8002892: 693b ldr r3, [r7, #16]
8002894: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8002896: 4b1c ldr r3, [pc, #112] @ (8002908 <HAL_GPIO_Init+0x31c>)
8002898: 681b ldr r3, [r3, #0]
800289a: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
800289c: 68fb ldr r3, [r7, #12]
800289e: 43db mvns r3, r3
80028a0: 693a ldr r2, [r7, #16]
80028a2: 4013 ands r3, r2
80028a4: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80028a6: 683b ldr r3, [r7, #0]
80028a8: 685b ldr r3, [r3, #4]
80028aa: f403 3380 and.w r3, r3, #65536 @ 0x10000
80028ae: 2b00 cmp r3, #0
80028b0: d003 beq.n 80028ba <HAL_GPIO_Init+0x2ce>
{
SET_BIT(temp, iocurrent);
80028b2: 693a ldr r2, [r7, #16]
80028b4: 68fb ldr r3, [r7, #12]
80028b6: 4313 orrs r3, r2
80028b8: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
80028ba: 4a13 ldr r2, [pc, #76] @ (8002908 <HAL_GPIO_Init+0x31c>)
80028bc: 693b ldr r3, [r7, #16]
80028be: 6013 str r3, [r2, #0]
}
}
position++;
80028c0: 697b ldr r3, [r7, #20]
80028c2: 3301 adds r3, #1
80028c4: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0)
80028c6: 683b ldr r3, [r7, #0]
80028c8: 681a ldr r2, [r3, #0]
80028ca: 697b ldr r3, [r7, #20]
80028cc: fa22 f303 lsr.w r3, r2, r3
80028d0: 2b00 cmp r3, #0
80028d2: f47f ae97 bne.w 8002604 <HAL_GPIO_Init+0x18>
}
}
80028d6: bf00 nop
80028d8: bf00 nop
80028da: 371c adds r7, #28
80028dc: 46bd mov sp, r7
80028de: bc80 pop {r7}
80028e0: 4770 bx lr
80028e2: bf00 nop
80028e4: 40023800 .word 0x40023800
80028e8: 40010000 .word 0x40010000
80028ec: 40020000 .word 0x40020000
80028f0: 40020400 .word 0x40020400
80028f4: 40020800 .word 0x40020800
80028f8: 40020c00 .word 0x40020c00
80028fc: 40021000 .word 0x40021000
8002900: 40021400 .word 0x40021400
8002904: 40021800 .word 0x40021800
8002908: 40010400 .word 0x40010400
0800290c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
800290c: b480 push {r7}
800290e: b083 sub sp, #12
8002910: af00 add r7, sp, #0
8002912: 6078 str r0, [r7, #4]
8002914: 460b mov r3, r1
8002916: 807b strh r3, [r7, #2]
8002918: 4613 mov r3, r2
800291a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
800291c: 787b ldrb r3, [r7, #1]
800291e: 2b00 cmp r3, #0
8002920: d003 beq.n 800292a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8002922: 887a ldrh r2, [r7, #2]
8002924: 687b ldr r3, [r7, #4]
8002926: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
}
}
8002928: e003 b.n 8002932 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
800292a: 887b ldrh r3, [r7, #2]
800292c: 041a lsls r2, r3, #16
800292e: 687b ldr r3, [r7, #4]
8002930: 619a str r2, [r3, #24]
}
8002932: bf00 nop
8002934: 370c adds r7, #12
8002936: 46bd mov sp, r7
8002938: bc80 pop {r7}
800293a: 4770 bx lr
0800293c <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800293c: b580 push {r7, lr}
800293e: b088 sub sp, #32
8002940: af00 add r7, sp, #0
8002942: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check the parameters */
if(RCC_OscInitStruct == NULL)
8002944: 687b ldr r3, [r7, #4]
8002946: 2b00 cmp r3, #0
8002948: d101 bne.n 800294e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800294a: 2301 movs r3, #1
800294c: e31d b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
}
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
800294e: 4b94 ldr r3, [pc, #592] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002950: 689b ldr r3, [r3, #8]
8002952: f003 030c and.w r3, r3, #12
8002956: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
8002958: 4b91 ldr r3, [pc, #580] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
800295a: 689b ldr r3, [r3, #8]
800295c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002960: 617b str r3, [r7, #20]
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002962: 687b ldr r3, [r7, #4]
8002964: 681b ldr r3, [r3, #0]
8002966: f003 0301 and.w r3, r3, #1
800296a: 2b00 cmp r3, #0
800296c: d07b beq.n 8002a66 <HAL_RCC_OscConfig+0x12a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
800296e: 69bb ldr r3, [r7, #24]
8002970: 2b08 cmp r3, #8
8002972: d006 beq.n 8002982 <HAL_RCC_OscConfig+0x46>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
8002974: 69bb ldr r3, [r7, #24]
8002976: 2b0c cmp r3, #12
8002978: d10f bne.n 800299a <HAL_RCC_OscConfig+0x5e>
800297a: 697b ldr r3, [r7, #20]
800297c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002980: d10b bne.n 800299a <HAL_RCC_OscConfig+0x5e>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002982: 4b87 ldr r3, [pc, #540] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002984: 681b ldr r3, [r3, #0]
8002986: f403 3300 and.w r3, r3, #131072 @ 0x20000
800298a: 2b00 cmp r3, #0
800298c: d06a beq.n 8002a64 <HAL_RCC_OscConfig+0x128>
800298e: 687b ldr r3, [r7, #4]
8002990: 685b ldr r3, [r3, #4]
8002992: 2b00 cmp r3, #0
8002994: d166 bne.n 8002a64 <HAL_RCC_OscConfig+0x128>
{
return HAL_ERROR;
8002996: 2301 movs r3, #1
8002998: e2f7 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800299a: 687b ldr r3, [r7, #4]
800299c: 685b ldr r3, [r3, #4]
800299e: 2b01 cmp r3, #1
80029a0: d106 bne.n 80029b0 <HAL_RCC_OscConfig+0x74>
80029a2: 4b7f ldr r3, [pc, #508] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029a4: 681b ldr r3, [r3, #0]
80029a6: 4a7e ldr r2, [pc, #504] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029a8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80029ac: 6013 str r3, [r2, #0]
80029ae: e02d b.n 8002a0c <HAL_RCC_OscConfig+0xd0>
80029b0: 687b ldr r3, [r7, #4]
80029b2: 685b ldr r3, [r3, #4]
80029b4: 2b00 cmp r3, #0
80029b6: d10c bne.n 80029d2 <HAL_RCC_OscConfig+0x96>
80029b8: 4b79 ldr r3, [pc, #484] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029ba: 681b ldr r3, [r3, #0]
80029bc: 4a78 ldr r2, [pc, #480] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029be: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80029c2: 6013 str r3, [r2, #0]
80029c4: 4b76 ldr r3, [pc, #472] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029c6: 681b ldr r3, [r3, #0]
80029c8: 4a75 ldr r2, [pc, #468] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029ca: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80029ce: 6013 str r3, [r2, #0]
80029d0: e01c b.n 8002a0c <HAL_RCC_OscConfig+0xd0>
80029d2: 687b ldr r3, [r7, #4]
80029d4: 685b ldr r3, [r3, #4]
80029d6: 2b05 cmp r3, #5
80029d8: d10c bne.n 80029f4 <HAL_RCC_OscConfig+0xb8>
80029da: 4b71 ldr r3, [pc, #452] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029dc: 681b ldr r3, [r3, #0]
80029de: 4a70 ldr r2, [pc, #448] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029e0: f443 2380 orr.w r3, r3, #262144 @ 0x40000
80029e4: 6013 str r3, [r2, #0]
80029e6: 4b6e ldr r3, [pc, #440] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029e8: 681b ldr r3, [r3, #0]
80029ea: 4a6d ldr r2, [pc, #436] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029ec: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80029f0: 6013 str r3, [r2, #0]
80029f2: e00b b.n 8002a0c <HAL_RCC_OscConfig+0xd0>
80029f4: 4b6a ldr r3, [pc, #424] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029f6: 681b ldr r3, [r3, #0]
80029f8: 4a69 ldr r2, [pc, #420] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
80029fa: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80029fe: 6013 str r3, [r2, #0]
8002a00: 4b67 ldr r3, [pc, #412] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002a02: 681b ldr r3, [r3, #0]
8002a04: 4a66 ldr r2, [pc, #408] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002a06: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8002a0a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8002a0c: 687b ldr r3, [r7, #4]
8002a0e: 685b ldr r3, [r3, #4]
8002a10: 2b00 cmp r3, #0
8002a12: d013 beq.n 8002a3c <HAL_RCC_OscConfig+0x100>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002a14: f7ff f862 bl 8001adc <HAL_GetTick>
8002a18: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002a1a: e008 b.n 8002a2e <HAL_RCC_OscConfig+0xf2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002a1c: f7ff f85e bl 8001adc <HAL_GetTick>
8002a20: 4602 mov r2, r0
8002a22: 693b ldr r3, [r7, #16]
8002a24: 1ad3 subs r3, r2, r3
8002a26: 2b64 cmp r3, #100 @ 0x64
8002a28: d901 bls.n 8002a2e <HAL_RCC_OscConfig+0xf2>
{
return HAL_TIMEOUT;
8002a2a: 2303 movs r3, #3
8002a2c: e2ad b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002a2e: 4b5c ldr r3, [pc, #368] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002a30: 681b ldr r3, [r3, #0]
8002a32: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002a36: 2b00 cmp r3, #0
8002a38: d0f0 beq.n 8002a1c <HAL_RCC_OscConfig+0xe0>
8002a3a: e014 b.n 8002a66 <HAL_RCC_OscConfig+0x12a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002a3c: f7ff f84e bl 8001adc <HAL_GetTick>
8002a40: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8002a42: e008 b.n 8002a56 <HAL_RCC_OscConfig+0x11a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002a44: f7ff f84a bl 8001adc <HAL_GetTick>
8002a48: 4602 mov r2, r0
8002a4a: 693b ldr r3, [r7, #16]
8002a4c: 1ad3 subs r3, r2, r3
8002a4e: 2b64 cmp r3, #100 @ 0x64
8002a50: d901 bls.n 8002a56 <HAL_RCC_OscConfig+0x11a>
{
return HAL_TIMEOUT;
8002a52: 2303 movs r3, #3
8002a54: e299 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8002a56: 4b52 ldr r3, [pc, #328] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002a58: 681b ldr r3, [r3, #0]
8002a5a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002a5e: 2b00 cmp r3, #0
8002a60: d1f0 bne.n 8002a44 <HAL_RCC_OscConfig+0x108>
8002a62: e000 b.n 8002a66 <HAL_RCC_OscConfig+0x12a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002a64: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002a66: 687b ldr r3, [r7, #4]
8002a68: 681b ldr r3, [r3, #0]
8002a6a: f003 0302 and.w r3, r3, #2
8002a6e: 2b00 cmp r3, #0
8002a70: d05a beq.n 8002b28 <HAL_RCC_OscConfig+0x1ec>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
8002a72: 69bb ldr r3, [r7, #24]
8002a74: 2b04 cmp r3, #4
8002a76: d005 beq.n 8002a84 <HAL_RCC_OscConfig+0x148>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
8002a78: 69bb ldr r3, [r7, #24]
8002a7a: 2b0c cmp r3, #12
8002a7c: d119 bne.n 8002ab2 <HAL_RCC_OscConfig+0x176>
8002a7e: 697b ldr r3, [r7, #20]
8002a80: 2b00 cmp r3, #0
8002a82: d116 bne.n 8002ab2 <HAL_RCC_OscConfig+0x176>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002a84: 4b46 ldr r3, [pc, #280] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002a86: 681b ldr r3, [r3, #0]
8002a88: f003 0302 and.w r3, r3, #2
8002a8c: 2b00 cmp r3, #0
8002a8e: d005 beq.n 8002a9c <HAL_RCC_OscConfig+0x160>
8002a90: 687b ldr r3, [r7, #4]
8002a92: 68db ldr r3, [r3, #12]
8002a94: 2b01 cmp r3, #1
8002a96: d001 beq.n 8002a9c <HAL_RCC_OscConfig+0x160>
{
return HAL_ERROR;
8002a98: 2301 movs r3, #1
8002a9a: e276 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002a9c: 4b40 ldr r3, [pc, #256] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002a9e: 685b ldr r3, [r3, #4]
8002aa0: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8002aa4: 687b ldr r3, [r7, #4]
8002aa6: 691b ldr r3, [r3, #16]
8002aa8: 021b lsls r3, r3, #8
8002aaa: 493d ldr r1, [pc, #244] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002aac: 4313 orrs r3, r2
8002aae: 604b str r3, [r1, #4]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002ab0: e03a b.n 8002b28 <HAL_RCC_OscConfig+0x1ec>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 68db ldr r3, [r3, #12]
8002ab6: 2b00 cmp r3, #0
8002ab8: d020 beq.n 8002afc <HAL_RCC_OscConfig+0x1c0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002aba: 4b3a ldr r3, [pc, #232] @ (8002ba4 <HAL_RCC_OscConfig+0x268>)
8002abc: 2201 movs r2, #1
8002abe: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002ac0: f7ff f80c bl 8001adc <HAL_GetTick>
8002ac4: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8002ac6: e008 b.n 8002ada <HAL_RCC_OscConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002ac8: f7ff f808 bl 8001adc <HAL_GetTick>
8002acc: 4602 mov r2, r0
8002ace: 693b ldr r3, [r7, #16]
8002ad0: 1ad3 subs r3, r2, r3
8002ad2: 2b02 cmp r3, #2
8002ad4: d901 bls.n 8002ada <HAL_RCC_OscConfig+0x19e>
{
return HAL_TIMEOUT;
8002ad6: 2303 movs r3, #3
8002ad8: e257 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8002ada: 4b31 ldr r3, [pc, #196] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002adc: 681b ldr r3, [r3, #0]
8002ade: f003 0302 and.w r3, r3, #2
8002ae2: 2b00 cmp r3, #0
8002ae4: d0f0 beq.n 8002ac8 <HAL_RCC_OscConfig+0x18c>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002ae6: 4b2e ldr r3, [pc, #184] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002ae8: 685b ldr r3, [r3, #4]
8002aea: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8002aee: 687b ldr r3, [r7, #4]
8002af0: 691b ldr r3, [r3, #16]
8002af2: 021b lsls r3, r3, #8
8002af4: 492a ldr r1, [pc, #168] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002af6: 4313 orrs r3, r2
8002af8: 604b str r3, [r1, #4]
8002afa: e015 b.n 8002b28 <HAL_RCC_OscConfig+0x1ec>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002afc: 4b29 ldr r3, [pc, #164] @ (8002ba4 <HAL_RCC_OscConfig+0x268>)
8002afe: 2200 movs r2, #0
8002b00: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002b02: f7fe ffeb bl 8001adc <HAL_GetTick>
8002b06: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8002b08: e008 b.n 8002b1c <HAL_RCC_OscConfig+0x1e0>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002b0a: f7fe ffe7 bl 8001adc <HAL_GetTick>
8002b0e: 4602 mov r2, r0
8002b10: 693b ldr r3, [r7, #16]
8002b12: 1ad3 subs r3, r2, r3
8002b14: 2b02 cmp r3, #2
8002b16: d901 bls.n 8002b1c <HAL_RCC_OscConfig+0x1e0>
{
return HAL_TIMEOUT;
8002b18: 2303 movs r3, #3
8002b1a: e236 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8002b1c: 4b20 ldr r3, [pc, #128] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002b1e: 681b ldr r3, [r3, #0]
8002b20: f003 0302 and.w r3, r3, #2
8002b24: 2b00 cmp r3, #0
8002b26: d1f0 bne.n 8002b0a <HAL_RCC_OscConfig+0x1ce>
}
}
}
}
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8002b28: 687b ldr r3, [r7, #4]
8002b2a: 681b ldr r3, [r3, #0]
8002b2c: f003 0310 and.w r3, r3, #16
8002b30: 2b00 cmp r3, #0
8002b32: f000 80b8 beq.w 8002ca6 <HAL_RCC_OscConfig+0x36a>
{
/* When the MSI is used as system clock it will not be disabled */
if(sysclk_source == RCC_CFGR_SWS_MSI)
8002b36: 69bb ldr r3, [r7, #24]
8002b38: 2b00 cmp r3, #0
8002b3a: d170 bne.n 8002c1e <HAL_RCC_OscConfig+0x2e2>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8002b3c: 4b18 ldr r3, [pc, #96] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002b3e: 681b ldr r3, [r3, #0]
8002b40: f403 7300 and.w r3, r3, #512 @ 0x200
8002b44: 2b00 cmp r3, #0
8002b46: d005 beq.n 8002b54 <HAL_RCC_OscConfig+0x218>
8002b48: 687b ldr r3, [r7, #4]
8002b4a: 699b ldr r3, [r3, #24]
8002b4c: 2b00 cmp r3, #0
8002b4e: d101 bne.n 8002b54 <HAL_RCC_OscConfig+0x218>
{
return HAL_ERROR;
8002b50: 2301 movs r3, #1
8002b52: e21a b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
8002b54: 687b ldr r3, [r7, #4]
8002b56: 6a1a ldr r2, [r3, #32]
8002b58: 4b11 ldr r3, [pc, #68] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002b5a: 685b ldr r3, [r3, #4]
8002b5c: f403 4360 and.w r3, r3, #57344 @ 0xe000
8002b60: 429a cmp r2, r3
8002b62: d921 bls.n 8002ba8 <HAL_RCC_OscConfig+0x26c>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8002b64: 687b ldr r3, [r7, #4]
8002b66: 6a1b ldr r3, [r3, #32]
8002b68: 4618 mov r0, r3
8002b6a: f000 fc09 bl 8003380 <RCC_SetFlashLatencyFromMSIRange>
8002b6e: 4603 mov r3, r0
8002b70: 2b00 cmp r3, #0
8002b72: d001 beq.n 8002b78 <HAL_RCC_OscConfig+0x23c>
{
return HAL_ERROR;
8002b74: 2301 movs r3, #1
8002b76: e208 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8002b78: 4b09 ldr r3, [pc, #36] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002b7a: 685b ldr r3, [r3, #4]
8002b7c: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8002b80: 687b ldr r3, [r7, #4]
8002b82: 6a1b ldr r3, [r3, #32]
8002b84: 4906 ldr r1, [pc, #24] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002b86: 4313 orrs r3, r2
8002b88: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8002b8a: 4b05 ldr r3, [pc, #20] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002b8c: 685b ldr r3, [r3, #4]
8002b8e: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
8002b92: 687b ldr r3, [r7, #4]
8002b94: 69db ldr r3, [r3, #28]
8002b96: 061b lsls r3, r3, #24
8002b98: 4901 ldr r1, [pc, #4] @ (8002ba0 <HAL_RCC_OscConfig+0x264>)
8002b9a: 4313 orrs r3, r2
8002b9c: 604b str r3, [r1, #4]
8002b9e: e020 b.n 8002be2 <HAL_RCC_OscConfig+0x2a6>
8002ba0: 40023800 .word 0x40023800
8002ba4: 42470000 .word 0x42470000
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8002ba8: 4b99 ldr r3, [pc, #612] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002baa: 685b ldr r3, [r3, #4]
8002bac: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8002bb0: 687b ldr r3, [r7, #4]
8002bb2: 6a1b ldr r3, [r3, #32]
8002bb4: 4996 ldr r1, [pc, #600] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002bb6: 4313 orrs r3, r2
8002bb8: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8002bba: 4b95 ldr r3, [pc, #596] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002bbc: 685b ldr r3, [r3, #4]
8002bbe: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
8002bc2: 687b ldr r3, [r7, #4]
8002bc4: 69db ldr r3, [r3, #28]
8002bc6: 061b lsls r3, r3, #24
8002bc8: 4991 ldr r1, [pc, #580] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002bca: 4313 orrs r3, r2
8002bcc: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8002bce: 687b ldr r3, [r7, #4]
8002bd0: 6a1b ldr r3, [r3, #32]
8002bd2: 4618 mov r0, r3
8002bd4: f000 fbd4 bl 8003380 <RCC_SetFlashLatencyFromMSIRange>
8002bd8: 4603 mov r3, r0
8002bda: 2b00 cmp r3, #0
8002bdc: d001 beq.n 8002be2 <HAL_RCC_OscConfig+0x2a6>
{
return HAL_ERROR;
8002bde: 2301 movs r3, #1
8002be0: e1d3 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
8002be2: 687b ldr r3, [r7, #4]
8002be4: 6a1b ldr r3, [r3, #32]
8002be6: 0b5b lsrs r3, r3, #13
8002be8: 3301 adds r3, #1
8002bea: f44f 4200 mov.w r2, #32768 @ 0x8000
8002bee: fa02 f303 lsl.w r3, r2, r3
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
8002bf2: 4a87 ldr r2, [pc, #540] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002bf4: 6892 ldr r2, [r2, #8]
8002bf6: 0912 lsrs r2, r2, #4
8002bf8: f002 020f and.w r2, r2, #15
8002bfc: 4985 ldr r1, [pc, #532] @ (8002e14 <HAL_RCC_OscConfig+0x4d8>)
8002bfe: 5c8a ldrb r2, [r1, r2]
8002c00: 40d3 lsrs r3, r2
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
8002c02: 4a85 ldr r2, [pc, #532] @ (8002e18 <HAL_RCC_OscConfig+0x4dc>)
8002c04: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8002c06: 4b85 ldr r3, [pc, #532] @ (8002e1c <HAL_RCC_OscConfig+0x4e0>)
8002c08: 681b ldr r3, [r3, #0]
8002c0a: 4618 mov r0, r3
8002c0c: f7fe ff1a bl 8001a44 <HAL_InitTick>
8002c10: 4603 mov r3, r0
8002c12: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
8002c14: 7bfb ldrb r3, [r7, #15]
8002c16: 2b00 cmp r3, #0
8002c18: d045 beq.n 8002ca6 <HAL_RCC_OscConfig+0x36a>
{
return status;
8002c1a: 7bfb ldrb r3, [r7, #15]
8002c1c: e1b5 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
{
/* Check MSI State */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8002c1e: 687b ldr r3, [r7, #4]
8002c20: 699b ldr r3, [r3, #24]
8002c22: 2b00 cmp r3, #0
8002c24: d029 beq.n 8002c7a <HAL_RCC_OscConfig+0x33e>
{
/* Enable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
8002c26: 4b7e ldr r3, [pc, #504] @ (8002e20 <HAL_RCC_OscConfig+0x4e4>)
8002c28: 2201 movs r2, #1
8002c2a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002c2c: f7fe ff56 bl 8001adc <HAL_GetTick>
8002c30: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
8002c32: e008 b.n 8002c46 <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8002c34: f7fe ff52 bl 8001adc <HAL_GetTick>
8002c38: 4602 mov r2, r0
8002c3a: 693b ldr r3, [r7, #16]
8002c3c: 1ad3 subs r3, r2, r3
8002c3e: 2b02 cmp r3, #2
8002c40: d901 bls.n 8002c46 <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
8002c42: 2303 movs r3, #3
8002c44: e1a1 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
8002c46: 4b72 ldr r3, [pc, #456] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002c48: 681b ldr r3, [r3, #0]
8002c4a: f403 7300 and.w r3, r3, #512 @ 0x200
8002c4e: 2b00 cmp r3, #0
8002c50: d0f0 beq.n 8002c34 <HAL_RCC_OscConfig+0x2f8>
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
8002c52: 4b6f ldr r3, [pc, #444] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002c54: 685b ldr r3, [r3, #4]
8002c56: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8002c5a: 687b ldr r3, [r7, #4]
8002c5c: 6a1b ldr r3, [r3, #32]
8002c5e: 496c ldr r1, [pc, #432] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002c60: 4313 orrs r3, r2
8002c62: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8002c64: 4b6a ldr r3, [pc, #424] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002c66: 685b ldr r3, [r3, #4]
8002c68: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
8002c6c: 687b ldr r3, [r7, #4]
8002c6e: 69db ldr r3, [r3, #28]
8002c70: 061b lsls r3, r3, #24
8002c72: 4967 ldr r1, [pc, #412] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002c74: 4313 orrs r3, r2
8002c76: 604b str r3, [r1, #4]
8002c78: e015 b.n 8002ca6 <HAL_RCC_OscConfig+0x36a>
}
else
{
/* Disable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
8002c7a: 4b69 ldr r3, [pc, #420] @ (8002e20 <HAL_RCC_OscConfig+0x4e4>)
8002c7c: 2200 movs r2, #0
8002c7e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002c80: f7fe ff2c bl 8001adc <HAL_GetTick>
8002c84: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
8002c86: e008 b.n 8002c9a <HAL_RCC_OscConfig+0x35e>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
8002c88: f7fe ff28 bl 8001adc <HAL_GetTick>
8002c8c: 4602 mov r2, r0
8002c8e: 693b ldr r3, [r7, #16]
8002c90: 1ad3 subs r3, r2, r3
8002c92: 2b02 cmp r3, #2
8002c94: d901 bls.n 8002c9a <HAL_RCC_OscConfig+0x35e>
{
return HAL_TIMEOUT;
8002c96: 2303 movs r3, #3
8002c98: e177 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
8002c9a: 4b5d ldr r3, [pc, #372] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002c9c: 681b ldr r3, [r3, #0]
8002c9e: f403 7300 and.w r3, r3, #512 @ 0x200
8002ca2: 2b00 cmp r3, #0
8002ca4: d1f0 bne.n 8002c88 <HAL_RCC_OscConfig+0x34c>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8002ca6: 687b ldr r3, [r7, #4]
8002ca8: 681b ldr r3, [r3, #0]
8002caa: f003 0308 and.w r3, r3, #8
8002cae: 2b00 cmp r3, #0
8002cb0: d030 beq.n 8002d14 <HAL_RCC_OscConfig+0x3d8>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8002cb2: 687b ldr r3, [r7, #4]
8002cb4: 695b ldr r3, [r3, #20]
8002cb6: 2b00 cmp r3, #0
8002cb8: d016 beq.n 8002ce8 <HAL_RCC_OscConfig+0x3ac>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8002cba: 4b5a ldr r3, [pc, #360] @ (8002e24 <HAL_RCC_OscConfig+0x4e8>)
8002cbc: 2201 movs r2, #1
8002cbe: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002cc0: f7fe ff0c bl 8001adc <HAL_GetTick>
8002cc4: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
8002cc6: e008 b.n 8002cda <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002cc8: f7fe ff08 bl 8001adc <HAL_GetTick>
8002ccc: 4602 mov r2, r0
8002cce: 693b ldr r3, [r7, #16]
8002cd0: 1ad3 subs r3, r2, r3
8002cd2: 2b02 cmp r3, #2
8002cd4: d901 bls.n 8002cda <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
8002cd6: 2303 movs r3, #3
8002cd8: e157 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
8002cda: 4b4d ldr r3, [pc, #308] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002cdc: 6b5b ldr r3, [r3, #52] @ 0x34
8002cde: f003 0302 and.w r3, r3, #2
8002ce2: 2b00 cmp r3, #0
8002ce4: d0f0 beq.n 8002cc8 <HAL_RCC_OscConfig+0x38c>
8002ce6: e015 b.n 8002d14 <HAL_RCC_OscConfig+0x3d8>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002ce8: 4b4e ldr r3, [pc, #312] @ (8002e24 <HAL_RCC_OscConfig+0x4e8>)
8002cea: 2200 movs r2, #0
8002cec: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002cee: f7fe fef5 bl 8001adc <HAL_GetTick>
8002cf2: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8002cf4: e008 b.n 8002d08 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002cf6: f7fe fef1 bl 8001adc <HAL_GetTick>
8002cfa: 4602 mov r2, r0
8002cfc: 693b ldr r3, [r7, #16]
8002cfe: 1ad3 subs r3, r2, r3
8002d00: 2b02 cmp r3, #2
8002d02: d901 bls.n 8002d08 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
8002d04: 2303 movs r3, #3
8002d06: e140 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8002d08: 4b41 ldr r3, [pc, #260] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002d0a: 6b5b ldr r3, [r3, #52] @ 0x34
8002d0c: f003 0302 and.w r3, r3, #2
8002d10: 2b00 cmp r3, #0
8002d12: d1f0 bne.n 8002cf6 <HAL_RCC_OscConfig+0x3ba>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002d14: 687b ldr r3, [r7, #4]
8002d16: 681b ldr r3, [r3, #0]
8002d18: f003 0304 and.w r3, r3, #4
8002d1c: 2b00 cmp r3, #0
8002d1e: f000 80b5 beq.w 8002e8c <HAL_RCC_OscConfig+0x550>
{
FlagStatus pwrclkchanged = RESET;
8002d22: 2300 movs r3, #0
8002d24: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8002d26: 4b3a ldr r3, [pc, #232] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002d28: 6a5b ldr r3, [r3, #36] @ 0x24
8002d2a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002d2e: 2b00 cmp r3, #0
8002d30: d10d bne.n 8002d4e <HAL_RCC_OscConfig+0x412>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002d32: 4b37 ldr r3, [pc, #220] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002d34: 6a5b ldr r3, [r3, #36] @ 0x24
8002d36: 4a36 ldr r2, [pc, #216] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002d38: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002d3c: 6253 str r3, [r2, #36] @ 0x24
8002d3e: 4b34 ldr r3, [pc, #208] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002d40: 6a5b ldr r3, [r3, #36] @ 0x24
8002d42: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002d46: 60bb str r3, [r7, #8]
8002d48: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002d4a: 2301 movs r3, #1
8002d4c: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002d4e: 4b36 ldr r3, [pc, #216] @ (8002e28 <HAL_RCC_OscConfig+0x4ec>)
8002d50: 681b ldr r3, [r3, #0]
8002d52: f403 7380 and.w r3, r3, #256 @ 0x100
8002d56: 2b00 cmp r3, #0
8002d58: d118 bne.n 8002d8c <HAL_RCC_OscConfig+0x450>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8002d5a: 4b33 ldr r3, [pc, #204] @ (8002e28 <HAL_RCC_OscConfig+0x4ec>)
8002d5c: 681b ldr r3, [r3, #0]
8002d5e: 4a32 ldr r2, [pc, #200] @ (8002e28 <HAL_RCC_OscConfig+0x4ec>)
8002d60: f443 7380 orr.w r3, r3, #256 @ 0x100
8002d64: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002d66: f7fe feb9 bl 8001adc <HAL_GetTick>
8002d6a: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002d6c: e008 b.n 8002d80 <HAL_RCC_OscConfig+0x444>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002d6e: f7fe feb5 bl 8001adc <HAL_GetTick>
8002d72: 4602 mov r2, r0
8002d74: 693b ldr r3, [r7, #16]
8002d76: 1ad3 subs r3, r2, r3
8002d78: 2b64 cmp r3, #100 @ 0x64
8002d7a: d901 bls.n 8002d80 <HAL_RCC_OscConfig+0x444>
{
return HAL_TIMEOUT;
8002d7c: 2303 movs r3, #3
8002d7e: e104 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002d80: 4b29 ldr r3, [pc, #164] @ (8002e28 <HAL_RCC_OscConfig+0x4ec>)
8002d82: 681b ldr r3, [r3, #0]
8002d84: f403 7380 and.w r3, r3, #256 @ 0x100
8002d88: 2b00 cmp r3, #0
8002d8a: d0f0 beq.n 8002d6e <HAL_RCC_OscConfig+0x432>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002d8c: 687b ldr r3, [r7, #4]
8002d8e: 689b ldr r3, [r3, #8]
8002d90: 2b01 cmp r3, #1
8002d92: d106 bne.n 8002da2 <HAL_RCC_OscConfig+0x466>
8002d94: 4b1e ldr r3, [pc, #120] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002d96: 6b5b ldr r3, [r3, #52] @ 0x34
8002d98: 4a1d ldr r2, [pc, #116] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002d9a: f443 7380 orr.w r3, r3, #256 @ 0x100
8002d9e: 6353 str r3, [r2, #52] @ 0x34
8002da0: e02d b.n 8002dfe <HAL_RCC_OscConfig+0x4c2>
8002da2: 687b ldr r3, [r7, #4]
8002da4: 689b ldr r3, [r3, #8]
8002da6: 2b00 cmp r3, #0
8002da8: d10c bne.n 8002dc4 <HAL_RCC_OscConfig+0x488>
8002daa: 4b19 ldr r3, [pc, #100] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002dac: 6b5b ldr r3, [r3, #52] @ 0x34
8002dae: 4a18 ldr r2, [pc, #96] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002db0: f423 7380 bic.w r3, r3, #256 @ 0x100
8002db4: 6353 str r3, [r2, #52] @ 0x34
8002db6: 4b16 ldr r3, [pc, #88] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002db8: 6b5b ldr r3, [r3, #52] @ 0x34
8002dba: 4a15 ldr r2, [pc, #84] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002dbc: f423 6380 bic.w r3, r3, #1024 @ 0x400
8002dc0: 6353 str r3, [r2, #52] @ 0x34
8002dc2: e01c b.n 8002dfe <HAL_RCC_OscConfig+0x4c2>
8002dc4: 687b ldr r3, [r7, #4]
8002dc6: 689b ldr r3, [r3, #8]
8002dc8: 2b05 cmp r3, #5
8002dca: d10c bne.n 8002de6 <HAL_RCC_OscConfig+0x4aa>
8002dcc: 4b10 ldr r3, [pc, #64] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002dce: 6b5b ldr r3, [r3, #52] @ 0x34
8002dd0: 4a0f ldr r2, [pc, #60] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002dd2: f443 6380 orr.w r3, r3, #1024 @ 0x400
8002dd6: 6353 str r3, [r2, #52] @ 0x34
8002dd8: 4b0d ldr r3, [pc, #52] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002dda: 6b5b ldr r3, [r3, #52] @ 0x34
8002ddc: 4a0c ldr r2, [pc, #48] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002dde: f443 7380 orr.w r3, r3, #256 @ 0x100
8002de2: 6353 str r3, [r2, #52] @ 0x34
8002de4: e00b b.n 8002dfe <HAL_RCC_OscConfig+0x4c2>
8002de6: 4b0a ldr r3, [pc, #40] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002de8: 6b5b ldr r3, [r3, #52] @ 0x34
8002dea: 4a09 ldr r2, [pc, #36] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002dec: f423 7380 bic.w r3, r3, #256 @ 0x100
8002df0: 6353 str r3, [r2, #52] @ 0x34
8002df2: 4b07 ldr r3, [pc, #28] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002df4: 6b5b ldr r3, [r3, #52] @ 0x34
8002df6: 4a06 ldr r2, [pc, #24] @ (8002e10 <HAL_RCC_OscConfig+0x4d4>)
8002df8: f423 6380 bic.w r3, r3, #1024 @ 0x400
8002dfc: 6353 str r3, [r2, #52] @ 0x34
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8002dfe: 687b ldr r3, [r7, #4]
8002e00: 689b ldr r3, [r3, #8]
8002e02: 2b00 cmp r3, #0
8002e04: d024 beq.n 8002e50 <HAL_RCC_OscConfig+0x514>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e06: f7fe fe69 bl 8001adc <HAL_GetTick>
8002e0a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8002e0c: e019 b.n 8002e42 <HAL_RCC_OscConfig+0x506>
8002e0e: bf00 nop
8002e10: 40023800 .word 0x40023800
8002e14: 08004098 .word 0x08004098
8002e18: 20000000 .word 0x20000000
8002e1c: 20000004 .word 0x20000004
8002e20: 42470020 .word 0x42470020
8002e24: 42470680 .word 0x42470680
8002e28: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002e2c: f7fe fe56 bl 8001adc <HAL_GetTick>
8002e30: 4602 mov r2, r0
8002e32: 693b ldr r3, [r7, #16]
8002e34: 1ad3 subs r3, r2, r3
8002e36: f241 3288 movw r2, #5000 @ 0x1388
8002e3a: 4293 cmp r3, r2
8002e3c: d901 bls.n 8002e42 <HAL_RCC_OscConfig+0x506>
{
return HAL_TIMEOUT;
8002e3e: 2303 movs r3, #3
8002e40: e0a3 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8002e42: 4b54 ldr r3, [pc, #336] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002e44: 6b5b ldr r3, [r3, #52] @ 0x34
8002e46: f403 7300 and.w r3, r3, #512 @ 0x200
8002e4a: 2b00 cmp r3, #0
8002e4c: d0ee beq.n 8002e2c <HAL_RCC_OscConfig+0x4f0>
8002e4e: e014 b.n 8002e7a <HAL_RCC_OscConfig+0x53e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e50: f7fe fe44 bl 8001adc <HAL_GetTick>
8002e54: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
8002e56: e00a b.n 8002e6e <HAL_RCC_OscConfig+0x532>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002e58: f7fe fe40 bl 8001adc <HAL_GetTick>
8002e5c: 4602 mov r2, r0
8002e5e: 693b ldr r3, [r7, #16]
8002e60: 1ad3 subs r3, r2, r3
8002e62: f241 3288 movw r2, #5000 @ 0x1388
8002e66: 4293 cmp r3, r2
8002e68: d901 bls.n 8002e6e <HAL_RCC_OscConfig+0x532>
{
return HAL_TIMEOUT;
8002e6a: 2303 movs r3, #3
8002e6c: e08d b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
8002e6e: 4b49 ldr r3, [pc, #292] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002e70: 6b5b ldr r3, [r3, #52] @ 0x34
8002e72: f403 7300 and.w r3, r3, #512 @ 0x200
8002e76: 2b00 cmp r3, #0
8002e78: d1ee bne.n 8002e58 <HAL_RCC_OscConfig+0x51c>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8002e7a: 7ffb ldrb r3, [r7, #31]
8002e7c: 2b01 cmp r3, #1
8002e7e: d105 bne.n 8002e8c <HAL_RCC_OscConfig+0x550>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002e80: 4b44 ldr r3, [pc, #272] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002e82: 6a5b ldr r3, [r3, #36] @ 0x24
8002e84: 4a43 ldr r2, [pc, #268] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002e86: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002e8a: 6253 str r3, [r2, #36] @ 0x24
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8002e8c: 687b ldr r3, [r7, #4]
8002e8e: 6a5b ldr r3, [r3, #36] @ 0x24
8002e90: 2b00 cmp r3, #0
8002e92: d079 beq.n 8002f88 <HAL_RCC_OscConfig+0x64c>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8002e94: 69bb ldr r3, [r7, #24]
8002e96: 2b0c cmp r3, #12
8002e98: d056 beq.n 8002f48 <HAL_RCC_OscConfig+0x60c>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8002e9a: 687b ldr r3, [r7, #4]
8002e9c: 6a5b ldr r3, [r3, #36] @ 0x24
8002e9e: 2b02 cmp r3, #2
8002ea0: d13b bne.n 8002f1a <HAL_RCC_OscConfig+0x5de>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002ea2: 4b3d ldr r3, [pc, #244] @ (8002f98 <HAL_RCC_OscConfig+0x65c>)
8002ea4: 2200 movs r2, #0
8002ea6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002ea8: f7fe fe18 bl 8001adc <HAL_GetTick>
8002eac: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8002eae: e008 b.n 8002ec2 <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002eb0: f7fe fe14 bl 8001adc <HAL_GetTick>
8002eb4: 4602 mov r2, r0
8002eb6: 693b ldr r3, [r7, #16]
8002eb8: 1ad3 subs r3, r2, r3
8002eba: 2b02 cmp r3, #2
8002ebc: d901 bls.n 8002ec2 <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8002ebe: 2303 movs r3, #3
8002ec0: e063 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8002ec2: 4b34 ldr r3, [pc, #208] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002ec4: 681b ldr r3, [r3, #0]
8002ec6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002eca: 2b00 cmp r3, #0
8002ecc: d1f0 bne.n 8002eb0 <HAL_RCC_OscConfig+0x574>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002ece: 4b31 ldr r3, [pc, #196] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002ed0: 689b ldr r3, [r3, #8]
8002ed2: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000
8002ed6: 687b ldr r3, [r7, #4]
8002ed8: 6a99 ldr r1, [r3, #40] @ 0x28
8002eda: 687b ldr r3, [r7, #4]
8002edc: 6adb ldr r3, [r3, #44] @ 0x2c
8002ede: 4319 orrs r1, r3
8002ee0: 687b ldr r3, [r7, #4]
8002ee2: 6b1b ldr r3, [r3, #48] @ 0x30
8002ee4: 430b orrs r3, r1
8002ee6: 492b ldr r1, [pc, #172] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002ee8: 4313 orrs r3, r2
8002eea: 608b str r3, [r1, #8]
RCC_OscInitStruct->PLL.PLLMUL,
RCC_OscInitStruct->PLL.PLLDIV);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002eec: 4b2a ldr r3, [pc, #168] @ (8002f98 <HAL_RCC_OscConfig+0x65c>)
8002eee: 2201 movs r2, #1
8002ef0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002ef2: f7fe fdf3 bl 8001adc <HAL_GetTick>
8002ef6: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8002ef8: e008 b.n 8002f0c <HAL_RCC_OscConfig+0x5d0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002efa: f7fe fdef bl 8001adc <HAL_GetTick>
8002efe: 4602 mov r2, r0
8002f00: 693b ldr r3, [r7, #16]
8002f02: 1ad3 subs r3, r2, r3
8002f04: 2b02 cmp r3, #2
8002f06: d901 bls.n 8002f0c <HAL_RCC_OscConfig+0x5d0>
{
return HAL_TIMEOUT;
8002f08: 2303 movs r3, #3
8002f0a: e03e b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8002f0c: 4b21 ldr r3, [pc, #132] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002f0e: 681b ldr r3, [r3, #0]
8002f10: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002f14: 2b00 cmp r3, #0
8002f16: d0f0 beq.n 8002efa <HAL_RCC_OscConfig+0x5be>
8002f18: e036 b.n 8002f88 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002f1a: 4b1f ldr r3, [pc, #124] @ (8002f98 <HAL_RCC_OscConfig+0x65c>)
8002f1c: 2200 movs r2, #0
8002f1e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002f20: f7fe fddc bl 8001adc <HAL_GetTick>
8002f24: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8002f26: e008 b.n 8002f3a <HAL_RCC_OscConfig+0x5fe>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002f28: f7fe fdd8 bl 8001adc <HAL_GetTick>
8002f2c: 4602 mov r2, r0
8002f2e: 693b ldr r3, [r7, #16]
8002f30: 1ad3 subs r3, r2, r3
8002f32: 2b02 cmp r3, #2
8002f34: d901 bls.n 8002f3a <HAL_RCC_OscConfig+0x5fe>
{
return HAL_TIMEOUT;
8002f36: 2303 movs r3, #3
8002f38: e027 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8002f3a: 4b16 ldr r3, [pc, #88] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002f3c: 681b ldr r3, [r3, #0]
8002f3e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002f42: 2b00 cmp r3, #0
8002f44: d1f0 bne.n 8002f28 <HAL_RCC_OscConfig+0x5ec>
8002f46: e01f b.n 8002f88 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002f48: 687b ldr r3, [r7, #4]
8002f4a: 6a5b ldr r3, [r3, #36] @ 0x24
8002f4c: 2b01 cmp r3, #1
8002f4e: d101 bne.n 8002f54 <HAL_RCC_OscConfig+0x618>
{
return HAL_ERROR;
8002f50: 2301 movs r3, #1
8002f52: e01a b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8002f54: 4b0f ldr r3, [pc, #60] @ (8002f94 <HAL_RCC_OscConfig+0x658>)
8002f56: 689b ldr r3, [r3, #8]
8002f58: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002f5a: 697b ldr r3, [r7, #20]
8002f5c: f403 3280 and.w r2, r3, #65536 @ 0x10000
8002f60: 687b ldr r3, [r7, #4]
8002f62: 6a9b ldr r3, [r3, #40] @ 0x28
8002f64: 429a cmp r2, r3
8002f66: d10d bne.n 8002f84 <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
8002f68: 697b ldr r3, [r7, #20]
8002f6a: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
8002f6e: 687b ldr r3, [r7, #4]
8002f70: 6adb ldr r3, [r3, #44] @ 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002f72: 429a cmp r2, r3
8002f74: d106 bne.n 8002f84 <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
8002f76: 697b ldr r3, [r7, #20]
8002f78: f403 0240 and.w r2, r3, #12582912 @ 0xc00000
8002f7c: 687b ldr r3, [r7, #4]
8002f7e: 6b1b ldr r3, [r3, #48] @ 0x30
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
8002f80: 429a cmp r2, r3
8002f82: d001 beq.n 8002f88 <HAL_RCC_OscConfig+0x64c>
{
return HAL_ERROR;
8002f84: 2301 movs r3, #1
8002f86: e000 b.n 8002f8a <HAL_RCC_OscConfig+0x64e>
}
}
}
}
return HAL_OK;
8002f88: 2300 movs r3, #0
}
8002f8a: 4618 mov r0, r3
8002f8c: 3720 adds r7, #32
8002f8e: 46bd mov sp, r7
8002f90: bd80 pop {r7, pc}
8002f92: bf00 nop
8002f94: 40023800 .word 0x40023800
8002f98: 42470060 .word 0x42470060
08002f9c <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002f9c: b580 push {r7, lr}
8002f9e: b084 sub sp, #16
8002fa0: af00 add r7, sp, #0
8002fa2: 6078 str r0, [r7, #4]
8002fa4: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status;
/* Check the parameters */
if(RCC_ClkInitStruct == NULL)
8002fa6: 687b ldr r3, [r7, #4]
8002fa8: 2b00 cmp r3, #0
8002faa: d101 bne.n 8002fb0 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8002fac: 2301 movs r3, #1
8002fae: e11a b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002fb0: 4b8f ldr r3, [pc, #572] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8002fb2: 681b ldr r3, [r3, #0]
8002fb4: f003 0301 and.w r3, r3, #1
8002fb8: 683a ldr r2, [r7, #0]
8002fba: 429a cmp r2, r3
8002fbc: d919 bls.n 8002ff2 <HAL_RCC_ClockConfig+0x56>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002fbe: 683b ldr r3, [r7, #0]
8002fc0: 2b01 cmp r3, #1
8002fc2: d105 bne.n 8002fd0 <HAL_RCC_ClockConfig+0x34>
8002fc4: 4b8a ldr r3, [pc, #552] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8002fc6: 681b ldr r3, [r3, #0]
8002fc8: 4a89 ldr r2, [pc, #548] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8002fca: f043 0304 orr.w r3, r3, #4
8002fce: 6013 str r3, [r2, #0]
8002fd0: 4b87 ldr r3, [pc, #540] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8002fd2: 681b ldr r3, [r3, #0]
8002fd4: f023 0201 bic.w r2, r3, #1
8002fd8: 4985 ldr r1, [pc, #532] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8002fda: 683b ldr r3, [r7, #0]
8002fdc: 4313 orrs r3, r2
8002fde: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002fe0: 4b83 ldr r3, [pc, #524] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8002fe2: 681b ldr r3, [r3, #0]
8002fe4: f003 0301 and.w r3, r3, #1
8002fe8: 683a ldr r2, [r7, #0]
8002fea: 429a cmp r2, r3
8002fec: d001 beq.n 8002ff2 <HAL_RCC_ClockConfig+0x56>
{
return HAL_ERROR;
8002fee: 2301 movs r3, #1
8002ff0: e0f9 b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002ff2: 687b ldr r3, [r7, #4]
8002ff4: 681b ldr r3, [r3, #0]
8002ff6: f003 0302 and.w r3, r3, #2
8002ffa: 2b00 cmp r3, #0
8002ffc: d008 beq.n 8003010 <HAL_RCC_ClockConfig+0x74>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002ffe: 4b7d ldr r3, [pc, #500] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003000: 689b ldr r3, [r3, #8]
8003002: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8003006: 687b ldr r3, [r7, #4]
8003008: 689b ldr r3, [r3, #8]
800300a: 497a ldr r1, [pc, #488] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
800300c: 4313 orrs r3, r2
800300e: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003010: 687b ldr r3, [r7, #4]
8003012: 681b ldr r3, [r3, #0]
8003014: f003 0301 and.w r3, r3, #1
8003018: 2b00 cmp r3, #0
800301a: f000 808e beq.w 800313a <HAL_RCC_ClockConfig+0x19e>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800301e: 687b ldr r3, [r7, #4]
8003020: 685b ldr r3, [r3, #4]
8003022: 2b02 cmp r3, #2
8003024: d107 bne.n 8003036 <HAL_RCC_ClockConfig+0x9a>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8003026: 4b73 ldr r3, [pc, #460] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003028: 681b ldr r3, [r3, #0]
800302a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800302e: 2b00 cmp r3, #0
8003030: d121 bne.n 8003076 <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8003032: 2301 movs r3, #1
8003034: e0d7 b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8003036: 687b ldr r3, [r7, #4]
8003038: 685b ldr r3, [r3, #4]
800303a: 2b03 cmp r3, #3
800303c: d107 bne.n 800304e <HAL_RCC_ClockConfig+0xb2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
800303e: 4b6d ldr r3, [pc, #436] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003040: 681b ldr r3, [r3, #0]
8003042: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003046: 2b00 cmp r3, #0
8003048: d115 bne.n 8003076 <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800304a: 2301 movs r3, #1
800304c: e0cb b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
}
}
/* HSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
800304e: 687b ldr r3, [r7, #4]
8003050: 685b ldr r3, [r3, #4]
8003052: 2b01 cmp r3, #1
8003054: d107 bne.n 8003066 <HAL_RCC_ClockConfig+0xca>
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8003056: 4b67 ldr r3, [pc, #412] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003058: 681b ldr r3, [r3, #0]
800305a: f003 0302 and.w r3, r3, #2
800305e: 2b00 cmp r3, #0
8003060: d109 bne.n 8003076 <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8003062: 2301 movs r3, #1
8003064: e0bf b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
}
/* MSI is selected as System Clock Source */
else
{
/* Check the MSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
8003066: 4b63 ldr r3, [pc, #396] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003068: 681b ldr r3, [r3, #0]
800306a: f403 7300 and.w r3, r3, #512 @ 0x200
800306e: 2b00 cmp r3, #0
8003070: d101 bne.n 8003076 <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8003072: 2301 movs r3, #1
8003074: e0b7 b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8003076: 4b5f ldr r3, [pc, #380] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003078: 689b ldr r3, [r3, #8]
800307a: f023 0203 bic.w r2, r3, #3
800307e: 687b ldr r3, [r7, #4]
8003080: 685b ldr r3, [r3, #4]
8003082: 495c ldr r1, [pc, #368] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003084: 4313 orrs r3, r2
8003086: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003088: f7fe fd28 bl 8001adc <HAL_GetTick>
800308c: 60f8 str r0, [r7, #12]
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800308e: 687b ldr r3, [r7, #4]
8003090: 685b ldr r3, [r3, #4]
8003092: 2b02 cmp r3, #2
8003094: d112 bne.n 80030bc <HAL_RCC_ClockConfig+0x120>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
8003096: e00a b.n 80030ae <HAL_RCC_ClockConfig+0x112>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8003098: f7fe fd20 bl 8001adc <HAL_GetTick>
800309c: 4602 mov r2, r0
800309e: 68fb ldr r3, [r7, #12]
80030a0: 1ad3 subs r3, r2, r3
80030a2: f241 3288 movw r2, #5000 @ 0x1388
80030a6: 4293 cmp r3, r2
80030a8: d901 bls.n 80030ae <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
80030aa: 2303 movs r3, #3
80030ac: e09b b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
80030ae: 4b51 ldr r3, [pc, #324] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
80030b0: 689b ldr r3, [r3, #8]
80030b2: f003 030c and.w r3, r3, #12
80030b6: 2b08 cmp r3, #8
80030b8: d1ee bne.n 8003098 <HAL_RCC_ClockConfig+0xfc>
80030ba: e03e b.n 800313a <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80030bc: 687b ldr r3, [r7, #4]
80030be: 685b ldr r3, [r3, #4]
80030c0: 2b03 cmp r3, #3
80030c2: d112 bne.n 80030ea <HAL_RCC_ClockConfig+0x14e>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80030c4: e00a b.n 80030dc <HAL_RCC_ClockConfig+0x140>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80030c6: f7fe fd09 bl 8001adc <HAL_GetTick>
80030ca: 4602 mov r2, r0
80030cc: 68fb ldr r3, [r7, #12]
80030ce: 1ad3 subs r3, r2, r3
80030d0: f241 3288 movw r2, #5000 @ 0x1388
80030d4: 4293 cmp r3, r2
80030d6: d901 bls.n 80030dc <HAL_RCC_ClockConfig+0x140>
{
return HAL_TIMEOUT;
80030d8: 2303 movs r3, #3
80030da: e084 b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80030dc: 4b45 ldr r3, [pc, #276] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
80030de: 689b ldr r3, [r3, #8]
80030e0: f003 030c and.w r3, r3, #12
80030e4: 2b0c cmp r3, #12
80030e6: d1ee bne.n 80030c6 <HAL_RCC_ClockConfig+0x12a>
80030e8: e027 b.n 800313a <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
80030ea: 687b ldr r3, [r7, #4]
80030ec: 685b ldr r3, [r3, #4]
80030ee: 2b01 cmp r3, #1
80030f0: d11d bne.n 800312e <HAL_RCC_ClockConfig+0x192>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
80030f2: e00a b.n 800310a <HAL_RCC_ClockConfig+0x16e>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80030f4: f7fe fcf2 bl 8001adc <HAL_GetTick>
80030f8: 4602 mov r2, r0
80030fa: 68fb ldr r3, [r7, #12]
80030fc: 1ad3 subs r3, r2, r3
80030fe: f241 3288 movw r2, #5000 @ 0x1388
8003102: 4293 cmp r3, r2
8003104: d901 bls.n 800310a <HAL_RCC_ClockConfig+0x16e>
{
return HAL_TIMEOUT;
8003106: 2303 movs r3, #3
8003108: e06d b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
800310a: 4b3a ldr r3, [pc, #232] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
800310c: 689b ldr r3, [r3, #8]
800310e: f003 030c and.w r3, r3, #12
8003112: 2b04 cmp r3, #4
8003114: d1ee bne.n 80030f4 <HAL_RCC_ClockConfig+0x158>
8003116: e010 b.n 800313a <HAL_RCC_ClockConfig+0x19e>
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8003118: f7fe fce0 bl 8001adc <HAL_GetTick>
800311c: 4602 mov r2, r0
800311e: 68fb ldr r3, [r7, #12]
8003120: 1ad3 subs r3, r2, r3
8003122: f241 3288 movw r2, #5000 @ 0x1388
8003126: 4293 cmp r3, r2
8003128: d901 bls.n 800312e <HAL_RCC_ClockConfig+0x192>
{
return HAL_TIMEOUT;
800312a: 2303 movs r3, #3
800312c: e05b b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
800312e: 4b31 ldr r3, [pc, #196] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003130: 689b ldr r3, [r3, #8]
8003132: f003 030c and.w r3, r3, #12
8003136: 2b00 cmp r3, #0
8003138: d1ee bne.n 8003118 <HAL_RCC_ClockConfig+0x17c>
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
800313a: 4b2d ldr r3, [pc, #180] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
800313c: 681b ldr r3, [r3, #0]
800313e: f003 0301 and.w r3, r3, #1
8003142: 683a ldr r2, [r7, #0]
8003144: 429a cmp r2, r3
8003146: d219 bcs.n 800317c <HAL_RCC_ClockConfig+0x1e0>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003148: 683b ldr r3, [r7, #0]
800314a: 2b01 cmp r3, #1
800314c: d105 bne.n 800315a <HAL_RCC_ClockConfig+0x1be>
800314e: 4b28 ldr r3, [pc, #160] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8003150: 681b ldr r3, [r3, #0]
8003152: 4a27 ldr r2, [pc, #156] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8003154: f043 0304 orr.w r3, r3, #4
8003158: 6013 str r3, [r2, #0]
800315a: 4b25 ldr r3, [pc, #148] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
800315c: 681b ldr r3, [r3, #0]
800315e: f023 0201 bic.w r2, r3, #1
8003162: 4923 ldr r1, [pc, #140] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
8003164: 683b ldr r3, [r7, #0]
8003166: 4313 orrs r3, r2
8003168: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800316a: 4b21 ldr r3, [pc, #132] @ (80031f0 <HAL_RCC_ClockConfig+0x254>)
800316c: 681b ldr r3, [r3, #0]
800316e: f003 0301 and.w r3, r3, #1
8003172: 683a ldr r2, [r7, #0]
8003174: 429a cmp r2, r3
8003176: d001 beq.n 800317c <HAL_RCC_ClockConfig+0x1e0>
{
return HAL_ERROR;
8003178: 2301 movs r3, #1
800317a: e034 b.n 80031e6 <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
800317c: 687b ldr r3, [r7, #4]
800317e: 681b ldr r3, [r3, #0]
8003180: f003 0304 and.w r3, r3, #4
8003184: 2b00 cmp r3, #0
8003186: d008 beq.n 800319a <HAL_RCC_ClockConfig+0x1fe>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8003188: 4b1a ldr r3, [pc, #104] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
800318a: 689b ldr r3, [r3, #8]
800318c: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8003190: 687b ldr r3, [r7, #4]
8003192: 68db ldr r3, [r3, #12]
8003194: 4917 ldr r1, [pc, #92] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
8003196: 4313 orrs r3, r2
8003198: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800319a: 687b ldr r3, [r7, #4]
800319c: 681b ldr r3, [r3, #0]
800319e: f003 0308 and.w r3, r3, #8
80031a2: 2b00 cmp r3, #0
80031a4: d009 beq.n 80031ba <HAL_RCC_ClockConfig+0x21e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80031a6: 4b13 ldr r3, [pc, #76] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
80031a8: 689b ldr r3, [r3, #8]
80031aa: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80031ae: 687b ldr r3, [r7, #4]
80031b0: 691b ldr r3, [r3, #16]
80031b2: 00db lsls r3, r3, #3
80031b4: 490f ldr r1, [pc, #60] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
80031b6: 4313 orrs r3, r2
80031b8: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
80031ba: f000 f823 bl 8003204 <HAL_RCC_GetSysClockFreq>
80031be: 4602 mov r2, r0
80031c0: 4b0c ldr r3, [pc, #48] @ (80031f4 <HAL_RCC_ClockConfig+0x258>)
80031c2: 689b ldr r3, [r3, #8]
80031c4: 091b lsrs r3, r3, #4
80031c6: f003 030f and.w r3, r3, #15
80031ca: 490b ldr r1, [pc, #44] @ (80031f8 <HAL_RCC_ClockConfig+0x25c>)
80031cc: 5ccb ldrb r3, [r1, r3]
80031ce: fa22 f303 lsr.w r3, r2, r3
80031d2: 4a0a ldr r2, [pc, #40] @ (80031fc <HAL_RCC_ClockConfig+0x260>)
80031d4: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
80031d6: 4b0a ldr r3, [pc, #40] @ (8003200 <HAL_RCC_ClockConfig+0x264>)
80031d8: 681b ldr r3, [r3, #0]
80031da: 4618 mov r0, r3
80031dc: f7fe fc32 bl 8001a44 <HAL_InitTick>
80031e0: 4603 mov r3, r0
80031e2: 72fb strb r3, [r7, #11]
return status;
80031e4: 7afb ldrb r3, [r7, #11]
}
80031e6: 4618 mov r0, r3
80031e8: 3710 adds r7, #16
80031ea: 46bd mov sp, r7
80031ec: bd80 pop {r7, pc}
80031ee: bf00 nop
80031f0: 40023c00 .word 0x40023c00
80031f4: 40023800 .word 0x40023800
80031f8: 08004098 .word 0x08004098
80031fc: 20000000 .word 0x20000000
8003200: 20000004 .word 0x20000004
08003204 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003204: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8003208: b08e sub sp, #56 @ 0x38
800320a: af00 add r7, sp, #0
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
tmpreg = RCC->CFGR;
800320c: 4b58 ldr r3, [pc, #352] @ (8003370 <HAL_RCC_GetSysClockFreq+0x16c>)
800320e: 689b ldr r3, [r3, #8]
8003210: 62fb str r3, [r7, #44] @ 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8003212: 6afb ldr r3, [r7, #44] @ 0x2c
8003214: f003 030c and.w r3, r3, #12
8003218: 2b0c cmp r3, #12
800321a: d00d beq.n 8003238 <HAL_RCC_GetSysClockFreq+0x34>
800321c: 2b0c cmp r3, #12
800321e: f200 8092 bhi.w 8003346 <HAL_RCC_GetSysClockFreq+0x142>
8003222: 2b04 cmp r3, #4
8003224: d002 beq.n 800322c <HAL_RCC_GetSysClockFreq+0x28>
8003226: 2b08 cmp r3, #8
8003228: d003 beq.n 8003232 <HAL_RCC_GetSysClockFreq+0x2e>
800322a: e08c b.n 8003346 <HAL_RCC_GetSysClockFreq+0x142>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
800322c: 4b51 ldr r3, [pc, #324] @ (8003374 <HAL_RCC_GetSysClockFreq+0x170>)
800322e: 633b str r3, [r7, #48] @ 0x30
break;
8003230: e097 b.n 8003362 <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8003232: 4b51 ldr r3, [pc, #324] @ (8003378 <HAL_RCC_GetSysClockFreq+0x174>)
8003234: 633b str r3, [r7, #48] @ 0x30
break;
8003236: e094 b.n 8003362 <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
8003238: 6afb ldr r3, [r7, #44] @ 0x2c
800323a: 0c9b lsrs r3, r3, #18
800323c: f003 020f and.w r2, r3, #15
8003240: 4b4e ldr r3, [pc, #312] @ (800337c <HAL_RCC_GetSysClockFreq+0x178>)
8003242: 5c9b ldrb r3, [r3, r2]
8003244: 62bb str r3, [r7, #40] @ 0x28
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
8003246: 6afb ldr r3, [r7, #44] @ 0x2c
8003248: 0d9b lsrs r3, r3, #22
800324a: f003 0303 and.w r3, r3, #3
800324e: 3301 adds r3, #1
8003250: 627b str r3, [r7, #36] @ 0x24
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8003252: 4b47 ldr r3, [pc, #284] @ (8003370 <HAL_RCC_GetSysClockFreq+0x16c>)
8003254: 689b ldr r3, [r3, #8]
8003256: f403 3380 and.w r3, r3, #65536 @ 0x10000
800325a: 2b00 cmp r3, #0
800325c: d021 beq.n 80032a2 <HAL_RCC_GetSysClockFreq+0x9e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
800325e: 6abb ldr r3, [r7, #40] @ 0x28
8003260: 2200 movs r2, #0
8003262: 61bb str r3, [r7, #24]
8003264: 61fa str r2, [r7, #28]
8003266: 4b44 ldr r3, [pc, #272] @ (8003378 <HAL_RCC_GetSysClockFreq+0x174>)
8003268: e9d7 8906 ldrd r8, r9, [r7, #24]
800326c: 464a mov r2, r9
800326e: fb03 f202 mul.w r2, r3, r2
8003272: 2300 movs r3, #0
8003274: 4644 mov r4, r8
8003276: fb04 f303 mul.w r3, r4, r3
800327a: 4413 add r3, r2
800327c: 4a3e ldr r2, [pc, #248] @ (8003378 <HAL_RCC_GetSysClockFreq+0x174>)
800327e: 4644 mov r4, r8
8003280: fba4 0102 umull r0, r1, r4, r2
8003284: 440b add r3, r1
8003286: 4619 mov r1, r3
8003288: 6a7b ldr r3, [r7, #36] @ 0x24
800328a: 2200 movs r2, #0
800328c: 613b str r3, [r7, #16]
800328e: 617a str r2, [r7, #20]
8003290: e9d7 2304 ldrd r2, r3, [r7, #16]
8003294: f7fd fde0 bl 8000e58 <__aeabi_uldivmod>
8003298: 4602 mov r2, r0
800329a: 460b mov r3, r1
800329c: 4613 mov r3, r2
800329e: 637b str r3, [r7, #52] @ 0x34
80032a0: e04e b.n 8003340 <HAL_RCC_GetSysClockFreq+0x13c>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
80032a2: 6abb ldr r3, [r7, #40] @ 0x28
80032a4: 2200 movs r2, #0
80032a6: 469a mov sl, r3
80032a8: 4693 mov fp, r2
80032aa: 4652 mov r2, sl
80032ac: 465b mov r3, fp
80032ae: f04f 0000 mov.w r0, #0
80032b2: f04f 0100 mov.w r1, #0
80032b6: 0159 lsls r1, r3, #5
80032b8: ea41 61d2 orr.w r1, r1, r2, lsr #27
80032bc: 0150 lsls r0, r2, #5
80032be: 4602 mov r2, r0
80032c0: 460b mov r3, r1
80032c2: ebb2 080a subs.w r8, r2, sl
80032c6: eb63 090b sbc.w r9, r3, fp
80032ca: f04f 0200 mov.w r2, #0
80032ce: f04f 0300 mov.w r3, #0
80032d2: ea4f 1389 mov.w r3, r9, lsl #6
80032d6: ea43 6398 orr.w r3, r3, r8, lsr #26
80032da: ea4f 1288 mov.w r2, r8, lsl #6
80032de: ebb2 0408 subs.w r4, r2, r8
80032e2: eb63 0509 sbc.w r5, r3, r9
80032e6: f04f 0200 mov.w r2, #0
80032ea: f04f 0300 mov.w r3, #0
80032ee: 00eb lsls r3, r5, #3
80032f0: ea43 7354 orr.w r3, r3, r4, lsr #29
80032f4: 00e2 lsls r2, r4, #3
80032f6: 4614 mov r4, r2
80032f8: 461d mov r5, r3
80032fa: eb14 030a adds.w r3, r4, sl
80032fe: 603b str r3, [r7, #0]
8003300: eb45 030b adc.w r3, r5, fp
8003304: 607b str r3, [r7, #4]
8003306: f04f 0200 mov.w r2, #0
800330a: f04f 0300 mov.w r3, #0
800330e: e9d7 4500 ldrd r4, r5, [r7]
8003312: 4629 mov r1, r5
8003314: 028b lsls r3, r1, #10
8003316: 4620 mov r0, r4
8003318: 4629 mov r1, r5
800331a: 4604 mov r4, r0
800331c: ea43 5394 orr.w r3, r3, r4, lsr #22
8003320: 4601 mov r1, r0
8003322: 028a lsls r2, r1, #10
8003324: 4610 mov r0, r2
8003326: 4619 mov r1, r3
8003328: 6a7b ldr r3, [r7, #36] @ 0x24
800332a: 2200 movs r2, #0
800332c: 60bb str r3, [r7, #8]
800332e: 60fa str r2, [r7, #12]
8003330: e9d7 2302 ldrd r2, r3, [r7, #8]
8003334: f7fd fd90 bl 8000e58 <__aeabi_uldivmod>
8003338: 4602 mov r2, r0
800333a: 460b mov r3, r1
800333c: 4613 mov r3, r2
800333e: 637b str r3, [r7, #52] @ 0x34
}
sysclockfreq = pllvco;
8003340: 6b7b ldr r3, [r7, #52] @ 0x34
8003342: 633b str r3, [r7, #48] @ 0x30
break;
8003344: e00d b.n 8003362 <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
default: /* MSI used as system clock */
{
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
8003346: 4b0a ldr r3, [pc, #40] @ (8003370 <HAL_RCC_GetSysClockFreq+0x16c>)
8003348: 685b ldr r3, [r3, #4]
800334a: 0b5b lsrs r3, r3, #13
800334c: f003 0307 and.w r3, r3, #7
8003350: 623b str r3, [r7, #32]
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
8003352: 6a3b ldr r3, [r7, #32]
8003354: 3301 adds r3, #1
8003356: f44f 4200 mov.w r2, #32768 @ 0x8000
800335a: fa02 f303 lsl.w r3, r2, r3
800335e: 633b str r3, [r7, #48] @ 0x30
break;
8003360: bf00 nop
}
}
return sysclockfreq;
8003362: 6b3b ldr r3, [r7, #48] @ 0x30
}
8003364: 4618 mov r0, r3
8003366: 3738 adds r7, #56 @ 0x38
8003368: 46bd mov sp, r7
800336a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
800336e: bf00 nop
8003370: 40023800 .word 0x40023800
8003374: 00f42400 .word 0x00f42400
8003378: 016e3600 .word 0x016e3600
800337c: 0800408c .word 0x0800408c
08003380 <RCC_SetFlashLatencyFromMSIRange>:
voltage range
* @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
8003380: b480 push {r7}
8003382: b087 sub sp, #28
8003384: af00 add r7, sp, #0
8003386: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8003388: 2300 movs r3, #0
800338a: 613b str r3, [r7, #16]
/* HCLK can reach 4 MHz only if AHB prescaler = 1 */
if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
800338c: 4b29 ldr r3, [pc, #164] @ (8003434 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
800338e: 689b ldr r3, [r3, #8]
8003390: f003 03f0 and.w r3, r3, #240 @ 0xf0
8003394: 2b00 cmp r3, #0
8003396: d12c bne.n 80033f2 <RCC_SetFlashLatencyFromMSIRange+0x72>
{
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8003398: 4b26 ldr r3, [pc, #152] @ (8003434 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
800339a: 6a5b ldr r3, [r3, #36] @ 0x24
800339c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80033a0: 2b00 cmp r3, #0
80033a2: d005 beq.n 80033b0 <RCC_SetFlashLatencyFromMSIRange+0x30>
{
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
80033a4: 4b24 ldr r3, [pc, #144] @ (8003438 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80033a6: 681b ldr r3, [r3, #0]
80033a8: f403 53c0 and.w r3, r3, #6144 @ 0x1800
80033ac: 617b str r3, [r7, #20]
80033ae: e016 b.n 80033de <RCC_SetFlashLatencyFromMSIRange+0x5e>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
80033b0: 4b20 ldr r3, [pc, #128] @ (8003434 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80033b2: 6a5b ldr r3, [r3, #36] @ 0x24
80033b4: 4a1f ldr r2, [pc, #124] @ (8003434 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80033b6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80033ba: 6253 str r3, [r2, #36] @ 0x24
80033bc: 4b1d ldr r3, [pc, #116] @ (8003434 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80033be: 6a5b ldr r3, [r3, #36] @ 0x24
80033c0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80033c4: 60fb str r3, [r7, #12]
80033c6: 68fb ldr r3, [r7, #12]
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
80033c8: 4b1b ldr r3, [pc, #108] @ (8003438 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80033ca: 681b ldr r3, [r3, #0]
80033cc: f403 53c0 and.w r3, r3, #6144 @ 0x1800
80033d0: 617b str r3, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
80033d2: 4b18 ldr r3, [pc, #96] @ (8003434 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80033d4: 6a5b ldr r3, [r3, #36] @ 0x24
80033d6: 4a17 ldr r2, [pc, #92] @ (8003434 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80033d8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80033dc: 6253 str r3, [r2, #36] @ 0x24
}
/* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
80033de: 697b ldr r3, [r7, #20]
80033e0: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800
80033e4: d105 bne.n 80033f2 <RCC_SetFlashLatencyFromMSIRange+0x72>
80033e6: 687b ldr r3, [r7, #4]
80033e8: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
80033ec: d101 bne.n 80033f2 <RCC_SetFlashLatencyFromMSIRange+0x72>
{
latency = FLASH_LATENCY_1; /* 1WS */
80033ee: 2301 movs r3, #1
80033f0: 613b str r3, [r7, #16]
}
}
__HAL_FLASH_SET_LATENCY(latency);
80033f2: 693b ldr r3, [r7, #16]
80033f4: 2b01 cmp r3, #1
80033f6: d105 bne.n 8003404 <RCC_SetFlashLatencyFromMSIRange+0x84>
80033f8: 4b10 ldr r3, [pc, #64] @ (800343c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80033fa: 681b ldr r3, [r3, #0]
80033fc: 4a0f ldr r2, [pc, #60] @ (800343c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
80033fe: f043 0304 orr.w r3, r3, #4
8003402: 6013 str r3, [r2, #0]
8003404: 4b0d ldr r3, [pc, #52] @ (800343c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8003406: 681b ldr r3, [r3, #0]
8003408: f023 0201 bic.w r2, r3, #1
800340c: 490b ldr r1, [pc, #44] @ (800343c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
800340e: 693b ldr r3, [r7, #16]
8003410: 4313 orrs r3, r2
8003412: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
8003414: 4b09 ldr r3, [pc, #36] @ (800343c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8003416: 681b ldr r3, [r3, #0]
8003418: f003 0301 and.w r3, r3, #1
800341c: 693a ldr r2, [r7, #16]
800341e: 429a cmp r2, r3
8003420: d001 beq.n 8003426 <RCC_SetFlashLatencyFromMSIRange+0xa6>
{
return HAL_ERROR;
8003422: 2301 movs r3, #1
8003424: e000 b.n 8003428 <RCC_SetFlashLatencyFromMSIRange+0xa8>
}
return HAL_OK;
8003426: 2300 movs r3, #0
}
8003428: 4618 mov r0, r3
800342a: 371c adds r7, #28
800342c: 46bd mov sp, r7
800342e: bc80 pop {r7}
8003430: 4770 bx lr
8003432: bf00 nop
8003434: 40023800 .word 0x40023800
8003438: 40007000 .word 0x40007000
800343c: 40023c00 .word 0x40023c00
08003440 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8003440: b580 push {r7, lr}
8003442: b082 sub sp, #8
8003444: af00 add r7, sp, #0
8003446: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
8003448: 687b ldr r3, [r7, #4]
800344a: 2b00 cmp r3, #0
800344c: d101 bne.n 8003452 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
800344e: 2301 movs r3, #1
8003450: e07b b.n 800354a <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
/* TI mode is not supported on all devices in stm32l1xx series.
TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8003452: 687b ldr r3, [r7, #4]
8003454: 6a5b ldr r3, [r3, #36] @ 0x24
8003456: 2b00 cmp r3, #0
8003458: d108 bne.n 800346c <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
800345a: 687b ldr r3, [r7, #4]
800345c: 685b ldr r3, [r3, #4]
800345e: f5b3 7f82 cmp.w r3, #260 @ 0x104
8003462: d009 beq.n 8003478 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8003464: 687b ldr r3, [r7, #4]
8003466: 2200 movs r2, #0
8003468: 61da str r2, [r3, #28]
800346a: e005 b.n 8003478 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
800346c: 687b ldr r3, [r7, #4]
800346e: 2200 movs r2, #0
8003470: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8003472: 687b ldr r3, [r7, #4]
8003474: 2200 movs r2, #0
8003476: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003478: 687b ldr r3, [r7, #4]
800347a: 2200 movs r2, #0
800347c: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
800347e: 687b ldr r3, [r7, #4]
8003480: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
8003484: b2db uxtb r3, r3
8003486: 2b00 cmp r3, #0
8003488: d106 bne.n 8003498 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
800348a: 687b ldr r3, [r7, #4]
800348c: 2200 movs r2, #0
800348e: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8003492: 6878 ldr r0, [r7, #4]
8003494: f7fe f9a6 bl 80017e4 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8003498: 687b ldr r3, [r7, #4]
800349a: 2202 movs r2, #2
800349c: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80034a0: 687b ldr r3, [r7, #4]
80034a2: 681b ldr r3, [r3, #0]
80034a4: 681a ldr r2, [r3, #0]
80034a6: 687b ldr r3, [r7, #4]
80034a8: 681b ldr r3, [r3, #0]
80034aa: f022 0240 bic.w r2, r2, #64 @ 0x40
80034ae: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
80034b0: 687b ldr r3, [r7, #4]
80034b2: 685b ldr r3, [r3, #4]
80034b4: f403 7282 and.w r2, r3, #260 @ 0x104
80034b8: 687b ldr r3, [r7, #4]
80034ba: 689b ldr r3, [r3, #8]
80034bc: f403 4304 and.w r3, r3, #33792 @ 0x8400
80034c0: 431a orrs r2, r3
80034c2: 687b ldr r3, [r7, #4]
80034c4: 68db ldr r3, [r3, #12]
80034c6: f403 6300 and.w r3, r3, #2048 @ 0x800
80034ca: 431a orrs r2, r3
80034cc: 687b ldr r3, [r7, #4]
80034ce: 691b ldr r3, [r3, #16]
80034d0: f003 0302 and.w r3, r3, #2
80034d4: 431a orrs r2, r3
80034d6: 687b ldr r3, [r7, #4]
80034d8: 695b ldr r3, [r3, #20]
80034da: f003 0301 and.w r3, r3, #1
80034de: 431a orrs r2, r3
80034e0: 687b ldr r3, [r7, #4]
80034e2: 699b ldr r3, [r3, #24]
80034e4: f403 7300 and.w r3, r3, #512 @ 0x200
80034e8: 431a orrs r2, r3
80034ea: 687b ldr r3, [r7, #4]
80034ec: 69db ldr r3, [r3, #28]
80034ee: f003 0338 and.w r3, r3, #56 @ 0x38
80034f2: 431a orrs r2, r3
80034f4: 687b ldr r3, [r7, #4]
80034f6: 6a1b ldr r3, [r3, #32]
80034f8: f003 0380 and.w r3, r3, #128 @ 0x80
80034fc: ea42 0103 orr.w r1, r2, r3
8003500: 687b ldr r3, [r7, #4]
8003502: 6a9b ldr r3, [r3, #40] @ 0x28
8003504: f403 5200 and.w r2, r3, #8192 @ 0x2000
8003508: 687b ldr r3, [r7, #4]
800350a: 681b ldr r3, [r3, #0]
800350c: 430a orrs r2, r1
800350e: 601a str r2, [r3, #0]
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
#if defined(SPI_CR2_FRF)
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
8003510: 687b ldr r3, [r7, #4]
8003512: 699b ldr r3, [r3, #24]
8003514: 0c1b lsrs r3, r3, #16
8003516: f003 0104 and.w r1, r3, #4
800351a: 687b ldr r3, [r7, #4]
800351c: 6a5b ldr r3, [r3, #36] @ 0x24
800351e: f003 0210 and.w r2, r3, #16
8003522: 687b ldr r3, [r7, #4]
8003524: 681b ldr r3, [r3, #0]
8003526: 430a orrs r2, r1
8003528: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
800352a: 687b ldr r3, [r7, #4]
800352c: 681b ldr r3, [r3, #0]
800352e: 69da ldr r2, [r3, #28]
8003530: 687b ldr r3, [r7, #4]
8003532: 681b ldr r3, [r3, #0]
8003534: f422 6200 bic.w r2, r2, #2048 @ 0x800
8003538: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800353a: 687b ldr r3, [r7, #4]
800353c: 2200 movs r2, #0
800353e: 655a str r2, [r3, #84] @ 0x54
hspi->State = HAL_SPI_STATE_READY;
8003540: 687b ldr r3, [r7, #4]
8003542: 2201 movs r2, #1
8003544: f883 2051 strb.w r2, [r3, #81] @ 0x51
return HAL_OK;
8003548: 2300 movs r3, #0
}
800354a: 4618 mov r0, r3
800354c: 3708 adds r7, #8
800354e: 46bd mov sp, r7
8003550: bd80 pop {r7, pc}
08003552 <HAL_SPI_Transmit>:
* @param Size amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration in ms
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003552: b580 push {r7, lr}
8003554: b088 sub sp, #32
8003556: af00 add r7, sp, #0
8003558: 60f8 str r0, [r7, #12]
800355a: 60b9 str r1, [r7, #8]
800355c: 603b str r3, [r7, #0]
800355e: 4613 mov r3, r2
8003560: 80fb strh r3, [r7, #6]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8003562: f7fe fabb bl 8001adc <HAL_GetTick>
8003566: 61f8 str r0, [r7, #28]
initial_TxXferCount = Size;
8003568: 88fb ldrh r3, [r7, #6]
800356a: 837b strh r3, [r7, #26]
if (hspi->State != HAL_SPI_STATE_READY)
800356c: 68fb ldr r3, [r7, #12]
800356e: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
8003572: b2db uxtb r3, r3
8003574: 2b01 cmp r3, #1
8003576: d001 beq.n 800357c <HAL_SPI_Transmit+0x2a>
{
return HAL_BUSY;
8003578: 2302 movs r3, #2
800357a: e12a b.n 80037d2 <HAL_SPI_Transmit+0x280>
}
if ((pData == NULL) || (Size == 0U))
800357c: 68bb ldr r3, [r7, #8]
800357e: 2b00 cmp r3, #0
8003580: d002 beq.n 8003588 <HAL_SPI_Transmit+0x36>
8003582: 88fb ldrh r3, [r7, #6]
8003584: 2b00 cmp r3, #0
8003586: d101 bne.n 800358c <HAL_SPI_Transmit+0x3a>
{
return HAL_ERROR;
8003588: 2301 movs r3, #1
800358a: e122 b.n 80037d2 <HAL_SPI_Transmit+0x280>
}
/* Process Locked */
__HAL_LOCK(hspi);
800358c: 68fb ldr r3, [r7, #12]
800358e: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
8003592: 2b01 cmp r3, #1
8003594: d101 bne.n 800359a <HAL_SPI_Transmit+0x48>
8003596: 2302 movs r3, #2
8003598: e11b b.n 80037d2 <HAL_SPI_Transmit+0x280>
800359a: 68fb ldr r3, [r7, #12]
800359c: 2201 movs r2, #1
800359e: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
80035a2: 68fb ldr r3, [r7, #12]
80035a4: 2203 movs r2, #3
80035a6: f883 2051 strb.w r2, [r3, #81] @ 0x51
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
80035aa: 68fb ldr r3, [r7, #12]
80035ac: 2200 movs r2, #0
80035ae: 655a str r2, [r3, #84] @ 0x54
hspi->pTxBuffPtr = (const uint8_t *)pData;
80035b0: 68fb ldr r3, [r7, #12]
80035b2: 68ba ldr r2, [r7, #8]
80035b4: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferSize = Size;
80035b6: 68fb ldr r3, [r7, #12]
80035b8: 88fa ldrh r2, [r7, #6]
80035ba: 869a strh r2, [r3, #52] @ 0x34
hspi->TxXferCount = Size;
80035bc: 68fb ldr r3, [r7, #12]
80035be: 88fa ldrh r2, [r7, #6]
80035c0: 86da strh r2, [r3, #54] @ 0x36
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
80035c2: 68fb ldr r3, [r7, #12]
80035c4: 2200 movs r2, #0
80035c6: 639a str r2, [r3, #56] @ 0x38
hspi->RxXferSize = 0U;
80035c8: 68fb ldr r3, [r7, #12]
80035ca: 2200 movs r2, #0
80035cc: 879a strh r2, [r3, #60] @ 0x3c
hspi->RxXferCount = 0U;
80035ce: 68fb ldr r3, [r7, #12]
80035d0: 2200 movs r2, #0
80035d2: 87da strh r2, [r3, #62] @ 0x3e
hspi->TxISR = NULL;
80035d4: 68fb ldr r3, [r7, #12]
80035d6: 2200 movs r2, #0
80035d8: 645a str r2, [r3, #68] @ 0x44
hspi->RxISR = NULL;
80035da: 68fb ldr r3, [r7, #12]
80035dc: 2200 movs r2, #0
80035de: 641a str r2, [r3, #64] @ 0x40
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
80035e0: 68fb ldr r3, [r7, #12]
80035e2: 689b ldr r3, [r3, #8]
80035e4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80035e8: d10f bne.n 800360a <HAL_SPI_Transmit+0xb8>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
80035ea: 68fb ldr r3, [r7, #12]
80035ec: 681b ldr r3, [r3, #0]
80035ee: 681a ldr r2, [r3, #0]
80035f0: 68fb ldr r3, [r7, #12]
80035f2: 681b ldr r3, [r3, #0]
80035f4: f022 0240 bic.w r2, r2, #64 @ 0x40
80035f8: 601a str r2, [r3, #0]
SPI_1LINE_TX(hspi);
80035fa: 68fb ldr r3, [r7, #12]
80035fc: 681b ldr r3, [r3, #0]
80035fe: 681a ldr r2, [r3, #0]
8003600: 68fb ldr r3, [r7, #12]
8003602: 681b ldr r3, [r3, #0]
8003604: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8003608: 601a str r2, [r3, #0]
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
800360a: 68fb ldr r3, [r7, #12]
800360c: 681b ldr r3, [r3, #0]
800360e: 681b ldr r3, [r3, #0]
8003610: f003 0340 and.w r3, r3, #64 @ 0x40
8003614: 2b40 cmp r3, #64 @ 0x40
8003616: d007 beq.n 8003628 <HAL_SPI_Transmit+0xd6>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8003618: 68fb ldr r3, [r7, #12]
800361a: 681b ldr r3, [r3, #0]
800361c: 681a ldr r2, [r3, #0]
800361e: 68fb ldr r3, [r7, #12]
8003620: 681b ldr r3, [r3, #0]
8003622: f042 0240 orr.w r2, r2, #64 @ 0x40
8003626: 601a str r2, [r3, #0]
}
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
8003628: 68fb ldr r3, [r7, #12]
800362a: 68db ldr r3, [r3, #12]
800362c: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003630: d152 bne.n 80036d8 <HAL_SPI_Transmit+0x186>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8003632: 68fb ldr r3, [r7, #12]
8003634: 685b ldr r3, [r3, #4]
8003636: 2b00 cmp r3, #0
8003638: d002 beq.n 8003640 <HAL_SPI_Transmit+0xee>
800363a: 8b7b ldrh r3, [r7, #26]
800363c: 2b01 cmp r3, #1
800363e: d145 bne.n 80036cc <HAL_SPI_Transmit+0x17a>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
8003640: 68fb ldr r3, [r7, #12]
8003642: 6b1b ldr r3, [r3, #48] @ 0x30
8003644: 881a ldrh r2, [r3, #0]
8003646: 68fb ldr r3, [r7, #12]
8003648: 681b ldr r3, [r3, #0]
800364a: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
800364c: 68fb ldr r3, [r7, #12]
800364e: 6b1b ldr r3, [r3, #48] @ 0x30
8003650: 1c9a adds r2, r3, #2
8003652: 68fb ldr r3, [r7, #12]
8003654: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
8003656: 68fb ldr r3, [r7, #12]
8003658: 8edb ldrh r3, [r3, #54] @ 0x36
800365a: b29b uxth r3, r3
800365c: 3b01 subs r3, #1
800365e: b29a uxth r2, r3
8003660: 68fb ldr r3, [r7, #12]
8003662: 86da strh r2, [r3, #54] @ 0x36
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
8003664: e032 b.n 80036cc <HAL_SPI_Transmit+0x17a>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
8003666: 68fb ldr r3, [r7, #12]
8003668: 681b ldr r3, [r3, #0]
800366a: 689b ldr r3, [r3, #8]
800366c: f003 0302 and.w r3, r3, #2
8003670: 2b02 cmp r3, #2
8003672: d112 bne.n 800369a <HAL_SPI_Transmit+0x148>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
8003674: 68fb ldr r3, [r7, #12]
8003676: 6b1b ldr r3, [r3, #48] @ 0x30
8003678: 881a ldrh r2, [r3, #0]
800367a: 68fb ldr r3, [r7, #12]
800367c: 681b ldr r3, [r3, #0]
800367e: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8003680: 68fb ldr r3, [r7, #12]
8003682: 6b1b ldr r3, [r3, #48] @ 0x30
8003684: 1c9a adds r2, r3, #2
8003686: 68fb ldr r3, [r7, #12]
8003688: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
800368a: 68fb ldr r3, [r7, #12]
800368c: 8edb ldrh r3, [r3, #54] @ 0x36
800368e: b29b uxth r3, r3
8003690: 3b01 subs r3, #1
8003692: b29a uxth r2, r3
8003694: 68fb ldr r3, [r7, #12]
8003696: 86da strh r2, [r3, #54] @ 0x36
8003698: e018 b.n 80036cc <HAL_SPI_Transmit+0x17a>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
800369a: f7fe fa1f bl 8001adc <HAL_GetTick>
800369e: 4602 mov r2, r0
80036a0: 69fb ldr r3, [r7, #28]
80036a2: 1ad3 subs r3, r2, r3
80036a4: 683a ldr r2, [r7, #0]
80036a6: 429a cmp r2, r3
80036a8: d803 bhi.n 80036b2 <HAL_SPI_Transmit+0x160>
80036aa: 683b ldr r3, [r7, #0]
80036ac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80036b0: d102 bne.n 80036b8 <HAL_SPI_Transmit+0x166>
80036b2: 683b ldr r3, [r7, #0]
80036b4: 2b00 cmp r3, #0
80036b6: d109 bne.n 80036cc <HAL_SPI_Transmit+0x17a>
{
hspi->State = HAL_SPI_STATE_READY;
80036b8: 68fb ldr r3, [r7, #12]
80036ba: 2201 movs r2, #1
80036bc: f883 2051 strb.w r2, [r3, #81] @ 0x51
__HAL_UNLOCK(hspi);
80036c0: 68fb ldr r3, [r7, #12]
80036c2: 2200 movs r2, #0
80036c4: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
80036c8: 2303 movs r3, #3
80036ca: e082 b.n 80037d2 <HAL_SPI_Transmit+0x280>
while (hspi->TxXferCount > 0U)
80036cc: 68fb ldr r3, [r7, #12]
80036ce: 8edb ldrh r3, [r3, #54] @ 0x36
80036d0: b29b uxth r3, r3
80036d2: 2b00 cmp r3, #0
80036d4: d1c7 bne.n 8003666 <HAL_SPI_Transmit+0x114>
80036d6: e053 b.n 8003780 <HAL_SPI_Transmit+0x22e>
}
}
/* Transmit data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
80036d8: 68fb ldr r3, [r7, #12]
80036da: 685b ldr r3, [r3, #4]
80036dc: 2b00 cmp r3, #0
80036de: d002 beq.n 80036e6 <HAL_SPI_Transmit+0x194>
80036e0: 8b7b ldrh r3, [r7, #26]
80036e2: 2b01 cmp r3, #1
80036e4: d147 bne.n 8003776 <HAL_SPI_Transmit+0x224>
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
80036e6: 68fb ldr r3, [r7, #12]
80036e8: 6b1a ldr r2, [r3, #48] @ 0x30
80036ea: 68fb ldr r3, [r7, #12]
80036ec: 681b ldr r3, [r3, #0]
80036ee: 330c adds r3, #12
80036f0: 7812 ldrb r2, [r2, #0]
80036f2: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
80036f4: 68fb ldr r3, [r7, #12]
80036f6: 6b1b ldr r3, [r3, #48] @ 0x30
80036f8: 1c5a adds r2, r3, #1
80036fa: 68fb ldr r3, [r7, #12]
80036fc: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
80036fe: 68fb ldr r3, [r7, #12]
8003700: 8edb ldrh r3, [r3, #54] @ 0x36
8003702: b29b uxth r3, r3
8003704: 3b01 subs r3, #1
8003706: b29a uxth r2, r3
8003708: 68fb ldr r3, [r7, #12]
800370a: 86da strh r2, [r3, #54] @ 0x36
}
while (hspi->TxXferCount > 0U)
800370c: e033 b.n 8003776 <HAL_SPI_Transmit+0x224>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
800370e: 68fb ldr r3, [r7, #12]
8003710: 681b ldr r3, [r3, #0]
8003712: 689b ldr r3, [r3, #8]
8003714: f003 0302 and.w r3, r3, #2
8003718: 2b02 cmp r3, #2
800371a: d113 bne.n 8003744 <HAL_SPI_Transmit+0x1f2>
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
800371c: 68fb ldr r3, [r7, #12]
800371e: 6b1a ldr r2, [r3, #48] @ 0x30
8003720: 68fb ldr r3, [r7, #12]
8003722: 681b ldr r3, [r3, #0]
8003724: 330c adds r3, #12
8003726: 7812 ldrb r2, [r2, #0]
8003728: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
800372a: 68fb ldr r3, [r7, #12]
800372c: 6b1b ldr r3, [r3, #48] @ 0x30
800372e: 1c5a adds r2, r3, #1
8003730: 68fb ldr r3, [r7, #12]
8003732: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
8003734: 68fb ldr r3, [r7, #12]
8003736: 8edb ldrh r3, [r3, #54] @ 0x36
8003738: b29b uxth r3, r3
800373a: 3b01 subs r3, #1
800373c: b29a uxth r2, r3
800373e: 68fb ldr r3, [r7, #12]
8003740: 86da strh r2, [r3, #54] @ 0x36
8003742: e018 b.n 8003776 <HAL_SPI_Transmit+0x224>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
8003744: f7fe f9ca bl 8001adc <HAL_GetTick>
8003748: 4602 mov r2, r0
800374a: 69fb ldr r3, [r7, #28]
800374c: 1ad3 subs r3, r2, r3
800374e: 683a ldr r2, [r7, #0]
8003750: 429a cmp r2, r3
8003752: d803 bhi.n 800375c <HAL_SPI_Transmit+0x20a>
8003754: 683b ldr r3, [r7, #0]
8003756: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800375a: d102 bne.n 8003762 <HAL_SPI_Transmit+0x210>
800375c: 683b ldr r3, [r7, #0]
800375e: 2b00 cmp r3, #0
8003760: d109 bne.n 8003776 <HAL_SPI_Transmit+0x224>
{
hspi->State = HAL_SPI_STATE_READY;
8003762: 68fb ldr r3, [r7, #12]
8003764: 2201 movs r2, #1
8003766: f883 2051 strb.w r2, [r3, #81] @ 0x51
__HAL_UNLOCK(hspi);
800376a: 68fb ldr r3, [r7, #12]
800376c: 2200 movs r2, #0
800376e: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
8003772: 2303 movs r3, #3
8003774: e02d b.n 80037d2 <HAL_SPI_Transmit+0x280>
while (hspi->TxXferCount > 0U)
8003776: 68fb ldr r3, [r7, #12]
8003778: 8edb ldrh r3, [r3, #54] @ 0x36
800377a: b29b uxth r3, r3
800377c: 2b00 cmp r3, #0
800377e: d1c6 bne.n 800370e <HAL_SPI_Transmit+0x1bc>
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
8003780: 69fa ldr r2, [r7, #28]
8003782: 6839 ldr r1, [r7, #0]
8003784: 68f8 ldr r0, [r7, #12]
8003786: f000 f8b1 bl 80038ec <SPI_EndRxTxTransaction>
800378a: 4603 mov r3, r0
800378c: 2b00 cmp r3, #0
800378e: d002 beq.n 8003796 <HAL_SPI_Transmit+0x244>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
8003790: 68fb ldr r3, [r7, #12]
8003792: 2220 movs r2, #32
8003794: 655a str r2, [r3, #84] @ 0x54
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
8003796: 68fb ldr r3, [r7, #12]
8003798: 689b ldr r3, [r3, #8]
800379a: 2b00 cmp r3, #0
800379c: d10a bne.n 80037b4 <HAL_SPI_Transmit+0x262>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
800379e: 2300 movs r3, #0
80037a0: 617b str r3, [r7, #20]
80037a2: 68fb ldr r3, [r7, #12]
80037a4: 681b ldr r3, [r3, #0]
80037a6: 68db ldr r3, [r3, #12]
80037a8: 617b str r3, [r7, #20]
80037aa: 68fb ldr r3, [r7, #12]
80037ac: 681b ldr r3, [r3, #0]
80037ae: 689b ldr r3, [r3, #8]
80037b0: 617b str r3, [r7, #20]
80037b2: 697b ldr r3, [r7, #20]
}
hspi->State = HAL_SPI_STATE_READY;
80037b4: 68fb ldr r3, [r7, #12]
80037b6: 2201 movs r2, #1
80037b8: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80037bc: 68fb ldr r3, [r7, #12]
80037be: 2200 movs r2, #0
80037c0: f883 2050 strb.w r2, [r3, #80] @ 0x50
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
80037c4: 68fb ldr r3, [r7, #12]
80037c6: 6d5b ldr r3, [r3, #84] @ 0x54
80037c8: 2b00 cmp r3, #0
80037ca: d001 beq.n 80037d0 <HAL_SPI_Transmit+0x27e>
{
return HAL_ERROR;
80037cc: 2301 movs r3, #1
80037ce: e000 b.n 80037d2 <HAL_SPI_Transmit+0x280>
}
else
{
return HAL_OK;
80037d0: 2300 movs r3, #0
}
}
80037d2: 4618 mov r0, r3
80037d4: 3720 adds r7, #32
80037d6: 46bd mov sp, r7
80037d8: bd80 pop {r7, pc}
...
080037dc <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
80037dc: b580 push {r7, lr}
80037de: b088 sub sp, #32
80037e0: af00 add r7, sp, #0
80037e2: 60f8 str r0, [r7, #12]
80037e4: 60b9 str r1, [r7, #8]
80037e6: 603b str r3, [r7, #0]
80037e8: 4613 mov r3, r2
80037ea: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
80037ec: f7fe f976 bl 8001adc <HAL_GetTick>
80037f0: 4602 mov r2, r0
80037f2: 6abb ldr r3, [r7, #40] @ 0x28
80037f4: 1a9b subs r3, r3, r2
80037f6: 683a ldr r2, [r7, #0]
80037f8: 4413 add r3, r2
80037fa: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
80037fc: f7fe f96e bl 8001adc <HAL_GetTick>
8003800: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
8003802: 4b39 ldr r3, [pc, #228] @ (80038e8 <SPI_WaitFlagStateUntilTimeout+0x10c>)
8003804: 681b ldr r3, [r3, #0]
8003806: 015b lsls r3, r3, #5
8003808: 0d1b lsrs r3, r3, #20
800380a: 69fa ldr r2, [r7, #28]
800380c: fb02 f303 mul.w r3, r2, r3
8003810: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8003812: e054 b.n 80038be <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
8003814: 683b ldr r3, [r7, #0]
8003816: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800381a: d050 beq.n 80038be <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
800381c: f7fe f95e bl 8001adc <HAL_GetTick>
8003820: 4602 mov r2, r0
8003822: 69bb ldr r3, [r7, #24]
8003824: 1ad3 subs r3, r2, r3
8003826: 69fa ldr r2, [r7, #28]
8003828: 429a cmp r2, r3
800382a: d902 bls.n 8003832 <SPI_WaitFlagStateUntilTimeout+0x56>
800382c: 69fb ldr r3, [r7, #28]
800382e: 2b00 cmp r3, #0
8003830: d13d bne.n 80038ae <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8003832: 68fb ldr r3, [r7, #12]
8003834: 681b ldr r3, [r3, #0]
8003836: 685a ldr r2, [r3, #4]
8003838: 68fb ldr r3, [r7, #12]
800383a: 681b ldr r3, [r3, #0]
800383c: f022 02e0 bic.w r2, r2, #224 @ 0xe0
8003840: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8003842: 68fb ldr r3, [r7, #12]
8003844: 685b ldr r3, [r3, #4]
8003846: f5b3 7f82 cmp.w r3, #260 @ 0x104
800384a: d111 bne.n 8003870 <SPI_WaitFlagStateUntilTimeout+0x94>
800384c: 68fb ldr r3, [r7, #12]
800384e: 689b ldr r3, [r3, #8]
8003850: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003854: d004 beq.n 8003860 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8003856: 68fb ldr r3, [r7, #12]
8003858: 689b ldr r3, [r3, #8]
800385a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800385e: d107 bne.n 8003870 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8003860: 68fb ldr r3, [r7, #12]
8003862: 681b ldr r3, [r3, #0]
8003864: 681a ldr r2, [r3, #0]
8003866: 68fb ldr r3, [r7, #12]
8003868: 681b ldr r3, [r3, #0]
800386a: f022 0240 bic.w r2, r2, #64 @ 0x40
800386e: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8003870: 68fb ldr r3, [r7, #12]
8003872: 6a9b ldr r3, [r3, #40] @ 0x28
8003874: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003878: d10f bne.n 800389a <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
800387a: 68fb ldr r3, [r7, #12]
800387c: 681b ldr r3, [r3, #0]
800387e: 681a ldr r2, [r3, #0]
8003880: 68fb ldr r3, [r7, #12]
8003882: 681b ldr r3, [r3, #0]
8003884: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8003888: 601a str r2, [r3, #0]
800388a: 68fb ldr r3, [r7, #12]
800388c: 681b ldr r3, [r3, #0]
800388e: 681a ldr r2, [r3, #0]
8003890: 68fb ldr r3, [r7, #12]
8003892: 681b ldr r3, [r3, #0]
8003894: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8003898: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
800389a: 68fb ldr r3, [r7, #12]
800389c: 2201 movs r2, #1
800389e: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80038a2: 68fb ldr r3, [r7, #12]
80038a4: 2200 movs r2, #0
80038a6: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
80038aa: 2303 movs r3, #3
80038ac: e017 b.n 80038de <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
80038ae: 697b ldr r3, [r7, #20]
80038b0: 2b00 cmp r3, #0
80038b2: d101 bne.n 80038b8 <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
80038b4: 2300 movs r3, #0
80038b6: 61fb str r3, [r7, #28]
}
count--;
80038b8: 697b ldr r3, [r7, #20]
80038ba: 3b01 subs r3, #1
80038bc: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
80038be: 68fb ldr r3, [r7, #12]
80038c0: 681b ldr r3, [r3, #0]
80038c2: 689a ldr r2, [r3, #8]
80038c4: 68bb ldr r3, [r7, #8]
80038c6: 4013 ands r3, r2
80038c8: 68ba ldr r2, [r7, #8]
80038ca: 429a cmp r2, r3
80038cc: bf0c ite eq
80038ce: 2301 moveq r3, #1
80038d0: 2300 movne r3, #0
80038d2: b2db uxtb r3, r3
80038d4: 461a mov r2, r3
80038d6: 79fb ldrb r3, [r7, #7]
80038d8: 429a cmp r2, r3
80038da: d19b bne.n 8003814 <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
80038dc: 2300 movs r3, #0
}
80038de: 4618 mov r0, r3
80038e0: 3720 adds r7, #32
80038e2: 46bd mov sp, r7
80038e4: bd80 pop {r7, pc}
80038e6: bf00 nop
80038e8: 20000000 .word 0x20000000
080038ec <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
80038ec: b580 push {r7, lr}
80038ee: b088 sub sp, #32
80038f0: af02 add r7, sp, #8
80038f2: 60f8 str r0, [r7, #12]
80038f4: 60b9 str r1, [r7, #8]
80038f6: 607a str r2, [r7, #4]
/* Wait until TXE flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK)
80038f8: 687b ldr r3, [r7, #4]
80038fa: 9300 str r3, [sp, #0]
80038fc: 68bb ldr r3, [r7, #8]
80038fe: 2201 movs r2, #1
8003900: 2102 movs r1, #2
8003902: 68f8 ldr r0, [r7, #12]
8003904: f7ff ff6a bl 80037dc <SPI_WaitFlagStateUntilTimeout>
8003908: 4603 mov r3, r0
800390a: 2b00 cmp r3, #0
800390c: d007 beq.n 800391e <SPI_EndRxTxTransaction+0x32>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800390e: 68fb ldr r3, [r7, #12]
8003910: 6d5b ldr r3, [r3, #84] @ 0x54
8003912: f043 0220 orr.w r2, r3, #32
8003916: 68fb ldr r3, [r7, #12]
8003918: 655a str r2, [r3, #84] @ 0x54
return HAL_TIMEOUT;
800391a: 2303 movs r3, #3
800391c: e032 b.n 8003984 <SPI_EndRxTxTransaction+0x98>
}
/* Timeout in us */
__IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
800391e: 4b1b ldr r3, [pc, #108] @ (800398c <SPI_EndRxTxTransaction+0xa0>)
8003920: 681b ldr r3, [r3, #0]
8003922: 4a1b ldr r2, [pc, #108] @ (8003990 <SPI_EndRxTxTransaction+0xa4>)
8003924: fba2 2303 umull r2, r3, r2, r3
8003928: 0d5b lsrs r3, r3, #21
800392a: f44f 727a mov.w r2, #1000 @ 0x3e8
800392e: fb02 f303 mul.w r3, r2, r3
8003932: 617b str r3, [r7, #20]
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
if (hspi->Init.Mode == SPI_MODE_MASTER)
8003934: 68fb ldr r3, [r7, #12]
8003936: 685b ldr r3, [r3, #4]
8003938: f5b3 7f82 cmp.w r3, #260 @ 0x104
800393c: d112 bne.n 8003964 <SPI_EndRxTxTransaction+0x78>
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
800393e: 687b ldr r3, [r7, #4]
8003940: 9300 str r3, [sp, #0]
8003942: 68bb ldr r3, [r7, #8]
8003944: 2200 movs r2, #0
8003946: 2180 movs r1, #128 @ 0x80
8003948: 68f8 ldr r0, [r7, #12]
800394a: f7ff ff47 bl 80037dc <SPI_WaitFlagStateUntilTimeout>
800394e: 4603 mov r3, r0
8003950: 2b00 cmp r3, #0
8003952: d016 beq.n 8003982 <SPI_EndRxTxTransaction+0x96>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8003954: 68fb ldr r3, [r7, #12]
8003956: 6d5b ldr r3, [r3, #84] @ 0x54
8003958: f043 0220 orr.w r2, r3, #32
800395c: 68fb ldr r3, [r7, #12]
800395e: 655a str r2, [r3, #84] @ 0x54
return HAL_TIMEOUT;
8003960: 2303 movs r3, #3
8003962: e00f b.n 8003984 <SPI_EndRxTxTransaction+0x98>
* User have to calculate the timeout value to fit with the time of 1 byte transfer.
* This time is directly link with the SPI clock from Master device.
*/
do
{
if (count == 0U)
8003964: 697b ldr r3, [r7, #20]
8003966: 2b00 cmp r3, #0
8003968: d00a beq.n 8003980 <SPI_EndRxTxTransaction+0x94>
{
break;
}
count--;
800396a: 697b ldr r3, [r7, #20]
800396c: 3b01 subs r3, #1
800396e: 617b str r3, [r7, #20]
} while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
8003970: 68fb ldr r3, [r7, #12]
8003972: 681b ldr r3, [r3, #0]
8003974: 689b ldr r3, [r3, #8]
8003976: f003 0380 and.w r3, r3, #128 @ 0x80
800397a: 2b80 cmp r3, #128 @ 0x80
800397c: d0f2 beq.n 8003964 <SPI_EndRxTxTransaction+0x78>
800397e: e000 b.n 8003982 <SPI_EndRxTxTransaction+0x96>
break;
8003980: bf00 nop
}
return HAL_OK;
8003982: 2300 movs r3, #0
}
8003984: 4618 mov r0, r3
8003986: 3718 adds r7, #24
8003988: 46bd mov sp, r7
800398a: bd80 pop {r7, pc}
800398c: 20000000 .word 0x20000000
8003990: 165e9f81 .word 0x165e9f81
08003994 <writecommand>:
* Input : command byte to write
* Output : None
* Return : None
*******************************************************************************/
void writecommand(unsigned char cmdout)
{
8003994: b580 push {r7, lr}
8003996: b082 sub sp, #8
8003998: af00 add r7, sp, #0
800399a: 4603 mov r3, r0
800399c: 71fb strb r3, [r7, #7]
//HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); // HAL_ERROR
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN << 16 ;// D/nC = 0 commande
800399e: 4b0a ldr r3, [pc, #40] @ (80039c8 <writecommand+0x34>)
80039a0: f44f 2280 mov.w r2, #262144 @ 0x40000
80039a4: 619a str r2, [r3, #24]
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0
80039a6: 4b08 ldr r3, [pc, #32] @ (80039c8 <writecommand+0x34>)
80039a8: f44f 3200 mov.w r2, #131072 @ 0x20000
80039ac: 619a str r2, [r3, #24]
HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); //
80039ae: 1df9 adds r1, r7, #7
80039b0: 2364 movs r3, #100 @ 0x64
80039b2: 2201 movs r2, #1
80039b4: 4805 ldr r0, [pc, #20] @ (80039cc <writecommand+0x38>)
80039b6: f7ff fdcc bl 8003552 <HAL_SPI_Transmit>
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
80039ba: 4b03 ldr r3, [pc, #12] @ (80039c8 <writecommand+0x34>)
80039bc: 2202 movs r2, #2
80039be: 619a str r2, [r3, #24]
}
80039c0: bf00 nop
80039c2: 3708 adds r7, #8
80039c4: 46bd mov sp, r7
80039c6: bd80 pop {r7, pc}
80039c8: 40020800 .word 0x40020800
80039cc: 2000007c .word 0x2000007c
080039d0 <writedata>:
* Input : data byte to write
* Output : None
* Return : None
*******************************************************************************/
void writedata(unsigned char dataout)
{
80039d0: b580 push {r7, lr}
80039d2: b082 sub sp, #8
80039d4: af00 add r7, sp, #0
80039d6: 4603 mov r3, r0
80039d8: 71fb strb r3, [r7, #7]
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
80039da: 4b0a ldr r3, [pc, #40] @ (8003a04 <writedata+0x34>)
80039dc: 2204 movs r2, #4
80039de: 619a str r2, [r3, #24]
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0
80039e0: 4b08 ldr r3, [pc, #32] @ (8003a04 <writedata+0x34>)
80039e2: f44f 3200 mov.w r2, #131072 @ 0x20000
80039e6: 619a str r2, [r3, #24]
HAL_SPI_Transmit(&hspi1, &dataout, 1, 100); //
80039e8: 1df9 adds r1, r7, #7
80039ea: 2364 movs r3, #100 @ 0x64
80039ec: 2201 movs r2, #1
80039ee: 4806 ldr r0, [pc, #24] @ (8003a08 <writedata+0x38>)
80039f0: f7ff fdaf bl 8003552 <HAL_SPI_Transmit>
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
80039f4: 4b03 ldr r3, [pc, #12] @ (8003a04 <writedata+0x34>)
80039f6: 2202 movs r2, #2
80039f8: 619a str r2, [r3, #24]
}
80039fa: bf00 nop
80039fc: 3708 adds r7, #8
80039fe: 46bd mov sp, r7
8003a00: bd80 pop {r7, pc}
8003a02: bf00 nop
8003a04: 40020800 .word 0x40020800
8003a08: 2000007c .word 0x2000007c
08003a0c <commandList>:
* Input : addr = pointer on command byte array
* Output : None
* Return : None
*******************************************************************************/
void commandList(const uint8_t *addr)
{
8003a0c: b580 push {r7, lr}
8003a0e: b084 sub sp, #16
8003a10: af00 add r7, sp, #0
8003a12: 6078 str r0, [r7, #4]
uint8_t numCommands, numArgs;
uint16_t ms;
numCommands = pgm_read_byte(addr++); // Number of commands to follow
8003a14: 687b ldr r3, [r7, #4]
8003a16: 1c5a adds r2, r3, #1
8003a18: 607a str r2, [r7, #4]
8003a1a: 781b ldrb r3, [r3, #0]
8003a1c: 73fb strb r3, [r7, #15]
while(numCommands--)
8003a1e: e033 b.n 8003a88 <commandList+0x7c>
{ // For each command...
writecommand(pgm_read_byte(addr++)); // Read, issue command
8003a20: 687b ldr r3, [r7, #4]
8003a22: 1c5a adds r2, r3, #1
8003a24: 607a str r2, [r7, #4]
8003a26: 781b ldrb r3, [r3, #0]
8003a28: 4618 mov r0, r3
8003a2a: f7ff ffb3 bl 8003994 <writecommand>
numArgs = pgm_read_byte(addr++); // Number of args to follow
8003a2e: 687b ldr r3, [r7, #4]
8003a30: 1c5a adds r2, r3, #1
8003a32: 607a str r2, [r7, #4]
8003a34: 781b ldrb r3, [r3, #0]
8003a36: 73bb strb r3, [r7, #14]
ms = numArgs & DELAY; // If hibit set, delay follows args
8003a38: 7bbb ldrb r3, [r7, #14]
8003a3a: b29b uxth r3, r3
8003a3c: f003 0380 and.w r3, r3, #128 @ 0x80
8003a40: 81bb strh r3, [r7, #12]
numArgs &= ~DELAY; // Mask out delay bit
8003a42: 7bbb ldrb r3, [r7, #14]
8003a44: f003 037f and.w r3, r3, #127 @ 0x7f
8003a48: 73bb strb r3, [r7, #14]
while(numArgs--) { // For each argument...
8003a4a: e006 b.n 8003a5a <commandList+0x4e>
writedata(pgm_read_byte(addr++)); // Read, issue argument
8003a4c: 687b ldr r3, [r7, #4]
8003a4e: 1c5a adds r2, r3, #1
8003a50: 607a str r2, [r7, #4]
8003a52: 781b ldrb r3, [r3, #0]
8003a54: 4618 mov r0, r3
8003a56: f7ff ffbb bl 80039d0 <writedata>
while(numArgs--) { // For each argument...
8003a5a: 7bbb ldrb r3, [r7, #14]
8003a5c: 1e5a subs r2, r3, #1
8003a5e: 73ba strb r2, [r7, #14]
8003a60: 2b00 cmp r3, #0
8003a62: d1f3 bne.n 8003a4c <commandList+0x40>
}
if(ms) {
8003a64: 89bb ldrh r3, [r7, #12]
8003a66: 2b00 cmp r3, #0
8003a68: d00e beq.n 8003a88 <commandList+0x7c>
ms = pgm_read_byte(addr++); // Read post-command delay time (ms)
8003a6a: 687b ldr r3, [r7, #4]
8003a6c: 1c5a adds r2, r3, #1
8003a6e: 607a str r2, [r7, #4]
8003a70: 781b ldrb r3, [r3, #0]
8003a72: 81bb strh r3, [r7, #12]
if(ms == 255) ms = 500; // If 255, delay for 500 ms
8003a74: 89bb ldrh r3, [r7, #12]
8003a76: 2bff cmp r3, #255 @ 0xff
8003a78: d102 bne.n 8003a80 <commandList+0x74>
8003a7a: f44f 73fa mov.w r3, #500 @ 0x1f4
8003a7e: 81bb strh r3, [r7, #12]
HAL_Delay(500);
8003a80: f44f 70fa mov.w r0, #500 @ 0x1f4
8003a84: f7fe f834 bl 8001af0 <HAL_Delay>
while(numCommands--)
8003a88: 7bfb ldrb r3, [r7, #15]
8003a8a: 1e5a subs r2, r3, #1
8003a8c: 73fa strb r2, [r7, #15]
8003a8e: 2b00 cmp r3, #0
8003a90: d1c6 bne.n 8003a20 <commandList+0x14>
}
}
}
8003a92: bf00 nop
8003a94: bf00 nop
8003a96: 3710 adds r7, #16
8003a98: 46bd mov sp, r7
8003a9a: bd80 pop {r7, pc}
08003a9c <setAddrWindow>:
* : y2 vertical position = y1 to ST7735_TFTHEIGHT-1-y1
* Output : None
* Return : None
*******************************************************************************/
void setAddrWindow(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1)
{
8003a9c: b590 push {r4, r7, lr}
8003a9e: b083 sub sp, #12
8003aa0: af00 add r7, sp, #0
8003aa2: 4604 mov r4, r0
8003aa4: 4608 mov r0, r1
8003aa6: 4611 mov r1, r2
8003aa8: 461a mov r2, r3
8003aaa: 4623 mov r3, r4
8003aac: 71fb strb r3, [r7, #7]
8003aae: 4603 mov r3, r0
8003ab0: 71bb strb r3, [r7, #6]
8003ab2: 460b mov r3, r1
8003ab4: 717b strb r3, [r7, #5]
8003ab6: 4613 mov r3, r2
8003ab8: 713b strb r3, [r7, #4]
writecommand(ST7735_CASET); // Column addr set
8003aba: 202a movs r0, #42 @ 0x2a
8003abc: f7ff ff6a bl 8003994 <writecommand>
writedata(0x00);
8003ac0: 2000 movs r0, #0
8003ac2: f7ff ff85 bl 80039d0 <writedata>
writedata(x0); // XSTART
8003ac6: 79fb ldrb r3, [r7, #7]
8003ac8: 4618 mov r0, r3
8003aca: f7ff ff81 bl 80039d0 <writedata>
writedata(0x00);
8003ace: 2000 movs r0, #0
8003ad0: f7ff ff7e bl 80039d0 <writedata>
writedata(x1); // XEND
8003ad4: 797b ldrb r3, [r7, #5]
8003ad6: 4618 mov r0, r3
8003ad8: f7ff ff7a bl 80039d0 <writedata>
writecommand(ST7735_RASET); // Row addr set
8003adc: 202b movs r0, #43 @ 0x2b
8003ade: f7ff ff59 bl 8003994 <writecommand>
writedata(0x00);
8003ae2: 2000 movs r0, #0
8003ae4: f7ff ff74 bl 80039d0 <writedata>
writedata(y0); // YSTART
8003ae8: 79bb ldrb r3, [r7, #6]
8003aea: 4618 mov r0, r3
8003aec: f7ff ff70 bl 80039d0 <writedata>
writedata(0x00);
8003af0: 2000 movs r0, #0
8003af2: f7ff ff6d bl 80039d0 <writedata>
writedata(y1); // YEND
8003af6: 793b ldrb r3, [r7, #4]
8003af8: 4618 mov r0, r3
8003afa: f7ff ff69 bl 80039d0 <writedata>
writecommand(ST7735_RAMWR); // write to RAM
8003afe: 202c movs r0, #44 @ 0x2c
8003b00: f7ff ff48 bl 8003994 <writecommand>
}
8003b04: bf00 nop
8003b06: 370c adds r7, #12
8003b08: 46bd mov sp, r7
8003b0a: bd90 pop {r4, r7, pc}
08003b0c <init_TFT>:
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void init_TFT( void)
{
8003b0c: b580 push {r7, lr}
8003b0e: b082 sub sp, #8
8003b10: af02 add r7, sp, #8
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, 1); // nRESET = 1
attend_500ms();
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // DC= 1
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
8003b12: 4b1e ldr r3, [pc, #120] @ (8003b8c <init_TFT+0x80>)
8003b14: 2204 movs r2, #4
8003b16: 619a str r2, [r3, #24]
ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1
8003b18: 4b1d ldr r3, [pc, #116] @ (8003b90 <init_TFT+0x84>)
8003b1a: 2204 movs r2, #4
8003b1c: 619a str r2, [r3, #24]
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0
8003b1e: 4b1b ldr r3, [pc, #108] @ (8003b8c <init_TFT+0x80>)
8003b20: f44f 3200 mov.w r2, #131072 @ 0x20000
8003b24: 619a str r2, [r3, #24]
HAL_Delay(500);
8003b26: f44f 70fa mov.w r0, #500 @ 0x1f4
8003b2a: f7fd ffe1 bl 8001af0 <HAL_Delay>
ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN<<16;// nRESET = 0
8003b2e: 4b18 ldr r3, [pc, #96] @ (8003b90 <init_TFT+0x84>)
8003b30: f44f 2280 mov.w r2, #262144 @ 0x40000
8003b34: 619a str r2, [r3, #24]
HAL_Delay(500);
8003b36: f44f 70fa mov.w r0, #500 @ 0x1f4
8003b3a: f7fd ffd9 bl 8001af0 <HAL_Delay>
ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1
8003b3e: 4b14 ldr r3, [pc, #80] @ (8003b90 <init_TFT+0x84>)
8003b40: 2204 movs r2, #4
8003b42: 619a str r2, [r3, #24]
HAL_Delay(500);
8003b44: f44f 70fa mov.w r0, #500 @ 0x1f4
8003b48: f7fd ffd2 bl 8001af0 <HAL_Delay>
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
8003b4c: 4b0f ldr r3, [pc, #60] @ (8003b8c <init_TFT+0x80>)
8003b4e: 2202 movs r2, #2
8003b50: 619a str r2, [r3, #24]
// initialization instruction
commandList(Rcmd1);
8003b52: 4810 ldr r0, [pc, #64] @ (8003b94 <init_TFT+0x88>)
8003b54: f7ff ff5a bl 8003a0c <commandList>
commandList(Rcmd2red);
8003b58: 480f ldr r0, [pc, #60] @ (8003b98 <init_TFT+0x8c>)
8003b5a: f7ff ff57 bl 8003a0c <commandList>
commandList(Rcmd3);
8003b5e: 480f ldr r0, [pc, #60] @ (8003b9c <init_TFT+0x90>)
8003b60: f7ff ff54 bl 8003a0c <commandList>
writecommand(ST7735_MADCTL);
8003b64: 2036 movs r0, #54 @ 0x36
8003b66: f7ff ff15 bl 8003994 <writecommand>
writedata(0xC0);
8003b6a: 20c0 movs r0, #192 @ 0xc0
8003b6c: f7ff ff30 bl 80039d0 <writedata>
// all display background is black
fillRect_TFT(0, 0, ST7735_TFTWIDTH, ST7735_TFTHEIGHT_18, ST7735_BLACK);
8003b70: 2300 movs r3, #0
8003b72: 9300 str r3, [sp, #0]
8003b74: 23a0 movs r3, #160 @ 0xa0
8003b76: 2280 movs r2, #128 @ 0x80
8003b78: 2100 movs r1, #0
8003b7a: 2000 movs r0, #0
8003b7c: f000 f856 bl 8003c2c <fillRect_TFT>
// display LOGO
displayLogo_TFT();
8003b80: f000 f998 bl 8003eb4 <displayLogo_TFT>
}
8003b84: bf00 nop
8003b86: 46bd mov sp, r7
8003b88: bd80 pop {r7, pc}
8003b8a: bf00 nop
8003b8c: 40020800 .word 0x40020800
8003b90: 40020c00 .word 0x40020c00
8003b94: 080040a8 .word 0x080040a8
8003b98: 080040e4 .word 0x080040e4
8003b9c: 080040f4 .word 0x080040f4
08003ba0 <drawPixel_TFT>:
* : color = 16bits RGB=(565) soit RRRRRGGGGGGGBBBBB
* Output : None
* Return : None
*******************************************************************************/
void drawPixel_TFT(uint16_t x, uint16_t y, uint16_t color)
{
8003ba0: b580 push {r7, lr}
8003ba2: b084 sub sp, #16
8003ba4: af00 add r7, sp, #0
8003ba6: 4603 mov r3, r0
8003ba8: 80fb strh r3, [r7, #6]
8003baa: 460b mov r3, r1
8003bac: 80bb strh r3, [r7, #4]
8003bae: 4613 mov r3, r2
8003bb0: 807b strh r3, [r7, #2]
uint8_t hi, lo;
// rudimentary clipping (drawChar w/big text requires this)
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
8003bb2: 88fb ldrh r3, [r7, #6]
8003bb4: 2b7f cmp r3, #127 @ 0x7f
8003bb6: d831 bhi.n 8003c1c <drawPixel_TFT+0x7c>
8003bb8: 88bb ldrh r3, [r7, #4]
8003bba: 2b9f cmp r3, #159 @ 0x9f
8003bbc: d82e bhi.n 8003c1c <drawPixel_TFT+0x7c>
setAddrWindow(x, y, x+1, y+1);
8003bbe: 88fb ldrh r3, [r7, #6]
8003bc0: b2d8 uxtb r0, r3
8003bc2: 88bb ldrh r3, [r7, #4]
8003bc4: b2d9 uxtb r1, r3
8003bc6: 88fb ldrh r3, [r7, #6]
8003bc8: b2db uxtb r3, r3
8003bca: 3301 adds r3, #1
8003bcc: b2da uxtb r2, r3
8003bce: 88bb ldrh r3, [r7, #4]
8003bd0: b2db uxtb r3, r3
8003bd2: 3301 adds r3, #1
8003bd4: b2db uxtb r3, r3
8003bd6: f7ff ff61 bl 8003a9c <setAddrWindow>
hi = color >> 8;
8003bda: 887b ldrh r3, [r7, #2]
8003bdc: 0a1b lsrs r3, r3, #8
8003bde: b29b uxth r3, r3
8003be0: b2db uxtb r3, r3
8003be2: 73fb strb r3, [r7, #15]
lo = color ;
8003be4: 887b ldrh r3, [r7, #2]
8003be6: b2db uxtb r3, r3
8003be8: 73bb strb r3, [r7, #14]
HAL_SPI_Transmit(&hspi1, &lo, 1, 100); //
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
8003bea: 4b0e ldr r3, [pc, #56] @ (8003c24 <drawPixel_TFT+0x84>)
8003bec: 2204 movs r2, #4
8003bee: 619a str r2, [r3, #24]
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0
8003bf0: 4b0c ldr r3, [pc, #48] @ (8003c24 <drawPixel_TFT+0x84>)
8003bf2: f44f 3200 mov.w r2, #131072 @ 0x20000
8003bf6: 619a str r2, [r3, #24]
HAL_SPI_Transmit(&hspi1, &hi, 1, 100); //
8003bf8: f107 010f add.w r1, r7, #15
8003bfc: 2364 movs r3, #100 @ 0x64
8003bfe: 2201 movs r2, #1
8003c00: 4809 ldr r0, [pc, #36] @ (8003c28 <drawPixel_TFT+0x88>)
8003c02: f7ff fca6 bl 8003552 <HAL_SPI_Transmit>
HAL_SPI_Transmit(&hspi1, &lo, 1, 100); //
8003c06: f107 010e add.w r1, r7, #14
8003c0a: 2364 movs r3, #100 @ 0x64
8003c0c: 2201 movs r2, #1
8003c0e: 4806 ldr r0, [pc, #24] @ (8003c28 <drawPixel_TFT+0x88>)
8003c10: f7ff fc9f bl 8003552 <HAL_SPI_Transmit>
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
8003c14: 4b03 ldr r3, [pc, #12] @ (8003c24 <drawPixel_TFT+0x84>)
8003c16: 2202 movs r2, #2
8003c18: 619a str r2, [r3, #24]
8003c1a: e000 b.n 8003c1e <drawPixel_TFT+0x7e>
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
8003c1c: bf00 nop
}
8003c1e: 3710 adds r7, #16
8003c20: 46bd mov sp, r7
8003c22: bd80 pop {r7, pc}
8003c24: 40020800 .word 0x40020800
8003c28: 2000007c .word 0x2000007c
08003c2c <fillRect_TFT>:
* : color = 16bits RGB(565) soit RRRRRGGGGGGGBBBBB
* Output : None
* Return : None
*******************************************************************************/
void fillRect_TFT(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color)
{
8003c2c: b590 push {r4, r7, lr}
8003c2e: b085 sub sp, #20
8003c30: af00 add r7, sp, #0
8003c32: 4604 mov r4, r0
8003c34: 4608 mov r0, r1
8003c36: 4611 mov r1, r2
8003c38: 461a mov r2, r3
8003c3a: 4623 mov r3, r4
8003c3c: 80fb strh r3, [r7, #6]
8003c3e: 4603 mov r3, r0
8003c40: 80bb strh r3, [r7, #4]
8003c42: 460b mov r3, r1
8003c44: 807b strh r3, [r7, #2]
8003c46: 4613 mov r3, r2
8003c48: 803b strh r3, [r7, #0]
uint8_t hi, lo;
// rudimentary clipping (drawChar w/big text requires this)
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
8003c4a: 88fb ldrh r3, [r7, #6]
8003c4c: 2b7f cmp r3, #127 @ 0x7f
8003c4e: d85e bhi.n 8003d0e <fillRect_TFT+0xe2>
8003c50: 88bb ldrh r3, [r7, #4]
8003c52: 2b9f cmp r3, #159 @ 0x9f
8003c54: d85b bhi.n 8003d0e <fillRect_TFT+0xe2>
if((x + w - 1) >= ST7735_TFTWIDTH) w = ST7735_TFTWIDTH - x;
8003c56: 88fa ldrh r2, [r7, #6]
8003c58: 887b ldrh r3, [r7, #2]
8003c5a: 4413 add r3, r2
8003c5c: 2b80 cmp r3, #128 @ 0x80
8003c5e: dd03 ble.n 8003c68 <fillRect_TFT+0x3c>
8003c60: 88fb ldrh r3, [r7, #6]
8003c62: f1c3 0380 rsb r3, r3, #128 @ 0x80
8003c66: 807b strh r3, [r7, #2]
if((y + h - 1) >= ST7735_TFTHEIGHT_18) h = ST7735_TFTHEIGHT_18 - y;
8003c68: 88ba ldrh r2, [r7, #4]
8003c6a: 883b ldrh r3, [r7, #0]
8003c6c: 4413 add r3, r2
8003c6e: 2ba0 cmp r3, #160 @ 0xa0
8003c70: dd03 ble.n 8003c7a <fillRect_TFT+0x4e>
8003c72: 88bb ldrh r3, [r7, #4]
8003c74: f1c3 03a0 rsb r3, r3, #160 @ 0xa0
8003c78: 803b strh r3, [r7, #0]
// select window
setAddrWindow(x, y, x+w-1, y+h-1);
8003c7a: 88fb ldrh r3, [r7, #6]
8003c7c: b2d8 uxtb r0, r3
8003c7e: 88bb ldrh r3, [r7, #4]
8003c80: b2d9 uxtb r1, r3
8003c82: 88fb ldrh r3, [r7, #6]
8003c84: b2da uxtb r2, r3
8003c86: 887b ldrh r3, [r7, #2]
8003c88: b2db uxtb r3, r3
8003c8a: 4413 add r3, r2
8003c8c: b2db uxtb r3, r3
8003c8e: 3b01 subs r3, #1
8003c90: b2dc uxtb r4, r3
8003c92: 88bb ldrh r3, [r7, #4]
8003c94: b2da uxtb r2, r3
8003c96: 883b ldrh r3, [r7, #0]
8003c98: b2db uxtb r3, r3
8003c9a: 4413 add r3, r2
8003c9c: b2db uxtb r3, r3
8003c9e: 3b01 subs r3, #1
8003ca0: b2db uxtb r3, r3
8003ca2: 4622 mov r2, r4
8003ca4: f7ff fefa bl 8003a9c <setAddrWindow>
hi = color >> 8;
8003ca8: 8c3b ldrh r3, [r7, #32]
8003caa: 0a1b lsrs r3, r3, #8
8003cac: b29b uxth r3, r3
8003cae: b2db uxtb r3, r3
8003cb0: 73fb strb r3, [r7, #15]
lo = color ;
8003cb2: 8c3b ldrh r3, [r7, #32]
8003cb4: b2db uxtb r3, r3
8003cb6: 73bb strb r3, [r7, #14]
*/
/*HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // D/nC = 1 data
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0*/
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
8003cb8: 4b17 ldr r3, [pc, #92] @ (8003d18 <fillRect_TFT+0xec>)
8003cba: 2204 movs r2, #4
8003cbc: 619a str r2, [r3, #24]
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0
8003cbe: 4b16 ldr r3, [pc, #88] @ (8003d18 <fillRect_TFT+0xec>)
8003cc0: f44f 3200 mov.w r2, #131072 @ 0x20000
8003cc4: 619a str r2, [r3, #24]
for(y=h; y>0; y--)
8003cc6: 883b ldrh r3, [r7, #0]
8003cc8: 80bb strh r3, [r7, #4]
8003cca: e019 b.n 8003d00 <fillRect_TFT+0xd4>
{
for(x=w; x>0; x--)
8003ccc: 887b ldrh r3, [r7, #2]
8003cce: 80fb strh r3, [r7, #6]
8003cd0: e010 b.n 8003cf4 <fillRect_TFT+0xc8>
{
HAL_SPI_Transmit(&hspi1, &hi, 1, 100); //
8003cd2: f107 010f add.w r1, r7, #15
8003cd6: 2364 movs r3, #100 @ 0x64
8003cd8: 2201 movs r2, #1
8003cda: 4810 ldr r0, [pc, #64] @ (8003d1c <fillRect_TFT+0xf0>)
8003cdc: f7ff fc39 bl 8003552 <HAL_SPI_Transmit>
HAL_SPI_Transmit(&hspi1, &lo, 1, 100); //
8003ce0: f107 010e add.w r1, r7, #14
8003ce4: 2364 movs r3, #100 @ 0x64
8003ce6: 2201 movs r2, #1
8003ce8: 480c ldr r0, [pc, #48] @ (8003d1c <fillRect_TFT+0xf0>)
8003cea: f7ff fc32 bl 8003552 <HAL_SPI_Transmit>
for(x=w; x>0; x--)
8003cee: 88fb ldrh r3, [r7, #6]
8003cf0: 3b01 subs r3, #1
8003cf2: 80fb strh r3, [r7, #6]
8003cf4: 88fb ldrh r3, [r7, #6]
8003cf6: 2b00 cmp r3, #0
8003cf8: d1eb bne.n 8003cd2 <fillRect_TFT+0xa6>
for(y=h; y>0; y--)
8003cfa: 88bb ldrh r3, [r7, #4]
8003cfc: 3b01 subs r3, #1
8003cfe: 80bb strh r3, [r7, #4]
8003d00: 88bb ldrh r3, [r7, #4]
8003d02: 2b00 cmp r3, #0
8003d04: d1e2 bne.n 8003ccc <fillRect_TFT+0xa0>
}
}
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
8003d06: 4b04 ldr r3, [pc, #16] @ (8003d18 <fillRect_TFT+0xec>)
8003d08: 2202 movs r2, #2
8003d0a: 619a str r2, [r3, #24]
8003d0c: e000 b.n 8003d10 <fillRect_TFT+0xe4>
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
8003d0e: bf00 nop
}
8003d10: 3714 adds r7, #20
8003d12: 46bd mov sp, r7
8003d14: bd90 pop {r4, r7, pc}
8003d16: bf00 nop
8003d18: 40020800 .word 0x40020800
8003d1c: 2000007c .word 0x2000007c
08003d20 <displayChar_TFT>:
* : size = 1 to 10
* Output : None
* Return : None
*******************************************************************************/
void displayChar_TFT(uint16_t x, uint16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size)
{
8003d20: b590 push {r4, r7, lr}
8003d22: b087 sub sp, #28
8003d24: af02 add r7, sp, #8
8003d26: 4604 mov r4, r0
8003d28: 4608 mov r0, r1
8003d2a: 4611 mov r1, r2
8003d2c: 461a mov r2, r3
8003d2e: 4623 mov r3, r4
8003d30: 80fb strh r3, [r7, #6]
8003d32: 4603 mov r3, r0
8003d34: 80bb strh r3, [r7, #4]
8003d36: 460b mov r3, r1
8003d38: 70fb strb r3, [r7, #3]
8003d3a: 4613 mov r3, r2
8003d3c: 803b strh r3, [r7, #0]
uint8_t i,j,line;
if((x >= ST7735_TFTWIDTH) || // Clip right
8003d3e: 88fb ldrh r3, [r7, #6]
8003d40: 2b7f cmp r3, #127 @ 0x7f
8003d42: f200 80b1 bhi.w 8003ea8 <displayChar_TFT+0x188>
8003d46: 88bb ldrh r3, [r7, #4]
8003d48: 2b9f cmp r3, #159 @ 0x9f
8003d4a: f200 80ad bhi.w 8003ea8 <displayChar_TFT+0x188>
(y >= ST7735_TFTHEIGHT_18) || // Clip bottom
((x + 6 * size - 1) < 0) || // Clip left
8003d4e: 88f9 ldrh r1, [r7, #6]
8003d50: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
8003d54: 4613 mov r3, r2
8003d56: 005b lsls r3, r3, #1
8003d58: 4413 add r3, r2
8003d5a: 005b lsls r3, r3, #1
8003d5c: 440b add r3, r1
(y >= ST7735_TFTHEIGHT_18) || // Clip bottom
8003d5e: 2b00 cmp r3, #0
8003d60: f340 80a2 ble.w 8003ea8 <displayChar_TFT+0x188>
((y + 8 * size - 1) < 0)) // Clip top
8003d64: 88ba ldrh r2, [r7, #4]
8003d66: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003d6a: 00db lsls r3, r3, #3
8003d6c: 4413 add r3, r2
((x + 6 * size - 1) < 0) || // Clip left
8003d6e: 2b00 cmp r3, #0
8003d70: f340 809a ble.w 8003ea8 <displayChar_TFT+0x188>
return;
for (i=0; i<6; i++ )
8003d74: 2300 movs r3, #0
8003d76: 73fb strb r3, [r7, #15]
8003d78: e091 b.n 8003e9e <displayChar_TFT+0x17e>
{
if (i == 5)
8003d7a: 7bfb ldrb r3, [r7, #15]
8003d7c: 2b05 cmp r3, #5
8003d7e: d102 bne.n 8003d86 <displayChar_TFT+0x66>
line = 0x0;
8003d80: 2300 movs r3, #0
8003d82: 737b strb r3, [r7, #13]
8003d84: e00a b.n 8003d9c <displayChar_TFT+0x7c>
else
line = pgm_read_byte(tab_font + (c*5) + i);
8003d86: 78fa ldrb r2, [r7, #3]
8003d88: 4613 mov r3, r2
8003d8a: 009b lsls r3, r3, #2
8003d8c: 4413 add r3, r2
8003d8e: 461a mov r2, r3
8003d90: 7bfb ldrb r3, [r7, #15]
8003d92: 4413 add r3, r2
8003d94: 4a46 ldr r2, [pc, #280] @ (8003eb0 <displayChar_TFT+0x190>)
8003d96: 4413 add r3, r2
8003d98: 781b ldrb r3, [r3, #0]
8003d9a: 737b strb r3, [r7, #13]
for ( j = 0; j<8; j++)
8003d9c: 2300 movs r3, #0
8003d9e: 73bb strb r3, [r7, #14]
8003da0: e077 b.n 8003e92 <displayChar_TFT+0x172>
{
if (line & 0x1)
8003da2: 7b7b ldrb r3, [r7, #13]
8003da4: f003 0301 and.w r3, r3, #1
8003da8: 2b00 cmp r3, #0
8003daa: d034 beq.n 8003e16 <displayChar_TFT+0xf6>
{
if (size == 1) // default size
8003dac: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003db0: 2b01 cmp r3, #1
8003db2: d10e bne.n 8003dd2 <displayChar_TFT+0xb2>
drawPixel_TFT(x+i, y+j, color);
8003db4: 7bfb ldrb r3, [r7, #15]
8003db6: b29a uxth r2, r3
8003db8: 88fb ldrh r3, [r7, #6]
8003dba: 4413 add r3, r2
8003dbc: b298 uxth r0, r3
8003dbe: 7bbb ldrb r3, [r7, #14]
8003dc0: b29a uxth r2, r3
8003dc2: 88bb ldrh r3, [r7, #4]
8003dc4: 4413 add r3, r2
8003dc6: b29b uxth r3, r3
8003dc8: 883a ldrh r2, [r7, #0]
8003dca: 4619 mov r1, r3
8003dcc: f7ff fee8 bl 8003ba0 <drawPixel_TFT>
8003dd0: e059 b.n 8003e86 <displayChar_TFT+0x166>
else
{ // big size
fillRect_TFT(x+(i*size), y+(j*size), size, size, color);
8003dd2: 7bfb ldrb r3, [r7, #15]
8003dd4: b29b uxth r3, r3
8003dd6: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
8003dda: b292 uxth r2, r2
8003ddc: fb02 f303 mul.w r3, r2, r3
8003de0: b29a uxth r2, r3
8003de2: 88fb ldrh r3, [r7, #6]
8003de4: 4413 add r3, r2
8003de6: b298 uxth r0, r3
8003de8: 7bbb ldrb r3, [r7, #14]
8003dea: b29b uxth r3, r3
8003dec: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
8003df0: b292 uxth r2, r2
8003df2: fb02 f303 mul.w r3, r2, r3
8003df6: b29a uxth r2, r3
8003df8: 88bb ldrh r3, [r7, #4]
8003dfa: 4413 add r3, r2
8003dfc: b299 uxth r1, r3
8003dfe: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003e02: b29a uxth r2, r3
8003e04: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003e08: b29c uxth r4, r3
8003e0a: 883b ldrh r3, [r7, #0]
8003e0c: 9300 str r3, [sp, #0]
8003e0e: 4623 mov r3, r4
8003e10: f7ff ff0c bl 8003c2c <fillRect_TFT>
8003e14: e037 b.n 8003e86 <displayChar_TFT+0x166>
}
}
else if (bg != color)
8003e16: 8c3a ldrh r2, [r7, #32]
8003e18: 883b ldrh r3, [r7, #0]
8003e1a: 429a cmp r2, r3
8003e1c: d033 beq.n 8003e86 <displayChar_TFT+0x166>
{
if (size == 1) // default size
8003e1e: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003e22: 2b01 cmp r3, #1
8003e24: d10e bne.n 8003e44 <displayChar_TFT+0x124>
drawPixel_TFT(x+i, y+j, bg);
8003e26: 7bfb ldrb r3, [r7, #15]
8003e28: b29a uxth r2, r3
8003e2a: 88fb ldrh r3, [r7, #6]
8003e2c: 4413 add r3, r2
8003e2e: b298 uxth r0, r3
8003e30: 7bbb ldrb r3, [r7, #14]
8003e32: b29a uxth r2, r3
8003e34: 88bb ldrh r3, [r7, #4]
8003e36: 4413 add r3, r2
8003e38: b29b uxth r3, r3
8003e3a: 8c3a ldrh r2, [r7, #32]
8003e3c: 4619 mov r1, r3
8003e3e: f7ff feaf bl 8003ba0 <drawPixel_TFT>
8003e42: e020 b.n 8003e86 <displayChar_TFT+0x166>
else
{ // big size
fillRect_TFT(x+i*size, y+j*size, size, size, bg);
8003e44: 7bfb ldrb r3, [r7, #15]
8003e46: b29b uxth r3, r3
8003e48: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
8003e4c: b292 uxth r2, r2
8003e4e: fb02 f303 mul.w r3, r2, r3
8003e52: b29a uxth r2, r3
8003e54: 88fb ldrh r3, [r7, #6]
8003e56: 4413 add r3, r2
8003e58: b298 uxth r0, r3
8003e5a: 7bbb ldrb r3, [r7, #14]
8003e5c: b29b uxth r3, r3
8003e5e: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
8003e62: b292 uxth r2, r2
8003e64: fb02 f303 mul.w r3, r2, r3
8003e68: b29a uxth r2, r3
8003e6a: 88bb ldrh r3, [r7, #4]
8003e6c: 4413 add r3, r2
8003e6e: b299 uxth r1, r3
8003e70: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003e74: b29a uxth r2, r3
8003e76: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003e7a: b29c uxth r4, r3
8003e7c: 8c3b ldrh r3, [r7, #32]
8003e7e: 9300 str r3, [sp, #0]
8003e80: 4623 mov r3, r4
8003e82: f7ff fed3 bl 8003c2c <fillRect_TFT>
}
}
line = line >> 1;
8003e86: 7b7b ldrb r3, [r7, #13]
8003e88: 085b lsrs r3, r3, #1
8003e8a: 737b strb r3, [r7, #13]
for ( j = 0; j<8; j++)
8003e8c: 7bbb ldrb r3, [r7, #14]
8003e8e: 3301 adds r3, #1
8003e90: 73bb strb r3, [r7, #14]
8003e92: 7bbb ldrb r3, [r7, #14]
8003e94: 2b07 cmp r3, #7
8003e96: d984 bls.n 8003da2 <displayChar_TFT+0x82>
for (i=0; i<6; i++ )
8003e98: 7bfb ldrb r3, [r7, #15]
8003e9a: 3301 adds r3, #1
8003e9c: 73fb strb r3, [r7, #15]
8003e9e: 7bfb ldrb r3, [r7, #15]
8003ea0: 2b05 cmp r3, #5
8003ea2: f67f af6a bls.w 8003d7a <displayChar_TFT+0x5a>
8003ea6: e000 b.n 8003eaa <displayChar_TFT+0x18a>
return;
8003ea8: bf00 nop
}
}
}
8003eaa: 3714 adds r7, #20
8003eac: 46bd mov sp, r7
8003eae: bd90 pop {r4, r7, pc}
8003eb0: 08004120 .word 0x08004120
08003eb4 <displayLogo_TFT>:
* Input :
* Output : None
* Return : None
*******************************************************************************/
void displayLogo_TFT( void)
{
8003eb4: b580 push {r7, lr}
8003eb6: b082 sub sp, #8
8003eb8: af00 add r7, sp, #0
uint8_t i,j,k,line;
uint16_t color=ST7735_WHITE;
8003eba: f64f 73ff movw r3, #65535 @ 0xffff
8003ebe: 807b strh r3, [r7, #2]
for(i=0;i<=120;i++)
8003ec0: 2300 movs r3, #0
8003ec2: 71fb strb r3, [r7, #7]
8003ec4: e09e b.n 8004004 <displayLogo_TFT+0x150>
{
for(j=0;j<= 1;j++)
8003ec6: 2300 movs r3, #0
8003ec8: 71bb strb r3, [r7, #6]
8003eca: e02b b.n 8003f24 <displayLogo_TFT+0x70>
{
line=(ALL_IS_mono_120[i+120*j]);
8003ecc: 79f9 ldrb r1, [r7, #7]
8003ece: 79ba ldrb r2, [r7, #6]
8003ed0: 4613 mov r3, r2
8003ed2: 011b lsls r3, r3, #4
8003ed4: 1a9b subs r3, r3, r2
8003ed6: 00db lsls r3, r3, #3
8003ed8: 440b add r3, r1
8003eda: 4a4f ldr r2, [pc, #316] @ (8004018 <displayLogo_TFT+0x164>)
8003edc: 5cd3 ldrb r3, [r2, r3]
8003ede: 713b strb r3, [r7, #4]
for ( k = 0; k<8; k++)
8003ee0: 2300 movs r3, #0
8003ee2: 717b strb r3, [r7, #5]
8003ee4: e018 b.n 8003f18 <displayLogo_TFT+0x64>
{
if (line & 0x1)
8003ee6: 793b ldrb r3, [r7, #4]
8003ee8: f003 0301 and.w r3, r3, #1
8003eec: 2b00 cmp r3, #0
8003eee: d00d beq.n 8003f0c <displayLogo_TFT+0x58>
{
drawPixel_TFT(i, j*8+k, color);
8003ef0: 79fb ldrb r3, [r7, #7]
8003ef2: b298 uxth r0, r3
8003ef4: 79bb ldrb r3, [r7, #6]
8003ef6: b29b uxth r3, r3
8003ef8: 00db lsls r3, r3, #3
8003efa: b29a uxth r2, r3
8003efc: 797b ldrb r3, [r7, #5]
8003efe: b29b uxth r3, r3
8003f00: 4413 add r3, r2
8003f02: b29b uxth r3, r3
8003f04: 887a ldrh r2, [r7, #2]
8003f06: 4619 mov r1, r3
8003f08: f7ff fe4a bl 8003ba0 <drawPixel_TFT>
}
line = line >> 1;
8003f0c: 793b ldrb r3, [r7, #4]
8003f0e: 085b lsrs r3, r3, #1
8003f10: 713b strb r3, [r7, #4]
for ( k = 0; k<8; k++)
8003f12: 797b ldrb r3, [r7, #5]
8003f14: 3301 adds r3, #1
8003f16: 717b strb r3, [r7, #5]
8003f18: 797b ldrb r3, [r7, #5]
8003f1a: 2b07 cmp r3, #7
8003f1c: d9e3 bls.n 8003ee6 <displayLogo_TFT+0x32>
for(j=0;j<= 1;j++)
8003f1e: 79bb ldrb r3, [r7, #6]
8003f20: 3301 adds r3, #1
8003f22: 71bb strb r3, [r7, #6]
8003f24: 79bb ldrb r3, [r7, #6]
8003f26: 2b01 cmp r3, #1
8003f28: d9d0 bls.n 8003ecc <displayLogo_TFT+0x18>
}
}
color=ST7735_RED;
8003f2a: f44f 4378 mov.w r3, #63488 @ 0xf800
8003f2e: 807b strh r3, [r7, #2]
for(j=2;j<= 3;j++)
8003f30: 2302 movs r3, #2
8003f32: 71bb strb r3, [r7, #6]
8003f34: e02b b.n 8003f8e <displayLogo_TFT+0xda>
{
line=(ALL_IS_mono_120[i+120*j]);
8003f36: 79f9 ldrb r1, [r7, #7]
8003f38: 79ba ldrb r2, [r7, #6]
8003f3a: 4613 mov r3, r2
8003f3c: 011b lsls r3, r3, #4
8003f3e: 1a9b subs r3, r3, r2
8003f40: 00db lsls r3, r3, #3
8003f42: 440b add r3, r1
8003f44: 4a34 ldr r2, [pc, #208] @ (8004018 <displayLogo_TFT+0x164>)
8003f46: 5cd3 ldrb r3, [r2, r3]
8003f48: 713b strb r3, [r7, #4]
for ( k = 0; k<8; k++)
8003f4a: 2300 movs r3, #0
8003f4c: 717b strb r3, [r7, #5]
8003f4e: e018 b.n 8003f82 <displayLogo_TFT+0xce>
{
if (line & 0x1)
8003f50: 793b ldrb r3, [r7, #4]
8003f52: f003 0301 and.w r3, r3, #1
8003f56: 2b00 cmp r3, #0
8003f58: d00d beq.n 8003f76 <displayLogo_TFT+0xc2>
{
drawPixel_TFT(i, j*8+k, color);
8003f5a: 79fb ldrb r3, [r7, #7]
8003f5c: b298 uxth r0, r3
8003f5e: 79bb ldrb r3, [r7, #6]
8003f60: b29b uxth r3, r3
8003f62: 00db lsls r3, r3, #3
8003f64: b29a uxth r2, r3
8003f66: 797b ldrb r3, [r7, #5]
8003f68: b29b uxth r3, r3
8003f6a: 4413 add r3, r2
8003f6c: b29b uxth r3, r3
8003f6e: 887a ldrh r2, [r7, #2]
8003f70: 4619 mov r1, r3
8003f72: f7ff fe15 bl 8003ba0 <drawPixel_TFT>
}
line = line >> 1;
8003f76: 793b ldrb r3, [r7, #4]
8003f78: 085b lsrs r3, r3, #1
8003f7a: 713b strb r3, [r7, #4]
for ( k = 0; k<8; k++)
8003f7c: 797b ldrb r3, [r7, #5]
8003f7e: 3301 adds r3, #1
8003f80: 717b strb r3, [r7, #5]
8003f82: 797b ldrb r3, [r7, #5]
8003f84: 2b07 cmp r3, #7
8003f86: d9e3 bls.n 8003f50 <displayLogo_TFT+0x9c>
for(j=2;j<= 3;j++)
8003f88: 79bb ldrb r3, [r7, #6]
8003f8a: 3301 adds r3, #1
8003f8c: 71bb strb r3, [r7, #6]
8003f8e: 79bb ldrb r3, [r7, #6]
8003f90: 2b03 cmp r3, #3
8003f92: d9d0 bls.n 8003f36 <displayLogo_TFT+0x82>
}
}
color=ST7735_WHITE;
8003f94: f64f 73ff movw r3, #65535 @ 0xffff
8003f98: 807b strh r3, [r7, #2]
for(j=4;j<= 5;j++)
8003f9a: 2304 movs r3, #4
8003f9c: 71bb strb r3, [r7, #6]
8003f9e: e02b b.n 8003ff8 <displayLogo_TFT+0x144>
{
line=(ALL_IS_mono_120[i+120*j]);
8003fa0: 79f9 ldrb r1, [r7, #7]
8003fa2: 79ba ldrb r2, [r7, #6]
8003fa4: 4613 mov r3, r2
8003fa6: 011b lsls r3, r3, #4
8003fa8: 1a9b subs r3, r3, r2
8003faa: 00db lsls r3, r3, #3
8003fac: 440b add r3, r1
8003fae: 4a1a ldr r2, [pc, #104] @ (8004018 <displayLogo_TFT+0x164>)
8003fb0: 5cd3 ldrb r3, [r2, r3]
8003fb2: 713b strb r3, [r7, #4]
for ( k = 0; k<8; k++)
8003fb4: 2300 movs r3, #0
8003fb6: 717b strb r3, [r7, #5]
8003fb8: e018 b.n 8003fec <displayLogo_TFT+0x138>
{
if (line & 0x1)
8003fba: 793b ldrb r3, [r7, #4]
8003fbc: f003 0301 and.w r3, r3, #1
8003fc0: 2b00 cmp r3, #0
8003fc2: d00d beq.n 8003fe0 <displayLogo_TFT+0x12c>
{
drawPixel_TFT(i, j*8+k, color);
8003fc4: 79fb ldrb r3, [r7, #7]
8003fc6: b298 uxth r0, r3
8003fc8: 79bb ldrb r3, [r7, #6]
8003fca: b29b uxth r3, r3
8003fcc: 00db lsls r3, r3, #3
8003fce: b29a uxth r2, r3
8003fd0: 797b ldrb r3, [r7, #5]
8003fd2: b29b uxth r3, r3
8003fd4: 4413 add r3, r2
8003fd6: b29b uxth r3, r3
8003fd8: 887a ldrh r2, [r7, #2]
8003fda: 4619 mov r1, r3
8003fdc: f7ff fde0 bl 8003ba0 <drawPixel_TFT>
}
line = line >> 1;
8003fe0: 793b ldrb r3, [r7, #4]
8003fe2: 085b lsrs r3, r3, #1
8003fe4: 713b strb r3, [r7, #4]
for ( k = 0; k<8; k++)
8003fe6: 797b ldrb r3, [r7, #5]
8003fe8: 3301 adds r3, #1
8003fea: 717b strb r3, [r7, #5]
8003fec: 797b ldrb r3, [r7, #5]
8003fee: 2b07 cmp r3, #7
8003ff0: d9e3 bls.n 8003fba <displayLogo_TFT+0x106>
for(j=4;j<= 5;j++)
8003ff2: 79bb ldrb r3, [r7, #6]
8003ff4: 3301 adds r3, #1
8003ff6: 71bb strb r3, [r7, #6]
8003ff8: 79bb ldrb r3, [r7, #6]
8003ffa: 2b05 cmp r3, #5
8003ffc: d9d0 bls.n 8003fa0 <displayLogo_TFT+0xec>
for(i=0;i<=120;i++)
8003ffe: 79fb ldrb r3, [r7, #7]
8004000: 3301 adds r3, #1
8004002: 71fb strb r3, [r7, #7]
8004004: 79fb ldrb r3, [r7, #7]
8004006: 2b78 cmp r3, #120 @ 0x78
8004008: f67f af5d bls.w 8003ec6 <displayLogo_TFT+0x12>
}
}
}
}
800400c: bf00 nop
800400e: bf00 nop
8004010: 3708 adds r7, #8
8004012: 46bd mov sp, r7
8004014: bd80 pop {r7, pc}
8004016: bf00 nop
8004018: 0800461c .word 0x0800461c
0800401c <memset>:
800401c: 4603 mov r3, r0
800401e: 4402 add r2, r0
8004020: 4293 cmp r3, r2
8004022: d100 bne.n 8004026 <memset+0xa>
8004024: 4770 bx lr
8004026: f803 1b01 strb.w r1, [r3], #1
800402a: e7f9 b.n 8004020 <memset+0x4>
0800402c <__libc_init_array>:
800402c: b570 push {r4, r5, r6, lr}
800402e: 2600 movs r6, #0
8004030: 4d0c ldr r5, [pc, #48] @ (8004064 <__libc_init_array+0x38>)
8004032: 4c0d ldr r4, [pc, #52] @ (8004068 <__libc_init_array+0x3c>)
8004034: 1b64 subs r4, r4, r5
8004036: 10a4 asrs r4, r4, #2
8004038: 42a6 cmp r6, r4
800403a: d109 bne.n 8004050 <__libc_init_array+0x24>
800403c: f000 f81a bl 8004074 <_init>
8004040: 2600 movs r6, #0
8004042: 4d0a ldr r5, [pc, #40] @ (800406c <__libc_init_array+0x40>)
8004044: 4c0a ldr r4, [pc, #40] @ (8004070 <__libc_init_array+0x44>)
8004046: 1b64 subs r4, r4, r5
8004048: 10a4 asrs r4, r4, #2
800404a: 42a6 cmp r6, r4
800404c: d105 bne.n 800405a <__libc_init_array+0x2e>
800404e: bd70 pop {r4, r5, r6, pc}
8004050: f855 3b04 ldr.w r3, [r5], #4
8004054: 4798 blx r3
8004056: 3601 adds r6, #1
8004058: e7ee b.n 8004038 <__libc_init_array+0xc>
800405a: f855 3b04 ldr.w r3, [r5], #4
800405e: 4798 blx r3
8004060: 3601 adds r6, #1
8004062: e7f2 b.n 800404a <__libc_init_array+0x1e>
8004064: 080048f4 .word 0x080048f4
8004068: 080048f4 .word 0x080048f4
800406c: 080048f4 .word 0x080048f4
8004070: 080048f8 .word 0x080048f8
08004074 <_init>:
8004074: b5f8 push {r3, r4, r5, r6, r7, lr}
8004076: bf00 nop
8004078: bcf8 pop {r3, r4, r5, r6, r7}
800407a: bc08 pop {r3}
800407c: 469e mov lr, r3
800407e: 4770 bx lr
08004080 <_fini>:
8004080: b5f8 push {r3, r4, r5, r6, r7, lr}
8004082: bf00 nop
8004084: bcf8 pop {r3, r4, r5, r6, r7}
8004086: bc08 pop {r3}
8004088: 469e mov lr, r3
800408a: 4770 bx lr
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