BreizhHardware/TP-STM32-CIPA3
1
0
Fork 0
mirror of https://github.com/BreizhHardware/TP-STM32-CIPA3.git synced 2026-01-18 16:17:23 +01:00
Code Issues Packages Projects Releases Wiki Activity
Files
78f4005599f2335f5bb4cf6c1ee655088df6704c
TP-STM32-CIPA3/TP4_GAMME/Debug/TP4_GAMME.list
Félix MARQUET 78f4005599 TP4 Exo 2 (Jouer la mélodie)
2025-06-25 15:09:27 +02:00

8030 lines
295 KiB
Plaintext
Raw Blame History

TP4_GAMME.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00002d68 0800013c 0800013c 0000113c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000002c 08002ea4 08002ea4 00003ea4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002ed0 08002ed0 0000400c 2**0
CONTENTS, READONLY
4 .ARM 00000008 08002ed0 08002ed0 00003ed0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08002ed8 08002ed8 0000400c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002ed8 08002ed8 00003ed8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08002edc 08002edc 00003edc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08002ee0 00004000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000000b8 2000000c 08002eec 0000400c 2**2
ALLOC
10 ._user_heap_stack 00000604 200000c4 08002eec 000040c4 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000400c 2**0
CONTENTS, READONLY
12 .debug_info 000090ef 00000000 00000000 00004035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000018df 00000000 00000000 0000d124 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000ab0 00000000 00000000 0000ea08 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 0000081a 00000000 00000000 0000f4b8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000155f9 00000000 00000000 0000fcd2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000aad6 00000000 00000000 000252cb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0008863a 00000000 00000000 0002fda1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000b83db 2**0
CONTENTS, READONLY
20 .debug_frame 00002c14 00000000 00000000 000b8420 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000070 00000000 00000000 000bb034 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800013c <__do_global_dtors_aux>:
800013c: b510 push {r4, lr}
800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>)
8000140: 7823 ldrb r3, [r4, #0]
8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16>
8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>)
8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12>
8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>)
800014a: f3af 8000 nop.w
800014e: 2301 movs r3, #1
8000150: 7023 strb r3, [r4, #0]
8000152: bd10 pop {r4, pc}
8000154: 2000000c .word 0x2000000c
8000158: 00000000 .word 0x00000000
800015c: 08002e8c .word 0x08002e8c
08000160 <frame_dummy>:
8000160: b508 push {r3, lr}
8000162: 4b03 ldr r3, [pc, #12] @ (8000170 <frame_dummy+0x10>)
8000164: b11b cbz r3, 800016e <frame_dummy+0xe>
8000166: 4903 ldr r1, [pc, #12] @ (8000174 <frame_dummy+0x14>)
8000168: 4803 ldr r0, [pc, #12] @ (8000178 <frame_dummy+0x18>)
800016a: f3af 8000 nop.w
800016e: bd08 pop {r3, pc}
8000170: 00000000 .word 0x00000000
8000174: 20000010 .word 0x20000010
8000178: 08002e8c .word 0x08002e8c
0800017c <__aeabi_uldivmod>:
800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18>
800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18>
8000180: 2900 cmp r1, #0
8000182: bf08 it eq
8000184: 2800 cmpeq r0, #0
8000186: bf1c itt ne
8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
8000190: f000 b98c b.w 80004ac <__aeabi_idiv0>
8000194: f1ad 0c08 sub.w ip, sp, #8
8000198: e96d ce04 strd ip, lr, [sp, #-16]!
800019c: f000 f806 bl 80001ac <__udivmoddi4>
80001a0: f8dd e004 ldr.w lr, [sp, #4]
80001a4: e9dd 2302 ldrd r2, r3, [sp, #8]
80001a8: b004 add sp, #16
80001aa: 4770 bx lr
080001ac <__udivmoddi4>:
80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001b0: 9d08 ldr r5, [sp, #32]
80001b2: 468e mov lr, r1
80001b4: 4604 mov r4, r0
80001b6: 4688 mov r8, r1
80001b8: 2b00 cmp r3, #0
80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6>
80001bc: 428a cmp r2, r1
80001be: 4617 mov r7, r2
80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc>
80001c2: fab2 f682 clz r6, r2
80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30>
80001c8: f1c6 0320 rsb r3, r6, #32
80001cc: fa01 f806 lsl.w r8, r1, r6
80001d0: fa20 f303 lsr.w r3, r0, r3
80001d4: 40b7 lsls r7, r6
80001d6: ea43 0808 orr.w r8, r3, r8
80001da: 40b4 lsls r4, r6
80001dc: ea4f 4e17 mov.w lr, r7, lsr #16
80001e0: fbb8 f1fe udiv r1, r8, lr
80001e4: fa1f fc87 uxth.w ip, r7
80001e8: fb0e 8811 mls r8, lr, r1, r8
80001ec: fb01 f20c mul.w r2, r1, ip
80001f0: 0c23 lsrs r3, r4, #16
80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16
80001f6: 429a cmp r2, r3
80001f8: d909 bls.n 800020e <__udivmoddi4+0x62>
80001fa: 18fb adds r3, r7, r3
80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e>
8000204: 429a cmp r2, r3
8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e>
800020a: 3902 subs r1, #2
800020c: 443b add r3, r7
800020e: 1a9a subs r2, r3, r2
8000210: fbb2 f0fe udiv r0, r2, lr
8000214: fb0e 2210 mls r2, lr, r0, r2
8000218: fb00 fc0c mul.w ip, r0, ip
800021c: b2a3 uxth r3, r4
800021e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000222: 459c cmp ip, r3
8000224: d909 bls.n 800023a <__udivmoddi4+0x8e>
8000226: 18fb adds r3, r7, r3
8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232>
8000230: 459c cmp ip, r3
8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232>
8000236: 443b add r3, r7
8000238: 3802 subs r0, #2
800023a: ea40 4001 orr.w r0, r0, r1, lsl #16
800023e: 2100 movs r1, #0
8000240: eba3 030c sub.w r3, r3, ip
8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2>
8000246: 2200 movs r2, #0
8000248: 40f3 lsrs r3, r6
800024a: e9c5 3200 strd r3, r2, [r5]
800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000252: 428b cmp r3, r1
8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6>
8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0>
8000258: e9c5 0100 strd r0, r1, [r5]
800025c: 2100 movs r1, #0
800025e: 4608 mov r0, r1
8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2>
8000262: fab3 f183 clz r1, r3
8000266: 2900 cmp r1, #0
8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c>
800026a: 4573 cmp r3, lr
800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8>
800026e: 4282 cmp r2, r0
8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8>
8000274: 1a84 subs r4, r0, r2
8000276: eb6e 0203 sbc.w r2, lr, r3
800027a: 2001 movs r0, #1
800027c: 4690 mov r8, r2
800027e: 2d00 cmp r5, #0
8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2>
8000282: e9c5 4800 strd r4, r8, [r5]
8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2>
8000288: 2a00 cmp r2, #0
800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204>
800028e: fab2 f682 clz r6, r2
8000292: 2e00 cmp r6, #0
8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236>
8000298: 1a8a subs r2, r1, r2
800029a: 2101 movs r1, #1
800029c: 0c03 lsrs r3, r0, #16
800029e: ea4f 4e17 mov.w lr, r7, lsr #16
80002a2: b280 uxth r0, r0
80002a4: b2bc uxth r4, r7
80002a6: fbb2 fcfe udiv ip, r2, lr
80002aa: fb0e 221c mls r2, lr, ip, r2
80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16
80002b2: fb04 f20c mul.w r2, r4, ip
80002b6: 429a cmp r2, r3
80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e>
80002ba: 18fb adds r3, r7, r3
80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c>
80002c2: 429a cmp r2, r3
80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2>
80002c8: 46c4 mov ip, r8
80002ca: 1a9b subs r3, r3, r2
80002cc: fbb3 f2fe udiv r2, r3, lr
80002d0: fb0e 3312 mls r3, lr, r2, r3
80002d4: fb02 f404 mul.w r4, r2, r4
80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16
80002dc: 429c cmp r4, r3
80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144>
80002e0: 18fb adds r3, r7, r3
80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142>
80002e8: 429c cmp r4, r3
80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc>
80002ee: 4602 mov r2, r0
80002f0: 1b1b subs r3, r3, r4
80002f2: ea42 400c orr.w r0, r2, ip, lsl #16
80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98>
80002f8: f1c1 0620 rsb r6, r1, #32
80002fc: 408b lsls r3, r1
80002fe: fa22 f706 lsr.w r7, r2, r6
8000302: 431f orrs r7, r3
8000304: fa2e fa06 lsr.w sl, lr, r6
8000308: ea4f 4917 mov.w r9, r7, lsr #16
800030c: fbba f8f9 udiv r8, sl, r9
8000310: fa0e fe01 lsl.w lr, lr, r1
8000314: fa20 f306 lsr.w r3, r0, r6
8000318: fb09 aa18 mls sl, r9, r8, sl
800031c: fa1f fc87 uxth.w ip, r7
8000320: ea43 030e orr.w r3, r3, lr
8000324: fa00 fe01 lsl.w lr, r0, r1
8000328: fb08 f00c mul.w r0, r8, ip
800032c: 0c1c lsrs r4, r3, #16
800032e: ea44 440a orr.w r4, r4, sl, lsl #16
8000332: 42a0 cmp r0, r4
8000334: fa02 f201 lsl.w r2, r2, r1
8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4>
800033a: 193c adds r4, r7, r4
800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff
8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4>
8000344: 42a0 cmp r0, r4
8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4>
800034a: f1a8 0802 sub.w r8, r8, #2
800034e: 443c add r4, r7
8000350: 1a24 subs r4, r4, r0
8000352: b298 uxth r0, r3
8000354: fbb4 f3f9 udiv r3, r4, r9
8000358: fb09 4413 mls r4, r9, r3, r4
800035c: fb03 fc0c mul.w ip, r3, ip
8000360: ea40 4404 orr.w r4, r0, r4, lsl #16
8000364: 45a4 cmp ip, r4
8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0>
8000368: 193c adds r4, r7, r4
800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff
800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0>
8000372: 45a4 cmp ip, r4
8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0>
8000378: 3b02 subs r3, #2
800037a: 443c add r4, r7
800037c: ea43 4008 orr.w r0, r3, r8, lsl #16
8000380: eba4 040c sub.w r4, r4, ip
8000384: fba0 8c02 umull r8, ip, r0, r2
8000388: 4564 cmp r4, ip
800038a: 4643 mov r3, r8
800038c: 46e1 mov r9, ip
800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae>
8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa>
8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200>
8000394: ebbe 0203 subs.w r2, lr, r3
8000398: eb64 0409 sbc.w r4, r4, r9
800039c: fa04 f606 lsl.w r6, r4, r6
80003a0: fa22 f301 lsr.w r3, r2, r1
80003a4: 431e orrs r6, r3
80003a6: 40cc lsrs r4, r1
80003a8: e9c5 6400 strd r6, r4, [r5]
80003ac: 2100 movs r1, #0
80003ae: e74e b.n 800024e <__udivmoddi4+0xa2>
80003b0: fbb1 fcf2 udiv ip, r1, r2
80003b4: 0c01 lsrs r1, r0, #16
80003b6: ea41 410e orr.w r1, r1, lr, lsl #16
80003ba: b280 uxth r0, r0
80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16
80003c0: 463b mov r3, r7
80003c2: fbb1 f1f7 udiv r1, r1, r7
80003c6: 4638 mov r0, r7
80003c8: 463c mov r4, r7
80003ca: 46b8 mov r8, r7
80003cc: 46be mov lr, r7
80003ce: 2620 movs r6, #32
80003d0: eba2 0208 sub.w r2, r2, r8
80003d4: ea41 410c orr.w r1, r1, ip, lsl #16
80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa>
80003da: 4601 mov r1, r0
80003dc: e717 b.n 800020e <__udivmoddi4+0x62>
80003de: 4610 mov r0, r2
80003e0: e72b b.n 800023a <__udivmoddi4+0x8e>
80003e2: f1c6 0120 rsb r1, r6, #32
80003e6: fa2e fc01 lsr.w ip, lr, r1
80003ea: 40b7 lsls r7, r6
80003ec: fa0e fe06 lsl.w lr, lr, r6
80003f0: fa20 f101 lsr.w r1, r0, r1
80003f4: ea41 010e orr.w r1, r1, lr
80003f8: ea4f 4e17 mov.w lr, r7, lsr #16
80003fc: fbbc f8fe udiv r8, ip, lr
8000400: b2bc uxth r4, r7
8000402: fb0e cc18 mls ip, lr, r8, ip
8000406: fb08 f904 mul.w r9, r8, r4
800040a: 0c0a lsrs r2, r1, #16
800040c: ea42 420c orr.w r2, r2, ip, lsl #16
8000410: 40b0 lsls r0, r6
8000412: 4591 cmp r9, r2
8000414: ea4f 4310 mov.w r3, r0, lsr #16
8000418: b280 uxth r0, r0
800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee>
800041c: 18ba adds r2, r7, r2
800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c>
8000424: 4591 cmp r9, r2
8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc>
8000428: eba2 0209 sub.w r2, r2, r9
800042c: fbb2 f9fe udiv r9, r2, lr
8000430: fb09 f804 mul.w r8, r9, r4
8000434: fb0e 2a19 mls sl, lr, r9, r2
8000438: b28a uxth r2, r1
800043a: ea42 420a orr.w r2, r2, sl, lsl #16
800043e: 4542 cmp r2, r8
8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea>
8000442: 18ba adds r2, r7, r2
8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224>
800044a: 4542 cmp r2, r8
800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224>
800044e: f1a9 0102 sub.w r1, r9, #2
8000452: 443a add r2, r7
8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224>
8000456: 45c6 cmp lr, r8
8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6>
800045a: ebb8 0302 subs.w r3, r8, r2
800045e: eb6c 0c07 sbc.w ip, ip, r7
8000462: 3801 subs r0, #1
8000464: 46e1 mov r9, ip
8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6>
8000468: eba7 0909 sub.w r9, r7, r9
800046c: 444a add r2, r9
800046e: fbb2 f9fe udiv r9, r2, lr
8000472: f1a8 0c02 sub.w ip, r8, #2
8000476: fb09 f804 mul.w r8, r9, r4
800047a: e7db b.n 8000434 <__udivmoddi4+0x288>
800047c: 4603 mov r3, r0
800047e: e77d b.n 800037c <__udivmoddi4+0x1d0>
8000480: 46d0 mov r8, sl
8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4>
8000484: 4608 mov r0, r1
8000486: e6fa b.n 800027e <__udivmoddi4+0xd2>
8000488: 443b add r3, r7
800048a: 3a02 subs r2, #2
800048c: e730 b.n 80002f0 <__udivmoddi4+0x144>
800048e: f1ac 0c02 sub.w ip, ip, #2
8000492: 443b add r3, r7
8000494: e719 b.n 80002ca <__udivmoddi4+0x11e>
8000496: 4649 mov r1, r9
8000498: e79a b.n 80003d0 <__udivmoddi4+0x224>
800049a: eba2 0209 sub.w r2, r2, r9
800049e: fbb2 f9fe udiv r9, r2, lr
80004a2: 46c4 mov ip, r8
80004a4: fb09 f804 mul.w r8, r9, r4
80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288>
80004aa: bf00 nop
080004ac <__aeabi_idiv0>:
80004ac: 4770 bx lr
80004ae: bf00 nop
080004b0 <DO>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void DO() {
80004b0: b580 push {r7, lr}
80004b2: af00 add r7, sp, #0
MAX7219_DisplayChar(4, 0);
80004b4: 2100 movs r1, #0
80004b6: 2004 movs r0, #4
80004b8: f000 fbb6 bl 8000c28 <MAX7219_DisplayChar>
TIM3->PSC = ((16000000/524)/1600) - 1;
80004bc: 4b02 ldr r3, [pc, #8] @ (80004c8 <DO+0x18>)
80004be: 2212 movs r2, #18
80004c0: 629a str r2, [r3, #40] @ 0x28
}
80004c2: bf00 nop
80004c4: bd80 pop {r7, pc}
80004c6: bf00 nop
80004c8: 40000400 .word 0x40000400
080004cc <RE>:
void RE() {
80004cc: b580 push {r7, lr}
80004ce: af00 add r7, sp, #0
MAX7219_DisplayChar(4, 1);
80004d0: 2101 movs r1, #1
80004d2: 2004 movs r0, #4
80004d4: f000 fba8 bl 8000c28 <MAX7219_DisplayChar>
TIM3->PSC = ((16000000/587)/1600) - 1;
80004d8: 4b02 ldr r3, [pc, #8] @ (80004e4 <RE+0x18>)
80004da: 2210 movs r2, #16
80004dc: 629a str r2, [r3, #40] @ 0x28
}
80004de: bf00 nop
80004e0: bd80 pop {r7, pc}
80004e2: bf00 nop
80004e4: 40000400 .word 0x40000400
080004e8 <MI>:
void MI() {
80004e8: b580 push {r7, lr}
80004ea: af00 add r7, sp, #0
MAX7219_DisplayChar(4, 2);
80004ec: 2102 movs r1, #2
80004ee: 2004 movs r0, #4
80004f0: f000 fb9a bl 8000c28 <MAX7219_DisplayChar>
TIM3->PSC = ((16000000/662)/1600) - 1;
80004f4: 4b02 ldr r3, [pc, #8] @ (8000500 <MI+0x18>)
80004f6: 220e movs r2, #14
80004f8: 629a str r2, [r3, #40] @ 0x28
}
80004fa: bf00 nop
80004fc: bd80 pop {r7, pc}
80004fe: bf00 nop
8000500: 40000400 .word 0x40000400
08000504 <FA>:
void FA() {
8000504: b580 push {r7, lr}
8000506: af00 add r7, sp, #0
MAX7219_DisplayChar(4, 3);
8000508: 2103 movs r1, #3
800050a: 2004 movs r0, #4
800050c: f000 fb8c bl 8000c28 <MAX7219_DisplayChar>
TIM3->PSC = ((16000000/701)/1600) - 1;
8000510: 4b02 ldr r3, [pc, #8] @ (800051c <FA+0x18>)
8000512: 220d movs r2, #13
8000514: 629a str r2, [r3, #40] @ 0x28
}
8000516: bf00 nop
8000518: bd80 pop {r7, pc}
800051a: bf00 nop
800051c: 40000400 .word 0x40000400
08000520 <SOL>:
void SOL() {
8000520: b580 push {r7, lr}
8000522: af00 add r7, sp, #0
MAX7219_DisplayChar(4, 4);
8000524: 2104 movs r1, #4
8000526: 2004 movs r0, #4
8000528: f000 fb7e bl 8000c28 <MAX7219_DisplayChar>
TIM3->PSC = ((16000000/787)/1600) - 1;
800052c: 4b02 ldr r3, [pc, #8] @ (8000538 <SOL+0x18>)
800052e: 220b movs r2, #11
8000530: 629a str r2, [r3, #40] @ 0x28
}
8000532: bf00 nop
8000534: bd80 pop {r7, pc}
8000536: bf00 nop
8000538: 40000400 .word 0x40000400
0800053c <LA>:
void LA() {
800053c: b580 push {r7, lr}
800053e: af00 add r7, sp, #0
MAX7219_DisplayChar(4, 5);
8000540: 2105 movs r1, #5
8000542: 2004 movs r0, #4
8000544: f000 fb70 bl 8000c28 <MAX7219_DisplayChar>
TIM3->PSC = ((16000000/878)/1600) - 1;
8000548: 4b02 ldr r3, [pc, #8] @ (8000554 <LA+0x18>)
800054a: 220a movs r2, #10
800054c: 629a str r2, [r3, #40] @ 0x28
}
800054e: bf00 nop
8000550: bd80 pop {r7, pc}
8000552: bf00 nop
8000554: 40000400 .word 0x40000400
08000558 <SI>:
void SI() {
8000558: b580 push {r7, lr}
800055a: af00 add r7, sp, #0
MAX7219_DisplayChar(4, 6);
800055c: 2106 movs r1, #6
800055e: 2004 movs r0, #4
8000560: f000 fb62 bl 8000c28 <MAX7219_DisplayChar>
TIM3->PSC = ((16000000/1004)/1600) - 1;
8000564: 4b02 ldr r3, [pc, #8] @ (8000570 <SI+0x18>)
8000566: 2208 movs r2, #8
8000568: 629a str r2, [r3, #40] @ 0x28
}
800056a: bf00 nop
800056c: bd80 pop {r7, pc}
800056e: bf00 nop
8000570: 40000400 .word 0x40000400
08000574 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000574: b580 push {r7, lr}
8000576: b082 sub sp, #8
8000578: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800057a: f000 fb9b bl 8000cb4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800057e: f000 f85f bl 8000640 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000582: f000 f94d bl 8000820 <MX_GPIO_Init>
MX_SPI1_Init();
8000586: f000 f8a1 bl 80006cc <MX_SPI1_Init>
MX_TIM3_Init();
800058a: f000 f8d5 bl 8000738 <MX_TIM3_Init>
/* USER CODE BEGIN 2 */
MAX7219_Init();
800058e: f000 fafe bl 8000b8e <MAX7219_Init>
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
8000592: 2100 movs r1, #0
8000594: 4829 ldr r0, [pc, #164] @ (800063c <main+0xc8>)
8000596: f001 ffa9 bl 80024ec <HAL_TIM_PWM_Start>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
MAX7219_Clear();
800059a: f000 fb2f bl 8000bfc <MAX7219_Clear>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
for (int i = 0; i < 7; i++) {
800059e: 2300 movs r3, #0
80005a0: 607b str r3, [r7, #4]
80005a2: e047 b.n 8000634 <main+0xc0>
if (i == 0) { // DO
80005a4: 687b ldr r3, [r7, #4]
80005a6: 2b00 cmp r3, #0
80005a8: d106 bne.n 80005b8 <main+0x44>
DO();
80005aa: f7ff ff81 bl 80004b0 <DO>
HAL_Delay(500);
80005ae: f44f 70fa mov.w r0, #500 @ 0x1f4
80005b2: f000 fbed bl 8000d90 <HAL_Delay>
80005b6: e03a b.n 800062e <main+0xba>
} else if (i == 1) { // RE
80005b8: 687b ldr r3, [r7, #4]
80005ba: 2b01 cmp r3, #1
80005bc: d106 bne.n 80005cc <main+0x58>
RE();
80005be: f7ff ff85 bl 80004cc <RE>
HAL_Delay(500);
80005c2: f44f 70fa mov.w r0, #500 @ 0x1f4
80005c6: f000 fbe3 bl 8000d90 <HAL_Delay>
80005ca: e030 b.n 800062e <main+0xba>
} else if (i == 2) { // MI
80005cc: 687b ldr r3, [r7, #4]
80005ce: 2b02 cmp r3, #2
80005d0: d106 bne.n 80005e0 <main+0x6c>
MI();
80005d2: f7ff ff89 bl 80004e8 <MI>
HAL_Delay(500);
80005d6: f44f 70fa mov.w r0, #500 @ 0x1f4
80005da: f000 fbd9 bl 8000d90 <HAL_Delay>
80005de: e026 b.n 800062e <main+0xba>
} else if (i == 3) { // FA
80005e0: 687b ldr r3, [r7, #4]
80005e2: 2b03 cmp r3, #3
80005e4: d106 bne.n 80005f4 <main+0x80>
FA();
80005e6: f7ff ff8d bl 8000504 <FA>
HAL_Delay(500);
80005ea: f44f 70fa mov.w r0, #500 @ 0x1f4
80005ee: f000 fbcf bl 8000d90 <HAL_Delay>
80005f2: e01c b.n 800062e <main+0xba>
} else if (i == 4) { // SOL
80005f4: 687b ldr r3, [r7, #4]
80005f6: 2b04 cmp r3, #4
80005f8: d106 bne.n 8000608 <main+0x94>
SOL();
80005fa: f7ff ff91 bl 8000520 <SOL>
HAL_Delay(500);
80005fe: f44f 70fa mov.w r0, #500 @ 0x1f4
8000602: f000 fbc5 bl 8000d90 <HAL_Delay>
8000606: e012 b.n 800062e <main+0xba>
} else if (i == 5) { // LA
8000608: 687b ldr r3, [r7, #4]
800060a: 2b05 cmp r3, #5
800060c: d106 bne.n 800061c <main+0xa8>
LA();
800060e: f7ff ff95 bl 800053c <LA>
HAL_Delay(500);
8000612: f44f 70fa mov.w r0, #500 @ 0x1f4
8000616: f000 fbbb bl 8000d90 <HAL_Delay>
800061a: e008 b.n 800062e <main+0xba>
} else if (i == 6) { // SI
800061c: 687b ldr r3, [r7, #4]
800061e: 2b06 cmp r3, #6
8000620: d105 bne.n 800062e <main+0xba>
SI();
8000622: f7ff ff99 bl 8000558 <SI>
HAL_Delay(500);
8000626: f44f 70fa mov.w r0, #500 @ 0x1f4
800062a: f000 fbb1 bl 8000d90 <HAL_Delay>
for (int i = 0; i < 7; i++) {
800062e: 687b ldr r3, [r7, #4]
8000630: 3301 adds r3, #1
8000632: 607b str r3, [r7, #4]
8000634: 687b ldr r3, [r7, #4]
8000636: 2b06 cmp r3, #6
8000638: ddb4 ble.n 80005a4 <main+0x30>
800063a: e7b0 b.n 800059e <main+0x2a>
800063c: 20000080 .word 0x20000080
08000640 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000640: b580 push {r7, lr}
8000642: b092 sub sp, #72 @ 0x48
8000644: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000646: f107 0314 add.w r3, r7, #20
800064a: 2234 movs r2, #52 @ 0x34
800064c: 2100 movs r1, #0
800064e: 4618 mov r0, r3
8000650: f002 fbf0 bl 8002e34 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000654: 463b mov r3, r7
8000656: 2200 movs r2, #0
8000658: 601a str r2, [r3, #0]
800065a: 605a str r2, [r3, #4]
800065c: 609a str r2, [r3, #8]
800065e: 60da str r2, [r3, #12]
8000660: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000662: 4b19 ldr r3, [pc, #100] @ (80006c8 <SystemClock_Config+0x88>)
8000664: 681b ldr r3, [r3, #0]
8000666: f423 53c0 bic.w r3, r3, #6144 @ 0x1800
800066a: 4a17 ldr r2, [pc, #92] @ (80006c8 <SystemClock_Config+0x88>)
800066c: f443 6300 orr.w r3, r3, #2048 @ 0x800
8000670: 6013 str r3, [r2, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000672: 2302 movs r3, #2
8000674: 617b str r3, [r7, #20]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000676: 2301 movs r3, #1
8000678: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800067a: 2310 movs r3, #16
800067c: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
800067e: 2300 movs r3, #0
8000680: 63bb str r3, [r7, #56] @ 0x38
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000682: f107 0314 add.w r3, r7, #20
8000686: 4618 mov r0, r3
8000688: f000 fe7c bl 8001384 <HAL_RCC_OscConfig>
800068c: 4603 mov r3, r0
800068e: 2b00 cmp r3, #0
8000690: d001 beq.n 8000696 <SystemClock_Config+0x56>
{
Error_Handler();
8000692: f000 f94b bl 800092c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000696: 230f movs r3, #15
8000698: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
800069a: 2301 movs r3, #1
800069c: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800069e: 2300 movs r3, #0
80006a0: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80006a2: 2300 movs r3, #0
80006a4: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80006a6: 2300 movs r3, #0
80006a8: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80006aa: 463b mov r3, r7
80006ac: 2100 movs r1, #0
80006ae: 4618 mov r0, r3
80006b0: f001 f998 bl 80019e4 <HAL_RCC_ClockConfig>
80006b4: 4603 mov r3, r0
80006b6: 2b00 cmp r3, #0
80006b8: d001 beq.n 80006be <SystemClock_Config+0x7e>
{
Error_Handler();
80006ba: f000 f937 bl 800092c <Error_Handler>
}
}
80006be: bf00 nop
80006c0: 3748 adds r7, #72 @ 0x48
80006c2: 46bd mov sp, r7
80006c4: bd80 pop {r7, pc}
80006c6: bf00 nop
80006c8: 40007000 .word 0x40007000
080006cc <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
80006cc: b580 push {r7, lr}
80006ce: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
80006d0: 4b17 ldr r3, [pc, #92] @ (8000730 <MX_SPI1_Init+0x64>)
80006d2: 4a18 ldr r2, [pc, #96] @ (8000734 <MX_SPI1_Init+0x68>)
80006d4: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
80006d6: 4b16 ldr r3, [pc, #88] @ (8000730 <MX_SPI1_Init+0x64>)
80006d8: f44f 7282 mov.w r2, #260 @ 0x104
80006dc: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
80006de: 4b14 ldr r3, [pc, #80] @ (8000730 <MX_SPI1_Init+0x64>)
80006e0: 2200 movs r2, #0
80006e2: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
80006e4: 4b12 ldr r3, [pc, #72] @ (8000730 <MX_SPI1_Init+0x64>)
80006e6: 2200 movs r2, #0
80006e8: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
80006ea: 4b11 ldr r3, [pc, #68] @ (8000730 <MX_SPI1_Init+0x64>)
80006ec: 2200 movs r2, #0
80006ee: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
80006f0: 4b0f ldr r3, [pc, #60] @ (8000730 <MX_SPI1_Init+0x64>)
80006f2: 2200 movs r2, #0
80006f4: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_SOFT;
80006f6: 4b0e ldr r3, [pc, #56] @ (8000730 <MX_SPI1_Init+0x64>)
80006f8: f44f 7200 mov.w r2, #512 @ 0x200
80006fc: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80006fe: 4b0c ldr r3, [pc, #48] @ (8000730 <MX_SPI1_Init+0x64>)
8000700: 2200 movs r2, #0
8000702: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000704: 4b0a ldr r3, [pc, #40] @ (8000730 <MX_SPI1_Init+0x64>)
8000706: 2200 movs r2, #0
8000708: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
800070a: 4b09 ldr r3, [pc, #36] @ (8000730 <MX_SPI1_Init+0x64>)
800070c: 2200 movs r2, #0
800070e: 625a str r2, [r3, #36] @ 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000710: 4b07 ldr r3, [pc, #28] @ (8000730 <MX_SPI1_Init+0x64>)
8000712: 2200 movs r2, #0
8000714: 629a str r2, [r3, #40] @ 0x28
hspi1.Init.CRCPolynomial = 10;
8000716: 4b06 ldr r3, [pc, #24] @ (8000730 <MX_SPI1_Init+0x64>)
8000718: 220a movs r2, #10
800071a: 62da str r2, [r3, #44] @ 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
800071c: 4804 ldr r0, [pc, #16] @ (8000730 <MX_SPI1_Init+0x64>)
800071e: f001 fbb3 bl 8001e88 <HAL_SPI_Init>
8000722: 4603 mov r3, r0
8000724: 2b00 cmp r3, #0
8000726: d001 beq.n 800072c <MX_SPI1_Init+0x60>
{
Error_Handler();
8000728: f000 f900 bl 800092c <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
800072c: bf00 nop
800072e: bd80 pop {r7, pc}
8000730: 20000028 .word 0x20000028
8000734: 40013000 .word 0x40013000
08000738 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
8000738: b580 push {r7, lr}
800073a: b08a sub sp, #40 @ 0x28
800073c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800073e: f107 0318 add.w r3, r7, #24
8000742: 2200 movs r2, #0
8000744: 601a str r2, [r3, #0]
8000746: 605a str r2, [r3, #4]
8000748: 609a str r2, [r3, #8]
800074a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800074c: f107 0310 add.w r3, r7, #16
8000750: 2200 movs r2, #0
8000752: 601a str r2, [r3, #0]
8000754: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8000756: 463b mov r3, r7
8000758: 2200 movs r2, #0
800075a: 601a str r2, [r3, #0]
800075c: 605a str r2, [r3, #4]
800075e: 609a str r2, [r3, #8]
8000760: 60da str r2, [r3, #12]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8000762: 4b2d ldr r3, [pc, #180] @ (8000818 <MX_TIM3_Init+0xe0>)
8000764: 4a2d ldr r2, [pc, #180] @ (800081c <MX_TIM3_Init+0xe4>)
8000766: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 19-1;
8000768: 4b2b ldr r3, [pc, #172] @ (8000818 <MX_TIM3_Init+0xe0>)
800076a: 2212 movs r2, #18
800076c: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
800076e: 4b2a ldr r3, [pc, #168] @ (8000818 <MX_TIM3_Init+0xe0>)
8000770: 2200 movs r2, #0
8000772: 609a str r2, [r3, #8]
htim3.Init.Period = 1600-1;
8000774: 4b28 ldr r3, [pc, #160] @ (8000818 <MX_TIM3_Init+0xe0>)
8000776: f240 623f movw r2, #1599 @ 0x63f
800077a: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800077c: 4b26 ldr r3, [pc, #152] @ (8000818 <MX_TIM3_Init+0xe0>)
800077e: 2200 movs r2, #0
8000780: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
8000782: 4b25 ldr r3, [pc, #148] @ (8000818 <MX_TIM3_Init+0xe0>)
8000784: 2280 movs r2, #128 @ 0x80
8000786: 615a str r2, [r3, #20]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8000788: 4823 ldr r0, [pc, #140] @ (8000818 <MX_TIM3_Init+0xe0>)
800078a: f001 fe27 bl 80023dc <HAL_TIM_Base_Init>
800078e: 4603 mov r3, r0
8000790: 2b00 cmp r3, #0
8000792: d001 beq.n 8000798 <MX_TIM3_Init+0x60>
{
Error_Handler();
8000794: f000 f8ca bl 800092c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000798: f44f 5380 mov.w r3, #4096 @ 0x1000
800079c: 61bb str r3, [r7, #24]
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
800079e: f107 0318 add.w r3, r7, #24
80007a2: 4619 mov r1, r3
80007a4: 481c ldr r0, [pc, #112] @ (8000818 <MX_TIM3_Init+0xe0>)
80007a6: f001 fff9 bl 800279c <HAL_TIM_ConfigClockSource>
80007aa: 4603 mov r3, r0
80007ac: 2b00 cmp r3, #0
80007ae: d001 beq.n 80007b4 <MX_TIM3_Init+0x7c>
{
Error_Handler();
80007b0: f000 f8bc bl 800092c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
80007b4: 4818 ldr r0, [pc, #96] @ (8000818 <MX_TIM3_Init+0xe0>)
80007b6: f001 fe50 bl 800245a <HAL_TIM_PWM_Init>
80007ba: 4603 mov r3, r0
80007bc: 2b00 cmp r3, #0
80007be: d001 beq.n 80007c4 <MX_TIM3_Init+0x8c>
{
Error_Handler();
80007c0: f000 f8b4 bl 800092c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80007c4: 2300 movs r3, #0
80007c6: 613b str r3, [r7, #16]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80007c8: 2300 movs r3, #0
80007ca: 617b str r3, [r7, #20]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
80007cc: f107 0310 add.w r3, r7, #16
80007d0: 4619 mov r1, r3
80007d2: 4811 ldr r0, [pc, #68] @ (8000818 <MX_TIM3_Init+0xe0>)
80007d4: f002 fad0 bl 8002d78 <HAL_TIMEx_MasterConfigSynchronization>
80007d8: 4603 mov r3, r0
80007da: 2b00 cmp r3, #0
80007dc: d001 beq.n 80007e2 <MX_TIM3_Init+0xaa>
{
Error_Handler();
80007de: f000 f8a5 bl 800092c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80007e2: 2360 movs r3, #96 @ 0x60
80007e4: 603b str r3, [r7, #0]
sConfigOC.Pulse = 800-1;
80007e6: f240 331f movw r3, #799 @ 0x31f
80007ea: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80007ec: 2300 movs r3, #0
80007ee: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80007f0: 2300 movs r3, #0
80007f2: 60fb str r3, [r7, #12]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80007f4: 463b mov r3, r7
80007f6: 2200 movs r2, #0
80007f8: 4619 mov r1, r3
80007fa: 4807 ldr r0, [pc, #28] @ (8000818 <MX_TIM3_Init+0xe0>)
80007fc: f001 ff0c bl 8002618 <HAL_TIM_PWM_ConfigChannel>
8000800: 4603 mov r3, r0
8000802: 2b00 cmp r3, #0
8000804: d001 beq.n 800080a <MX_TIM3_Init+0xd2>
{
Error_Handler();
8000806: f000 f891 bl 800092c <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
800080a: 4803 ldr r0, [pc, #12] @ (8000818 <MX_TIM3_Init+0xe0>)
800080c: f000 f924 bl 8000a58 <HAL_TIM_MspPostInit>
}
8000810: bf00 nop
8000812: 3728 adds r7, #40 @ 0x28
8000814: 46bd mov sp, r7
8000816: bd80 pop {r7, pc}
8000818: 20000080 .word 0x20000080
800081c: 40000400 .word 0x40000400
08000820 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000820: b580 push {r7, lr}
8000822: b088 sub sp, #32
8000824: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000826: f107 030c add.w r3, r7, #12
800082a: 2200 movs r2, #0
800082c: 601a str r2, [r3, #0]
800082e: 605a str r2, [r3, #4]
8000830: 609a str r2, [r3, #8]
8000832: 60da str r2, [r3, #12]
8000834: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000836: 4b39 ldr r3, [pc, #228] @ (800091c <MX_GPIO_Init+0xfc>)
8000838: 69db ldr r3, [r3, #28]
800083a: 4a38 ldr r2, [pc, #224] @ (800091c <MX_GPIO_Init+0xfc>)
800083c: f043 0304 orr.w r3, r3, #4
8000840: 61d3 str r3, [r2, #28]
8000842: 4b36 ldr r3, [pc, #216] @ (800091c <MX_GPIO_Init+0xfc>)
8000844: 69db ldr r3, [r3, #28]
8000846: f003 0304 and.w r3, r3, #4
800084a: 60bb str r3, [r7, #8]
800084c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800084e: 4b33 ldr r3, [pc, #204] @ (800091c <MX_GPIO_Init+0xfc>)
8000850: 69db ldr r3, [r3, #28]
8000852: 4a32 ldr r2, [pc, #200] @ (800091c <MX_GPIO_Init+0xfc>)
8000854: f043 0301 orr.w r3, r3, #1
8000858: 61d3 str r3, [r2, #28]
800085a: 4b30 ldr r3, [pc, #192] @ (800091c <MX_GPIO_Init+0xfc>)
800085c: 69db ldr r3, [r3, #28]
800085e: f003 0301 and.w r3, r3, #1
8000862: 607b str r3, [r7, #4]
8000864: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000866: 4b2d ldr r3, [pc, #180] @ (800091c <MX_GPIO_Init+0xfc>)
8000868: 69db ldr r3, [r3, #28]
800086a: 4a2c ldr r2, [pc, #176] @ (800091c <MX_GPIO_Init+0xfc>)
800086c: f043 0302 orr.w r3, r3, #2
8000870: 61d3 str r3, [r2, #28]
8000872: 4b2a ldr r3, [pc, #168] @ (800091c <MX_GPIO_Init+0xfc>)
8000874: 69db ldr r3, [r3, #28]
8000876: f003 0302 and.w r3, r3, #2
800087a: 603b str r3, [r7, #0]
800087c: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET);
800087e: 2200 movs r2, #0
8000880: 2101 movs r1, #1
8000882: 4827 ldr r0, [pc, #156] @ (8000920 <MX_GPIO_Init+0x100>)
8000884: f000 fd44 bl 8001310 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PC0 */
GPIO_InitStruct.Pin = GPIO_PIN_0;
8000888: 2301 movs r3, #1
800088a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800088c: 2301 movs r3, #1
800088e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000890: 2300 movs r3, #0
8000892: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000894: 2300 movs r3, #0
8000896: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000898: f107 030c add.w r3, r7, #12
800089c: 4619 mov r1, r3
800089e: 4820 ldr r0, [pc, #128] @ (8000920 <MX_GPIO_Init+0x100>)
80008a0: f000 fba6 bl 8000ff0 <HAL_GPIO_Init>
/*Configure GPIO pin : PB15 */
GPIO_InitStruct.Pin = GPIO_PIN_15;
80008a4: f44f 4300 mov.w r3, #32768 @ 0x8000
80008a8: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80008aa: 2302 movs r3, #2
80008ac: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008ae: 2300 movs r3, #0
80008b0: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008b2: 2300 movs r3, #0
80008b4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF3_TIM11;
80008b6: 2303 movs r3, #3
80008b8: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80008ba: f107 030c add.w r3, r7, #12
80008be: 4619 mov r1, r3
80008c0: 4818 ldr r0, [pc, #96] @ (8000924 <MX_GPIO_Init+0x104>)
80008c2: f000 fb95 bl 8000ff0 <HAL_GPIO_Init>
/*Configure GPIO pins : PA11 PA12 */
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
80008c6: f44f 53c0 mov.w r3, #6144 @ 0x1800
80008ca: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80008cc: f44f 1388 mov.w r3, #1114112 @ 0x110000
80008d0: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008d2: 2300 movs r3, #0
80008d4: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80008d6: f107 030c add.w r3, r7, #12
80008da: 4619 mov r1, r3
80008dc: 4812 ldr r0, [pc, #72] @ (8000928 <MX_GPIO_Init+0x108>)
80008de: f000 fb87 bl 8000ff0 <HAL_GPIO_Init>
/*Configure GPIO pin : PB7 */
GPIO_InitStruct.Pin = GPIO_PIN_7;
80008e2: 2380 movs r3, #128 @ 0x80
80008e4: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80008e6: 2302 movs r3, #2
80008e8: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008ea: 2300 movs r3, #0
80008ec: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008ee: 2300 movs r3, #0
80008f0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
80008f2: 2302 movs r3, #2
80008f4: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80008f6: f107 030c add.w r3, r7, #12
80008fa: 4619 mov r1, r3
80008fc: 4809 ldr r0, [pc, #36] @ (8000924 <MX_GPIO_Init+0x104>)
80008fe: f000 fb77 bl 8000ff0 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0);
8000902: 2200 movs r2, #0
8000904: 2100 movs r1, #0
8000906: 2028 movs r0, #40 @ 0x28
8000908: f000 fb3b bl 8000f82 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
800090c: 2028 movs r0, #40 @ 0x28
800090e: f000 fb54 bl 8000fba <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000912: bf00 nop
8000914: 3720 adds r7, #32
8000916: 46bd mov sp, r7
8000918: bd80 pop {r7, pc}
800091a: bf00 nop
800091c: 40023800 .word 0x40023800
8000920: 40020800 .word 0x40020800
8000924: 40020400 .word 0x40020400
8000928: 40020000 .word 0x40020000
0800092c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800092c: b480 push {r7}
800092e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000930: b672 cpsid i
}
8000932: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000934: bf00 nop
8000936: e7fd b.n 8000934 <Error_Handler+0x8>
08000938 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000938: b480 push {r7}
800093a: b085 sub sp, #20
800093c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_COMP_CLK_ENABLE();
800093e: 4b14 ldr r3, [pc, #80] @ (8000990 <HAL_MspInit+0x58>)
8000940: 6a5b ldr r3, [r3, #36] @ 0x24
8000942: 4a13 ldr r2, [pc, #76] @ (8000990 <HAL_MspInit+0x58>)
8000944: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8000948: 6253 str r3, [r2, #36] @ 0x24
800094a: 4b11 ldr r3, [pc, #68] @ (8000990 <HAL_MspInit+0x58>)
800094c: 6a5b ldr r3, [r3, #36] @ 0x24
800094e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8000952: 60fb str r3, [r7, #12]
8000954: 68fb ldr r3, [r7, #12]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000956: 4b0e ldr r3, [pc, #56] @ (8000990 <HAL_MspInit+0x58>)
8000958: 6a1b ldr r3, [r3, #32]
800095a: 4a0d ldr r2, [pc, #52] @ (8000990 <HAL_MspInit+0x58>)
800095c: f043 0301 orr.w r3, r3, #1
8000960: 6213 str r3, [r2, #32]
8000962: 4b0b ldr r3, [pc, #44] @ (8000990 <HAL_MspInit+0x58>)
8000964: 6a1b ldr r3, [r3, #32]
8000966: f003 0301 and.w r3, r3, #1
800096a: 60bb str r3, [r7, #8]
800096c: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
800096e: 4b08 ldr r3, [pc, #32] @ (8000990 <HAL_MspInit+0x58>)
8000970: 6a5b ldr r3, [r3, #36] @ 0x24
8000972: 4a07 ldr r2, [pc, #28] @ (8000990 <HAL_MspInit+0x58>)
8000974: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000978: 6253 str r3, [r2, #36] @ 0x24
800097a: 4b05 ldr r3, [pc, #20] @ (8000990 <HAL_MspInit+0x58>)
800097c: 6a5b ldr r3, [r3, #36] @ 0x24
800097e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000982: 607b str r3, [r7, #4]
8000984: 687b ldr r3, [r7, #4]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000986: bf00 nop
8000988: 3714 adds r7, #20
800098a: 46bd mov sp, r7
800098c: bc80 pop {r7}
800098e: 4770 bx lr
8000990: 40023800 .word 0x40023800
08000994 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8000994: b580 push {r7, lr}
8000996: b08a sub sp, #40 @ 0x28
8000998: af00 add r7, sp, #0
800099a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800099c: f107 0314 add.w r3, r7, #20
80009a0: 2200 movs r2, #0
80009a2: 601a str r2, [r3, #0]
80009a4: 605a str r2, [r3, #4]
80009a6: 609a str r2, [r3, #8]
80009a8: 60da str r2, [r3, #12]
80009aa: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
80009ac: 687b ldr r3, [r7, #4]
80009ae: 681b ldr r3, [r3, #0]
80009b0: 4a17 ldr r2, [pc, #92] @ (8000a10 <HAL_SPI_MspInit+0x7c>)
80009b2: 4293 cmp r3, r2
80009b4: d127 bne.n 8000a06 <HAL_SPI_MspInit+0x72>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
80009b6: 4b17 ldr r3, [pc, #92] @ (8000a14 <HAL_SPI_MspInit+0x80>)
80009b8: 6a1b ldr r3, [r3, #32]
80009ba: 4a16 ldr r2, [pc, #88] @ (8000a14 <HAL_SPI_MspInit+0x80>)
80009bc: f443 5380 orr.w r3, r3, #4096 @ 0x1000
80009c0: 6213 str r3, [r2, #32]
80009c2: 4b14 ldr r3, [pc, #80] @ (8000a14 <HAL_SPI_MspInit+0x80>)
80009c4: 6a1b ldr r3, [r3, #32]
80009c6: f403 5380 and.w r3, r3, #4096 @ 0x1000
80009ca: 613b str r3, [r7, #16]
80009cc: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80009ce: 4b11 ldr r3, [pc, #68] @ (8000a14 <HAL_SPI_MspInit+0x80>)
80009d0: 69db ldr r3, [r3, #28]
80009d2: 4a10 ldr r2, [pc, #64] @ (8000a14 <HAL_SPI_MspInit+0x80>)
80009d4: f043 0301 orr.w r3, r3, #1
80009d8: 61d3 str r3, [r2, #28]
80009da: 4b0e ldr r3, [pc, #56] @ (8000a14 <HAL_SPI_MspInit+0x80>)
80009dc: 69db ldr r3, [r3, #28]
80009de: f003 0301 and.w r3, r3, #1
80009e2: 60fb str r3, [r7, #12]
80009e4: 68fb ldr r3, [r7, #12]
/**SPI1 GPIO Configuration
PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO
PA7 ------> SPI1_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
80009e6: 23e0 movs r3, #224 @ 0xe0
80009e8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80009ea: 2302 movs r3, #2
80009ec: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009ee: 2300 movs r3, #0
80009f0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80009f2: 2303 movs r3, #3
80009f4: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
80009f6: 2305 movs r3, #5
80009f8: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80009fa: f107 0314 add.w r3, r7, #20
80009fe: 4619 mov r1, r3
8000a00: 4805 ldr r0, [pc, #20] @ (8000a18 <HAL_SPI_MspInit+0x84>)
8000a02: f000 faf5 bl 8000ff0 <HAL_GPIO_Init>
/* USER CODE END SPI1_MspInit 1 */
}
}
8000a06: bf00 nop
8000a08: 3728 adds r7, #40 @ 0x28
8000a0a: 46bd mov sp, r7
8000a0c: bd80 pop {r7, pc}
8000a0e: bf00 nop
8000a10: 40013000 .word 0x40013000
8000a14: 40023800 .word 0x40023800
8000a18: 40020000 .word 0x40020000
08000a1c <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8000a1c: b480 push {r7}
8000a1e: b085 sub sp, #20
8000a20: af00 add r7, sp, #0
8000a22: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM3)
8000a24: 687b ldr r3, [r7, #4]
8000a26: 681b ldr r3, [r3, #0]
8000a28: 4a09 ldr r2, [pc, #36] @ (8000a50 <HAL_TIM_Base_MspInit+0x34>)
8000a2a: 4293 cmp r3, r2
8000a2c: d10b bne.n 8000a46 <HAL_TIM_Base_MspInit+0x2a>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
8000a2e: 4b09 ldr r3, [pc, #36] @ (8000a54 <HAL_TIM_Base_MspInit+0x38>)
8000a30: 6a5b ldr r3, [r3, #36] @ 0x24
8000a32: 4a08 ldr r2, [pc, #32] @ (8000a54 <HAL_TIM_Base_MspInit+0x38>)
8000a34: f043 0302 orr.w r3, r3, #2
8000a38: 6253 str r3, [r2, #36] @ 0x24
8000a3a: 4b06 ldr r3, [pc, #24] @ (8000a54 <HAL_TIM_Base_MspInit+0x38>)
8000a3c: 6a5b ldr r3, [r3, #36] @ 0x24
8000a3e: f003 0302 and.w r3, r3, #2
8000a42: 60fb str r3, [r7, #12]
8000a44: 68fb ldr r3, [r7, #12]
/* USER CODE END TIM3_MspInit 1 */
}
}
8000a46: bf00 nop
8000a48: 3714 adds r7, #20
8000a4a: 46bd mov sp, r7
8000a4c: bc80 pop {r7}
8000a4e: 4770 bx lr
8000a50: 40000400 .word 0x40000400
8000a54: 40023800 .word 0x40023800
08000a58 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8000a58: b580 push {r7, lr}
8000a5a: b088 sub sp, #32
8000a5c: af00 add r7, sp, #0
8000a5e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000a60: f107 030c add.w r3, r7, #12
8000a64: 2200 movs r2, #0
8000a66: 601a str r2, [r3, #0]
8000a68: 605a str r2, [r3, #4]
8000a6a: 609a str r2, [r3, #8]
8000a6c: 60da str r2, [r3, #12]
8000a6e: 611a str r2, [r3, #16]
if(htim->Instance==TIM3)
8000a70: 687b ldr r3, [r7, #4]
8000a72: 681b ldr r3, [r3, #0]
8000a74: 4a11 ldr r2, [pc, #68] @ (8000abc <HAL_TIM_MspPostInit+0x64>)
8000a76: 4293 cmp r3, r2
8000a78: d11b bne.n 8000ab2 <HAL_TIM_MspPostInit+0x5a>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000a7a: 4b11 ldr r3, [pc, #68] @ (8000ac0 <HAL_TIM_MspPostInit+0x68>)
8000a7c: 69db ldr r3, [r3, #28]
8000a7e: 4a10 ldr r2, [pc, #64] @ (8000ac0 <HAL_TIM_MspPostInit+0x68>)
8000a80: f043 0304 orr.w r3, r3, #4
8000a84: 61d3 str r3, [r2, #28]
8000a86: 4b0e ldr r3, [pc, #56] @ (8000ac0 <HAL_TIM_MspPostInit+0x68>)
8000a88: 69db ldr r3, [r3, #28]
8000a8a: f003 0304 and.w r3, r3, #4
8000a8e: 60bb str r3, [r7, #8]
8000a90: 68bb ldr r3, [r7, #8]
/**TIM3 GPIO Configuration
PC6 ------> TIM3_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
8000a92: 2340 movs r3, #64 @ 0x40
8000a94: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a96: 2302 movs r3, #2
8000a98: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a9a: 2300 movs r3, #0
8000a9c: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a9e: 2300 movs r3, #0
8000aa0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
8000aa2: 2302 movs r3, #2
8000aa4: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000aa6: f107 030c add.w r3, r7, #12
8000aaa: 4619 mov r1, r3
8000aac: 4805 ldr r0, [pc, #20] @ (8000ac4 <HAL_TIM_MspPostInit+0x6c>)
8000aae: f000 fa9f bl 8000ff0 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
8000ab2: bf00 nop
8000ab4: 3720 adds r7, #32
8000ab6: 46bd mov sp, r7
8000ab8: bd80 pop {r7, pc}
8000aba: bf00 nop
8000abc: 40000400 .word 0x40000400
8000ac0: 40023800 .word 0x40023800
8000ac4: 40020800 .word 0x40020800
08000ac8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000ac8: b480 push {r7}
8000aca: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000acc: bf00 nop
8000ace: e7fd b.n 8000acc <NMI_Handler+0x4>
08000ad0 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000ad0: b480 push {r7}
8000ad2: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000ad4: bf00 nop
8000ad6: e7fd b.n 8000ad4 <HardFault_Handler+0x4>
08000ad8 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000ad8: b480 push {r7}
8000ada: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000adc: bf00 nop
8000ade: e7fd b.n 8000adc <MemManage_Handler+0x4>
08000ae0 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000ae0: b480 push {r7}
8000ae2: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000ae4: bf00 nop
8000ae6: e7fd b.n 8000ae4 <BusFault_Handler+0x4>
08000ae8 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000ae8: b480 push {r7}
8000aea: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000aec: bf00 nop
8000aee: e7fd b.n 8000aec <UsageFault_Handler+0x4>
08000af0 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000af0: b480 push {r7}
8000af2: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000af4: bf00 nop
8000af6: 46bd mov sp, r7
8000af8: bc80 pop {r7}
8000afa: 4770 bx lr
08000afc <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000afc: b480 push {r7}
8000afe: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000b00: bf00 nop
8000b02: 46bd mov sp, r7
8000b04: bc80 pop {r7}
8000b06: 4770 bx lr
08000b08 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000b08: b480 push {r7}
8000b0a: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000b0c: bf00 nop
8000b0e: 46bd mov sp, r7
8000b10: bc80 pop {r7}
8000b12: 4770 bx lr
08000b14 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000b14: b580 push {r7, lr}
8000b16: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000b18: f000 f91e bl 8000d58 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000b1c: bf00 nop
8000b1e: bd80 pop {r7, pc}
08000b20 <EXTI15_10_IRQHandler>:
/**
* @brief This function handles EXTI line[15:10] interrupts.
*/
void EXTI15_10_IRQHandler(void)
{
8000b20: b580 push {r7, lr}
8000b22: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI15_10_IRQn 0 */
/* USER CODE END EXTI15_10_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
8000b24: f44f 6000 mov.w r0, #2048 @ 0x800
8000b28: f000 fc0a bl 8001340 <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
8000b2c: f44f 5080 mov.w r0, #4096 @ 0x1000
8000b30: f000 fc06 bl 8001340 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI15_10_IRQn 1 */
/* USER CODE END EXTI15_10_IRQn 1 */
}
8000b34: bf00 nop
8000b36: bd80 pop {r7, pc}
08000b38 <SystemInit>:
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
8000b38: b480 push {r7}
8000b3a: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000b3c: bf00 nop
8000b3e: 46bd mov sp, r7
8000b40: bc80 pop {r7}
8000b42: 4770 bx lr
08000b44 <Reset_Handler>:
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8000b44: f7ff fff8 bl 8000b38 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000b48: 480b ldr r0, [pc, #44] @ (8000b78 <LoopFillZerobss+0xe>)
ldr r1, =_edata
8000b4a: 490c ldr r1, [pc, #48] @ (8000b7c <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8000b4c: 4a0c ldr r2, [pc, #48] @ (8000b80 <LoopFillZerobss+0x16>)
movs r3, #0
8000b4e: 2300 movs r3, #0
b LoopCopyDataInit
8000b50: e002 b.n 8000b58 <LoopCopyDataInit>
08000b52 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000b52: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000b54: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000b56: 3304 adds r3, #4
08000b58 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000b58: 18c4 adds r4, r0, r3
cmp r4, r1
8000b5a: 428c cmp r4, r1
bcc CopyDataInit
8000b5c: d3f9 bcc.n 8000b52 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000b5e: 4a09 ldr r2, [pc, #36] @ (8000b84 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
8000b60: 4c09 ldr r4, [pc, #36] @ (8000b88 <LoopFillZerobss+0x1e>)
movs r3, #0
8000b62: 2300 movs r3, #0
b LoopFillZerobss
8000b64: e001 b.n 8000b6a <LoopFillZerobss>
08000b66 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000b66: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000b68: 3204 adds r2, #4
08000b6a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000b6a: 42a2 cmp r2, r4
bcc FillZerobss
8000b6c: d3fb bcc.n 8000b66 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000b6e: f002 f969 bl 8002e44 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000b72: f7ff fcff bl 8000574 <main>
bx lr
8000b76: 4770 bx lr
ldr r0, =_sdata
8000b78: 20000000 .word 0x20000000
ldr r1, =_edata
8000b7c: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000b80: 08002ee0 .word 0x08002ee0
ldr r2, =_sbss
8000b84: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000b88: 200000c4 .word 0x200000c4
08000b8c <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000b8c: e7fe b.n 8000b8c <ADC1_IRQHandler>
08000b8e <MAX7219_Init>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Init (void)
{
8000b8e: b580 push {r7, lr}
8000b90: af00 add r7, sp, #0
// configure "LOAD" as output
MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits
8000b92: 2107 movs r1, #7
8000b94: 200b movs r0, #11
8000b96: f000 f85d bl 8000c54 <MAX7219_Write>
MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits
8000b9a: 2100 movs r1, #0
8000b9c: 2009 movs r0, #9
8000b9e: f000 f859 bl 8000c54 <MAX7219_Write>
MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown)
8000ba2: f000 f809 bl 8000bb8 <MAX7219_ShutdownStop>
MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode)
8000ba6: f000 f80f bl 8000bc8 <MAX7219_DisplayTestStop>
MAX7219_Clear(); // clear all digits
8000baa: f000 f827 bl 8000bfc <MAX7219_Clear>
MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity
8000bae: 200f movs r0, #15
8000bb0: f000 f812 bl 8000bd8 <MAX7219_SetBrightness>
}
8000bb4: bf00 nop
8000bb6: bd80 pop {r7, pc}
08000bb8 <MAX7219_ShutdownStop>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_ShutdownStop (void)
{
8000bb8: b580 push {r7, lr}
8000bba: af00 add r7, sp, #0
MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode
8000bbc: 2101 movs r1, #1
8000bbe: 200c movs r0, #12
8000bc0: f000 f848 bl 8000c54 <MAX7219_Write>
}
8000bc4: bf00 nop
8000bc6: bd80 pop {r7, pc}
08000bc8 <MAX7219_DisplayTestStop>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_DisplayTestStop (void)
{
8000bc8: b580 push {r7, lr}
8000bca: af00 add r7, sp, #0
MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode
8000bcc: 2100 movs r1, #0
8000bce: 200f movs r0, #15
8000bd0: f000 f840 bl 8000c54 <MAX7219_Write>
}
8000bd4: bf00 nop
8000bd6: bd80 pop {r7, pc}
08000bd8 <MAX7219_SetBrightness>:
* Arguments : brightness (0-15)
* Returns : none
*********************************************************************************************************
*/
void MAX7219_SetBrightness (char brightness)
{
8000bd8: b580 push {r7, lr}
8000bda: b082 sub sp, #8
8000bdc: af00 add r7, sp, #0
8000bde: 4603 mov r3, r0
8000be0: 71fb strb r3, [r7, #7]
brightness &= 0x0f; // mask off extra bits
8000be2: 79fb ldrb r3, [r7, #7]
8000be4: f003 030f and.w r3, r3, #15
8000be8: 71fb strb r3, [r7, #7]
MAX7219_Write(REG_INTENSITY, brightness); // set brightness
8000bea: 79fb ldrb r3, [r7, #7]
8000bec: 4619 mov r1, r3
8000bee: 200a movs r0, #10
8000bf0: f000 f830 bl 8000c54 <MAX7219_Write>
}
8000bf4: bf00 nop
8000bf6: 3708 adds r7, #8
8000bf8: 46bd mov sp, r7
8000bfa: bd80 pop {r7, pc}
08000bfc <MAX7219_Clear>:
* Arguments : none
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Clear (void)
{
8000bfc: b580 push {r7, lr}
8000bfe: b082 sub sp, #8
8000c00: af00 add r7, sp, #0
char i;
for (i=0; i < 8; i++)
8000c02: 2300 movs r3, #0
8000c04: 71fb strb r3, [r7, #7]
8000c06: e007 b.n 8000c18 <MAX7219_Clear+0x1c>
MAX7219_Write(i, 0x00); // turn all segments off
8000c08: 79fb ldrb r3, [r7, #7]
8000c0a: 2100 movs r1, #0
8000c0c: 4618 mov r0, r3
8000c0e: f000 f821 bl 8000c54 <MAX7219_Write>
for (i=0; i < 8; i++)
8000c12: 79fb ldrb r3, [r7, #7]
8000c14: 3301 adds r3, #1
8000c16: 71fb strb r3, [r7, #7]
8000c18: 79fb ldrb r3, [r7, #7]
8000c1a: 2b07 cmp r3, #7
8000c1c: d9f4 bls.n 8000c08 <MAX7219_Clear+0xc>
}
8000c1e: bf00 nop
8000c20: bf00 nop
8000c22: 3708 adds r7, #8
8000c24: 46bd mov sp, r7
8000c26: bd80 pop {r7, pc}
08000c28 <MAX7219_DisplayChar>:
* character = character to display (0-9, A-Z)
* Returns : none
*********************************************************************************************************
*/
void MAX7219_DisplayChar(char digit, char character)
{
8000c28: b580 push {r7, lr}
8000c2a: b082 sub sp, #8
8000c2c: af00 add r7, sp, #0
8000c2e: 4603 mov r3, r0
8000c30: 460a mov r2, r1
8000c32: 71fb strb r3, [r7, #7]
8000c34: 4613 mov r3, r2
8000c36: 71bb strb r3, [r7, #6]
//MAX7219_Write(digit, MAX7219_LookupCode(character));
MAX7219_Write(digit, conv_7seg[character]);
8000c38: 79bb ldrb r3, [r7, #6]
8000c3a: 4a05 ldr r2, [pc, #20] @ (8000c50 <MAX7219_DisplayChar+0x28>)
8000c3c: 5cd2 ldrb r2, [r2, r3]
8000c3e: 79fb ldrb r3, [r7, #7]
8000c40: 4611 mov r1, r2
8000c42: 4618 mov r0, r3
8000c44: f000 f806 bl 8000c54 <MAX7219_Write>
}
8000c48: bf00 nop
8000c4a: 3708 adds r7, #8
8000c4c: 46bd mov sp, r7
8000c4e: bd80 pop {r7, pc}
8000c50: 08002ec0 .word 0x08002ec0
08000c54 <MAX7219_Write>:
* dataout = data to write to MAX7219
* Returns : none
*********************************************************************************************************
*/
void MAX7219_Write (unsigned char reg_number, unsigned char dataout)
{
8000c54: b580 push {r7, lr}
8000c56: b082 sub sp, #8
8000c58: af00 add r7, sp, #0
8000c5a: 4603 mov r3, r0
8000c5c: 460a mov r2, r1
8000c5e: 71fb strb r3, [r7, #7]
8000c60: 4613 mov r3, r2
8000c62: 71bb strb r3, [r7, #6]
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin
8000c64: 4b09 ldr r3, [pc, #36] @ (8000c8c <MAX7219_Write+0x38>)
8000c66: f44f 3280 mov.w r2, #65536 @ 0x10000
8000c6a: 619a str r2, [r3, #24]
MAX7219_SendByte(reg_number); // write register number to MAX7219
8000c6c: 79fb ldrb r3, [r7, #7]
8000c6e: 4618 mov r0, r3
8000c70: f000 f80e bl 8000c90 <MAX7219_SendByte>
MAX7219_SendByte(dataout); // write data to MAX7219
8000c74: 79bb ldrb r3, [r7, #6]
8000c76: 4618 mov r0, r3
8000c78: f000 f80a bl 8000c90 <MAX7219_SendByte>
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data
8000c7c: 4b03 ldr r3, [pc, #12] @ (8000c8c <MAX7219_Write+0x38>)
8000c7e: 2201 movs r2, #1
8000c80: 619a str r2, [r3, #24]
}
8000c82: bf00 nop
8000c84: 3708 adds r7, #8
8000c86: 46bd mov sp, r7
8000c88: bd80 pop {r7, pc}
8000c8a: bf00 nop
8000c8c: 40020800 .word 0x40020800
08000c90 <MAX7219_SendByte>:
* Returns : none
*********************************************************************************************************
*/
static void MAX7219_SendByte (unsigned char dataout)
{
8000c90: b580 push {r7, lr}
8000c92: b082 sub sp, #8
8000c94: af00 add r7, sp, #0
8000c96: 4603 mov r3, r0
8000c98: 71fb strb r3, [r7, #7]
HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000);
8000c9a: 1df9 adds r1, r7, #7
8000c9c: f44f 737a mov.w r3, #1000 @ 0x3e8
8000ca0: 2201 movs r2, #1
8000ca2: 4803 ldr r0, [pc, #12] @ (8000cb0 <MAX7219_SendByte+0x20>)
8000ca4: f001 f979 bl 8001f9a <HAL_SPI_Transmit>
}
8000ca8: bf00 nop
8000caa: 3708 adds r7, #8
8000cac: 46bd mov sp, r7
8000cae: bd80 pop {r7, pc}
8000cb0: 20000028 .word 0x20000028
08000cb4 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000cb4: b580 push {r7, lr}
8000cb6: b082 sub sp, #8
8000cb8: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8000cba: 2300 movs r3, #0
8000cbc: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000cbe: 2003 movs r0, #3
8000cc0: f000 f954 bl 8000f6c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8000cc4: 200f movs r0, #15
8000cc6: f000 f80d bl 8000ce4 <HAL_InitTick>
8000cca: 4603 mov r3, r0
8000ccc: 2b00 cmp r3, #0
8000cce: d002 beq.n 8000cd6 <HAL_Init+0x22>
{
status = HAL_ERROR;
8000cd0: 2301 movs r3, #1
8000cd2: 71fb strb r3, [r7, #7]
8000cd4: e001 b.n 8000cda <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8000cd6: f7ff fe2f bl 8000938 <HAL_MspInit>
}
/* Return function status */
return status;
8000cda: 79fb ldrb r3, [r7, #7]
}
8000cdc: 4618 mov r0, r3
8000cde: 3708 adds r7, #8
8000ce0: 46bd mov sp, r7
8000ce2: bd80 pop {r7, pc}
08000ce4 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000ce4: b580 push {r7, lr}
8000ce6: b084 sub sp, #16
8000ce8: af00 add r7, sp, #0
8000cea: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000cec: 2300 movs r3, #0
8000cee: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8000cf0: 4b16 ldr r3, [pc, #88] @ (8000d4c <HAL_InitTick+0x68>)
8000cf2: 681b ldr r3, [r3, #0]
8000cf4: 2b00 cmp r3, #0
8000cf6: d022 beq.n 8000d3e <HAL_InitTick+0x5a>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8000cf8: 4b15 ldr r3, [pc, #84] @ (8000d50 <HAL_InitTick+0x6c>)
8000cfa: 681a ldr r2, [r3, #0]
8000cfc: 4b13 ldr r3, [pc, #76] @ (8000d4c <HAL_InitTick+0x68>)
8000cfe: 681b ldr r3, [r3, #0]
8000d00: f44f 717a mov.w r1, #1000 @ 0x3e8
8000d04: fbb1 f3f3 udiv r3, r1, r3
8000d08: fbb2 f3f3 udiv r3, r2, r3
8000d0c: 4618 mov r0, r3
8000d0e: f000 f962 bl 8000fd6 <HAL_SYSTICK_Config>
8000d12: 4603 mov r3, r0
8000d14: 2b00 cmp r3, #0
8000d16: d10f bne.n 8000d38 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 2b0f cmp r3, #15
8000d1c: d809 bhi.n 8000d32 <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000d1e: 2200 movs r2, #0
8000d20: 6879 ldr r1, [r7, #4]
8000d22: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000d26: f000 f92c bl 8000f82 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000d2a: 4a0a ldr r2, [pc, #40] @ (8000d54 <HAL_InitTick+0x70>)
8000d2c: 687b ldr r3, [r7, #4]
8000d2e: 6013 str r3, [r2, #0]
8000d30: e007 b.n 8000d42 <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8000d32: 2301 movs r3, #1
8000d34: 73fb strb r3, [r7, #15]
8000d36: e004 b.n 8000d42 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8000d38: 2301 movs r3, #1
8000d3a: 73fb strb r3, [r7, #15]
8000d3c: e001 b.n 8000d42 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8000d3e: 2301 movs r3, #1
8000d40: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8000d42: 7bfb ldrb r3, [r7, #15]
}
8000d44: 4618 mov r0, r3
8000d46: 3710 adds r7, #16
8000d48: 46bd mov sp, r7
8000d4a: bd80 pop {r7, pc}
8000d4c: 20000008 .word 0x20000008
8000d50: 20000000 .word 0x20000000
8000d54: 20000004 .word 0x20000004
08000d58 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000d58: b480 push {r7}
8000d5a: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000d5c: 4b05 ldr r3, [pc, #20] @ (8000d74 <HAL_IncTick+0x1c>)
8000d5e: 681a ldr r2, [r3, #0]
8000d60: 4b05 ldr r3, [pc, #20] @ (8000d78 <HAL_IncTick+0x20>)
8000d62: 681b ldr r3, [r3, #0]
8000d64: 4413 add r3, r2
8000d66: 4a03 ldr r2, [pc, #12] @ (8000d74 <HAL_IncTick+0x1c>)
8000d68: 6013 str r3, [r2, #0]
}
8000d6a: bf00 nop
8000d6c: 46bd mov sp, r7
8000d6e: bc80 pop {r7}
8000d70: 4770 bx lr
8000d72: bf00 nop
8000d74: 200000c0 .word 0x200000c0
8000d78: 20000008 .word 0x20000008
08000d7c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000d7c: b480 push {r7}
8000d7e: af00 add r7, sp, #0
return uwTick;
8000d80: 4b02 ldr r3, [pc, #8] @ (8000d8c <HAL_GetTick+0x10>)
8000d82: 681b ldr r3, [r3, #0]
}
8000d84: 4618 mov r0, r3
8000d86: 46bd mov sp, r7
8000d88: bc80 pop {r7}
8000d8a: 4770 bx lr
8000d8c: 200000c0 .word 0x200000c0
08000d90 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000d90: b580 push {r7, lr}
8000d92: b084 sub sp, #16
8000d94: af00 add r7, sp, #0
8000d96: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000d98: f7ff fff0 bl 8000d7c <HAL_GetTick>
8000d9c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000d9e: 687b ldr r3, [r7, #4]
8000da0: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
8000da2: 68fb ldr r3, [r7, #12]
8000da4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8000da8: d004 beq.n 8000db4 <HAL_Delay+0x24>
{
wait += (uint32_t)(uwTickFreq);
8000daa: 4b09 ldr r3, [pc, #36] @ (8000dd0 <HAL_Delay+0x40>)
8000dac: 681b ldr r3, [r3, #0]
8000dae: 68fa ldr r2, [r7, #12]
8000db0: 4413 add r3, r2
8000db2: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8000db4: bf00 nop
8000db6: f7ff ffe1 bl 8000d7c <HAL_GetTick>
8000dba: 4602 mov r2, r0
8000dbc: 68bb ldr r3, [r7, #8]
8000dbe: 1ad3 subs r3, r2, r3
8000dc0: 68fa ldr r2, [r7, #12]
8000dc2: 429a cmp r2, r3
8000dc4: d8f7 bhi.n 8000db6 <HAL_Delay+0x26>
{
}
}
8000dc6: bf00 nop
8000dc8: bf00 nop
8000dca: 3710 adds r7, #16
8000dcc: 46bd mov sp, r7
8000dce: bd80 pop {r7, pc}
8000dd0: 20000008 .word 0x20000008
08000dd4 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000dd4: b480 push {r7}
8000dd6: b085 sub sp, #20
8000dd8: af00 add r7, sp, #0
8000dda: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000ddc: 687b ldr r3, [r7, #4]
8000dde: f003 0307 and.w r3, r3, #7
8000de2: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000de4: 4b0c ldr r3, [pc, #48] @ (8000e18 <__NVIC_SetPriorityGrouping+0x44>)
8000de6: 68db ldr r3, [r3, #12]
8000de8: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000dea: 68ba ldr r2, [r7, #8]
8000dec: f64f 03ff movw r3, #63743 @ 0xf8ff
8000df0: 4013 ands r3, r2
8000df2: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000df4: 68fb ldr r3, [r7, #12]
8000df6: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000df8: 68bb ldr r3, [r7, #8]
8000dfa: 4313 orrs r3, r2
reg_value = (reg_value |
8000dfc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8000e00: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000e04: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000e06: 4a04 ldr r2, [pc, #16] @ (8000e18 <__NVIC_SetPriorityGrouping+0x44>)
8000e08: 68bb ldr r3, [r7, #8]
8000e0a: 60d3 str r3, [r2, #12]
}
8000e0c: bf00 nop
8000e0e: 3714 adds r7, #20
8000e10: 46bd mov sp, r7
8000e12: bc80 pop {r7}
8000e14: 4770 bx lr
8000e16: bf00 nop
8000e18: e000ed00 .word 0xe000ed00
08000e1c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000e1c: b480 push {r7}
8000e1e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000e20: 4b04 ldr r3, [pc, #16] @ (8000e34 <__NVIC_GetPriorityGrouping+0x18>)
8000e22: 68db ldr r3, [r3, #12]
8000e24: 0a1b lsrs r3, r3, #8
8000e26: f003 0307 and.w r3, r3, #7
}
8000e2a: 4618 mov r0, r3
8000e2c: 46bd mov sp, r7
8000e2e: bc80 pop {r7}
8000e30: 4770 bx lr
8000e32: bf00 nop
8000e34: e000ed00 .word 0xe000ed00
08000e38 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000e38: b480 push {r7}
8000e3a: b083 sub sp, #12
8000e3c: af00 add r7, sp, #0
8000e3e: 4603 mov r3, r0
8000e40: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000e42: f997 3007 ldrsb.w r3, [r7, #7]
8000e46: 2b00 cmp r3, #0
8000e48: db0b blt.n 8000e62 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8000e4a: 79fb ldrb r3, [r7, #7]
8000e4c: f003 021f and.w r2, r3, #31
8000e50: 4906 ldr r1, [pc, #24] @ (8000e6c <__NVIC_EnableIRQ+0x34>)
8000e52: f997 3007 ldrsb.w r3, [r7, #7]
8000e56: 095b lsrs r3, r3, #5
8000e58: 2001 movs r0, #1
8000e5a: fa00 f202 lsl.w r2, r0, r2
8000e5e: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8000e62: bf00 nop
8000e64: 370c adds r7, #12
8000e66: 46bd mov sp, r7
8000e68: bc80 pop {r7}
8000e6a: 4770 bx lr
8000e6c: e000e100 .word 0xe000e100
08000e70 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000e70: b480 push {r7}
8000e72: b083 sub sp, #12
8000e74: af00 add r7, sp, #0
8000e76: 4603 mov r3, r0
8000e78: 6039 str r1, [r7, #0]
8000e7a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000e7c: f997 3007 ldrsb.w r3, [r7, #7]
8000e80: 2b00 cmp r3, #0
8000e82: db0a blt.n 8000e9a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000e84: 683b ldr r3, [r7, #0]
8000e86: b2da uxtb r2, r3
8000e88: 490c ldr r1, [pc, #48] @ (8000ebc <__NVIC_SetPriority+0x4c>)
8000e8a: f997 3007 ldrsb.w r3, [r7, #7]
8000e8e: 0112 lsls r2, r2, #4
8000e90: b2d2 uxtb r2, r2
8000e92: 440b add r3, r1
8000e94: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000e98: e00a b.n 8000eb0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000e9a: 683b ldr r3, [r7, #0]
8000e9c: b2da uxtb r2, r3
8000e9e: 4908 ldr r1, [pc, #32] @ (8000ec0 <__NVIC_SetPriority+0x50>)
8000ea0: 79fb ldrb r3, [r7, #7]
8000ea2: f003 030f and.w r3, r3, #15
8000ea6: 3b04 subs r3, #4
8000ea8: 0112 lsls r2, r2, #4
8000eaa: b2d2 uxtb r2, r2
8000eac: 440b add r3, r1
8000eae: 761a strb r2, [r3, #24]
}
8000eb0: bf00 nop
8000eb2: 370c adds r7, #12
8000eb4: 46bd mov sp, r7
8000eb6: bc80 pop {r7}
8000eb8: 4770 bx lr
8000eba: bf00 nop
8000ebc: e000e100 .word 0xe000e100
8000ec0: e000ed00 .word 0xe000ed00
08000ec4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000ec4: b480 push {r7}
8000ec6: b089 sub sp, #36 @ 0x24
8000ec8: af00 add r7, sp, #0
8000eca: 60f8 str r0, [r7, #12]
8000ecc: 60b9 str r1, [r7, #8]
8000ece: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000ed0: 68fb ldr r3, [r7, #12]
8000ed2: f003 0307 and.w r3, r3, #7
8000ed6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000ed8: 69fb ldr r3, [r7, #28]
8000eda: f1c3 0307 rsb r3, r3, #7
8000ede: 2b04 cmp r3, #4
8000ee0: bf28 it cs
8000ee2: 2304 movcs r3, #4
8000ee4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000ee6: 69fb ldr r3, [r7, #28]
8000ee8: 3304 adds r3, #4
8000eea: 2b06 cmp r3, #6
8000eec: d902 bls.n 8000ef4 <NVIC_EncodePriority+0x30>
8000eee: 69fb ldr r3, [r7, #28]
8000ef0: 3b03 subs r3, #3
8000ef2: e000 b.n 8000ef6 <NVIC_EncodePriority+0x32>
8000ef4: 2300 movs r3, #0
8000ef6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000ef8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8000efc: 69bb ldr r3, [r7, #24]
8000efe: fa02 f303 lsl.w r3, r2, r3
8000f02: 43da mvns r2, r3
8000f04: 68bb ldr r3, [r7, #8]
8000f06: 401a ands r2, r3
8000f08: 697b ldr r3, [r7, #20]
8000f0a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000f0c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8000f10: 697b ldr r3, [r7, #20]
8000f12: fa01 f303 lsl.w r3, r1, r3
8000f16: 43d9 mvns r1, r3
8000f18: 687b ldr r3, [r7, #4]
8000f1a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000f1c: 4313 orrs r3, r2
);
}
8000f1e: 4618 mov r0, r3
8000f20: 3724 adds r7, #36 @ 0x24
8000f22: 46bd mov sp, r7
8000f24: bc80 pop {r7}
8000f26: 4770 bx lr
08000f28 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000f28: b580 push {r7, lr}
8000f2a: b082 sub sp, #8
8000f2c: af00 add r7, sp, #0
8000f2e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000f30: 687b ldr r3, [r7, #4]
8000f32: 3b01 subs r3, #1
8000f34: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8000f38: d301 bcc.n 8000f3e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000f3a: 2301 movs r3, #1
8000f3c: e00f b.n 8000f5e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000f3e: 4a0a ldr r2, [pc, #40] @ (8000f68 <SysTick_Config+0x40>)
8000f40: 687b ldr r3, [r7, #4]
8000f42: 3b01 subs r3, #1
8000f44: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000f46: 210f movs r1, #15
8000f48: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000f4c: f7ff ff90 bl 8000e70 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000f50: 4b05 ldr r3, [pc, #20] @ (8000f68 <SysTick_Config+0x40>)
8000f52: 2200 movs r2, #0
8000f54: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000f56: 4b04 ldr r3, [pc, #16] @ (8000f68 <SysTick_Config+0x40>)
8000f58: 2207 movs r2, #7
8000f5a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000f5c: 2300 movs r3, #0
}
8000f5e: 4618 mov r0, r3
8000f60: 3708 adds r7, #8
8000f62: 46bd mov sp, r7
8000f64: bd80 pop {r7, pc}
8000f66: bf00 nop
8000f68: e000e010 .word 0xe000e010
08000f6c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000f6c: b580 push {r7, lr}
8000f6e: b082 sub sp, #8
8000f70: af00 add r7, sp, #0
8000f72: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000f74: 6878 ldr r0, [r7, #4]
8000f76: f7ff ff2d bl 8000dd4 <__NVIC_SetPriorityGrouping>
}
8000f7a: bf00 nop
8000f7c: 3708 adds r7, #8
8000f7e: 46bd mov sp, r7
8000f80: bd80 pop {r7, pc}
08000f82 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000f82: b580 push {r7, lr}
8000f84: b086 sub sp, #24
8000f86: af00 add r7, sp, #0
8000f88: 4603 mov r3, r0
8000f8a: 60b9 str r1, [r7, #8]
8000f8c: 607a str r2, [r7, #4]
8000f8e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8000f90: 2300 movs r3, #0
8000f92: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000f94: f7ff ff42 bl 8000e1c <__NVIC_GetPriorityGrouping>
8000f98: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000f9a: 687a ldr r2, [r7, #4]
8000f9c: 68b9 ldr r1, [r7, #8]
8000f9e: 6978 ldr r0, [r7, #20]
8000fa0: f7ff ff90 bl 8000ec4 <NVIC_EncodePriority>
8000fa4: 4602 mov r2, r0
8000fa6: f997 300f ldrsb.w r3, [r7, #15]
8000faa: 4611 mov r1, r2
8000fac: 4618 mov r0, r3
8000fae: f7ff ff5f bl 8000e70 <__NVIC_SetPriority>
}
8000fb2: bf00 nop
8000fb4: 3718 adds r7, #24
8000fb6: 46bd mov sp, r7
8000fb8: bd80 pop {r7, pc}
08000fba <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000fba: b580 push {r7, lr}
8000fbc: b082 sub sp, #8
8000fbe: af00 add r7, sp, #0
8000fc0: 4603 mov r3, r0
8000fc2: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8000fc4: f997 3007 ldrsb.w r3, [r7, #7]
8000fc8: 4618 mov r0, r3
8000fca: f7ff ff35 bl 8000e38 <__NVIC_EnableIRQ>
}
8000fce: bf00 nop
8000fd0: 3708 adds r7, #8
8000fd2: 46bd mov sp, r7
8000fd4: bd80 pop {r7, pc}
08000fd6 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000fd6: b580 push {r7, lr}
8000fd8: b082 sub sp, #8
8000fda: af00 add r7, sp, #0
8000fdc: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000fde: 6878 ldr r0, [r7, #4]
8000fe0: f7ff ffa2 bl 8000f28 <SysTick_Config>
8000fe4: 4603 mov r3, r0
}
8000fe6: 4618 mov r0, r3
8000fe8: 3708 adds r7, #8
8000fea: 46bd mov sp, r7
8000fec: bd80 pop {r7, pc}
...
08000ff0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000ff0: b480 push {r7}
8000ff2: b087 sub sp, #28
8000ff4: af00 add r7, sp, #0
8000ff6: 6078 str r0, [r7, #4]
8000ff8: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
8000ffa: 2300 movs r3, #0
8000ffc: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
8000ffe: 2300 movs r3, #0
8001000: 60fb str r3, [r7, #12]
uint32_t temp = 0x00;
8001002: 2300 movs r3, #0
8001004: 613b str r3, [r7, #16]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0)
8001006: e160 b.n 80012ca <HAL_GPIO_Init+0x2da>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
8001008: 683b ldr r3, [r7, #0]
800100a: 681a ldr r2, [r3, #0]
800100c: 2101 movs r1, #1
800100e: 697b ldr r3, [r7, #20]
8001010: fa01 f303 lsl.w r3, r1, r3
8001014: 4013 ands r3, r2
8001016: 60fb str r3, [r7, #12]
if (iocurrent)
8001018: 68fb ldr r3, [r7, #12]
800101a: 2b00 cmp r3, #0
800101c: f000 8152 beq.w 80012c4 <HAL_GPIO_Init+0x2d4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001020: 683b ldr r3, [r7, #0]
8001022: 685b ldr r3, [r3, #4]
8001024: f003 0303 and.w r3, r3, #3
8001028: 2b01 cmp r3, #1
800102a: d005 beq.n 8001038 <HAL_GPIO_Init+0x48>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
800102c: 683b ldr r3, [r7, #0]
800102e: 685b ldr r3, [r3, #4]
8001030: f003 0303 and.w r3, r3, #3
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8001034: 2b02 cmp r3, #2
8001036: d130 bne.n 800109a <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001038: 687b ldr r3, [r7, #4]
800103a: 689b ldr r3, [r3, #8]
800103c: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
800103e: 697b ldr r3, [r7, #20]
8001040: 005b lsls r3, r3, #1
8001042: 2203 movs r2, #3
8001044: fa02 f303 lsl.w r3, r2, r3
8001048: 43db mvns r3, r3
800104a: 693a ldr r2, [r7, #16]
800104c: 4013 ands r3, r2
800104e: 613b str r3, [r7, #16]
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
8001050: 683b ldr r3, [r7, #0]
8001052: 68da ldr r2, [r3, #12]
8001054: 697b ldr r3, [r7, #20]
8001056: 005b lsls r3, r3, #1
8001058: fa02 f303 lsl.w r3, r2, r3
800105c: 693a ldr r2, [r7, #16]
800105e: 4313 orrs r3, r2
8001060: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8001062: 687b ldr r3, [r7, #4]
8001064: 693a ldr r2, [r7, #16]
8001066: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001068: 687b ldr r3, [r7, #4]
800106a: 685b ldr r3, [r3, #4]
800106c: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
800106e: 2201 movs r2, #1
8001070: 697b ldr r3, [r7, #20]
8001072: fa02 f303 lsl.w r3, r2, r3
8001076: 43db mvns r3, r3
8001078: 693a ldr r2, [r7, #16]
800107a: 4013 ands r3, r2
800107c: 613b str r3, [r7, #16]
SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800107e: 683b ldr r3, [r7, #0]
8001080: 685b ldr r3, [r3, #4]
8001082: 091b lsrs r3, r3, #4
8001084: f003 0201 and.w r2, r3, #1
8001088: 697b ldr r3, [r7, #20]
800108a: fa02 f303 lsl.w r3, r2, r3
800108e: 693a ldr r2, [r7, #16]
8001090: 4313 orrs r3, r2
8001092: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8001094: 687b ldr r3, [r7, #4]
8001096: 693a ldr r2, [r7, #16]
8001098: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
800109a: 683b ldr r3, [r7, #0]
800109c: 685b ldr r3, [r3, #4]
800109e: f003 0303 and.w r3, r3, #3
80010a2: 2b03 cmp r3, #3
80010a4: d017 beq.n 80010d6 <HAL_GPIO_Init+0xe6>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80010a6: 687b ldr r3, [r7, #4]
80010a8: 68db ldr r3, [r3, #12]
80010aa: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
80010ac: 697b ldr r3, [r7, #20]
80010ae: 005b lsls r3, r3, #1
80010b0: 2203 movs r2, #3
80010b2: fa02 f303 lsl.w r3, r2, r3
80010b6: 43db mvns r3, r3
80010b8: 693a ldr r2, [r7, #16]
80010ba: 4013 ands r3, r2
80010bc: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
80010be: 683b ldr r3, [r7, #0]
80010c0: 689a ldr r2, [r3, #8]
80010c2: 697b ldr r3, [r7, #20]
80010c4: 005b lsls r3, r3, #1
80010c6: fa02 f303 lsl.w r3, r2, r3
80010ca: 693a ldr r2, [r7, #16]
80010cc: 4313 orrs r3, r2
80010ce: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80010d0: 687b ldr r3, [r7, #4]
80010d2: 693a ldr r2, [r7, #16]
80010d4: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80010d6: 683b ldr r3, [r7, #0]
80010d8: 685b ldr r3, [r3, #4]
80010da: f003 0303 and.w r3, r3, #3
80010de: 2b02 cmp r3, #2
80010e0: d123 bne.n 800112a <HAL_GPIO_Init+0x13a>
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
/* Identify AFRL or AFRH register based on IO position*/
temp = GPIOx->AFR[position >> 3];
80010e2: 697b ldr r3, [r7, #20]
80010e4: 08da lsrs r2, r3, #3
80010e6: 687b ldr r3, [r7, #4]
80010e8: 3208 adds r2, #8
80010ea: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80010ee: 613b str r3, [r7, #16]
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
80010f0: 697b ldr r3, [r7, #20]
80010f2: f003 0307 and.w r3, r3, #7
80010f6: 009b lsls r3, r3, #2
80010f8: 220f movs r2, #15
80010fa: fa02 f303 lsl.w r3, r2, r3
80010fe: 43db mvns r3, r3
8001100: 693a ldr r2, [r7, #16]
8001102: 4013 ands r3, r2
8001104: 613b str r3, [r7, #16]
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
8001106: 683b ldr r3, [r7, #0]
8001108: 691a ldr r2, [r3, #16]
800110a: 697b ldr r3, [r7, #20]
800110c: f003 0307 and.w r3, r3, #7
8001110: 009b lsls r3, r3, #2
8001112: fa02 f303 lsl.w r3, r2, r3
8001116: 693a ldr r2, [r7, #16]
8001118: 4313 orrs r3, r2
800111a: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3] = temp;
800111c: 697b ldr r3, [r7, #20]
800111e: 08da lsrs r2, r3, #3
8001120: 687b ldr r3, [r7, #4]
8001122: 3208 adds r2, #8
8001124: 6939 ldr r1, [r7, #16]
8001126: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800112a: 687b ldr r3, [r7, #4]
800112c: 681b ldr r3, [r3, #0]
800112e: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
8001130: 697b ldr r3, [r7, #20]
8001132: 005b lsls r3, r3, #1
8001134: 2203 movs r2, #3
8001136: fa02 f303 lsl.w r3, r2, r3
800113a: 43db mvns r3, r3
800113c: 693a ldr r2, [r7, #16]
800113e: 4013 ands r3, r2
8001140: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8001142: 683b ldr r3, [r7, #0]
8001144: 685b ldr r3, [r3, #4]
8001146: f003 0203 and.w r2, r3, #3
800114a: 697b ldr r3, [r7, #20]
800114c: 005b lsls r3, r3, #1
800114e: fa02 f303 lsl.w r3, r2, r3
8001152: 693a ldr r2, [r7, #16]
8001154: 4313 orrs r3, r2
8001156: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001158: 687b ldr r3, [r7, #4]
800115a: 693a ldr r2, [r7, #16]
800115c: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
800115e: 683b ldr r3, [r7, #0]
8001160: 685b ldr r3, [r3, #4]
8001162: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001166: 2b00 cmp r3, #0
8001168: f000 80ac beq.w 80012c4 <HAL_GPIO_Init+0x2d4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800116c: 4b5e ldr r3, [pc, #376] @ (80012e8 <HAL_GPIO_Init+0x2f8>)
800116e: 6a1b ldr r3, [r3, #32]
8001170: 4a5d ldr r2, [pc, #372] @ (80012e8 <HAL_GPIO_Init+0x2f8>)
8001172: f043 0301 orr.w r3, r3, #1
8001176: 6213 str r3, [r2, #32]
8001178: 4b5b ldr r3, [pc, #364] @ (80012e8 <HAL_GPIO_Init+0x2f8>)
800117a: 6a1b ldr r3, [r3, #32]
800117c: f003 0301 and.w r3, r3, #1
8001180: 60bb str r3, [r7, #8]
8001182: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2];
8001184: 4a59 ldr r2, [pc, #356] @ (80012ec <HAL_GPIO_Init+0x2fc>)
8001186: 697b ldr r3, [r7, #20]
8001188: 089b lsrs r3, r3, #2
800118a: 3302 adds r3, #2
800118c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001190: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
8001192: 697b ldr r3, [r7, #20]
8001194: f003 0303 and.w r3, r3, #3
8001198: 009b lsls r3, r3, #2
800119a: 220f movs r2, #15
800119c: fa02 f303 lsl.w r3, r2, r3
80011a0: 43db mvns r3, r3
80011a2: 693a ldr r2, [r7, #16]
80011a4: 4013 ands r3, r2
80011a6: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
80011a8: 687b ldr r3, [r7, #4]
80011aa: 4a51 ldr r2, [pc, #324] @ (80012f0 <HAL_GPIO_Init+0x300>)
80011ac: 4293 cmp r3, r2
80011ae: d025 beq.n 80011fc <HAL_GPIO_Init+0x20c>
80011b0: 687b ldr r3, [r7, #4]
80011b2: 4a50 ldr r2, [pc, #320] @ (80012f4 <HAL_GPIO_Init+0x304>)
80011b4: 4293 cmp r3, r2
80011b6: d01f beq.n 80011f8 <HAL_GPIO_Init+0x208>
80011b8: 687b ldr r3, [r7, #4]
80011ba: 4a4f ldr r2, [pc, #316] @ (80012f8 <HAL_GPIO_Init+0x308>)
80011bc: 4293 cmp r3, r2
80011be: d019 beq.n 80011f4 <HAL_GPIO_Init+0x204>
80011c0: 687b ldr r3, [r7, #4]
80011c2: 4a4e ldr r2, [pc, #312] @ (80012fc <HAL_GPIO_Init+0x30c>)
80011c4: 4293 cmp r3, r2
80011c6: d013 beq.n 80011f0 <HAL_GPIO_Init+0x200>
80011c8: 687b ldr r3, [r7, #4]
80011ca: 4a4d ldr r2, [pc, #308] @ (8001300 <HAL_GPIO_Init+0x310>)
80011cc: 4293 cmp r3, r2
80011ce: d00d beq.n 80011ec <HAL_GPIO_Init+0x1fc>
80011d0: 687b ldr r3, [r7, #4]
80011d2: 4a4c ldr r2, [pc, #304] @ (8001304 <HAL_GPIO_Init+0x314>)
80011d4: 4293 cmp r3, r2
80011d6: d007 beq.n 80011e8 <HAL_GPIO_Init+0x1f8>
80011d8: 687b ldr r3, [r7, #4]
80011da: 4a4b ldr r2, [pc, #300] @ (8001308 <HAL_GPIO_Init+0x318>)
80011dc: 4293 cmp r3, r2
80011de: d101 bne.n 80011e4 <HAL_GPIO_Init+0x1f4>
80011e0: 2306 movs r3, #6
80011e2: e00c b.n 80011fe <HAL_GPIO_Init+0x20e>
80011e4: 2307 movs r3, #7
80011e6: e00a b.n 80011fe <HAL_GPIO_Init+0x20e>
80011e8: 2305 movs r3, #5
80011ea: e008 b.n 80011fe <HAL_GPIO_Init+0x20e>
80011ec: 2304 movs r3, #4
80011ee: e006 b.n 80011fe <HAL_GPIO_Init+0x20e>
80011f0: 2303 movs r3, #3
80011f2: e004 b.n 80011fe <HAL_GPIO_Init+0x20e>
80011f4: 2302 movs r3, #2
80011f6: e002 b.n 80011fe <HAL_GPIO_Init+0x20e>
80011f8: 2301 movs r3, #1
80011fa: e000 b.n 80011fe <HAL_GPIO_Init+0x20e>
80011fc: 2300 movs r3, #0
80011fe: 697a ldr r2, [r7, #20]
8001200: f002 0203 and.w r2, r2, #3
8001204: 0092 lsls r2, r2, #2
8001206: 4093 lsls r3, r2
8001208: 693a ldr r2, [r7, #16]
800120a: 4313 orrs r3, r2
800120c: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2] = temp;
800120e: 4937 ldr r1, [pc, #220] @ (80012ec <HAL_GPIO_Init+0x2fc>)
8001210: 697b ldr r3, [r7, #20]
8001212: 089b lsrs r3, r3, #2
8001214: 3302 adds r3, #2
8001216: 693a ldr r2, [r7, #16]
8001218: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
800121c: 4b3b ldr r3, [pc, #236] @ (800130c <HAL_GPIO_Init+0x31c>)
800121e: 689b ldr r3, [r3, #8]
8001220: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8001222: 68fb ldr r3, [r7, #12]
8001224: 43db mvns r3, r3
8001226: 693a ldr r2, [r7, #16]
8001228: 4013 ands r3, r2
800122a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
800122c: 683b ldr r3, [r7, #0]
800122e: 685b ldr r3, [r3, #4]
8001230: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001234: 2b00 cmp r3, #0
8001236: d003 beq.n 8001240 <HAL_GPIO_Init+0x250>
{
SET_BIT(temp, iocurrent);
8001238: 693a ldr r2, [r7, #16]
800123a: 68fb ldr r3, [r7, #12]
800123c: 4313 orrs r3, r2
800123e: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8001240: 4a32 ldr r2, [pc, #200] @ (800130c <HAL_GPIO_Init+0x31c>)
8001242: 693b ldr r3, [r7, #16]
8001244: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001246: 4b31 ldr r3, [pc, #196] @ (800130c <HAL_GPIO_Init+0x31c>)
8001248: 68db ldr r3, [r3, #12]
800124a: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
800124c: 68fb ldr r3, [r7, #12]
800124e: 43db mvns r3, r3
8001250: 693a ldr r2, [r7, #16]
8001252: 4013 ands r3, r2
8001254: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001256: 683b ldr r3, [r7, #0]
8001258: 685b ldr r3, [r3, #4]
800125a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800125e: 2b00 cmp r3, #0
8001260: d003 beq.n 800126a <HAL_GPIO_Init+0x27a>
{
SET_BIT(temp, iocurrent);
8001262: 693a ldr r2, [r7, #16]
8001264: 68fb ldr r3, [r7, #12]
8001266: 4313 orrs r3, r2
8001268: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
800126a: 4a28 ldr r2, [pc, #160] @ (800130c <HAL_GPIO_Init+0x31c>)
800126c: 693b ldr r3, [r7, #16]
800126e: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001270: 4b26 ldr r3, [pc, #152] @ (800130c <HAL_GPIO_Init+0x31c>)
8001272: 685b ldr r3, [r3, #4]
8001274: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8001276: 68fb ldr r3, [r7, #12]
8001278: 43db mvns r3, r3
800127a: 693a ldr r2, [r7, #16]
800127c: 4013 ands r3, r2
800127e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8001280: 683b ldr r3, [r7, #0]
8001282: 685b ldr r3, [r3, #4]
8001284: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001288: 2b00 cmp r3, #0
800128a: d003 beq.n 8001294 <HAL_GPIO_Init+0x2a4>
{
SET_BIT(temp, iocurrent);
800128c: 693a ldr r2, [r7, #16]
800128e: 68fb ldr r3, [r7, #12]
8001290: 4313 orrs r3, r2
8001292: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8001294: 4a1d ldr r2, [pc, #116] @ (800130c <HAL_GPIO_Init+0x31c>)
8001296: 693b ldr r3, [r7, #16]
8001298: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
800129a: 4b1c ldr r3, [pc, #112] @ (800130c <HAL_GPIO_Init+0x31c>)
800129c: 681b ldr r3, [r3, #0]
800129e: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
80012a0: 68fb ldr r3, [r7, #12]
80012a2: 43db mvns r3, r3
80012a4: 693a ldr r2, [r7, #16]
80012a6: 4013 ands r3, r2
80012a8: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80012aa: 683b ldr r3, [r7, #0]
80012ac: 685b ldr r3, [r3, #4]
80012ae: f403 3380 and.w r3, r3, #65536 @ 0x10000
80012b2: 2b00 cmp r3, #0
80012b4: d003 beq.n 80012be <HAL_GPIO_Init+0x2ce>
{
SET_BIT(temp, iocurrent);
80012b6: 693a ldr r2, [r7, #16]
80012b8: 68fb ldr r3, [r7, #12]
80012ba: 4313 orrs r3, r2
80012bc: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
80012be: 4a13 ldr r2, [pc, #76] @ (800130c <HAL_GPIO_Init+0x31c>)
80012c0: 693b ldr r3, [r7, #16]
80012c2: 6013 str r3, [r2, #0]
}
}
position++;
80012c4: 697b ldr r3, [r7, #20]
80012c6: 3301 adds r3, #1
80012c8: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0)
80012ca: 683b ldr r3, [r7, #0]
80012cc: 681a ldr r2, [r3, #0]
80012ce: 697b ldr r3, [r7, #20]
80012d0: fa22 f303 lsr.w r3, r2, r3
80012d4: 2b00 cmp r3, #0
80012d6: f47f ae97 bne.w 8001008 <HAL_GPIO_Init+0x18>
}
}
80012da: bf00 nop
80012dc: bf00 nop
80012de: 371c adds r7, #28
80012e0: 46bd mov sp, r7
80012e2: bc80 pop {r7}
80012e4: 4770 bx lr
80012e6: bf00 nop
80012e8: 40023800 .word 0x40023800
80012ec: 40010000 .word 0x40010000
80012f0: 40020000 .word 0x40020000
80012f4: 40020400 .word 0x40020400
80012f8: 40020800 .word 0x40020800
80012fc: 40020c00 .word 0x40020c00
8001300: 40021000 .word 0x40021000
8001304: 40021400 .word 0x40021400
8001308: 40021800 .word 0x40021800
800130c: 40010400 .word 0x40010400
08001310 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001310: b480 push {r7}
8001312: b083 sub sp, #12
8001314: af00 add r7, sp, #0
8001316: 6078 str r0, [r7, #4]
8001318: 460b mov r3, r1
800131a: 807b strh r3, [r7, #2]
800131c: 4613 mov r3, r2
800131e: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001320: 787b ldrb r3, [r7, #1]
8001322: 2b00 cmp r3, #0
8001324: d003 beq.n 800132e <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001326: 887a ldrh r2, [r7, #2]
8001328: 687b ldr r3, [r7, #4]
800132a: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
}
}
800132c: e003 b.n 8001336 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
800132e: 887b ldrh r3, [r7, #2]
8001330: 041a lsls r2, r3, #16
8001332: 687b ldr r3, [r7, #4]
8001334: 619a str r2, [r3, #24]
}
8001336: bf00 nop
8001338: 370c adds r7, #12
800133a: 46bd mov sp, r7
800133c: bc80 pop {r7}
800133e: 4770 bx lr
08001340 <HAL_GPIO_EXTI_IRQHandler>:
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
8001340: b580 push {r7, lr}
8001342: b082 sub sp, #8
8001344: af00 add r7, sp, #0
8001346: 4603 mov r3, r0
8001348: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
800134a: 4b08 ldr r3, [pc, #32] @ (800136c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
800134c: 695a ldr r2, [r3, #20]
800134e: 88fb ldrh r3, [r7, #6]
8001350: 4013 ands r3, r2
8001352: 2b00 cmp r3, #0
8001354: d006 beq.n 8001364 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8001356: 4a05 ldr r2, [pc, #20] @ (800136c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8001358: 88fb ldrh r3, [r7, #6]
800135a: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
800135c: 88fb ldrh r3, [r7, #6]
800135e: 4618 mov r0, r3
8001360: f000 f806 bl 8001370 <HAL_GPIO_EXTI_Callback>
}
}
8001364: bf00 nop
8001366: 3708 adds r7, #8
8001368: 46bd mov sp, r7
800136a: bd80 pop {r7, pc}
800136c: 40010400 .word 0x40010400
08001370 <HAL_GPIO_EXTI_Callback>:
* @brief EXTI line detection callbacks.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8001370: b480 push {r7}
8001372: b083 sub sp, #12
8001374: af00 add r7, sp, #0
8001376: 4603 mov r3, r0
8001378: 80fb strh r3, [r7, #6]
UNUSED(GPIO_Pin);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
800137a: bf00 nop
800137c: 370c adds r7, #12
800137e: 46bd mov sp, r7
8001380: bc80 pop {r7}
8001382: 4770 bx lr
08001384 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001384: b580 push {r7, lr}
8001386: b088 sub sp, #32
8001388: af00 add r7, sp, #0
800138a: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check the parameters */
if(RCC_OscInitStruct == NULL)
800138c: 687b ldr r3, [r7, #4]
800138e: 2b00 cmp r3, #0
8001390: d101 bne.n 8001396 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8001392: 2301 movs r3, #1
8001394: e31d b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
}
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8001396: 4b94 ldr r3, [pc, #592] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001398: 689b ldr r3, [r3, #8]
800139a: f003 030c and.w r3, r3, #12
800139e: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
80013a0: 4b91 ldr r3, [pc, #580] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80013a2: 689b ldr r3, [r3, #8]
80013a4: f403 3380 and.w r3, r3, #65536 @ 0x10000
80013a8: 617b str r3, [r7, #20]
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80013aa: 687b ldr r3, [r7, #4]
80013ac: 681b ldr r3, [r3, #0]
80013ae: f003 0301 and.w r3, r3, #1
80013b2: 2b00 cmp r3, #0
80013b4: d07b beq.n 80014ae <HAL_RCC_OscConfig+0x12a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
80013b6: 69bb ldr r3, [r7, #24]
80013b8: 2b08 cmp r3, #8
80013ba: d006 beq.n 80013ca <HAL_RCC_OscConfig+0x46>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
80013bc: 69bb ldr r3, [r7, #24]
80013be: 2b0c cmp r3, #12
80013c0: d10f bne.n 80013e2 <HAL_RCC_OscConfig+0x5e>
80013c2: 697b ldr r3, [r7, #20]
80013c4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80013c8: d10b bne.n 80013e2 <HAL_RCC_OscConfig+0x5e>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80013ca: 4b87 ldr r3, [pc, #540] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80013cc: 681b ldr r3, [r3, #0]
80013ce: f403 3300 and.w r3, r3, #131072 @ 0x20000
80013d2: 2b00 cmp r3, #0
80013d4: d06a beq.n 80014ac <HAL_RCC_OscConfig+0x128>
80013d6: 687b ldr r3, [r7, #4]
80013d8: 685b ldr r3, [r3, #4]
80013da: 2b00 cmp r3, #0
80013dc: d166 bne.n 80014ac <HAL_RCC_OscConfig+0x128>
{
return HAL_ERROR;
80013de: 2301 movs r3, #1
80013e0: e2f7 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80013e2: 687b ldr r3, [r7, #4]
80013e4: 685b ldr r3, [r3, #4]
80013e6: 2b01 cmp r3, #1
80013e8: d106 bne.n 80013f8 <HAL_RCC_OscConfig+0x74>
80013ea: 4b7f ldr r3, [pc, #508] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80013ec: 681b ldr r3, [r3, #0]
80013ee: 4a7e ldr r2, [pc, #504] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80013f0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80013f4: 6013 str r3, [r2, #0]
80013f6: e02d b.n 8001454 <HAL_RCC_OscConfig+0xd0>
80013f8: 687b ldr r3, [r7, #4]
80013fa: 685b ldr r3, [r3, #4]
80013fc: 2b00 cmp r3, #0
80013fe: d10c bne.n 800141a <HAL_RCC_OscConfig+0x96>
8001400: 4b79 ldr r3, [pc, #484] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001402: 681b ldr r3, [r3, #0]
8001404: 4a78 ldr r2, [pc, #480] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001406: f423 3380 bic.w r3, r3, #65536 @ 0x10000
800140a: 6013 str r3, [r2, #0]
800140c: 4b76 ldr r3, [pc, #472] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
800140e: 681b ldr r3, [r3, #0]
8001410: 4a75 ldr r2, [pc, #468] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001412: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001416: 6013 str r3, [r2, #0]
8001418: e01c b.n 8001454 <HAL_RCC_OscConfig+0xd0>
800141a: 687b ldr r3, [r7, #4]
800141c: 685b ldr r3, [r3, #4]
800141e: 2b05 cmp r3, #5
8001420: d10c bne.n 800143c <HAL_RCC_OscConfig+0xb8>
8001422: 4b71 ldr r3, [pc, #452] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001424: 681b ldr r3, [r3, #0]
8001426: 4a70 ldr r2, [pc, #448] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001428: f443 2380 orr.w r3, r3, #262144 @ 0x40000
800142c: 6013 str r3, [r2, #0]
800142e: 4b6e ldr r3, [pc, #440] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001430: 681b ldr r3, [r3, #0]
8001432: 4a6d ldr r2, [pc, #436] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001434: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001438: 6013 str r3, [r2, #0]
800143a: e00b b.n 8001454 <HAL_RCC_OscConfig+0xd0>
800143c: 4b6a ldr r3, [pc, #424] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
800143e: 681b ldr r3, [r3, #0]
8001440: 4a69 ldr r2, [pc, #420] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001442: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001446: 6013 str r3, [r2, #0]
8001448: 4b67 ldr r3, [pc, #412] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
800144a: 681b ldr r3, [r3, #0]
800144c: 4a66 ldr r2, [pc, #408] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
800144e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001452: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001454: 687b ldr r3, [r7, #4]
8001456: 685b ldr r3, [r3, #4]
8001458: 2b00 cmp r3, #0
800145a: d013 beq.n 8001484 <HAL_RCC_OscConfig+0x100>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800145c: f7ff fc8e bl 8000d7c <HAL_GetTick>
8001460: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8001462: e008 b.n 8001476 <HAL_RCC_OscConfig+0xf2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001464: f7ff fc8a bl 8000d7c <HAL_GetTick>
8001468: 4602 mov r2, r0
800146a: 693b ldr r3, [r7, #16]
800146c: 1ad3 subs r3, r2, r3
800146e: 2b64 cmp r3, #100 @ 0x64
8001470: d901 bls.n 8001476 <HAL_RCC_OscConfig+0xf2>
{
return HAL_TIMEOUT;
8001472: 2303 movs r3, #3
8001474: e2ad b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8001476: 4b5c ldr r3, [pc, #368] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001478: 681b ldr r3, [r3, #0]
800147a: f403 3300 and.w r3, r3, #131072 @ 0x20000
800147e: 2b00 cmp r3, #0
8001480: d0f0 beq.n 8001464 <HAL_RCC_OscConfig+0xe0>
8001482: e014 b.n 80014ae <HAL_RCC_OscConfig+0x12a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001484: f7ff fc7a bl 8000d7c <HAL_GetTick>
8001488: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
800148a: e008 b.n 800149e <HAL_RCC_OscConfig+0x11a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800148c: f7ff fc76 bl 8000d7c <HAL_GetTick>
8001490: 4602 mov r2, r0
8001492: 693b ldr r3, [r7, #16]
8001494: 1ad3 subs r3, r2, r3
8001496: 2b64 cmp r3, #100 @ 0x64
8001498: d901 bls.n 800149e <HAL_RCC_OscConfig+0x11a>
{
return HAL_TIMEOUT;
800149a: 2303 movs r3, #3
800149c: e299 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
800149e: 4b52 ldr r3, [pc, #328] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80014a0: 681b ldr r3, [r3, #0]
80014a2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80014a6: 2b00 cmp r3, #0
80014a8: d1f0 bne.n 800148c <HAL_RCC_OscConfig+0x108>
80014aa: e000 b.n 80014ae <HAL_RCC_OscConfig+0x12a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80014ac: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80014ae: 687b ldr r3, [r7, #4]
80014b0: 681b ldr r3, [r3, #0]
80014b2: f003 0302 and.w r3, r3, #2
80014b6: 2b00 cmp r3, #0
80014b8: d05a beq.n 8001570 <HAL_RCC_OscConfig+0x1ec>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
80014ba: 69bb ldr r3, [r7, #24]
80014bc: 2b04 cmp r3, #4
80014be: d005 beq.n 80014cc <HAL_RCC_OscConfig+0x148>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
80014c0: 69bb ldr r3, [r7, #24]
80014c2: 2b0c cmp r3, #12
80014c4: d119 bne.n 80014fa <HAL_RCC_OscConfig+0x176>
80014c6: 697b ldr r3, [r7, #20]
80014c8: 2b00 cmp r3, #0
80014ca: d116 bne.n 80014fa <HAL_RCC_OscConfig+0x176>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80014cc: 4b46 ldr r3, [pc, #280] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80014ce: 681b ldr r3, [r3, #0]
80014d0: f003 0302 and.w r3, r3, #2
80014d4: 2b00 cmp r3, #0
80014d6: d005 beq.n 80014e4 <HAL_RCC_OscConfig+0x160>
80014d8: 687b ldr r3, [r7, #4]
80014da: 68db ldr r3, [r3, #12]
80014dc: 2b01 cmp r3, #1
80014de: d001 beq.n 80014e4 <HAL_RCC_OscConfig+0x160>
{
return HAL_ERROR;
80014e0: 2301 movs r3, #1
80014e2: e276 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80014e4: 4b40 ldr r3, [pc, #256] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80014e6: 685b ldr r3, [r3, #4]
80014e8: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
80014ec: 687b ldr r3, [r7, #4]
80014ee: 691b ldr r3, [r3, #16]
80014f0: 021b lsls r3, r3, #8
80014f2: 493d ldr r1, [pc, #244] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80014f4: 4313 orrs r3, r2
80014f6: 604b str r3, [r1, #4]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80014f8: e03a b.n 8001570 <HAL_RCC_OscConfig+0x1ec>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80014fa: 687b ldr r3, [r7, #4]
80014fc: 68db ldr r3, [r3, #12]
80014fe: 2b00 cmp r3, #0
8001500: d020 beq.n 8001544 <HAL_RCC_OscConfig+0x1c0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001502: 4b3a ldr r3, [pc, #232] @ (80015ec <HAL_RCC_OscConfig+0x268>)
8001504: 2201 movs r2, #1
8001506: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001508: f7ff fc38 bl 8000d7c <HAL_GetTick>
800150c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
800150e: e008 b.n 8001522 <HAL_RCC_OscConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001510: f7ff fc34 bl 8000d7c <HAL_GetTick>
8001514: 4602 mov r2, r0
8001516: 693b ldr r3, [r7, #16]
8001518: 1ad3 subs r3, r2, r3
800151a: 2b02 cmp r3, #2
800151c: d901 bls.n 8001522 <HAL_RCC_OscConfig+0x19e>
{
return HAL_TIMEOUT;
800151e: 2303 movs r3, #3
8001520: e257 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8001522: 4b31 ldr r3, [pc, #196] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001524: 681b ldr r3, [r3, #0]
8001526: f003 0302 and.w r3, r3, #2
800152a: 2b00 cmp r3, #0
800152c: d0f0 beq.n 8001510 <HAL_RCC_OscConfig+0x18c>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800152e: 4b2e ldr r3, [pc, #184] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001530: 685b ldr r3, [r3, #4]
8001532: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8001536: 687b ldr r3, [r7, #4]
8001538: 691b ldr r3, [r3, #16]
800153a: 021b lsls r3, r3, #8
800153c: 492a ldr r1, [pc, #168] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
800153e: 4313 orrs r3, r2
8001540: 604b str r3, [r1, #4]
8001542: e015 b.n 8001570 <HAL_RCC_OscConfig+0x1ec>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001544: 4b29 ldr r3, [pc, #164] @ (80015ec <HAL_RCC_OscConfig+0x268>)
8001546: 2200 movs r2, #0
8001548: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800154a: f7ff fc17 bl 8000d7c <HAL_GetTick>
800154e: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001550: e008 b.n 8001564 <HAL_RCC_OscConfig+0x1e0>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001552: f7ff fc13 bl 8000d7c <HAL_GetTick>
8001556: 4602 mov r2, r0
8001558: 693b ldr r3, [r7, #16]
800155a: 1ad3 subs r3, r2, r3
800155c: 2b02 cmp r3, #2
800155e: d901 bls.n 8001564 <HAL_RCC_OscConfig+0x1e0>
{
return HAL_TIMEOUT;
8001560: 2303 movs r3, #3
8001562: e236 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001564: 4b20 ldr r3, [pc, #128] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001566: 681b ldr r3, [r3, #0]
8001568: f003 0302 and.w r3, r3, #2
800156c: 2b00 cmp r3, #0
800156e: d1f0 bne.n 8001552 <HAL_RCC_OscConfig+0x1ce>
}
}
}
}
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8001570: 687b ldr r3, [r7, #4]
8001572: 681b ldr r3, [r3, #0]
8001574: f003 0310 and.w r3, r3, #16
8001578: 2b00 cmp r3, #0
800157a: f000 80b8 beq.w 80016ee <HAL_RCC_OscConfig+0x36a>
{
/* When the MSI is used as system clock it will not be disabled */
if(sysclk_source == RCC_CFGR_SWS_MSI)
800157e: 69bb ldr r3, [r7, #24]
8001580: 2b00 cmp r3, #0
8001582: d170 bne.n 8001666 <HAL_RCC_OscConfig+0x2e2>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001584: 4b18 ldr r3, [pc, #96] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
8001586: 681b ldr r3, [r3, #0]
8001588: f403 7300 and.w r3, r3, #512 @ 0x200
800158c: 2b00 cmp r3, #0
800158e: d005 beq.n 800159c <HAL_RCC_OscConfig+0x218>
8001590: 687b ldr r3, [r7, #4]
8001592: 699b ldr r3, [r3, #24]
8001594: 2b00 cmp r3, #0
8001596: d101 bne.n 800159c <HAL_RCC_OscConfig+0x218>
{
return HAL_ERROR;
8001598: 2301 movs r3, #1
800159a: e21a b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
800159c: 687b ldr r3, [r7, #4]
800159e: 6a1a ldr r2, [r3, #32]
80015a0: 4b11 ldr r3, [pc, #68] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80015a2: 685b ldr r3, [r3, #4]
80015a4: f403 4360 and.w r3, r3, #57344 @ 0xe000
80015a8: 429a cmp r2, r3
80015aa: d921 bls.n 80015f0 <HAL_RCC_OscConfig+0x26c>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
80015ac: 687b ldr r3, [r7, #4]
80015ae: 6a1b ldr r3, [r3, #32]
80015b0: 4618 mov r0, r3
80015b2: f000 fc09 bl 8001dc8 <RCC_SetFlashLatencyFromMSIRange>
80015b6: 4603 mov r3, r0
80015b8: 2b00 cmp r3, #0
80015ba: d001 beq.n 80015c0 <HAL_RCC_OscConfig+0x23c>
{
return HAL_ERROR;
80015bc: 2301 movs r3, #1
80015be: e208 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80015c0: 4b09 ldr r3, [pc, #36] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80015c2: 685b ldr r3, [r3, #4]
80015c4: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80015c8: 687b ldr r3, [r7, #4]
80015ca: 6a1b ldr r3, [r3, #32]
80015cc: 4906 ldr r1, [pc, #24] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80015ce: 4313 orrs r3, r2
80015d0: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80015d2: 4b05 ldr r3, [pc, #20] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80015d4: 685b ldr r3, [r3, #4]
80015d6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
80015da: 687b ldr r3, [r7, #4]
80015dc: 69db ldr r3, [r3, #28]
80015de: 061b lsls r3, r3, #24
80015e0: 4901 ldr r1, [pc, #4] @ (80015e8 <HAL_RCC_OscConfig+0x264>)
80015e2: 4313 orrs r3, r2
80015e4: 604b str r3, [r1, #4]
80015e6: e020 b.n 800162a <HAL_RCC_OscConfig+0x2a6>
80015e8: 40023800 .word 0x40023800
80015ec: 42470000 .word 0x42470000
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80015f0: 4b99 ldr r3, [pc, #612] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80015f2: 685b ldr r3, [r3, #4]
80015f4: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80015f8: 687b ldr r3, [r7, #4]
80015fa: 6a1b ldr r3, [r3, #32]
80015fc: 4996 ldr r1, [pc, #600] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80015fe: 4313 orrs r3, r2
8001600: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001602: 4b95 ldr r3, [pc, #596] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001604: 685b ldr r3, [r3, #4]
8001606: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
800160a: 687b ldr r3, [r7, #4]
800160c: 69db ldr r3, [r3, #28]
800160e: 061b lsls r3, r3, #24
8001610: 4991 ldr r1, [pc, #580] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001612: 4313 orrs r3, r2
8001614: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8001616: 687b ldr r3, [r7, #4]
8001618: 6a1b ldr r3, [r3, #32]
800161a: 4618 mov r0, r3
800161c: f000 fbd4 bl 8001dc8 <RCC_SetFlashLatencyFromMSIRange>
8001620: 4603 mov r3, r0
8001622: 2b00 cmp r3, #0
8001624: d001 beq.n 800162a <HAL_RCC_OscConfig+0x2a6>
{
return HAL_ERROR;
8001626: 2301 movs r3, #1
8001628: e1d3 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
800162a: 687b ldr r3, [r7, #4]
800162c: 6a1b ldr r3, [r3, #32]
800162e: 0b5b lsrs r3, r3, #13
8001630: 3301 adds r3, #1
8001632: f44f 4200 mov.w r2, #32768 @ 0x8000
8001636: fa02 f303 lsl.w r3, r2, r3
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
800163a: 4a87 ldr r2, [pc, #540] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
800163c: 6892 ldr r2, [r2, #8]
800163e: 0912 lsrs r2, r2, #4
8001640: f002 020f and.w r2, r2, #15
8001644: 4985 ldr r1, [pc, #532] @ (800185c <HAL_RCC_OscConfig+0x4d8>)
8001646: 5c8a ldrb r2, [r1, r2]
8001648: 40d3 lsrs r3, r2
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
800164a: 4a85 ldr r2, [pc, #532] @ (8001860 <HAL_RCC_OscConfig+0x4dc>)
800164c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
800164e: 4b85 ldr r3, [pc, #532] @ (8001864 <HAL_RCC_OscConfig+0x4e0>)
8001650: 681b ldr r3, [r3, #0]
8001652: 4618 mov r0, r3
8001654: f7ff fb46 bl 8000ce4 <HAL_InitTick>
8001658: 4603 mov r3, r0
800165a: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
800165c: 7bfb ldrb r3, [r7, #15]
800165e: 2b00 cmp r3, #0
8001660: d045 beq.n 80016ee <HAL_RCC_OscConfig+0x36a>
{
return status;
8001662: 7bfb ldrb r3, [r7, #15]
8001664: e1b5 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
{
/* Check MSI State */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8001666: 687b ldr r3, [r7, #4]
8001668: 699b ldr r3, [r3, #24]
800166a: 2b00 cmp r3, #0
800166c: d029 beq.n 80016c2 <HAL_RCC_OscConfig+0x33e>
{
/* Enable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
800166e: 4b7e ldr r3, [pc, #504] @ (8001868 <HAL_RCC_OscConfig+0x4e4>)
8001670: 2201 movs r2, #1
8001672: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001674: f7ff fb82 bl 8000d7c <HAL_GetTick>
8001678: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800167a: e008 b.n 800168e <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
800167c: f7ff fb7e bl 8000d7c <HAL_GetTick>
8001680: 4602 mov r2, r0
8001682: 693b ldr r3, [r7, #16]
8001684: 1ad3 subs r3, r2, r3
8001686: 2b02 cmp r3, #2
8001688: d901 bls.n 800168e <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
800168a: 2303 movs r3, #3
800168c: e1a1 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800168e: 4b72 ldr r3, [pc, #456] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001690: 681b ldr r3, [r3, #0]
8001692: f403 7300 and.w r3, r3, #512 @ 0x200
8001696: 2b00 cmp r3, #0
8001698: d0f0 beq.n 800167c <HAL_RCC_OscConfig+0x2f8>
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800169a: 4b6f ldr r3, [pc, #444] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
800169c: 685b ldr r3, [r3, #4]
800169e: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80016a2: 687b ldr r3, [r7, #4]
80016a4: 6a1b ldr r3, [r3, #32]
80016a6: 496c ldr r1, [pc, #432] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80016a8: 4313 orrs r3, r2
80016aa: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80016ac: 4b6a ldr r3, [pc, #424] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80016ae: 685b ldr r3, [r3, #4]
80016b0: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
80016b4: 687b ldr r3, [r7, #4]
80016b6: 69db ldr r3, [r3, #28]
80016b8: 061b lsls r3, r3, #24
80016ba: 4967 ldr r1, [pc, #412] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80016bc: 4313 orrs r3, r2
80016be: 604b str r3, [r1, #4]
80016c0: e015 b.n 80016ee <HAL_RCC_OscConfig+0x36a>
}
else
{
/* Disable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
80016c2: 4b69 ldr r3, [pc, #420] @ (8001868 <HAL_RCC_OscConfig+0x4e4>)
80016c4: 2200 movs r2, #0
80016c6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80016c8: f7ff fb58 bl 8000d7c <HAL_GetTick>
80016cc: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
80016ce: e008 b.n 80016e2 <HAL_RCC_OscConfig+0x35e>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
80016d0: f7ff fb54 bl 8000d7c <HAL_GetTick>
80016d4: 4602 mov r2, r0
80016d6: 693b ldr r3, [r7, #16]
80016d8: 1ad3 subs r3, r2, r3
80016da: 2b02 cmp r3, #2
80016dc: d901 bls.n 80016e2 <HAL_RCC_OscConfig+0x35e>
{
return HAL_TIMEOUT;
80016de: 2303 movs r3, #3
80016e0: e177 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
80016e2: 4b5d ldr r3, [pc, #372] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80016e4: 681b ldr r3, [r3, #0]
80016e6: f403 7300 and.w r3, r3, #512 @ 0x200
80016ea: 2b00 cmp r3, #0
80016ec: d1f0 bne.n 80016d0 <HAL_RCC_OscConfig+0x34c>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80016ee: 687b ldr r3, [r7, #4]
80016f0: 681b ldr r3, [r3, #0]
80016f2: f003 0308 and.w r3, r3, #8
80016f6: 2b00 cmp r3, #0
80016f8: d030 beq.n 800175c <HAL_RCC_OscConfig+0x3d8>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80016fa: 687b ldr r3, [r7, #4]
80016fc: 695b ldr r3, [r3, #20]
80016fe: 2b00 cmp r3, #0
8001700: d016 beq.n 8001730 <HAL_RCC_OscConfig+0x3ac>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001702: 4b5a ldr r3, [pc, #360] @ (800186c <HAL_RCC_OscConfig+0x4e8>)
8001704: 2201 movs r2, #1
8001706: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001708: f7ff fb38 bl 8000d7c <HAL_GetTick>
800170c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
800170e: e008 b.n 8001722 <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001710: f7ff fb34 bl 8000d7c <HAL_GetTick>
8001714: 4602 mov r2, r0
8001716: 693b ldr r3, [r7, #16]
8001718: 1ad3 subs r3, r2, r3
800171a: 2b02 cmp r3, #2
800171c: d901 bls.n 8001722 <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
800171e: 2303 movs r3, #3
8001720: e157 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
8001722: 4b4d ldr r3, [pc, #308] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001724: 6b5b ldr r3, [r3, #52] @ 0x34
8001726: f003 0302 and.w r3, r3, #2
800172a: 2b00 cmp r3, #0
800172c: d0f0 beq.n 8001710 <HAL_RCC_OscConfig+0x38c>
800172e: e015 b.n 800175c <HAL_RCC_OscConfig+0x3d8>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001730: 4b4e ldr r3, [pc, #312] @ (800186c <HAL_RCC_OscConfig+0x4e8>)
8001732: 2200 movs r2, #0
8001734: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001736: f7ff fb21 bl 8000d7c <HAL_GetTick>
800173a: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
800173c: e008 b.n 8001750 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800173e: f7ff fb1d bl 8000d7c <HAL_GetTick>
8001742: 4602 mov r2, r0
8001744: 693b ldr r3, [r7, #16]
8001746: 1ad3 subs r3, r2, r3
8001748: 2b02 cmp r3, #2
800174a: d901 bls.n 8001750 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
800174c: 2303 movs r3, #3
800174e: e140 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8001750: 4b41 ldr r3, [pc, #260] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001752: 6b5b ldr r3, [r3, #52] @ 0x34
8001754: f003 0302 and.w r3, r3, #2
8001758: 2b00 cmp r3, #0
800175a: d1f0 bne.n 800173e <HAL_RCC_OscConfig+0x3ba>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800175c: 687b ldr r3, [r7, #4]
800175e: 681b ldr r3, [r3, #0]
8001760: f003 0304 and.w r3, r3, #4
8001764: 2b00 cmp r3, #0
8001766: f000 80b5 beq.w 80018d4 <HAL_RCC_OscConfig+0x550>
{
FlagStatus pwrclkchanged = RESET;
800176a: 2300 movs r3, #0
800176c: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800176e: 4b3a ldr r3, [pc, #232] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001770: 6a5b ldr r3, [r3, #36] @ 0x24
8001772: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001776: 2b00 cmp r3, #0
8001778: d10d bne.n 8001796 <HAL_RCC_OscConfig+0x412>
{
__HAL_RCC_PWR_CLK_ENABLE();
800177a: 4b37 ldr r3, [pc, #220] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
800177c: 6a5b ldr r3, [r3, #36] @ 0x24
800177e: 4a36 ldr r2, [pc, #216] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001780: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001784: 6253 str r3, [r2, #36] @ 0x24
8001786: 4b34 ldr r3, [pc, #208] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001788: 6a5b ldr r3, [r3, #36] @ 0x24
800178a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800178e: 60bb str r3, [r7, #8]
8001790: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001792: 2301 movs r3, #1
8001794: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001796: 4b36 ldr r3, [pc, #216] @ (8001870 <HAL_RCC_OscConfig+0x4ec>)
8001798: 681b ldr r3, [r3, #0]
800179a: f403 7380 and.w r3, r3, #256 @ 0x100
800179e: 2b00 cmp r3, #0
80017a0: d118 bne.n 80017d4 <HAL_RCC_OscConfig+0x450>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80017a2: 4b33 ldr r3, [pc, #204] @ (8001870 <HAL_RCC_OscConfig+0x4ec>)
80017a4: 681b ldr r3, [r3, #0]
80017a6: 4a32 ldr r2, [pc, #200] @ (8001870 <HAL_RCC_OscConfig+0x4ec>)
80017a8: f443 7380 orr.w r3, r3, #256 @ 0x100
80017ac: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80017ae: f7ff fae5 bl 8000d7c <HAL_GetTick>
80017b2: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80017b4: e008 b.n 80017c8 <HAL_RCC_OscConfig+0x444>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80017b6: f7ff fae1 bl 8000d7c <HAL_GetTick>
80017ba: 4602 mov r2, r0
80017bc: 693b ldr r3, [r7, #16]
80017be: 1ad3 subs r3, r2, r3
80017c0: 2b64 cmp r3, #100 @ 0x64
80017c2: d901 bls.n 80017c8 <HAL_RCC_OscConfig+0x444>
{
return HAL_TIMEOUT;
80017c4: 2303 movs r3, #3
80017c6: e104 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80017c8: 4b29 ldr r3, [pc, #164] @ (8001870 <HAL_RCC_OscConfig+0x4ec>)
80017ca: 681b ldr r3, [r3, #0]
80017cc: f403 7380 and.w r3, r3, #256 @ 0x100
80017d0: 2b00 cmp r3, #0
80017d2: d0f0 beq.n 80017b6 <HAL_RCC_OscConfig+0x432>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80017d4: 687b ldr r3, [r7, #4]
80017d6: 689b ldr r3, [r3, #8]
80017d8: 2b01 cmp r3, #1
80017da: d106 bne.n 80017ea <HAL_RCC_OscConfig+0x466>
80017dc: 4b1e ldr r3, [pc, #120] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80017de: 6b5b ldr r3, [r3, #52] @ 0x34
80017e0: 4a1d ldr r2, [pc, #116] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80017e2: f443 7380 orr.w r3, r3, #256 @ 0x100
80017e6: 6353 str r3, [r2, #52] @ 0x34
80017e8: e02d b.n 8001846 <HAL_RCC_OscConfig+0x4c2>
80017ea: 687b ldr r3, [r7, #4]
80017ec: 689b ldr r3, [r3, #8]
80017ee: 2b00 cmp r3, #0
80017f0: d10c bne.n 800180c <HAL_RCC_OscConfig+0x488>
80017f2: 4b19 ldr r3, [pc, #100] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80017f4: 6b5b ldr r3, [r3, #52] @ 0x34
80017f6: 4a18 ldr r2, [pc, #96] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
80017f8: f423 7380 bic.w r3, r3, #256 @ 0x100
80017fc: 6353 str r3, [r2, #52] @ 0x34
80017fe: 4b16 ldr r3, [pc, #88] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001800: 6b5b ldr r3, [r3, #52] @ 0x34
8001802: 4a15 ldr r2, [pc, #84] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001804: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001808: 6353 str r3, [r2, #52] @ 0x34
800180a: e01c b.n 8001846 <HAL_RCC_OscConfig+0x4c2>
800180c: 687b ldr r3, [r7, #4]
800180e: 689b ldr r3, [r3, #8]
8001810: 2b05 cmp r3, #5
8001812: d10c bne.n 800182e <HAL_RCC_OscConfig+0x4aa>
8001814: 4b10 ldr r3, [pc, #64] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001816: 6b5b ldr r3, [r3, #52] @ 0x34
8001818: 4a0f ldr r2, [pc, #60] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
800181a: f443 6380 orr.w r3, r3, #1024 @ 0x400
800181e: 6353 str r3, [r2, #52] @ 0x34
8001820: 4b0d ldr r3, [pc, #52] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001822: 6b5b ldr r3, [r3, #52] @ 0x34
8001824: 4a0c ldr r2, [pc, #48] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001826: f443 7380 orr.w r3, r3, #256 @ 0x100
800182a: 6353 str r3, [r2, #52] @ 0x34
800182c: e00b b.n 8001846 <HAL_RCC_OscConfig+0x4c2>
800182e: 4b0a ldr r3, [pc, #40] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001830: 6b5b ldr r3, [r3, #52] @ 0x34
8001832: 4a09 ldr r2, [pc, #36] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001834: f423 7380 bic.w r3, r3, #256 @ 0x100
8001838: 6353 str r3, [r2, #52] @ 0x34
800183a: 4b07 ldr r3, [pc, #28] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
800183c: 6b5b ldr r3, [r3, #52] @ 0x34
800183e: 4a06 ldr r2, [pc, #24] @ (8001858 <HAL_RCC_OscConfig+0x4d4>)
8001840: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001844: 6353 str r3, [r2, #52] @ 0x34
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001846: 687b ldr r3, [r7, #4]
8001848: 689b ldr r3, [r3, #8]
800184a: 2b00 cmp r3, #0
800184c: d024 beq.n 8001898 <HAL_RCC_OscConfig+0x514>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800184e: f7ff fa95 bl 8000d7c <HAL_GetTick>
8001852: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8001854: e019 b.n 800188a <HAL_RCC_OscConfig+0x506>
8001856: bf00 nop
8001858: 40023800 .word 0x40023800
800185c: 08002eb0 .word 0x08002eb0
8001860: 20000000 .word 0x20000000
8001864: 20000004 .word 0x20000004
8001868: 42470020 .word 0x42470020
800186c: 42470680 .word 0x42470680
8001870: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001874: f7ff fa82 bl 8000d7c <HAL_GetTick>
8001878: 4602 mov r2, r0
800187a: 693b ldr r3, [r7, #16]
800187c: 1ad3 subs r3, r2, r3
800187e: f241 3288 movw r2, #5000 @ 0x1388
8001882: 4293 cmp r3, r2
8001884: d901 bls.n 800188a <HAL_RCC_OscConfig+0x506>
{
return HAL_TIMEOUT;
8001886: 2303 movs r3, #3
8001888: e0a3 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
800188a: 4b54 ldr r3, [pc, #336] @ (80019dc <HAL_RCC_OscConfig+0x658>)
800188c: 6b5b ldr r3, [r3, #52] @ 0x34
800188e: f403 7300 and.w r3, r3, #512 @ 0x200
8001892: 2b00 cmp r3, #0
8001894: d0ee beq.n 8001874 <HAL_RCC_OscConfig+0x4f0>
8001896: e014 b.n 80018c2 <HAL_RCC_OscConfig+0x53e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001898: f7ff fa70 bl 8000d7c <HAL_GetTick>
800189c: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
800189e: e00a b.n 80018b6 <HAL_RCC_OscConfig+0x532>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80018a0: f7ff fa6c bl 8000d7c <HAL_GetTick>
80018a4: 4602 mov r2, r0
80018a6: 693b ldr r3, [r7, #16]
80018a8: 1ad3 subs r3, r2, r3
80018aa: f241 3288 movw r2, #5000 @ 0x1388
80018ae: 4293 cmp r3, r2
80018b0: d901 bls.n 80018b6 <HAL_RCC_OscConfig+0x532>
{
return HAL_TIMEOUT;
80018b2: 2303 movs r3, #3
80018b4: e08d b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
80018b6: 4b49 ldr r3, [pc, #292] @ (80019dc <HAL_RCC_OscConfig+0x658>)
80018b8: 6b5b ldr r3, [r3, #52] @ 0x34
80018ba: f403 7300 and.w r3, r3, #512 @ 0x200
80018be: 2b00 cmp r3, #0
80018c0: d1ee bne.n 80018a0 <HAL_RCC_OscConfig+0x51c>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80018c2: 7ffb ldrb r3, [r7, #31]
80018c4: 2b01 cmp r3, #1
80018c6: d105 bne.n 80018d4 <HAL_RCC_OscConfig+0x550>
{
__HAL_RCC_PWR_CLK_DISABLE();
80018c8: 4b44 ldr r3, [pc, #272] @ (80019dc <HAL_RCC_OscConfig+0x658>)
80018ca: 6a5b ldr r3, [r3, #36] @ 0x24
80018cc: 4a43 ldr r2, [pc, #268] @ (80019dc <HAL_RCC_OscConfig+0x658>)
80018ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80018d2: 6253 str r3, [r2, #36] @ 0x24
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80018d4: 687b ldr r3, [r7, #4]
80018d6: 6a5b ldr r3, [r3, #36] @ 0x24
80018d8: 2b00 cmp r3, #0
80018da: d079 beq.n 80019d0 <HAL_RCC_OscConfig+0x64c>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80018dc: 69bb ldr r3, [r7, #24]
80018de: 2b0c cmp r3, #12
80018e0: d056 beq.n 8001990 <HAL_RCC_OscConfig+0x60c>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80018e2: 687b ldr r3, [r7, #4]
80018e4: 6a5b ldr r3, [r3, #36] @ 0x24
80018e6: 2b02 cmp r3, #2
80018e8: d13b bne.n 8001962 <HAL_RCC_OscConfig+0x5de>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80018ea: 4b3d ldr r3, [pc, #244] @ (80019e0 <HAL_RCC_OscConfig+0x65c>)
80018ec: 2200 movs r2, #0
80018ee: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80018f0: f7ff fa44 bl 8000d7c <HAL_GetTick>
80018f4: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80018f6: e008 b.n 800190a <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80018f8: f7ff fa40 bl 8000d7c <HAL_GetTick>
80018fc: 4602 mov r2, r0
80018fe: 693b ldr r3, [r7, #16]
8001900: 1ad3 subs r3, r2, r3
8001902: 2b02 cmp r3, #2
8001904: d901 bls.n 800190a <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8001906: 2303 movs r3, #3
8001908: e063 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
800190a: 4b34 ldr r3, [pc, #208] @ (80019dc <HAL_RCC_OscConfig+0x658>)
800190c: 681b ldr r3, [r3, #0]
800190e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001912: 2b00 cmp r3, #0
8001914: d1f0 bne.n 80018f8 <HAL_RCC_OscConfig+0x574>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001916: 4b31 ldr r3, [pc, #196] @ (80019dc <HAL_RCC_OscConfig+0x658>)
8001918: 689b ldr r3, [r3, #8]
800191a: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000
800191e: 687b ldr r3, [r7, #4]
8001920: 6a99 ldr r1, [r3, #40] @ 0x28
8001922: 687b ldr r3, [r7, #4]
8001924: 6adb ldr r3, [r3, #44] @ 0x2c
8001926: 4319 orrs r1, r3
8001928: 687b ldr r3, [r7, #4]
800192a: 6b1b ldr r3, [r3, #48] @ 0x30
800192c: 430b orrs r3, r1
800192e: 492b ldr r1, [pc, #172] @ (80019dc <HAL_RCC_OscConfig+0x658>)
8001930: 4313 orrs r3, r2
8001932: 608b str r3, [r1, #8]
RCC_OscInitStruct->PLL.PLLMUL,
RCC_OscInitStruct->PLL.PLLDIV);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001934: 4b2a ldr r3, [pc, #168] @ (80019e0 <HAL_RCC_OscConfig+0x65c>)
8001936: 2201 movs r2, #1
8001938: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800193a: f7ff fa1f bl 8000d7c <HAL_GetTick>
800193e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001940: e008 b.n 8001954 <HAL_RCC_OscConfig+0x5d0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001942: f7ff fa1b bl 8000d7c <HAL_GetTick>
8001946: 4602 mov r2, r0
8001948: 693b ldr r3, [r7, #16]
800194a: 1ad3 subs r3, r2, r3
800194c: 2b02 cmp r3, #2
800194e: d901 bls.n 8001954 <HAL_RCC_OscConfig+0x5d0>
{
return HAL_TIMEOUT;
8001950: 2303 movs r3, #3
8001952: e03e b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001954: 4b21 ldr r3, [pc, #132] @ (80019dc <HAL_RCC_OscConfig+0x658>)
8001956: 681b ldr r3, [r3, #0]
8001958: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800195c: 2b00 cmp r3, #0
800195e: d0f0 beq.n 8001942 <HAL_RCC_OscConfig+0x5be>
8001960: e036 b.n 80019d0 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001962: 4b1f ldr r3, [pc, #124] @ (80019e0 <HAL_RCC_OscConfig+0x65c>)
8001964: 2200 movs r2, #0
8001966: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001968: f7ff fa08 bl 8000d7c <HAL_GetTick>
800196c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
800196e: e008 b.n 8001982 <HAL_RCC_OscConfig+0x5fe>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001970: f7ff fa04 bl 8000d7c <HAL_GetTick>
8001974: 4602 mov r2, r0
8001976: 693b ldr r3, [r7, #16]
8001978: 1ad3 subs r3, r2, r3
800197a: 2b02 cmp r3, #2
800197c: d901 bls.n 8001982 <HAL_RCC_OscConfig+0x5fe>
{
return HAL_TIMEOUT;
800197e: 2303 movs r3, #3
8001980: e027 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8001982: 4b16 ldr r3, [pc, #88] @ (80019dc <HAL_RCC_OscConfig+0x658>)
8001984: 681b ldr r3, [r3, #0]
8001986: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800198a: 2b00 cmp r3, #0
800198c: d1f0 bne.n 8001970 <HAL_RCC_OscConfig+0x5ec>
800198e: e01f b.n 80019d0 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001990: 687b ldr r3, [r7, #4]
8001992: 6a5b ldr r3, [r3, #36] @ 0x24
8001994: 2b01 cmp r3, #1
8001996: d101 bne.n 800199c <HAL_RCC_OscConfig+0x618>
{
return HAL_ERROR;
8001998: 2301 movs r3, #1
800199a: e01a b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800199c: 4b0f ldr r3, [pc, #60] @ (80019dc <HAL_RCC_OscConfig+0x658>)
800199e: 689b ldr r3, [r3, #8]
80019a0: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80019a2: 697b ldr r3, [r7, #20]
80019a4: f403 3280 and.w r2, r3, #65536 @ 0x10000
80019a8: 687b ldr r3, [r7, #4]
80019aa: 6a9b ldr r3, [r3, #40] @ 0x28
80019ac: 429a cmp r2, r3
80019ae: d10d bne.n 80019cc <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
80019b0: 697b ldr r3, [r7, #20]
80019b2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
80019b6: 687b ldr r3, [r7, #4]
80019b8: 6adb ldr r3, [r3, #44] @ 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80019ba: 429a cmp r2, r3
80019bc: d106 bne.n 80019cc <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
80019be: 697b ldr r3, [r7, #20]
80019c0: f403 0240 and.w r2, r3, #12582912 @ 0xc00000
80019c4: 687b ldr r3, [r7, #4]
80019c6: 6b1b ldr r3, [r3, #48] @ 0x30
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
80019c8: 429a cmp r2, r3
80019ca: d001 beq.n 80019d0 <HAL_RCC_OscConfig+0x64c>
{
return HAL_ERROR;
80019cc: 2301 movs r3, #1
80019ce: e000 b.n 80019d2 <HAL_RCC_OscConfig+0x64e>
}
}
}
}
return HAL_OK;
80019d0: 2300 movs r3, #0
}
80019d2: 4618 mov r0, r3
80019d4: 3720 adds r7, #32
80019d6: 46bd mov sp, r7
80019d8: bd80 pop {r7, pc}
80019da: bf00 nop
80019dc: 40023800 .word 0x40023800
80019e0: 42470060 .word 0x42470060
080019e4 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80019e4: b580 push {r7, lr}
80019e6: b084 sub sp, #16
80019e8: af00 add r7, sp, #0
80019ea: 6078 str r0, [r7, #4]
80019ec: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status;
/* Check the parameters */
if(RCC_ClkInitStruct == NULL)
80019ee: 687b ldr r3, [r7, #4]
80019f0: 2b00 cmp r3, #0
80019f2: d101 bne.n 80019f8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80019f4: 2301 movs r3, #1
80019f6: e11a b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80019f8: 4b8f ldr r3, [pc, #572] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
80019fa: 681b ldr r3, [r3, #0]
80019fc: f003 0301 and.w r3, r3, #1
8001a00: 683a ldr r2, [r7, #0]
8001a02: 429a cmp r2, r3
8001a04: d919 bls.n 8001a3a <HAL_RCC_ClockConfig+0x56>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001a06: 683b ldr r3, [r7, #0]
8001a08: 2b01 cmp r3, #1
8001a0a: d105 bne.n 8001a18 <HAL_RCC_ClockConfig+0x34>
8001a0c: 4b8a ldr r3, [pc, #552] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001a0e: 681b ldr r3, [r3, #0]
8001a10: 4a89 ldr r2, [pc, #548] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001a12: f043 0304 orr.w r3, r3, #4
8001a16: 6013 str r3, [r2, #0]
8001a18: 4b87 ldr r3, [pc, #540] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001a1a: 681b ldr r3, [r3, #0]
8001a1c: f023 0201 bic.w r2, r3, #1
8001a20: 4985 ldr r1, [pc, #532] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001a22: 683b ldr r3, [r7, #0]
8001a24: 4313 orrs r3, r2
8001a26: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001a28: 4b83 ldr r3, [pc, #524] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001a2a: 681b ldr r3, [r3, #0]
8001a2c: f003 0301 and.w r3, r3, #1
8001a30: 683a ldr r2, [r7, #0]
8001a32: 429a cmp r2, r3
8001a34: d001 beq.n 8001a3a <HAL_RCC_ClockConfig+0x56>
{
return HAL_ERROR;
8001a36: 2301 movs r3, #1
8001a38: e0f9 b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001a3a: 687b ldr r3, [r7, #4]
8001a3c: 681b ldr r3, [r3, #0]
8001a3e: f003 0302 and.w r3, r3, #2
8001a42: 2b00 cmp r3, #0
8001a44: d008 beq.n 8001a58 <HAL_RCC_ClockConfig+0x74>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001a46: 4b7d ldr r3, [pc, #500] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001a48: 689b ldr r3, [r3, #8]
8001a4a: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8001a4e: 687b ldr r3, [r7, #4]
8001a50: 689b ldr r3, [r3, #8]
8001a52: 497a ldr r1, [pc, #488] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001a54: 4313 orrs r3, r2
8001a56: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001a58: 687b ldr r3, [r7, #4]
8001a5a: 681b ldr r3, [r3, #0]
8001a5c: f003 0301 and.w r3, r3, #1
8001a60: 2b00 cmp r3, #0
8001a62: f000 808e beq.w 8001b82 <HAL_RCC_ClockConfig+0x19e>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001a66: 687b ldr r3, [r7, #4]
8001a68: 685b ldr r3, [r3, #4]
8001a6a: 2b02 cmp r3, #2
8001a6c: d107 bne.n 8001a7e <HAL_RCC_ClockConfig+0x9a>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8001a6e: 4b73 ldr r3, [pc, #460] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001a70: 681b ldr r3, [r3, #0]
8001a72: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001a76: 2b00 cmp r3, #0
8001a78: d121 bne.n 8001abe <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8001a7a: 2301 movs r3, #1
8001a7c: e0d7 b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001a7e: 687b ldr r3, [r7, #4]
8001a80: 685b ldr r3, [r3, #4]
8001a82: 2b03 cmp r3, #3
8001a84: d107 bne.n 8001a96 <HAL_RCC_ClockConfig+0xb2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001a86: 4b6d ldr r3, [pc, #436] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001a88: 681b ldr r3, [r3, #0]
8001a8a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001a8e: 2b00 cmp r3, #0
8001a90: d115 bne.n 8001abe <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8001a92: 2301 movs r3, #1
8001a94: e0cb b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
}
}
/* HSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8001a96: 687b ldr r3, [r7, #4]
8001a98: 685b ldr r3, [r3, #4]
8001a9a: 2b01 cmp r3, #1
8001a9c: d107 bne.n 8001aae <HAL_RCC_ClockConfig+0xca>
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8001a9e: 4b67 ldr r3, [pc, #412] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001aa0: 681b ldr r3, [r3, #0]
8001aa2: f003 0302 and.w r3, r3, #2
8001aa6: 2b00 cmp r3, #0
8001aa8: d109 bne.n 8001abe <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8001aaa: 2301 movs r3, #1
8001aac: e0bf b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
}
/* MSI is selected as System Clock Source */
else
{
/* Check the MSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
8001aae: 4b63 ldr r3, [pc, #396] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001ab0: 681b ldr r3, [r3, #0]
8001ab2: f403 7300 and.w r3, r3, #512 @ 0x200
8001ab6: 2b00 cmp r3, #0
8001ab8: d101 bne.n 8001abe <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8001aba: 2301 movs r3, #1
8001abc: e0b7 b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001abe: 4b5f ldr r3, [pc, #380] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001ac0: 689b ldr r3, [r3, #8]
8001ac2: f023 0203 bic.w r2, r3, #3
8001ac6: 687b ldr r3, [r7, #4]
8001ac8: 685b ldr r3, [r3, #4]
8001aca: 495c ldr r1, [pc, #368] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001acc: 4313 orrs r3, r2
8001ace: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ad0: f7ff f954 bl 8000d7c <HAL_GetTick>
8001ad4: 60f8 str r0, [r7, #12]
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001ad6: 687b ldr r3, [r7, #4]
8001ad8: 685b ldr r3, [r3, #4]
8001ada: 2b02 cmp r3, #2
8001adc: d112 bne.n 8001b04 <HAL_RCC_ClockConfig+0x120>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
8001ade: e00a b.n 8001af6 <HAL_RCC_ClockConfig+0x112>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001ae0: f7ff f94c bl 8000d7c <HAL_GetTick>
8001ae4: 4602 mov r2, r0
8001ae6: 68fb ldr r3, [r7, #12]
8001ae8: 1ad3 subs r3, r2, r3
8001aea: f241 3288 movw r2, #5000 @ 0x1388
8001aee: 4293 cmp r3, r2
8001af0: d901 bls.n 8001af6 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8001af2: 2303 movs r3, #3
8001af4: e09b b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
8001af6: 4b51 ldr r3, [pc, #324] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001af8: 689b ldr r3, [r3, #8]
8001afa: f003 030c and.w r3, r3, #12
8001afe: 2b08 cmp r3, #8
8001b00: d1ee bne.n 8001ae0 <HAL_RCC_ClockConfig+0xfc>
8001b02: e03e b.n 8001b82 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001b04: 687b ldr r3, [r7, #4]
8001b06: 685b ldr r3, [r3, #4]
8001b08: 2b03 cmp r3, #3
8001b0a: d112 bne.n 8001b32 <HAL_RCC_ClockConfig+0x14e>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001b0c: e00a b.n 8001b24 <HAL_RCC_ClockConfig+0x140>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001b0e: f7ff f935 bl 8000d7c <HAL_GetTick>
8001b12: 4602 mov r2, r0
8001b14: 68fb ldr r3, [r7, #12]
8001b16: 1ad3 subs r3, r2, r3
8001b18: f241 3288 movw r2, #5000 @ 0x1388
8001b1c: 4293 cmp r3, r2
8001b1e: d901 bls.n 8001b24 <HAL_RCC_ClockConfig+0x140>
{
return HAL_TIMEOUT;
8001b20: 2303 movs r3, #3
8001b22: e084 b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001b24: 4b45 ldr r3, [pc, #276] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001b26: 689b ldr r3, [r3, #8]
8001b28: f003 030c and.w r3, r3, #12
8001b2c: 2b0c cmp r3, #12
8001b2e: d1ee bne.n 8001b0e <HAL_RCC_ClockConfig+0x12a>
8001b30: e027 b.n 8001b82 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8001b32: 687b ldr r3, [r7, #4]
8001b34: 685b ldr r3, [r3, #4]
8001b36: 2b01 cmp r3, #1
8001b38: d11d bne.n 8001b76 <HAL_RCC_ClockConfig+0x192>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
8001b3a: e00a b.n 8001b52 <HAL_RCC_ClockConfig+0x16e>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001b3c: f7ff f91e bl 8000d7c <HAL_GetTick>
8001b40: 4602 mov r2, r0
8001b42: 68fb ldr r3, [r7, #12]
8001b44: 1ad3 subs r3, r2, r3
8001b46: f241 3288 movw r2, #5000 @ 0x1388
8001b4a: 4293 cmp r3, r2
8001b4c: d901 bls.n 8001b52 <HAL_RCC_ClockConfig+0x16e>
{
return HAL_TIMEOUT;
8001b4e: 2303 movs r3, #3
8001b50: e06d b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
8001b52: 4b3a ldr r3, [pc, #232] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001b54: 689b ldr r3, [r3, #8]
8001b56: f003 030c and.w r3, r3, #12
8001b5a: 2b04 cmp r3, #4
8001b5c: d1ee bne.n 8001b3c <HAL_RCC_ClockConfig+0x158>
8001b5e: e010 b.n 8001b82 <HAL_RCC_ClockConfig+0x19e>
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001b60: f7ff f90c bl 8000d7c <HAL_GetTick>
8001b64: 4602 mov r2, r0
8001b66: 68fb ldr r3, [r7, #12]
8001b68: 1ad3 subs r3, r2, r3
8001b6a: f241 3288 movw r2, #5000 @ 0x1388
8001b6e: 4293 cmp r3, r2
8001b70: d901 bls.n 8001b76 <HAL_RCC_ClockConfig+0x192>
{
return HAL_TIMEOUT;
8001b72: 2303 movs r3, #3
8001b74: e05b b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
8001b76: 4b31 ldr r3, [pc, #196] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001b78: 689b ldr r3, [r3, #8]
8001b7a: f003 030c and.w r3, r3, #12
8001b7e: 2b00 cmp r3, #0
8001b80: d1ee bne.n 8001b60 <HAL_RCC_ClockConfig+0x17c>
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001b82: 4b2d ldr r3, [pc, #180] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001b84: 681b ldr r3, [r3, #0]
8001b86: f003 0301 and.w r3, r3, #1
8001b8a: 683a ldr r2, [r7, #0]
8001b8c: 429a cmp r2, r3
8001b8e: d219 bcs.n 8001bc4 <HAL_RCC_ClockConfig+0x1e0>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001b90: 683b ldr r3, [r7, #0]
8001b92: 2b01 cmp r3, #1
8001b94: d105 bne.n 8001ba2 <HAL_RCC_ClockConfig+0x1be>
8001b96: 4b28 ldr r3, [pc, #160] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001b98: 681b ldr r3, [r3, #0]
8001b9a: 4a27 ldr r2, [pc, #156] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001b9c: f043 0304 orr.w r3, r3, #4
8001ba0: 6013 str r3, [r2, #0]
8001ba2: 4b25 ldr r3, [pc, #148] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001ba4: 681b ldr r3, [r3, #0]
8001ba6: f023 0201 bic.w r2, r3, #1
8001baa: 4923 ldr r1, [pc, #140] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001bac: 683b ldr r3, [r7, #0]
8001bae: 4313 orrs r3, r2
8001bb0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001bb2: 4b21 ldr r3, [pc, #132] @ (8001c38 <HAL_RCC_ClockConfig+0x254>)
8001bb4: 681b ldr r3, [r3, #0]
8001bb6: f003 0301 and.w r3, r3, #1
8001bba: 683a ldr r2, [r7, #0]
8001bbc: 429a cmp r2, r3
8001bbe: d001 beq.n 8001bc4 <HAL_RCC_ClockConfig+0x1e0>
{
return HAL_ERROR;
8001bc0: 2301 movs r3, #1
8001bc2: e034 b.n 8001c2e <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001bc4: 687b ldr r3, [r7, #4]
8001bc6: 681b ldr r3, [r3, #0]
8001bc8: f003 0304 and.w r3, r3, #4
8001bcc: 2b00 cmp r3, #0
8001bce: d008 beq.n 8001be2 <HAL_RCC_ClockConfig+0x1fe>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001bd0: 4b1a ldr r3, [pc, #104] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001bd2: 689b ldr r3, [r3, #8]
8001bd4: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8001bd8: 687b ldr r3, [r7, #4]
8001bda: 68db ldr r3, [r3, #12]
8001bdc: 4917 ldr r1, [pc, #92] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001bde: 4313 orrs r3, r2
8001be0: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001be2: 687b ldr r3, [r7, #4]
8001be4: 681b ldr r3, [r3, #0]
8001be6: f003 0308 and.w r3, r3, #8
8001bea: 2b00 cmp r3, #0
8001bec: d009 beq.n 8001c02 <HAL_RCC_ClockConfig+0x21e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8001bee: 4b13 ldr r3, [pc, #76] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001bf0: 689b ldr r3, [r3, #8]
8001bf2: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8001bf6: 687b ldr r3, [r7, #4]
8001bf8: 691b ldr r3, [r3, #16]
8001bfa: 00db lsls r3, r3, #3
8001bfc: 490f ldr r1, [pc, #60] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001bfe: 4313 orrs r3, r2
8001c00: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001c02: f000 f823 bl 8001c4c <HAL_RCC_GetSysClockFreq>
8001c06: 4602 mov r2, r0
8001c08: 4b0c ldr r3, [pc, #48] @ (8001c3c <HAL_RCC_ClockConfig+0x258>)
8001c0a: 689b ldr r3, [r3, #8]
8001c0c: 091b lsrs r3, r3, #4
8001c0e: f003 030f and.w r3, r3, #15
8001c12: 490b ldr r1, [pc, #44] @ (8001c40 <HAL_RCC_ClockConfig+0x25c>)
8001c14: 5ccb ldrb r3, [r1, r3]
8001c16: fa22 f303 lsr.w r3, r2, r3
8001c1a: 4a0a ldr r2, [pc, #40] @ (8001c44 <HAL_RCC_ClockConfig+0x260>)
8001c1c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
8001c1e: 4b0a ldr r3, [pc, #40] @ (8001c48 <HAL_RCC_ClockConfig+0x264>)
8001c20: 681b ldr r3, [r3, #0]
8001c22: 4618 mov r0, r3
8001c24: f7ff f85e bl 8000ce4 <HAL_InitTick>
8001c28: 4603 mov r3, r0
8001c2a: 72fb strb r3, [r7, #11]
return status;
8001c2c: 7afb ldrb r3, [r7, #11]
}
8001c2e: 4618 mov r0, r3
8001c30: 3710 adds r7, #16
8001c32: 46bd mov sp, r7
8001c34: bd80 pop {r7, pc}
8001c36: bf00 nop
8001c38: 40023c00 .word 0x40023c00
8001c3c: 40023800 .word 0x40023800
8001c40: 08002eb0 .word 0x08002eb0
8001c44: 20000000 .word 0x20000000
8001c48: 20000004 .word 0x20000004
08001c4c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001c4c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001c50: b08e sub sp, #56 @ 0x38
8001c52: af00 add r7, sp, #0
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
tmpreg = RCC->CFGR;
8001c54: 4b58 ldr r3, [pc, #352] @ (8001db8 <HAL_RCC_GetSysClockFreq+0x16c>)
8001c56: 689b ldr r3, [r3, #8]
8001c58: 62fb str r3, [r7, #44] @ 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8001c5a: 6afb ldr r3, [r7, #44] @ 0x2c
8001c5c: f003 030c and.w r3, r3, #12
8001c60: 2b0c cmp r3, #12
8001c62: d00d beq.n 8001c80 <HAL_RCC_GetSysClockFreq+0x34>
8001c64: 2b0c cmp r3, #12
8001c66: f200 8092 bhi.w 8001d8e <HAL_RCC_GetSysClockFreq+0x142>
8001c6a: 2b04 cmp r3, #4
8001c6c: d002 beq.n 8001c74 <HAL_RCC_GetSysClockFreq+0x28>
8001c6e: 2b08 cmp r3, #8
8001c70: d003 beq.n 8001c7a <HAL_RCC_GetSysClockFreq+0x2e>
8001c72: e08c b.n 8001d8e <HAL_RCC_GetSysClockFreq+0x142>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001c74: 4b51 ldr r3, [pc, #324] @ (8001dbc <HAL_RCC_GetSysClockFreq+0x170>)
8001c76: 633b str r3, [r7, #48] @ 0x30
break;
8001c78: e097 b.n 8001daa <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8001c7a: 4b51 ldr r3, [pc, #324] @ (8001dc0 <HAL_RCC_GetSysClockFreq+0x174>)
8001c7c: 633b str r3, [r7, #48] @ 0x30
break;
8001c7e: e094 b.n 8001daa <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
8001c80: 6afb ldr r3, [r7, #44] @ 0x2c
8001c82: 0c9b lsrs r3, r3, #18
8001c84: f003 020f and.w r2, r3, #15
8001c88: 4b4e ldr r3, [pc, #312] @ (8001dc4 <HAL_RCC_GetSysClockFreq+0x178>)
8001c8a: 5c9b ldrb r3, [r3, r2]
8001c8c: 62bb str r3, [r7, #40] @ 0x28
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
8001c8e: 6afb ldr r3, [r7, #44] @ 0x2c
8001c90: 0d9b lsrs r3, r3, #22
8001c92: f003 0303 and.w r3, r3, #3
8001c96: 3301 adds r3, #1
8001c98: 627b str r3, [r7, #36] @ 0x24
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8001c9a: 4b47 ldr r3, [pc, #284] @ (8001db8 <HAL_RCC_GetSysClockFreq+0x16c>)
8001c9c: 689b ldr r3, [r3, #8]
8001c9e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001ca2: 2b00 cmp r3, #0
8001ca4: d021 beq.n 8001cea <HAL_RCC_GetSysClockFreq+0x9e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
8001ca6: 6abb ldr r3, [r7, #40] @ 0x28
8001ca8: 2200 movs r2, #0
8001caa: 61bb str r3, [r7, #24]
8001cac: 61fa str r2, [r7, #28]
8001cae: 4b44 ldr r3, [pc, #272] @ (8001dc0 <HAL_RCC_GetSysClockFreq+0x174>)
8001cb0: e9d7 8906 ldrd r8, r9, [r7, #24]
8001cb4: 464a mov r2, r9
8001cb6: fb03 f202 mul.w r2, r3, r2
8001cba: 2300 movs r3, #0
8001cbc: 4644 mov r4, r8
8001cbe: fb04 f303 mul.w r3, r4, r3
8001cc2: 4413 add r3, r2
8001cc4: 4a3e ldr r2, [pc, #248] @ (8001dc0 <HAL_RCC_GetSysClockFreq+0x174>)
8001cc6: 4644 mov r4, r8
8001cc8: fba4 0102 umull r0, r1, r4, r2
8001ccc: 440b add r3, r1
8001cce: 4619 mov r1, r3
8001cd0: 6a7b ldr r3, [r7, #36] @ 0x24
8001cd2: 2200 movs r2, #0
8001cd4: 613b str r3, [r7, #16]
8001cd6: 617a str r2, [r7, #20]
8001cd8: e9d7 2304 ldrd r2, r3, [r7, #16]
8001cdc: f7fe fa4e bl 800017c <__aeabi_uldivmod>
8001ce0: 4602 mov r2, r0
8001ce2: 460b mov r3, r1
8001ce4: 4613 mov r3, r2
8001ce6: 637b str r3, [r7, #52] @ 0x34
8001ce8: e04e b.n 8001d88 <HAL_RCC_GetSysClockFreq+0x13c>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
8001cea: 6abb ldr r3, [r7, #40] @ 0x28
8001cec: 2200 movs r2, #0
8001cee: 469a mov sl, r3
8001cf0: 4693 mov fp, r2
8001cf2: 4652 mov r2, sl
8001cf4: 465b mov r3, fp
8001cf6: f04f 0000 mov.w r0, #0
8001cfa: f04f 0100 mov.w r1, #0
8001cfe: 0159 lsls r1, r3, #5
8001d00: ea41 61d2 orr.w r1, r1, r2, lsr #27
8001d04: 0150 lsls r0, r2, #5
8001d06: 4602 mov r2, r0
8001d08: 460b mov r3, r1
8001d0a: ebb2 080a subs.w r8, r2, sl
8001d0e: eb63 090b sbc.w r9, r3, fp
8001d12: f04f 0200 mov.w r2, #0
8001d16: f04f 0300 mov.w r3, #0
8001d1a: ea4f 1389 mov.w r3, r9, lsl #6
8001d1e: ea43 6398 orr.w r3, r3, r8, lsr #26
8001d22: ea4f 1288 mov.w r2, r8, lsl #6
8001d26: ebb2 0408 subs.w r4, r2, r8
8001d2a: eb63 0509 sbc.w r5, r3, r9
8001d2e: f04f 0200 mov.w r2, #0
8001d32: f04f 0300 mov.w r3, #0
8001d36: 00eb lsls r3, r5, #3
8001d38: ea43 7354 orr.w r3, r3, r4, lsr #29
8001d3c: 00e2 lsls r2, r4, #3
8001d3e: 4614 mov r4, r2
8001d40: 461d mov r5, r3
8001d42: eb14 030a adds.w r3, r4, sl
8001d46: 603b str r3, [r7, #0]
8001d48: eb45 030b adc.w r3, r5, fp
8001d4c: 607b str r3, [r7, #4]
8001d4e: f04f 0200 mov.w r2, #0
8001d52: f04f 0300 mov.w r3, #0
8001d56: e9d7 4500 ldrd r4, r5, [r7]
8001d5a: 4629 mov r1, r5
8001d5c: 028b lsls r3, r1, #10
8001d5e: 4620 mov r0, r4
8001d60: 4629 mov r1, r5
8001d62: 4604 mov r4, r0
8001d64: ea43 5394 orr.w r3, r3, r4, lsr #22
8001d68: 4601 mov r1, r0
8001d6a: 028a lsls r2, r1, #10
8001d6c: 4610 mov r0, r2
8001d6e: 4619 mov r1, r3
8001d70: 6a7b ldr r3, [r7, #36] @ 0x24
8001d72: 2200 movs r2, #0
8001d74: 60bb str r3, [r7, #8]
8001d76: 60fa str r2, [r7, #12]
8001d78: e9d7 2302 ldrd r2, r3, [r7, #8]
8001d7c: f7fe f9fe bl 800017c <__aeabi_uldivmod>
8001d80: 4602 mov r2, r0
8001d82: 460b mov r3, r1
8001d84: 4613 mov r3, r2
8001d86: 637b str r3, [r7, #52] @ 0x34
}
sysclockfreq = pllvco;
8001d88: 6b7b ldr r3, [r7, #52] @ 0x34
8001d8a: 633b str r3, [r7, #48] @ 0x30
break;
8001d8c: e00d b.n 8001daa <HAL_RCC_GetSysClockFreq+0x15e>
}
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
default: /* MSI used as system clock */
{
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
8001d8e: 4b0a ldr r3, [pc, #40] @ (8001db8 <HAL_RCC_GetSysClockFreq+0x16c>)
8001d90: 685b ldr r3, [r3, #4]
8001d92: 0b5b lsrs r3, r3, #13
8001d94: f003 0307 and.w r3, r3, #7
8001d98: 623b str r3, [r7, #32]
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
8001d9a: 6a3b ldr r3, [r7, #32]
8001d9c: 3301 adds r3, #1
8001d9e: f44f 4200 mov.w r2, #32768 @ 0x8000
8001da2: fa02 f303 lsl.w r3, r2, r3
8001da6: 633b str r3, [r7, #48] @ 0x30
break;
8001da8: bf00 nop
}
}
return sysclockfreq;
8001daa: 6b3b ldr r3, [r7, #48] @ 0x30
}
8001dac: 4618 mov r0, r3
8001dae: 3738 adds r7, #56 @ 0x38
8001db0: 46bd mov sp, r7
8001db2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001db6: bf00 nop
8001db8: 40023800 .word 0x40023800
8001dbc: 00f42400 .word 0x00f42400
8001dc0: 016e3600 .word 0x016e3600
8001dc4: 08002ea4 .word 0x08002ea4
08001dc8 <RCC_SetFlashLatencyFromMSIRange>:
voltage range
* @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
8001dc8: b480 push {r7}
8001dca: b087 sub sp, #28
8001dcc: af00 add r7, sp, #0
8001dce: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
8001dd0: 2300 movs r3, #0
8001dd2: 613b str r3, [r7, #16]
/* HCLK can reach 4 MHz only if AHB prescaler = 1 */
if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
8001dd4: 4b29 ldr r3, [pc, #164] @ (8001e7c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001dd6: 689b ldr r3, [r3, #8]
8001dd8: f003 03f0 and.w r3, r3, #240 @ 0xf0
8001ddc: 2b00 cmp r3, #0
8001dde: d12c bne.n 8001e3a <RCC_SetFlashLatencyFromMSIRange+0x72>
{
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
8001de0: 4b26 ldr r3, [pc, #152] @ (8001e7c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001de2: 6a5b ldr r3, [r3, #36] @ 0x24
8001de4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001de8: 2b00 cmp r3, #0
8001dea: d005 beq.n 8001df8 <RCC_SetFlashLatencyFromMSIRange+0x30>
{
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
8001dec: 4b24 ldr r3, [pc, #144] @ (8001e80 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8001dee: 681b ldr r3, [r3, #0]
8001df0: f403 53c0 and.w r3, r3, #6144 @ 0x1800
8001df4: 617b str r3, [r7, #20]
8001df6: e016 b.n 8001e26 <RCC_SetFlashLatencyFromMSIRange+0x5e>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
8001df8: 4b20 ldr r3, [pc, #128] @ (8001e7c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001dfa: 6a5b ldr r3, [r3, #36] @ 0x24
8001dfc: 4a1f ldr r2, [pc, #124] @ (8001e7c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001dfe: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001e02: 6253 str r3, [r2, #36] @ 0x24
8001e04: 4b1d ldr r3, [pc, #116] @ (8001e7c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001e06: 6a5b ldr r3, [r3, #36] @ 0x24
8001e08: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001e0c: 60fb str r3, [r7, #12]
8001e0e: 68fb ldr r3, [r7, #12]
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
8001e10: 4b1b ldr r3, [pc, #108] @ (8001e80 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
8001e12: 681b ldr r3, [r3, #0]
8001e14: f403 53c0 and.w r3, r3, #6144 @ 0x1800
8001e18: 617b str r3, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
8001e1a: 4b18 ldr r3, [pc, #96] @ (8001e7c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001e1c: 6a5b ldr r3, [r3, #36] @ 0x24
8001e1e: 4a17 ldr r2, [pc, #92] @ (8001e7c <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001e20: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8001e24: 6253 str r3, [r2, #36] @ 0x24
}
/* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
8001e26: 697b ldr r3, [r7, #20]
8001e28: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800
8001e2c: d105 bne.n 8001e3a <RCC_SetFlashLatencyFromMSIRange+0x72>
8001e2e: 687b ldr r3, [r7, #4]
8001e30: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8001e34: d101 bne.n 8001e3a <RCC_SetFlashLatencyFromMSIRange+0x72>
{
latency = FLASH_LATENCY_1; /* 1WS */
8001e36: 2301 movs r3, #1
8001e38: 613b str r3, [r7, #16]
}
}
__HAL_FLASH_SET_LATENCY(latency);
8001e3a: 693b ldr r3, [r7, #16]
8001e3c: 2b01 cmp r3, #1
8001e3e: d105 bne.n 8001e4c <RCC_SetFlashLatencyFromMSIRange+0x84>
8001e40: 4b10 ldr r3, [pc, #64] @ (8001e84 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001e42: 681b ldr r3, [r3, #0]
8001e44: 4a0f ldr r2, [pc, #60] @ (8001e84 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001e46: f043 0304 orr.w r3, r3, #4
8001e4a: 6013 str r3, [r2, #0]
8001e4c: 4b0d ldr r3, [pc, #52] @ (8001e84 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001e4e: 681b ldr r3, [r3, #0]
8001e50: f023 0201 bic.w r2, r3, #1
8001e54: 490b ldr r1, [pc, #44] @ (8001e84 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001e56: 693b ldr r3, [r7, #16]
8001e58: 4313 orrs r3, r2
8001e5a: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
8001e5c: 4b09 ldr r3, [pc, #36] @ (8001e84 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001e5e: 681b ldr r3, [r3, #0]
8001e60: f003 0301 and.w r3, r3, #1
8001e64: 693a ldr r2, [r7, #16]
8001e66: 429a cmp r2, r3
8001e68: d001 beq.n 8001e6e <RCC_SetFlashLatencyFromMSIRange+0xa6>
{
return HAL_ERROR;
8001e6a: 2301 movs r3, #1
8001e6c: e000 b.n 8001e70 <RCC_SetFlashLatencyFromMSIRange+0xa8>
}
return HAL_OK;
8001e6e: 2300 movs r3, #0
}
8001e70: 4618 mov r0, r3
8001e72: 371c adds r7, #28
8001e74: 46bd mov sp, r7
8001e76: bc80 pop {r7}
8001e78: 4770 bx lr
8001e7a: bf00 nop
8001e7c: 40023800 .word 0x40023800
8001e80: 40007000 .word 0x40007000
8001e84: 40023c00 .word 0x40023c00
08001e88 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8001e88: b580 push {r7, lr}
8001e8a: b082 sub sp, #8
8001e8c: af00 add r7, sp, #0
8001e8e: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
8001e90: 687b ldr r3, [r7, #4]
8001e92: 2b00 cmp r3, #0
8001e94: d101 bne.n 8001e9a <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8001e96: 2301 movs r3, #1
8001e98: e07b b.n 8001f92 <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
/* TI mode is not supported on all devices in stm32l1xx series.
TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 6a5b ldr r3, [r3, #36] @ 0x24
8001e9e: 2b00 cmp r3, #0
8001ea0: d108 bne.n 8001eb4 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 685b ldr r3, [r3, #4]
8001ea6: f5b3 7f82 cmp.w r3, #260 @ 0x104
8001eaa: d009 beq.n 8001ec0 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8001eac: 687b ldr r3, [r7, #4]
8001eae: 2200 movs r2, #0
8001eb0: 61da str r2, [r3, #28]
8001eb2: e005 b.n 8001ec0 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 2200 movs r2, #0
8001eb8: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8001eba: 687b ldr r3, [r7, #4]
8001ebc: 2200 movs r2, #0
8001ebe: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8001ec0: 687b ldr r3, [r7, #4]
8001ec2: 2200 movs r2, #0
8001ec4: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8001ec6: 687b ldr r3, [r7, #4]
8001ec8: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
8001ecc: b2db uxtb r3, r3
8001ece: 2b00 cmp r3, #0
8001ed0: d106 bne.n 8001ee0 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8001ed2: 687b ldr r3, [r7, #4]
8001ed4: 2200 movs r2, #0
8001ed6: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8001eda: 6878 ldr r0, [r7, #4]
8001edc: f7fe fd5a bl 8000994 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8001ee0: 687b ldr r3, [r7, #4]
8001ee2: 2202 movs r2, #2
8001ee4: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8001ee8: 687b ldr r3, [r7, #4]
8001eea: 681b ldr r3, [r3, #0]
8001eec: 681a ldr r2, [r3, #0]
8001eee: 687b ldr r3, [r7, #4]
8001ef0: 681b ldr r3, [r3, #0]
8001ef2: f022 0240 bic.w r2, r2, #64 @ 0x40
8001ef6: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
8001ef8: 687b ldr r3, [r7, #4]
8001efa: 685b ldr r3, [r3, #4]
8001efc: f403 7282 and.w r2, r3, #260 @ 0x104
8001f00: 687b ldr r3, [r7, #4]
8001f02: 689b ldr r3, [r3, #8]
8001f04: f403 4304 and.w r3, r3, #33792 @ 0x8400
8001f08: 431a orrs r2, r3
8001f0a: 687b ldr r3, [r7, #4]
8001f0c: 68db ldr r3, [r3, #12]
8001f0e: f403 6300 and.w r3, r3, #2048 @ 0x800
8001f12: 431a orrs r2, r3
8001f14: 687b ldr r3, [r7, #4]
8001f16: 691b ldr r3, [r3, #16]
8001f18: f003 0302 and.w r3, r3, #2
8001f1c: 431a orrs r2, r3
8001f1e: 687b ldr r3, [r7, #4]
8001f20: 695b ldr r3, [r3, #20]
8001f22: f003 0301 and.w r3, r3, #1
8001f26: 431a orrs r2, r3
8001f28: 687b ldr r3, [r7, #4]
8001f2a: 699b ldr r3, [r3, #24]
8001f2c: f403 7300 and.w r3, r3, #512 @ 0x200
8001f30: 431a orrs r2, r3
8001f32: 687b ldr r3, [r7, #4]
8001f34: 69db ldr r3, [r3, #28]
8001f36: f003 0338 and.w r3, r3, #56 @ 0x38
8001f3a: 431a orrs r2, r3
8001f3c: 687b ldr r3, [r7, #4]
8001f3e: 6a1b ldr r3, [r3, #32]
8001f40: f003 0380 and.w r3, r3, #128 @ 0x80
8001f44: ea42 0103 orr.w r1, r2, r3
8001f48: 687b ldr r3, [r7, #4]
8001f4a: 6a9b ldr r3, [r3, #40] @ 0x28
8001f4c: f403 5200 and.w r2, r3, #8192 @ 0x2000
8001f50: 687b ldr r3, [r7, #4]
8001f52: 681b ldr r3, [r3, #0]
8001f54: 430a orrs r2, r1
8001f56: 601a str r2, [r3, #0]
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
#if defined(SPI_CR2_FRF)
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
8001f58: 687b ldr r3, [r7, #4]
8001f5a: 699b ldr r3, [r3, #24]
8001f5c: 0c1b lsrs r3, r3, #16
8001f5e: f003 0104 and.w r1, r3, #4
8001f62: 687b ldr r3, [r7, #4]
8001f64: 6a5b ldr r3, [r3, #36] @ 0x24
8001f66: f003 0210 and.w r2, r3, #16
8001f6a: 687b ldr r3, [r7, #4]
8001f6c: 681b ldr r3, [r3, #0]
8001f6e: 430a orrs r2, r1
8001f70: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8001f72: 687b ldr r3, [r7, #4]
8001f74: 681b ldr r3, [r3, #0]
8001f76: 69da ldr r2, [r3, #28]
8001f78: 687b ldr r3, [r7, #4]
8001f7a: 681b ldr r3, [r3, #0]
8001f7c: f422 6200 bic.w r2, r2, #2048 @ 0x800
8001f80: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001f82: 687b ldr r3, [r7, #4]
8001f84: 2200 movs r2, #0
8001f86: 655a str r2, [r3, #84] @ 0x54
hspi->State = HAL_SPI_STATE_READY;
8001f88: 687b ldr r3, [r7, #4]
8001f8a: 2201 movs r2, #1
8001f8c: f883 2051 strb.w r2, [r3, #81] @ 0x51
return HAL_OK;
8001f90: 2300 movs r3, #0
}
8001f92: 4618 mov r0, r3
8001f94: 3708 adds r7, #8
8001f96: 46bd mov sp, r7
8001f98: bd80 pop {r7, pc}
08001f9a <HAL_SPI_Transmit>:
* @param Size amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration in ms
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8001f9a: b580 push {r7, lr}
8001f9c: b088 sub sp, #32
8001f9e: af00 add r7, sp, #0
8001fa0: 60f8 str r0, [r7, #12]
8001fa2: 60b9 str r1, [r7, #8]
8001fa4: 603b str r3, [r7, #0]
8001fa6: 4613 mov r3, r2
8001fa8: 80fb strh r3, [r7, #6]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8001faa: f7fe fee7 bl 8000d7c <HAL_GetTick>
8001fae: 61f8 str r0, [r7, #28]
initial_TxXferCount = Size;
8001fb0: 88fb ldrh r3, [r7, #6]
8001fb2: 837b strh r3, [r7, #26]
if (hspi->State != HAL_SPI_STATE_READY)
8001fb4: 68fb ldr r3, [r7, #12]
8001fb6: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
8001fba: b2db uxtb r3, r3
8001fbc: 2b01 cmp r3, #1
8001fbe: d001 beq.n 8001fc4 <HAL_SPI_Transmit+0x2a>
{
return HAL_BUSY;
8001fc0: 2302 movs r3, #2
8001fc2: e12a b.n 800221a <HAL_SPI_Transmit+0x280>
}
if ((pData == NULL) || (Size == 0U))
8001fc4: 68bb ldr r3, [r7, #8]
8001fc6: 2b00 cmp r3, #0
8001fc8: d002 beq.n 8001fd0 <HAL_SPI_Transmit+0x36>
8001fca: 88fb ldrh r3, [r7, #6]
8001fcc: 2b00 cmp r3, #0
8001fce: d101 bne.n 8001fd4 <HAL_SPI_Transmit+0x3a>
{
return HAL_ERROR;
8001fd0: 2301 movs r3, #1
8001fd2: e122 b.n 800221a <HAL_SPI_Transmit+0x280>
}
/* Process Locked */
__HAL_LOCK(hspi);
8001fd4: 68fb ldr r3, [r7, #12]
8001fd6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
8001fda: 2b01 cmp r3, #1
8001fdc: d101 bne.n 8001fe2 <HAL_SPI_Transmit+0x48>
8001fde: 2302 movs r3, #2
8001fe0: e11b b.n 800221a <HAL_SPI_Transmit+0x280>
8001fe2: 68fb ldr r3, [r7, #12]
8001fe4: 2201 movs r2, #1
8001fe6: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
8001fea: 68fb ldr r3, [r7, #12]
8001fec: 2203 movs r2, #3
8001fee: f883 2051 strb.w r2, [r3, #81] @ 0x51
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8001ff2: 68fb ldr r3, [r7, #12]
8001ff4: 2200 movs r2, #0
8001ff6: 655a str r2, [r3, #84] @ 0x54
hspi->pTxBuffPtr = (const uint8_t *)pData;
8001ff8: 68fb ldr r3, [r7, #12]
8001ffa: 68ba ldr r2, [r7, #8]
8001ffc: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferSize = Size;
8001ffe: 68fb ldr r3, [r7, #12]
8002000: 88fa ldrh r2, [r7, #6]
8002002: 869a strh r2, [r3, #52] @ 0x34
hspi->TxXferCount = Size;
8002004: 68fb ldr r3, [r7, #12]
8002006: 88fa ldrh r2, [r7, #6]
8002008: 86da strh r2, [r3, #54] @ 0x36
/*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
800200a: 68fb ldr r3, [r7, #12]
800200c: 2200 movs r2, #0
800200e: 639a str r2, [r3, #56] @ 0x38
hspi->RxXferSize = 0U;
8002010: 68fb ldr r3, [r7, #12]
8002012: 2200 movs r2, #0
8002014: 879a strh r2, [r3, #60] @ 0x3c
hspi->RxXferCount = 0U;
8002016: 68fb ldr r3, [r7, #12]
8002018: 2200 movs r2, #0
800201a: 87da strh r2, [r3, #62] @ 0x3e
hspi->TxISR = NULL;
800201c: 68fb ldr r3, [r7, #12]
800201e: 2200 movs r2, #0
8002020: 645a str r2, [r3, #68] @ 0x44
hspi->RxISR = NULL;
8002022: 68fb ldr r3, [r7, #12]
8002024: 2200 movs r2, #0
8002026: 641a str r2, [r3, #64] @ 0x40
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
8002028: 68fb ldr r3, [r7, #12]
800202a: 689b ldr r3, [r3, #8]
800202c: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8002030: d10f bne.n 8002052 <HAL_SPI_Transmit+0xb8>
{
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
8002032: 68fb ldr r3, [r7, #12]
8002034: 681b ldr r3, [r3, #0]
8002036: 681a ldr r2, [r3, #0]
8002038: 68fb ldr r3, [r7, #12]
800203a: 681b ldr r3, [r3, #0]
800203c: f022 0240 bic.w r2, r2, #64 @ 0x40
8002040: 601a str r2, [r3, #0]
SPI_1LINE_TX(hspi);
8002042: 68fb ldr r3, [r7, #12]
8002044: 681b ldr r3, [r3, #0]
8002046: 681a ldr r2, [r3, #0]
8002048: 68fb ldr r3, [r7, #12]
800204a: 681b ldr r3, [r3, #0]
800204c: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8002050: 601a str r2, [r3, #0]
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8002052: 68fb ldr r3, [r7, #12]
8002054: 681b ldr r3, [r3, #0]
8002056: 681b ldr r3, [r3, #0]
8002058: f003 0340 and.w r3, r3, #64 @ 0x40
800205c: 2b40 cmp r3, #64 @ 0x40
800205e: d007 beq.n 8002070 <HAL_SPI_Transmit+0xd6>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
8002060: 68fb ldr r3, [r7, #12]
8002062: 681b ldr r3, [r3, #0]
8002064: 681a ldr r2, [r3, #0]
8002066: 68fb ldr r3, [r7, #12]
8002068: 681b ldr r3, [r3, #0]
800206a: f042 0240 orr.w r2, r2, #64 @ 0x40
800206e: 601a str r2, [r3, #0]
}
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
8002070: 68fb ldr r3, [r7, #12]
8002072: 68db ldr r3, [r3, #12]
8002074: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8002078: d152 bne.n 8002120 <HAL_SPI_Transmit+0x186>
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
800207a: 68fb ldr r3, [r7, #12]
800207c: 685b ldr r3, [r3, #4]
800207e: 2b00 cmp r3, #0
8002080: d002 beq.n 8002088 <HAL_SPI_Transmit+0xee>
8002082: 8b7b ldrh r3, [r7, #26]
8002084: 2b01 cmp r3, #1
8002086: d145 bne.n 8002114 <HAL_SPI_Transmit+0x17a>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
8002088: 68fb ldr r3, [r7, #12]
800208a: 6b1b ldr r3, [r3, #48] @ 0x30
800208c: 881a ldrh r2, [r3, #0]
800208e: 68fb ldr r3, [r7, #12]
8002090: 681b ldr r3, [r3, #0]
8002092: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8002094: 68fb ldr r3, [r7, #12]
8002096: 6b1b ldr r3, [r3, #48] @ 0x30
8002098: 1c9a adds r2, r3, #2
800209a: 68fb ldr r3, [r7, #12]
800209c: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
800209e: 68fb ldr r3, [r7, #12]
80020a0: 8edb ldrh r3, [r3, #54] @ 0x36
80020a2: b29b uxth r3, r3
80020a4: 3b01 subs r3, #1
80020a6: b29a uxth r2, r3
80020a8: 68fb ldr r3, [r7, #12]
80020aa: 86da strh r2, [r3, #54] @ 0x36
}
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0U)
80020ac: e032 b.n 8002114 <HAL_SPI_Transmit+0x17a>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
80020ae: 68fb ldr r3, [r7, #12]
80020b0: 681b ldr r3, [r3, #0]
80020b2: 689b ldr r3, [r3, #8]
80020b4: f003 0302 and.w r3, r3, #2
80020b8: 2b02 cmp r3, #2
80020ba: d112 bne.n 80020e2 <HAL_SPI_Transmit+0x148>
{
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
80020bc: 68fb ldr r3, [r7, #12]
80020be: 6b1b ldr r3, [r3, #48] @ 0x30
80020c0: 881a ldrh r2, [r3, #0]
80020c2: 68fb ldr r3, [r7, #12]
80020c4: 681b ldr r3, [r3, #0]
80020c6: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
80020c8: 68fb ldr r3, [r7, #12]
80020ca: 6b1b ldr r3, [r3, #48] @ 0x30
80020cc: 1c9a adds r2, r3, #2
80020ce: 68fb ldr r3, [r7, #12]
80020d0: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
80020d2: 68fb ldr r3, [r7, #12]
80020d4: 8edb ldrh r3, [r3, #54] @ 0x36
80020d6: b29b uxth r3, r3
80020d8: 3b01 subs r3, #1
80020da: b29a uxth r2, r3
80020dc: 68fb ldr r3, [r7, #12]
80020de: 86da strh r2, [r3, #54] @ 0x36
80020e0: e018 b.n 8002114 <HAL_SPI_Transmit+0x17a>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
80020e2: f7fe fe4b bl 8000d7c <HAL_GetTick>
80020e6: 4602 mov r2, r0
80020e8: 69fb ldr r3, [r7, #28]
80020ea: 1ad3 subs r3, r2, r3
80020ec: 683a ldr r2, [r7, #0]
80020ee: 429a cmp r2, r3
80020f0: d803 bhi.n 80020fa <HAL_SPI_Transmit+0x160>
80020f2: 683b ldr r3, [r7, #0]
80020f4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80020f8: d102 bne.n 8002100 <HAL_SPI_Transmit+0x166>
80020fa: 683b ldr r3, [r7, #0]
80020fc: 2b00 cmp r3, #0
80020fe: d109 bne.n 8002114 <HAL_SPI_Transmit+0x17a>
{
hspi->State = HAL_SPI_STATE_READY;
8002100: 68fb ldr r3, [r7, #12]
8002102: 2201 movs r2, #1
8002104: f883 2051 strb.w r2, [r3, #81] @ 0x51
__HAL_UNLOCK(hspi);
8002108: 68fb ldr r3, [r7, #12]
800210a: 2200 movs r2, #0
800210c: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
8002110: 2303 movs r3, #3
8002112: e082 b.n 800221a <HAL_SPI_Transmit+0x280>
while (hspi->TxXferCount > 0U)
8002114: 68fb ldr r3, [r7, #12]
8002116: 8edb ldrh r3, [r3, #54] @ 0x36
8002118: b29b uxth r3, r3
800211a: 2b00 cmp r3, #0
800211c: d1c7 bne.n 80020ae <HAL_SPI_Transmit+0x114>
800211e: e053 b.n 80021c8 <HAL_SPI_Transmit+0x22e>
}
}
/* Transmit data in 8 Bit mode */
else
{
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
8002120: 68fb ldr r3, [r7, #12]
8002122: 685b ldr r3, [r3, #4]
8002124: 2b00 cmp r3, #0
8002126: d002 beq.n 800212e <HAL_SPI_Transmit+0x194>
8002128: 8b7b ldrh r3, [r7, #26]
800212a: 2b01 cmp r3, #1
800212c: d147 bne.n 80021be <HAL_SPI_Transmit+0x224>
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
800212e: 68fb ldr r3, [r7, #12]
8002130: 6b1a ldr r2, [r3, #48] @ 0x30
8002132: 68fb ldr r3, [r7, #12]
8002134: 681b ldr r3, [r3, #0]
8002136: 330c adds r3, #12
8002138: 7812 ldrb r2, [r2, #0]
800213a: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
800213c: 68fb ldr r3, [r7, #12]
800213e: 6b1b ldr r3, [r3, #48] @ 0x30
8002140: 1c5a adds r2, r3, #1
8002142: 68fb ldr r3, [r7, #12]
8002144: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
8002146: 68fb ldr r3, [r7, #12]
8002148: 8edb ldrh r3, [r3, #54] @ 0x36
800214a: b29b uxth r3, r3
800214c: 3b01 subs r3, #1
800214e: b29a uxth r2, r3
8002150: 68fb ldr r3, [r7, #12]
8002152: 86da strh r2, [r3, #54] @ 0x36
}
while (hspi->TxXferCount > 0U)
8002154: e033 b.n 80021be <HAL_SPI_Transmit+0x224>
{
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
8002156: 68fb ldr r3, [r7, #12]
8002158: 681b ldr r3, [r3, #0]
800215a: 689b ldr r3, [r3, #8]
800215c: f003 0302 and.w r3, r3, #2
8002160: 2b02 cmp r3, #2
8002162: d113 bne.n 800218c <HAL_SPI_Transmit+0x1f2>
{
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
8002164: 68fb ldr r3, [r7, #12]
8002166: 6b1a ldr r2, [r3, #48] @ 0x30
8002168: 68fb ldr r3, [r7, #12]
800216a: 681b ldr r3, [r3, #0]
800216c: 330c adds r3, #12
800216e: 7812 ldrb r2, [r2, #0]
8002170: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr += sizeof(uint8_t);
8002172: 68fb ldr r3, [r7, #12]
8002174: 6b1b ldr r3, [r3, #48] @ 0x30
8002176: 1c5a adds r2, r3, #1
8002178: 68fb ldr r3, [r7, #12]
800217a: 631a str r2, [r3, #48] @ 0x30
hspi->TxXferCount--;
800217c: 68fb ldr r3, [r7, #12]
800217e: 8edb ldrh r3, [r3, #54] @ 0x36
8002180: b29b uxth r3, r3
8002182: 3b01 subs r3, #1
8002184: b29a uxth r2, r3
8002186: 68fb ldr r3, [r7, #12]
8002188: 86da strh r2, [r3, #54] @ 0x36
800218a: e018 b.n 80021be <HAL_SPI_Transmit+0x224>
}
else
{
/* Timeout management */
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
800218c: f7fe fdf6 bl 8000d7c <HAL_GetTick>
8002190: 4602 mov r2, r0
8002192: 69fb ldr r3, [r7, #28]
8002194: 1ad3 subs r3, r2, r3
8002196: 683a ldr r2, [r7, #0]
8002198: 429a cmp r2, r3
800219a: d803 bhi.n 80021a4 <HAL_SPI_Transmit+0x20a>
800219c: 683b ldr r3, [r7, #0]
800219e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
80021a2: d102 bne.n 80021aa <HAL_SPI_Transmit+0x210>
80021a4: 683b ldr r3, [r7, #0]
80021a6: 2b00 cmp r3, #0
80021a8: d109 bne.n 80021be <HAL_SPI_Transmit+0x224>
{
hspi->State = HAL_SPI_STATE_READY;
80021aa: 68fb ldr r3, [r7, #12]
80021ac: 2201 movs r2, #1
80021ae: f883 2051 strb.w r2, [r3, #81] @ 0x51
__HAL_UNLOCK(hspi);
80021b2: 68fb ldr r3, [r7, #12]
80021b4: 2200 movs r2, #0
80021b6: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
80021ba: 2303 movs r3, #3
80021bc: e02d b.n 800221a <HAL_SPI_Transmit+0x280>
while (hspi->TxXferCount > 0U)
80021be: 68fb ldr r3, [r7, #12]
80021c0: 8edb ldrh r3, [r3, #54] @ 0x36
80021c2: b29b uxth r3, r3
80021c4: 2b00 cmp r3, #0
80021c6: d1c6 bne.n 8002156 <HAL_SPI_Transmit+0x1bc>
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
80021c8: 69fa ldr r2, [r7, #28]
80021ca: 6839 ldr r1, [r7, #0]
80021cc: 68f8 ldr r0, [r7, #12]
80021ce: f000 f8b1 bl 8002334 <SPI_EndRxTxTransaction>
80021d2: 4603 mov r3, r0
80021d4: 2b00 cmp r3, #0
80021d6: d002 beq.n 80021de <HAL_SPI_Transmit+0x244>
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
80021d8: 68fb ldr r3, [r7, #12]
80021da: 2220 movs r2, #32
80021dc: 655a str r2, [r3, #84] @ 0x54
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
80021de: 68fb ldr r3, [r7, #12]
80021e0: 689b ldr r3, [r3, #8]
80021e2: 2b00 cmp r3, #0
80021e4: d10a bne.n 80021fc <HAL_SPI_Transmit+0x262>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
80021e6: 2300 movs r3, #0
80021e8: 617b str r3, [r7, #20]
80021ea: 68fb ldr r3, [r7, #12]
80021ec: 681b ldr r3, [r3, #0]
80021ee: 68db ldr r3, [r3, #12]
80021f0: 617b str r3, [r7, #20]
80021f2: 68fb ldr r3, [r7, #12]
80021f4: 681b ldr r3, [r3, #0]
80021f6: 689b ldr r3, [r3, #8]
80021f8: 617b str r3, [r7, #20]
80021fa: 697b ldr r3, [r7, #20]
}
hspi->State = HAL_SPI_STATE_READY;
80021fc: 68fb ldr r3, [r7, #12]
80021fe: 2201 movs r2, #1
8002200: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8002204: 68fb ldr r3, [r7, #12]
8002206: 2200 movs r2, #0
8002208: f883 2050 strb.w r2, [r3, #80] @ 0x50
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
800220c: 68fb ldr r3, [r7, #12]
800220e: 6d5b ldr r3, [r3, #84] @ 0x54
8002210: 2b00 cmp r3, #0
8002212: d001 beq.n 8002218 <HAL_SPI_Transmit+0x27e>
{
return HAL_ERROR;
8002214: 2301 movs r3, #1
8002216: e000 b.n 800221a <HAL_SPI_Transmit+0x280>
}
else
{
return HAL_OK;
8002218: 2300 movs r3, #0
}
}
800221a: 4618 mov r0, r3
800221c: 3720 adds r7, #32
800221e: 46bd mov sp, r7
8002220: bd80 pop {r7, pc}
...
08002224 <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8002224: b580 push {r7, lr}
8002226: b088 sub sp, #32
8002228: af00 add r7, sp, #0
800222a: 60f8 str r0, [r7, #12]
800222c: 60b9 str r1, [r7, #8]
800222e: 603b str r3, [r7, #0]
8002230: 4613 mov r3, r2
8002232: 71fb strb r3, [r7, #7]
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
8002234: f7fe fda2 bl 8000d7c <HAL_GetTick>
8002238: 4602 mov r2, r0
800223a: 6abb ldr r3, [r7, #40] @ 0x28
800223c: 1a9b subs r3, r3, r2
800223e: 683a ldr r2, [r7, #0]
8002240: 4413 add r3, r2
8002242: 61fb str r3, [r7, #28]
tmp_tickstart = HAL_GetTick();
8002244: f7fe fd9a bl 8000d7c <HAL_GetTick>
8002248: 61b8 str r0, [r7, #24]
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
800224a: 4b39 ldr r3, [pc, #228] @ (8002330 <SPI_WaitFlagStateUntilTimeout+0x10c>)
800224c: 681b ldr r3, [r3, #0]
800224e: 015b lsls r3, r3, #5
8002250: 0d1b lsrs r3, r3, #20
8002252: 69fa ldr r2, [r7, #28]
8002254: fb02 f303 mul.w r3, r2, r3
8002258: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
800225a: e054 b.n 8002306 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (Timeout != HAL_MAX_DELAY)
800225c: 683b ldr r3, [r7, #0]
800225e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8002262: d050 beq.n 8002306 <SPI_WaitFlagStateUntilTimeout+0xe2>
{
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
8002264: f7fe fd8a bl 8000d7c <HAL_GetTick>
8002268: 4602 mov r2, r0
800226a: 69bb ldr r3, [r7, #24]
800226c: 1ad3 subs r3, r2, r3
800226e: 69fa ldr r2, [r7, #28]
8002270: 429a cmp r2, r3
8002272: d902 bls.n 800227a <SPI_WaitFlagStateUntilTimeout+0x56>
8002274: 69fb ldr r3, [r7, #28]
8002276: 2b00 cmp r3, #0
8002278: d13d bne.n 80022f6 <SPI_WaitFlagStateUntilTimeout+0xd2>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
800227a: 68fb ldr r3, [r7, #12]
800227c: 681b ldr r3, [r3, #0]
800227e: 685a ldr r2, [r3, #4]
8002280: 68fb ldr r3, [r7, #12]
8002282: 681b ldr r3, [r3, #0]
8002284: f022 02e0 bic.w r2, r2, #224 @ 0xe0
8002288: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
800228a: 68fb ldr r3, [r7, #12]
800228c: 685b ldr r3, [r3, #4]
800228e: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002292: d111 bne.n 80022b8 <SPI_WaitFlagStateUntilTimeout+0x94>
8002294: 68fb ldr r3, [r7, #12]
8002296: 689b ldr r3, [r3, #8]
8002298: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800229c: d004 beq.n 80022a8 <SPI_WaitFlagStateUntilTimeout+0x84>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
800229e: 68fb ldr r3, [r7, #12]
80022a0: 689b ldr r3, [r3, #8]
80022a2: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80022a6: d107 bne.n 80022b8 <SPI_WaitFlagStateUntilTimeout+0x94>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80022a8: 68fb ldr r3, [r7, #12]
80022aa: 681b ldr r3, [r3, #0]
80022ac: 681a ldr r2, [r3, #0]
80022ae: 68fb ldr r3, [r7, #12]
80022b0: 681b ldr r3, [r3, #0]
80022b2: f022 0240 bic.w r2, r2, #64 @ 0x40
80022b6: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
80022b8: 68fb ldr r3, [r7, #12]
80022ba: 6a9b ldr r3, [r3, #40] @ 0x28
80022bc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80022c0: d10f bne.n 80022e2 <SPI_WaitFlagStateUntilTimeout+0xbe>
{
SPI_RESET_CRC(hspi);
80022c2: 68fb ldr r3, [r7, #12]
80022c4: 681b ldr r3, [r3, #0]
80022c6: 681a ldr r2, [r3, #0]
80022c8: 68fb ldr r3, [r7, #12]
80022ca: 681b ldr r3, [r3, #0]
80022cc: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80022d0: 601a str r2, [r3, #0]
80022d2: 68fb ldr r3, [r7, #12]
80022d4: 681b ldr r3, [r3, #0]
80022d6: 681a ldr r2, [r3, #0]
80022d8: 68fb ldr r3, [r7, #12]
80022da: 681b ldr r3, [r3, #0]
80022dc: f442 5200 orr.w r2, r2, #8192 @ 0x2000
80022e0: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
80022e2: 68fb ldr r3, [r7, #12]
80022e4: 2201 movs r2, #1
80022e6: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
80022ea: 68fb ldr r3, [r7, #12]
80022ec: 2200 movs r2, #0
80022ee: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_TIMEOUT;
80022f2: 2303 movs r3, #3
80022f4: e017 b.n 8002326 <SPI_WaitFlagStateUntilTimeout+0x102>
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if (count == 0U)
80022f6: 697b ldr r3, [r7, #20]
80022f8: 2b00 cmp r3, #0
80022fa: d101 bne.n 8002300 <SPI_WaitFlagStateUntilTimeout+0xdc>
{
tmp_timeout = 0U;
80022fc: 2300 movs r3, #0
80022fe: 61fb str r3, [r7, #28]
}
count--;
8002300: 697b ldr r3, [r7, #20]
8002302: 3b01 subs r3, #1
8002304: 617b str r3, [r7, #20]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8002306: 68fb ldr r3, [r7, #12]
8002308: 681b ldr r3, [r3, #0]
800230a: 689a ldr r2, [r3, #8]
800230c: 68bb ldr r3, [r7, #8]
800230e: 4013 ands r3, r2
8002310: 68ba ldr r2, [r7, #8]
8002312: 429a cmp r2, r3
8002314: bf0c ite eq
8002316: 2301 moveq r3, #1
8002318: 2300 movne r3, #0
800231a: b2db uxtb r3, r3
800231c: 461a mov r2, r3
800231e: 79fb ldrb r3, [r7, #7]
8002320: 429a cmp r2, r3
8002322: d19b bne.n 800225c <SPI_WaitFlagStateUntilTimeout+0x38>
}
}
return HAL_OK;
8002324: 2300 movs r3, #0
}
8002326: 4618 mov r0, r3
8002328: 3720 adds r7, #32
800232a: 46bd mov sp, r7
800232c: bd80 pop {r7, pc}
800232e: bf00 nop
8002330: 20000000 .word 0x20000000
08002334 <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
8002334: b580 push {r7, lr}
8002336: b088 sub sp, #32
8002338: af02 add r7, sp, #8
800233a: 60f8 str r0, [r7, #12]
800233c: 60b9 str r1, [r7, #8]
800233e: 607a str r2, [r7, #4]
/* Wait until TXE flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK)
8002340: 687b ldr r3, [r7, #4]
8002342: 9300 str r3, [sp, #0]
8002344: 68bb ldr r3, [r7, #8]
8002346: 2201 movs r2, #1
8002348: 2102 movs r1, #2
800234a: 68f8 ldr r0, [r7, #12]
800234c: f7ff ff6a bl 8002224 <SPI_WaitFlagStateUntilTimeout>
8002350: 4603 mov r3, r0
8002352: 2b00 cmp r3, #0
8002354: d007 beq.n 8002366 <SPI_EndRxTxTransaction+0x32>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8002356: 68fb ldr r3, [r7, #12]
8002358: 6d5b ldr r3, [r3, #84] @ 0x54
800235a: f043 0220 orr.w r2, r3, #32
800235e: 68fb ldr r3, [r7, #12]
8002360: 655a str r2, [r3, #84] @ 0x54
return HAL_TIMEOUT;
8002362: 2303 movs r3, #3
8002364: e032 b.n 80023cc <SPI_EndRxTxTransaction+0x98>
}
/* Timeout in us */
__IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
8002366: 4b1b ldr r3, [pc, #108] @ (80023d4 <SPI_EndRxTxTransaction+0xa0>)
8002368: 681b ldr r3, [r3, #0]
800236a: 4a1b ldr r2, [pc, #108] @ (80023d8 <SPI_EndRxTxTransaction+0xa4>)
800236c: fba2 2303 umull r2, r3, r2, r3
8002370: 0d5b lsrs r3, r3, #21
8002372: f44f 727a mov.w r2, #1000 @ 0x3e8
8002376: fb02 f303 mul.w r3, r2, r3
800237a: 617b str r3, [r7, #20]
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
if (hspi->Init.Mode == SPI_MODE_MASTER)
800237c: 68fb ldr r3, [r7, #12]
800237e: 685b ldr r3, [r3, #4]
8002380: f5b3 7f82 cmp.w r3, #260 @ 0x104
8002384: d112 bne.n 80023ac <SPI_EndRxTxTransaction+0x78>
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8002386: 687b ldr r3, [r7, #4]
8002388: 9300 str r3, [sp, #0]
800238a: 68bb ldr r3, [r7, #8]
800238c: 2200 movs r2, #0
800238e: 2180 movs r1, #128 @ 0x80
8002390: 68f8 ldr r0, [r7, #12]
8002392: f7ff ff47 bl 8002224 <SPI_WaitFlagStateUntilTimeout>
8002396: 4603 mov r3, r0
8002398: 2b00 cmp r3, #0
800239a: d016 beq.n 80023ca <SPI_EndRxTxTransaction+0x96>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
800239c: 68fb ldr r3, [r7, #12]
800239e: 6d5b ldr r3, [r3, #84] @ 0x54
80023a0: f043 0220 orr.w r2, r3, #32
80023a4: 68fb ldr r3, [r7, #12]
80023a6: 655a str r2, [r3, #84] @ 0x54
return HAL_TIMEOUT;
80023a8: 2303 movs r3, #3
80023aa: e00f b.n 80023cc <SPI_EndRxTxTransaction+0x98>
* User have to calculate the timeout value to fit with the time of 1 byte transfer.
* This time is directly link with the SPI clock from Master device.
*/
do
{
if (count == 0U)
80023ac: 697b ldr r3, [r7, #20]
80023ae: 2b00 cmp r3, #0
80023b0: d00a beq.n 80023c8 <SPI_EndRxTxTransaction+0x94>
{
break;
}
count--;
80023b2: 697b ldr r3, [r7, #20]
80023b4: 3b01 subs r3, #1
80023b6: 617b str r3, [r7, #20]
} while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
80023b8: 68fb ldr r3, [r7, #12]
80023ba: 681b ldr r3, [r3, #0]
80023bc: 689b ldr r3, [r3, #8]
80023be: f003 0380 and.w r3, r3, #128 @ 0x80
80023c2: 2b80 cmp r3, #128 @ 0x80
80023c4: d0f2 beq.n 80023ac <SPI_EndRxTxTransaction+0x78>
80023c6: e000 b.n 80023ca <SPI_EndRxTxTransaction+0x96>
break;
80023c8: bf00 nop
}
return HAL_OK;
80023ca: 2300 movs r3, #0
}
80023cc: 4618 mov r0, r3
80023ce: 3718 adds r7, #24
80023d0: 46bd mov sp, r7
80023d2: bd80 pop {r7, pc}
80023d4: 20000000 .word 0x20000000
80023d8: 165e9f81 .word 0x165e9f81
080023dc <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80023dc: b580 push {r7, lr}
80023de: b082 sub sp, #8
80023e0: af00 add r7, sp, #0
80023e2: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80023e4: 687b ldr r3, [r7, #4]
80023e6: 2b00 cmp r3, #0
80023e8: d101 bne.n 80023ee <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80023ea: 2301 movs r3, #1
80023ec: e031 b.n 8002452 <HAL_TIM_Base_Init+0x76>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80023ee: 687b ldr r3, [r7, #4]
80023f0: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
80023f4: b2db uxtb r3, r3
80023f6: 2b00 cmp r3, #0
80023f8: d106 bne.n 8002408 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80023fa: 687b ldr r3, [r7, #4]
80023fc: 2200 movs r2, #0
80023fe: f883 2038 strb.w r2, [r3, #56] @ 0x38
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8002402: 6878 ldr r0, [r7, #4]
8002404: f7fe fb0a bl 8000a1c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002408: 687b ldr r3, [r7, #4]
800240a: 2202 movs r2, #2
800240c: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8002410: 687b ldr r3, [r7, #4]
8002412: 681a ldr r2, [r3, #0]
8002414: 687b ldr r3, [r7, #4]
8002416: 3304 adds r3, #4
8002418: 4619 mov r1, r3
800241a: 4610 mov r0, r2
800241c: f000 fa86 bl 800292c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8002420: 687b ldr r3, [r7, #4]
8002422: 2201 movs r2, #1
8002424: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8002428: 687b ldr r3, [r7, #4]
800242a: 2201 movs r2, #1
800242c: f883 203a strb.w r2, [r3, #58] @ 0x3a
8002430: 687b ldr r3, [r7, #4]
8002432: 2201 movs r2, #1
8002434: f883 203b strb.w r2, [r3, #59] @ 0x3b
8002438: 687b ldr r3, [r7, #4]
800243a: 2201 movs r2, #1
800243c: f883 203c strb.w r2, [r3, #60] @ 0x3c
8002440: 687b ldr r3, [r7, #4]
8002442: 2201 movs r2, #1
8002444: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8002448: 687b ldr r3, [r7, #4]
800244a: 2201 movs r2, #1
800244c: f883 2039 strb.w r2, [r3, #57] @ 0x39
return HAL_OK;
8002450: 2300 movs r3, #0
}
8002452: 4618 mov r0, r3
8002454: 3708 adds r7, #8
8002456: 46bd mov sp, r7
8002458: bd80 pop {r7, pc}
0800245a <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
800245a: b580 push {r7, lr}
800245c: b082 sub sp, #8
800245e: af00 add r7, sp, #0
8002460: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8002462: 687b ldr r3, [r7, #4]
8002464: 2b00 cmp r3, #0
8002466: d101 bne.n 800246c <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8002468: 2301 movs r3, #1
800246a: e031 b.n 80024d0 <HAL_TIM_PWM_Init+0x76>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800246c: 687b ldr r3, [r7, #4]
800246e: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
8002472: b2db uxtb r3, r3
8002474: 2b00 cmp r3, #0
8002476: d106 bne.n 8002486 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8002478: 687b ldr r3, [r7, #4]
800247a: 2200 movs r2, #0
800247c: f883 2038 strb.w r2, [r3, #56] @ 0x38
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8002480: 6878 ldr r0, [r7, #4]
8002482: f000 f829 bl 80024d8 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8002486: 687b ldr r3, [r7, #4]
8002488: 2202 movs r2, #2
800248a: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800248e: 687b ldr r3, [r7, #4]
8002490: 681a ldr r2, [r3, #0]
8002492: 687b ldr r3, [r7, #4]
8002494: 3304 adds r3, #4
8002496: 4619 mov r1, r3
8002498: 4610 mov r0, r2
800249a: f000 fa47 bl 800292c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800249e: 687b ldr r3, [r7, #4]
80024a0: 2201 movs r2, #1
80024a2: f883 203e strb.w r2, [r3, #62] @ 0x3e
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80024a6: 687b ldr r3, [r7, #4]
80024a8: 2201 movs r2, #1
80024aa: f883 203a strb.w r2, [r3, #58] @ 0x3a
80024ae: 687b ldr r3, [r7, #4]
80024b0: 2201 movs r2, #1
80024b2: f883 203b strb.w r2, [r3, #59] @ 0x3b
80024b6: 687b ldr r3, [r7, #4]
80024b8: 2201 movs r2, #1
80024ba: f883 203c strb.w r2, [r3, #60] @ 0x3c
80024be: 687b ldr r3, [r7, #4]
80024c0: 2201 movs r2, #1
80024c2: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80024c6: 687b ldr r3, [r7, #4]
80024c8: 2201 movs r2, #1
80024ca: f883 2039 strb.w r2, [r3, #57] @ 0x39
return HAL_OK;
80024ce: 2300 movs r3, #0
}
80024d0: 4618 mov r0, r3
80024d2: 3708 adds r7, #8
80024d4: 46bd mov sp, r7
80024d6: bd80 pop {r7, pc}
080024d8 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
80024d8: b480 push {r7}
80024da: b083 sub sp, #12
80024dc: af00 add r7, sp, #0
80024de: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
80024e0: bf00 nop
80024e2: 370c adds r7, #12
80024e4: 46bd mov sp, r7
80024e6: bc80 pop {r7}
80024e8: 4770 bx lr
...
080024ec <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
80024ec: b580 push {r7, lr}
80024ee: b084 sub sp, #16
80024f0: af00 add r7, sp, #0
80024f2: 6078 str r0, [r7, #4]
80024f4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
80024f6: 683b ldr r3, [r7, #0]
80024f8: 2b00 cmp r3, #0
80024fa: d109 bne.n 8002510 <HAL_TIM_PWM_Start+0x24>
80024fc: 687b ldr r3, [r7, #4]
80024fe: f893 303a ldrb.w r3, [r3, #58] @ 0x3a
8002502: b2db uxtb r3, r3
8002504: 2b01 cmp r3, #1
8002506: bf14 ite ne
8002508: 2301 movne r3, #1
800250a: 2300 moveq r3, #0
800250c: b2db uxtb r3, r3
800250e: e022 b.n 8002556 <HAL_TIM_PWM_Start+0x6a>
8002510: 683b ldr r3, [r7, #0]
8002512: 2b04 cmp r3, #4
8002514: d109 bne.n 800252a <HAL_TIM_PWM_Start+0x3e>
8002516: 687b ldr r3, [r7, #4]
8002518: f893 303b ldrb.w r3, [r3, #59] @ 0x3b
800251c: b2db uxtb r3, r3
800251e: 2b01 cmp r3, #1
8002520: bf14 ite ne
8002522: 2301 movne r3, #1
8002524: 2300 moveq r3, #0
8002526: b2db uxtb r3, r3
8002528: e015 b.n 8002556 <HAL_TIM_PWM_Start+0x6a>
800252a: 683b ldr r3, [r7, #0]
800252c: 2b08 cmp r3, #8
800252e: d109 bne.n 8002544 <HAL_TIM_PWM_Start+0x58>
8002530: 687b ldr r3, [r7, #4]
8002532: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8002536: b2db uxtb r3, r3
8002538: 2b01 cmp r3, #1
800253a: bf14 ite ne
800253c: 2301 movne r3, #1
800253e: 2300 moveq r3, #0
8002540: b2db uxtb r3, r3
8002542: e008 b.n 8002556 <HAL_TIM_PWM_Start+0x6a>
8002544: 687b ldr r3, [r7, #4]
8002546: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800254a: b2db uxtb r3, r3
800254c: 2b01 cmp r3, #1
800254e: bf14 ite ne
8002550: 2301 movne r3, #1
8002552: 2300 moveq r3, #0
8002554: b2db uxtb r3, r3
8002556: 2b00 cmp r3, #0
8002558: d001 beq.n 800255e <HAL_TIM_PWM_Start+0x72>
{
return HAL_ERROR;
800255a: 2301 movs r3, #1
800255c: e051 b.n 8002602 <HAL_TIM_PWM_Start+0x116>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
800255e: 683b ldr r3, [r7, #0]
8002560: 2b00 cmp r3, #0
8002562: d104 bne.n 800256e <HAL_TIM_PWM_Start+0x82>
8002564: 687b ldr r3, [r7, #4]
8002566: 2202 movs r2, #2
8002568: f883 203a strb.w r2, [r3, #58] @ 0x3a
800256c: e013 b.n 8002596 <HAL_TIM_PWM_Start+0xaa>
800256e: 683b ldr r3, [r7, #0]
8002570: 2b04 cmp r3, #4
8002572: d104 bne.n 800257e <HAL_TIM_PWM_Start+0x92>
8002574: 687b ldr r3, [r7, #4]
8002576: 2202 movs r2, #2
8002578: f883 203b strb.w r2, [r3, #59] @ 0x3b
800257c: e00b b.n 8002596 <HAL_TIM_PWM_Start+0xaa>
800257e: 683b ldr r3, [r7, #0]
8002580: 2b08 cmp r3, #8
8002582: d104 bne.n 800258e <HAL_TIM_PWM_Start+0xa2>
8002584: 687b ldr r3, [r7, #4]
8002586: 2202 movs r2, #2
8002588: f883 203c strb.w r2, [r3, #60] @ 0x3c
800258c: e003 b.n 8002596 <HAL_TIM_PWM_Start+0xaa>
800258e: 687b ldr r3, [r7, #4]
8002590: 2202 movs r2, #2
8002592: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8002596: 687b ldr r3, [r7, #4]
8002598: 681b ldr r3, [r3, #0]
800259a: 2201 movs r2, #1
800259c: 6839 ldr r1, [r7, #0]
800259e: 4618 mov r0, r3
80025a0: f000 fbc5 bl 8002d2e <TIM_CCxChannelCmd>
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80025a4: 687b ldr r3, [r7, #4]
80025a6: 681b ldr r3, [r3, #0]
80025a8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80025ac: d00e beq.n 80025cc <HAL_TIM_PWM_Start+0xe0>
80025ae: 687b ldr r3, [r7, #4]
80025b0: 681b ldr r3, [r3, #0]
80025b2: 4a16 ldr r2, [pc, #88] @ (800260c <HAL_TIM_PWM_Start+0x120>)
80025b4: 4293 cmp r3, r2
80025b6: d009 beq.n 80025cc <HAL_TIM_PWM_Start+0xe0>
80025b8: 687b ldr r3, [r7, #4]
80025ba: 681b ldr r3, [r3, #0]
80025bc: 4a14 ldr r2, [pc, #80] @ (8002610 <HAL_TIM_PWM_Start+0x124>)
80025be: 4293 cmp r3, r2
80025c0: d004 beq.n 80025cc <HAL_TIM_PWM_Start+0xe0>
80025c2: 687b ldr r3, [r7, #4]
80025c4: 681b ldr r3, [r3, #0]
80025c6: 4a13 ldr r2, [pc, #76] @ (8002614 <HAL_TIM_PWM_Start+0x128>)
80025c8: 4293 cmp r3, r2
80025ca: d111 bne.n 80025f0 <HAL_TIM_PWM_Start+0x104>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80025cc: 687b ldr r3, [r7, #4]
80025ce: 681b ldr r3, [r3, #0]
80025d0: 689b ldr r3, [r3, #8]
80025d2: f003 0307 and.w r3, r3, #7
80025d6: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80025d8: 68fb ldr r3, [r7, #12]
80025da: 2b06 cmp r3, #6
80025dc: d010 beq.n 8002600 <HAL_TIM_PWM_Start+0x114>
{
__HAL_TIM_ENABLE(htim);
80025de: 687b ldr r3, [r7, #4]
80025e0: 681b ldr r3, [r3, #0]
80025e2: 681a ldr r2, [r3, #0]
80025e4: 687b ldr r3, [r7, #4]
80025e6: 681b ldr r3, [r3, #0]
80025e8: f042 0201 orr.w r2, r2, #1
80025ec: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80025ee: e007 b.n 8002600 <HAL_TIM_PWM_Start+0x114>
}
}
else
{
__HAL_TIM_ENABLE(htim);
80025f0: 687b ldr r3, [r7, #4]
80025f2: 681b ldr r3, [r3, #0]
80025f4: 681a ldr r2, [r3, #0]
80025f6: 687b ldr r3, [r7, #4]
80025f8: 681b ldr r3, [r3, #0]
80025fa: f042 0201 orr.w r2, r2, #1
80025fe: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8002600: 2300 movs r3, #0
}
8002602: 4618 mov r0, r3
8002604: 3710 adds r7, #16
8002606: 46bd mov sp, r7
8002608: bd80 pop {r7, pc}
800260a: bf00 nop
800260c: 40000400 .word 0x40000400
8002610: 40000800 .word 0x40000800
8002614: 40010800 .word 0x40010800
08002618 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8002618: b580 push {r7, lr}
800261a: b086 sub sp, #24
800261c: af00 add r7, sp, #0
800261e: 60f8 str r0, [r7, #12]
8002620: 60b9 str r1, [r7, #8]
8002622: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8002624: 2300 movs r3, #0
8002626: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8002628: 68fb ldr r3, [r7, #12]
800262a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
800262e: 2b01 cmp r3, #1
8002630: d101 bne.n 8002636 <HAL_TIM_PWM_ConfigChannel+0x1e>
8002632: 2302 movs r3, #2
8002634: e0ae b.n 8002794 <HAL_TIM_PWM_ConfigChannel+0x17c>
8002636: 68fb ldr r3, [r7, #12]
8002638: 2201 movs r2, #1
800263a: f883 2038 strb.w r2, [r3, #56] @ 0x38
switch (Channel)
800263e: 687b ldr r3, [r7, #4]
8002640: 2b0c cmp r3, #12
8002642: f200 809f bhi.w 8002784 <HAL_TIM_PWM_ConfigChannel+0x16c>
8002646: a201 add r2, pc, #4 @ (adr r2, 800264c <HAL_TIM_PWM_ConfigChannel+0x34>)
8002648: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800264c: 08002681 .word 0x08002681
8002650: 08002785 .word 0x08002785
8002654: 08002785 .word 0x08002785
8002658: 08002785 .word 0x08002785
800265c: 080026c1 .word 0x080026c1
8002660: 08002785 .word 0x08002785
8002664: 08002785 .word 0x08002785
8002668: 08002785 .word 0x08002785
800266c: 08002703 .word 0x08002703
8002670: 08002785 .word 0x08002785
8002674: 08002785 .word 0x08002785
8002678: 08002785 .word 0x08002785
800267c: 08002743 .word 0x08002743
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8002680: 68fb ldr r3, [r7, #12]
8002682: 681b ldr r3, [r3, #0]
8002684: 68b9 ldr r1, [r7, #8]
8002686: 4618 mov r0, r3
8002688: f000 f9c6 bl 8002a18 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
800268c: 68fb ldr r3, [r7, #12]
800268e: 681b ldr r3, [r3, #0]
8002690: 699a ldr r2, [r3, #24]
8002692: 68fb ldr r3, [r7, #12]
8002694: 681b ldr r3, [r3, #0]
8002696: f042 0208 orr.w r2, r2, #8
800269a: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
800269c: 68fb ldr r3, [r7, #12]
800269e: 681b ldr r3, [r3, #0]
80026a0: 699a ldr r2, [r3, #24]
80026a2: 68fb ldr r3, [r7, #12]
80026a4: 681b ldr r3, [r3, #0]
80026a6: f022 0204 bic.w r2, r2, #4
80026aa: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
80026ac: 68fb ldr r3, [r7, #12]
80026ae: 681b ldr r3, [r3, #0]
80026b0: 6999 ldr r1, [r3, #24]
80026b2: 68bb ldr r3, [r7, #8]
80026b4: 68da ldr r2, [r3, #12]
80026b6: 68fb ldr r3, [r7, #12]
80026b8: 681b ldr r3, [r3, #0]
80026ba: 430a orrs r2, r1
80026bc: 619a str r2, [r3, #24]
break;
80026be: e064 b.n 800278a <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
80026c0: 68fb ldr r3, [r7, #12]
80026c2: 681b ldr r3, [r3, #0]
80026c4: 68b9 ldr r1, [r7, #8]
80026c6: 4618 mov r0, r3
80026c8: f000 f9e2 bl 8002a90 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
80026cc: 68fb ldr r3, [r7, #12]
80026ce: 681b ldr r3, [r3, #0]
80026d0: 699a ldr r2, [r3, #24]
80026d2: 68fb ldr r3, [r7, #12]
80026d4: 681b ldr r3, [r3, #0]
80026d6: f442 6200 orr.w r2, r2, #2048 @ 0x800
80026da: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
80026dc: 68fb ldr r3, [r7, #12]
80026de: 681b ldr r3, [r3, #0]
80026e0: 699a ldr r2, [r3, #24]
80026e2: 68fb ldr r3, [r7, #12]
80026e4: 681b ldr r3, [r3, #0]
80026e6: f422 6280 bic.w r2, r2, #1024 @ 0x400
80026ea: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80026ec: 68fb ldr r3, [r7, #12]
80026ee: 681b ldr r3, [r3, #0]
80026f0: 6999 ldr r1, [r3, #24]
80026f2: 68bb ldr r3, [r7, #8]
80026f4: 68db ldr r3, [r3, #12]
80026f6: 021a lsls r2, r3, #8
80026f8: 68fb ldr r3, [r7, #12]
80026fa: 681b ldr r3, [r3, #0]
80026fc: 430a orrs r2, r1
80026fe: 619a str r2, [r3, #24]
break;
8002700: e043 b.n 800278a <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8002702: 68fb ldr r3, [r7, #12]
8002704: 681b ldr r3, [r3, #0]
8002706: 68b9 ldr r1, [r7, #8]
8002708: 4618 mov r0, r3
800270a: f000 f9ff bl 8002b0c <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800270e: 68fb ldr r3, [r7, #12]
8002710: 681b ldr r3, [r3, #0]
8002712: 69da ldr r2, [r3, #28]
8002714: 68fb ldr r3, [r7, #12]
8002716: 681b ldr r3, [r3, #0]
8002718: f042 0208 orr.w r2, r2, #8
800271c: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800271e: 68fb ldr r3, [r7, #12]
8002720: 681b ldr r3, [r3, #0]
8002722: 69da ldr r2, [r3, #28]
8002724: 68fb ldr r3, [r7, #12]
8002726: 681b ldr r3, [r3, #0]
8002728: f022 0204 bic.w r2, r2, #4
800272c: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800272e: 68fb ldr r3, [r7, #12]
8002730: 681b ldr r3, [r3, #0]
8002732: 69d9 ldr r1, [r3, #28]
8002734: 68bb ldr r3, [r7, #8]
8002736: 68da ldr r2, [r3, #12]
8002738: 68fb ldr r3, [r7, #12]
800273a: 681b ldr r3, [r3, #0]
800273c: 430a orrs r2, r1
800273e: 61da str r2, [r3, #28]
break;
8002740: e023 b.n 800278a <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8002742: 68fb ldr r3, [r7, #12]
8002744: 681b ldr r3, [r3, #0]
8002746: 68b9 ldr r1, [r7, #8]
8002748: 4618 mov r0, r3
800274a: f000 fa1c bl 8002b86 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800274e: 68fb ldr r3, [r7, #12]
8002750: 681b ldr r3, [r3, #0]
8002752: 69da ldr r2, [r3, #28]
8002754: 68fb ldr r3, [r7, #12]
8002756: 681b ldr r3, [r3, #0]
8002758: f442 6200 orr.w r2, r2, #2048 @ 0x800
800275c: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800275e: 68fb ldr r3, [r7, #12]
8002760: 681b ldr r3, [r3, #0]
8002762: 69da ldr r2, [r3, #28]
8002764: 68fb ldr r3, [r7, #12]
8002766: 681b ldr r3, [r3, #0]
8002768: f422 6280 bic.w r2, r2, #1024 @ 0x400
800276c: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800276e: 68fb ldr r3, [r7, #12]
8002770: 681b ldr r3, [r3, #0]
8002772: 69d9 ldr r1, [r3, #28]
8002774: 68bb ldr r3, [r7, #8]
8002776: 68db ldr r3, [r3, #12]
8002778: 021a lsls r2, r3, #8
800277a: 68fb ldr r3, [r7, #12]
800277c: 681b ldr r3, [r3, #0]
800277e: 430a orrs r2, r1
8002780: 61da str r2, [r3, #28]
break;
8002782: e002 b.n 800278a <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8002784: 2301 movs r3, #1
8002786: 75fb strb r3, [r7, #23]
break;
8002788: bf00 nop
}
__HAL_UNLOCK(htim);
800278a: 68fb ldr r3, [r7, #12]
800278c: 2200 movs r2, #0
800278e: f883 2038 strb.w r2, [r3, #56] @ 0x38
return status;
8002792: 7dfb ldrb r3, [r7, #23]
}
8002794: 4618 mov r0, r3
8002796: 3718 adds r7, #24
8002798: 46bd mov sp, r7
800279a: bd80 pop {r7, pc}
0800279c <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
800279c: b580 push {r7, lr}
800279e: b084 sub sp, #16
80027a0: af00 add r7, sp, #0
80027a2: 6078 str r0, [r7, #4]
80027a4: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
80027a6: 2300 movs r3, #0
80027a8: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
80027aa: 687b ldr r3, [r7, #4]
80027ac: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
80027b0: 2b01 cmp r3, #1
80027b2: d101 bne.n 80027b8 <HAL_TIM_ConfigClockSource+0x1c>
80027b4: 2302 movs r3, #2
80027b6: e0b4 b.n 8002922 <HAL_TIM_ConfigClockSource+0x186>
80027b8: 687b ldr r3, [r7, #4]
80027ba: 2201 movs r2, #1
80027bc: f883 2038 strb.w r2, [r3, #56] @ 0x38
htim->State = HAL_TIM_STATE_BUSY;
80027c0: 687b ldr r3, [r7, #4]
80027c2: 2202 movs r2, #2
80027c4: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
80027c8: 687b ldr r3, [r7, #4]
80027ca: 681b ldr r3, [r3, #0]
80027cc: 689b ldr r3, [r3, #8]
80027ce: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
80027d0: 68bb ldr r3, [r7, #8]
80027d2: f023 0377 bic.w r3, r3, #119 @ 0x77
80027d6: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
80027d8: 68bb ldr r3, [r7, #8]
80027da: f423 437f bic.w r3, r3, #65280 @ 0xff00
80027de: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
80027e0: 687b ldr r3, [r7, #4]
80027e2: 681b ldr r3, [r3, #0]
80027e4: 68ba ldr r2, [r7, #8]
80027e6: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
80027e8: 683b ldr r3, [r7, #0]
80027ea: 681b ldr r3, [r3, #0]
80027ec: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80027f0: d03e beq.n 8002870 <HAL_TIM_ConfigClockSource+0xd4>
80027f2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80027f6: f200 8087 bhi.w 8002908 <HAL_TIM_ConfigClockSource+0x16c>
80027fa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80027fe: f000 8086 beq.w 800290e <HAL_TIM_ConfigClockSource+0x172>
8002802: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8002806: d87f bhi.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
8002808: 2b70 cmp r3, #112 @ 0x70
800280a: d01a beq.n 8002842 <HAL_TIM_ConfigClockSource+0xa6>
800280c: 2b70 cmp r3, #112 @ 0x70
800280e: d87b bhi.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
8002810: 2b60 cmp r3, #96 @ 0x60
8002812: d050 beq.n 80028b6 <HAL_TIM_ConfigClockSource+0x11a>
8002814: 2b60 cmp r3, #96 @ 0x60
8002816: d877 bhi.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
8002818: 2b50 cmp r3, #80 @ 0x50
800281a: d03c beq.n 8002896 <HAL_TIM_ConfigClockSource+0xfa>
800281c: 2b50 cmp r3, #80 @ 0x50
800281e: d873 bhi.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
8002820: 2b40 cmp r3, #64 @ 0x40
8002822: d058 beq.n 80028d6 <HAL_TIM_ConfigClockSource+0x13a>
8002824: 2b40 cmp r3, #64 @ 0x40
8002826: d86f bhi.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
8002828: 2b30 cmp r3, #48 @ 0x30
800282a: d064 beq.n 80028f6 <HAL_TIM_ConfigClockSource+0x15a>
800282c: 2b30 cmp r3, #48 @ 0x30
800282e: d86b bhi.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
8002830: 2b20 cmp r3, #32
8002832: d060 beq.n 80028f6 <HAL_TIM_ConfigClockSource+0x15a>
8002834: 2b20 cmp r3, #32
8002836: d867 bhi.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
8002838: 2b00 cmp r3, #0
800283a: d05c beq.n 80028f6 <HAL_TIM_ConfigClockSource+0x15a>
800283c: 2b10 cmp r3, #16
800283e: d05a beq.n 80028f6 <HAL_TIM_ConfigClockSource+0x15a>
8002840: e062 b.n 8002908 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8002842: 687b ldr r3, [r7, #4]
8002844: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8002846: 683b ldr r3, [r7, #0]
8002848: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
800284a: 683b ldr r3, [r7, #0]
800284c: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800284e: 683b ldr r3, [r7, #0]
8002850: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8002852: f000 fa4d bl 8002cf0 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8002856: 687b ldr r3, [r7, #4]
8002858: 681b ldr r3, [r3, #0]
800285a: 689b ldr r3, [r3, #8]
800285c: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800285e: 68bb ldr r3, [r7, #8]
8002860: f043 0377 orr.w r3, r3, #119 @ 0x77
8002864: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8002866: 687b ldr r3, [r7, #4]
8002868: 681b ldr r3, [r3, #0]
800286a: 68ba ldr r2, [r7, #8]
800286c: 609a str r2, [r3, #8]
break;
800286e: e04f b.n 8002910 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8002870: 687b ldr r3, [r7, #4]
8002872: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8002874: 683b ldr r3, [r7, #0]
8002876: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8002878: 683b ldr r3, [r7, #0]
800287a: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
800287c: 683b ldr r3, [r7, #0]
800287e: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8002880: f000 fa36 bl 8002cf0 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8002884: 687b ldr r3, [r7, #4]
8002886: 681b ldr r3, [r3, #0]
8002888: 689a ldr r2, [r3, #8]
800288a: 687b ldr r3, [r7, #4]
800288c: 681b ldr r3, [r3, #0]
800288e: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8002892: 609a str r2, [r3, #8]
break;
8002894: e03c b.n 8002910 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8002896: 687b ldr r3, [r7, #4]
8002898: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800289a: 683b ldr r3, [r7, #0]
800289c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800289e: 683b ldr r3, [r7, #0]
80028a0: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80028a2: 461a mov r2, r3
80028a4: f000 f9ad bl 8002c02 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80028a8: 687b ldr r3, [r7, #4]
80028aa: 681b ldr r3, [r3, #0]
80028ac: 2150 movs r1, #80 @ 0x50
80028ae: 4618 mov r0, r3
80028b0: f000 fa04 bl 8002cbc <TIM_ITRx_SetConfig>
break;
80028b4: e02c b.n 8002910 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
80028b6: 687b ldr r3, [r7, #4]
80028b8: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80028ba: 683b ldr r3, [r7, #0]
80028bc: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80028be: 683b ldr r3, [r7, #0]
80028c0: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
80028c2: 461a mov r2, r3
80028c4: f000 f9cb bl 8002c5e <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80028c8: 687b ldr r3, [r7, #4]
80028ca: 681b ldr r3, [r3, #0]
80028cc: 2160 movs r1, #96 @ 0x60
80028ce: 4618 mov r0, r3
80028d0: f000 f9f4 bl 8002cbc <TIM_ITRx_SetConfig>
break;
80028d4: e01c b.n 8002910 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80028d6: 687b ldr r3, [r7, #4]
80028d8: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80028da: 683b ldr r3, [r7, #0]
80028dc: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80028de: 683b ldr r3, [r7, #0]
80028e0: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80028e2: 461a mov r2, r3
80028e4: f000 f98d bl 8002c02 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80028e8: 687b ldr r3, [r7, #4]
80028ea: 681b ldr r3, [r3, #0]
80028ec: 2140 movs r1, #64 @ 0x40
80028ee: 4618 mov r0, r3
80028f0: f000 f9e4 bl 8002cbc <TIM_ITRx_SetConfig>
break;
80028f4: e00c b.n 8002910 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80028f6: 687b ldr r3, [r7, #4]
80028f8: 681a ldr r2, [r3, #0]
80028fa: 683b ldr r3, [r7, #0]
80028fc: 681b ldr r3, [r3, #0]
80028fe: 4619 mov r1, r3
8002900: 4610 mov r0, r2
8002902: f000 f9db bl 8002cbc <TIM_ITRx_SetConfig>
break;
8002906: e003 b.n 8002910 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
8002908: 2301 movs r3, #1
800290a: 73fb strb r3, [r7, #15]
break;
800290c: e000 b.n 8002910 <HAL_TIM_ConfigClockSource+0x174>
break;
800290e: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8002910: 687b ldr r3, [r7, #4]
8002912: 2201 movs r2, #1
8002914: f883 2039 strb.w r2, [r3, #57] @ 0x39
__HAL_UNLOCK(htim);
8002918: 687b ldr r3, [r7, #4]
800291a: 2200 movs r2, #0
800291c: f883 2038 strb.w r2, [r3, #56] @ 0x38
return status;
8002920: 7bfb ldrb r3, [r7, #15]
}
8002922: 4618 mov r0, r3
8002924: 3710 adds r7, #16
8002926: 46bd mov sp, r7
8002928: bd80 pop {r7, pc}
...
0800292c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
800292c: b480 push {r7}
800292e: b085 sub sp, #20
8002930: af00 add r7, sp, #0
8002932: 6078 str r0, [r7, #4]
8002934: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8002936: 687b ldr r3, [r7, #4]
8002938: 681b ldr r3, [r3, #0]
800293a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800293c: 687b ldr r3, [r7, #4]
800293e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002942: d00f beq.n 8002964 <TIM_Base_SetConfig+0x38>
8002944: 687b ldr r3, [r7, #4]
8002946: 4a2e ldr r2, [pc, #184] @ (8002a00 <TIM_Base_SetConfig+0xd4>)
8002948: 4293 cmp r3, r2
800294a: d00b beq.n 8002964 <TIM_Base_SetConfig+0x38>
800294c: 687b ldr r3, [r7, #4]
800294e: 4a2d ldr r2, [pc, #180] @ (8002a04 <TIM_Base_SetConfig+0xd8>)
8002950: 4293 cmp r3, r2
8002952: d007 beq.n 8002964 <TIM_Base_SetConfig+0x38>
8002954: 687b ldr r3, [r7, #4]
8002956: 4a2c ldr r2, [pc, #176] @ (8002a08 <TIM_Base_SetConfig+0xdc>)
8002958: 4293 cmp r3, r2
800295a: d003 beq.n 8002964 <TIM_Base_SetConfig+0x38>
800295c: 687b ldr r3, [r7, #4]
800295e: 4a2b ldr r2, [pc, #172] @ (8002a0c <TIM_Base_SetConfig+0xe0>)
8002960: 4293 cmp r3, r2
8002962: d108 bne.n 8002976 <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8002964: 68fb ldr r3, [r7, #12]
8002966: f023 0370 bic.w r3, r3, #112 @ 0x70
800296a: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800296c: 683b ldr r3, [r7, #0]
800296e: 685b ldr r3, [r3, #4]
8002970: 68fa ldr r2, [r7, #12]
8002972: 4313 orrs r3, r2
8002974: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8002976: 687b ldr r3, [r7, #4]
8002978: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800297c: d017 beq.n 80029ae <TIM_Base_SetConfig+0x82>
800297e: 687b ldr r3, [r7, #4]
8002980: 4a1f ldr r2, [pc, #124] @ (8002a00 <TIM_Base_SetConfig+0xd4>)
8002982: 4293 cmp r3, r2
8002984: d013 beq.n 80029ae <TIM_Base_SetConfig+0x82>
8002986: 687b ldr r3, [r7, #4]
8002988: 4a1e ldr r2, [pc, #120] @ (8002a04 <TIM_Base_SetConfig+0xd8>)
800298a: 4293 cmp r3, r2
800298c: d00f beq.n 80029ae <TIM_Base_SetConfig+0x82>
800298e: 687b ldr r3, [r7, #4]
8002990: 4a1d ldr r2, [pc, #116] @ (8002a08 <TIM_Base_SetConfig+0xdc>)
8002992: 4293 cmp r3, r2
8002994: d00b beq.n 80029ae <TIM_Base_SetConfig+0x82>
8002996: 687b ldr r3, [r7, #4]
8002998: 4a1c ldr r2, [pc, #112] @ (8002a0c <TIM_Base_SetConfig+0xe0>)
800299a: 4293 cmp r3, r2
800299c: d007 beq.n 80029ae <TIM_Base_SetConfig+0x82>
800299e: 687b ldr r3, [r7, #4]
80029a0: 4a1b ldr r2, [pc, #108] @ (8002a10 <TIM_Base_SetConfig+0xe4>)
80029a2: 4293 cmp r3, r2
80029a4: d003 beq.n 80029ae <TIM_Base_SetConfig+0x82>
80029a6: 687b ldr r3, [r7, #4]
80029a8: 4a1a ldr r2, [pc, #104] @ (8002a14 <TIM_Base_SetConfig+0xe8>)
80029aa: 4293 cmp r3, r2
80029ac: d108 bne.n 80029c0 <TIM_Base_SetConfig+0x94>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
80029ae: 68fb ldr r3, [r7, #12]
80029b0: f423 7340 bic.w r3, r3, #768 @ 0x300
80029b4: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80029b6: 683b ldr r3, [r7, #0]
80029b8: 68db ldr r3, [r3, #12]
80029ba: 68fa ldr r2, [r7, #12]
80029bc: 4313 orrs r3, r2
80029be: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80029c0: 68fb ldr r3, [r7, #12]
80029c2: f023 0280 bic.w r2, r3, #128 @ 0x80
80029c6: 683b ldr r3, [r7, #0]
80029c8: 691b ldr r3, [r3, #16]
80029ca: 4313 orrs r3, r2
80029cc: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80029ce: 683b ldr r3, [r7, #0]
80029d0: 689a ldr r2, [r3, #8]
80029d2: 687b ldr r3, [r7, #4]
80029d4: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80029d6: 683b ldr r3, [r7, #0]
80029d8: 681a ldr r2, [r3, #0]
80029da: 687b ldr r3, [r7, #4]
80029dc: 629a str r2, [r3, #40] @ 0x28
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
80029de: 687b ldr r3, [r7, #4]
80029e0: 681b ldr r3, [r3, #0]
80029e2: f043 0204 orr.w r2, r3, #4
80029e6: 687b ldr r3, [r7, #4]
80029e8: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80029ea: 687b ldr r3, [r7, #4]
80029ec: 2201 movs r2, #1
80029ee: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
80029f0: 687b ldr r3, [r7, #4]
80029f2: 68fa ldr r2, [r7, #12]
80029f4: 601a str r2, [r3, #0]
}
80029f6: bf00 nop
80029f8: 3714 adds r7, #20
80029fa: 46bd mov sp, r7
80029fc: bc80 pop {r7}
80029fe: 4770 bx lr
8002a00: 40000400 .word 0x40000400
8002a04: 40000800 .word 0x40000800
8002a08: 40000c00 .word 0x40000c00
8002a0c: 40010800 .word 0x40010800
8002a10: 40010c00 .word 0x40010c00
8002a14: 40011000 .word 0x40011000
08002a18 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8002a18: b480 push {r7}
8002a1a: b087 sub sp, #28
8002a1c: af00 add r7, sp, #0
8002a1e: 6078 str r0, [r7, #4]
8002a20: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002a22: 687b ldr r3, [r7, #4]
8002a24: 6a1b ldr r3, [r3, #32]
8002a26: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8002a28: 687b ldr r3, [r7, #4]
8002a2a: 6a1b ldr r3, [r3, #32]
8002a2c: f023 0201 bic.w r2, r3, #1
8002a30: 687b ldr r3, [r7, #4]
8002a32: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002a34: 687b ldr r3, [r7, #4]
8002a36: 685b ldr r3, [r3, #4]
8002a38: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8002a3a: 687b ldr r3, [r7, #4]
8002a3c: 699b ldr r3, [r3, #24]
8002a3e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8002a40: 68fb ldr r3, [r7, #12]
8002a42: f023 0370 bic.w r3, r3, #112 @ 0x70
8002a46: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8002a48: 68fb ldr r3, [r7, #12]
8002a4a: f023 0303 bic.w r3, r3, #3
8002a4e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8002a50: 683b ldr r3, [r7, #0]
8002a52: 681b ldr r3, [r3, #0]
8002a54: 68fa ldr r2, [r7, #12]
8002a56: 4313 orrs r3, r2
8002a58: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8002a5a: 697b ldr r3, [r7, #20]
8002a5c: f023 0302 bic.w r3, r3, #2
8002a60: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8002a62: 683b ldr r3, [r7, #0]
8002a64: 689b ldr r3, [r3, #8]
8002a66: 697a ldr r2, [r7, #20]
8002a68: 4313 orrs r3, r2
8002a6a: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002a6c: 687b ldr r3, [r7, #4]
8002a6e: 693a ldr r2, [r7, #16]
8002a70: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8002a72: 687b ldr r3, [r7, #4]
8002a74: 68fa ldr r2, [r7, #12]
8002a76: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8002a78: 683b ldr r3, [r7, #0]
8002a7a: 685a ldr r2, [r3, #4]
8002a7c: 687b ldr r3, [r7, #4]
8002a7e: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002a80: 687b ldr r3, [r7, #4]
8002a82: 697a ldr r2, [r7, #20]
8002a84: 621a str r2, [r3, #32]
}
8002a86: bf00 nop
8002a88: 371c adds r7, #28
8002a8a: 46bd mov sp, r7
8002a8c: bc80 pop {r7}
8002a8e: 4770 bx lr
08002a90 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8002a90: b480 push {r7}
8002a92: b087 sub sp, #28
8002a94: af00 add r7, sp, #0
8002a96: 6078 str r0, [r7, #4]
8002a98: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002a9a: 687b ldr r3, [r7, #4]
8002a9c: 6a1b ldr r3, [r3, #32]
8002a9e: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8002aa0: 687b ldr r3, [r7, #4]
8002aa2: 6a1b ldr r3, [r3, #32]
8002aa4: f023 0210 bic.w r2, r3, #16
8002aa8: 687b ldr r3, [r7, #4]
8002aaa: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002aac: 687b ldr r3, [r7, #4]
8002aae: 685b ldr r3, [r3, #4]
8002ab0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 699b ldr r3, [r3, #24]
8002ab6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8002ab8: 68fb ldr r3, [r7, #12]
8002aba: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002abe: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8002ac0: 68fb ldr r3, [r7, #12]
8002ac2: f423 7340 bic.w r3, r3, #768 @ 0x300
8002ac6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002ac8: 683b ldr r3, [r7, #0]
8002aca: 681b ldr r3, [r3, #0]
8002acc: 021b lsls r3, r3, #8
8002ace: 68fa ldr r2, [r7, #12]
8002ad0: 4313 orrs r3, r2
8002ad2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8002ad4: 697b ldr r3, [r7, #20]
8002ad6: f023 0320 bic.w r3, r3, #32
8002ada: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8002adc: 683b ldr r3, [r7, #0]
8002ade: 689b ldr r3, [r3, #8]
8002ae0: 011b lsls r3, r3, #4
8002ae2: 697a ldr r2, [r7, #20]
8002ae4: 4313 orrs r3, r2
8002ae6: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002ae8: 687b ldr r3, [r7, #4]
8002aea: 693a ldr r2, [r7, #16]
8002aec: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8002aee: 687b ldr r3, [r7, #4]
8002af0: 68fa ldr r2, [r7, #12]
8002af2: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8002af4: 683b ldr r3, [r7, #0]
8002af6: 685a ldr r2, [r3, #4]
8002af8: 687b ldr r3, [r7, #4]
8002afa: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002afc: 687b ldr r3, [r7, #4]
8002afe: 697a ldr r2, [r7, #20]
8002b00: 621a str r2, [r3, #32]
}
8002b02: bf00 nop
8002b04: 371c adds r7, #28
8002b06: 46bd mov sp, r7
8002b08: bc80 pop {r7}
8002b0a: 4770 bx lr
08002b0c <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8002b0c: b480 push {r7}
8002b0e: b087 sub sp, #28
8002b10: af00 add r7, sp, #0
8002b12: 6078 str r0, [r7, #4]
8002b14: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002b16: 687b ldr r3, [r7, #4]
8002b18: 6a1b ldr r3, [r3, #32]
8002b1a: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8002b1c: 687b ldr r3, [r7, #4]
8002b1e: 6a1b ldr r3, [r3, #32]
8002b20: f423 7280 bic.w r2, r3, #256 @ 0x100
8002b24: 687b ldr r3, [r7, #4]
8002b26: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002b28: 687b ldr r3, [r7, #4]
8002b2a: 685b ldr r3, [r3, #4]
8002b2c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8002b2e: 687b ldr r3, [r7, #4]
8002b30: 69db ldr r3, [r3, #28]
8002b32: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8002b34: 68fb ldr r3, [r7, #12]
8002b36: f023 0370 bic.w r3, r3, #112 @ 0x70
8002b3a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8002b3c: 68fb ldr r3, [r7, #12]
8002b3e: f023 0303 bic.w r3, r3, #3
8002b42: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8002b44: 683b ldr r3, [r7, #0]
8002b46: 681b ldr r3, [r3, #0]
8002b48: 68fa ldr r2, [r7, #12]
8002b4a: 4313 orrs r3, r2
8002b4c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8002b4e: 697b ldr r3, [r7, #20]
8002b50: f423 7300 bic.w r3, r3, #512 @ 0x200
8002b54: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8002b56: 683b ldr r3, [r7, #0]
8002b58: 689b ldr r3, [r3, #8]
8002b5a: 021b lsls r3, r3, #8
8002b5c: 697a ldr r2, [r7, #20]
8002b5e: 4313 orrs r3, r2
8002b60: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002b62: 687b ldr r3, [r7, #4]
8002b64: 693a ldr r2, [r7, #16]
8002b66: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002b68: 687b ldr r3, [r7, #4]
8002b6a: 68fa ldr r2, [r7, #12]
8002b6c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8002b6e: 683b ldr r3, [r7, #0]
8002b70: 685a ldr r2, [r3, #4]
8002b72: 687b ldr r3, [r7, #4]
8002b74: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002b76: 687b ldr r3, [r7, #4]
8002b78: 697a ldr r2, [r7, #20]
8002b7a: 621a str r2, [r3, #32]
}
8002b7c: bf00 nop
8002b7e: 371c adds r7, #28
8002b80: 46bd mov sp, r7
8002b82: bc80 pop {r7}
8002b84: 4770 bx lr
08002b86 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8002b86: b480 push {r7}
8002b88: b087 sub sp, #28
8002b8a: af00 add r7, sp, #0
8002b8c: 6078 str r0, [r7, #4]
8002b8e: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8002b90: 687b ldr r3, [r7, #4]
8002b92: 6a1b ldr r3, [r3, #32]
8002b94: 617b str r3, [r7, #20]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8002b96: 687b ldr r3, [r7, #4]
8002b98: 6a1b ldr r3, [r3, #32]
8002b9a: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8002b9e: 687b ldr r3, [r7, #4]
8002ba0: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8002ba2: 687b ldr r3, [r7, #4]
8002ba4: 685b ldr r3, [r3, #4]
8002ba6: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8002ba8: 687b ldr r3, [r7, #4]
8002baa: 69db ldr r3, [r3, #28]
8002bac: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8002bae: 68fb ldr r3, [r7, #12]
8002bb0: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002bb4: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8002bb6: 68fb ldr r3, [r7, #12]
8002bb8: f423 7340 bic.w r3, r3, #768 @ 0x300
8002bbc: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8002bbe: 683b ldr r3, [r7, #0]
8002bc0: 681b ldr r3, [r3, #0]
8002bc2: 021b lsls r3, r3, #8
8002bc4: 68fa ldr r2, [r7, #12]
8002bc6: 4313 orrs r3, r2
8002bc8: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8002bca: 697b ldr r3, [r7, #20]
8002bcc: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8002bd0: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8002bd2: 683b ldr r3, [r7, #0]
8002bd4: 689b ldr r3, [r3, #8]
8002bd6: 031b lsls r3, r3, #12
8002bd8: 697a ldr r2, [r7, #20]
8002bda: 4313 orrs r3, r2
8002bdc: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8002bde: 687b ldr r3, [r7, #4]
8002be0: 693a ldr r2, [r7, #16]
8002be2: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8002be4: 687b ldr r3, [r7, #4]
8002be6: 68fa ldr r2, [r7, #12]
8002be8: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8002bea: 683b ldr r3, [r7, #0]
8002bec: 685a ldr r2, [r3, #4]
8002bee: 687b ldr r3, [r7, #4]
8002bf0: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8002bf2: 687b ldr r3, [r7, #4]
8002bf4: 697a ldr r2, [r7, #20]
8002bf6: 621a str r2, [r3, #32]
}
8002bf8: bf00 nop
8002bfa: 371c adds r7, #28
8002bfc: 46bd mov sp, r7
8002bfe: bc80 pop {r7}
8002c00: 4770 bx lr
08002c02 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8002c02: b480 push {r7}
8002c04: b087 sub sp, #28
8002c06: af00 add r7, sp, #0
8002c08: 60f8 str r0, [r7, #12]
8002c0a: 60b9 str r1, [r7, #8]
8002c0c: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8002c0e: 68fb ldr r3, [r7, #12]
8002c10: 6a1b ldr r3, [r3, #32]
8002c12: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8002c14: 68fb ldr r3, [r7, #12]
8002c16: 6a1b ldr r3, [r3, #32]
8002c18: f023 0201 bic.w r2, r3, #1
8002c1c: 68fb ldr r3, [r7, #12]
8002c1e: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8002c20: 68fb ldr r3, [r7, #12]
8002c22: 699b ldr r3, [r3, #24]
8002c24: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8002c26: 693b ldr r3, [r7, #16]
8002c28: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8002c2c: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8002c2e: 687b ldr r3, [r7, #4]
8002c30: 011b lsls r3, r3, #4
8002c32: 693a ldr r2, [r7, #16]
8002c34: 4313 orrs r3, r2
8002c36: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8002c38: 697b ldr r3, [r7, #20]
8002c3a: f023 030a bic.w r3, r3, #10
8002c3e: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8002c40: 697a ldr r2, [r7, #20]
8002c42: 68bb ldr r3, [r7, #8]
8002c44: 4313 orrs r3, r2
8002c46: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8002c48: 68fb ldr r3, [r7, #12]
8002c4a: 693a ldr r2, [r7, #16]
8002c4c: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8002c4e: 68fb ldr r3, [r7, #12]
8002c50: 697a ldr r2, [r7, #20]
8002c52: 621a str r2, [r3, #32]
}
8002c54: bf00 nop
8002c56: 371c adds r7, #28
8002c58: 46bd mov sp, r7
8002c5a: bc80 pop {r7}
8002c5c: 4770 bx lr
08002c5e <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8002c5e: b480 push {r7}
8002c60: b087 sub sp, #28
8002c62: af00 add r7, sp, #0
8002c64: 60f8 str r0, [r7, #12]
8002c66: 60b9 str r1, [r7, #8]
8002c68: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8002c6a: 68fb ldr r3, [r7, #12]
8002c6c: 6a1b ldr r3, [r3, #32]
8002c6e: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8002c70: 68fb ldr r3, [r7, #12]
8002c72: 6a1b ldr r3, [r3, #32]
8002c74: f023 0210 bic.w r2, r3, #16
8002c78: 68fb ldr r3, [r7, #12]
8002c7a: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8002c7c: 68fb ldr r3, [r7, #12]
8002c7e: 699b ldr r3, [r3, #24]
8002c80: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8002c82: 693b ldr r3, [r7, #16]
8002c84: f423 4370 bic.w r3, r3, #61440 @ 0xf000
8002c88: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
8002c8a: 687b ldr r3, [r7, #4]
8002c8c: 031b lsls r3, r3, #12
8002c8e: 693a ldr r2, [r7, #16]
8002c90: 4313 orrs r3, r2
8002c92: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8002c94: 697b ldr r3, [r7, #20]
8002c96: f023 03a0 bic.w r3, r3, #160 @ 0xa0
8002c9a: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8002c9c: 68bb ldr r3, [r7, #8]
8002c9e: 011b lsls r3, r3, #4
8002ca0: 697a ldr r2, [r7, #20]
8002ca2: 4313 orrs r3, r2
8002ca4: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8002ca6: 68fb ldr r3, [r7, #12]
8002ca8: 693a ldr r2, [r7, #16]
8002caa: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8002cac: 68fb ldr r3, [r7, #12]
8002cae: 697a ldr r2, [r7, #20]
8002cb0: 621a str r2, [r3, #32]
}
8002cb2: bf00 nop
8002cb4: 371c adds r7, #28
8002cb6: 46bd mov sp, r7
8002cb8: bc80 pop {r7}
8002cba: 4770 bx lr
08002cbc <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8002cbc: b480 push {r7}
8002cbe: b085 sub sp, #20
8002cc0: af00 add r7, sp, #0
8002cc2: 6078 str r0, [r7, #4]
8002cc4: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8002cc6: 687b ldr r3, [r7, #4]
8002cc8: 689b ldr r3, [r3, #8]
8002cca: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8002ccc: 68fb ldr r3, [r7, #12]
8002cce: f023 0370 bic.w r3, r3, #112 @ 0x70
8002cd2: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8002cd4: 683a ldr r2, [r7, #0]
8002cd6: 68fb ldr r3, [r7, #12]
8002cd8: 4313 orrs r3, r2
8002cda: f043 0307 orr.w r3, r3, #7
8002cde: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8002ce0: 687b ldr r3, [r7, #4]
8002ce2: 68fa ldr r2, [r7, #12]
8002ce4: 609a str r2, [r3, #8]
}
8002ce6: bf00 nop
8002ce8: 3714 adds r7, #20
8002cea: 46bd mov sp, r7
8002cec: bc80 pop {r7}
8002cee: 4770 bx lr
08002cf0 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8002cf0: b480 push {r7}
8002cf2: b087 sub sp, #28
8002cf4: af00 add r7, sp, #0
8002cf6: 60f8 str r0, [r7, #12]
8002cf8: 60b9 str r1, [r7, #8]
8002cfa: 607a str r2, [r7, #4]
8002cfc: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8002cfe: 68fb ldr r3, [r7, #12]
8002d00: 689b ldr r3, [r3, #8]
8002d02: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8002d04: 697b ldr r3, [r7, #20]
8002d06: f423 437f bic.w r3, r3, #65280 @ 0xff00
8002d0a: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8002d0c: 683b ldr r3, [r7, #0]
8002d0e: 021a lsls r2, r3, #8
8002d10: 687b ldr r3, [r7, #4]
8002d12: 431a orrs r2, r3
8002d14: 68bb ldr r3, [r7, #8]
8002d16: 4313 orrs r3, r2
8002d18: 697a ldr r2, [r7, #20]
8002d1a: 4313 orrs r3, r2
8002d1c: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8002d1e: 68fb ldr r3, [r7, #12]
8002d20: 697a ldr r2, [r7, #20]
8002d22: 609a str r2, [r3, #8]
}
8002d24: bf00 nop
8002d26: 371c adds r7, #28
8002d28: 46bd mov sp, r7
8002d2a: bc80 pop {r7}
8002d2c: 4770 bx lr
08002d2e <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8002d2e: b480 push {r7}
8002d30: b087 sub sp, #28
8002d32: af00 add r7, sp, #0
8002d34: 60f8 str r0, [r7, #12]
8002d36: 60b9 str r1, [r7, #8]
8002d38: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8002d3a: 68bb ldr r3, [r7, #8]
8002d3c: f003 031f and.w r3, r3, #31
8002d40: 2201 movs r2, #1
8002d42: fa02 f303 lsl.w r3, r2, r3
8002d46: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8002d48: 68fb ldr r3, [r7, #12]
8002d4a: 6a1a ldr r2, [r3, #32]
8002d4c: 697b ldr r3, [r7, #20]
8002d4e: 43db mvns r3, r3
8002d50: 401a ands r2, r3
8002d52: 68fb ldr r3, [r7, #12]
8002d54: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8002d56: 68fb ldr r3, [r7, #12]
8002d58: 6a1a ldr r2, [r3, #32]
8002d5a: 68bb ldr r3, [r7, #8]
8002d5c: f003 031f and.w r3, r3, #31
8002d60: 6879 ldr r1, [r7, #4]
8002d62: fa01 f303 lsl.w r3, r1, r3
8002d66: 431a orrs r2, r3
8002d68: 68fb ldr r3, [r7, #12]
8002d6a: 621a str r2, [r3, #32]
}
8002d6c: bf00 nop
8002d6e: 371c adds r7, #28
8002d70: 46bd mov sp, r7
8002d72: bc80 pop {r7}
8002d74: 4770 bx lr
...
08002d78 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8002d78: b480 push {r7}
8002d7a: b085 sub sp, #20
8002d7c: af00 add r7, sp, #0
8002d7e: 6078 str r0, [r7, #4]
8002d80: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8002d82: 687b ldr r3, [r7, #4]
8002d84: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8002d88: 2b01 cmp r3, #1
8002d8a: d101 bne.n 8002d90 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8002d8c: 2302 movs r3, #2
8002d8e: e046 b.n 8002e1e <HAL_TIMEx_MasterConfigSynchronization+0xa6>
8002d90: 687b ldr r3, [r7, #4]
8002d92: 2201 movs r2, #1
8002d94: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8002d98: 687b ldr r3, [r7, #4]
8002d9a: 2202 movs r2, #2
8002d9c: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8002da0: 687b ldr r3, [r7, #4]
8002da2: 681b ldr r3, [r3, #0]
8002da4: 685b ldr r3, [r3, #4]
8002da6: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8002da8: 687b ldr r3, [r7, #4]
8002daa: 681b ldr r3, [r3, #0]
8002dac: 689b ldr r3, [r3, #8]
8002dae: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8002db0: 68fb ldr r3, [r7, #12]
8002db2: f023 0370 bic.w r3, r3, #112 @ 0x70
8002db6: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8002db8: 683b ldr r3, [r7, #0]
8002dba: 681b ldr r3, [r3, #0]
8002dbc: 68fa ldr r2, [r7, #12]
8002dbe: 4313 orrs r3, r2
8002dc0: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8002dc2: 687b ldr r3, [r7, #4]
8002dc4: 681b ldr r3, [r3, #0]
8002dc6: 68fa ldr r2, [r7, #12]
8002dc8: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8002dca: 687b ldr r3, [r7, #4]
8002dcc: 681b ldr r3, [r3, #0]
8002dce: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8002dd2: d00e beq.n 8002df2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8002dd4: 687b ldr r3, [r7, #4]
8002dd6: 681b ldr r3, [r3, #0]
8002dd8: 4a13 ldr r2, [pc, #76] @ (8002e28 <HAL_TIMEx_MasterConfigSynchronization+0xb0>)
8002dda: 4293 cmp r3, r2
8002ddc: d009 beq.n 8002df2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8002dde: 687b ldr r3, [r7, #4]
8002de0: 681b ldr r3, [r3, #0]
8002de2: 4a12 ldr r2, [pc, #72] @ (8002e2c <HAL_TIMEx_MasterConfigSynchronization+0xb4>)
8002de4: 4293 cmp r3, r2
8002de6: d004 beq.n 8002df2 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8002de8: 687b ldr r3, [r7, #4]
8002dea: 681b ldr r3, [r3, #0]
8002dec: 4a10 ldr r2, [pc, #64] @ (8002e30 <HAL_TIMEx_MasterConfigSynchronization+0xb8>)
8002dee: 4293 cmp r3, r2
8002df0: d10c bne.n 8002e0c <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8002df2: 68bb ldr r3, [r7, #8]
8002df4: f023 0380 bic.w r3, r3, #128 @ 0x80
8002df8: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8002dfa: 683b ldr r3, [r7, #0]
8002dfc: 685b ldr r3, [r3, #4]
8002dfe: 68ba ldr r2, [r7, #8]
8002e00: 4313 orrs r3, r2
8002e02: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8002e04: 687b ldr r3, [r7, #4]
8002e06: 681b ldr r3, [r3, #0]
8002e08: 68ba ldr r2, [r7, #8]
8002e0a: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8002e0c: 687b ldr r3, [r7, #4]
8002e0e: 2201 movs r2, #1
8002e10: f883 2039 strb.w r2, [r3, #57] @ 0x39
__HAL_UNLOCK(htim);
8002e14: 687b ldr r3, [r7, #4]
8002e16: 2200 movs r2, #0
8002e18: f883 2038 strb.w r2, [r3, #56] @ 0x38
return HAL_OK;
8002e1c: 2300 movs r3, #0
}
8002e1e: 4618 mov r0, r3
8002e20: 3714 adds r7, #20
8002e22: 46bd mov sp, r7
8002e24: bc80 pop {r7}
8002e26: 4770 bx lr
8002e28: 40000400 .word 0x40000400
8002e2c: 40000800 .word 0x40000800
8002e30: 40010800 .word 0x40010800
08002e34 <memset>:
8002e34: 4603 mov r3, r0
8002e36: 4402 add r2, r0
8002e38: 4293 cmp r3, r2
8002e3a: d100 bne.n 8002e3e <memset+0xa>
8002e3c: 4770 bx lr
8002e3e: f803 1b01 strb.w r1, [r3], #1
8002e42: e7f9 b.n 8002e38 <memset+0x4>
08002e44 <__libc_init_array>:
8002e44: b570 push {r4, r5, r6, lr}
8002e46: 2600 movs r6, #0
8002e48: 4d0c ldr r5, [pc, #48] @ (8002e7c <__libc_init_array+0x38>)
8002e4a: 4c0d ldr r4, [pc, #52] @ (8002e80 <__libc_init_array+0x3c>)
8002e4c: 1b64 subs r4, r4, r5
8002e4e: 10a4 asrs r4, r4, #2
8002e50: 42a6 cmp r6, r4
8002e52: d109 bne.n 8002e68 <__libc_init_array+0x24>
8002e54: f000 f81a bl 8002e8c <_init>
8002e58: 2600 movs r6, #0
8002e5a: 4d0a ldr r5, [pc, #40] @ (8002e84 <__libc_init_array+0x40>)
8002e5c: 4c0a ldr r4, [pc, #40] @ (8002e88 <__libc_init_array+0x44>)
8002e5e: 1b64 subs r4, r4, r5
8002e60: 10a4 asrs r4, r4, #2
8002e62: 42a6 cmp r6, r4
8002e64: d105 bne.n 8002e72 <__libc_init_array+0x2e>
8002e66: bd70 pop {r4, r5, r6, pc}
8002e68: f855 3b04 ldr.w r3, [r5], #4
8002e6c: 4798 blx r3
8002e6e: 3601 adds r6, #1
8002e70: e7ee b.n 8002e50 <__libc_init_array+0xc>
8002e72: f855 3b04 ldr.w r3, [r5], #4
8002e76: 4798 blx r3
8002e78: 3601 adds r6, #1
8002e7a: e7f2 b.n 8002e62 <__libc_init_array+0x1e>
8002e7c: 08002ed8 .word 0x08002ed8
8002e80: 08002ed8 .word 0x08002ed8
8002e84: 08002ed8 .word 0x08002ed8
8002e88: 08002edc .word 0x08002edc
08002e8c <_init>:
8002e8c: b5f8 push {r3, r4, r5, r6, r7, lr}
8002e8e: bf00 nop
8002e90: bcf8 pop {r3, r4, r5, r6, r7}
8002e92: bc08 pop {r3}
8002e94: 469e mov lr, r3
8002e96: 4770 bx lr
08002e98 <_fini>:
8002e98: b5f8 push {r3, r4, r5, r6, r7, lr}
8002e9a: bf00 nop
8002e9c: bcf8 pop {r3, r4, r5, r6, r7}
8002e9e: bc08 pop {r3}
8002ea0: 469e mov lr, r3
8002ea2: 4770 bx lr
Reference in New Issue View Git Blame Copy Permalink