mirror of
https://github.com/BreizhHardware/TP-STM32-CIPA3.git
synced 2026-01-18 16:17:23 +01:00
6809 lines
255 KiB
Plaintext
6809 lines
255 KiB
Plaintext
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TP4_INIT_TFT.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00002850 0800013c 0800013c 0000113c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000964 0800298c 0800298c 0000398c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 080032f0 080032f0 0000505c 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 080032f0 080032f0 000042f0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 080032f8 080032f8 0000505c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 080032f8 080032f8 000042f8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 080032fc 080032fc 000042fc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 0000005c 20000000 08003300 00005000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 000001b0 2000005c 0800335c 0000505c 2**2
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ALLOC
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10 ._user_heap_stack 00000604 2000020c 0800335c 0000520c 2**0
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ALLOC
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11 .ARM.attributes 00000029 00000000 00000000 0000505c 2**0
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CONTENTS, READONLY
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12 .debug_info 0000629e 00000000 00000000 00005085 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 000016c7 00000000 00000000 0000b323 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 000006d8 00000000 00000000 0000c9f0 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 00000512 00000000 00000000 0000d0c8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 000155d9 00000000 00000000 0000d5da 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00007c47 00000000 00000000 00022bb3 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000849cb 00000000 00000000 0002a7fa 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 000af1c5 2**0
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CONTENTS, READONLY
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20 .debug_frame 00001c78 00000000 00000000 000af208 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 0000006c 00000000 00000000 000b0e80 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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0800013c <__do_global_dtors_aux>:
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800013c: b510 push {r4, lr}
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800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>)
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8000140: 7823 ldrb r3, [r4, #0]
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8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16>
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8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>)
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8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12>
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8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>)
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800014a: f3af 8000 nop.w
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800014e: 2301 movs r3, #1
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8000150: 7023 strb r3, [r4, #0]
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8000152: bd10 pop {r4, pc}
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8000154: 2000005c .word 0x2000005c
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8000158: 00000000 .word 0x00000000
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800015c: 08002974 .word 0x08002974
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08000160 <frame_dummy>:
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8000160: b508 push {r3, lr}
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8000162: 4b03 ldr r3, [pc, #12] @ (8000170 <frame_dummy+0x10>)
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8000164: b11b cbz r3, 800016e <frame_dummy+0xe>
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8000166: 4903 ldr r1, [pc, #12] @ (8000174 <frame_dummy+0x14>)
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8000168: 4803 ldr r0, [pc, #12] @ (8000178 <frame_dummy+0x18>)
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800016a: f3af 8000 nop.w
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800016e: bd08 pop {r3, pc}
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8000170: 00000000 .word 0x00000000
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8000174: 20000060 .word 0x20000060
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8000178: 08002974 .word 0x08002974
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0800017c <__aeabi_uldivmod>:
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800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18>
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800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18>
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8000180: 2900 cmp r1, #0
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8000182: bf08 it eq
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8000184: 2800 cmpeq r0, #0
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8000186: bf1c itt ne
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8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000190: f000 b98c b.w 80004ac <__aeabi_idiv0>
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8000194: f1ad 0c08 sub.w ip, sp, #8
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8000198: e96d ce04 strd ip, lr, [sp, #-16]!
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800019c: f000 f806 bl 80001ac <__udivmoddi4>
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80001a0: f8dd e004 ldr.w lr, [sp, #4]
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80001a4: e9dd 2302 ldrd r2, r3, [sp, #8]
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80001a8: b004 add sp, #16
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80001aa: 4770 bx lr
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080001ac <__udivmoddi4>:
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80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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80001b0: 9d08 ldr r5, [sp, #32]
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80001b2: 468e mov lr, r1
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80001b4: 4604 mov r4, r0
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80001b6: 4688 mov r8, r1
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80001b8: 2b00 cmp r3, #0
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80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6>
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80001bc: 428a cmp r2, r1
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80001be: 4617 mov r7, r2
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80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc>
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80001c2: fab2 f682 clz r6, r2
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80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30>
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80001c8: f1c6 0320 rsb r3, r6, #32
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80001cc: fa01 f806 lsl.w r8, r1, r6
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80001d0: fa20 f303 lsr.w r3, r0, r3
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80001d4: 40b7 lsls r7, r6
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80001d6: ea43 0808 orr.w r8, r3, r8
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80001da: 40b4 lsls r4, r6
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80001dc: ea4f 4e17 mov.w lr, r7, lsr #16
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80001e0: fbb8 f1fe udiv r1, r8, lr
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80001e4: fa1f fc87 uxth.w ip, r7
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80001e8: fb0e 8811 mls r8, lr, r1, r8
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80001ec: fb01 f20c mul.w r2, r1, ip
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80001f0: 0c23 lsrs r3, r4, #16
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80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16
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80001f6: 429a cmp r2, r3
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80001f8: d909 bls.n 800020e <__udivmoddi4+0x62>
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80001fa: 18fb adds r3, r7, r3
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80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e>
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8000204: 429a cmp r2, r3
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8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e>
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800020a: 3902 subs r1, #2
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800020c: 443b add r3, r7
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800020e: 1a9a subs r2, r3, r2
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8000210: fbb2 f0fe udiv r0, r2, lr
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8000214: fb0e 2210 mls r2, lr, r0, r2
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8000218: fb00 fc0c mul.w ip, r0, ip
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800021c: b2a3 uxth r3, r4
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800021e: ea43 4302 orr.w r3, r3, r2, lsl #16
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8000222: 459c cmp ip, r3
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8000224: d909 bls.n 800023a <__udivmoddi4+0x8e>
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8000226: 18fb adds r3, r7, r3
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8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232>
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8000230: 459c cmp ip, r3
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8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232>
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8000236: 443b add r3, r7
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8000238: 3802 subs r0, #2
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800023a: ea40 4001 orr.w r0, r0, r1, lsl #16
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800023e: 2100 movs r1, #0
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8000240: eba3 030c sub.w r3, r3, ip
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8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2>
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8000246: 2200 movs r2, #0
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8000248: 40f3 lsrs r3, r6
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800024a: e9c5 3200 strd r3, r2, [r5]
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800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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8000252: 428b cmp r3, r1
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8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6>
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8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0>
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8000258: e9c5 0100 strd r0, r1, [r5]
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800025c: 2100 movs r1, #0
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800025e: 4608 mov r0, r1
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8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2>
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8000262: fab3 f183 clz r1, r3
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8000266: 2900 cmp r1, #0
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8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c>
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800026a: 4573 cmp r3, lr
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800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8>
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800026e: 4282 cmp r2, r0
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8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8>
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8000274: 1a84 subs r4, r0, r2
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8000276: eb6e 0203 sbc.w r2, lr, r3
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800027a: 2001 movs r0, #1
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800027c: 4690 mov r8, r2
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800027e: 2d00 cmp r5, #0
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8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2>
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8000282: e9c5 4800 strd r4, r8, [r5]
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8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2>
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8000288: 2a00 cmp r2, #0
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800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204>
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800028e: fab2 f682 clz r6, r2
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8000292: 2e00 cmp r6, #0
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8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236>
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8000298: 1a8a subs r2, r1, r2
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800029a: 2101 movs r1, #1
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800029c: 0c03 lsrs r3, r0, #16
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800029e: ea4f 4e17 mov.w lr, r7, lsr #16
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80002a2: b280 uxth r0, r0
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80002a4: b2bc uxth r4, r7
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80002a6: fbb2 fcfe udiv ip, r2, lr
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80002aa: fb0e 221c mls r2, lr, ip, r2
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80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16
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80002b2: fb04 f20c mul.w r2, r4, ip
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80002b6: 429a cmp r2, r3
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80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e>
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80002ba: 18fb adds r3, r7, r3
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80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c>
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80002c2: 429a cmp r2, r3
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80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2>
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80002c8: 46c4 mov ip, r8
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80002ca: 1a9b subs r3, r3, r2
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80002cc: fbb3 f2fe udiv r2, r3, lr
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80002d0: fb0e 3312 mls r3, lr, r2, r3
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80002d4: fb02 f404 mul.w r4, r2, r4
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80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16
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80002dc: 429c cmp r4, r3
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80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144>
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80002e0: 18fb adds r3, r7, r3
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80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142>
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80002e8: 429c cmp r4, r3
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80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc>
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80002ee: 4602 mov r2, r0
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80002f0: 1b1b subs r3, r3, r4
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80002f2: ea42 400c orr.w r0, r2, ip, lsl #16
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80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98>
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80002f8: f1c1 0620 rsb r6, r1, #32
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80002fc: 408b lsls r3, r1
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80002fe: fa22 f706 lsr.w r7, r2, r6
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8000302: 431f orrs r7, r3
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8000304: fa2e fa06 lsr.w sl, lr, r6
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8000308: ea4f 4917 mov.w r9, r7, lsr #16
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800030c: fbba f8f9 udiv r8, sl, r9
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8000310: fa0e fe01 lsl.w lr, lr, r1
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8000314: fa20 f306 lsr.w r3, r0, r6
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8000318: fb09 aa18 mls sl, r9, r8, sl
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800031c: fa1f fc87 uxth.w ip, r7
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8000320: ea43 030e orr.w r3, r3, lr
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8000324: fa00 fe01 lsl.w lr, r0, r1
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8000328: fb08 f00c mul.w r0, r8, ip
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800032c: 0c1c lsrs r4, r3, #16
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800032e: ea44 440a orr.w r4, r4, sl, lsl #16
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8000332: 42a0 cmp r0, r4
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8000334: fa02 f201 lsl.w r2, r2, r1
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8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4>
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800033a: 193c adds r4, r7, r4
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800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff
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8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4>
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8000344: 42a0 cmp r0, r4
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8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4>
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800034a: f1a8 0802 sub.w r8, r8, #2
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800034e: 443c add r4, r7
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8000350: 1a24 subs r4, r4, r0
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8000352: b298 uxth r0, r3
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8000354: fbb4 f3f9 udiv r3, r4, r9
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8000358: fb09 4413 mls r4, r9, r3, r4
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800035c: fb03 fc0c mul.w ip, r3, ip
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8000360: ea40 4404 orr.w r4, r0, r4, lsl #16
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8000364: 45a4 cmp ip, r4
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8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0>
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8000368: 193c adds r4, r7, r4
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800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff
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800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0>
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8000372: 45a4 cmp ip, r4
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8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0>
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8000378: 3b02 subs r3, #2
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800037a: 443c add r4, r7
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800037c: ea43 4008 orr.w r0, r3, r8, lsl #16
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8000380: eba4 040c sub.w r4, r4, ip
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8000384: fba0 8c02 umull r8, ip, r0, r2
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8000388: 4564 cmp r4, ip
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800038a: 4643 mov r3, r8
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800038c: 46e1 mov r9, ip
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800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae>
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8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa>
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8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200>
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8000394: ebbe 0203 subs.w r2, lr, r3
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8000398: eb64 0409 sbc.w r4, r4, r9
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800039c: fa04 f606 lsl.w r6, r4, r6
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80003a0: fa22 f301 lsr.w r3, r2, r1
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80003a4: 431e orrs r6, r3
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80003a6: 40cc lsrs r4, r1
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80003a8: e9c5 6400 strd r6, r4, [r5]
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80003ac: 2100 movs r1, #0
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80003ae: e74e b.n 800024e <__udivmoddi4+0xa2>
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80003b0: fbb1 fcf2 udiv ip, r1, r2
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80003b4: 0c01 lsrs r1, r0, #16
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80003b6: ea41 410e orr.w r1, r1, lr, lsl #16
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80003ba: b280 uxth r0, r0
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80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16
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80003c0: 463b mov r3, r7
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80003c2: fbb1 f1f7 udiv r1, r1, r7
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80003c6: 4638 mov r0, r7
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80003c8: 463c mov r4, r7
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80003ca: 46b8 mov r8, r7
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80003cc: 46be mov lr, r7
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80003ce: 2620 movs r6, #32
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80003d0: eba2 0208 sub.w r2, r2, r8
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80003d4: ea41 410c orr.w r1, r1, ip, lsl #16
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80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa>
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80003da: 4601 mov r1, r0
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80003dc: e717 b.n 800020e <__udivmoddi4+0x62>
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80003de: 4610 mov r0, r2
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80003e0: e72b b.n 800023a <__udivmoddi4+0x8e>
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80003e2: f1c6 0120 rsb r1, r6, #32
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80003e6: fa2e fc01 lsr.w ip, lr, r1
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80003ea: 40b7 lsls r7, r6
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80003ec: fa0e fe06 lsl.w lr, lr, r6
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80003f0: fa20 f101 lsr.w r1, r0, r1
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80003f4: ea41 010e orr.w r1, r1, lr
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80003f8: ea4f 4e17 mov.w lr, r7, lsr #16
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80003fc: fbbc f8fe udiv r8, ip, lr
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8000400: b2bc uxth r4, r7
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8000402: fb0e cc18 mls ip, lr, r8, ip
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8000406: fb08 f904 mul.w r9, r8, r4
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800040a: 0c0a lsrs r2, r1, #16
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800040c: ea42 420c orr.w r2, r2, ip, lsl #16
|
|
8000410: 40b0 lsls r0, r6
|
|
8000412: 4591 cmp r9, r2
|
|
8000414: ea4f 4310 mov.w r3, r0, lsr #16
|
|
8000418: b280 uxth r0, r0
|
|
800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee>
|
|
800041c: 18ba adds r2, r7, r2
|
|
800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c>
|
|
8000424: 4591 cmp r9, r2
|
|
8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc>
|
|
8000428: eba2 0209 sub.w r2, r2, r9
|
|
800042c: fbb2 f9fe udiv r9, r2, lr
|
|
8000430: fb09 f804 mul.w r8, r9, r4
|
|
8000434: fb0e 2a19 mls sl, lr, r9, r2
|
|
8000438: b28a uxth r2, r1
|
|
800043a: ea42 420a orr.w r2, r2, sl, lsl #16
|
|
800043e: 4542 cmp r2, r8
|
|
8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea>
|
|
8000442: 18ba adds r2, r7, r2
|
|
8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224>
|
|
800044a: 4542 cmp r2, r8
|
|
800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224>
|
|
800044e: f1a9 0102 sub.w r1, r9, #2
|
|
8000452: 443a add r2, r7
|
|
8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224>
|
|
8000456: 45c6 cmp lr, r8
|
|
8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6>
|
|
800045a: ebb8 0302 subs.w r3, r8, r2
|
|
800045e: eb6c 0c07 sbc.w ip, ip, r7
|
|
8000462: 3801 subs r0, #1
|
|
8000464: 46e1 mov r9, ip
|
|
8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6>
|
|
8000468: eba7 0909 sub.w r9, r7, r9
|
|
800046c: 444a add r2, r9
|
|
800046e: fbb2 f9fe udiv r9, r2, lr
|
|
8000472: f1a8 0c02 sub.w ip, r8, #2
|
|
8000476: fb09 f804 mul.w r8, r9, r4
|
|
800047a: e7db b.n 8000434 <__udivmoddi4+0x288>
|
|
800047c: 4603 mov r3, r0
|
|
800047e: e77d b.n 800037c <__udivmoddi4+0x1d0>
|
|
8000480: 46d0 mov r8, sl
|
|
8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4>
|
|
8000484: 4608 mov r0, r1
|
|
8000486: e6fa b.n 800027e <__udivmoddi4+0xd2>
|
|
8000488: 443b add r3, r7
|
|
800048a: 3a02 subs r2, #2
|
|
800048c: e730 b.n 80002f0 <__udivmoddi4+0x144>
|
|
800048e: f1ac 0c02 sub.w ip, ip, #2
|
|
8000492: 443b add r3, r7
|
|
8000494: e719 b.n 80002ca <__udivmoddi4+0x11e>
|
|
8000496: 4649 mov r1, r9
|
|
8000498: e79a b.n 80003d0 <__udivmoddi4+0x224>
|
|
800049a: eba2 0209 sub.w r2, r2, r9
|
|
800049e: fbb2 f9fe udiv r9, r2, lr
|
|
80004a2: 46c4 mov ip, r8
|
|
80004a4: fb09 f804 mul.w r8, r9, r4
|
|
80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288>
|
|
80004aa: bf00 nop
|
|
|
|
080004ac <__aeabi_idiv0>:
|
|
80004ac: 4770 bx lr
|
|
80004ae: bf00 nop
|
|
|
|
080004b0 <affiche_nombre>:
|
|
|
|
/* USER CODE END PFP */
|
|
|
|
/* Private user code ---------------------------------------------------------*/
|
|
/* USER CODE BEGIN 0 */
|
|
void affiche_nombre(char nombre[], uint8_t col, uint8_t ligne) {
|
|
80004b0: b580 push {r7, lr}
|
|
80004b2: b086 sub sp, #24
|
|
80004b4: af02 add r7, sp, #8
|
|
80004b6: 6078 str r0, [r7, #4]
|
|
80004b8: 460b mov r3, r1
|
|
80004ba: 70fb strb r3, [r7, #3]
|
|
80004bc: 4613 mov r3, r2
|
|
80004be: 70bb strb r3, [r7, #2]
|
|
int nombre_int = atoi(nombre);
|
|
80004c0: 6878 ldr r0, [r7, #4]
|
|
80004c2: f002 f99d bl 8002800 <atoi>
|
|
80004c6: 60f8 str r0, [r7, #12]
|
|
|
|
if (nombre_int < 0 || nombre_int > 9999) {
|
|
80004c8: 68fb ldr r3, [r7, #12]
|
|
80004ca: 2b00 cmp r3, #0
|
|
80004cc: f2c0 8087 blt.w 80005de <affiche_nombre+0x12e>
|
|
80004d0: 68fb ldr r3, [r7, #12]
|
|
80004d2: f242 720f movw r2, #9999 @ 0x270f
|
|
80004d6: 4293 cmp r3, r2
|
|
80004d8: f300 8081 bgt.w 80005de <affiche_nombre+0x12e>
|
|
return;
|
|
}
|
|
|
|
uint8_t mil = nombre_int / 1000;
|
|
80004dc: 68fb ldr r3, [r7, #12]
|
|
80004de: 4a42 ldr r2, [pc, #264] @ (80005e8 <affiche_nombre+0x138>)
|
|
80004e0: fb82 1203 smull r1, r2, r2, r3
|
|
80004e4: 1192 asrs r2, r2, #6
|
|
80004e6: 17db asrs r3, r3, #31
|
|
80004e8: 1ad3 subs r3, r2, r3
|
|
80004ea: 72fb strb r3, [r7, #11]
|
|
uint8_t cen = (nombre_int / 100) % 10;
|
|
80004ec: 68fb ldr r3, [r7, #12]
|
|
80004ee: 4a3f ldr r2, [pc, #252] @ (80005ec <affiche_nombre+0x13c>)
|
|
80004f0: fb82 1203 smull r1, r2, r2, r3
|
|
80004f4: 1152 asrs r2, r2, #5
|
|
80004f6: 17db asrs r3, r3, #31
|
|
80004f8: 1ad2 subs r2, r2, r3
|
|
80004fa: 4b3d ldr r3, [pc, #244] @ (80005f0 <affiche_nombre+0x140>)
|
|
80004fc: fb83 1302 smull r1, r3, r3, r2
|
|
8000500: 1099 asrs r1, r3, #2
|
|
8000502: 17d3 asrs r3, r2, #31
|
|
8000504: 1ac9 subs r1, r1, r3
|
|
8000506: 460b mov r3, r1
|
|
8000508: 009b lsls r3, r3, #2
|
|
800050a: 440b add r3, r1
|
|
800050c: 005b lsls r3, r3, #1
|
|
800050e: 1ad1 subs r1, r2, r3
|
|
8000510: 460b mov r3, r1
|
|
8000512: 72bb strb r3, [r7, #10]
|
|
uint8_t diz = (nombre_int / 10) % 10;
|
|
8000514: 68fb ldr r3, [r7, #12]
|
|
8000516: 4a36 ldr r2, [pc, #216] @ (80005f0 <affiche_nombre+0x140>)
|
|
8000518: fb82 1203 smull r1, r2, r2, r3
|
|
800051c: 1092 asrs r2, r2, #2
|
|
800051e: 17db asrs r3, r3, #31
|
|
8000520: 1ad2 subs r2, r2, r3
|
|
8000522: 4b33 ldr r3, [pc, #204] @ (80005f0 <affiche_nombre+0x140>)
|
|
8000524: fb83 1302 smull r1, r3, r3, r2
|
|
8000528: 1099 asrs r1, r3, #2
|
|
800052a: 17d3 asrs r3, r2, #31
|
|
800052c: 1ac9 subs r1, r1, r3
|
|
800052e: 460b mov r3, r1
|
|
8000530: 009b lsls r3, r3, #2
|
|
8000532: 440b add r3, r1
|
|
8000534: 005b lsls r3, r3, #1
|
|
8000536: 1ad1 subs r1, r2, r3
|
|
8000538: 460b mov r3, r1
|
|
800053a: 727b strb r3, [r7, #9]
|
|
uint8_t uni = nombre_int % 10;
|
|
800053c: 68fa ldr r2, [r7, #12]
|
|
800053e: 4b2c ldr r3, [pc, #176] @ (80005f0 <affiche_nombre+0x140>)
|
|
8000540: fb83 1302 smull r1, r3, r3, r2
|
|
8000544: 1099 asrs r1, r3, #2
|
|
8000546: 17d3 asrs r3, r2, #31
|
|
8000548: 1ac9 subs r1, r1, r3
|
|
800054a: 460b mov r3, r1
|
|
800054c: 009b lsls r3, r3, #2
|
|
800054e: 440b add r3, r1
|
|
8000550: 005b lsls r3, r3, #1
|
|
8000552: 1ad1 subs r1, r2, r3
|
|
8000554: 460b mov r3, r1
|
|
8000556: 723b strb r3, [r7, #8]
|
|
|
|
displayChar_TFT(col, ligne, mil + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
|
|
8000558: 78fb ldrb r3, [r7, #3]
|
|
800055a: b298 uxth r0, r3
|
|
800055c: 78bb ldrb r3, [r7, #2]
|
|
800055e: b299 uxth r1, r3
|
|
8000560: 7afb ldrb r3, [r7, #11]
|
|
8000562: 3330 adds r3, #48 @ 0x30
|
|
8000564: b2da uxtb r2, r3
|
|
8000566: 2302 movs r3, #2
|
|
8000568: 9301 str r3, [sp, #4]
|
|
800056a: 2300 movs r3, #0
|
|
800056c: 9300 str r3, [sp, #0]
|
|
800056e: f64f 73e0 movw r3, #65504 @ 0xffe0
|
|
8000572: f001 ffc7 bl 8002504 <displayChar_TFT>
|
|
displayChar_TFT(col + 12, ligne, cen + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
|
|
8000576: 78fb ldrb r3, [r7, #3]
|
|
8000578: b29b uxth r3, r3
|
|
800057a: 330c adds r3, #12
|
|
800057c: b298 uxth r0, r3
|
|
800057e: 78bb ldrb r3, [r7, #2]
|
|
8000580: b299 uxth r1, r3
|
|
8000582: 7abb ldrb r3, [r7, #10]
|
|
8000584: 3330 adds r3, #48 @ 0x30
|
|
8000586: b2da uxtb r2, r3
|
|
8000588: 2302 movs r3, #2
|
|
800058a: 9301 str r3, [sp, #4]
|
|
800058c: 2300 movs r3, #0
|
|
800058e: 9300 str r3, [sp, #0]
|
|
8000590: f64f 73e0 movw r3, #65504 @ 0xffe0
|
|
8000594: f001 ffb6 bl 8002504 <displayChar_TFT>
|
|
displayChar_TFT(col + 24, ligne, diz + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
|
|
8000598: 78fb ldrb r3, [r7, #3]
|
|
800059a: b29b uxth r3, r3
|
|
800059c: 3318 adds r3, #24
|
|
800059e: b298 uxth r0, r3
|
|
80005a0: 78bb ldrb r3, [r7, #2]
|
|
80005a2: b299 uxth r1, r3
|
|
80005a4: 7a7b ldrb r3, [r7, #9]
|
|
80005a6: 3330 adds r3, #48 @ 0x30
|
|
80005a8: b2da uxtb r2, r3
|
|
80005aa: 2302 movs r3, #2
|
|
80005ac: 9301 str r3, [sp, #4]
|
|
80005ae: 2300 movs r3, #0
|
|
80005b0: 9300 str r3, [sp, #0]
|
|
80005b2: f64f 73e0 movw r3, #65504 @ 0xffe0
|
|
80005b6: f001 ffa5 bl 8002504 <displayChar_TFT>
|
|
displayChar_TFT(col + 36, ligne, uni + 0x30, ST7735_YELLOW, ST7735_BLACK, 2);
|
|
80005ba: 78fb ldrb r3, [r7, #3]
|
|
80005bc: b29b uxth r3, r3
|
|
80005be: 3324 adds r3, #36 @ 0x24
|
|
80005c0: b298 uxth r0, r3
|
|
80005c2: 78bb ldrb r3, [r7, #2]
|
|
80005c4: b299 uxth r1, r3
|
|
80005c6: 7a3b ldrb r3, [r7, #8]
|
|
80005c8: 3330 adds r3, #48 @ 0x30
|
|
80005ca: b2da uxtb r2, r3
|
|
80005cc: 2302 movs r3, #2
|
|
80005ce: 9301 str r3, [sp, #4]
|
|
80005d0: 2300 movs r3, #0
|
|
80005d2: 9300 str r3, [sp, #0]
|
|
80005d4: f64f 73e0 movw r3, #65504 @ 0xffe0
|
|
80005d8: f001 ff94 bl 8002504 <displayChar_TFT>
|
|
80005dc: e000 b.n 80005e0 <affiche_nombre+0x130>
|
|
return;
|
|
80005de: bf00 nop
|
|
}
|
|
80005e0: 3710 adds r7, #16
|
|
80005e2: 46bd mov sp, r7
|
|
80005e4: bd80 pop {r7, pc}
|
|
80005e6: bf00 nop
|
|
80005e8: 10624dd3 .word 0x10624dd3
|
|
80005ec: 51eb851f .word 0x51eb851f
|
|
80005f0: 66666667 .word 0x66666667
|
|
|
|
080005f4 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
80005f4: b580 push {r7, lr}
|
|
80005f6: b082 sub sp, #8
|
|
80005f8: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
80005fa: f000 fa75 bl 8000ae8 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
80005fe: f000 f817 bl 8000630 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000602: f000 f891 bl 8000728 <MX_GPIO_Init>
|
|
MX_SPI1_Init();
|
|
8000606: f000 f859 bl 80006bc <MX_SPI1_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
MAX7219_Init();
|
|
800060a: f000 f9f0 bl 80009ee <MAX7219_Init>
|
|
init_TFT();
|
|
800060e: f001 fe6f bl 80022f0 <init_TFT>
|
|
MAX7219_Clear();
|
|
8000612: f000 fa23 bl 8000a5c <MAX7219_Clear>
|
|
|
|
/* USER CODE END 2 */
|
|
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
char nombre[] = "4090";
|
|
8000616: 4b05 ldr r3, [pc, #20] @ (800062c <main+0x38>)
|
|
8000618: 603b str r3, [r7, #0]
|
|
800061a: 2300 movs r3, #0
|
|
800061c: 713b strb r3, [r7, #4]
|
|
while (1)
|
|
{
|
|
/* USER CODE END WHILE */
|
|
|
|
/* USER CODE BEGIN 3 */
|
|
affiche_nombre(nombre, 10, 80);
|
|
800061e: 463b mov r3, r7
|
|
8000620: 2250 movs r2, #80 @ 0x50
|
|
8000622: 210a movs r1, #10
|
|
8000624: 4618 mov r0, r3
|
|
8000626: f7ff ff43 bl 80004b0 <affiche_nombre>
|
|
800062a: e7f8 b.n 800061e <main+0x2a>
|
|
800062c: 30393034 .word 0x30393034
|
|
|
|
08000630 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000630: b580 push {r7, lr}
|
|
8000632: b092 sub sp, #72 @ 0x48
|
|
8000634: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8000636: f107 0314 add.w r3, r7, #20
|
|
800063a: 2234 movs r2, #52 @ 0x34
|
|
800063c: 2100 movs r1, #0
|
|
800063e: 4618 mov r0, r3
|
|
8000640: f002 f966 bl 8002910 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8000644: 463b mov r3, r7
|
|
8000646: 2200 movs r2, #0
|
|
8000648: 601a str r2, [r3, #0]
|
|
800064a: 605a str r2, [r3, #4]
|
|
800064c: 609a str r2, [r3, #8]
|
|
800064e: 60da str r2, [r3, #12]
|
|
8000650: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8000652: 4b19 ldr r3, [pc, #100] @ (80006b8 <SystemClock_Config+0x88>)
|
|
8000654: 681b ldr r3, [r3, #0]
|
|
8000656: f423 53c0 bic.w r3, r3, #6144 @ 0x1800
|
|
800065a: 4a17 ldr r2, [pc, #92] @ (80006b8 <SystemClock_Config+0x88>)
|
|
800065c: f443 6300 orr.w r3, r3, #2048 @ 0x800
|
|
8000660: 6013 str r3, [r2, #0]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
8000662: 2302 movs r3, #2
|
|
8000664: 617b str r3, [r7, #20]
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
8000666: 2301 movs r3, #1
|
|
8000668: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
800066a: 2310 movs r3, #16
|
|
800066c: 627b str r3, [r7, #36] @ 0x24
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
|
800066e: 2300 movs r3, #0
|
|
8000670: 63bb str r3, [r7, #56] @ 0x38
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000672: f107 0314 add.w r3, r7, #20
|
|
8000676: 4618 mov r0, r3
|
|
8000678: f000 fd52 bl 8001120 <HAL_RCC_OscConfig>
|
|
800067c: 4603 mov r3, r0
|
|
800067e: 2b00 cmp r3, #0
|
|
8000680: d001 beq.n 8000686 <SystemClock_Config+0x56>
|
|
{
|
|
Error_Handler();
|
|
8000682: f000 f8e5 bl 8000850 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8000686: 230f movs r3, #15
|
|
8000688: 603b str r3, [r7, #0]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
|
800068a: 2301 movs r3, #1
|
|
800068c: 607b str r3, [r7, #4]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
800068e: 2300 movs r3, #0
|
|
8000690: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8000692: 2300 movs r3, #0
|
|
8000694: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8000696: 2300 movs r3, #0
|
|
8000698: 613b str r3, [r7, #16]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
|
800069a: 463b mov r3, r7
|
|
800069c: 2100 movs r1, #0
|
|
800069e: 4618 mov r0, r3
|
|
80006a0: f001 f86e bl 8001780 <HAL_RCC_ClockConfig>
|
|
80006a4: 4603 mov r3, r0
|
|
80006a6: 2b00 cmp r3, #0
|
|
80006a8: d001 beq.n 80006ae <SystemClock_Config+0x7e>
|
|
{
|
|
Error_Handler();
|
|
80006aa: f000 f8d1 bl 8000850 <Error_Handler>
|
|
}
|
|
}
|
|
80006ae: bf00 nop
|
|
80006b0: 3748 adds r7, #72 @ 0x48
|
|
80006b2: 46bd mov sp, r7
|
|
80006b4: bd80 pop {r7, pc}
|
|
80006b6: bf00 nop
|
|
80006b8: 40007000 .word 0x40007000
|
|
|
|
080006bc <MX_SPI1_Init>:
|
|
* @brief SPI1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI1_Init(void)
|
|
{
|
|
80006bc: b580 push {r7, lr}
|
|
80006be: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI1_Init 1 */
|
|
|
|
/* USER CODE END SPI1_Init 1 */
|
|
/* SPI1 parameter configuration*/
|
|
hspi1.Instance = SPI1;
|
|
80006c0: 4b17 ldr r3, [pc, #92] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006c2: 4a18 ldr r2, [pc, #96] @ (8000724 <MX_SPI1_Init+0x68>)
|
|
80006c4: 601a str r2, [r3, #0]
|
|
hspi1.Init.Mode = SPI_MODE_MASTER;
|
|
80006c6: 4b16 ldr r3, [pc, #88] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006c8: f44f 7282 mov.w r2, #260 @ 0x104
|
|
80006cc: 605a str r2, [r3, #4]
|
|
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
|
|
80006ce: 4b14 ldr r3, [pc, #80] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006d0: 2200 movs r2, #0
|
|
80006d2: 609a str r2, [r3, #8]
|
|
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
|
|
80006d4: 4b12 ldr r3, [pc, #72] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006d6: 2200 movs r2, #0
|
|
80006d8: 60da str r2, [r3, #12]
|
|
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
80006da: 4b11 ldr r3, [pc, #68] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006dc: 2200 movs r2, #0
|
|
80006de: 611a str r2, [r3, #16]
|
|
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
80006e0: 4b0f ldr r3, [pc, #60] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006e2: 2200 movs r2, #0
|
|
80006e4: 615a str r2, [r3, #20]
|
|
hspi1.Init.NSS = SPI_NSS_SOFT;
|
|
80006e6: 4b0e ldr r3, [pc, #56] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006e8: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80006ec: 619a str r2, [r3, #24]
|
|
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
80006ee: 4b0c ldr r3, [pc, #48] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006f0: 2200 movs r2, #0
|
|
80006f2: 61da str r2, [r3, #28]
|
|
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
80006f4: 4b0a ldr r3, [pc, #40] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006f6: 2200 movs r2, #0
|
|
80006f8: 621a str r2, [r3, #32]
|
|
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
80006fa: 4b09 ldr r3, [pc, #36] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
80006fc: 2200 movs r2, #0
|
|
80006fe: 625a str r2, [r3, #36] @ 0x24
|
|
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8000700: 4b07 ldr r3, [pc, #28] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
8000702: 2200 movs r2, #0
|
|
8000704: 629a str r2, [r3, #40] @ 0x28
|
|
hspi1.Init.CRCPolynomial = 10;
|
|
8000706: 4b06 ldr r3, [pc, #24] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
8000708: 220a movs r2, #10
|
|
800070a: 62da str r2, [r3, #44] @ 0x2c
|
|
if (HAL_SPI_Init(&hspi1) != HAL_OK)
|
|
800070c: 4804 ldr r0, [pc, #16] @ (8000720 <MX_SPI1_Init+0x64>)
|
|
800070e: f001 fa89 bl 8001c24 <HAL_SPI_Init>
|
|
8000712: 4603 mov r3, r0
|
|
8000714: 2b00 cmp r3, #0
|
|
8000716: d001 beq.n 800071c <MX_SPI1_Init+0x60>
|
|
{
|
|
Error_Handler();
|
|
8000718: f000 f89a bl 8000850 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI1_Init 2 */
|
|
|
|
/* USER CODE END SPI1_Init 2 */
|
|
|
|
}
|
|
800071c: bf00 nop
|
|
800071e: bd80 pop {r7, pc}
|
|
8000720: 20000078 .word 0x20000078
|
|
8000724: 40013000 .word 0x40013000
|
|
|
|
08000728 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000728: b580 push {r7, lr}
|
|
800072a: b08a sub sp, #40 @ 0x28
|
|
800072c: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800072e: f107 0314 add.w r3, r7, #20
|
|
8000732: 2200 movs r2, #0
|
|
8000734: 601a str r2, [r3, #0]
|
|
8000736: 605a str r2, [r3, #4]
|
|
8000738: 609a str r2, [r3, #8]
|
|
800073a: 60da str r2, [r3, #12]
|
|
800073c: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800073e: 4b40 ldr r3, [pc, #256] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000740: 69db ldr r3, [r3, #28]
|
|
8000742: 4a3f ldr r2, [pc, #252] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000744: f043 0304 orr.w r3, r3, #4
|
|
8000748: 61d3 str r3, [r2, #28]
|
|
800074a: 4b3d ldr r3, [pc, #244] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
800074c: 69db ldr r3, [r3, #28]
|
|
800074e: f003 0304 and.w r3, r3, #4
|
|
8000752: 613b str r3, [r7, #16]
|
|
8000754: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000756: 4b3a ldr r3, [pc, #232] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000758: 69db ldr r3, [r3, #28]
|
|
800075a: 4a39 ldr r2, [pc, #228] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
800075c: f043 0301 orr.w r3, r3, #1
|
|
8000760: 61d3 str r3, [r2, #28]
|
|
8000762: 4b37 ldr r3, [pc, #220] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000764: 69db ldr r3, [r3, #28]
|
|
8000766: f003 0301 and.w r3, r3, #1
|
|
800076a: 60fb str r3, [r7, #12]
|
|
800076c: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800076e: 4b34 ldr r3, [pc, #208] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000770: 69db ldr r3, [r3, #28]
|
|
8000772: 4a33 ldr r2, [pc, #204] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000774: f043 0302 orr.w r3, r3, #2
|
|
8000778: 61d3 str r3, [r2, #28]
|
|
800077a: 4b31 ldr r3, [pc, #196] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
800077c: 69db ldr r3, [r3, #28]
|
|
800077e: f003 0302 and.w r3, r3, #2
|
|
8000782: 60bb str r3, [r7, #8]
|
|
8000784: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000786: 4b2e ldr r3, [pc, #184] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000788: 69db ldr r3, [r3, #28]
|
|
800078a: 4a2d ldr r2, [pc, #180] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
800078c: f043 0308 orr.w r3, r3, #8
|
|
8000790: 61d3 str r3, [r2, #28]
|
|
8000792: 4b2b ldr r3, [pc, #172] @ (8000840 <MX_GPIO_Init+0x118>)
|
|
8000794: 69db ldr r3, [r3, #28]
|
|
8000796: f003 0308 and.w r3, r3, #8
|
|
800079a: 607b str r3, [r7, #4]
|
|
800079c: 687b ldr r3, [r7, #4]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_0, GPIO_PIN_RESET);
|
|
800079e: 2200 movs r2, #0
|
|
80007a0: 2101 movs r1, #1
|
|
80007a2: 4828 ldr r0, [pc, #160] @ (8000844 <MX_GPIO_Init+0x11c>)
|
|
80007a4: f000 fca4 bl 80010f0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, GPIO_PIN_SET);
|
|
80007a8: 2201 movs r2, #1
|
|
80007aa: 210e movs r1, #14
|
|
80007ac: 4825 ldr r0, [pc, #148] @ (8000844 <MX_GPIO_Init+0x11c>)
|
|
80007ae: f000 fc9f bl 80010f0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOD, GPIO_PIN_2, GPIO_PIN_SET);
|
|
80007b2: 2201 movs r2, #1
|
|
80007b4: 2104 movs r1, #4
|
|
80007b6: 4824 ldr r0, [pc, #144] @ (8000848 <MX_GPIO_Init+0x120>)
|
|
80007b8: f000 fc9a bl 80010f0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : PC0 PC1 PC2 PC3 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
|
|
80007bc: 230f movs r3, #15
|
|
80007be: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80007c0: 2301 movs r3, #1
|
|
80007c2: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80007c4: 2300 movs r3, #0
|
|
80007c6: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80007c8: 2300 movs r3, #0
|
|
80007ca: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80007cc: f107 0314 add.w r3, r7, #20
|
|
80007d0: 4619 mov r1, r3
|
|
80007d2: 481c ldr r0, [pc, #112] @ (8000844 <MX_GPIO_Init+0x11c>)
|
|
80007d4: f000 fafc bl 8000dd0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PB15 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_15;
|
|
80007d8: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80007dc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80007de: 2302 movs r3, #2
|
|
80007e0: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80007e2: 2300 movs r3, #0
|
|
80007e4: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80007e6: 2300 movs r3, #0
|
|
80007e8: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF3_TIM11;
|
|
80007ea: 2303 movs r3, #3
|
|
80007ec: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80007ee: f107 0314 add.w r3, r7, #20
|
|
80007f2: 4619 mov r1, r3
|
|
80007f4: 4815 ldr r0, [pc, #84] @ (800084c <MX_GPIO_Init+0x124>)
|
|
80007f6: f000 faeb bl 8000dd0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PD2 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
80007fa: 2304 movs r3, #4
|
|
80007fc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80007fe: 2301 movs r3, #1
|
|
8000800: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000802: 2300 movs r3, #0
|
|
8000804: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000806: 2300 movs r3, #0
|
|
8000808: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
800080a: f107 0314 add.w r3, r7, #20
|
|
800080e: 4619 mov r1, r3
|
|
8000810: 480d ldr r0, [pc, #52] @ (8000848 <MX_GPIO_Init+0x120>)
|
|
8000812: f000 fadd bl 8000dd0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PB7 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_7;
|
|
8000816: 2380 movs r3, #128 @ 0x80
|
|
8000818: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800081a: 2302 movs r3, #2
|
|
800081c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800081e: 2300 movs r3, #0
|
|
8000820: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000822: 2300 movs r3, #0
|
|
8000824: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
|
|
8000826: 2302 movs r3, #2
|
|
8000828: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
800082a: f107 0314 add.w r3, r7, #20
|
|
800082e: 4619 mov r1, r3
|
|
8000830: 4806 ldr r0, [pc, #24] @ (800084c <MX_GPIO_Init+0x124>)
|
|
8000832: f000 facd bl 8000dd0 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000836: bf00 nop
|
|
8000838: 3728 adds r7, #40 @ 0x28
|
|
800083a: 46bd mov sp, r7
|
|
800083c: bd80 pop {r7, pc}
|
|
800083e: bf00 nop
|
|
8000840: 40023800 .word 0x40023800
|
|
8000844: 40020800 .word 0x40020800
|
|
8000848: 40020c00 .word 0x40020c00
|
|
800084c: 40020400 .word 0x40020400
|
|
|
|
08000850 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000850: b480 push {r7}
|
|
8000852: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000854: b672 cpsid i
|
|
}
|
|
8000856: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000858: bf00 nop
|
|
800085a: e7fd b.n 8000858 <Error_Handler+0x8>
|
|
|
|
0800085c <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
800085c: b480 push {r7}
|
|
800085e: b085 sub sp, #20
|
|
8000860: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_COMP_CLK_ENABLE();
|
|
8000862: 4b14 ldr r3, [pc, #80] @ (80008b4 <HAL_MspInit+0x58>)
|
|
8000864: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8000866: 4a13 ldr r2, [pc, #76] @ (80008b4 <HAL_MspInit+0x58>)
|
|
8000868: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
800086c: 6253 str r3, [r2, #36] @ 0x24
|
|
800086e: 4b11 ldr r3, [pc, #68] @ (80008b4 <HAL_MspInit+0x58>)
|
|
8000870: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8000872: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8000876: 60fb str r3, [r7, #12]
|
|
8000878: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800087a: 4b0e ldr r3, [pc, #56] @ (80008b4 <HAL_MspInit+0x58>)
|
|
800087c: 6a1b ldr r3, [r3, #32]
|
|
800087e: 4a0d ldr r2, [pc, #52] @ (80008b4 <HAL_MspInit+0x58>)
|
|
8000880: f043 0301 orr.w r3, r3, #1
|
|
8000884: 6213 str r3, [r2, #32]
|
|
8000886: 4b0b ldr r3, [pc, #44] @ (80008b4 <HAL_MspInit+0x58>)
|
|
8000888: 6a1b ldr r3, [r3, #32]
|
|
800088a: f003 0301 and.w r3, r3, #1
|
|
800088e: 60bb str r3, [r7, #8]
|
|
8000890: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000892: 4b08 ldr r3, [pc, #32] @ (80008b4 <HAL_MspInit+0x58>)
|
|
8000894: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8000896: 4a07 ldr r2, [pc, #28] @ (80008b4 <HAL_MspInit+0x58>)
|
|
8000898: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800089c: 6253 str r3, [r2, #36] @ 0x24
|
|
800089e: 4b05 ldr r3, [pc, #20] @ (80008b4 <HAL_MspInit+0x58>)
|
|
80008a0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80008a2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80008a6: 607b str r3, [r7, #4]
|
|
80008a8: 687b ldr r3, [r7, #4]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
80008aa: bf00 nop
|
|
80008ac: 3714 adds r7, #20
|
|
80008ae: 46bd mov sp, r7
|
|
80008b0: bc80 pop {r7}
|
|
80008b2: 4770 bx lr
|
|
80008b4: 40023800 .word 0x40023800
|
|
|
|
080008b8 <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
80008b8: b580 push {r7, lr}
|
|
80008ba: b08a sub sp, #40 @ 0x28
|
|
80008bc: af00 add r7, sp, #0
|
|
80008be: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80008c0: f107 0314 add.w r3, r7, #20
|
|
80008c4: 2200 movs r2, #0
|
|
80008c6: 601a str r2, [r3, #0]
|
|
80008c8: 605a str r2, [r3, #4]
|
|
80008ca: 609a str r2, [r3, #8]
|
|
80008cc: 60da str r2, [r3, #12]
|
|
80008ce: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI1)
|
|
80008d0: 687b ldr r3, [r7, #4]
|
|
80008d2: 681b ldr r3, [r3, #0]
|
|
80008d4: 4a17 ldr r2, [pc, #92] @ (8000934 <HAL_SPI_MspInit+0x7c>)
|
|
80008d6: 4293 cmp r3, r2
|
|
80008d8: d127 bne.n 800092a <HAL_SPI_MspInit+0x72>
|
|
{
|
|
/* USER CODE BEGIN SPI1_MspInit 0 */
|
|
|
|
/* USER CODE END SPI1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI1_CLK_ENABLE();
|
|
80008da: 4b17 ldr r3, [pc, #92] @ (8000938 <HAL_SPI_MspInit+0x80>)
|
|
80008dc: 6a1b ldr r3, [r3, #32]
|
|
80008de: 4a16 ldr r2, [pc, #88] @ (8000938 <HAL_SPI_MspInit+0x80>)
|
|
80008e0: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
80008e4: 6213 str r3, [r2, #32]
|
|
80008e6: 4b14 ldr r3, [pc, #80] @ (8000938 <HAL_SPI_MspInit+0x80>)
|
|
80008e8: 6a1b ldr r3, [r3, #32]
|
|
80008ea: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80008ee: 613b str r3, [r7, #16]
|
|
80008f0: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80008f2: 4b11 ldr r3, [pc, #68] @ (8000938 <HAL_SPI_MspInit+0x80>)
|
|
80008f4: 69db ldr r3, [r3, #28]
|
|
80008f6: 4a10 ldr r2, [pc, #64] @ (8000938 <HAL_SPI_MspInit+0x80>)
|
|
80008f8: f043 0301 orr.w r3, r3, #1
|
|
80008fc: 61d3 str r3, [r2, #28]
|
|
80008fe: 4b0e ldr r3, [pc, #56] @ (8000938 <HAL_SPI_MspInit+0x80>)
|
|
8000900: 69db ldr r3, [r3, #28]
|
|
8000902: f003 0301 and.w r3, r3, #1
|
|
8000906: 60fb str r3, [r7, #12]
|
|
8000908: 68fb ldr r3, [r7, #12]
|
|
/**SPI1 GPIO Configuration
|
|
PA5 ------> SPI1_SCK
|
|
PA6 ------> SPI1_MISO
|
|
PA7 ------> SPI1_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
|
|
800090a: 23e0 movs r3, #224 @ 0xe0
|
|
800090c: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800090e: 2302 movs r3, #2
|
|
8000910: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000912: 2300 movs r3, #0
|
|
8000914: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8000916: 2303 movs r3, #3
|
|
8000918: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
|
800091a: 2305 movs r3, #5
|
|
800091c: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800091e: f107 0314 add.w r3, r7, #20
|
|
8000922: 4619 mov r1, r3
|
|
8000924: 4805 ldr r0, [pc, #20] @ (800093c <HAL_SPI_MspInit+0x84>)
|
|
8000926: f000 fa53 bl 8000dd0 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END SPI1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
800092a: bf00 nop
|
|
800092c: 3728 adds r7, #40 @ 0x28
|
|
800092e: 46bd mov sp, r7
|
|
8000930: bd80 pop {r7, pc}
|
|
8000932: bf00 nop
|
|
8000934: 40013000 .word 0x40013000
|
|
8000938: 40023800 .word 0x40023800
|
|
800093c: 40020000 .word 0x40020000
|
|
|
|
08000940 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8000940: b480 push {r7}
|
|
8000942: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8000944: bf00 nop
|
|
8000946: e7fd b.n 8000944 <NMI_Handler+0x4>
|
|
|
|
08000948 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8000948: b480 push {r7}
|
|
800094a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
800094c: bf00 nop
|
|
800094e: e7fd b.n 800094c <HardFault_Handler+0x4>
|
|
|
|
08000950 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8000950: b480 push {r7}
|
|
8000952: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8000954: bf00 nop
|
|
8000956: e7fd b.n 8000954 <MemManage_Handler+0x4>
|
|
|
|
08000958 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8000958: b480 push {r7}
|
|
800095a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
800095c: bf00 nop
|
|
800095e: e7fd b.n 800095c <BusFault_Handler+0x4>
|
|
|
|
08000960 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8000960: b480 push {r7}
|
|
8000962: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8000964: bf00 nop
|
|
8000966: e7fd b.n 8000964 <UsageFault_Handler+0x4>
|
|
|
|
08000968 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8000968: b480 push {r7}
|
|
800096a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVC_IRQn 0 */
|
|
/* USER CODE BEGIN SVC_IRQn 1 */
|
|
|
|
/* USER CODE END SVC_IRQn 1 */
|
|
}
|
|
800096c: bf00 nop
|
|
800096e: 46bd mov sp, r7
|
|
8000970: bc80 pop {r7}
|
|
8000972: 4770 bx lr
|
|
|
|
08000974 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8000974: b480 push {r7}
|
|
8000976: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8000978: bf00 nop
|
|
800097a: 46bd mov sp, r7
|
|
800097c: bc80 pop {r7}
|
|
800097e: 4770 bx lr
|
|
|
|
08000980 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8000980: b480 push {r7}
|
|
8000982: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8000984: bf00 nop
|
|
8000986: 46bd mov sp, r7
|
|
8000988: bc80 pop {r7}
|
|
800098a: 4770 bx lr
|
|
|
|
0800098c <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
800098c: b580 push {r7, lr}
|
|
800098e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8000990: f000 f8fc bl 8000b8c <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8000994: bf00 nop
|
|
8000996: bd80 pop {r7, pc}
|
|
|
|
08000998 <SystemInit>:
|
|
* SystemCoreClock variable.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit (void)
|
|
{
|
|
8000998: b480 push {r7}
|
|
800099a: af00 add r7, sp, #0
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
800099c: bf00 nop
|
|
800099e: 46bd mov sp, r7
|
|
80009a0: bc80 pop {r7}
|
|
80009a2: 4770 bx lr
|
|
|
|
080009a4 <Reset_Handler>:
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
80009a4: f7ff fff8 bl 8000998 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
80009a8: 480b ldr r0, [pc, #44] @ (80009d8 <LoopFillZerobss+0xe>)
|
|
ldr r1, =_edata
|
|
80009aa: 490c ldr r1, [pc, #48] @ (80009dc <LoopFillZerobss+0x12>)
|
|
ldr r2, =_sidata
|
|
80009ac: 4a0c ldr r2, [pc, #48] @ (80009e0 <LoopFillZerobss+0x16>)
|
|
movs r3, #0
|
|
80009ae: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
80009b0: e002 b.n 80009b8 <LoopCopyDataInit>
|
|
|
|
080009b2 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
80009b2: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
80009b4: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
80009b6: 3304 adds r3, #4
|
|
|
|
080009b8 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
80009b8: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
80009ba: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
80009bc: d3f9 bcc.n 80009b2 <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
80009be: 4a09 ldr r2, [pc, #36] @ (80009e4 <LoopFillZerobss+0x1a>)
|
|
ldr r4, =_ebss
|
|
80009c0: 4c09 ldr r4, [pc, #36] @ (80009e8 <LoopFillZerobss+0x1e>)
|
|
movs r3, #0
|
|
80009c2: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
80009c4: e001 b.n 80009ca <LoopFillZerobss>
|
|
|
|
080009c6 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
80009c6: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
80009c8: 3204 adds r2, #4
|
|
|
|
080009ca <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
80009ca: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
80009cc: d3fb bcc.n 80009c6 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
80009ce: f001 ffad bl 800292c <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
80009d2: f7ff fe0f bl 80005f4 <main>
|
|
bx lr
|
|
80009d6: 4770 bx lr
|
|
ldr r0, =_sdata
|
|
80009d8: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
80009dc: 2000005c .word 0x2000005c
|
|
ldr r2, =_sidata
|
|
80009e0: 08003300 .word 0x08003300
|
|
ldr r2, =_sbss
|
|
80009e4: 2000005c .word 0x2000005c
|
|
ldr r4, =_ebss
|
|
80009e8: 2000020c .word 0x2000020c
|
|
|
|
080009ec <ADC1_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80009ec: e7fe b.n 80009ec <ADC1_IRQHandler>
|
|
|
|
080009ee <MAX7219_Init>:
|
|
* Arguments : none
|
|
* Returns : none
|
|
*********************************************************************************************************
|
|
*/
|
|
void MAX7219_Init (void)
|
|
{
|
|
80009ee: b580 push {r7, lr}
|
|
80009f0: af00 add r7, sp, #0
|
|
// configure "LOAD" as output
|
|
|
|
MAX7219_Write(REG_SCAN_LIMIT, 7); // set up to scan all eight digits
|
|
80009f2: 2107 movs r1, #7
|
|
80009f4: 200b movs r0, #11
|
|
80009f6: f000 f847 bl 8000a88 <MAX7219_Write>
|
|
MAX7219_Write(REG_DECODE, 0x00); // set to "no decode" for all digits
|
|
80009fa: 2100 movs r1, #0
|
|
80009fc: 2009 movs r0, #9
|
|
80009fe: f000 f843 bl 8000a88 <MAX7219_Write>
|
|
MAX7219_ShutdownStop(); // select normal operation (i.e. not shutdown)
|
|
8000a02: f000 f809 bl 8000a18 <MAX7219_ShutdownStop>
|
|
MAX7219_DisplayTestStop(); // select normal operation (i.e. not test mode)
|
|
8000a06: f000 f80f bl 8000a28 <MAX7219_DisplayTestStop>
|
|
MAX7219_Clear(); // clear all digits
|
|
8000a0a: f000 f827 bl 8000a5c <MAX7219_Clear>
|
|
MAX7219_SetBrightness(INTENSITY_MAX); // set to maximum intensity
|
|
8000a0e: 200f movs r0, #15
|
|
8000a10: f000 f812 bl 8000a38 <MAX7219_SetBrightness>
|
|
}
|
|
8000a14: bf00 nop
|
|
8000a16: bd80 pop {r7, pc}
|
|
|
|
08000a18 <MAX7219_ShutdownStop>:
|
|
* Arguments : none
|
|
* Returns : none
|
|
*********************************************************************************************************
|
|
*/
|
|
void MAX7219_ShutdownStop (void)
|
|
{
|
|
8000a18: b580 push {r7, lr}
|
|
8000a1a: af00 add r7, sp, #0
|
|
MAX7219_Write(REG_SHUTDOWN, 1); // put MAX7219 into "normal" mode
|
|
8000a1c: 2101 movs r1, #1
|
|
8000a1e: 200c movs r0, #12
|
|
8000a20: f000 f832 bl 8000a88 <MAX7219_Write>
|
|
}
|
|
8000a24: bf00 nop
|
|
8000a26: bd80 pop {r7, pc}
|
|
|
|
08000a28 <MAX7219_DisplayTestStop>:
|
|
* Arguments : none
|
|
* Returns : none
|
|
*********************************************************************************************************
|
|
*/
|
|
void MAX7219_DisplayTestStop (void)
|
|
{
|
|
8000a28: b580 push {r7, lr}
|
|
8000a2a: af00 add r7, sp, #0
|
|
MAX7219_Write(REG_DISPLAY_TEST, 0); // put MAX7219 into "normal" mode
|
|
8000a2c: 2100 movs r1, #0
|
|
8000a2e: 200f movs r0, #15
|
|
8000a30: f000 f82a bl 8000a88 <MAX7219_Write>
|
|
}
|
|
8000a34: bf00 nop
|
|
8000a36: bd80 pop {r7, pc}
|
|
|
|
08000a38 <MAX7219_SetBrightness>:
|
|
* Arguments : brightness (0-15)
|
|
* Returns : none
|
|
*********************************************************************************************************
|
|
*/
|
|
void MAX7219_SetBrightness (char brightness)
|
|
{
|
|
8000a38: b580 push {r7, lr}
|
|
8000a3a: b082 sub sp, #8
|
|
8000a3c: af00 add r7, sp, #0
|
|
8000a3e: 4603 mov r3, r0
|
|
8000a40: 71fb strb r3, [r7, #7]
|
|
brightness &= 0x0f; // mask off extra bits
|
|
8000a42: 79fb ldrb r3, [r7, #7]
|
|
8000a44: f003 030f and.w r3, r3, #15
|
|
8000a48: 71fb strb r3, [r7, #7]
|
|
MAX7219_Write(REG_INTENSITY, brightness); // set brightness
|
|
8000a4a: 79fb ldrb r3, [r7, #7]
|
|
8000a4c: 4619 mov r1, r3
|
|
8000a4e: 200a movs r0, #10
|
|
8000a50: f000 f81a bl 8000a88 <MAX7219_Write>
|
|
}
|
|
8000a54: bf00 nop
|
|
8000a56: 3708 adds r7, #8
|
|
8000a58: 46bd mov sp, r7
|
|
8000a5a: bd80 pop {r7, pc}
|
|
|
|
08000a5c <MAX7219_Clear>:
|
|
* Arguments : none
|
|
* Returns : none
|
|
*********************************************************************************************************
|
|
*/
|
|
void MAX7219_Clear (void)
|
|
{
|
|
8000a5c: b580 push {r7, lr}
|
|
8000a5e: b082 sub sp, #8
|
|
8000a60: af00 add r7, sp, #0
|
|
char i;
|
|
for (i=0; i < 8; i++)
|
|
8000a62: 2300 movs r3, #0
|
|
8000a64: 71fb strb r3, [r7, #7]
|
|
8000a66: e007 b.n 8000a78 <MAX7219_Clear+0x1c>
|
|
MAX7219_Write(i, 0x00); // turn all segments off
|
|
8000a68: 79fb ldrb r3, [r7, #7]
|
|
8000a6a: 2100 movs r1, #0
|
|
8000a6c: 4618 mov r0, r3
|
|
8000a6e: f000 f80b bl 8000a88 <MAX7219_Write>
|
|
for (i=0; i < 8; i++)
|
|
8000a72: 79fb ldrb r3, [r7, #7]
|
|
8000a74: 3301 adds r3, #1
|
|
8000a76: 71fb strb r3, [r7, #7]
|
|
8000a78: 79fb ldrb r3, [r7, #7]
|
|
8000a7a: 2b07 cmp r3, #7
|
|
8000a7c: d9f4 bls.n 8000a68 <MAX7219_Clear+0xc>
|
|
}
|
|
8000a7e: bf00 nop
|
|
8000a80: bf00 nop
|
|
8000a82: 3708 adds r7, #8
|
|
8000a84: 46bd mov sp, r7
|
|
8000a86: bd80 pop {r7, pc}
|
|
|
|
08000a88 <MAX7219_Write>:
|
|
* dataout = data to write to MAX7219
|
|
* Returns : none
|
|
*********************************************************************************************************
|
|
*/
|
|
void MAX7219_Write (unsigned char reg_number, unsigned char dataout)
|
|
{
|
|
8000a88: b580 push {r7, lr}
|
|
8000a8a: b082 sub sp, #8
|
|
8000a8c: af00 add r7, sp, #0
|
|
8000a8e: 4603 mov r3, r0
|
|
8000a90: 460a mov r2, r1
|
|
8000a92: 71fb strb r3, [r7, #7]
|
|
8000a94: 4613 mov r3, r2
|
|
8000a96: 71bb strb r3, [r7, #6]
|
|
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN<<16;// nCS = 0 // take LOAD high to begin
|
|
8000a98: 4b09 ldr r3, [pc, #36] @ (8000ac0 <MAX7219_Write+0x38>)
|
|
8000a9a: f44f 3280 mov.w r2, #65536 @ 0x10000
|
|
8000a9e: 619a str r2, [r3, #24]
|
|
MAX7219_SendByte(reg_number); // write register number to MAX7219
|
|
8000aa0: 79fb ldrb r3, [r7, #7]
|
|
8000aa2: 4618 mov r0, r3
|
|
8000aa4: f000 f80e bl 8000ac4 <MAX7219_SendByte>
|
|
MAX7219_SendByte(dataout); // write data to MAX7219
|
|
8000aa8: 79bb ldrb r3, [r7, #6]
|
|
8000aaa: 4618 mov r0, r3
|
|
8000aac: f000 f80a bl 8000ac4 <MAX7219_SendByte>
|
|
MAX7219_nCS_PORT->BSRR = (uint32_t)MAX7219_nCS_PIN;// nCS = 1 // take LOAD low to latch in data
|
|
8000ab0: 4b03 ldr r3, [pc, #12] @ (8000ac0 <MAX7219_Write+0x38>)
|
|
8000ab2: 2201 movs r2, #1
|
|
8000ab4: 619a str r2, [r3, #24]
|
|
}
|
|
8000ab6: bf00 nop
|
|
8000ab8: 3708 adds r7, #8
|
|
8000aba: 46bd mov sp, r7
|
|
8000abc: bd80 pop {r7, pc}
|
|
8000abe: bf00 nop
|
|
8000ac0: 40020800 .word 0x40020800
|
|
|
|
08000ac4 <MAX7219_SendByte>:
|
|
* Returns : none
|
|
*********************************************************************************************************
|
|
*/
|
|
|
|
static void MAX7219_SendByte (unsigned char dataout)
|
|
{
|
|
8000ac4: b580 push {r7, lr}
|
|
8000ac6: b082 sub sp, #8
|
|
8000ac8: af00 add r7, sp, #0
|
|
8000aca: 4603 mov r3, r0
|
|
8000acc: 71fb strb r3, [r7, #7]
|
|
|
|
HAL_SPI_Transmit(&hspi1, &dataout, 1, 1000);
|
|
8000ace: 1df9 adds r1, r7, #7
|
|
8000ad0: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000ad4: 2201 movs r2, #1
|
|
8000ad6: 4803 ldr r0, [pc, #12] @ (8000ae4 <MAX7219_SendByte+0x20>)
|
|
8000ad8: f001 f92d bl 8001d36 <HAL_SPI_Transmit>
|
|
|
|
}
|
|
8000adc: bf00 nop
|
|
8000ade: 3708 adds r7, #8
|
|
8000ae0: 46bd mov sp, r7
|
|
8000ae2: bd80 pop {r7, pc}
|
|
8000ae4: 20000078 .word 0x20000078
|
|
|
|
08000ae8 <HAL_Init>:
|
|
* In the default implementation,Systick is used as source of time base.
|
|
* the tick variable is incremented each 1ms in its ISR.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8000ae8: b580 push {r7, lr}
|
|
8000aea: b082 sub sp, #8
|
|
8000aec: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8000aee: 2300 movs r3, #0
|
|
8000af0: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8000af2: 2003 movs r0, #3
|
|
8000af4: f000 f938 bl 8000d68 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
8000af8: 200f movs r0, #15
|
|
8000afa: f000 f80d bl 8000b18 <HAL_InitTick>
|
|
8000afe: 4603 mov r3, r0
|
|
8000b00: 2b00 cmp r3, #0
|
|
8000b02: d002 beq.n 8000b0a <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
8000b04: 2301 movs r3, #1
|
|
8000b06: 71fb strb r3, [r7, #7]
|
|
8000b08: e001 b.n 8000b0e <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
8000b0a: f7ff fea7 bl 800085c <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8000b0e: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8000b10: 4618 mov r0, r3
|
|
8000b12: 3708 adds r7, #8
|
|
8000b14: 46bd mov sp, r7
|
|
8000b16: bd80 pop {r7, pc}
|
|
|
|
08000b18 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8000b18: b580 push {r7, lr}
|
|
8000b1a: b084 sub sp, #16
|
|
8000b1c: af00 add r7, sp, #0
|
|
8000b1e: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8000b20: 2300 movs r3, #0
|
|
8000b22: 73fb strb r3, [r7, #15]
|
|
|
|
if (uwTickFreq != 0U)
|
|
8000b24: 4b16 ldr r3, [pc, #88] @ (8000b80 <HAL_InitTick+0x68>)
|
|
8000b26: 681b ldr r3, [r3, #0]
|
|
8000b28: 2b00 cmp r3, #0
|
|
8000b2a: d022 beq.n 8000b72 <HAL_InitTick+0x5a>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
|
|
8000b2c: 4b15 ldr r3, [pc, #84] @ (8000b84 <HAL_InitTick+0x6c>)
|
|
8000b2e: 681a ldr r2, [r3, #0]
|
|
8000b30: 4b13 ldr r3, [pc, #76] @ (8000b80 <HAL_InitTick+0x68>)
|
|
8000b32: 681b ldr r3, [r3, #0]
|
|
8000b34: f44f 717a mov.w r1, #1000 @ 0x3e8
|
|
8000b38: fbb1 f3f3 udiv r3, r1, r3
|
|
8000b3c: fbb2 f3f3 udiv r3, r2, r3
|
|
8000b40: 4618 mov r0, r3
|
|
8000b42: f000 f938 bl 8000db6 <HAL_SYSTICK_Config>
|
|
8000b46: 4603 mov r3, r0
|
|
8000b48: 2b00 cmp r3, #0
|
|
8000b4a: d10f bne.n 8000b6c <HAL_InitTick+0x54>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8000b4c: 687b ldr r3, [r7, #4]
|
|
8000b4e: 2b0f cmp r3, #15
|
|
8000b50: d809 bhi.n 8000b66 <HAL_InitTick+0x4e>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
8000b52: 2200 movs r2, #0
|
|
8000b54: 6879 ldr r1, [r7, #4]
|
|
8000b56: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8000b5a: f000 f910 bl 8000d7e <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8000b5e: 4a0a ldr r2, [pc, #40] @ (8000b88 <HAL_InitTick+0x70>)
|
|
8000b60: 687b ldr r3, [r7, #4]
|
|
8000b62: 6013 str r3, [r2, #0]
|
|
8000b64: e007 b.n 8000b76 <HAL_InitTick+0x5e>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000b66: 2301 movs r3, #1
|
|
8000b68: 73fb strb r3, [r7, #15]
|
|
8000b6a: e004 b.n 8000b76 <HAL_InitTick+0x5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000b6c: 2301 movs r3, #1
|
|
8000b6e: 73fb strb r3, [r7, #15]
|
|
8000b70: e001 b.n 8000b76 <HAL_InitTick+0x5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8000b72: 2301 movs r3, #1
|
|
8000b74: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8000b76: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8000b78: 4618 mov r0, r3
|
|
8000b7a: 3710 adds r7, #16
|
|
8000b7c: 46bd mov sp, r7
|
|
8000b7e: bd80 pop {r7, pc}
|
|
8000b80: 20000008 .word 0x20000008
|
|
8000b84: 20000000 .word 0x20000000
|
|
8000b88: 20000004 .word 0x20000004
|
|
|
|
08000b8c <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8000b8c: b480 push {r7}
|
|
8000b8e: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8000b90: 4b05 ldr r3, [pc, #20] @ (8000ba8 <HAL_IncTick+0x1c>)
|
|
8000b92: 681a ldr r2, [r3, #0]
|
|
8000b94: 4b05 ldr r3, [pc, #20] @ (8000bac <HAL_IncTick+0x20>)
|
|
8000b96: 681b ldr r3, [r3, #0]
|
|
8000b98: 4413 add r3, r2
|
|
8000b9a: 4a03 ldr r2, [pc, #12] @ (8000ba8 <HAL_IncTick+0x1c>)
|
|
8000b9c: 6013 str r3, [r2, #0]
|
|
}
|
|
8000b9e: bf00 nop
|
|
8000ba0: 46bd mov sp, r7
|
|
8000ba2: bc80 pop {r7}
|
|
8000ba4: 4770 bx lr
|
|
8000ba6: bf00 nop
|
|
8000ba8: 200000d0 .word 0x200000d0
|
|
8000bac: 20000008 .word 0x20000008
|
|
|
|
08000bb0 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8000bb0: b480 push {r7}
|
|
8000bb2: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8000bb4: 4b02 ldr r3, [pc, #8] @ (8000bc0 <HAL_GetTick+0x10>)
|
|
8000bb6: 681b ldr r3, [r3, #0]
|
|
}
|
|
8000bb8: 4618 mov r0, r3
|
|
8000bba: 46bd mov sp, r7
|
|
8000bbc: bc80 pop {r7}
|
|
8000bbe: 4770 bx lr
|
|
8000bc0: 200000d0 .word 0x200000d0
|
|
|
|
08000bc4 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8000bc4: b580 push {r7, lr}
|
|
8000bc6: b084 sub sp, #16
|
|
8000bc8: af00 add r7, sp, #0
|
|
8000bca: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8000bcc: f7ff fff0 bl 8000bb0 <HAL_GetTick>
|
|
8000bd0: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8000bd2: 687b ldr r3, [r7, #4]
|
|
8000bd4: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a period to guaranty minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8000bd6: 68fb ldr r3, [r7, #12]
|
|
8000bd8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8000bdc: d004 beq.n 8000be8 <HAL_Delay+0x24>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8000bde: 4b09 ldr r3, [pc, #36] @ (8000c04 <HAL_Delay+0x40>)
|
|
8000be0: 681b ldr r3, [r3, #0]
|
|
8000be2: 68fa ldr r2, [r7, #12]
|
|
8000be4: 4413 add r3, r2
|
|
8000be6: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
8000be8: bf00 nop
|
|
8000bea: f7ff ffe1 bl 8000bb0 <HAL_GetTick>
|
|
8000bee: 4602 mov r2, r0
|
|
8000bf0: 68bb ldr r3, [r7, #8]
|
|
8000bf2: 1ad3 subs r3, r2, r3
|
|
8000bf4: 68fa ldr r2, [r7, #12]
|
|
8000bf6: 429a cmp r2, r3
|
|
8000bf8: d8f7 bhi.n 8000bea <HAL_Delay+0x26>
|
|
{
|
|
}
|
|
}
|
|
8000bfa: bf00 nop
|
|
8000bfc: bf00 nop
|
|
8000bfe: 3710 adds r7, #16
|
|
8000c00: 46bd mov sp, r7
|
|
8000c02: bd80 pop {r7, pc}
|
|
8000c04: 20000008 .word 0x20000008
|
|
|
|
08000c08 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8000c08: b480 push {r7}
|
|
8000c0a: b085 sub sp, #20
|
|
8000c0c: af00 add r7, sp, #0
|
|
8000c0e: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000c10: 687b ldr r3, [r7, #4]
|
|
8000c12: f003 0307 and.w r3, r3, #7
|
|
8000c16: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8000c18: 4b0c ldr r3, [pc, #48] @ (8000c4c <__NVIC_SetPriorityGrouping+0x44>)
|
|
8000c1a: 68db ldr r3, [r3, #12]
|
|
8000c1c: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8000c1e: 68ba ldr r2, [r7, #8]
|
|
8000c20: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8000c24: 4013 ands r3, r2
|
|
8000c26: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
8000c28: 68fb ldr r3, [r7, #12]
|
|
8000c2a: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8000c2c: 68bb ldr r3, [r7, #8]
|
|
8000c2e: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8000c30: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
8000c34: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8000c38: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
8000c3a: 4a04 ldr r2, [pc, #16] @ (8000c4c <__NVIC_SetPriorityGrouping+0x44>)
|
|
8000c3c: 68bb ldr r3, [r7, #8]
|
|
8000c3e: 60d3 str r3, [r2, #12]
|
|
}
|
|
8000c40: bf00 nop
|
|
8000c42: 3714 adds r7, #20
|
|
8000c44: 46bd mov sp, r7
|
|
8000c46: bc80 pop {r7}
|
|
8000c48: 4770 bx lr
|
|
8000c4a: bf00 nop
|
|
8000c4c: e000ed00 .word 0xe000ed00
|
|
|
|
08000c50 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8000c50: b480 push {r7}
|
|
8000c52: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8000c54: 4b04 ldr r3, [pc, #16] @ (8000c68 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8000c56: 68db ldr r3, [r3, #12]
|
|
8000c58: 0a1b lsrs r3, r3, #8
|
|
8000c5a: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8000c5e: 4618 mov r0, r3
|
|
8000c60: 46bd mov sp, r7
|
|
8000c62: bc80 pop {r7}
|
|
8000c64: 4770 bx lr
|
|
8000c66: bf00 nop
|
|
8000c68: e000ed00 .word 0xe000ed00
|
|
|
|
08000c6c <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8000c6c: b480 push {r7}
|
|
8000c6e: b083 sub sp, #12
|
|
8000c70: af00 add r7, sp, #0
|
|
8000c72: 4603 mov r3, r0
|
|
8000c74: 6039 str r1, [r7, #0]
|
|
8000c76: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8000c78: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000c7c: 2b00 cmp r3, #0
|
|
8000c7e: db0a blt.n 8000c96 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000c80: 683b ldr r3, [r7, #0]
|
|
8000c82: b2da uxtb r2, r3
|
|
8000c84: 490c ldr r1, [pc, #48] @ (8000cb8 <__NVIC_SetPriority+0x4c>)
|
|
8000c86: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8000c8a: 0112 lsls r2, r2, #4
|
|
8000c8c: b2d2 uxtb r2, r2
|
|
8000c8e: 440b add r3, r1
|
|
8000c90: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8000c94: e00a b.n 8000cac <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8000c96: 683b ldr r3, [r7, #0]
|
|
8000c98: b2da uxtb r2, r3
|
|
8000c9a: 4908 ldr r1, [pc, #32] @ (8000cbc <__NVIC_SetPriority+0x50>)
|
|
8000c9c: 79fb ldrb r3, [r7, #7]
|
|
8000c9e: f003 030f and.w r3, r3, #15
|
|
8000ca2: 3b04 subs r3, #4
|
|
8000ca4: 0112 lsls r2, r2, #4
|
|
8000ca6: b2d2 uxtb r2, r2
|
|
8000ca8: 440b add r3, r1
|
|
8000caa: 761a strb r2, [r3, #24]
|
|
}
|
|
8000cac: bf00 nop
|
|
8000cae: 370c adds r7, #12
|
|
8000cb0: 46bd mov sp, r7
|
|
8000cb2: bc80 pop {r7}
|
|
8000cb4: 4770 bx lr
|
|
8000cb6: bf00 nop
|
|
8000cb8: e000e100 .word 0xe000e100
|
|
8000cbc: e000ed00 .word 0xe000ed00
|
|
|
|
08000cc0 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000cc0: b480 push {r7}
|
|
8000cc2: b089 sub sp, #36 @ 0x24
|
|
8000cc4: af00 add r7, sp, #0
|
|
8000cc6: 60f8 str r0, [r7, #12]
|
|
8000cc8: 60b9 str r1, [r7, #8]
|
|
8000cca: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8000ccc: 68fb ldr r3, [r7, #12]
|
|
8000cce: f003 0307 and.w r3, r3, #7
|
|
8000cd2: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8000cd4: 69fb ldr r3, [r7, #28]
|
|
8000cd6: f1c3 0307 rsb r3, r3, #7
|
|
8000cda: 2b04 cmp r3, #4
|
|
8000cdc: bf28 it cs
|
|
8000cde: 2304 movcs r3, #4
|
|
8000ce0: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8000ce2: 69fb ldr r3, [r7, #28]
|
|
8000ce4: 3304 adds r3, #4
|
|
8000ce6: 2b06 cmp r3, #6
|
|
8000ce8: d902 bls.n 8000cf0 <NVIC_EncodePriority+0x30>
|
|
8000cea: 69fb ldr r3, [r7, #28]
|
|
8000cec: 3b03 subs r3, #3
|
|
8000cee: e000 b.n 8000cf2 <NVIC_EncodePriority+0x32>
|
|
8000cf0: 2300 movs r3, #0
|
|
8000cf2: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000cf4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8000cf8: 69bb ldr r3, [r7, #24]
|
|
8000cfa: fa02 f303 lsl.w r3, r2, r3
|
|
8000cfe: 43da mvns r2, r3
|
|
8000d00: 68bb ldr r3, [r7, #8]
|
|
8000d02: 401a ands r2, r3
|
|
8000d04: 697b ldr r3, [r7, #20]
|
|
8000d06: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8000d08: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
8000d0c: 697b ldr r3, [r7, #20]
|
|
8000d0e: fa01 f303 lsl.w r3, r1, r3
|
|
8000d12: 43d9 mvns r1, r3
|
|
8000d14: 687b ldr r3, [r7, #4]
|
|
8000d16: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8000d18: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8000d1a: 4618 mov r0, r3
|
|
8000d1c: 3724 adds r7, #36 @ 0x24
|
|
8000d1e: 46bd mov sp, r7
|
|
8000d20: bc80 pop {r7}
|
|
8000d22: 4770 bx lr
|
|
|
|
08000d24 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8000d24: b580 push {r7, lr}
|
|
8000d26: b082 sub sp, #8
|
|
8000d28: af00 add r7, sp, #0
|
|
8000d2a: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8000d2c: 687b ldr r3, [r7, #4]
|
|
8000d2e: 3b01 subs r3, #1
|
|
8000d30: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8000d34: d301 bcc.n 8000d3a <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8000d36: 2301 movs r3, #1
|
|
8000d38: e00f b.n 8000d5a <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8000d3a: 4a0a ldr r2, [pc, #40] @ (8000d64 <SysTick_Config+0x40>)
|
|
8000d3c: 687b ldr r3, [r7, #4]
|
|
8000d3e: 3b01 subs r3, #1
|
|
8000d40: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8000d42: 210f movs r1, #15
|
|
8000d44: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8000d48: f7ff ff90 bl 8000c6c <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8000d4c: 4b05 ldr r3, [pc, #20] @ (8000d64 <SysTick_Config+0x40>)
|
|
8000d4e: 2200 movs r2, #0
|
|
8000d50: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8000d52: 4b04 ldr r3, [pc, #16] @ (8000d64 <SysTick_Config+0x40>)
|
|
8000d54: 2207 movs r2, #7
|
|
8000d56: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8000d58: 2300 movs r3, #0
|
|
}
|
|
8000d5a: 4618 mov r0, r3
|
|
8000d5c: 3708 adds r7, #8
|
|
8000d5e: 46bd mov sp, r7
|
|
8000d60: bd80 pop {r7, pc}
|
|
8000d62: bf00 nop
|
|
8000d64: e000e010 .word 0xe000e010
|
|
|
|
08000d68 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8000d68: b580 push {r7, lr}
|
|
8000d6a: b082 sub sp, #8
|
|
8000d6c: af00 add r7, sp, #0
|
|
8000d6e: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8000d70: 6878 ldr r0, [r7, #4]
|
|
8000d72: f7ff ff49 bl 8000c08 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8000d76: bf00 nop
|
|
8000d78: 3708 adds r7, #8
|
|
8000d7a: 46bd mov sp, r7
|
|
8000d7c: bd80 pop {r7, pc}
|
|
|
|
08000d7e <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8000d7e: b580 push {r7, lr}
|
|
8000d80: b086 sub sp, #24
|
|
8000d82: af00 add r7, sp, #0
|
|
8000d84: 4603 mov r3, r0
|
|
8000d86: 60b9 str r1, [r7, #8]
|
|
8000d88: 607a str r2, [r7, #4]
|
|
8000d8a: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8000d8c: 2300 movs r3, #0
|
|
8000d8e: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8000d90: f7ff ff5e bl 8000c50 <__NVIC_GetPriorityGrouping>
|
|
8000d94: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8000d96: 687a ldr r2, [r7, #4]
|
|
8000d98: 68b9 ldr r1, [r7, #8]
|
|
8000d9a: 6978 ldr r0, [r7, #20]
|
|
8000d9c: f7ff ff90 bl 8000cc0 <NVIC_EncodePriority>
|
|
8000da0: 4602 mov r2, r0
|
|
8000da2: f997 300f ldrsb.w r3, [r7, #15]
|
|
8000da6: 4611 mov r1, r2
|
|
8000da8: 4618 mov r0, r3
|
|
8000daa: f7ff ff5f bl 8000c6c <__NVIC_SetPriority>
|
|
}
|
|
8000dae: bf00 nop
|
|
8000db0: 3718 adds r7, #24
|
|
8000db2: 46bd mov sp, r7
|
|
8000db4: bd80 pop {r7, pc}
|
|
|
|
08000db6 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8000db6: b580 push {r7, lr}
|
|
8000db8: b082 sub sp, #8
|
|
8000dba: af00 add r7, sp, #0
|
|
8000dbc: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8000dbe: 6878 ldr r0, [r7, #4]
|
|
8000dc0: f7ff ffb0 bl 8000d24 <SysTick_Config>
|
|
8000dc4: 4603 mov r3, r0
|
|
}
|
|
8000dc6: 4618 mov r0, r3
|
|
8000dc8: 3708 adds r7, #8
|
|
8000dca: 46bd mov sp, r7
|
|
8000dcc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000dd0 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8000dd0: b480 push {r7}
|
|
8000dd2: b087 sub sp, #28
|
|
8000dd4: af00 add r7, sp, #0
|
|
8000dd6: 6078 str r0, [r7, #4]
|
|
8000dd8: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00;
|
|
8000dda: 2300 movs r3, #0
|
|
8000ddc: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00;
|
|
8000dde: 2300 movs r3, #0
|
|
8000de0: 60fb str r3, [r7, #12]
|
|
uint32_t temp = 0x00;
|
|
8000de2: 2300 movs r3, #0
|
|
8000de4: 613b str r3, [r7, #16]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0)
|
|
8000de6: e160 b.n 80010aa <HAL_GPIO_Init+0x2da>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1U << position);
|
|
8000de8: 683b ldr r3, [r7, #0]
|
|
8000dea: 681a ldr r2, [r3, #0]
|
|
8000dec: 2101 movs r1, #1
|
|
8000dee: 697b ldr r3, [r7, #20]
|
|
8000df0: fa01 f303 lsl.w r3, r1, r3
|
|
8000df4: 4013 ands r3, r2
|
|
8000df6: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent)
|
|
8000df8: 68fb ldr r3, [r7, #12]
|
|
8000dfa: 2b00 cmp r3, #0
|
|
8000dfc: f000 8152 beq.w 80010a4 <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
|
8000e00: 683b ldr r3, [r7, #0]
|
|
8000e02: 685b ldr r3, [r3, #4]
|
|
8000e04: f003 0303 and.w r3, r3, #3
|
|
8000e08: 2b01 cmp r3, #1
|
|
8000e0a: d005 beq.n 8000e18 <HAL_GPIO_Init+0x48>
|
|
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8000e0c: 683b ldr r3, [r7, #0]
|
|
8000e0e: 685b ldr r3, [r3, #4]
|
|
8000e10: f003 0303 and.w r3, r3, #3
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
|
8000e14: 2b02 cmp r3, #2
|
|
8000e16: d130 bne.n 8000e7a <HAL_GPIO_Init+0xaa>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8000e18: 687b ldr r3, [r7, #4]
|
|
8000e1a: 689b ldr r3, [r3, #8]
|
|
8000e1c: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
|
8000e1e: 697b ldr r3, [r7, #20]
|
|
8000e20: 005b lsls r3, r3, #1
|
|
8000e22: 2203 movs r2, #3
|
|
8000e24: fa02 f303 lsl.w r3, r2, r3
|
|
8000e28: 43db mvns r3, r3
|
|
8000e2a: 693a ldr r2, [r7, #16]
|
|
8000e2c: 4013 ands r3, r2
|
|
8000e2e: 613b str r3, [r7, #16]
|
|
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
|
|
8000e30: 683b ldr r3, [r7, #0]
|
|
8000e32: 68da ldr r2, [r3, #12]
|
|
8000e34: 697b ldr r3, [r7, #20]
|
|
8000e36: 005b lsls r3, r3, #1
|
|
8000e38: fa02 f303 lsl.w r3, r2, r3
|
|
8000e3c: 693a ldr r2, [r7, #16]
|
|
8000e3e: 4313 orrs r3, r2
|
|
8000e40: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8000e42: 687b ldr r3, [r7, #4]
|
|
8000e44: 693a ldr r2, [r7, #16]
|
|
8000e46: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8000e48: 687b ldr r3, [r7, #4]
|
|
8000e4a: 685b ldr r3, [r3, #4]
|
|
8000e4c: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
|
|
8000e4e: 2201 movs r2, #1
|
|
8000e50: 697b ldr r3, [r7, #20]
|
|
8000e52: fa02 f303 lsl.w r3, r2, r3
|
|
8000e56: 43db mvns r3, r3
|
|
8000e58: 693a ldr r2, [r7, #16]
|
|
8000e5a: 4013 ands r3, r2
|
|
8000e5c: 613b str r3, [r7, #16]
|
|
SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8000e5e: 683b ldr r3, [r7, #0]
|
|
8000e60: 685b ldr r3, [r3, #4]
|
|
8000e62: 091b lsrs r3, r3, #4
|
|
8000e64: f003 0201 and.w r2, r3, #1
|
|
8000e68: 697b ldr r3, [r7, #20]
|
|
8000e6a: fa02 f303 lsl.w r3, r2, r3
|
|
8000e6e: 693a ldr r2, [r7, #16]
|
|
8000e70: 4313 orrs r3, r2
|
|
8000e72: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8000e74: 687b ldr r3, [r7, #4]
|
|
8000e76: 693a ldr r2, [r7, #16]
|
|
8000e78: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8000e7a: 683b ldr r3, [r7, #0]
|
|
8000e7c: 685b ldr r3, [r3, #4]
|
|
8000e7e: f003 0303 and.w r3, r3, #3
|
|
8000e82: 2b03 cmp r3, #3
|
|
8000e84: d017 beq.n 8000eb6 <HAL_GPIO_Init+0xe6>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8000e86: 687b ldr r3, [r7, #4]
|
|
8000e88: 68db ldr r3, [r3, #12]
|
|
8000e8a: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
|
|
8000e8c: 697b ldr r3, [r7, #20]
|
|
8000e8e: 005b lsls r3, r3, #1
|
|
8000e90: 2203 movs r2, #3
|
|
8000e92: fa02 f303 lsl.w r3, r2, r3
|
|
8000e96: 43db mvns r3, r3
|
|
8000e98: 693a ldr r2, [r7, #16]
|
|
8000e9a: 4013 ands r3, r2
|
|
8000e9c: 613b str r3, [r7, #16]
|
|
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
|
|
8000e9e: 683b ldr r3, [r7, #0]
|
|
8000ea0: 689a ldr r2, [r3, #8]
|
|
8000ea2: 697b ldr r3, [r7, #20]
|
|
8000ea4: 005b lsls r3, r3, #1
|
|
8000ea6: fa02 f303 lsl.w r3, r2, r3
|
|
8000eaa: 693a ldr r2, [r7, #16]
|
|
8000eac: 4313 orrs r3, r2
|
|
8000eae: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8000eb0: 687b ldr r3, [r7, #4]
|
|
8000eb2: 693a ldr r2, [r7, #16]
|
|
8000eb4: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8000eb6: 683b ldr r3, [r7, #0]
|
|
8000eb8: 685b ldr r3, [r3, #4]
|
|
8000eba: f003 0303 and.w r3, r3, #3
|
|
8000ebe: 2b02 cmp r3, #2
|
|
8000ec0: d123 bne.n 8000f0a <HAL_GPIO_Init+0x13a>
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
/* Identify AFRL or AFRH register based on IO position*/
|
|
temp = GPIOx->AFR[position >> 3];
|
|
8000ec2: 697b ldr r3, [r7, #20]
|
|
8000ec4: 08da lsrs r2, r3, #3
|
|
8000ec6: 687b ldr r3, [r7, #4]
|
|
8000ec8: 3208 adds r2, #8
|
|
8000eca: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8000ece: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
|
|
8000ed0: 697b ldr r3, [r7, #20]
|
|
8000ed2: f003 0307 and.w r3, r3, #7
|
|
8000ed6: 009b lsls r3, r3, #2
|
|
8000ed8: 220f movs r2, #15
|
|
8000eda: fa02 f303 lsl.w r3, r2, r3
|
|
8000ede: 43db mvns r3, r3
|
|
8000ee0: 693a ldr r2, [r7, #16]
|
|
8000ee2: 4013 ands r3, r2
|
|
8000ee4: 613b str r3, [r7, #16]
|
|
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
|
|
8000ee6: 683b ldr r3, [r7, #0]
|
|
8000ee8: 691a ldr r2, [r3, #16]
|
|
8000eea: 697b ldr r3, [r7, #20]
|
|
8000eec: f003 0307 and.w r3, r3, #7
|
|
8000ef0: 009b lsls r3, r3, #2
|
|
8000ef2: fa02 f303 lsl.w r3, r2, r3
|
|
8000ef6: 693a ldr r2, [r7, #16]
|
|
8000ef8: 4313 orrs r3, r2
|
|
8000efa: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3] = temp;
|
|
8000efc: 697b ldr r3, [r7, #20]
|
|
8000efe: 08da lsrs r2, r3, #3
|
|
8000f00: 687b ldr r3, [r7, #4]
|
|
8000f02: 3208 adds r2, #8
|
|
8000f04: 6939 ldr r1, [r7, #16]
|
|
8000f06: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8000f0a: 687b ldr r3, [r7, #4]
|
|
8000f0c: 681b ldr r3, [r3, #0]
|
|
8000f0e: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
|
|
8000f10: 697b ldr r3, [r7, #20]
|
|
8000f12: 005b lsls r3, r3, #1
|
|
8000f14: 2203 movs r2, #3
|
|
8000f16: fa02 f303 lsl.w r3, r2, r3
|
|
8000f1a: 43db mvns r3, r3
|
|
8000f1c: 693a ldr r2, [r7, #16]
|
|
8000f1e: 4013 ands r3, r2
|
|
8000f20: 613b str r3, [r7, #16]
|
|
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
|
|
8000f22: 683b ldr r3, [r7, #0]
|
|
8000f24: 685b ldr r3, [r3, #4]
|
|
8000f26: f003 0203 and.w r2, r3, #3
|
|
8000f2a: 697b ldr r3, [r7, #20]
|
|
8000f2c: 005b lsls r3, r3, #1
|
|
8000f2e: fa02 f303 lsl.w r3, r2, r3
|
|
8000f32: 693a ldr r2, [r7, #16]
|
|
8000f34: 4313 orrs r3, r2
|
|
8000f36: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
8000f38: 687b ldr r3, [r7, #4]
|
|
8000f3a: 693a ldr r2, [r7, #16]
|
|
8000f3c: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
8000f3e: 683b ldr r3, [r7, #0]
|
|
8000f40: 685b ldr r3, [r3, #4]
|
|
8000f42: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8000f46: 2b00 cmp r3, #0
|
|
8000f48: f000 80ac beq.w 80010a4 <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000f4c: 4b5e ldr r3, [pc, #376] @ (80010c8 <HAL_GPIO_Init+0x2f8>)
|
|
8000f4e: 6a1b ldr r3, [r3, #32]
|
|
8000f50: 4a5d ldr r2, [pc, #372] @ (80010c8 <HAL_GPIO_Init+0x2f8>)
|
|
8000f52: f043 0301 orr.w r3, r3, #1
|
|
8000f56: 6213 str r3, [r2, #32]
|
|
8000f58: 4b5b ldr r3, [pc, #364] @ (80010c8 <HAL_GPIO_Init+0x2f8>)
|
|
8000f5a: 6a1b ldr r3, [r3, #32]
|
|
8000f5c: f003 0301 and.w r3, r3, #1
|
|
8000f60: 60bb str r3, [r7, #8]
|
|
8000f62: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2];
|
|
8000f64: 4a59 ldr r2, [pc, #356] @ (80010cc <HAL_GPIO_Init+0x2fc>)
|
|
8000f66: 697b ldr r3, [r7, #20]
|
|
8000f68: 089b lsrs r3, r3, #2
|
|
8000f6a: 3302 adds r3, #2
|
|
8000f6c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000f70: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
|
|
8000f72: 697b ldr r3, [r7, #20]
|
|
8000f74: f003 0303 and.w r3, r3, #3
|
|
8000f78: 009b lsls r3, r3, #2
|
|
8000f7a: 220f movs r2, #15
|
|
8000f7c: fa02 f303 lsl.w r3, r2, r3
|
|
8000f80: 43db mvns r3, r3
|
|
8000f82: 693a ldr r2, [r7, #16]
|
|
8000f84: 4013 ands r3, r2
|
|
8000f86: 613b str r3, [r7, #16]
|
|
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
|
|
8000f88: 687b ldr r3, [r7, #4]
|
|
8000f8a: 4a51 ldr r2, [pc, #324] @ (80010d0 <HAL_GPIO_Init+0x300>)
|
|
8000f8c: 4293 cmp r3, r2
|
|
8000f8e: d025 beq.n 8000fdc <HAL_GPIO_Init+0x20c>
|
|
8000f90: 687b ldr r3, [r7, #4]
|
|
8000f92: 4a50 ldr r2, [pc, #320] @ (80010d4 <HAL_GPIO_Init+0x304>)
|
|
8000f94: 4293 cmp r3, r2
|
|
8000f96: d01f beq.n 8000fd8 <HAL_GPIO_Init+0x208>
|
|
8000f98: 687b ldr r3, [r7, #4]
|
|
8000f9a: 4a4f ldr r2, [pc, #316] @ (80010d8 <HAL_GPIO_Init+0x308>)
|
|
8000f9c: 4293 cmp r3, r2
|
|
8000f9e: d019 beq.n 8000fd4 <HAL_GPIO_Init+0x204>
|
|
8000fa0: 687b ldr r3, [r7, #4]
|
|
8000fa2: 4a4e ldr r2, [pc, #312] @ (80010dc <HAL_GPIO_Init+0x30c>)
|
|
8000fa4: 4293 cmp r3, r2
|
|
8000fa6: d013 beq.n 8000fd0 <HAL_GPIO_Init+0x200>
|
|
8000fa8: 687b ldr r3, [r7, #4]
|
|
8000faa: 4a4d ldr r2, [pc, #308] @ (80010e0 <HAL_GPIO_Init+0x310>)
|
|
8000fac: 4293 cmp r3, r2
|
|
8000fae: d00d beq.n 8000fcc <HAL_GPIO_Init+0x1fc>
|
|
8000fb0: 687b ldr r3, [r7, #4]
|
|
8000fb2: 4a4c ldr r2, [pc, #304] @ (80010e4 <HAL_GPIO_Init+0x314>)
|
|
8000fb4: 4293 cmp r3, r2
|
|
8000fb6: d007 beq.n 8000fc8 <HAL_GPIO_Init+0x1f8>
|
|
8000fb8: 687b ldr r3, [r7, #4]
|
|
8000fba: 4a4b ldr r2, [pc, #300] @ (80010e8 <HAL_GPIO_Init+0x318>)
|
|
8000fbc: 4293 cmp r3, r2
|
|
8000fbe: d101 bne.n 8000fc4 <HAL_GPIO_Init+0x1f4>
|
|
8000fc0: 2306 movs r3, #6
|
|
8000fc2: e00c b.n 8000fde <HAL_GPIO_Init+0x20e>
|
|
8000fc4: 2307 movs r3, #7
|
|
8000fc6: e00a b.n 8000fde <HAL_GPIO_Init+0x20e>
|
|
8000fc8: 2305 movs r3, #5
|
|
8000fca: e008 b.n 8000fde <HAL_GPIO_Init+0x20e>
|
|
8000fcc: 2304 movs r3, #4
|
|
8000fce: e006 b.n 8000fde <HAL_GPIO_Init+0x20e>
|
|
8000fd0: 2303 movs r3, #3
|
|
8000fd2: e004 b.n 8000fde <HAL_GPIO_Init+0x20e>
|
|
8000fd4: 2302 movs r3, #2
|
|
8000fd6: e002 b.n 8000fde <HAL_GPIO_Init+0x20e>
|
|
8000fd8: 2301 movs r3, #1
|
|
8000fda: e000 b.n 8000fde <HAL_GPIO_Init+0x20e>
|
|
8000fdc: 2300 movs r3, #0
|
|
8000fde: 697a ldr r2, [r7, #20]
|
|
8000fe0: f002 0203 and.w r2, r2, #3
|
|
8000fe4: 0092 lsls r2, r2, #2
|
|
8000fe6: 4093 lsls r3, r2
|
|
8000fe8: 693a ldr r2, [r7, #16]
|
|
8000fea: 4313 orrs r3, r2
|
|
8000fec: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2] = temp;
|
|
8000fee: 4937 ldr r1, [pc, #220] @ (80010cc <HAL_GPIO_Init+0x2fc>)
|
|
8000ff0: 697b ldr r3, [r7, #20]
|
|
8000ff2: 089b lsrs r3, r3, #2
|
|
8000ff4: 3302 adds r3, #2
|
|
8000ff6: 693a ldr r2, [r7, #16]
|
|
8000ff8: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8000ffc: 4b3b ldr r3, [pc, #236] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
8000ffe: 689b ldr r3, [r3, #8]
|
|
8001000: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
|
8001002: 68fb ldr r3, [r7, #12]
|
|
8001004: 43db mvns r3, r3
|
|
8001006: 693a ldr r2, [r7, #16]
|
|
8001008: 4013 ands r3, r2
|
|
800100a: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
800100c: 683b ldr r3, [r7, #0]
|
|
800100e: 685b ldr r3, [r3, #4]
|
|
8001010: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001014: 2b00 cmp r3, #0
|
|
8001016: d003 beq.n 8001020 <HAL_GPIO_Init+0x250>
|
|
{
|
|
SET_BIT(temp, iocurrent);
|
|
8001018: 693a ldr r2, [r7, #16]
|
|
800101a: 68fb ldr r3, [r7, #12]
|
|
800101c: 4313 orrs r3, r2
|
|
800101e: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8001020: 4a32 ldr r2, [pc, #200] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
8001022: 693b ldr r3, [r7, #16]
|
|
8001024: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8001026: 4b31 ldr r3, [pc, #196] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
8001028: 68db ldr r3, [r3, #12]
|
|
800102a: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
|
800102c: 68fb ldr r3, [r7, #12]
|
|
800102e: 43db mvns r3, r3
|
|
8001030: 693a ldr r2, [r7, #16]
|
|
8001032: 4013 ands r3, r2
|
|
8001034: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8001036: 683b ldr r3, [r7, #0]
|
|
8001038: 685b ldr r3, [r3, #4]
|
|
800103a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
800103e: 2b00 cmp r3, #0
|
|
8001040: d003 beq.n 800104a <HAL_GPIO_Init+0x27a>
|
|
{
|
|
SET_BIT(temp, iocurrent);
|
|
8001042: 693a ldr r2, [r7, #16]
|
|
8001044: 68fb ldr r3, [r7, #12]
|
|
8001046: 4313 orrs r3, r2
|
|
8001048: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
800104a: 4a28 ldr r2, [pc, #160] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
800104c: 693b ldr r3, [r7, #16]
|
|
800104e: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8001050: 4b26 ldr r3, [pc, #152] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
8001052: 685b ldr r3, [r3, #4]
|
|
8001054: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
|
8001056: 68fb ldr r3, [r7, #12]
|
|
8001058: 43db mvns r3, r3
|
|
800105a: 693a ldr r2, [r7, #16]
|
|
800105c: 4013 ands r3, r2
|
|
800105e: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8001060: 683b ldr r3, [r7, #0]
|
|
8001062: 685b ldr r3, [r3, #4]
|
|
8001064: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001068: 2b00 cmp r3, #0
|
|
800106a: d003 beq.n 8001074 <HAL_GPIO_Init+0x2a4>
|
|
{
|
|
SET_BIT(temp, iocurrent);
|
|
800106c: 693a ldr r2, [r7, #16]
|
|
800106e: 68fb ldr r3, [r7, #12]
|
|
8001070: 4313 orrs r3, r2
|
|
8001072: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8001074: 4a1d ldr r2, [pc, #116] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
8001076: 693b ldr r3, [r7, #16]
|
|
8001078: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
800107a: 4b1c ldr r3, [pc, #112] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
800107c: 681b ldr r3, [r3, #0]
|
|
800107e: 613b str r3, [r7, #16]
|
|
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
|
8001080: 68fb ldr r3, [r7, #12]
|
|
8001082: 43db mvns r3, r3
|
|
8001084: 693a ldr r2, [r7, #16]
|
|
8001086: 4013 ands r3, r2
|
|
8001088: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
800108a: 683b ldr r3, [r7, #0]
|
|
800108c: 685b ldr r3, [r3, #4]
|
|
800108e: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001092: 2b00 cmp r3, #0
|
|
8001094: d003 beq.n 800109e <HAL_GPIO_Init+0x2ce>
|
|
{
|
|
SET_BIT(temp, iocurrent);
|
|
8001096: 693a ldr r2, [r7, #16]
|
|
8001098: 68fb ldr r3, [r7, #12]
|
|
800109a: 4313 orrs r3, r2
|
|
800109c: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR = temp;
|
|
800109e: 4a13 ldr r2, [pc, #76] @ (80010ec <HAL_GPIO_Init+0x31c>)
|
|
80010a0: 693b ldr r3, [r7, #16]
|
|
80010a2: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
80010a4: 697b ldr r3, [r7, #20]
|
|
80010a6: 3301 adds r3, #1
|
|
80010a8: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0)
|
|
80010aa: 683b ldr r3, [r7, #0]
|
|
80010ac: 681a ldr r2, [r3, #0]
|
|
80010ae: 697b ldr r3, [r7, #20]
|
|
80010b0: fa22 f303 lsr.w r3, r2, r3
|
|
80010b4: 2b00 cmp r3, #0
|
|
80010b6: f47f ae97 bne.w 8000de8 <HAL_GPIO_Init+0x18>
|
|
}
|
|
}
|
|
80010ba: bf00 nop
|
|
80010bc: bf00 nop
|
|
80010be: 371c adds r7, #28
|
|
80010c0: 46bd mov sp, r7
|
|
80010c2: bc80 pop {r7}
|
|
80010c4: 4770 bx lr
|
|
80010c6: bf00 nop
|
|
80010c8: 40023800 .word 0x40023800
|
|
80010cc: 40010000 .word 0x40010000
|
|
80010d0: 40020000 .word 0x40020000
|
|
80010d4: 40020400 .word 0x40020400
|
|
80010d8: 40020800 .word 0x40020800
|
|
80010dc: 40020c00 .word 0x40020c00
|
|
80010e0: 40021000 .word 0x40021000
|
|
80010e4: 40021400 .word 0x40021400
|
|
80010e8: 40021800 .word 0x40021800
|
|
80010ec: 40010400 .word 0x40010400
|
|
|
|
080010f0 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
80010f0: b480 push {r7}
|
|
80010f2: b083 sub sp, #12
|
|
80010f4: af00 add r7, sp, #0
|
|
80010f6: 6078 str r0, [r7, #4]
|
|
80010f8: 460b mov r3, r1
|
|
80010fa: 807b strh r3, [r7, #2]
|
|
80010fc: 4613 mov r3, r2
|
|
80010fe: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8001100: 787b ldrb r3, [r7, #1]
|
|
8001102: 2b00 cmp r3, #0
|
|
8001104: d003 beq.n 800110e <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8001106: 887a ldrh r2, [r7, #2]
|
|
8001108: 687b ldr r3, [r7, #4]
|
|
800110a: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
|
|
}
|
|
}
|
|
800110c: e003 b.n 8001116 <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
|
|
800110e: 887b ldrh r3, [r7, #2]
|
|
8001110: 041a lsls r2, r3, #16
|
|
8001112: 687b ldr r3, [r7, #4]
|
|
8001114: 619a str r2, [r3, #24]
|
|
}
|
|
8001116: bf00 nop
|
|
8001118: 370c adds r7, #12
|
|
800111a: 46bd mov sp, r7
|
|
800111c: bc80 pop {r7}
|
|
800111e: 4770 bx lr
|
|
|
|
08001120 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8001120: b580 push {r7, lr}
|
|
8001122: b088 sub sp, #32
|
|
8001124: af00 add r7, sp, #0
|
|
8001126: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status;
|
|
uint32_t sysclk_source, pll_config;
|
|
|
|
/* Check the parameters */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8001128: 687b ldr r3, [r7, #4]
|
|
800112a: 2b00 cmp r3, #0
|
|
800112c: d101 bne.n 8001132 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800112e: 2301 movs r3, #1
|
|
8001130: e31d b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
}
|
|
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8001132: 4b94 ldr r3, [pc, #592] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001134: 689b ldr r3, [r3, #8]
|
|
8001136: f003 030c and.w r3, r3, #12
|
|
800113a: 61bb str r3, [r7, #24]
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
800113c: 4b91 ldr r3, [pc, #580] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800113e: 689b ldr r3, [r3, #8]
|
|
8001140: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001144: 617b str r3, [r7, #20]
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8001146: 687b ldr r3, [r7, #4]
|
|
8001148: 681b ldr r3, [r3, #0]
|
|
800114a: f003 0301 and.w r3, r3, #1
|
|
800114e: 2b00 cmp r3, #0
|
|
8001150: d07b beq.n 800124a <HAL_RCC_OscConfig+0x12a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8001152: 69bb ldr r3, [r7, #24]
|
|
8001154: 2b08 cmp r3, #8
|
|
8001156: d006 beq.n 8001166 <HAL_RCC_OscConfig+0x46>
|
|
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
8001158: 69bb ldr r3, [r7, #24]
|
|
800115a: 2b0c cmp r3, #12
|
|
800115c: d10f bne.n 800117e <HAL_RCC_OscConfig+0x5e>
|
|
800115e: 697b ldr r3, [r7, #20]
|
|
8001160: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8001164: d10b bne.n 800117e <HAL_RCC_OscConfig+0x5e>
|
|
{
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8001166: 4b87 ldr r3, [pc, #540] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001168: 681b ldr r3, [r3, #0]
|
|
800116a: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800116e: 2b00 cmp r3, #0
|
|
8001170: d06a beq.n 8001248 <HAL_RCC_OscConfig+0x128>
|
|
8001172: 687b ldr r3, [r7, #4]
|
|
8001174: 685b ldr r3, [r3, #4]
|
|
8001176: 2b00 cmp r3, #0
|
|
8001178: d166 bne.n 8001248 <HAL_RCC_OscConfig+0x128>
|
|
{
|
|
return HAL_ERROR;
|
|
800117a: 2301 movs r3, #1
|
|
800117c: e2f7 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
800117e: 687b ldr r3, [r7, #4]
|
|
8001180: 685b ldr r3, [r3, #4]
|
|
8001182: 2b01 cmp r3, #1
|
|
8001184: d106 bne.n 8001194 <HAL_RCC_OscConfig+0x74>
|
|
8001186: 4b7f ldr r3, [pc, #508] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001188: 681b ldr r3, [r3, #0]
|
|
800118a: 4a7e ldr r2, [pc, #504] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800118c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8001190: 6013 str r3, [r2, #0]
|
|
8001192: e02d b.n 80011f0 <HAL_RCC_OscConfig+0xd0>
|
|
8001194: 687b ldr r3, [r7, #4]
|
|
8001196: 685b ldr r3, [r3, #4]
|
|
8001198: 2b00 cmp r3, #0
|
|
800119a: d10c bne.n 80011b6 <HAL_RCC_OscConfig+0x96>
|
|
800119c: 4b79 ldr r3, [pc, #484] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800119e: 681b ldr r3, [r3, #0]
|
|
80011a0: 4a78 ldr r2, [pc, #480] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011a2: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80011a6: 6013 str r3, [r2, #0]
|
|
80011a8: 4b76 ldr r3, [pc, #472] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011aa: 681b ldr r3, [r3, #0]
|
|
80011ac: 4a75 ldr r2, [pc, #468] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011ae: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80011b2: 6013 str r3, [r2, #0]
|
|
80011b4: e01c b.n 80011f0 <HAL_RCC_OscConfig+0xd0>
|
|
80011b6: 687b ldr r3, [r7, #4]
|
|
80011b8: 685b ldr r3, [r3, #4]
|
|
80011ba: 2b05 cmp r3, #5
|
|
80011bc: d10c bne.n 80011d8 <HAL_RCC_OscConfig+0xb8>
|
|
80011be: 4b71 ldr r3, [pc, #452] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011c0: 681b ldr r3, [r3, #0]
|
|
80011c2: 4a70 ldr r2, [pc, #448] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011c4: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
80011c8: 6013 str r3, [r2, #0]
|
|
80011ca: 4b6e ldr r3, [pc, #440] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011cc: 681b ldr r3, [r3, #0]
|
|
80011ce: 4a6d ldr r2, [pc, #436] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011d0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80011d4: 6013 str r3, [r2, #0]
|
|
80011d6: e00b b.n 80011f0 <HAL_RCC_OscConfig+0xd0>
|
|
80011d8: 4b6a ldr r3, [pc, #424] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011da: 681b ldr r3, [r3, #0]
|
|
80011dc: 4a69 ldr r2, [pc, #420] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011de: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80011e2: 6013 str r3, [r2, #0]
|
|
80011e4: 4b67 ldr r3, [pc, #412] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011e6: 681b ldr r3, [r3, #0]
|
|
80011e8: 4a66 ldr r2, [pc, #408] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80011ea: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80011ee: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
80011f0: 687b ldr r3, [r7, #4]
|
|
80011f2: 685b ldr r3, [r3, #4]
|
|
80011f4: 2b00 cmp r3, #0
|
|
80011f6: d013 beq.n 8001220 <HAL_RCC_OscConfig+0x100>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80011f8: f7ff fcda bl 8000bb0 <HAL_GetTick>
|
|
80011fc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
|
80011fe: e008 b.n 8001212 <HAL_RCC_OscConfig+0xf2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
8001200: f7ff fcd6 bl 8000bb0 <HAL_GetTick>
|
|
8001204: 4602 mov r2, r0
|
|
8001206: 693b ldr r3, [r7, #16]
|
|
8001208: 1ad3 subs r3, r2, r3
|
|
800120a: 2b64 cmp r3, #100 @ 0x64
|
|
800120c: d901 bls.n 8001212 <HAL_RCC_OscConfig+0xf2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800120e: 2303 movs r3, #3
|
|
8001210: e2ad b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
|
8001212: 4b5c ldr r3, [pc, #368] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001214: 681b ldr r3, [r3, #0]
|
|
8001216: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800121a: 2b00 cmp r3, #0
|
|
800121c: d0f0 beq.n 8001200 <HAL_RCC_OscConfig+0xe0>
|
|
800121e: e014 b.n 800124a <HAL_RCC_OscConfig+0x12a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001220: f7ff fcc6 bl 8000bb0 <HAL_GetTick>
|
|
8001224: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
|
|
8001226: e008 b.n 800123a <HAL_RCC_OscConfig+0x11a>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
8001228: f7ff fcc2 bl 8000bb0 <HAL_GetTick>
|
|
800122c: 4602 mov r2, r0
|
|
800122e: 693b ldr r3, [r7, #16]
|
|
8001230: 1ad3 subs r3, r2, r3
|
|
8001232: 2b64 cmp r3, #100 @ 0x64
|
|
8001234: d901 bls.n 800123a <HAL_RCC_OscConfig+0x11a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001236: 2303 movs r3, #3
|
|
8001238: e299 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
|
|
800123a: 4b52 ldr r3, [pc, #328] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800123c: 681b ldr r3, [r3, #0]
|
|
800123e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001242: 2b00 cmp r3, #0
|
|
8001244: d1f0 bne.n 8001228 <HAL_RCC_OscConfig+0x108>
|
|
8001246: e000 b.n 800124a <HAL_RCC_OscConfig+0x12a>
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8001248: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
800124a: 687b ldr r3, [r7, #4]
|
|
800124c: 681b ldr r3, [r3, #0]
|
|
800124e: f003 0302 and.w r3, r3, #2
|
|
8001252: 2b00 cmp r3, #0
|
|
8001254: d05a beq.n 800130c <HAL_RCC_OscConfig+0x1ec>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8001256: 69bb ldr r3, [r7, #24]
|
|
8001258: 2b04 cmp r3, #4
|
|
800125a: d005 beq.n 8001268 <HAL_RCC_OscConfig+0x148>
|
|
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
800125c: 69bb ldr r3, [r7, #24]
|
|
800125e: 2b0c cmp r3, #12
|
|
8001260: d119 bne.n 8001296 <HAL_RCC_OscConfig+0x176>
|
|
8001262: 697b ldr r3, [r7, #20]
|
|
8001264: 2b00 cmp r3, #0
|
|
8001266: d116 bne.n 8001296 <HAL_RCC_OscConfig+0x176>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8001268: 4b46 ldr r3, [pc, #280] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800126a: 681b ldr r3, [r3, #0]
|
|
800126c: f003 0302 and.w r3, r3, #2
|
|
8001270: 2b00 cmp r3, #0
|
|
8001272: d005 beq.n 8001280 <HAL_RCC_OscConfig+0x160>
|
|
8001274: 687b ldr r3, [r7, #4]
|
|
8001276: 68db ldr r3, [r3, #12]
|
|
8001278: 2b01 cmp r3, #1
|
|
800127a: d001 beq.n 8001280 <HAL_RCC_OscConfig+0x160>
|
|
{
|
|
return HAL_ERROR;
|
|
800127c: 2301 movs r3, #1
|
|
800127e: e276 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8001280: 4b40 ldr r3, [pc, #256] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001282: 685b ldr r3, [r3, #4]
|
|
8001284: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
8001288: 687b ldr r3, [r7, #4]
|
|
800128a: 691b ldr r3, [r3, #16]
|
|
800128c: 021b lsls r3, r3, #8
|
|
800128e: 493d ldr r1, [pc, #244] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001290: 4313 orrs r3, r2
|
|
8001292: 604b str r3, [r1, #4]
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8001294: e03a b.n 800130c <HAL_RCC_OscConfig+0x1ec>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8001296: 687b ldr r3, [r7, #4]
|
|
8001298: 68db ldr r3, [r3, #12]
|
|
800129a: 2b00 cmp r3, #0
|
|
800129c: d020 beq.n 80012e0 <HAL_RCC_OscConfig+0x1c0>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800129e: 4b3a ldr r3, [pc, #232] @ (8001388 <HAL_RCC_OscConfig+0x268>)
|
|
80012a0: 2201 movs r2, #1
|
|
80012a2: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80012a4: f7ff fc84 bl 8000bb0 <HAL_GetTick>
|
|
80012a8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
|
80012aa: e008 b.n 80012be <HAL_RCC_OscConfig+0x19e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
80012ac: f7ff fc80 bl 8000bb0 <HAL_GetTick>
|
|
80012b0: 4602 mov r2, r0
|
|
80012b2: 693b ldr r3, [r7, #16]
|
|
80012b4: 1ad3 subs r3, r2, r3
|
|
80012b6: 2b02 cmp r3, #2
|
|
80012b8: d901 bls.n 80012be <HAL_RCC_OscConfig+0x19e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80012ba: 2303 movs r3, #3
|
|
80012bc: e257 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
|
80012be: 4b31 ldr r3, [pc, #196] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80012c0: 681b ldr r3, [r3, #0]
|
|
80012c2: f003 0302 and.w r3, r3, #2
|
|
80012c6: 2b00 cmp r3, #0
|
|
80012c8: d0f0 beq.n 80012ac <HAL_RCC_OscConfig+0x18c>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
80012ca: 4b2e ldr r3, [pc, #184] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80012cc: 685b ldr r3, [r3, #4]
|
|
80012ce: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
80012d2: 687b ldr r3, [r7, #4]
|
|
80012d4: 691b ldr r3, [r3, #16]
|
|
80012d6: 021b lsls r3, r3, #8
|
|
80012d8: 492a ldr r1, [pc, #168] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
80012da: 4313 orrs r3, r2
|
|
80012dc: 604b str r3, [r1, #4]
|
|
80012de: e015 b.n 800130c <HAL_RCC_OscConfig+0x1ec>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
80012e0: 4b29 ldr r3, [pc, #164] @ (8001388 <HAL_RCC_OscConfig+0x268>)
|
|
80012e2: 2200 movs r2, #0
|
|
80012e4: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80012e6: f7ff fc63 bl 8000bb0 <HAL_GetTick>
|
|
80012ea: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
|
|
80012ec: e008 b.n 8001300 <HAL_RCC_OscConfig+0x1e0>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
80012ee: f7ff fc5f bl 8000bb0 <HAL_GetTick>
|
|
80012f2: 4602 mov r2, r0
|
|
80012f4: 693b ldr r3, [r7, #16]
|
|
80012f6: 1ad3 subs r3, r2, r3
|
|
80012f8: 2b02 cmp r3, #2
|
|
80012fa: d901 bls.n 8001300 <HAL_RCC_OscConfig+0x1e0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80012fc: 2303 movs r3, #3
|
|
80012fe: e236 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
|
|
8001300: 4b20 ldr r3, [pc, #128] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001302: 681b ldr r3, [r3, #0]
|
|
8001304: f003 0302 and.w r3, r3, #2
|
|
8001308: 2b00 cmp r3, #0
|
|
800130a: d1f0 bne.n 80012ee <HAL_RCC_OscConfig+0x1ce>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
800130c: 687b ldr r3, [r7, #4]
|
|
800130e: 681b ldr r3, [r3, #0]
|
|
8001310: f003 0310 and.w r3, r3, #16
|
|
8001314: 2b00 cmp r3, #0
|
|
8001316: f000 80b8 beq.w 800148a <HAL_RCC_OscConfig+0x36a>
|
|
{
|
|
/* When the MSI is used as system clock it will not be disabled */
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
800131a: 69bb ldr r3, [r7, #24]
|
|
800131c: 2b00 cmp r3, #0
|
|
800131e: d170 bne.n 8001402 <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8001320: 4b18 ldr r3, [pc, #96] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001322: 681b ldr r3, [r3, #0]
|
|
8001324: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001328: 2b00 cmp r3, #0
|
|
800132a: d005 beq.n 8001338 <HAL_RCC_OscConfig+0x218>
|
|
800132c: 687b ldr r3, [r7, #4]
|
|
800132e: 699b ldr r3, [r3, #24]
|
|
8001330: 2b00 cmp r3, #0
|
|
8001332: d101 bne.n 8001338 <HAL_RCC_OscConfig+0x218>
|
|
{
|
|
return HAL_ERROR;
|
|
8001334: 2301 movs r3, #1
|
|
8001336: e21a b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
8001338: 687b ldr r3, [r7, #4]
|
|
800133a: 6a1a ldr r2, [r3, #32]
|
|
800133c: 4b11 ldr r3, [pc, #68] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800133e: 685b ldr r3, [r3, #4]
|
|
8001340: f403 4360 and.w r3, r3, #57344 @ 0xe000
|
|
8001344: 429a cmp r2, r3
|
|
8001346: d921 bls.n 800138c <HAL_RCC_OscConfig+0x26c>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8001348: 687b ldr r3, [r7, #4]
|
|
800134a: 6a1b ldr r3, [r3, #32]
|
|
800134c: 4618 mov r0, r3
|
|
800134e: f000 fc09 bl 8001b64 <RCC_SetFlashLatencyFromMSIRange>
|
|
8001352: 4603 mov r3, r0
|
|
8001354: 2b00 cmp r3, #0
|
|
8001356: d001 beq.n 800135c <HAL_RCC_OscConfig+0x23c>
|
|
{
|
|
return HAL_ERROR;
|
|
8001358: 2301 movs r3, #1
|
|
800135a: e208 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
800135c: 4b09 ldr r3, [pc, #36] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800135e: 685b ldr r3, [r3, #4]
|
|
8001360: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
8001364: 687b ldr r3, [r7, #4]
|
|
8001366: 6a1b ldr r3, [r3, #32]
|
|
8001368: 4906 ldr r1, [pc, #24] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800136a: 4313 orrs r3, r2
|
|
800136c: 604b str r3, [r1, #4]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
800136e: 4b05 ldr r3, [pc, #20] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
8001370: 685b ldr r3, [r3, #4]
|
|
8001372: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
|
|
8001376: 687b ldr r3, [r7, #4]
|
|
8001378: 69db ldr r3, [r3, #28]
|
|
800137a: 061b lsls r3, r3, #24
|
|
800137c: 4901 ldr r1, [pc, #4] @ (8001384 <HAL_RCC_OscConfig+0x264>)
|
|
800137e: 4313 orrs r3, r2
|
|
8001380: 604b str r3, [r1, #4]
|
|
8001382: e020 b.n 80013c6 <HAL_RCC_OscConfig+0x2a6>
|
|
8001384: 40023800 .word 0x40023800
|
|
8001388: 42470000 .word 0x42470000
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
800138c: 4b99 ldr r3, [pc, #612] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800138e: 685b ldr r3, [r3, #4]
|
|
8001390: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
8001394: 687b ldr r3, [r7, #4]
|
|
8001396: 6a1b ldr r3, [r3, #32]
|
|
8001398: 4996 ldr r1, [pc, #600] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800139a: 4313 orrs r3, r2
|
|
800139c: 604b str r3, [r1, #4]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
800139e: 4b95 ldr r3, [pc, #596] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80013a0: 685b ldr r3, [r3, #4]
|
|
80013a2: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
|
|
80013a6: 687b ldr r3, [r7, #4]
|
|
80013a8: 69db ldr r3, [r3, #28]
|
|
80013aa: 061b lsls r3, r3, #24
|
|
80013ac: 4991 ldr r1, [pc, #580] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80013ae: 4313 orrs r3, r2
|
|
80013b0: 604b str r3, [r1, #4]
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
80013b2: 687b ldr r3, [r7, #4]
|
|
80013b4: 6a1b ldr r3, [r3, #32]
|
|
80013b6: 4618 mov r0, r3
|
|
80013b8: f000 fbd4 bl 8001b64 <RCC_SetFlashLatencyFromMSIRange>
|
|
80013bc: 4603 mov r3, r0
|
|
80013be: 2b00 cmp r3, #0
|
|
80013c0: d001 beq.n 80013c6 <HAL_RCC_OscConfig+0x2a6>
|
|
{
|
|
return HAL_ERROR;
|
|
80013c2: 2301 movs r3, #1
|
|
80013c4: e1d3 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
|
|
80013c6: 687b ldr r3, [r7, #4]
|
|
80013c8: 6a1b ldr r3, [r3, #32]
|
|
80013ca: 0b5b lsrs r3, r3, #13
|
|
80013cc: 3301 adds r3, #1
|
|
80013ce: f44f 4200 mov.w r2, #32768 @ 0x8000
|
|
80013d2: fa02 f303 lsl.w r3, r2, r3
|
|
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
|
80013d6: 4a87 ldr r2, [pc, #540] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80013d8: 6892 ldr r2, [r2, #8]
|
|
80013da: 0912 lsrs r2, r2, #4
|
|
80013dc: f002 020f and.w r2, r2, #15
|
|
80013e0: 4985 ldr r1, [pc, #532] @ (80015f8 <HAL_RCC_OscConfig+0x4d8>)
|
|
80013e2: 5c8a ldrb r2, [r1, r2]
|
|
80013e4: 40d3 lsrs r3, r2
|
|
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
|
|
80013e6: 4a85 ldr r2, [pc, #532] @ (80015fc <HAL_RCC_OscConfig+0x4dc>)
|
|
80013e8: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
80013ea: 4b85 ldr r3, [pc, #532] @ (8001600 <HAL_RCC_OscConfig+0x4e0>)
|
|
80013ec: 681b ldr r3, [r3, #0]
|
|
80013ee: 4618 mov r0, r3
|
|
80013f0: f7ff fb92 bl 8000b18 <HAL_InitTick>
|
|
80013f4: 4603 mov r3, r0
|
|
80013f6: 73fb strb r3, [r7, #15]
|
|
if(status != HAL_OK)
|
|
80013f8: 7bfb ldrb r3, [r7, #15]
|
|
80013fa: 2b00 cmp r3, #0
|
|
80013fc: d045 beq.n 800148a <HAL_RCC_OscConfig+0x36a>
|
|
{
|
|
return status;
|
|
80013fe: 7bfb ldrb r3, [r7, #15]
|
|
8001400: e1b5 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
{
|
|
/* Check MSI State */
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
|
|
/* Check the MSI State */
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
8001402: 687b ldr r3, [r7, #4]
|
|
8001404: 699b ldr r3, [r3, #24]
|
|
8001406: 2b00 cmp r3, #0
|
|
8001408: d029 beq.n 800145e <HAL_RCC_OscConfig+0x33e>
|
|
{
|
|
/* Enable the Multi Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
800140a: 4b7e ldr r3, [pc, #504] @ (8001604 <HAL_RCC_OscConfig+0x4e4>)
|
|
800140c: 2201 movs r2, #1
|
|
800140e: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001410: f7ff fbce bl 8000bb0 <HAL_GetTick>
|
|
8001414: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
|
8001416: e008 b.n 800142a <HAL_RCC_OscConfig+0x30a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8001418: f7ff fbca bl 8000bb0 <HAL_GetTick>
|
|
800141c: 4602 mov r2, r0
|
|
800141e: 693b ldr r3, [r7, #16]
|
|
8001420: 1ad3 subs r3, r2, r3
|
|
8001422: 2b02 cmp r3, #2
|
|
8001424: d901 bls.n 800142a <HAL_RCC_OscConfig+0x30a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001426: 2303 movs r3, #3
|
|
8001428: e1a1 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
|
800142a: 4b72 ldr r3, [pc, #456] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800142c: 681b ldr r3, [r3, #0]
|
|
800142e: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001432: 2b00 cmp r3, #0
|
|
8001434: d0f0 beq.n 8001418 <HAL_RCC_OscConfig+0x2f8>
|
|
/* Check MSICalibrationValue and MSIClockRange input parameters */
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8001436: 4b6f ldr r3, [pc, #444] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001438: 685b ldr r3, [r3, #4]
|
|
800143a: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
800143e: 687b ldr r3, [r7, #4]
|
|
8001440: 6a1b ldr r3, [r3, #32]
|
|
8001442: 496c ldr r1, [pc, #432] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001444: 4313 orrs r3, r2
|
|
8001446: 604b str r3, [r1, #4]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8001448: 4b6a ldr r3, [pc, #424] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800144a: 685b ldr r3, [r3, #4]
|
|
800144c: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
|
|
8001450: 687b ldr r3, [r7, #4]
|
|
8001452: 69db ldr r3, [r3, #28]
|
|
8001454: 061b lsls r3, r3, #24
|
|
8001456: 4967 ldr r1, [pc, #412] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001458: 4313 orrs r3, r2
|
|
800145a: 604b str r3, [r1, #4]
|
|
800145c: e015 b.n 800148a <HAL_RCC_OscConfig+0x36a>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Multi Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
800145e: 4b69 ldr r3, [pc, #420] @ (8001604 <HAL_RCC_OscConfig+0x4e4>)
|
|
8001460: 2200 movs r2, #0
|
|
8001462: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001464: f7ff fba4 bl 8000bb0 <HAL_GetTick>
|
|
8001468: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
|
|
800146a: e008 b.n 800147e <HAL_RCC_OscConfig+0x35e>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
800146c: f7ff fba0 bl 8000bb0 <HAL_GetTick>
|
|
8001470: 4602 mov r2, r0
|
|
8001472: 693b ldr r3, [r7, #16]
|
|
8001474: 1ad3 subs r3, r2, r3
|
|
8001476: 2b02 cmp r3, #2
|
|
8001478: d901 bls.n 800147e <HAL_RCC_OscConfig+0x35e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800147a: 2303 movs r3, #3
|
|
800147c: e177 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
|
|
800147e: 4b5d ldr r3, [pc, #372] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001480: 681b ldr r3, [r3, #0]
|
|
8001482: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001486: 2b00 cmp r3, #0
|
|
8001488: d1f0 bne.n 800146c <HAL_RCC_OscConfig+0x34c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
800148a: 687b ldr r3, [r7, #4]
|
|
800148c: 681b ldr r3, [r3, #0]
|
|
800148e: f003 0308 and.w r3, r3, #8
|
|
8001492: 2b00 cmp r3, #0
|
|
8001494: d030 beq.n 80014f8 <HAL_RCC_OscConfig+0x3d8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8001496: 687b ldr r3, [r7, #4]
|
|
8001498: 695b ldr r3, [r3, #20]
|
|
800149a: 2b00 cmp r3, #0
|
|
800149c: d016 beq.n 80014cc <HAL_RCC_OscConfig+0x3ac>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
800149e: 4b5a ldr r3, [pc, #360] @ (8001608 <HAL_RCC_OscConfig+0x4e8>)
|
|
80014a0: 2201 movs r2, #1
|
|
80014a2: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80014a4: f7ff fb84 bl 8000bb0 <HAL_GetTick>
|
|
80014a8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
|
|
80014aa: e008 b.n 80014be <HAL_RCC_OscConfig+0x39e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
80014ac: f7ff fb80 bl 8000bb0 <HAL_GetTick>
|
|
80014b0: 4602 mov r2, r0
|
|
80014b2: 693b ldr r3, [r7, #16]
|
|
80014b4: 1ad3 subs r3, r2, r3
|
|
80014b6: 2b02 cmp r3, #2
|
|
80014b8: d901 bls.n 80014be <HAL_RCC_OscConfig+0x39e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80014ba: 2303 movs r3, #3
|
|
80014bc: e157 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
|
|
80014be: 4b4d ldr r3, [pc, #308] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80014c0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80014c2: f003 0302 and.w r3, r3, #2
|
|
80014c6: 2b00 cmp r3, #0
|
|
80014c8: d0f0 beq.n 80014ac <HAL_RCC_OscConfig+0x38c>
|
|
80014ca: e015 b.n 80014f8 <HAL_RCC_OscConfig+0x3d8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80014cc: 4b4e ldr r3, [pc, #312] @ (8001608 <HAL_RCC_OscConfig+0x4e8>)
|
|
80014ce: 2200 movs r2, #0
|
|
80014d0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80014d2: f7ff fb6d bl 8000bb0 <HAL_GetTick>
|
|
80014d6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
|
|
80014d8: e008 b.n 80014ec <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
80014da: f7ff fb69 bl 8000bb0 <HAL_GetTick>
|
|
80014de: 4602 mov r2, r0
|
|
80014e0: 693b ldr r3, [r7, #16]
|
|
80014e2: 1ad3 subs r3, r2, r3
|
|
80014e4: 2b02 cmp r3, #2
|
|
80014e6: d901 bls.n 80014ec <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80014e8: 2303 movs r3, #3
|
|
80014ea: e140 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
|
|
80014ec: 4b41 ldr r3, [pc, #260] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80014ee: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80014f0: f003 0302 and.w r3, r3, #2
|
|
80014f4: 2b00 cmp r3, #0
|
|
80014f6: d1f0 bne.n 80014da <HAL_RCC_OscConfig+0x3ba>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
80014f8: 687b ldr r3, [r7, #4]
|
|
80014fa: 681b ldr r3, [r3, #0]
|
|
80014fc: f003 0304 and.w r3, r3, #4
|
|
8001500: 2b00 cmp r3, #0
|
|
8001502: f000 80b5 beq.w 8001670 <HAL_RCC_OscConfig+0x550>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8001506: 2300 movs r3, #0
|
|
8001508: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
800150a: 4b3a ldr r3, [pc, #232] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800150c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800150e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001512: 2b00 cmp r3, #0
|
|
8001514: d10d bne.n 8001532 <HAL_RCC_OscConfig+0x412>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8001516: 4b37 ldr r3, [pc, #220] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001518: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800151a: 4a36 ldr r2, [pc, #216] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800151c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001520: 6253 str r3, [r2, #36] @ 0x24
|
|
8001522: 4b34 ldr r3, [pc, #208] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001524: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001526: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800152a: 60bb str r3, [r7, #8]
|
|
800152c: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
800152e: 2301 movs r3, #1
|
|
8001530: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8001532: 4b36 ldr r3, [pc, #216] @ (800160c <HAL_RCC_OscConfig+0x4ec>)
|
|
8001534: 681b ldr r3, [r3, #0]
|
|
8001536: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800153a: 2b00 cmp r3, #0
|
|
800153c: d118 bne.n 8001570 <HAL_RCC_OscConfig+0x450>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
800153e: 4b33 ldr r3, [pc, #204] @ (800160c <HAL_RCC_OscConfig+0x4ec>)
|
|
8001540: 681b ldr r3, [r3, #0]
|
|
8001542: 4a32 ldr r2, [pc, #200] @ (800160c <HAL_RCC_OscConfig+0x4ec>)
|
|
8001544: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001548: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800154a: f7ff fb31 bl 8000bb0 <HAL_GetTick>
|
|
800154e: 6138 str r0, [r7, #16]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8001550: e008 b.n 8001564 <HAL_RCC_OscConfig+0x444>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8001552: f7ff fb2d bl 8000bb0 <HAL_GetTick>
|
|
8001556: 4602 mov r2, r0
|
|
8001558: 693b ldr r3, [r7, #16]
|
|
800155a: 1ad3 subs r3, r2, r3
|
|
800155c: 2b64 cmp r3, #100 @ 0x64
|
|
800155e: d901 bls.n 8001564 <HAL_RCC_OscConfig+0x444>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001560: 2303 movs r3, #3
|
|
8001562: e104 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8001564: 4b29 ldr r3, [pc, #164] @ (800160c <HAL_RCC_OscConfig+0x4ec>)
|
|
8001566: 681b ldr r3, [r3, #0]
|
|
8001568: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800156c: 2b00 cmp r3, #0
|
|
800156e: d0f0 beq.n 8001552 <HAL_RCC_OscConfig+0x432>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8001570: 687b ldr r3, [r7, #4]
|
|
8001572: 689b ldr r3, [r3, #8]
|
|
8001574: 2b01 cmp r3, #1
|
|
8001576: d106 bne.n 8001586 <HAL_RCC_OscConfig+0x466>
|
|
8001578: 4b1e ldr r3, [pc, #120] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800157a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800157c: 4a1d ldr r2, [pc, #116] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800157e: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001582: 6353 str r3, [r2, #52] @ 0x34
|
|
8001584: e02d b.n 80015e2 <HAL_RCC_OscConfig+0x4c2>
|
|
8001586: 687b ldr r3, [r7, #4]
|
|
8001588: 689b ldr r3, [r3, #8]
|
|
800158a: 2b00 cmp r3, #0
|
|
800158c: d10c bne.n 80015a8 <HAL_RCC_OscConfig+0x488>
|
|
800158e: 4b19 ldr r3, [pc, #100] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001590: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001592: 4a18 ldr r2, [pc, #96] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
8001594: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8001598: 6353 str r3, [r2, #52] @ 0x34
|
|
800159a: 4b16 ldr r3, [pc, #88] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
800159c: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800159e: 4a15 ldr r2, [pc, #84] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015a0: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
80015a4: 6353 str r3, [r2, #52] @ 0x34
|
|
80015a6: e01c b.n 80015e2 <HAL_RCC_OscConfig+0x4c2>
|
|
80015a8: 687b ldr r3, [r7, #4]
|
|
80015aa: 689b ldr r3, [r3, #8]
|
|
80015ac: 2b05 cmp r3, #5
|
|
80015ae: d10c bne.n 80015ca <HAL_RCC_OscConfig+0x4aa>
|
|
80015b0: 4b10 ldr r3, [pc, #64] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015b2: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80015b4: 4a0f ldr r2, [pc, #60] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015b6: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
80015ba: 6353 str r3, [r2, #52] @ 0x34
|
|
80015bc: 4b0d ldr r3, [pc, #52] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015be: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80015c0: 4a0c ldr r2, [pc, #48] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015c2: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80015c6: 6353 str r3, [r2, #52] @ 0x34
|
|
80015c8: e00b b.n 80015e2 <HAL_RCC_OscConfig+0x4c2>
|
|
80015ca: 4b0a ldr r3, [pc, #40] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015cc: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80015ce: 4a09 ldr r2, [pc, #36] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015d0: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80015d4: 6353 str r3, [r2, #52] @ 0x34
|
|
80015d6: 4b07 ldr r3, [pc, #28] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015d8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80015da: 4a06 ldr r2, [pc, #24] @ (80015f4 <HAL_RCC_OscConfig+0x4d4>)
|
|
80015dc: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
80015e0: 6353 str r3, [r2, #52] @ 0x34
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
80015e2: 687b ldr r3, [r7, #4]
|
|
80015e4: 689b ldr r3, [r3, #8]
|
|
80015e6: 2b00 cmp r3, #0
|
|
80015e8: d024 beq.n 8001634 <HAL_RCC_OscConfig+0x514>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80015ea: f7ff fae1 bl 8000bb0 <HAL_GetTick>
|
|
80015ee: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
|
80015f0: e019 b.n 8001626 <HAL_RCC_OscConfig+0x506>
|
|
80015f2: bf00 nop
|
|
80015f4: 40023800 .word 0x40023800
|
|
80015f8: 08002998 .word 0x08002998
|
|
80015fc: 20000000 .word 0x20000000
|
|
8001600: 20000004 .word 0x20000004
|
|
8001604: 42470020 .word 0x42470020
|
|
8001608: 42470680 .word 0x42470680
|
|
800160c: 40007000 .word 0x40007000
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
8001610: f7ff face bl 8000bb0 <HAL_GetTick>
|
|
8001614: 4602 mov r2, r0
|
|
8001616: 693b ldr r3, [r7, #16]
|
|
8001618: 1ad3 subs r3, r2, r3
|
|
800161a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800161e: 4293 cmp r3, r2
|
|
8001620: d901 bls.n 8001626 <HAL_RCC_OscConfig+0x506>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8001622: 2303 movs r3, #3
|
|
8001624: e0a3 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
|
8001626: 4b54 ldr r3, [pc, #336] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
8001628: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
800162a: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800162e: 2b00 cmp r3, #0
|
|
8001630: d0ee beq.n 8001610 <HAL_RCC_OscConfig+0x4f0>
|
|
8001632: e014 b.n 800165e <HAL_RCC_OscConfig+0x53e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001634: f7ff fabc bl 8000bb0 <HAL_GetTick>
|
|
8001638: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
|
|
800163a: e00a b.n 8001652 <HAL_RCC_OscConfig+0x532>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
800163c: f7ff fab8 bl 8000bb0 <HAL_GetTick>
|
|
8001640: 4602 mov r2, r0
|
|
8001642: 693b ldr r3, [r7, #16]
|
|
8001644: 1ad3 subs r3, r2, r3
|
|
8001646: f241 3288 movw r2, #5000 @ 0x1388
|
|
800164a: 4293 cmp r3, r2
|
|
800164c: d901 bls.n 8001652 <HAL_RCC_OscConfig+0x532>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800164e: 2303 movs r3, #3
|
|
8001650: e08d b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
|
|
8001652: 4b49 ldr r3, [pc, #292] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
8001654: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001656: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800165a: 2b00 cmp r3, #0
|
|
800165c: d1ee bne.n 800163c <HAL_RCC_OscConfig+0x51c>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if(pwrclkchanged == SET)
|
|
800165e: 7ffb ldrb r3, [r7, #31]
|
|
8001660: 2b01 cmp r3, #1
|
|
8001662: d105 bne.n 8001670 <HAL_RCC_OscConfig+0x550>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8001664: 4b44 ldr r3, [pc, #272] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
8001666: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001668: 4a43 ldr r2, [pc, #268] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
800166a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800166e: 6253 str r3, [r2, #36] @ 0x24
|
|
}
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8001670: 687b ldr r3, [r7, #4]
|
|
8001672: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001674: 2b00 cmp r3, #0
|
|
8001676: d079 beq.n 800176c <HAL_RCC_OscConfig+0x64c>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8001678: 69bb ldr r3, [r7, #24]
|
|
800167a: 2b0c cmp r3, #12
|
|
800167c: d056 beq.n 800172c <HAL_RCC_OscConfig+0x60c>
|
|
{
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
800167e: 687b ldr r3, [r7, #4]
|
|
8001680: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001682: 2b02 cmp r3, #2
|
|
8001684: d13b bne.n 80016fe <HAL_RCC_OscConfig+0x5de>
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8001686: 4b3d ldr r3, [pc, #244] @ (800177c <HAL_RCC_OscConfig+0x65c>)
|
|
8001688: 2200 movs r2, #0
|
|
800168a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800168c: f7ff fa90 bl 8000bb0 <HAL_GetTick>
|
|
8001690: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|
8001692: e008 b.n 80016a6 <HAL_RCC_OscConfig+0x586>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
8001694: f7ff fa8c bl 8000bb0 <HAL_GetTick>
|
|
8001698: 4602 mov r2, r0
|
|
800169a: 693b ldr r3, [r7, #16]
|
|
800169c: 1ad3 subs r3, r2, r3
|
|
800169e: 2b02 cmp r3, #2
|
|
80016a0: d901 bls.n 80016a6 <HAL_RCC_OscConfig+0x586>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80016a2: 2303 movs r3, #3
|
|
80016a4: e063 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|
80016a6: 4b34 ldr r3, [pc, #208] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
80016a8: 681b ldr r3, [r3, #0]
|
|
80016aa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80016ae: 2b00 cmp r3, #0
|
|
80016b0: d1f0 bne.n 8001694 <HAL_RCC_OscConfig+0x574>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
80016b2: 4b31 ldr r3, [pc, #196] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
80016b4: 689b ldr r3, [r3, #8]
|
|
80016b6: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000
|
|
80016ba: 687b ldr r3, [r7, #4]
|
|
80016bc: 6a99 ldr r1, [r3, #40] @ 0x28
|
|
80016be: 687b ldr r3, [r7, #4]
|
|
80016c0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80016c2: 4319 orrs r1, r3
|
|
80016c4: 687b ldr r3, [r7, #4]
|
|
80016c6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80016c8: 430b orrs r3, r1
|
|
80016ca: 492b ldr r1, [pc, #172] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
80016cc: 4313 orrs r3, r2
|
|
80016ce: 608b str r3, [r1, #8]
|
|
RCC_OscInitStruct->PLL.PLLMUL,
|
|
RCC_OscInitStruct->PLL.PLLDIV);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80016d0: 4b2a ldr r3, [pc, #168] @ (800177c <HAL_RCC_OscConfig+0x65c>)
|
|
80016d2: 2201 movs r2, #1
|
|
80016d4: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80016d6: f7ff fa6b bl 8000bb0 <HAL_GetTick>
|
|
80016da: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
|
80016dc: e008 b.n 80016f0 <HAL_RCC_OscConfig+0x5d0>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
80016de: f7ff fa67 bl 8000bb0 <HAL_GetTick>
|
|
80016e2: 4602 mov r2, r0
|
|
80016e4: 693b ldr r3, [r7, #16]
|
|
80016e6: 1ad3 subs r3, r2, r3
|
|
80016e8: 2b02 cmp r3, #2
|
|
80016ea: d901 bls.n 80016f0 <HAL_RCC_OscConfig+0x5d0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80016ec: 2303 movs r3, #3
|
|
80016ee: e03e b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
|
80016f0: 4b21 ldr r3, [pc, #132] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
80016f2: 681b ldr r3, [r3, #0]
|
|
80016f4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80016f8: 2b00 cmp r3, #0
|
|
80016fa: d0f0 beq.n 80016de <HAL_RCC_OscConfig+0x5be>
|
|
80016fc: e036 b.n 800176c <HAL_RCC_OscConfig+0x64c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80016fe: 4b1f ldr r3, [pc, #124] @ (800177c <HAL_RCC_OscConfig+0x65c>)
|
|
8001700: 2200 movs r2, #0
|
|
8001702: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8001704: f7ff fa54 bl 8000bb0 <HAL_GetTick>
|
|
8001708: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|
800170a: e008 b.n 800171e <HAL_RCC_OscConfig+0x5fe>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
800170c: f7ff fa50 bl 8000bb0 <HAL_GetTick>
|
|
8001710: 4602 mov r2, r0
|
|
8001712: 693b ldr r3, [r7, #16]
|
|
8001714: 1ad3 subs r3, r2, r3
|
|
8001716: 2b02 cmp r3, #2
|
|
8001718: d901 bls.n 800171e <HAL_RCC_OscConfig+0x5fe>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800171a: 2303 movs r3, #3
|
|
800171c: e027 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
|
|
800171e: 4b16 ldr r3, [pc, #88] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
8001720: 681b ldr r3, [r3, #0]
|
|
8001722: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8001726: 2b00 cmp r3, #0
|
|
8001728: d1f0 bne.n 800170c <HAL_RCC_OscConfig+0x5ec>
|
|
800172a: e01f b.n 800176c <HAL_RCC_OscConfig+0x64c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
800172c: 687b ldr r3, [r7, #4]
|
|
800172e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001730: 2b01 cmp r3, #1
|
|
8001732: d101 bne.n 8001738 <HAL_RCC_OscConfig+0x618>
|
|
{
|
|
return HAL_ERROR;
|
|
8001734: 2301 movs r3, #1
|
|
8001736: e01a b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8001738: 4b0f ldr r3, [pc, #60] @ (8001778 <HAL_RCC_OscConfig+0x658>)
|
|
800173a: 689b ldr r3, [r3, #8]
|
|
800173c: 617b str r3, [r7, #20]
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800173e: 697b ldr r3, [r7, #20]
|
|
8001740: f403 3280 and.w r2, r3, #65536 @ 0x10000
|
|
8001744: 687b ldr r3, [r7, #4]
|
|
8001746: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001748: 429a cmp r2, r3
|
|
800174a: d10d bne.n 8001768 <HAL_RCC_OscConfig+0x648>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
|
800174c: 697b ldr r3, [r7, #20]
|
|
800174e: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
|
|
8001752: 687b ldr r3, [r7, #4]
|
|
8001754: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8001756: 429a cmp r2, r3
|
|
8001758: d106 bne.n 8001768 <HAL_RCC_OscConfig+0x648>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
|
|
800175a: 697b ldr r3, [r7, #20]
|
|
800175c: f403 0240 and.w r2, r3, #12582912 @ 0xc00000
|
|
8001760: 687b ldr r3, [r7, #4]
|
|
8001762: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
|
8001764: 429a cmp r2, r3
|
|
8001766: d001 beq.n 800176c <HAL_RCC_OscConfig+0x64c>
|
|
{
|
|
return HAL_ERROR;
|
|
8001768: 2301 movs r3, #1
|
|
800176a: e000 b.n 800176e <HAL_RCC_OscConfig+0x64e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800176c: 2300 movs r3, #0
|
|
}
|
|
800176e: 4618 mov r0, r3
|
|
8001770: 3720 adds r7, #32
|
|
8001772: 46bd mov sp, r7
|
|
8001774: bd80 pop {r7, pc}
|
|
8001776: bf00 nop
|
|
8001778: 40023800 .word 0x40023800
|
|
800177c: 42470060 .word 0x42470060
|
|
|
|
08001780 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8001780: b580 push {r7, lr}
|
|
8001782: b084 sub sp, #16
|
|
8001784: af00 add r7, sp, #0
|
|
8001786: 6078 str r0, [r7, #4]
|
|
8001788: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check the parameters */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
800178a: 687b ldr r3, [r7, #4]
|
|
800178c: 2b00 cmp r3, #0
|
|
800178e: d101 bne.n 8001794 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8001790: 2301 movs r3, #1
|
|
8001792: e11a b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8001794: 4b8f ldr r3, [pc, #572] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
8001796: 681b ldr r3, [r3, #0]
|
|
8001798: f003 0301 and.w r3, r3, #1
|
|
800179c: 683a ldr r2, [r7, #0]
|
|
800179e: 429a cmp r2, r3
|
|
80017a0: d919 bls.n 80017d6 <HAL_RCC_ClockConfig+0x56>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80017a2: 683b ldr r3, [r7, #0]
|
|
80017a4: 2b01 cmp r3, #1
|
|
80017a6: d105 bne.n 80017b4 <HAL_RCC_ClockConfig+0x34>
|
|
80017a8: 4b8a ldr r3, [pc, #552] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
80017aa: 681b ldr r3, [r3, #0]
|
|
80017ac: 4a89 ldr r2, [pc, #548] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
80017ae: f043 0304 orr.w r3, r3, #4
|
|
80017b2: 6013 str r3, [r2, #0]
|
|
80017b4: 4b87 ldr r3, [pc, #540] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
80017b6: 681b ldr r3, [r3, #0]
|
|
80017b8: f023 0201 bic.w r2, r3, #1
|
|
80017bc: 4985 ldr r1, [pc, #532] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
80017be: 683b ldr r3, [r7, #0]
|
|
80017c0: 4313 orrs r3, r2
|
|
80017c2: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80017c4: 4b83 ldr r3, [pc, #524] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
80017c6: 681b ldr r3, [r3, #0]
|
|
80017c8: f003 0301 and.w r3, r3, #1
|
|
80017cc: 683a ldr r2, [r7, #0]
|
|
80017ce: 429a cmp r2, r3
|
|
80017d0: d001 beq.n 80017d6 <HAL_RCC_ClockConfig+0x56>
|
|
{
|
|
return HAL_ERROR;
|
|
80017d2: 2301 movs r3, #1
|
|
80017d4: e0f9 b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80017d6: 687b ldr r3, [r7, #4]
|
|
80017d8: 681b ldr r3, [r3, #0]
|
|
80017da: f003 0302 and.w r3, r3, #2
|
|
80017de: 2b00 cmp r3, #0
|
|
80017e0: d008 beq.n 80017f4 <HAL_RCC_ClockConfig+0x74>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
80017e2: 4b7d ldr r3, [pc, #500] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
80017e4: 689b ldr r3, [r3, #8]
|
|
80017e6: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
80017ea: 687b ldr r3, [r7, #4]
|
|
80017ec: 689b ldr r3, [r3, #8]
|
|
80017ee: 497a ldr r1, [pc, #488] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
80017f0: 4313 orrs r3, r2
|
|
80017f2: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
80017f4: 687b ldr r3, [r7, #4]
|
|
80017f6: 681b ldr r3, [r3, #0]
|
|
80017f8: f003 0301 and.w r3, r3, #1
|
|
80017fc: 2b00 cmp r3, #0
|
|
80017fe: f000 808e beq.w 800191e <HAL_RCC_ClockConfig+0x19e>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8001802: 687b ldr r3, [r7, #4]
|
|
8001804: 685b ldr r3, [r3, #4]
|
|
8001806: 2b02 cmp r3, #2
|
|
8001808: d107 bne.n 800181a <HAL_RCC_ClockConfig+0x9a>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
|
|
800180a: 4b73 ldr r3, [pc, #460] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800180c: 681b ldr r3, [r3, #0]
|
|
800180e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001812: 2b00 cmp r3, #0
|
|
8001814: d121 bne.n 800185a <HAL_RCC_ClockConfig+0xda>
|
|
{
|
|
return HAL_ERROR;
|
|
8001816: 2301 movs r3, #1
|
|
8001818: e0d7 b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
800181a: 687b ldr r3, [r7, #4]
|
|
800181c: 685b ldr r3, [r3, #4]
|
|
800181e: 2b03 cmp r3, #3
|
|
8001820: d107 bne.n 8001832 <HAL_RCC_ClockConfig+0xb2>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
|
|
8001822: 4b6d ldr r3, [pc, #436] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
8001824: 681b ldr r3, [r3, #0]
|
|
8001826: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800182a: 2b00 cmp r3, #0
|
|
800182c: d115 bne.n 800185a <HAL_RCC_ClockConfig+0xda>
|
|
{
|
|
return HAL_ERROR;
|
|
800182e: 2301 movs r3, #1
|
|
8001830: e0cb b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
}
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|
8001832: 687b ldr r3, [r7, #4]
|
|
8001834: 685b ldr r3, [r3, #4]
|
|
8001836: 2b01 cmp r3, #1
|
|
8001838: d107 bne.n 800184a <HAL_RCC_ClockConfig+0xca>
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
|
|
800183a: 4b67 ldr r3, [pc, #412] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800183c: 681b ldr r3, [r3, #0]
|
|
800183e: f003 0302 and.w r3, r3, #2
|
|
8001842: 2b00 cmp r3, #0
|
|
8001844: d109 bne.n 800185a <HAL_RCC_ClockConfig+0xda>
|
|
{
|
|
return HAL_ERROR;
|
|
8001846: 2301 movs r3, #1
|
|
8001848: e0bf b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
|
|
800184a: 4b63 ldr r3, [pc, #396] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800184c: 681b ldr r3, [r3, #0]
|
|
800184e: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001852: 2b00 cmp r3, #0
|
|
8001854: d101 bne.n 800185a <HAL_RCC_ClockConfig+0xda>
|
|
{
|
|
return HAL_ERROR;
|
|
8001856: 2301 movs r3, #1
|
|
8001858: e0b7 b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
800185a: 4b5f ldr r3, [pc, #380] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800185c: 689b ldr r3, [r3, #8]
|
|
800185e: f023 0203 bic.w r2, r3, #3
|
|
8001862: 687b ldr r3, [r7, #4]
|
|
8001864: 685b ldr r3, [r3, #4]
|
|
8001866: 495c ldr r1, [pc, #368] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
8001868: 4313 orrs r3, r2
|
|
800186a: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800186c: f7ff f9a0 bl 8000bb0 <HAL_GetTick>
|
|
8001870: 60f8 str r0, [r7, #12]
|
|
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8001872: 687b ldr r3, [r7, #4]
|
|
8001874: 685b ldr r3, [r3, #4]
|
|
8001876: 2b02 cmp r3, #2
|
|
8001878: d112 bne.n 80018a0 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
800187a: e00a b.n 8001892 <HAL_RCC_ClockConfig+0x112>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
800187c: f7ff f998 bl 8000bb0 <HAL_GetTick>
|
|
8001880: 4602 mov r2, r0
|
|
8001882: 68fb ldr r3, [r7, #12]
|
|
8001884: 1ad3 subs r3, r2, r3
|
|
8001886: f241 3288 movw r2, #5000 @ 0x1388
|
|
800188a: 4293 cmp r3, r2
|
|
800188c: d901 bls.n 8001892 <HAL_RCC_ClockConfig+0x112>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800188e: 2303 movs r3, #3
|
|
8001890: e09b b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8001892: 4b51 ldr r3, [pc, #324] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
8001894: 689b ldr r3, [r3, #8]
|
|
8001896: f003 030c and.w r3, r3, #12
|
|
800189a: 2b08 cmp r3, #8
|
|
800189c: d1ee bne.n 800187c <HAL_RCC_ClockConfig+0xfc>
|
|
800189e: e03e b.n 800191e <HAL_RCC_ClockConfig+0x19e>
|
|
}
|
|
}
|
|
}
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
80018a0: 687b ldr r3, [r7, #4]
|
|
80018a2: 685b ldr r3, [r3, #4]
|
|
80018a4: 2b03 cmp r3, #3
|
|
80018a6: d112 bne.n 80018ce <HAL_RCC_ClockConfig+0x14e>
|
|
{
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
80018a8: e00a b.n 80018c0 <HAL_RCC_ClockConfig+0x140>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80018aa: f7ff f981 bl 8000bb0 <HAL_GetTick>
|
|
80018ae: 4602 mov r2, r0
|
|
80018b0: 68fb ldr r3, [r7, #12]
|
|
80018b2: 1ad3 subs r3, r2, r3
|
|
80018b4: f241 3288 movw r2, #5000 @ 0x1388
|
|
80018b8: 4293 cmp r3, r2
|
|
80018ba: d901 bls.n 80018c0 <HAL_RCC_ClockConfig+0x140>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80018bc: 2303 movs r3, #3
|
|
80018be: e084 b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
80018c0: 4b45 ldr r3, [pc, #276] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
80018c2: 689b ldr r3, [r3, #8]
|
|
80018c4: f003 030c and.w r3, r3, #12
|
|
80018c8: 2b0c cmp r3, #12
|
|
80018ca: d1ee bne.n 80018aa <HAL_RCC_ClockConfig+0x12a>
|
|
80018cc: e027 b.n 800191e <HAL_RCC_ClockConfig+0x19e>
|
|
}
|
|
}
|
|
}
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|
80018ce: 687b ldr r3, [r7, #4]
|
|
80018d0: 685b ldr r3, [r3, #4]
|
|
80018d2: 2b01 cmp r3, #1
|
|
80018d4: d11d bne.n 8001912 <HAL_RCC_ClockConfig+0x192>
|
|
{
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
80018d6: e00a b.n 80018ee <HAL_RCC_ClockConfig+0x16e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80018d8: f7ff f96a bl 8000bb0 <HAL_GetTick>
|
|
80018dc: 4602 mov r2, r0
|
|
80018de: 68fb ldr r3, [r7, #12]
|
|
80018e0: 1ad3 subs r3, r2, r3
|
|
80018e2: f241 3288 movw r2, #5000 @ 0x1388
|
|
80018e6: 4293 cmp r3, r2
|
|
80018e8: d901 bls.n 80018ee <HAL_RCC_ClockConfig+0x16e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80018ea: 2303 movs r3, #3
|
|
80018ec: e06d b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
80018ee: 4b3a ldr r3, [pc, #232] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
80018f0: 689b ldr r3, [r3, #8]
|
|
80018f2: f003 030c and.w r3, r3, #12
|
|
80018f6: 2b04 cmp r3, #4
|
|
80018f8: d1ee bne.n 80018d8 <HAL_RCC_ClockConfig+0x158>
|
|
80018fa: e010 b.n 800191e <HAL_RCC_ClockConfig+0x19e>
|
|
}
|
|
else
|
|
{
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80018fc: f7ff f958 bl 8000bb0 <HAL_GetTick>
|
|
8001900: 4602 mov r2, r0
|
|
8001902: 68fb ldr r3, [r7, #12]
|
|
8001904: 1ad3 subs r3, r2, r3
|
|
8001906: f241 3288 movw r2, #5000 @ 0x1388
|
|
800190a: 4293 cmp r3, r2
|
|
800190c: d901 bls.n 8001912 <HAL_RCC_ClockConfig+0x192>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800190e: 2303 movs r3, #3
|
|
8001910: e05b b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
|
|
8001912: 4b31 ldr r3, [pc, #196] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
8001914: 689b ldr r3, [r3, #8]
|
|
8001916: f003 030c and.w r3, r3, #12
|
|
800191a: 2b00 cmp r3, #0
|
|
800191c: d1ee bne.n 80018fc <HAL_RCC_ClockConfig+0x17c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
800191e: 4b2d ldr r3, [pc, #180] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
8001920: 681b ldr r3, [r3, #0]
|
|
8001922: f003 0301 and.w r3, r3, #1
|
|
8001926: 683a ldr r2, [r7, #0]
|
|
8001928: 429a cmp r2, r3
|
|
800192a: d219 bcs.n 8001960 <HAL_RCC_ClockConfig+0x1e0>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800192c: 683b ldr r3, [r7, #0]
|
|
800192e: 2b01 cmp r3, #1
|
|
8001930: d105 bne.n 800193e <HAL_RCC_ClockConfig+0x1be>
|
|
8001932: 4b28 ldr r3, [pc, #160] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
8001934: 681b ldr r3, [r3, #0]
|
|
8001936: 4a27 ldr r2, [pc, #156] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
8001938: f043 0304 orr.w r3, r3, #4
|
|
800193c: 6013 str r3, [r2, #0]
|
|
800193e: 4b25 ldr r3, [pc, #148] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
8001940: 681b ldr r3, [r3, #0]
|
|
8001942: f023 0201 bic.w r2, r3, #1
|
|
8001946: 4923 ldr r1, [pc, #140] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
8001948: 683b ldr r3, [r7, #0]
|
|
800194a: 4313 orrs r3, r2
|
|
800194c: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800194e: 4b21 ldr r3, [pc, #132] @ (80019d4 <HAL_RCC_ClockConfig+0x254>)
|
|
8001950: 681b ldr r3, [r3, #0]
|
|
8001952: f003 0301 and.w r3, r3, #1
|
|
8001956: 683a ldr r2, [r7, #0]
|
|
8001958: 429a cmp r2, r3
|
|
800195a: d001 beq.n 8001960 <HAL_RCC_ClockConfig+0x1e0>
|
|
{
|
|
return HAL_ERROR;
|
|
800195c: 2301 movs r3, #1
|
|
800195e: e034 b.n 80019ca <HAL_RCC_ClockConfig+0x24a>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8001960: 687b ldr r3, [r7, #4]
|
|
8001962: 681b ldr r3, [r3, #0]
|
|
8001964: f003 0304 and.w r3, r3, #4
|
|
8001968: 2b00 cmp r3, #0
|
|
800196a: d008 beq.n 800197e <HAL_RCC_ClockConfig+0x1fe>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
800196c: 4b1a ldr r3, [pc, #104] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800196e: 689b ldr r3, [r3, #8]
|
|
8001970: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
8001974: 687b ldr r3, [r7, #4]
|
|
8001976: 68db ldr r3, [r3, #12]
|
|
8001978: 4917 ldr r1, [pc, #92] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800197a: 4313 orrs r3, r2
|
|
800197c: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800197e: 687b ldr r3, [r7, #4]
|
|
8001980: 681b ldr r3, [r3, #0]
|
|
8001982: f003 0308 and.w r3, r3, #8
|
|
8001986: 2b00 cmp r3, #0
|
|
8001988: d009 beq.n 800199e <HAL_RCC_ClockConfig+0x21e>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
800198a: 4b13 ldr r3, [pc, #76] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800198c: 689b ldr r3, [r3, #8]
|
|
800198e: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
8001992: 687b ldr r3, [r7, #4]
|
|
8001994: 691b ldr r3, [r3, #16]
|
|
8001996: 00db lsls r3, r3, #3
|
|
8001998: 490f ldr r1, [pc, #60] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
800199a: 4313 orrs r3, r2
|
|
800199c: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
|
|
800199e: f000 f823 bl 80019e8 <HAL_RCC_GetSysClockFreq>
|
|
80019a2: 4602 mov r2, r0
|
|
80019a4: 4b0c ldr r3, [pc, #48] @ (80019d8 <HAL_RCC_ClockConfig+0x258>)
|
|
80019a6: 689b ldr r3, [r3, #8]
|
|
80019a8: 091b lsrs r3, r3, #4
|
|
80019aa: f003 030f and.w r3, r3, #15
|
|
80019ae: 490b ldr r1, [pc, #44] @ (80019dc <HAL_RCC_ClockConfig+0x25c>)
|
|
80019b0: 5ccb ldrb r3, [r1, r3]
|
|
80019b2: fa22 f303 lsr.w r3, r2, r3
|
|
80019b6: 4a0a ldr r2, [pc, #40] @ (80019e0 <HAL_RCC_ClockConfig+0x260>)
|
|
80019b8: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
80019ba: 4b0a ldr r3, [pc, #40] @ (80019e4 <HAL_RCC_ClockConfig+0x264>)
|
|
80019bc: 681b ldr r3, [r3, #0]
|
|
80019be: 4618 mov r0, r3
|
|
80019c0: f7ff f8aa bl 8000b18 <HAL_InitTick>
|
|
80019c4: 4603 mov r3, r0
|
|
80019c6: 72fb strb r3, [r7, #11]
|
|
|
|
return status;
|
|
80019c8: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
80019ca: 4618 mov r0, r3
|
|
80019cc: 3710 adds r7, #16
|
|
80019ce: 46bd mov sp, r7
|
|
80019d0: bd80 pop {r7, pc}
|
|
80019d2: bf00 nop
|
|
80019d4: 40023c00 .word 0x40023c00
|
|
80019d8: 40023800 .word 0x40023800
|
|
80019dc: 08002998 .word 0x08002998
|
|
80019e0: 20000000 .word 0x20000000
|
|
80019e4: 20000004 .word 0x20000004
|
|
|
|
080019e8 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80019e8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
80019ec: b08e sub sp, #56 @ 0x38
|
|
80019ee: af00 add r7, sp, #0
|
|
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
|
|
|
|
tmpreg = RCC->CFGR;
|
|
80019f0: 4b58 ldr r3, [pc, #352] @ (8001b54 <HAL_RCC_GetSysClockFreq+0x16c>)
|
|
80019f2: 689b ldr r3, [r3, #8]
|
|
80019f4: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
80019f6: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80019f8: f003 030c and.w r3, r3, #12
|
|
80019fc: 2b0c cmp r3, #12
|
|
80019fe: d00d beq.n 8001a1c <HAL_RCC_GetSysClockFreq+0x34>
|
|
8001a00: 2b0c cmp r3, #12
|
|
8001a02: f200 8092 bhi.w 8001b2a <HAL_RCC_GetSysClockFreq+0x142>
|
|
8001a06: 2b04 cmp r3, #4
|
|
8001a08: d002 beq.n 8001a10 <HAL_RCC_GetSysClockFreq+0x28>
|
|
8001a0a: 2b08 cmp r3, #8
|
|
8001a0c: d003 beq.n 8001a16 <HAL_RCC_GetSysClockFreq+0x2e>
|
|
8001a0e: e08c b.n 8001b2a <HAL_RCC_GetSysClockFreq+0x142>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8001a10: 4b51 ldr r3, [pc, #324] @ (8001b58 <HAL_RCC_GetSysClockFreq+0x170>)
|
|
8001a12: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8001a14: e097 b.n 8001b46 <HAL_RCC_GetSysClockFreq+0x15e>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8001a16: 4b51 ldr r3, [pc, #324] @ (8001b5c <HAL_RCC_GetSysClockFreq+0x174>)
|
|
8001a18: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8001a1a: e094 b.n 8001b46 <HAL_RCC_GetSysClockFreq+0x15e>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
|
|
8001a1c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8001a1e: 0c9b lsrs r3, r3, #18
|
|
8001a20: f003 020f and.w r2, r3, #15
|
|
8001a24: 4b4e ldr r3, [pc, #312] @ (8001b60 <HAL_RCC_GetSysClockFreq+0x178>)
|
|
8001a26: 5c9b ldrb r3, [r3, r2]
|
|
8001a28: 62bb str r3, [r7, #40] @ 0x28
|
|
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
|
|
8001a2a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8001a2c: 0d9b lsrs r3, r3, #22
|
|
8001a2e: f003 0303 and.w r3, r3, #3
|
|
8001a32: 3301 adds r3, #1
|
|
8001a34: 627b str r3, [r7, #36] @ 0x24
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8001a36: 4b47 ldr r3, [pc, #284] @ (8001b54 <HAL_RCC_GetSysClockFreq+0x16c>)
|
|
8001a38: 689b ldr r3, [r3, #8]
|
|
8001a3a: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001a3e: 2b00 cmp r3, #0
|
|
8001a40: d021 beq.n 8001a86 <HAL_RCC_GetSysClockFreq+0x9e>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
|
|
8001a42: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001a44: 2200 movs r2, #0
|
|
8001a46: 61bb str r3, [r7, #24]
|
|
8001a48: 61fa str r2, [r7, #28]
|
|
8001a4a: 4b44 ldr r3, [pc, #272] @ (8001b5c <HAL_RCC_GetSysClockFreq+0x174>)
|
|
8001a4c: e9d7 8906 ldrd r8, r9, [r7, #24]
|
|
8001a50: 464a mov r2, r9
|
|
8001a52: fb03 f202 mul.w r2, r3, r2
|
|
8001a56: 2300 movs r3, #0
|
|
8001a58: 4644 mov r4, r8
|
|
8001a5a: fb04 f303 mul.w r3, r4, r3
|
|
8001a5e: 4413 add r3, r2
|
|
8001a60: 4a3e ldr r2, [pc, #248] @ (8001b5c <HAL_RCC_GetSysClockFreq+0x174>)
|
|
8001a62: 4644 mov r4, r8
|
|
8001a64: fba4 0102 umull r0, r1, r4, r2
|
|
8001a68: 440b add r3, r1
|
|
8001a6a: 4619 mov r1, r3
|
|
8001a6c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001a6e: 2200 movs r2, #0
|
|
8001a70: 613b str r3, [r7, #16]
|
|
8001a72: 617a str r2, [r7, #20]
|
|
8001a74: e9d7 2304 ldrd r2, r3, [r7, #16]
|
|
8001a78: f7fe fb80 bl 800017c <__aeabi_uldivmod>
|
|
8001a7c: 4602 mov r2, r0
|
|
8001a7e: 460b mov r3, r1
|
|
8001a80: 4613 mov r3, r2
|
|
8001a82: 637b str r3, [r7, #52] @ 0x34
|
|
8001a84: e04e b.n 8001b24 <HAL_RCC_GetSysClockFreq+0x13c>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
|
|
8001a86: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001a88: 2200 movs r2, #0
|
|
8001a8a: 469a mov sl, r3
|
|
8001a8c: 4693 mov fp, r2
|
|
8001a8e: 4652 mov r2, sl
|
|
8001a90: 465b mov r3, fp
|
|
8001a92: f04f 0000 mov.w r0, #0
|
|
8001a96: f04f 0100 mov.w r1, #0
|
|
8001a9a: 0159 lsls r1, r3, #5
|
|
8001a9c: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8001aa0: 0150 lsls r0, r2, #5
|
|
8001aa2: 4602 mov r2, r0
|
|
8001aa4: 460b mov r3, r1
|
|
8001aa6: ebb2 080a subs.w r8, r2, sl
|
|
8001aaa: eb63 090b sbc.w r9, r3, fp
|
|
8001aae: f04f 0200 mov.w r2, #0
|
|
8001ab2: f04f 0300 mov.w r3, #0
|
|
8001ab6: ea4f 1389 mov.w r3, r9, lsl #6
|
|
8001aba: ea43 6398 orr.w r3, r3, r8, lsr #26
|
|
8001abe: ea4f 1288 mov.w r2, r8, lsl #6
|
|
8001ac2: ebb2 0408 subs.w r4, r2, r8
|
|
8001ac6: eb63 0509 sbc.w r5, r3, r9
|
|
8001aca: f04f 0200 mov.w r2, #0
|
|
8001ace: f04f 0300 mov.w r3, #0
|
|
8001ad2: 00eb lsls r3, r5, #3
|
|
8001ad4: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8001ad8: 00e2 lsls r2, r4, #3
|
|
8001ada: 4614 mov r4, r2
|
|
8001adc: 461d mov r5, r3
|
|
8001ade: eb14 030a adds.w r3, r4, sl
|
|
8001ae2: 603b str r3, [r7, #0]
|
|
8001ae4: eb45 030b adc.w r3, r5, fp
|
|
8001ae8: 607b str r3, [r7, #4]
|
|
8001aea: f04f 0200 mov.w r2, #0
|
|
8001aee: f04f 0300 mov.w r3, #0
|
|
8001af2: e9d7 4500 ldrd r4, r5, [r7]
|
|
8001af6: 4629 mov r1, r5
|
|
8001af8: 028b lsls r3, r1, #10
|
|
8001afa: 4620 mov r0, r4
|
|
8001afc: 4629 mov r1, r5
|
|
8001afe: 4604 mov r4, r0
|
|
8001b00: ea43 5394 orr.w r3, r3, r4, lsr #22
|
|
8001b04: 4601 mov r1, r0
|
|
8001b06: 028a lsls r2, r1, #10
|
|
8001b08: 4610 mov r0, r2
|
|
8001b0a: 4619 mov r1, r3
|
|
8001b0c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8001b0e: 2200 movs r2, #0
|
|
8001b10: 60bb str r3, [r7, #8]
|
|
8001b12: 60fa str r2, [r7, #12]
|
|
8001b14: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
8001b18: f7fe fb30 bl 800017c <__aeabi_uldivmod>
|
|
8001b1c: 4602 mov r2, r0
|
|
8001b1e: 460b mov r3, r1
|
|
8001b20: 4613 mov r3, r2
|
|
8001b22: 637b str r3, [r7, #52] @ 0x34
|
|
}
|
|
sysclockfreq = pllvco;
|
|
8001b24: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8001b26: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8001b28: e00d b.n 8001b46 <HAL_RCC_GetSysClockFreq+0x15e>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
|
|
default: /* MSI used as system clock */
|
|
{
|
|
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
|
|
8001b2a: 4b0a ldr r3, [pc, #40] @ (8001b54 <HAL_RCC_GetSysClockFreq+0x16c>)
|
|
8001b2c: 685b ldr r3, [r3, #4]
|
|
8001b2e: 0b5b lsrs r3, r3, #13
|
|
8001b30: f003 0307 and.w r3, r3, #7
|
|
8001b34: 623b str r3, [r7, #32]
|
|
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
|
|
8001b36: 6a3b ldr r3, [r7, #32]
|
|
8001b38: 3301 adds r3, #1
|
|
8001b3a: f44f 4200 mov.w r2, #32768 @ 0x8000
|
|
8001b3e: fa02 f303 lsl.w r3, r2, r3
|
|
8001b42: 633b str r3, [r7, #48] @ 0x30
|
|
break;
|
|
8001b44: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8001b46: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
}
|
|
8001b48: 4618 mov r0, r3
|
|
8001b4a: 3738 adds r7, #56 @ 0x38
|
|
8001b4c: 46bd mov sp, r7
|
|
8001b4e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8001b52: bf00 nop
|
|
8001b54: 40023800 .word 0x40023800
|
|
8001b58: 00f42400 .word 0x00f42400
|
|
8001b5c: 016e3600 .word 0x016e3600
|
|
8001b60: 0800298c .word 0x0800298c
|
|
|
|
08001b64 <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range
|
|
* @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
|
|
{
|
|
8001b64: b480 push {r7}
|
|
8001b66: b087 sub sp, #28
|
|
8001b68: af00 add r7, sp, #0
|
|
8001b6a: 6078 str r0, [r7, #4]
|
|
uint32_t vos;
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
8001b6c: 2300 movs r3, #0
|
|
8001b6e: 613b str r3, [r7, #16]
|
|
|
|
/* HCLK can reach 4 MHz only if AHB prescaler = 1 */
|
|
if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
|
|
8001b70: 4b29 ldr r3, [pc, #164] @ (8001c18 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
|
|
8001b72: 689b ldr r3, [r3, #8]
|
|
8001b74: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8001b78: 2b00 cmp r3, #0
|
|
8001b7a: d12c bne.n 8001bd6 <RCC_SetFlashLatencyFromMSIRange+0x72>
|
|
{
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
8001b7c: 4b26 ldr r3, [pc, #152] @ (8001c18 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
|
|
8001b7e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001b80: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001b84: 2b00 cmp r3, #0
|
|
8001b86: d005 beq.n 8001b94 <RCC_SetFlashLatencyFromMSIRange+0x30>
|
|
{
|
|
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
|
|
8001b88: 4b24 ldr r3, [pc, #144] @ (8001c1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8001b8a: 681b ldr r3, [r3, #0]
|
|
8001b8c: f403 53c0 and.w r3, r3, #6144 @ 0x1800
|
|
8001b90: 617b str r3, [r7, #20]
|
|
8001b92: e016 b.n 8001bc2 <RCC_SetFlashLatencyFromMSIRange+0x5e>
|
|
}
|
|
else
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8001b94: 4b20 ldr r3, [pc, #128] @ (8001c18 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
|
|
8001b96: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001b98: 4a1f ldr r2, [pc, #124] @ (8001c18 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
|
|
8001b9a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001b9e: 6253 str r3, [r2, #36] @ 0x24
|
|
8001ba0: 4b1d ldr r3, [pc, #116] @ (8001c18 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
|
|
8001ba2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001ba4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001ba8: 60fb str r3, [r7, #12]
|
|
8001baa: 68fb ldr r3, [r7, #12]
|
|
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
|
|
8001bac: 4b1b ldr r3, [pc, #108] @ (8001c1c <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
8001bae: 681b ldr r3, [r3, #0]
|
|
8001bb0: f403 53c0 and.w r3, r3, #6144 @ 0x1800
|
|
8001bb4: 617b str r3, [r7, #20]
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8001bb6: 4b18 ldr r3, [pc, #96] @ (8001c18 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
|
|
8001bb8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001bba: 4a17 ldr r2, [pc, #92] @ (8001c18 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
|
|
8001bbc: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8001bc0: 6253 str r3, [r2, #36] @ 0x24
|
|
}
|
|
|
|
/* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
|
|
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
|
|
8001bc2: 697b ldr r3, [r7, #20]
|
|
8001bc4: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800
|
|
8001bc8: d105 bne.n 8001bd6 <RCC_SetFlashLatencyFromMSIRange+0x72>
|
|
8001bca: 687b ldr r3, [r7, #4]
|
|
8001bcc: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
|
|
8001bd0: d101 bne.n 8001bd6 <RCC_SetFlashLatencyFromMSIRange+0x72>
|
|
{
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
8001bd2: 2301 movs r3, #1
|
|
8001bd4: 613b str r3, [r7, #16]
|
|
}
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
8001bd6: 693b ldr r3, [r7, #16]
|
|
8001bd8: 2b01 cmp r3, #1
|
|
8001bda: d105 bne.n 8001be8 <RCC_SetFlashLatencyFromMSIRange+0x84>
|
|
8001bdc: 4b10 ldr r3, [pc, #64] @ (8001c20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
8001bde: 681b ldr r3, [r3, #0]
|
|
8001be0: 4a0f ldr r2, [pc, #60] @ (8001c20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
8001be2: f043 0304 orr.w r3, r3, #4
|
|
8001be6: 6013 str r3, [r2, #0]
|
|
8001be8: 4b0d ldr r3, [pc, #52] @ (8001c20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
8001bea: 681b ldr r3, [r3, #0]
|
|
8001bec: f023 0201 bic.w r2, r3, #1
|
|
8001bf0: 490b ldr r1, [pc, #44] @ (8001c20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
8001bf2: 693b ldr r3, [r7, #16]
|
|
8001bf4: 4313 orrs r3, r2
|
|
8001bf6: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
|
8001bf8: 4b09 ldr r3, [pc, #36] @ (8001c20 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
8001bfa: 681b ldr r3, [r3, #0]
|
|
8001bfc: f003 0301 and.w r3, r3, #1
|
|
8001c00: 693a ldr r2, [r7, #16]
|
|
8001c02: 429a cmp r2, r3
|
|
8001c04: d001 beq.n 8001c0a <RCC_SetFlashLatencyFromMSIRange+0xa6>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c06: 2301 movs r3, #1
|
|
8001c08: e000 b.n 8001c0c <RCC_SetFlashLatencyFromMSIRange+0xa8>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8001c0a: 2300 movs r3, #0
|
|
}
|
|
8001c0c: 4618 mov r0, r3
|
|
8001c0e: 371c adds r7, #28
|
|
8001c10: 46bd mov sp, r7
|
|
8001c12: bc80 pop {r7}
|
|
8001c14: 4770 bx lr
|
|
8001c16: bf00 nop
|
|
8001c18: 40023800 .word 0x40023800
|
|
8001c1c: 40007000 .word 0x40007000
|
|
8001c20: 40023c00 .word 0x40023c00
|
|
|
|
08001c24 <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8001c24: b580 push {r7, lr}
|
|
8001c26: b082 sub sp, #8
|
|
8001c28: af00 add r7, sp, #0
|
|
8001c2a: 6078 str r0, [r7, #4]
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
8001c2c: 687b ldr r3, [r7, #4]
|
|
8001c2e: 2b00 cmp r3, #0
|
|
8001c30: d101 bne.n 8001c36 <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c32: 2301 movs r3, #1
|
|
8001c34: e07b b.n 8001d2e <HAL_SPI_Init+0x10a>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
|
/* TI mode is not supported on all devices in stm32l1xx series.
|
|
TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
|
|
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
|
|
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
|
|
8001c36: 687b ldr r3, [r7, #4]
|
|
8001c38: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001c3a: 2b00 cmp r3, #0
|
|
8001c3c: d108 bne.n 8001c50 <HAL_SPI_Init+0x2c>
|
|
{
|
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
|
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
8001c3e: 687b ldr r3, [r7, #4]
|
|
8001c40: 685b ldr r3, [r3, #4]
|
|
8001c42: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8001c46: d009 beq.n 8001c5c <HAL_SPI_Init+0x38>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
}
|
|
else
|
|
{
|
|
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
|
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
8001c48: 687b ldr r3, [r7, #4]
|
|
8001c4a: 2200 movs r2, #0
|
|
8001c4c: 61da str r2, [r3, #28]
|
|
8001c4e: e005 b.n 8001c5c <HAL_SPI_Init+0x38>
|
|
else
|
|
{
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
|
|
/* Force polarity and phase to TI protocaol requirements */
|
|
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
8001c50: 687b ldr r3, [r7, #4]
|
|
8001c52: 2200 movs r2, #0
|
|
8001c54: 611a str r2, [r3, #16]
|
|
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8001c56: 687b ldr r3, [r7, #4]
|
|
8001c58: 2200 movs r2, #0
|
|
8001c5a: 615a str r2, [r3, #20]
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8001c5c: 687b ldr r3, [r7, #4]
|
|
8001c5e: 2200 movs r2, #0
|
|
8001c60: 629a str r2, [r3, #40] @ 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
8001c62: 687b ldr r3, [r7, #4]
|
|
8001c64: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
|
|
8001c68: b2db uxtb r3, r3
|
|
8001c6a: 2b00 cmp r3, #0
|
|
8001c6c: d106 bne.n 8001c7c <HAL_SPI_Init+0x58>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
8001c6e: 687b ldr r3, [r7, #4]
|
|
8001c70: 2200 movs r2, #0
|
|
8001c72: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
8001c76: 6878 ldr r0, [r7, #4]
|
|
8001c78: f7fe fe1e bl 80008b8 <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
8001c7c: 687b ldr r3, [r7, #4]
|
|
8001c7e: 2202 movs r2, #2
|
|
8001c80: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8001c84: 687b ldr r3, [r7, #4]
|
|
8001c86: 681b ldr r3, [r3, #0]
|
|
8001c88: 681a ldr r2, [r3, #0]
|
|
8001c8a: 687b ldr r3, [r7, #4]
|
|
8001c8c: 681b ldr r3, [r3, #0]
|
|
8001c8e: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8001c92: 601a str r2, [r3, #0]
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
|
8001c94: 687b ldr r3, [r7, #4]
|
|
8001c96: 685b ldr r3, [r3, #4]
|
|
8001c98: f403 7282 and.w r2, r3, #260 @ 0x104
|
|
8001c9c: 687b ldr r3, [r7, #4]
|
|
8001c9e: 689b ldr r3, [r3, #8]
|
|
8001ca0: f403 4304 and.w r3, r3, #33792 @ 0x8400
|
|
8001ca4: 431a orrs r2, r3
|
|
8001ca6: 687b ldr r3, [r7, #4]
|
|
8001ca8: 68db ldr r3, [r3, #12]
|
|
8001caa: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8001cae: 431a orrs r2, r3
|
|
8001cb0: 687b ldr r3, [r7, #4]
|
|
8001cb2: 691b ldr r3, [r3, #16]
|
|
8001cb4: f003 0302 and.w r3, r3, #2
|
|
8001cb8: 431a orrs r2, r3
|
|
8001cba: 687b ldr r3, [r7, #4]
|
|
8001cbc: 695b ldr r3, [r3, #20]
|
|
8001cbe: f003 0301 and.w r3, r3, #1
|
|
8001cc2: 431a orrs r2, r3
|
|
8001cc4: 687b ldr r3, [r7, #4]
|
|
8001cc6: 699b ldr r3, [r3, #24]
|
|
8001cc8: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001ccc: 431a orrs r2, r3
|
|
8001cce: 687b ldr r3, [r7, #4]
|
|
8001cd0: 69db ldr r3, [r3, #28]
|
|
8001cd2: f003 0338 and.w r3, r3, #56 @ 0x38
|
|
8001cd6: 431a orrs r2, r3
|
|
8001cd8: 687b ldr r3, [r7, #4]
|
|
8001cda: 6a1b ldr r3, [r3, #32]
|
|
8001cdc: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8001ce0: ea42 0103 orr.w r1, r2, r3
|
|
8001ce4: 687b ldr r3, [r7, #4]
|
|
8001ce6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001ce8: f403 5200 and.w r2, r3, #8192 @ 0x2000
|
|
8001cec: 687b ldr r3, [r7, #4]
|
|
8001cee: 681b ldr r3, [r3, #0]
|
|
8001cf0: 430a orrs r2, r1
|
|
8001cf2: 601a str r2, [r3, #0]
|
|
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
|
|
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
|
|
|
|
#if defined(SPI_CR2_FRF)
|
|
/* Configure : NSS management, TI Mode */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
|
|
8001cf4: 687b ldr r3, [r7, #4]
|
|
8001cf6: 699b ldr r3, [r3, #24]
|
|
8001cf8: 0c1b lsrs r3, r3, #16
|
|
8001cfa: f003 0104 and.w r1, r3, #4
|
|
8001cfe: 687b ldr r3, [r7, #4]
|
|
8001d00: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8001d02: f003 0210 and.w r2, r3, #16
|
|
8001d06: 687b ldr r3, [r7, #4]
|
|
8001d08: 681b ldr r3, [r3, #0]
|
|
8001d0a: 430a orrs r2, r1
|
|
8001d0c: 605a str r2, [r3, #4]
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
8001d0e: 687b ldr r3, [r7, #4]
|
|
8001d10: 681b ldr r3, [r3, #0]
|
|
8001d12: 69da ldr r2, [r3, #28]
|
|
8001d14: 687b ldr r3, [r7, #4]
|
|
8001d16: 681b ldr r3, [r3, #0]
|
|
8001d18: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8001d1c: 61da str r2, [r3, #28]
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8001d1e: 687b ldr r3, [r7, #4]
|
|
8001d20: 2200 movs r2, #0
|
|
8001d22: 655a str r2, [r3, #84] @ 0x54
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8001d24: 687b ldr r3, [r7, #4]
|
|
8001d26: 2201 movs r2, #1
|
|
8001d28: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
|
|
return HAL_OK;
|
|
8001d2c: 2300 movs r3, #0
|
|
}
|
|
8001d2e: 4618 mov r0, r3
|
|
8001d30: 3708 adds r7, #8
|
|
8001d32: 46bd mov sp, r7
|
|
8001d34: bd80 pop {r7, pc}
|
|
|
|
08001d36 <HAL_SPI_Transmit>:
|
|
* @param Size amount of data elements (u8 or u16) to be sent
|
|
* @param Timeout Timeout duration in ms
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8001d36: b580 push {r7, lr}
|
|
8001d38: b088 sub sp, #32
|
|
8001d3a: af00 add r7, sp, #0
|
|
8001d3c: 60f8 str r0, [r7, #12]
|
|
8001d3e: 60b9 str r1, [r7, #8]
|
|
8001d40: 603b str r3, [r7, #0]
|
|
8001d42: 4613 mov r3, r2
|
|
8001d44: 80fb strh r3, [r7, #6]
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8001d46: f7fe ff33 bl 8000bb0 <HAL_GetTick>
|
|
8001d4a: 61f8 str r0, [r7, #28]
|
|
initial_TxXferCount = Size;
|
|
8001d4c: 88fb ldrh r3, [r7, #6]
|
|
8001d4e: 837b strh r3, [r7, #26]
|
|
|
|
if (hspi->State != HAL_SPI_STATE_READY)
|
|
8001d50: 68fb ldr r3, [r7, #12]
|
|
8001d52: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
|
|
8001d56: b2db uxtb r3, r3
|
|
8001d58: 2b01 cmp r3, #1
|
|
8001d5a: d001 beq.n 8001d60 <HAL_SPI_Transmit+0x2a>
|
|
{
|
|
return HAL_BUSY;
|
|
8001d5c: 2302 movs r3, #2
|
|
8001d5e: e12a b.n 8001fb6 <HAL_SPI_Transmit+0x280>
|
|
}
|
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8001d60: 68bb ldr r3, [r7, #8]
|
|
8001d62: 2b00 cmp r3, #0
|
|
8001d64: d002 beq.n 8001d6c <HAL_SPI_Transmit+0x36>
|
|
8001d66: 88fb ldrh r3, [r7, #6]
|
|
8001d68: 2b00 cmp r3, #0
|
|
8001d6a: d101 bne.n 8001d70 <HAL_SPI_Transmit+0x3a>
|
|
{
|
|
return HAL_ERROR;
|
|
8001d6c: 2301 movs r3, #1
|
|
8001d6e: e122 b.n 8001fb6 <HAL_SPI_Transmit+0x280>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
8001d70: 68fb ldr r3, [r7, #12]
|
|
8001d72: f893 3050 ldrb.w r3, [r3, #80] @ 0x50
|
|
8001d76: 2b01 cmp r3, #1
|
|
8001d78: d101 bne.n 8001d7e <HAL_SPI_Transmit+0x48>
|
|
8001d7a: 2302 movs r3, #2
|
|
8001d7c: e11b b.n 8001fb6 <HAL_SPI_Transmit+0x280>
|
|
8001d7e: 68fb ldr r3, [r7, #12]
|
|
8001d80: 2201 movs r2, #1
|
|
8001d82: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
|
|
/* Set the transaction information */
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX;
|
|
8001d86: 68fb ldr r3, [r7, #12]
|
|
8001d88: 2203 movs r2, #3
|
|
8001d8a: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8001d8e: 68fb ldr r3, [r7, #12]
|
|
8001d90: 2200 movs r2, #0
|
|
8001d92: 655a str r2, [r3, #84] @ 0x54
|
|
hspi->pTxBuffPtr = (const uint8_t *)pData;
|
|
8001d94: 68fb ldr r3, [r7, #12]
|
|
8001d96: 68ba ldr r2, [r7, #8]
|
|
8001d98: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->TxXferSize = Size;
|
|
8001d9a: 68fb ldr r3, [r7, #12]
|
|
8001d9c: 88fa ldrh r2, [r7, #6]
|
|
8001d9e: 869a strh r2, [r3, #52] @ 0x34
|
|
hspi->TxXferCount = Size;
|
|
8001da0: 68fb ldr r3, [r7, #12]
|
|
8001da2: 88fa ldrh r2, [r7, #6]
|
|
8001da4: 86da strh r2, [r3, #54] @ 0x36
|
|
|
|
/*Init field not used in handle to zero */
|
|
hspi->pRxBuffPtr = (uint8_t *)NULL;
|
|
8001da6: 68fb ldr r3, [r7, #12]
|
|
8001da8: 2200 movs r2, #0
|
|
8001daa: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->RxXferSize = 0U;
|
|
8001dac: 68fb ldr r3, [r7, #12]
|
|
8001dae: 2200 movs r2, #0
|
|
8001db0: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->RxXferCount = 0U;
|
|
8001db2: 68fb ldr r3, [r7, #12]
|
|
8001db4: 2200 movs r2, #0
|
|
8001db6: 87da strh r2, [r3, #62] @ 0x3e
|
|
hspi->TxISR = NULL;
|
|
8001db8: 68fb ldr r3, [r7, #12]
|
|
8001dba: 2200 movs r2, #0
|
|
8001dbc: 645a str r2, [r3, #68] @ 0x44
|
|
hspi->RxISR = NULL;
|
|
8001dbe: 68fb ldr r3, [r7, #12]
|
|
8001dc0: 2200 movs r2, #0
|
|
8001dc2: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Configure communication direction : 1Line */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
8001dc4: 68fb ldr r3, [r7, #12]
|
|
8001dc6: 689b ldr r3, [r3, #8]
|
|
8001dc8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8001dcc: d10f bne.n 8001dee <HAL_SPI_Transmit+0xb8>
|
|
{
|
|
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8001dce: 68fb ldr r3, [r7, #12]
|
|
8001dd0: 681b ldr r3, [r3, #0]
|
|
8001dd2: 681a ldr r2, [r3, #0]
|
|
8001dd4: 68fb ldr r3, [r7, #12]
|
|
8001dd6: 681b ldr r3, [r3, #0]
|
|
8001dd8: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8001ddc: 601a str r2, [r3, #0]
|
|
SPI_1LINE_TX(hspi);
|
|
8001dde: 68fb ldr r3, [r7, #12]
|
|
8001de0: 681b ldr r3, [r3, #0]
|
|
8001de2: 681a ldr r2, [r3, #0]
|
|
8001de4: 68fb ldr r3, [r7, #12]
|
|
8001de6: 681b ldr r3, [r3, #0]
|
|
8001de8: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8001dec: 601a str r2, [r3, #0]
|
|
SPI_RESET_CRC(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
8001dee: 68fb ldr r3, [r7, #12]
|
|
8001df0: 681b ldr r3, [r3, #0]
|
|
8001df2: 681b ldr r3, [r3, #0]
|
|
8001df4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8001df8: 2b40 cmp r3, #64 @ 0x40
|
|
8001dfa: d007 beq.n 8001e0c <HAL_SPI_Transmit+0xd6>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
8001dfc: 68fb ldr r3, [r7, #12]
|
|
8001dfe: 681b ldr r3, [r3, #0]
|
|
8001e00: 681a ldr r2, [r3, #0]
|
|
8001e02: 68fb ldr r3, [r7, #12]
|
|
8001e04: 681b ldr r3, [r3, #0]
|
|
8001e06: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8001e0a: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Transmit data in 16 Bit mode */
|
|
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
|
|
8001e0c: 68fb ldr r3, [r7, #12]
|
|
8001e0e: 68db ldr r3, [r3, #12]
|
|
8001e10: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8001e14: d152 bne.n 8001ebc <HAL_SPI_Transmit+0x186>
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
8001e16: 68fb ldr r3, [r7, #12]
|
|
8001e18: 685b ldr r3, [r3, #4]
|
|
8001e1a: 2b00 cmp r3, #0
|
|
8001e1c: d002 beq.n 8001e24 <HAL_SPI_Transmit+0xee>
|
|
8001e1e: 8b7b ldrh r3, [r7, #26]
|
|
8001e20: 2b01 cmp r3, #1
|
|
8001e22: d145 bne.n 8001eb0 <HAL_SPI_Transmit+0x17a>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
8001e24: 68fb ldr r3, [r7, #12]
|
|
8001e26: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001e28: 881a ldrh r2, [r3, #0]
|
|
8001e2a: 68fb ldr r3, [r7, #12]
|
|
8001e2c: 681b ldr r3, [r3, #0]
|
|
8001e2e: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8001e30: 68fb ldr r3, [r7, #12]
|
|
8001e32: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001e34: 1c9a adds r2, r3, #2
|
|
8001e36: 68fb ldr r3, [r7, #12]
|
|
8001e38: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->TxXferCount--;
|
|
8001e3a: 68fb ldr r3, [r7, #12]
|
|
8001e3c: 8edb ldrh r3, [r3, #54] @ 0x36
|
|
8001e3e: b29b uxth r3, r3
|
|
8001e40: 3b01 subs r3, #1
|
|
8001e42: b29a uxth r2, r3
|
|
8001e44: 68fb ldr r3, [r7, #12]
|
|
8001e46: 86da strh r2, [r3, #54] @ 0x36
|
|
}
|
|
/* Transmit data in 16 Bit mode */
|
|
while (hspi->TxXferCount > 0U)
|
|
8001e48: e032 b.n 8001eb0 <HAL_SPI_Transmit+0x17a>
|
|
{
|
|
/* Wait until TXE flag is set to send data */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
|
|
8001e4a: 68fb ldr r3, [r7, #12]
|
|
8001e4c: 681b ldr r3, [r3, #0]
|
|
8001e4e: 689b ldr r3, [r3, #8]
|
|
8001e50: f003 0302 and.w r3, r3, #2
|
|
8001e54: 2b02 cmp r3, #2
|
|
8001e56: d112 bne.n 8001e7e <HAL_SPI_Transmit+0x148>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
8001e58: 68fb ldr r3, [r7, #12]
|
|
8001e5a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001e5c: 881a ldrh r2, [r3, #0]
|
|
8001e5e: 68fb ldr r3, [r7, #12]
|
|
8001e60: 681b ldr r3, [r3, #0]
|
|
8001e62: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8001e64: 68fb ldr r3, [r7, #12]
|
|
8001e66: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001e68: 1c9a adds r2, r3, #2
|
|
8001e6a: 68fb ldr r3, [r7, #12]
|
|
8001e6c: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->TxXferCount--;
|
|
8001e6e: 68fb ldr r3, [r7, #12]
|
|
8001e70: 8edb ldrh r3, [r3, #54] @ 0x36
|
|
8001e72: b29b uxth r3, r3
|
|
8001e74: 3b01 subs r3, #1
|
|
8001e76: b29a uxth r2, r3
|
|
8001e78: 68fb ldr r3, [r7, #12]
|
|
8001e7a: 86da strh r2, [r3, #54] @ 0x36
|
|
8001e7c: e018 b.n 8001eb0 <HAL_SPI_Transmit+0x17a>
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
8001e7e: f7fe fe97 bl 8000bb0 <HAL_GetTick>
|
|
8001e82: 4602 mov r2, r0
|
|
8001e84: 69fb ldr r3, [r7, #28]
|
|
8001e86: 1ad3 subs r3, r2, r3
|
|
8001e88: 683a ldr r2, [r7, #0]
|
|
8001e8a: 429a cmp r2, r3
|
|
8001e8c: d803 bhi.n 8001e96 <HAL_SPI_Transmit+0x160>
|
|
8001e8e: 683b ldr r3, [r7, #0]
|
|
8001e90: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8001e94: d102 bne.n 8001e9c <HAL_SPI_Transmit+0x166>
|
|
8001e96: 683b ldr r3, [r7, #0]
|
|
8001e98: 2b00 cmp r3, #0
|
|
8001e9a: d109 bne.n 8001eb0 <HAL_SPI_Transmit+0x17a>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8001e9c: 68fb ldr r3, [r7, #12]
|
|
8001e9e: 2201 movs r2, #1
|
|
8001ea0: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
__HAL_UNLOCK(hspi);
|
|
8001ea4: 68fb ldr r3, [r7, #12]
|
|
8001ea6: 2200 movs r2, #0
|
|
8001ea8: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
return HAL_TIMEOUT;
|
|
8001eac: 2303 movs r3, #3
|
|
8001eae: e082 b.n 8001fb6 <HAL_SPI_Transmit+0x280>
|
|
while (hspi->TxXferCount > 0U)
|
|
8001eb0: 68fb ldr r3, [r7, #12]
|
|
8001eb2: 8edb ldrh r3, [r3, #54] @ 0x36
|
|
8001eb4: b29b uxth r3, r3
|
|
8001eb6: 2b00 cmp r3, #0
|
|
8001eb8: d1c7 bne.n 8001e4a <HAL_SPI_Transmit+0x114>
|
|
8001eba: e053 b.n 8001f64 <HAL_SPI_Transmit+0x22e>
|
|
}
|
|
}
|
|
/* Transmit data in 8 Bit mode */
|
|
else
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
8001ebc: 68fb ldr r3, [r7, #12]
|
|
8001ebe: 685b ldr r3, [r3, #4]
|
|
8001ec0: 2b00 cmp r3, #0
|
|
8001ec2: d002 beq.n 8001eca <HAL_SPI_Transmit+0x194>
|
|
8001ec4: 8b7b ldrh r3, [r7, #26]
|
|
8001ec6: 2b01 cmp r3, #1
|
|
8001ec8: d147 bne.n 8001f5a <HAL_SPI_Transmit+0x224>
|
|
{
|
|
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
8001eca: 68fb ldr r3, [r7, #12]
|
|
8001ecc: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8001ece: 68fb ldr r3, [r7, #12]
|
|
8001ed0: 681b ldr r3, [r3, #0]
|
|
8001ed2: 330c adds r3, #12
|
|
8001ed4: 7812 ldrb r2, [r2, #0]
|
|
8001ed6: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr += sizeof(uint8_t);
|
|
8001ed8: 68fb ldr r3, [r7, #12]
|
|
8001eda: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001edc: 1c5a adds r2, r3, #1
|
|
8001ede: 68fb ldr r3, [r7, #12]
|
|
8001ee0: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->TxXferCount--;
|
|
8001ee2: 68fb ldr r3, [r7, #12]
|
|
8001ee4: 8edb ldrh r3, [r3, #54] @ 0x36
|
|
8001ee6: b29b uxth r3, r3
|
|
8001ee8: 3b01 subs r3, #1
|
|
8001eea: b29a uxth r2, r3
|
|
8001eec: 68fb ldr r3, [r7, #12]
|
|
8001eee: 86da strh r2, [r3, #54] @ 0x36
|
|
}
|
|
while (hspi->TxXferCount > 0U)
|
|
8001ef0: e033 b.n 8001f5a <HAL_SPI_Transmit+0x224>
|
|
{
|
|
/* Wait until TXE flag is set to send data */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
|
|
8001ef2: 68fb ldr r3, [r7, #12]
|
|
8001ef4: 681b ldr r3, [r3, #0]
|
|
8001ef6: 689b ldr r3, [r3, #8]
|
|
8001ef8: f003 0302 and.w r3, r3, #2
|
|
8001efc: 2b02 cmp r3, #2
|
|
8001efe: d113 bne.n 8001f28 <HAL_SPI_Transmit+0x1f2>
|
|
{
|
|
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
8001f00: 68fb ldr r3, [r7, #12]
|
|
8001f02: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8001f04: 68fb ldr r3, [r7, #12]
|
|
8001f06: 681b ldr r3, [r3, #0]
|
|
8001f08: 330c adds r3, #12
|
|
8001f0a: 7812 ldrb r2, [r2, #0]
|
|
8001f0c: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr += sizeof(uint8_t);
|
|
8001f0e: 68fb ldr r3, [r7, #12]
|
|
8001f10: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001f12: 1c5a adds r2, r3, #1
|
|
8001f14: 68fb ldr r3, [r7, #12]
|
|
8001f16: 631a str r2, [r3, #48] @ 0x30
|
|
hspi->TxXferCount--;
|
|
8001f18: 68fb ldr r3, [r7, #12]
|
|
8001f1a: 8edb ldrh r3, [r3, #54] @ 0x36
|
|
8001f1c: b29b uxth r3, r3
|
|
8001f1e: 3b01 subs r3, #1
|
|
8001f20: b29a uxth r2, r3
|
|
8001f22: 68fb ldr r3, [r7, #12]
|
|
8001f24: 86da strh r2, [r3, #54] @ 0x36
|
|
8001f26: e018 b.n 8001f5a <HAL_SPI_Transmit+0x224>
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
8001f28: f7fe fe42 bl 8000bb0 <HAL_GetTick>
|
|
8001f2c: 4602 mov r2, r0
|
|
8001f2e: 69fb ldr r3, [r7, #28]
|
|
8001f30: 1ad3 subs r3, r2, r3
|
|
8001f32: 683a ldr r2, [r7, #0]
|
|
8001f34: 429a cmp r2, r3
|
|
8001f36: d803 bhi.n 8001f40 <HAL_SPI_Transmit+0x20a>
|
|
8001f38: 683b ldr r3, [r7, #0]
|
|
8001f3a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8001f3e: d102 bne.n 8001f46 <HAL_SPI_Transmit+0x210>
|
|
8001f40: 683b ldr r3, [r7, #0]
|
|
8001f42: 2b00 cmp r3, #0
|
|
8001f44: d109 bne.n 8001f5a <HAL_SPI_Transmit+0x224>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8001f46: 68fb ldr r3, [r7, #12]
|
|
8001f48: 2201 movs r2, #1
|
|
8001f4a: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
__HAL_UNLOCK(hspi);
|
|
8001f4e: 68fb ldr r3, [r7, #12]
|
|
8001f50: 2200 movs r2, #0
|
|
8001f52: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
return HAL_TIMEOUT;
|
|
8001f56: 2303 movs r3, #3
|
|
8001f58: e02d b.n 8001fb6 <HAL_SPI_Transmit+0x280>
|
|
while (hspi->TxXferCount > 0U)
|
|
8001f5a: 68fb ldr r3, [r7, #12]
|
|
8001f5c: 8edb ldrh r3, [r3, #54] @ 0x36
|
|
8001f5e: b29b uxth r3, r3
|
|
8001f60: 2b00 cmp r3, #0
|
|
8001f62: d1c6 bne.n 8001ef2 <HAL_SPI_Transmit+0x1bc>
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
|
|
8001f64: 69fa ldr r2, [r7, #28]
|
|
8001f66: 6839 ldr r1, [r7, #0]
|
|
8001f68: 68f8 ldr r0, [r7, #12]
|
|
8001f6a: f000 f8b1 bl 80020d0 <SPI_EndRxTxTransaction>
|
|
8001f6e: 4603 mov r3, r0
|
|
8001f70: 2b00 cmp r3, #0
|
|
8001f72: d002 beq.n 8001f7a <HAL_SPI_Transmit+0x244>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
|
|
8001f74: 68fb ldr r3, [r7, #12]
|
|
8001f76: 2220 movs r2, #32
|
|
8001f78: 655a str r2, [r3, #84] @ 0x54
|
|
}
|
|
|
|
/* Clear overrun flag in 2 Lines communication mode because received is not read */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
|
|
8001f7a: 68fb ldr r3, [r7, #12]
|
|
8001f7c: 689b ldr r3, [r3, #8]
|
|
8001f7e: 2b00 cmp r3, #0
|
|
8001f80: d10a bne.n 8001f98 <HAL_SPI_Transmit+0x262>
|
|
{
|
|
__HAL_SPI_CLEAR_OVRFLAG(hspi);
|
|
8001f82: 2300 movs r3, #0
|
|
8001f84: 617b str r3, [r7, #20]
|
|
8001f86: 68fb ldr r3, [r7, #12]
|
|
8001f88: 681b ldr r3, [r3, #0]
|
|
8001f8a: 68db ldr r3, [r3, #12]
|
|
8001f8c: 617b str r3, [r7, #20]
|
|
8001f8e: 68fb ldr r3, [r7, #12]
|
|
8001f90: 681b ldr r3, [r3, #0]
|
|
8001f92: 689b ldr r3, [r3, #8]
|
|
8001f94: 617b str r3, [r7, #20]
|
|
8001f96: 697b ldr r3, [r7, #20]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8001f98: 68fb ldr r3, [r7, #12]
|
|
8001f9a: 2201 movs r2, #1
|
|
8001f9c: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
8001fa0: 68fb ldr r3, [r7, #12]
|
|
8001fa2: 2200 movs r2, #0
|
|
8001fa4: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
8001fa8: 68fb ldr r3, [r7, #12]
|
|
8001faa: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001fac: 2b00 cmp r3, #0
|
|
8001fae: d001 beq.n 8001fb4 <HAL_SPI_Transmit+0x27e>
|
|
{
|
|
return HAL_ERROR;
|
|
8001fb0: 2301 movs r3, #1
|
|
8001fb2: e000 b.n 8001fb6 <HAL_SPI_Transmit+0x280>
|
|
}
|
|
else
|
|
{
|
|
return HAL_OK;
|
|
8001fb4: 2300 movs r3, #0
|
|
}
|
|
}
|
|
8001fb6: 4618 mov r0, r3
|
|
8001fb8: 3720 adds r7, #32
|
|
8001fba: 46bd mov sp, r7
|
|
8001fbc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001fc0 <SPI_WaitFlagStateUntilTimeout>:
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8001fc0: b580 push {r7, lr}
|
|
8001fc2: b088 sub sp, #32
|
|
8001fc4: af00 add r7, sp, #0
|
|
8001fc6: 60f8 str r0, [r7, #12]
|
|
8001fc8: 60b9 str r1, [r7, #8]
|
|
8001fca: 603b str r3, [r7, #0]
|
|
8001fcc: 4613 mov r3, r2
|
|
8001fce: 71fb strb r3, [r7, #7]
|
|
__IO uint32_t count;
|
|
uint32_t tmp_timeout;
|
|
uint32_t tmp_tickstart;
|
|
|
|
/* Adjust Timeout value in case of end of transfer */
|
|
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
|
8001fd0: f7fe fdee bl 8000bb0 <HAL_GetTick>
|
|
8001fd4: 4602 mov r2, r0
|
|
8001fd6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001fd8: 1a9b subs r3, r3, r2
|
|
8001fda: 683a ldr r2, [r7, #0]
|
|
8001fdc: 4413 add r3, r2
|
|
8001fde: 61fb str r3, [r7, #28]
|
|
tmp_tickstart = HAL_GetTick();
|
|
8001fe0: f7fe fde6 bl 8000bb0 <HAL_GetTick>
|
|
8001fe4: 61b8 str r0, [r7, #24]
|
|
|
|
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
|
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
|
|
8001fe6: 4b39 ldr r3, [pc, #228] @ (80020cc <SPI_WaitFlagStateUntilTimeout+0x10c>)
|
|
8001fe8: 681b ldr r3, [r3, #0]
|
|
8001fea: 015b lsls r3, r3, #5
|
|
8001fec: 0d1b lsrs r3, r3, #20
|
|
8001fee: 69fa ldr r2, [r7, #28]
|
|
8001ff0: fb02 f303 mul.w r3, r2, r3
|
|
8001ff4: 617b str r3, [r7, #20]
|
|
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
8001ff6: e054 b.n 80020a2 <SPI_WaitFlagStateUntilTimeout+0xe2>
|
|
{
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8001ff8: 683b ldr r3, [r7, #0]
|
|
8001ffa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8001ffe: d050 beq.n 80020a2 <SPI_WaitFlagStateUntilTimeout+0xe2>
|
|
{
|
|
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
|
8002000: f7fe fdd6 bl 8000bb0 <HAL_GetTick>
|
|
8002004: 4602 mov r2, r0
|
|
8002006: 69bb ldr r3, [r7, #24]
|
|
8002008: 1ad3 subs r3, r2, r3
|
|
800200a: 69fa ldr r2, [r7, #28]
|
|
800200c: 429a cmp r2, r3
|
|
800200e: d902 bls.n 8002016 <SPI_WaitFlagStateUntilTimeout+0x56>
|
|
8002010: 69fb ldr r3, [r7, #28]
|
|
8002012: 2b00 cmp r3, #0
|
|
8002014: d13d bne.n 8002092 <SPI_WaitFlagStateUntilTimeout+0xd2>
|
|
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
|
on both master and slave sides in order to resynchronize the master
|
|
and slave for their respective CRC calculation */
|
|
|
|
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
8002016: 68fb ldr r3, [r7, #12]
|
|
8002018: 681b ldr r3, [r3, #0]
|
|
800201a: 685a ldr r2, [r3, #4]
|
|
800201c: 68fb ldr r3, [r7, #12]
|
|
800201e: 681b ldr r3, [r3, #0]
|
|
8002020: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
8002024: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
8002026: 68fb ldr r3, [r7, #12]
|
|
8002028: 685b ldr r3, [r3, #4]
|
|
800202a: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800202e: d111 bne.n 8002054 <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
8002030: 68fb ldr r3, [r7, #12]
|
|
8002032: 689b ldr r3, [r3, #8]
|
|
8002034: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8002038: d004 beq.n 8002044 <SPI_WaitFlagStateUntilTimeout+0x84>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
800203a: 68fb ldr r3, [r7, #12]
|
|
800203c: 689b ldr r3, [r3, #8]
|
|
800203e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8002042: d107 bne.n 8002054 <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8002044: 68fb ldr r3, [r7, #12]
|
|
8002046: 681b ldr r3, [r3, #0]
|
|
8002048: 681a ldr r2, [r3, #0]
|
|
800204a: 68fb ldr r3, [r7, #12]
|
|
800204c: 681b ldr r3, [r3, #0]
|
|
800204e: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8002052: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset CRC Calculation */
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
8002054: 68fb ldr r3, [r7, #12]
|
|
8002056: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002058: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
800205c: d10f bne.n 800207e <SPI_WaitFlagStateUntilTimeout+0xbe>
|
|
{
|
|
SPI_RESET_CRC(hspi);
|
|
800205e: 68fb ldr r3, [r7, #12]
|
|
8002060: 681b ldr r3, [r3, #0]
|
|
8002062: 681a ldr r2, [r3, #0]
|
|
8002064: 68fb ldr r3, [r7, #12]
|
|
8002066: 681b ldr r3, [r3, #0]
|
|
8002068: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
800206c: 601a str r2, [r3, #0]
|
|
800206e: 68fb ldr r3, [r7, #12]
|
|
8002070: 681b ldr r3, [r3, #0]
|
|
8002072: 681a ldr r2, [r3, #0]
|
|
8002074: 68fb ldr r3, [r7, #12]
|
|
8002076: 681b ldr r3, [r3, #0]
|
|
8002078: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
800207c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800207e: 68fb ldr r3, [r7, #12]
|
|
8002080: 2201 movs r2, #1
|
|
8002082: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
8002086: 68fb ldr r3, [r7, #12]
|
|
8002088: 2200 movs r2, #0
|
|
800208a: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
|
|
return HAL_TIMEOUT;
|
|
800208e: 2303 movs r3, #3
|
|
8002090: e017 b.n 80020c2 <SPI_WaitFlagStateUntilTimeout+0x102>
|
|
}
|
|
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
|
if (count == 0U)
|
|
8002092: 697b ldr r3, [r7, #20]
|
|
8002094: 2b00 cmp r3, #0
|
|
8002096: d101 bne.n 800209c <SPI_WaitFlagStateUntilTimeout+0xdc>
|
|
{
|
|
tmp_timeout = 0U;
|
|
8002098: 2300 movs r3, #0
|
|
800209a: 61fb str r3, [r7, #28]
|
|
}
|
|
count--;
|
|
800209c: 697b ldr r3, [r7, #20]
|
|
800209e: 3b01 subs r3, #1
|
|
80020a0: 617b str r3, [r7, #20]
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
80020a2: 68fb ldr r3, [r7, #12]
|
|
80020a4: 681b ldr r3, [r3, #0]
|
|
80020a6: 689a ldr r2, [r3, #8]
|
|
80020a8: 68bb ldr r3, [r7, #8]
|
|
80020aa: 4013 ands r3, r2
|
|
80020ac: 68ba ldr r2, [r7, #8]
|
|
80020ae: 429a cmp r2, r3
|
|
80020b0: bf0c ite eq
|
|
80020b2: 2301 moveq r3, #1
|
|
80020b4: 2300 movne r3, #0
|
|
80020b6: b2db uxtb r3, r3
|
|
80020b8: 461a mov r2, r3
|
|
80020ba: 79fb ldrb r3, [r7, #7]
|
|
80020bc: 429a cmp r2, r3
|
|
80020be: d19b bne.n 8001ff8 <SPI_WaitFlagStateUntilTimeout+0x38>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
80020c0: 2300 movs r3, #0
|
|
}
|
|
80020c2: 4618 mov r0, r3
|
|
80020c4: 3720 adds r7, #32
|
|
80020c6: 46bd mov sp, r7
|
|
80020c8: bd80 pop {r7, pc}
|
|
80020ca: bf00 nop
|
|
80020cc: 20000000 .word 0x20000000
|
|
|
|
080020d0 <SPI_EndRxTxTransaction>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80020d0: b580 push {r7, lr}
|
|
80020d2: b088 sub sp, #32
|
|
80020d4: af02 add r7, sp, #8
|
|
80020d6: 60f8 str r0, [r7, #12]
|
|
80020d8: 60b9 str r1, [r7, #8]
|
|
80020da: 607a str r2, [r7, #4]
|
|
/* Wait until TXE flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK)
|
|
80020dc: 687b ldr r3, [r7, #4]
|
|
80020de: 9300 str r3, [sp, #0]
|
|
80020e0: 68bb ldr r3, [r7, #8]
|
|
80020e2: 2201 movs r2, #1
|
|
80020e4: 2102 movs r1, #2
|
|
80020e6: 68f8 ldr r0, [r7, #12]
|
|
80020e8: f7ff ff6a bl 8001fc0 <SPI_WaitFlagStateUntilTimeout>
|
|
80020ec: 4603 mov r3, r0
|
|
80020ee: 2b00 cmp r3, #0
|
|
80020f0: d007 beq.n 8002102 <SPI_EndRxTxTransaction+0x32>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
80020f2: 68fb ldr r3, [r7, #12]
|
|
80020f4: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80020f6: f043 0220 orr.w r2, r3, #32
|
|
80020fa: 68fb ldr r3, [r7, #12]
|
|
80020fc: 655a str r2, [r3, #84] @ 0x54
|
|
return HAL_TIMEOUT;
|
|
80020fe: 2303 movs r3, #3
|
|
8002100: e032 b.n 8002168 <SPI_EndRxTxTransaction+0x98>
|
|
}
|
|
|
|
/* Timeout in us */
|
|
__IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
|
|
8002102: 4b1b ldr r3, [pc, #108] @ (8002170 <SPI_EndRxTxTransaction+0xa0>)
|
|
8002104: 681b ldr r3, [r3, #0]
|
|
8002106: 4a1b ldr r2, [pc, #108] @ (8002174 <SPI_EndRxTxTransaction+0xa4>)
|
|
8002108: fba2 2303 umull r2, r3, r2, r3
|
|
800210c: 0d5b lsrs r3, r3, #21
|
|
800210e: f44f 727a mov.w r2, #1000 @ 0x3e8
|
|
8002112: fb02 f303 mul.w r3, r2, r3
|
|
8002116: 617b str r3, [r7, #20]
|
|
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
8002118: 68fb ldr r3, [r7, #12]
|
|
800211a: 685b ldr r3, [r3, #4]
|
|
800211c: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8002120: d112 bne.n 8002148 <SPI_EndRxTxTransaction+0x78>
|
|
{
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8002122: 687b ldr r3, [r7, #4]
|
|
8002124: 9300 str r3, [sp, #0]
|
|
8002126: 68bb ldr r3, [r7, #8]
|
|
8002128: 2200 movs r2, #0
|
|
800212a: 2180 movs r1, #128 @ 0x80
|
|
800212c: 68f8 ldr r0, [r7, #12]
|
|
800212e: f7ff ff47 bl 8001fc0 <SPI_WaitFlagStateUntilTimeout>
|
|
8002132: 4603 mov r3, r0
|
|
8002134: 2b00 cmp r3, #0
|
|
8002136: d016 beq.n 8002166 <SPI_EndRxTxTransaction+0x96>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
8002138: 68fb ldr r3, [r7, #12]
|
|
800213a: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800213c: f043 0220 orr.w r2, r3, #32
|
|
8002140: 68fb ldr r3, [r7, #12]
|
|
8002142: 655a str r2, [r3, #84] @ 0x54
|
|
return HAL_TIMEOUT;
|
|
8002144: 2303 movs r3, #3
|
|
8002146: e00f b.n 8002168 <SPI_EndRxTxTransaction+0x98>
|
|
* User have to calculate the timeout value to fit with the time of 1 byte transfer.
|
|
* This time is directly link with the SPI clock from Master device.
|
|
*/
|
|
do
|
|
{
|
|
if (count == 0U)
|
|
8002148: 697b ldr r3, [r7, #20]
|
|
800214a: 2b00 cmp r3, #0
|
|
800214c: d00a beq.n 8002164 <SPI_EndRxTxTransaction+0x94>
|
|
{
|
|
break;
|
|
}
|
|
count--;
|
|
800214e: 697b ldr r3, [r7, #20]
|
|
8002150: 3b01 subs r3, #1
|
|
8002152: 617b str r3, [r7, #20]
|
|
} while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
|
|
8002154: 68fb ldr r3, [r7, #12]
|
|
8002156: 681b ldr r3, [r3, #0]
|
|
8002158: 689b ldr r3, [r3, #8]
|
|
800215a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800215e: 2b80 cmp r3, #128 @ 0x80
|
|
8002160: d0f2 beq.n 8002148 <SPI_EndRxTxTransaction+0x78>
|
|
8002162: e000 b.n 8002166 <SPI_EndRxTxTransaction+0x96>
|
|
break;
|
|
8002164: bf00 nop
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002166: 2300 movs r3, #0
|
|
}
|
|
8002168: 4618 mov r0, r3
|
|
800216a: 3718 adds r7, #24
|
|
800216c: 46bd mov sp, r7
|
|
800216e: bd80 pop {r7, pc}
|
|
8002170: 20000000 .word 0x20000000
|
|
8002174: 165e9f81 .word 0x165e9f81
|
|
|
|
08002178 <writecommand>:
|
|
* Input : command byte to write
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void writecommand(unsigned char cmdout)
|
|
{
|
|
8002178: b580 push {r7, lr}
|
|
800217a: b082 sub sp, #8
|
|
800217c: af00 add r7, sp, #0
|
|
800217e: 4603 mov r3, r0
|
|
8002180: 71fb strb r3, [r7, #7]
|
|
|
|
//HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); // HAL_ERROR
|
|
|
|
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1
|
|
|
|
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN << 16 ;// D/nC = 0 commande
|
|
8002182: 4b0a ldr r3, [pc, #40] @ (80021ac <writecommand+0x34>)
|
|
8002184: f44f 2280 mov.w r2, #262144 @ 0x40000
|
|
8002188: 619a str r2, [r3, #24]
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0
|
|
800218a: 4b08 ldr r3, [pc, #32] @ (80021ac <writecommand+0x34>)
|
|
800218c: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
8002190: 619a str r2, [r3, #24]
|
|
HAL_SPI_Transmit(&hspi1, &cmdout, 1, 100); //
|
|
8002192: 1df9 adds r1, r7, #7
|
|
8002194: 2364 movs r3, #100 @ 0x64
|
|
8002196: 2201 movs r2, #1
|
|
8002198: 4805 ldr r0, [pc, #20] @ (80021b0 <writecommand+0x38>)
|
|
800219a: f7ff fdcc bl 8001d36 <HAL_SPI_Transmit>
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
|
|
800219e: 4b03 ldr r3, [pc, #12] @ (80021ac <writecommand+0x34>)
|
|
80021a0: 2202 movs r2, #2
|
|
80021a2: 619a str r2, [r3, #24]
|
|
|
|
}
|
|
80021a4: bf00 nop
|
|
80021a6: 3708 adds r7, #8
|
|
80021a8: 46bd mov sp, r7
|
|
80021aa: bd80 pop {r7, pc}
|
|
80021ac: 40020800 .word 0x40020800
|
|
80021b0: 20000078 .word 0x20000078
|
|
|
|
080021b4 <writedata>:
|
|
* Input : data byte to write
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void writedata(unsigned char dataout)
|
|
{
|
|
80021b4: b580 push {r7, lr}
|
|
80021b6: b082 sub sp, #8
|
|
80021b8: af00 add r7, sp, #0
|
|
80021ba: 4603 mov r3, r0
|
|
80021bc: 71fb strb r3, [r7, #7]
|
|
|
|
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1
|
|
|
|
|
|
|
|
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
|
|
80021be: 4b0a ldr r3, [pc, #40] @ (80021e8 <writedata+0x34>)
|
|
80021c0: 2204 movs r2, #4
|
|
80021c2: 619a str r2, [r3, #24]
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN << 16 ;// nCS = 0
|
|
80021c4: 4b08 ldr r3, [pc, #32] @ (80021e8 <writedata+0x34>)
|
|
80021c6: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
80021ca: 619a str r2, [r3, #24]
|
|
HAL_SPI_Transmit(&hspi1, &dataout, 1, 100); //
|
|
80021cc: 1df9 adds r1, r7, #7
|
|
80021ce: 2364 movs r3, #100 @ 0x64
|
|
80021d0: 2201 movs r2, #1
|
|
80021d2: 4806 ldr r0, [pc, #24] @ (80021ec <writedata+0x38>)
|
|
80021d4: f7ff fdaf bl 8001d36 <HAL_SPI_Transmit>
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
|
|
80021d8: 4b03 ldr r3, [pc, #12] @ (80021e8 <writedata+0x34>)
|
|
80021da: 2202 movs r2, #2
|
|
80021dc: 619a str r2, [r3, #24]
|
|
|
|
}
|
|
80021de: bf00 nop
|
|
80021e0: 3708 adds r7, #8
|
|
80021e2: 46bd mov sp, r7
|
|
80021e4: bd80 pop {r7, pc}
|
|
80021e6: bf00 nop
|
|
80021e8: 40020800 .word 0x40020800
|
|
80021ec: 20000078 .word 0x20000078
|
|
|
|
080021f0 <commandList>:
|
|
* Input : addr = pointer on command byte array
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void commandList(const uint8_t *addr)
|
|
{
|
|
80021f0: b580 push {r7, lr}
|
|
80021f2: b084 sub sp, #16
|
|
80021f4: af00 add r7, sp, #0
|
|
80021f6: 6078 str r0, [r7, #4]
|
|
uint8_t numCommands, numArgs;
|
|
uint16_t ms;
|
|
|
|
numCommands = pgm_read_byte(addr++); // Number of commands to follow
|
|
80021f8: 687b ldr r3, [r7, #4]
|
|
80021fa: 1c5a adds r2, r3, #1
|
|
80021fc: 607a str r2, [r7, #4]
|
|
80021fe: 781b ldrb r3, [r3, #0]
|
|
8002200: 73fb strb r3, [r7, #15]
|
|
while(numCommands--)
|
|
8002202: e033 b.n 800226c <commandList+0x7c>
|
|
{ // For each command...
|
|
writecommand(pgm_read_byte(addr++)); // Read, issue command
|
|
8002204: 687b ldr r3, [r7, #4]
|
|
8002206: 1c5a adds r2, r3, #1
|
|
8002208: 607a str r2, [r7, #4]
|
|
800220a: 781b ldrb r3, [r3, #0]
|
|
800220c: 4618 mov r0, r3
|
|
800220e: f7ff ffb3 bl 8002178 <writecommand>
|
|
numArgs = pgm_read_byte(addr++); // Number of args to follow
|
|
8002212: 687b ldr r3, [r7, #4]
|
|
8002214: 1c5a adds r2, r3, #1
|
|
8002216: 607a str r2, [r7, #4]
|
|
8002218: 781b ldrb r3, [r3, #0]
|
|
800221a: 73bb strb r3, [r7, #14]
|
|
ms = numArgs & DELAY; // If hibit set, delay follows args
|
|
800221c: 7bbb ldrb r3, [r7, #14]
|
|
800221e: b29b uxth r3, r3
|
|
8002220: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002224: 81bb strh r3, [r7, #12]
|
|
numArgs &= ~DELAY; // Mask out delay bit
|
|
8002226: 7bbb ldrb r3, [r7, #14]
|
|
8002228: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
800222c: 73bb strb r3, [r7, #14]
|
|
while(numArgs--) { // For each argument...
|
|
800222e: e006 b.n 800223e <commandList+0x4e>
|
|
writedata(pgm_read_byte(addr++)); // Read, issue argument
|
|
8002230: 687b ldr r3, [r7, #4]
|
|
8002232: 1c5a adds r2, r3, #1
|
|
8002234: 607a str r2, [r7, #4]
|
|
8002236: 781b ldrb r3, [r3, #0]
|
|
8002238: 4618 mov r0, r3
|
|
800223a: f7ff ffbb bl 80021b4 <writedata>
|
|
while(numArgs--) { // For each argument...
|
|
800223e: 7bbb ldrb r3, [r7, #14]
|
|
8002240: 1e5a subs r2, r3, #1
|
|
8002242: 73ba strb r2, [r7, #14]
|
|
8002244: 2b00 cmp r3, #0
|
|
8002246: d1f3 bne.n 8002230 <commandList+0x40>
|
|
}
|
|
|
|
if(ms) {
|
|
8002248: 89bb ldrh r3, [r7, #12]
|
|
800224a: 2b00 cmp r3, #0
|
|
800224c: d00e beq.n 800226c <commandList+0x7c>
|
|
ms = pgm_read_byte(addr++); // Read post-command delay time (ms)
|
|
800224e: 687b ldr r3, [r7, #4]
|
|
8002250: 1c5a adds r2, r3, #1
|
|
8002252: 607a str r2, [r7, #4]
|
|
8002254: 781b ldrb r3, [r3, #0]
|
|
8002256: 81bb strh r3, [r7, #12]
|
|
if(ms == 255) ms = 500; // If 255, delay for 500 ms
|
|
8002258: 89bb ldrh r3, [r7, #12]
|
|
800225a: 2bff cmp r3, #255 @ 0xff
|
|
800225c: d102 bne.n 8002264 <commandList+0x74>
|
|
800225e: f44f 73fa mov.w r3, #500 @ 0x1f4
|
|
8002262: 81bb strh r3, [r7, #12]
|
|
HAL_Delay(500);
|
|
8002264: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
8002268: f7fe fcac bl 8000bc4 <HAL_Delay>
|
|
while(numCommands--)
|
|
800226c: 7bfb ldrb r3, [r7, #15]
|
|
800226e: 1e5a subs r2, r3, #1
|
|
8002270: 73fa strb r2, [r7, #15]
|
|
8002272: 2b00 cmp r3, #0
|
|
8002274: d1c6 bne.n 8002204 <commandList+0x14>
|
|
}
|
|
}
|
|
}
|
|
8002276: bf00 nop
|
|
8002278: bf00 nop
|
|
800227a: 3710 adds r7, #16
|
|
800227c: 46bd mov sp, r7
|
|
800227e: bd80 pop {r7, pc}
|
|
|
|
08002280 <setAddrWindow>:
|
|
* : y2 vertical position = y1 to ST7735_TFTHEIGHT-1-y1
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void setAddrWindow(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1)
|
|
{
|
|
8002280: b590 push {r4, r7, lr}
|
|
8002282: b083 sub sp, #12
|
|
8002284: af00 add r7, sp, #0
|
|
8002286: 4604 mov r4, r0
|
|
8002288: 4608 mov r0, r1
|
|
800228a: 4611 mov r1, r2
|
|
800228c: 461a mov r2, r3
|
|
800228e: 4623 mov r3, r4
|
|
8002290: 71fb strb r3, [r7, #7]
|
|
8002292: 4603 mov r3, r0
|
|
8002294: 71bb strb r3, [r7, #6]
|
|
8002296: 460b mov r3, r1
|
|
8002298: 717b strb r3, [r7, #5]
|
|
800229a: 4613 mov r3, r2
|
|
800229c: 713b strb r3, [r7, #4]
|
|
|
|
writecommand(ST7735_CASET); // Column addr set
|
|
800229e: 202a movs r0, #42 @ 0x2a
|
|
80022a0: f7ff ff6a bl 8002178 <writecommand>
|
|
writedata(0x00);
|
|
80022a4: 2000 movs r0, #0
|
|
80022a6: f7ff ff85 bl 80021b4 <writedata>
|
|
writedata(x0); // XSTART
|
|
80022aa: 79fb ldrb r3, [r7, #7]
|
|
80022ac: 4618 mov r0, r3
|
|
80022ae: f7ff ff81 bl 80021b4 <writedata>
|
|
writedata(0x00);
|
|
80022b2: 2000 movs r0, #0
|
|
80022b4: f7ff ff7e bl 80021b4 <writedata>
|
|
writedata(x1); // XEND
|
|
80022b8: 797b ldrb r3, [r7, #5]
|
|
80022ba: 4618 mov r0, r3
|
|
80022bc: f7ff ff7a bl 80021b4 <writedata>
|
|
|
|
writecommand(ST7735_RASET); // Row addr set
|
|
80022c0: 202b movs r0, #43 @ 0x2b
|
|
80022c2: f7ff ff59 bl 8002178 <writecommand>
|
|
writedata(0x00);
|
|
80022c6: 2000 movs r0, #0
|
|
80022c8: f7ff ff74 bl 80021b4 <writedata>
|
|
writedata(y0); // YSTART
|
|
80022cc: 79bb ldrb r3, [r7, #6]
|
|
80022ce: 4618 mov r0, r3
|
|
80022d0: f7ff ff70 bl 80021b4 <writedata>
|
|
writedata(0x00);
|
|
80022d4: 2000 movs r0, #0
|
|
80022d6: f7ff ff6d bl 80021b4 <writedata>
|
|
writedata(y1); // YEND
|
|
80022da: 793b ldrb r3, [r7, #4]
|
|
80022dc: 4618 mov r0, r3
|
|
80022de: f7ff ff69 bl 80021b4 <writedata>
|
|
|
|
writecommand(ST7735_RAMWR); // write to RAM
|
|
80022e2: 202c movs r0, #44 @ 0x2c
|
|
80022e4: f7ff ff48 bl 8002178 <writecommand>
|
|
}
|
|
80022e8: bf00 nop
|
|
80022ea: 370c adds r7, #12
|
|
80022ec: 46bd mov sp, r7
|
|
80022ee: bd90 pop {r4, r7, pc}
|
|
|
|
080022f0 <init_TFT>:
|
|
* Input : None
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void init_TFT( void)
|
|
{
|
|
80022f0: b580 push {r7, lr}
|
|
80022f2: b082 sub sp, #8
|
|
80022f4: af02 add r7, sp, #8
|
|
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_13, 1); // nRESET = 1
|
|
attend_500ms();
|
|
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/
|
|
|
|
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // DC= 1
|
|
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
|
|
80022f6: 4b1e ldr r3, [pc, #120] @ (8002370 <init_TFT+0x80>)
|
|
80022f8: 2204 movs r2, #4
|
|
80022fa: 619a str r2, [r3, #24]
|
|
ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1
|
|
80022fc: 4b1d ldr r3, [pc, #116] @ (8002374 <init_TFT+0x84>)
|
|
80022fe: 2204 movs r2, #4
|
|
8002300: 619a str r2, [r3, #24]
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0
|
|
8002302: 4b1b ldr r3, [pc, #108] @ (8002370 <init_TFT+0x80>)
|
|
8002304: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
8002308: 619a str r2, [r3, #24]
|
|
HAL_Delay(500);
|
|
800230a: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
800230e: f7fe fc59 bl 8000bc4 <HAL_Delay>
|
|
ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN<<16;// nRESET = 0
|
|
8002312: 4b18 ldr r3, [pc, #96] @ (8002374 <init_TFT+0x84>)
|
|
8002314: f44f 2280 mov.w r2, #262144 @ 0x40000
|
|
8002318: 619a str r2, [r3, #24]
|
|
HAL_Delay(500);
|
|
800231a: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
800231e: f7fe fc51 bl 8000bc4 <HAL_Delay>
|
|
ST7735_RST_PORT->BSRR = (uint32_t)ST7735_RST_PIN;// nRESET = 1
|
|
8002322: 4b14 ldr r3, [pc, #80] @ (8002374 <init_TFT+0x84>)
|
|
8002324: 2204 movs r2, #4
|
|
8002326: 619a str r2, [r3, #24]
|
|
HAL_Delay(500);
|
|
8002328: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
800232c: f7fe fc4a bl 8000bc4 <HAL_Delay>
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
|
|
8002330: 4b0f ldr r3, [pc, #60] @ (8002370 <init_TFT+0x80>)
|
|
8002332: 2202 movs r2, #2
|
|
8002334: 619a str r2, [r3, #24]
|
|
|
|
// initialization instruction
|
|
commandList(Rcmd1);
|
|
8002336: 4810 ldr r0, [pc, #64] @ (8002378 <init_TFT+0x88>)
|
|
8002338: f7ff ff5a bl 80021f0 <commandList>
|
|
commandList(Rcmd2red);
|
|
800233c: 480f ldr r0, [pc, #60] @ (800237c <init_TFT+0x8c>)
|
|
800233e: f7ff ff57 bl 80021f0 <commandList>
|
|
commandList(Rcmd3);
|
|
8002342: 480f ldr r0, [pc, #60] @ (8002380 <init_TFT+0x90>)
|
|
8002344: f7ff ff54 bl 80021f0 <commandList>
|
|
|
|
writecommand(ST7735_MADCTL);
|
|
8002348: 2036 movs r0, #54 @ 0x36
|
|
800234a: f7ff ff15 bl 8002178 <writecommand>
|
|
writedata(0xC0);
|
|
800234e: 20c0 movs r0, #192 @ 0xc0
|
|
8002350: f7ff ff30 bl 80021b4 <writedata>
|
|
|
|
// all display background is black
|
|
fillRect_TFT(0, 0, ST7735_TFTWIDTH, ST7735_TFTHEIGHT_18, ST7735_BLACK);
|
|
8002354: 2300 movs r3, #0
|
|
8002356: 9300 str r3, [sp, #0]
|
|
8002358: 23a0 movs r3, #160 @ 0xa0
|
|
800235a: 2280 movs r2, #128 @ 0x80
|
|
800235c: 2100 movs r1, #0
|
|
800235e: 2000 movs r0, #0
|
|
8002360: f000 f856 bl 8002410 <fillRect_TFT>
|
|
|
|
// display LOGO
|
|
displayLogo_TFT();
|
|
8002364: f000 f998 bl 8002698 <displayLogo_TFT>
|
|
}
|
|
8002368: bf00 nop
|
|
800236a: 46bd mov sp, r7
|
|
800236c: bd80 pop {r7, pc}
|
|
800236e: bf00 nop
|
|
8002370: 40020800 .word 0x40020800
|
|
8002374: 40020c00 .word 0x40020c00
|
|
8002378: 080029a8 .word 0x080029a8
|
|
800237c: 080029e4 .word 0x080029e4
|
|
8002380: 080029f4 .word 0x080029f4
|
|
|
|
08002384 <drawPixel_TFT>:
|
|
* : color = 16bits RGB=(565) soit RRRRRGGGGGGGBBBBB
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void drawPixel_TFT(uint16_t x, uint16_t y, uint16_t color)
|
|
{
|
|
8002384: b580 push {r7, lr}
|
|
8002386: b084 sub sp, #16
|
|
8002388: af00 add r7, sp, #0
|
|
800238a: 4603 mov r3, r0
|
|
800238c: 80fb strh r3, [r7, #6]
|
|
800238e: 460b mov r3, r1
|
|
8002390: 80bb strh r3, [r7, #4]
|
|
8002392: 4613 mov r3, r2
|
|
8002394: 807b strh r3, [r7, #2]
|
|
uint8_t hi, lo;
|
|
|
|
// rudimentary clipping (drawChar w/big text requires this)
|
|
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
|
|
8002396: 88fb ldrh r3, [r7, #6]
|
|
8002398: 2b7f cmp r3, #127 @ 0x7f
|
|
800239a: d831 bhi.n 8002400 <drawPixel_TFT+0x7c>
|
|
800239c: 88bb ldrh r3, [r7, #4]
|
|
800239e: 2b9f cmp r3, #159 @ 0x9f
|
|
80023a0: d82e bhi.n 8002400 <drawPixel_TFT+0x7c>
|
|
|
|
setAddrWindow(x, y, x+1, y+1);
|
|
80023a2: 88fb ldrh r3, [r7, #6]
|
|
80023a4: b2d8 uxtb r0, r3
|
|
80023a6: 88bb ldrh r3, [r7, #4]
|
|
80023a8: b2d9 uxtb r1, r3
|
|
80023aa: 88fb ldrh r3, [r7, #6]
|
|
80023ac: b2db uxtb r3, r3
|
|
80023ae: 3301 adds r3, #1
|
|
80023b0: b2da uxtb r2, r3
|
|
80023b2: 88bb ldrh r3, [r7, #4]
|
|
80023b4: b2db uxtb r3, r3
|
|
80023b6: 3301 adds r3, #1
|
|
80023b8: b2db uxtb r3, r3
|
|
80023ba: f7ff ff61 bl 8002280 <setAddrWindow>
|
|
|
|
hi = color >> 8;
|
|
80023be: 887b ldrh r3, [r7, #2]
|
|
80023c0: 0a1b lsrs r3, r3, #8
|
|
80023c2: b29b uxth r3, r3
|
|
80023c4: b2db uxtb r3, r3
|
|
80023c6: 73fb strb r3, [r7, #15]
|
|
lo = color ;
|
|
80023c8: 887b ldrh r3, [r7, #2]
|
|
80023ca: b2db uxtb r3, r3
|
|
80023cc: 73bb strb r3, [r7, #14]
|
|
HAL_SPI_Transmit(&hspi1, &lo, 1, 100); //
|
|
|
|
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1*/
|
|
|
|
|
|
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
|
|
80023ce: 4b0e ldr r3, [pc, #56] @ (8002408 <drawPixel_TFT+0x84>)
|
|
80023d0: 2204 movs r2, #4
|
|
80023d2: 619a str r2, [r3, #24]
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0
|
|
80023d4: 4b0c ldr r3, [pc, #48] @ (8002408 <drawPixel_TFT+0x84>)
|
|
80023d6: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
80023da: 619a str r2, [r3, #24]
|
|
|
|
HAL_SPI_Transmit(&hspi1, &hi, 1, 100); //
|
|
80023dc: f107 010f add.w r1, r7, #15
|
|
80023e0: 2364 movs r3, #100 @ 0x64
|
|
80023e2: 2201 movs r2, #1
|
|
80023e4: 4809 ldr r0, [pc, #36] @ (800240c <drawPixel_TFT+0x88>)
|
|
80023e6: f7ff fca6 bl 8001d36 <HAL_SPI_Transmit>
|
|
HAL_SPI_Transmit(&hspi1, &lo, 1, 100); //
|
|
80023ea: f107 010e add.w r1, r7, #14
|
|
80023ee: 2364 movs r3, #100 @ 0x64
|
|
80023f0: 2201 movs r2, #1
|
|
80023f2: 4806 ldr r0, [pc, #24] @ (800240c <drawPixel_TFT+0x88>)
|
|
80023f4: f7ff fc9f bl 8001d36 <HAL_SPI_Transmit>
|
|
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
|
|
80023f8: 4b03 ldr r3, [pc, #12] @ (8002408 <drawPixel_TFT+0x84>)
|
|
80023fa: 2202 movs r2, #2
|
|
80023fc: 619a str r2, [r3, #24]
|
|
80023fe: e000 b.n 8002402 <drawPixel_TFT+0x7e>
|
|
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
|
|
8002400: bf00 nop
|
|
}
|
|
8002402: 3710 adds r7, #16
|
|
8002404: 46bd mov sp, r7
|
|
8002406: bd80 pop {r7, pc}
|
|
8002408: 40020800 .word 0x40020800
|
|
800240c: 20000078 .word 0x20000078
|
|
|
|
08002410 <fillRect_TFT>:
|
|
* : color = 16bits RGB(565) soit RRRRRGGGGGGGBBBBB
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void fillRect_TFT(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color)
|
|
{
|
|
8002410: b590 push {r4, r7, lr}
|
|
8002412: b085 sub sp, #20
|
|
8002414: af00 add r7, sp, #0
|
|
8002416: 4604 mov r4, r0
|
|
8002418: 4608 mov r0, r1
|
|
800241a: 4611 mov r1, r2
|
|
800241c: 461a mov r2, r3
|
|
800241e: 4623 mov r3, r4
|
|
8002420: 80fb strh r3, [r7, #6]
|
|
8002422: 4603 mov r3, r0
|
|
8002424: 80bb strh r3, [r7, #4]
|
|
8002426: 460b mov r3, r1
|
|
8002428: 807b strh r3, [r7, #2]
|
|
800242a: 4613 mov r3, r2
|
|
800242c: 803b strh r3, [r7, #0]
|
|
uint8_t hi, lo;
|
|
|
|
// rudimentary clipping (drawChar w/big text requires this)
|
|
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
|
|
800242e: 88fb ldrh r3, [r7, #6]
|
|
8002430: 2b7f cmp r3, #127 @ 0x7f
|
|
8002432: d85e bhi.n 80024f2 <fillRect_TFT+0xe2>
|
|
8002434: 88bb ldrh r3, [r7, #4]
|
|
8002436: 2b9f cmp r3, #159 @ 0x9f
|
|
8002438: d85b bhi.n 80024f2 <fillRect_TFT+0xe2>
|
|
|
|
if((x + w - 1) >= ST7735_TFTWIDTH) w = ST7735_TFTWIDTH - x;
|
|
800243a: 88fa ldrh r2, [r7, #6]
|
|
800243c: 887b ldrh r3, [r7, #2]
|
|
800243e: 4413 add r3, r2
|
|
8002440: 2b80 cmp r3, #128 @ 0x80
|
|
8002442: dd03 ble.n 800244c <fillRect_TFT+0x3c>
|
|
8002444: 88fb ldrh r3, [r7, #6]
|
|
8002446: f1c3 0380 rsb r3, r3, #128 @ 0x80
|
|
800244a: 807b strh r3, [r7, #2]
|
|
if((y + h - 1) >= ST7735_TFTHEIGHT_18) h = ST7735_TFTHEIGHT_18 - y;
|
|
800244c: 88ba ldrh r2, [r7, #4]
|
|
800244e: 883b ldrh r3, [r7, #0]
|
|
8002450: 4413 add r3, r2
|
|
8002452: 2ba0 cmp r3, #160 @ 0xa0
|
|
8002454: dd03 ble.n 800245e <fillRect_TFT+0x4e>
|
|
8002456: 88bb ldrh r3, [r7, #4]
|
|
8002458: f1c3 03a0 rsb r3, r3, #160 @ 0xa0
|
|
800245c: 803b strh r3, [r7, #0]
|
|
|
|
// select window
|
|
setAddrWindow(x, y, x+w-1, y+h-1);
|
|
800245e: 88fb ldrh r3, [r7, #6]
|
|
8002460: b2d8 uxtb r0, r3
|
|
8002462: 88bb ldrh r3, [r7, #4]
|
|
8002464: b2d9 uxtb r1, r3
|
|
8002466: 88fb ldrh r3, [r7, #6]
|
|
8002468: b2da uxtb r2, r3
|
|
800246a: 887b ldrh r3, [r7, #2]
|
|
800246c: b2db uxtb r3, r3
|
|
800246e: 4413 add r3, r2
|
|
8002470: b2db uxtb r3, r3
|
|
8002472: 3b01 subs r3, #1
|
|
8002474: b2dc uxtb r4, r3
|
|
8002476: 88bb ldrh r3, [r7, #4]
|
|
8002478: b2da uxtb r2, r3
|
|
800247a: 883b ldrh r3, [r7, #0]
|
|
800247c: b2db uxtb r3, r3
|
|
800247e: 4413 add r3, r2
|
|
8002480: b2db uxtb r3, r3
|
|
8002482: 3b01 subs r3, #1
|
|
8002484: b2db uxtb r3, r3
|
|
8002486: 4622 mov r2, r4
|
|
8002488: f7ff fefa bl 8002280 <setAddrWindow>
|
|
|
|
hi = color >> 8;
|
|
800248c: 8c3b ldrh r3, [r7, #32]
|
|
800248e: 0a1b lsrs r3, r3, #8
|
|
8002490: b29b uxth r3, r3
|
|
8002492: b2db uxtb r3, r3
|
|
8002494: 73fb strb r3, [r7, #15]
|
|
lo = color ;
|
|
8002496: 8c3b ldrh r3, [r7, #32]
|
|
8002498: b2db uxtb r3, r3
|
|
800249a: 73bb strb r3, [r7, #14]
|
|
*/
|
|
|
|
/*HAL_GPIO_WritePin(GPIOB, GPIO_PIN_14, 1); // D/nC = 1 data
|
|
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 0); // nCS = 0*/
|
|
|
|
ST7735_D_nC_PORT->BSRR = (uint32_t)ST7735_D_nC_PIN ;// D/nC = 1 data
|
|
800249c: 4b17 ldr r3, [pc, #92] @ (80024fc <fillRect_TFT+0xec>)
|
|
800249e: 2204 movs r2, #4
|
|
80024a0: 619a str r2, [r3, #24]
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN<<16;// nCS = 0
|
|
80024a2: 4b16 ldr r3, [pc, #88] @ (80024fc <fillRect_TFT+0xec>)
|
|
80024a4: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
80024a8: 619a str r2, [r3, #24]
|
|
|
|
for(y=h; y>0; y--)
|
|
80024aa: 883b ldrh r3, [r7, #0]
|
|
80024ac: 80bb strh r3, [r7, #4]
|
|
80024ae: e019 b.n 80024e4 <fillRect_TFT+0xd4>
|
|
{
|
|
for(x=w; x>0; x--)
|
|
80024b0: 887b ldrh r3, [r7, #2]
|
|
80024b2: 80fb strh r3, [r7, #6]
|
|
80024b4: e010 b.n 80024d8 <fillRect_TFT+0xc8>
|
|
{
|
|
|
|
HAL_SPI_Transmit(&hspi1, &hi, 1, 100); //
|
|
80024b6: f107 010f add.w r1, r7, #15
|
|
80024ba: 2364 movs r3, #100 @ 0x64
|
|
80024bc: 2201 movs r2, #1
|
|
80024be: 4810 ldr r0, [pc, #64] @ (8002500 <fillRect_TFT+0xf0>)
|
|
80024c0: f7ff fc39 bl 8001d36 <HAL_SPI_Transmit>
|
|
HAL_SPI_Transmit(&hspi1, &lo, 1, 100); //
|
|
80024c4: f107 010e add.w r1, r7, #14
|
|
80024c8: 2364 movs r3, #100 @ 0x64
|
|
80024ca: 2201 movs r2, #1
|
|
80024cc: 480c ldr r0, [pc, #48] @ (8002500 <fillRect_TFT+0xf0>)
|
|
80024ce: f7ff fc32 bl 8001d36 <HAL_SPI_Transmit>
|
|
for(x=w; x>0; x--)
|
|
80024d2: 88fb ldrh r3, [r7, #6]
|
|
80024d4: 3b01 subs r3, #1
|
|
80024d6: 80fb strh r3, [r7, #6]
|
|
80024d8: 88fb ldrh r3, [r7, #6]
|
|
80024da: 2b00 cmp r3, #0
|
|
80024dc: d1eb bne.n 80024b6 <fillRect_TFT+0xa6>
|
|
for(y=h; y>0; y--)
|
|
80024de: 88bb ldrh r3, [r7, #4]
|
|
80024e0: 3b01 subs r3, #1
|
|
80024e2: 80bb strh r3, [r7, #4]
|
|
80024e4: 88bb ldrh r3, [r7, #4]
|
|
80024e6: 2b00 cmp r3, #0
|
|
80024e8: d1e2 bne.n 80024b0 <fillRect_TFT+0xa0>
|
|
|
|
}
|
|
}
|
|
|
|
//HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, 1); // nCS = 1
|
|
ST7735_nCS_PORT->BSRR = (uint32_t)ST7735_nCS_PIN;// nCS = 1
|
|
80024ea: 4b04 ldr r3, [pc, #16] @ (80024fc <fillRect_TFT+0xec>)
|
|
80024ec: 2202 movs r2, #2
|
|
80024ee: 619a str r2, [r3, #24]
|
|
80024f0: e000 b.n 80024f4 <fillRect_TFT+0xe4>
|
|
if((x >= ST7735_TFTWIDTH) || (y >= ST7735_TFTHEIGHT_18)) return;
|
|
80024f2: bf00 nop
|
|
|
|
}
|
|
80024f4: 3714 adds r7, #20
|
|
80024f6: 46bd mov sp, r7
|
|
80024f8: bd90 pop {r4, r7, pc}
|
|
80024fa: bf00 nop
|
|
80024fc: 40020800 .word 0x40020800
|
|
8002500: 20000078 .word 0x20000078
|
|
|
|
08002504 <displayChar_TFT>:
|
|
* : size = 1 to 10
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void displayChar_TFT(uint16_t x, uint16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size)
|
|
{
|
|
8002504: b590 push {r4, r7, lr}
|
|
8002506: b087 sub sp, #28
|
|
8002508: af02 add r7, sp, #8
|
|
800250a: 4604 mov r4, r0
|
|
800250c: 4608 mov r0, r1
|
|
800250e: 4611 mov r1, r2
|
|
8002510: 461a mov r2, r3
|
|
8002512: 4623 mov r3, r4
|
|
8002514: 80fb strh r3, [r7, #6]
|
|
8002516: 4603 mov r3, r0
|
|
8002518: 80bb strh r3, [r7, #4]
|
|
800251a: 460b mov r3, r1
|
|
800251c: 70fb strb r3, [r7, #3]
|
|
800251e: 4613 mov r3, r2
|
|
8002520: 803b strh r3, [r7, #0]
|
|
uint8_t i,j,line;
|
|
|
|
|
|
if((x >= ST7735_TFTWIDTH) || // Clip right
|
|
8002522: 88fb ldrh r3, [r7, #6]
|
|
8002524: 2b7f cmp r3, #127 @ 0x7f
|
|
8002526: f200 80b1 bhi.w 800268c <displayChar_TFT+0x188>
|
|
800252a: 88bb ldrh r3, [r7, #4]
|
|
800252c: 2b9f cmp r3, #159 @ 0x9f
|
|
800252e: f200 80ad bhi.w 800268c <displayChar_TFT+0x188>
|
|
(y >= ST7735_TFTHEIGHT_18) || // Clip bottom
|
|
((x + 6 * size - 1) < 0) || // Clip left
|
|
8002532: 88f9 ldrh r1, [r7, #6]
|
|
8002534: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
|
|
8002538: 4613 mov r3, r2
|
|
800253a: 005b lsls r3, r3, #1
|
|
800253c: 4413 add r3, r2
|
|
800253e: 005b lsls r3, r3, #1
|
|
8002540: 440b add r3, r1
|
|
(y >= ST7735_TFTHEIGHT_18) || // Clip bottom
|
|
8002542: 2b00 cmp r3, #0
|
|
8002544: f340 80a2 ble.w 800268c <displayChar_TFT+0x188>
|
|
((y + 8 * size - 1) < 0)) // Clip top
|
|
8002548: 88ba ldrh r2, [r7, #4]
|
|
800254a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800254e: 00db lsls r3, r3, #3
|
|
8002550: 4413 add r3, r2
|
|
((x + 6 * size - 1) < 0) || // Clip left
|
|
8002552: 2b00 cmp r3, #0
|
|
8002554: f340 809a ble.w 800268c <displayChar_TFT+0x188>
|
|
return;
|
|
|
|
for (i=0; i<6; i++ )
|
|
8002558: 2300 movs r3, #0
|
|
800255a: 73fb strb r3, [r7, #15]
|
|
800255c: e091 b.n 8002682 <displayChar_TFT+0x17e>
|
|
{
|
|
if (i == 5)
|
|
800255e: 7bfb ldrb r3, [r7, #15]
|
|
8002560: 2b05 cmp r3, #5
|
|
8002562: d102 bne.n 800256a <displayChar_TFT+0x66>
|
|
line = 0x0;
|
|
8002564: 2300 movs r3, #0
|
|
8002566: 737b strb r3, [r7, #13]
|
|
8002568: e00a b.n 8002580 <displayChar_TFT+0x7c>
|
|
else
|
|
line = pgm_read_byte(tab_font + (c*5) + i);
|
|
800256a: 78fa ldrb r2, [r7, #3]
|
|
800256c: 4613 mov r3, r2
|
|
800256e: 009b lsls r3, r3, #2
|
|
8002570: 4413 add r3, r2
|
|
8002572: 461a mov r2, r3
|
|
8002574: 7bfb ldrb r3, [r7, #15]
|
|
8002576: 4413 add r3, r2
|
|
8002578: 4a46 ldr r2, [pc, #280] @ (8002694 <displayChar_TFT+0x190>)
|
|
800257a: 4413 add r3, r2
|
|
800257c: 781b ldrb r3, [r3, #0]
|
|
800257e: 737b strb r3, [r7, #13]
|
|
|
|
for ( j = 0; j<8; j++)
|
|
8002580: 2300 movs r3, #0
|
|
8002582: 73bb strb r3, [r7, #14]
|
|
8002584: e077 b.n 8002676 <displayChar_TFT+0x172>
|
|
{
|
|
if (line & 0x1)
|
|
8002586: 7b7b ldrb r3, [r7, #13]
|
|
8002588: f003 0301 and.w r3, r3, #1
|
|
800258c: 2b00 cmp r3, #0
|
|
800258e: d034 beq.n 80025fa <displayChar_TFT+0xf6>
|
|
{
|
|
if (size == 1) // default size
|
|
8002590: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8002594: 2b01 cmp r3, #1
|
|
8002596: d10e bne.n 80025b6 <displayChar_TFT+0xb2>
|
|
drawPixel_TFT(x+i, y+j, color);
|
|
8002598: 7bfb ldrb r3, [r7, #15]
|
|
800259a: b29a uxth r2, r3
|
|
800259c: 88fb ldrh r3, [r7, #6]
|
|
800259e: 4413 add r3, r2
|
|
80025a0: b298 uxth r0, r3
|
|
80025a2: 7bbb ldrb r3, [r7, #14]
|
|
80025a4: b29a uxth r2, r3
|
|
80025a6: 88bb ldrh r3, [r7, #4]
|
|
80025a8: 4413 add r3, r2
|
|
80025aa: b29b uxth r3, r3
|
|
80025ac: 883a ldrh r2, [r7, #0]
|
|
80025ae: 4619 mov r1, r3
|
|
80025b0: f7ff fee8 bl 8002384 <drawPixel_TFT>
|
|
80025b4: e059 b.n 800266a <displayChar_TFT+0x166>
|
|
else
|
|
{ // big size
|
|
fillRect_TFT(x+(i*size), y+(j*size), size, size, color);
|
|
80025b6: 7bfb ldrb r3, [r7, #15]
|
|
80025b8: b29b uxth r3, r3
|
|
80025ba: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
|
|
80025be: b292 uxth r2, r2
|
|
80025c0: fb02 f303 mul.w r3, r2, r3
|
|
80025c4: b29a uxth r2, r3
|
|
80025c6: 88fb ldrh r3, [r7, #6]
|
|
80025c8: 4413 add r3, r2
|
|
80025ca: b298 uxth r0, r3
|
|
80025cc: 7bbb ldrb r3, [r7, #14]
|
|
80025ce: b29b uxth r3, r3
|
|
80025d0: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
|
|
80025d4: b292 uxth r2, r2
|
|
80025d6: fb02 f303 mul.w r3, r2, r3
|
|
80025da: b29a uxth r2, r3
|
|
80025dc: 88bb ldrh r3, [r7, #4]
|
|
80025de: 4413 add r3, r2
|
|
80025e0: b299 uxth r1, r3
|
|
80025e2: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
80025e6: b29a uxth r2, r3
|
|
80025e8: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
80025ec: b29c uxth r4, r3
|
|
80025ee: 883b ldrh r3, [r7, #0]
|
|
80025f0: 9300 str r3, [sp, #0]
|
|
80025f2: 4623 mov r3, r4
|
|
80025f4: f7ff ff0c bl 8002410 <fillRect_TFT>
|
|
80025f8: e037 b.n 800266a <displayChar_TFT+0x166>
|
|
}
|
|
}
|
|
else if (bg != color)
|
|
80025fa: 8c3a ldrh r2, [r7, #32]
|
|
80025fc: 883b ldrh r3, [r7, #0]
|
|
80025fe: 429a cmp r2, r3
|
|
8002600: d033 beq.n 800266a <displayChar_TFT+0x166>
|
|
{
|
|
if (size == 1) // default size
|
|
8002602: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8002606: 2b01 cmp r3, #1
|
|
8002608: d10e bne.n 8002628 <displayChar_TFT+0x124>
|
|
drawPixel_TFT(x+i, y+j, bg);
|
|
800260a: 7bfb ldrb r3, [r7, #15]
|
|
800260c: b29a uxth r2, r3
|
|
800260e: 88fb ldrh r3, [r7, #6]
|
|
8002610: 4413 add r3, r2
|
|
8002612: b298 uxth r0, r3
|
|
8002614: 7bbb ldrb r3, [r7, #14]
|
|
8002616: b29a uxth r2, r3
|
|
8002618: 88bb ldrh r3, [r7, #4]
|
|
800261a: 4413 add r3, r2
|
|
800261c: b29b uxth r3, r3
|
|
800261e: 8c3a ldrh r2, [r7, #32]
|
|
8002620: 4619 mov r1, r3
|
|
8002622: f7ff feaf bl 8002384 <drawPixel_TFT>
|
|
8002626: e020 b.n 800266a <displayChar_TFT+0x166>
|
|
else
|
|
{ // big size
|
|
fillRect_TFT(x+i*size, y+j*size, size, size, bg);
|
|
8002628: 7bfb ldrb r3, [r7, #15]
|
|
800262a: b29b uxth r3, r3
|
|
800262c: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
|
|
8002630: b292 uxth r2, r2
|
|
8002632: fb02 f303 mul.w r3, r2, r3
|
|
8002636: b29a uxth r2, r3
|
|
8002638: 88fb ldrh r3, [r7, #6]
|
|
800263a: 4413 add r3, r2
|
|
800263c: b298 uxth r0, r3
|
|
800263e: 7bbb ldrb r3, [r7, #14]
|
|
8002640: b29b uxth r3, r3
|
|
8002642: f897 2024 ldrb.w r2, [r7, #36] @ 0x24
|
|
8002646: b292 uxth r2, r2
|
|
8002648: fb02 f303 mul.w r3, r2, r3
|
|
800264c: b29a uxth r2, r3
|
|
800264e: 88bb ldrh r3, [r7, #4]
|
|
8002650: 4413 add r3, r2
|
|
8002652: b299 uxth r1, r3
|
|
8002654: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
8002658: b29a uxth r2, r3
|
|
800265a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800265e: b29c uxth r4, r3
|
|
8002660: 8c3b ldrh r3, [r7, #32]
|
|
8002662: 9300 str r3, [sp, #0]
|
|
8002664: 4623 mov r3, r4
|
|
8002666: f7ff fed3 bl 8002410 <fillRect_TFT>
|
|
}
|
|
}
|
|
line = line >> 1;
|
|
800266a: 7b7b ldrb r3, [r7, #13]
|
|
800266c: 085b lsrs r3, r3, #1
|
|
800266e: 737b strb r3, [r7, #13]
|
|
for ( j = 0; j<8; j++)
|
|
8002670: 7bbb ldrb r3, [r7, #14]
|
|
8002672: 3301 adds r3, #1
|
|
8002674: 73bb strb r3, [r7, #14]
|
|
8002676: 7bbb ldrb r3, [r7, #14]
|
|
8002678: 2b07 cmp r3, #7
|
|
800267a: d984 bls.n 8002586 <displayChar_TFT+0x82>
|
|
for (i=0; i<6; i++ )
|
|
800267c: 7bfb ldrb r3, [r7, #15]
|
|
800267e: 3301 adds r3, #1
|
|
8002680: 73fb strb r3, [r7, #15]
|
|
8002682: 7bfb ldrb r3, [r7, #15]
|
|
8002684: 2b05 cmp r3, #5
|
|
8002686: f67f af6a bls.w 800255e <displayChar_TFT+0x5a>
|
|
800268a: e000 b.n 800268e <displayChar_TFT+0x18a>
|
|
return;
|
|
800268c: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
800268e: 3714 adds r7, #20
|
|
8002690: 46bd mov sp, r7
|
|
8002692: bd90 pop {r4, r7, pc}
|
|
8002694: 08002a20 .word 0x08002a20
|
|
|
|
08002698 <displayLogo_TFT>:
|
|
* Input :
|
|
* Output : None
|
|
* Return : None
|
|
*******************************************************************************/
|
|
void displayLogo_TFT( void)
|
|
{
|
|
8002698: b580 push {r7, lr}
|
|
800269a: b082 sub sp, #8
|
|
800269c: af00 add r7, sp, #0
|
|
uint8_t i,j,k,line;
|
|
uint16_t color=ST7735_WHITE;
|
|
800269e: f64f 73ff movw r3, #65535 @ 0xffff
|
|
80026a2: 807b strh r3, [r7, #2]
|
|
|
|
|
|
|
|
for(i=0;i<=120;i++)
|
|
80026a4: 2300 movs r3, #0
|
|
80026a6: 71fb strb r3, [r7, #7]
|
|
80026a8: e09e b.n 80027e8 <displayLogo_TFT+0x150>
|
|
{
|
|
|
|
for(j=0;j<= 1;j++)
|
|
80026aa: 2300 movs r3, #0
|
|
80026ac: 71bb strb r3, [r7, #6]
|
|
80026ae: e02b b.n 8002708 <displayLogo_TFT+0x70>
|
|
{
|
|
line=(ALL_IS_mono_120[i+120*j]);
|
|
80026b0: 79f9 ldrb r1, [r7, #7]
|
|
80026b2: 79ba ldrb r2, [r7, #6]
|
|
80026b4: 4613 mov r3, r2
|
|
80026b6: 011b lsls r3, r3, #4
|
|
80026b8: 1a9b subs r3, r3, r2
|
|
80026ba: 00db lsls r3, r3, #3
|
|
80026bc: 440b add r3, r1
|
|
80026be: 4a4f ldr r2, [pc, #316] @ (80027fc <displayLogo_TFT+0x164>)
|
|
80026c0: 5cd3 ldrb r3, [r2, r3]
|
|
80026c2: 713b strb r3, [r7, #4]
|
|
for ( k = 0; k<8; k++)
|
|
80026c4: 2300 movs r3, #0
|
|
80026c6: 717b strb r3, [r7, #5]
|
|
80026c8: e018 b.n 80026fc <displayLogo_TFT+0x64>
|
|
{
|
|
if (line & 0x1)
|
|
80026ca: 793b ldrb r3, [r7, #4]
|
|
80026cc: f003 0301 and.w r3, r3, #1
|
|
80026d0: 2b00 cmp r3, #0
|
|
80026d2: d00d beq.n 80026f0 <displayLogo_TFT+0x58>
|
|
{
|
|
|
|
drawPixel_TFT(i, j*8+k, color);
|
|
80026d4: 79fb ldrb r3, [r7, #7]
|
|
80026d6: b298 uxth r0, r3
|
|
80026d8: 79bb ldrb r3, [r7, #6]
|
|
80026da: b29b uxth r3, r3
|
|
80026dc: 00db lsls r3, r3, #3
|
|
80026de: b29a uxth r2, r3
|
|
80026e0: 797b ldrb r3, [r7, #5]
|
|
80026e2: b29b uxth r3, r3
|
|
80026e4: 4413 add r3, r2
|
|
80026e6: b29b uxth r3, r3
|
|
80026e8: 887a ldrh r2, [r7, #2]
|
|
80026ea: 4619 mov r1, r3
|
|
80026ec: f7ff fe4a bl 8002384 <drawPixel_TFT>
|
|
}
|
|
line = line >> 1;
|
|
80026f0: 793b ldrb r3, [r7, #4]
|
|
80026f2: 085b lsrs r3, r3, #1
|
|
80026f4: 713b strb r3, [r7, #4]
|
|
for ( k = 0; k<8; k++)
|
|
80026f6: 797b ldrb r3, [r7, #5]
|
|
80026f8: 3301 adds r3, #1
|
|
80026fa: 717b strb r3, [r7, #5]
|
|
80026fc: 797b ldrb r3, [r7, #5]
|
|
80026fe: 2b07 cmp r3, #7
|
|
8002700: d9e3 bls.n 80026ca <displayLogo_TFT+0x32>
|
|
for(j=0;j<= 1;j++)
|
|
8002702: 79bb ldrb r3, [r7, #6]
|
|
8002704: 3301 adds r3, #1
|
|
8002706: 71bb strb r3, [r7, #6]
|
|
8002708: 79bb ldrb r3, [r7, #6]
|
|
800270a: 2b01 cmp r3, #1
|
|
800270c: d9d0 bls.n 80026b0 <displayLogo_TFT+0x18>
|
|
}
|
|
}
|
|
|
|
color=ST7735_RED;
|
|
800270e: f44f 4378 mov.w r3, #63488 @ 0xf800
|
|
8002712: 807b strh r3, [r7, #2]
|
|
for(j=2;j<= 3;j++)
|
|
8002714: 2302 movs r3, #2
|
|
8002716: 71bb strb r3, [r7, #6]
|
|
8002718: e02b b.n 8002772 <displayLogo_TFT+0xda>
|
|
{
|
|
line=(ALL_IS_mono_120[i+120*j]);
|
|
800271a: 79f9 ldrb r1, [r7, #7]
|
|
800271c: 79ba ldrb r2, [r7, #6]
|
|
800271e: 4613 mov r3, r2
|
|
8002720: 011b lsls r3, r3, #4
|
|
8002722: 1a9b subs r3, r3, r2
|
|
8002724: 00db lsls r3, r3, #3
|
|
8002726: 440b add r3, r1
|
|
8002728: 4a34 ldr r2, [pc, #208] @ (80027fc <displayLogo_TFT+0x164>)
|
|
800272a: 5cd3 ldrb r3, [r2, r3]
|
|
800272c: 713b strb r3, [r7, #4]
|
|
for ( k = 0; k<8; k++)
|
|
800272e: 2300 movs r3, #0
|
|
8002730: 717b strb r3, [r7, #5]
|
|
8002732: e018 b.n 8002766 <displayLogo_TFT+0xce>
|
|
{
|
|
if (line & 0x1)
|
|
8002734: 793b ldrb r3, [r7, #4]
|
|
8002736: f003 0301 and.w r3, r3, #1
|
|
800273a: 2b00 cmp r3, #0
|
|
800273c: d00d beq.n 800275a <displayLogo_TFT+0xc2>
|
|
{
|
|
|
|
drawPixel_TFT(i, j*8+k, color);
|
|
800273e: 79fb ldrb r3, [r7, #7]
|
|
8002740: b298 uxth r0, r3
|
|
8002742: 79bb ldrb r3, [r7, #6]
|
|
8002744: b29b uxth r3, r3
|
|
8002746: 00db lsls r3, r3, #3
|
|
8002748: b29a uxth r2, r3
|
|
800274a: 797b ldrb r3, [r7, #5]
|
|
800274c: b29b uxth r3, r3
|
|
800274e: 4413 add r3, r2
|
|
8002750: b29b uxth r3, r3
|
|
8002752: 887a ldrh r2, [r7, #2]
|
|
8002754: 4619 mov r1, r3
|
|
8002756: f7ff fe15 bl 8002384 <drawPixel_TFT>
|
|
}
|
|
line = line >> 1;
|
|
800275a: 793b ldrb r3, [r7, #4]
|
|
800275c: 085b lsrs r3, r3, #1
|
|
800275e: 713b strb r3, [r7, #4]
|
|
for ( k = 0; k<8; k++)
|
|
8002760: 797b ldrb r3, [r7, #5]
|
|
8002762: 3301 adds r3, #1
|
|
8002764: 717b strb r3, [r7, #5]
|
|
8002766: 797b ldrb r3, [r7, #5]
|
|
8002768: 2b07 cmp r3, #7
|
|
800276a: d9e3 bls.n 8002734 <displayLogo_TFT+0x9c>
|
|
for(j=2;j<= 3;j++)
|
|
800276c: 79bb ldrb r3, [r7, #6]
|
|
800276e: 3301 adds r3, #1
|
|
8002770: 71bb strb r3, [r7, #6]
|
|
8002772: 79bb ldrb r3, [r7, #6]
|
|
8002774: 2b03 cmp r3, #3
|
|
8002776: d9d0 bls.n 800271a <displayLogo_TFT+0x82>
|
|
}
|
|
}
|
|
|
|
color=ST7735_WHITE;
|
|
8002778: f64f 73ff movw r3, #65535 @ 0xffff
|
|
800277c: 807b strh r3, [r7, #2]
|
|
for(j=4;j<= 5;j++)
|
|
800277e: 2304 movs r3, #4
|
|
8002780: 71bb strb r3, [r7, #6]
|
|
8002782: e02b b.n 80027dc <displayLogo_TFT+0x144>
|
|
{
|
|
line=(ALL_IS_mono_120[i+120*j]);
|
|
8002784: 79f9 ldrb r1, [r7, #7]
|
|
8002786: 79ba ldrb r2, [r7, #6]
|
|
8002788: 4613 mov r3, r2
|
|
800278a: 011b lsls r3, r3, #4
|
|
800278c: 1a9b subs r3, r3, r2
|
|
800278e: 00db lsls r3, r3, #3
|
|
8002790: 440b add r3, r1
|
|
8002792: 4a1a ldr r2, [pc, #104] @ (80027fc <displayLogo_TFT+0x164>)
|
|
8002794: 5cd3 ldrb r3, [r2, r3]
|
|
8002796: 713b strb r3, [r7, #4]
|
|
for ( k = 0; k<8; k++)
|
|
8002798: 2300 movs r3, #0
|
|
800279a: 717b strb r3, [r7, #5]
|
|
800279c: e018 b.n 80027d0 <displayLogo_TFT+0x138>
|
|
{
|
|
if (line & 0x1)
|
|
800279e: 793b ldrb r3, [r7, #4]
|
|
80027a0: f003 0301 and.w r3, r3, #1
|
|
80027a4: 2b00 cmp r3, #0
|
|
80027a6: d00d beq.n 80027c4 <displayLogo_TFT+0x12c>
|
|
{
|
|
|
|
drawPixel_TFT(i, j*8+k, color);
|
|
80027a8: 79fb ldrb r3, [r7, #7]
|
|
80027aa: b298 uxth r0, r3
|
|
80027ac: 79bb ldrb r3, [r7, #6]
|
|
80027ae: b29b uxth r3, r3
|
|
80027b0: 00db lsls r3, r3, #3
|
|
80027b2: b29a uxth r2, r3
|
|
80027b4: 797b ldrb r3, [r7, #5]
|
|
80027b6: b29b uxth r3, r3
|
|
80027b8: 4413 add r3, r2
|
|
80027ba: b29b uxth r3, r3
|
|
80027bc: 887a ldrh r2, [r7, #2]
|
|
80027be: 4619 mov r1, r3
|
|
80027c0: f7ff fde0 bl 8002384 <drawPixel_TFT>
|
|
}
|
|
line = line >> 1;
|
|
80027c4: 793b ldrb r3, [r7, #4]
|
|
80027c6: 085b lsrs r3, r3, #1
|
|
80027c8: 713b strb r3, [r7, #4]
|
|
for ( k = 0; k<8; k++)
|
|
80027ca: 797b ldrb r3, [r7, #5]
|
|
80027cc: 3301 adds r3, #1
|
|
80027ce: 717b strb r3, [r7, #5]
|
|
80027d0: 797b ldrb r3, [r7, #5]
|
|
80027d2: 2b07 cmp r3, #7
|
|
80027d4: d9e3 bls.n 800279e <displayLogo_TFT+0x106>
|
|
for(j=4;j<= 5;j++)
|
|
80027d6: 79bb ldrb r3, [r7, #6]
|
|
80027d8: 3301 adds r3, #1
|
|
80027da: 71bb strb r3, [r7, #6]
|
|
80027dc: 79bb ldrb r3, [r7, #6]
|
|
80027de: 2b05 cmp r3, #5
|
|
80027e0: d9d0 bls.n 8002784 <displayLogo_TFT+0xec>
|
|
for(i=0;i<=120;i++)
|
|
80027e2: 79fb ldrb r3, [r7, #7]
|
|
80027e4: 3301 adds r3, #1
|
|
80027e6: 71fb strb r3, [r7, #7]
|
|
80027e8: 79fb ldrb r3, [r7, #7]
|
|
80027ea: 2b78 cmp r3, #120 @ 0x78
|
|
80027ec: f67f af5d bls.w 80026aa <displayLogo_TFT+0x12>
|
|
}
|
|
}
|
|
|
|
}
|
|
}
|
|
80027f0: bf00 nop
|
|
80027f2: bf00 nop
|
|
80027f4: 3708 adds r7, #8
|
|
80027f6: 46bd mov sp, r7
|
|
80027f8: bd80 pop {r7, pc}
|
|
80027fa: bf00 nop
|
|
80027fc: 08002f1c .word 0x08002f1c
|
|
|
|
08002800 <atoi>:
|
|
8002800: 220a movs r2, #10
|
|
8002802: 2100 movs r1, #0
|
|
8002804: f000 b87a b.w 80028fc <strtol>
|
|
|
|
08002808 <_strtol_l.isra.0>:
|
|
8002808: 2b24 cmp r3, #36 @ 0x24
|
|
800280a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800280e: 4686 mov lr, r0
|
|
8002810: 4690 mov r8, r2
|
|
8002812: d801 bhi.n 8002818 <_strtol_l.isra.0+0x10>
|
|
8002814: 2b01 cmp r3, #1
|
|
8002816: d106 bne.n 8002826 <_strtol_l.isra.0+0x1e>
|
|
8002818: f000 f882 bl 8002920 <__errno>
|
|
800281c: 2316 movs r3, #22
|
|
800281e: 6003 str r3, [r0, #0]
|
|
8002820: 2000 movs r0, #0
|
|
8002822: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8002826: 460d mov r5, r1
|
|
8002828: 4833 ldr r0, [pc, #204] @ (80028f8 <_strtol_l.isra.0+0xf0>)
|
|
800282a: 462a mov r2, r5
|
|
800282c: f815 4b01 ldrb.w r4, [r5], #1
|
|
8002830: 5d06 ldrb r6, [r0, r4]
|
|
8002832: f016 0608 ands.w r6, r6, #8
|
|
8002836: d1f8 bne.n 800282a <_strtol_l.isra.0+0x22>
|
|
8002838: 2c2d cmp r4, #45 @ 0x2d
|
|
800283a: d110 bne.n 800285e <_strtol_l.isra.0+0x56>
|
|
800283c: 2601 movs r6, #1
|
|
800283e: 782c ldrb r4, [r5, #0]
|
|
8002840: 1c95 adds r5, r2, #2
|
|
8002842: f033 0210 bics.w r2, r3, #16
|
|
8002846: d115 bne.n 8002874 <_strtol_l.isra.0+0x6c>
|
|
8002848: 2c30 cmp r4, #48 @ 0x30
|
|
800284a: d10d bne.n 8002868 <_strtol_l.isra.0+0x60>
|
|
800284c: 782a ldrb r2, [r5, #0]
|
|
800284e: f002 02df and.w r2, r2, #223 @ 0xdf
|
|
8002852: 2a58 cmp r2, #88 @ 0x58
|
|
8002854: d108 bne.n 8002868 <_strtol_l.isra.0+0x60>
|
|
8002856: 786c ldrb r4, [r5, #1]
|
|
8002858: 3502 adds r5, #2
|
|
800285a: 2310 movs r3, #16
|
|
800285c: e00a b.n 8002874 <_strtol_l.isra.0+0x6c>
|
|
800285e: 2c2b cmp r4, #43 @ 0x2b
|
|
8002860: bf04 itt eq
|
|
8002862: 782c ldrbeq r4, [r5, #0]
|
|
8002864: 1c95 addeq r5, r2, #2
|
|
8002866: e7ec b.n 8002842 <_strtol_l.isra.0+0x3a>
|
|
8002868: 2b00 cmp r3, #0
|
|
800286a: d1f6 bne.n 800285a <_strtol_l.isra.0+0x52>
|
|
800286c: 2c30 cmp r4, #48 @ 0x30
|
|
800286e: bf14 ite ne
|
|
8002870: 230a movne r3, #10
|
|
8002872: 2308 moveq r3, #8
|
|
8002874: 2200 movs r2, #0
|
|
8002876: f106 4c00 add.w ip, r6, #2147483648 @ 0x80000000
|
|
800287a: f10c 3cff add.w ip, ip, #4294967295 @ 0xffffffff
|
|
800287e: fbbc f9f3 udiv r9, ip, r3
|
|
8002882: 4610 mov r0, r2
|
|
8002884: fb03 ca19 mls sl, r3, r9, ip
|
|
8002888: f1a4 0730 sub.w r7, r4, #48 @ 0x30
|
|
800288c: 2f09 cmp r7, #9
|
|
800288e: d80f bhi.n 80028b0 <_strtol_l.isra.0+0xa8>
|
|
8002890: 463c mov r4, r7
|
|
8002892: 42a3 cmp r3, r4
|
|
8002894: dd1b ble.n 80028ce <_strtol_l.isra.0+0xc6>
|
|
8002896: 1c57 adds r7, r2, #1
|
|
8002898: d007 beq.n 80028aa <_strtol_l.isra.0+0xa2>
|
|
800289a: 4581 cmp r9, r0
|
|
800289c: d314 bcc.n 80028c8 <_strtol_l.isra.0+0xc0>
|
|
800289e: d101 bne.n 80028a4 <_strtol_l.isra.0+0x9c>
|
|
80028a0: 45a2 cmp sl, r4
|
|
80028a2: db11 blt.n 80028c8 <_strtol_l.isra.0+0xc0>
|
|
80028a4: 2201 movs r2, #1
|
|
80028a6: fb00 4003 mla r0, r0, r3, r4
|
|
80028aa: f815 4b01 ldrb.w r4, [r5], #1
|
|
80028ae: e7eb b.n 8002888 <_strtol_l.isra.0+0x80>
|
|
80028b0: f1a4 0741 sub.w r7, r4, #65 @ 0x41
|
|
80028b4: 2f19 cmp r7, #25
|
|
80028b6: d801 bhi.n 80028bc <_strtol_l.isra.0+0xb4>
|
|
80028b8: 3c37 subs r4, #55 @ 0x37
|
|
80028ba: e7ea b.n 8002892 <_strtol_l.isra.0+0x8a>
|
|
80028bc: f1a4 0761 sub.w r7, r4, #97 @ 0x61
|
|
80028c0: 2f19 cmp r7, #25
|
|
80028c2: d804 bhi.n 80028ce <_strtol_l.isra.0+0xc6>
|
|
80028c4: 3c57 subs r4, #87 @ 0x57
|
|
80028c6: e7e4 b.n 8002892 <_strtol_l.isra.0+0x8a>
|
|
80028c8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80028cc: e7ed b.n 80028aa <_strtol_l.isra.0+0xa2>
|
|
80028ce: 1c53 adds r3, r2, #1
|
|
80028d0: d108 bne.n 80028e4 <_strtol_l.isra.0+0xdc>
|
|
80028d2: 2322 movs r3, #34 @ 0x22
|
|
80028d4: 4660 mov r0, ip
|
|
80028d6: f8ce 3000 str.w r3, [lr]
|
|
80028da: f1b8 0f00 cmp.w r8, #0
|
|
80028de: d0a0 beq.n 8002822 <_strtol_l.isra.0+0x1a>
|
|
80028e0: 1e69 subs r1, r5, #1
|
|
80028e2: e006 b.n 80028f2 <_strtol_l.isra.0+0xea>
|
|
80028e4: b106 cbz r6, 80028e8 <_strtol_l.isra.0+0xe0>
|
|
80028e6: 4240 negs r0, r0
|
|
80028e8: f1b8 0f00 cmp.w r8, #0
|
|
80028ec: d099 beq.n 8002822 <_strtol_l.isra.0+0x1a>
|
|
80028ee: 2a00 cmp r2, #0
|
|
80028f0: d1f6 bne.n 80028e0 <_strtol_l.isra.0+0xd8>
|
|
80028f2: f8c8 1000 str.w r1, [r8]
|
|
80028f6: e794 b.n 8002822 <_strtol_l.isra.0+0x1a>
|
|
80028f8: 080031ed .word 0x080031ed
|
|
|
|
080028fc <strtol>:
|
|
80028fc: 4613 mov r3, r2
|
|
80028fe: 460a mov r2, r1
|
|
8002900: 4601 mov r1, r0
|
|
8002902: 4802 ldr r0, [pc, #8] @ (800290c <strtol+0x10>)
|
|
8002904: 6800 ldr r0, [r0, #0]
|
|
8002906: f7ff bf7f b.w 8002808 <_strtol_l.isra.0>
|
|
800290a: bf00 nop
|
|
800290c: 2000000c .word 0x2000000c
|
|
|
|
08002910 <memset>:
|
|
8002910: 4603 mov r3, r0
|
|
8002912: 4402 add r2, r0
|
|
8002914: 4293 cmp r3, r2
|
|
8002916: d100 bne.n 800291a <memset+0xa>
|
|
8002918: 4770 bx lr
|
|
800291a: f803 1b01 strb.w r1, [r3], #1
|
|
800291e: e7f9 b.n 8002914 <memset+0x4>
|
|
|
|
08002920 <__errno>:
|
|
8002920: 4b01 ldr r3, [pc, #4] @ (8002928 <__errno+0x8>)
|
|
8002922: 6818 ldr r0, [r3, #0]
|
|
8002924: 4770 bx lr
|
|
8002926: bf00 nop
|
|
8002928: 2000000c .word 0x2000000c
|
|
|
|
0800292c <__libc_init_array>:
|
|
800292c: b570 push {r4, r5, r6, lr}
|
|
800292e: 2600 movs r6, #0
|
|
8002930: 4d0c ldr r5, [pc, #48] @ (8002964 <__libc_init_array+0x38>)
|
|
8002932: 4c0d ldr r4, [pc, #52] @ (8002968 <__libc_init_array+0x3c>)
|
|
8002934: 1b64 subs r4, r4, r5
|
|
8002936: 10a4 asrs r4, r4, #2
|
|
8002938: 42a6 cmp r6, r4
|
|
800293a: d109 bne.n 8002950 <__libc_init_array+0x24>
|
|
800293c: f000 f81a bl 8002974 <_init>
|
|
8002940: 2600 movs r6, #0
|
|
8002942: 4d0a ldr r5, [pc, #40] @ (800296c <__libc_init_array+0x40>)
|
|
8002944: 4c0a ldr r4, [pc, #40] @ (8002970 <__libc_init_array+0x44>)
|
|
8002946: 1b64 subs r4, r4, r5
|
|
8002948: 10a4 asrs r4, r4, #2
|
|
800294a: 42a6 cmp r6, r4
|
|
800294c: d105 bne.n 800295a <__libc_init_array+0x2e>
|
|
800294e: bd70 pop {r4, r5, r6, pc}
|
|
8002950: f855 3b04 ldr.w r3, [r5], #4
|
|
8002954: 4798 blx r3
|
|
8002956: 3601 adds r6, #1
|
|
8002958: e7ee b.n 8002938 <__libc_init_array+0xc>
|
|
800295a: f855 3b04 ldr.w r3, [r5], #4
|
|
800295e: 4798 blx r3
|
|
8002960: 3601 adds r6, #1
|
|
8002962: e7f2 b.n 800294a <__libc_init_array+0x1e>
|
|
8002964: 080032f8 .word 0x080032f8
|
|
8002968: 080032f8 .word 0x080032f8
|
|
800296c: 080032f8 .word 0x080032f8
|
|
8002970: 080032fc .word 0x080032fc
|
|
|
|
08002974 <_init>:
|
|
8002974: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8002976: bf00 nop
|
|
8002978: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800297a: bc08 pop {r3}
|
|
800297c: 469e mov lr, r3
|
|
800297e: 4770 bx lr
|
|
|
|
08002980 <_fini>:
|
|
8002980: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8002982: bf00 nop
|
|
8002984: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8002986: bc08 pop {r3}
|
|
8002988: 469e mov lr, r3
|
|
800298a: 4770 bx lr
|