BreizhHardware/TP-STM32-CIPA3
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db89b9427c74908d8a0f70b4ee0973c1b8637e98
TP-STM32-CIPA3/TD-1-test/Debug/TD-1-test.list
Félix MARQUET db89b9427c TP1 début
2025-04-03 10:12:51 +02:00

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TD-1-test.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 0000013c 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001c0c 0800013c 0800013c 0000113c 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000024 08001d48 08001d48 00002d48 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08001d6c 08001d6c 0000300c 2**0
CONTENTS, READONLY
4 .ARM 00000008 08001d6c 08001d6c 00002d6c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08001d74 08001d74 0000300c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08001d74 08001d74 00002d74 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08001d78 08001d78 00002d78 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08001d7c 00003000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000068 2000000c 08001d88 0000300c 2**2
ALLOC
10 ._user_heap_stack 00000604 20000074 08001d88 00003074 2**0
ALLOC
11 .ARM.attributes 00000029 00000000 00000000 0000300c 2**0
CONTENTS, READONLY
12 .debug_info 000068b5 00000000 00000000 00003035 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000012b0 00000000 00000000 000098ea 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000618 00000000 00000000 0000aba0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 000004a7 00000000 00000000 0000b1b8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00014885 00000000 00000000 0000b65f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000704a 00000000 00000000 0001fee4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000819c0 00000000 00000000 00026f2e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000a88ee 2**0
CONTENTS, READONLY
20 .debug_frame 00001804 00000000 00000000 000a8934 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000069 00000000 00000000 000aa138 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
0800013c <__do_global_dtors_aux>:
800013c: b510 push {r4, lr}
800013e: 4c05 ldr r4, [pc, #20] @ (8000154 <__do_global_dtors_aux+0x18>)
8000140: 7823 ldrb r3, [r4, #0]
8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16>
8000144: 4b04 ldr r3, [pc, #16] @ (8000158 <__do_global_dtors_aux+0x1c>)
8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12>
8000148: 4804 ldr r0, [pc, #16] @ (800015c <__do_global_dtors_aux+0x20>)
800014a: f3af 8000 nop.w
800014e: 2301 movs r3, #1
8000150: 7023 strb r3, [r4, #0]
8000152: bd10 pop {r4, pc}
8000154: 2000000c .word 0x2000000c
8000158: 00000000 .word 0x00000000
800015c: 08001d30 .word 0x08001d30
08000160 <frame_dummy>:
8000160: b508 push {r3, lr}
8000162: 4b03 ldr r3, [pc, #12] @ (8000170 <frame_dummy+0x10>)
8000164: b11b cbz r3, 800016e <frame_dummy+0xe>
8000166: 4903 ldr r1, [pc, #12] @ (8000174 <frame_dummy+0x14>)
8000168: 4803 ldr r0, [pc, #12] @ (8000178 <frame_dummy+0x18>)
800016a: f3af 8000 nop.w
800016e: bd08 pop {r3, pc}
8000170: 00000000 .word 0x00000000
8000174: 20000010 .word 0x20000010
8000178: 08001d30 .word 0x08001d30
0800017c <__aeabi_uldivmod>:
800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18>
800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18>
8000180: 2900 cmp r1, #0
8000182: bf08 it eq
8000184: 2800 cmpeq r0, #0
8000186: bf1c itt ne
8000188: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
800018c: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
8000190: f000 b98c b.w 80004ac <__aeabi_idiv0>
8000194: f1ad 0c08 sub.w ip, sp, #8
8000198: e96d ce04 strd ip, lr, [sp, #-16]!
800019c: f000 f806 bl 80001ac <__udivmoddi4>
80001a0: f8dd e004 ldr.w lr, [sp, #4]
80001a4: e9dd 2302 ldrd r2, r3, [sp, #8]
80001a8: b004 add sp, #16
80001aa: 4770 bx lr
080001ac <__udivmoddi4>:
80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001b0: 9d08 ldr r5, [sp, #32]
80001b2: 468e mov lr, r1
80001b4: 4604 mov r4, r0
80001b6: 4688 mov r8, r1
80001b8: 2b00 cmp r3, #0
80001ba: d14a bne.n 8000252 <__udivmoddi4+0xa6>
80001bc: 428a cmp r2, r1
80001be: 4617 mov r7, r2
80001c0: d962 bls.n 8000288 <__udivmoddi4+0xdc>
80001c2: fab2 f682 clz r6, r2
80001c6: b14e cbz r6, 80001dc <__udivmoddi4+0x30>
80001c8: f1c6 0320 rsb r3, r6, #32
80001cc: fa01 f806 lsl.w r8, r1, r6
80001d0: fa20 f303 lsr.w r3, r0, r3
80001d4: 40b7 lsls r7, r6
80001d6: ea43 0808 orr.w r8, r3, r8
80001da: 40b4 lsls r4, r6
80001dc: ea4f 4e17 mov.w lr, r7, lsr #16
80001e0: fbb8 f1fe udiv r1, r8, lr
80001e4: fa1f fc87 uxth.w ip, r7
80001e8: fb0e 8811 mls r8, lr, r1, r8
80001ec: fb01 f20c mul.w r2, r1, ip
80001f0: 0c23 lsrs r3, r4, #16
80001f2: ea43 4308 orr.w r3, r3, r8, lsl #16
80001f6: 429a cmp r2, r3
80001f8: d909 bls.n 800020e <__udivmoddi4+0x62>
80001fa: 18fb adds r3, r7, r3
80001fc: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000200: f080 80eb bcs.w 80003da <__udivmoddi4+0x22e>
8000204: 429a cmp r2, r3
8000206: f240 80e8 bls.w 80003da <__udivmoddi4+0x22e>
800020a: 3902 subs r1, #2
800020c: 443b add r3, r7
800020e: 1a9a subs r2, r3, r2
8000210: fbb2 f0fe udiv r0, r2, lr
8000214: fb0e 2210 mls r2, lr, r0, r2
8000218: fb00 fc0c mul.w ip, r0, ip
800021c: b2a3 uxth r3, r4
800021e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000222: 459c cmp ip, r3
8000224: d909 bls.n 800023a <__udivmoddi4+0x8e>
8000226: 18fb adds r3, r7, r3
8000228: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
800022c: f080 80d7 bcs.w 80003de <__udivmoddi4+0x232>
8000230: 459c cmp ip, r3
8000232: f240 80d4 bls.w 80003de <__udivmoddi4+0x232>
8000236: 443b add r3, r7
8000238: 3802 subs r0, #2
800023a: ea40 4001 orr.w r0, r0, r1, lsl #16
800023e: 2100 movs r1, #0
8000240: eba3 030c sub.w r3, r3, ip
8000244: b11d cbz r5, 800024e <__udivmoddi4+0xa2>
8000246: 2200 movs r2, #0
8000248: 40f3 lsrs r3, r6
800024a: e9c5 3200 strd r3, r2, [r5]
800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000252: 428b cmp r3, r1
8000254: d905 bls.n 8000262 <__udivmoddi4+0xb6>
8000256: b10d cbz r5, 800025c <__udivmoddi4+0xb0>
8000258: e9c5 0100 strd r0, r1, [r5]
800025c: 2100 movs r1, #0
800025e: 4608 mov r0, r1
8000260: e7f5 b.n 800024e <__udivmoddi4+0xa2>
8000262: fab3 f183 clz r1, r3
8000266: 2900 cmp r1, #0
8000268: d146 bne.n 80002f8 <__udivmoddi4+0x14c>
800026a: 4573 cmp r3, lr
800026c: d302 bcc.n 8000274 <__udivmoddi4+0xc8>
800026e: 4282 cmp r2, r0
8000270: f200 8108 bhi.w 8000484 <__udivmoddi4+0x2d8>
8000274: 1a84 subs r4, r0, r2
8000276: eb6e 0203 sbc.w r2, lr, r3
800027a: 2001 movs r0, #1
800027c: 4690 mov r8, r2
800027e: 2d00 cmp r5, #0
8000280: d0e5 beq.n 800024e <__udivmoddi4+0xa2>
8000282: e9c5 4800 strd r4, r8, [r5]
8000286: e7e2 b.n 800024e <__udivmoddi4+0xa2>
8000288: 2a00 cmp r2, #0
800028a: f000 8091 beq.w 80003b0 <__udivmoddi4+0x204>
800028e: fab2 f682 clz r6, r2
8000292: 2e00 cmp r6, #0
8000294: f040 80a5 bne.w 80003e2 <__udivmoddi4+0x236>
8000298: 1a8a subs r2, r1, r2
800029a: 2101 movs r1, #1
800029c: 0c03 lsrs r3, r0, #16
800029e: ea4f 4e17 mov.w lr, r7, lsr #16
80002a2: b280 uxth r0, r0
80002a4: b2bc uxth r4, r7
80002a6: fbb2 fcfe udiv ip, r2, lr
80002aa: fb0e 221c mls r2, lr, ip, r2
80002ae: ea43 4302 orr.w r3, r3, r2, lsl #16
80002b2: fb04 f20c mul.w r2, r4, ip
80002b6: 429a cmp r2, r3
80002b8: d907 bls.n 80002ca <__udivmoddi4+0x11e>
80002ba: 18fb adds r3, r7, r3
80002bc: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
80002c0: d202 bcs.n 80002c8 <__udivmoddi4+0x11c>
80002c2: 429a cmp r2, r3
80002c4: f200 80e3 bhi.w 800048e <__udivmoddi4+0x2e2>
80002c8: 46c4 mov ip, r8
80002ca: 1a9b subs r3, r3, r2
80002cc: fbb3 f2fe udiv r2, r3, lr
80002d0: fb0e 3312 mls r3, lr, r2, r3
80002d4: fb02 f404 mul.w r4, r2, r4
80002d8: ea40 4303 orr.w r3, r0, r3, lsl #16
80002dc: 429c cmp r4, r3
80002de: d907 bls.n 80002f0 <__udivmoddi4+0x144>
80002e0: 18fb adds r3, r7, r3
80002e2: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
80002e6: d202 bcs.n 80002ee <__udivmoddi4+0x142>
80002e8: 429c cmp r4, r3
80002ea: f200 80cd bhi.w 8000488 <__udivmoddi4+0x2dc>
80002ee: 4602 mov r2, r0
80002f0: 1b1b subs r3, r3, r4
80002f2: ea42 400c orr.w r0, r2, ip, lsl #16
80002f6: e7a5 b.n 8000244 <__udivmoddi4+0x98>
80002f8: f1c1 0620 rsb r6, r1, #32
80002fc: 408b lsls r3, r1
80002fe: fa22 f706 lsr.w r7, r2, r6
8000302: 431f orrs r7, r3
8000304: fa2e fa06 lsr.w sl, lr, r6
8000308: ea4f 4917 mov.w r9, r7, lsr #16
800030c: fbba f8f9 udiv r8, sl, r9
8000310: fa0e fe01 lsl.w lr, lr, r1
8000314: fa20 f306 lsr.w r3, r0, r6
8000318: fb09 aa18 mls sl, r9, r8, sl
800031c: fa1f fc87 uxth.w ip, r7
8000320: ea43 030e orr.w r3, r3, lr
8000324: fa00 fe01 lsl.w lr, r0, r1
8000328: fb08 f00c mul.w r0, r8, ip
800032c: 0c1c lsrs r4, r3, #16
800032e: ea44 440a orr.w r4, r4, sl, lsl #16
8000332: 42a0 cmp r0, r4
8000334: fa02 f201 lsl.w r2, r2, r1
8000338: d90a bls.n 8000350 <__udivmoddi4+0x1a4>
800033a: 193c adds r4, r7, r4
800033c: f108 3aff add.w sl, r8, #4294967295 @ 0xffffffff
8000340: f080 809e bcs.w 8000480 <__udivmoddi4+0x2d4>
8000344: 42a0 cmp r0, r4
8000346: f240 809b bls.w 8000480 <__udivmoddi4+0x2d4>
800034a: f1a8 0802 sub.w r8, r8, #2
800034e: 443c add r4, r7
8000350: 1a24 subs r4, r4, r0
8000352: b298 uxth r0, r3
8000354: fbb4 f3f9 udiv r3, r4, r9
8000358: fb09 4413 mls r4, r9, r3, r4
800035c: fb03 fc0c mul.w ip, r3, ip
8000360: ea40 4404 orr.w r4, r0, r4, lsl #16
8000364: 45a4 cmp ip, r4
8000366: d909 bls.n 800037c <__udivmoddi4+0x1d0>
8000368: 193c adds r4, r7, r4
800036a: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff
800036e: f080 8085 bcs.w 800047c <__udivmoddi4+0x2d0>
8000372: 45a4 cmp ip, r4
8000374: f240 8082 bls.w 800047c <__udivmoddi4+0x2d0>
8000378: 3b02 subs r3, #2
800037a: 443c add r4, r7
800037c: ea43 4008 orr.w r0, r3, r8, lsl #16
8000380: eba4 040c sub.w r4, r4, ip
8000384: fba0 8c02 umull r8, ip, r0, r2
8000388: 4564 cmp r4, ip
800038a: 4643 mov r3, r8
800038c: 46e1 mov r9, ip
800038e: d364 bcc.n 800045a <__udivmoddi4+0x2ae>
8000390: d061 beq.n 8000456 <__udivmoddi4+0x2aa>
8000392: b15d cbz r5, 80003ac <__udivmoddi4+0x200>
8000394: ebbe 0203 subs.w r2, lr, r3
8000398: eb64 0409 sbc.w r4, r4, r9
800039c: fa04 f606 lsl.w r6, r4, r6
80003a0: fa22 f301 lsr.w r3, r2, r1
80003a4: 431e orrs r6, r3
80003a6: 40cc lsrs r4, r1
80003a8: e9c5 6400 strd r6, r4, [r5]
80003ac: 2100 movs r1, #0
80003ae: e74e b.n 800024e <__udivmoddi4+0xa2>
80003b0: fbb1 fcf2 udiv ip, r1, r2
80003b4: 0c01 lsrs r1, r0, #16
80003b6: ea41 410e orr.w r1, r1, lr, lsl #16
80003ba: b280 uxth r0, r0
80003bc: ea40 4201 orr.w r2, r0, r1, lsl #16
80003c0: 463b mov r3, r7
80003c2: fbb1 f1f7 udiv r1, r1, r7
80003c6: 4638 mov r0, r7
80003c8: 463c mov r4, r7
80003ca: 46b8 mov r8, r7
80003cc: 46be mov lr, r7
80003ce: 2620 movs r6, #32
80003d0: eba2 0208 sub.w r2, r2, r8
80003d4: ea41 410c orr.w r1, r1, ip, lsl #16
80003d8: e765 b.n 80002a6 <__udivmoddi4+0xfa>
80003da: 4601 mov r1, r0
80003dc: e717 b.n 800020e <__udivmoddi4+0x62>
80003de: 4610 mov r0, r2
80003e0: e72b b.n 800023a <__udivmoddi4+0x8e>
80003e2: f1c6 0120 rsb r1, r6, #32
80003e6: fa2e fc01 lsr.w ip, lr, r1
80003ea: 40b7 lsls r7, r6
80003ec: fa0e fe06 lsl.w lr, lr, r6
80003f0: fa20 f101 lsr.w r1, r0, r1
80003f4: ea41 010e orr.w r1, r1, lr
80003f8: ea4f 4e17 mov.w lr, r7, lsr #16
80003fc: fbbc f8fe udiv r8, ip, lr
8000400: b2bc uxth r4, r7
8000402: fb0e cc18 mls ip, lr, r8, ip
8000406: fb08 f904 mul.w r9, r8, r4
800040a: 0c0a lsrs r2, r1, #16
800040c: ea42 420c orr.w r2, r2, ip, lsl #16
8000410: 40b0 lsls r0, r6
8000412: 4591 cmp r9, r2
8000414: ea4f 4310 mov.w r3, r0, lsr #16
8000418: b280 uxth r0, r0
800041a: d93e bls.n 800049a <__udivmoddi4+0x2ee>
800041c: 18ba adds r2, r7, r2
800041e: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000422: d201 bcs.n 8000428 <__udivmoddi4+0x27c>
8000424: 4591 cmp r9, r2
8000426: d81f bhi.n 8000468 <__udivmoddi4+0x2bc>
8000428: eba2 0209 sub.w r2, r2, r9
800042c: fbb2 f9fe udiv r9, r2, lr
8000430: fb09 f804 mul.w r8, r9, r4
8000434: fb0e 2a19 mls sl, lr, r9, r2
8000438: b28a uxth r2, r1
800043a: ea42 420a orr.w r2, r2, sl, lsl #16
800043e: 4542 cmp r2, r8
8000440: d229 bcs.n 8000496 <__udivmoddi4+0x2ea>
8000442: 18ba adds r2, r7, r2
8000444: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
8000448: d2c2 bcs.n 80003d0 <__udivmoddi4+0x224>
800044a: 4542 cmp r2, r8
800044c: d2c0 bcs.n 80003d0 <__udivmoddi4+0x224>
800044e: f1a9 0102 sub.w r1, r9, #2
8000452: 443a add r2, r7
8000454: e7bc b.n 80003d0 <__udivmoddi4+0x224>
8000456: 45c6 cmp lr, r8
8000458: d29b bcs.n 8000392 <__udivmoddi4+0x1e6>
800045a: ebb8 0302 subs.w r3, r8, r2
800045e: eb6c 0c07 sbc.w ip, ip, r7
8000462: 3801 subs r0, #1
8000464: 46e1 mov r9, ip
8000466: e794 b.n 8000392 <__udivmoddi4+0x1e6>
8000468: eba7 0909 sub.w r9, r7, r9
800046c: 444a add r2, r9
800046e: fbb2 f9fe udiv r9, r2, lr
8000472: f1a8 0c02 sub.w ip, r8, #2
8000476: fb09 f804 mul.w r8, r9, r4
800047a: e7db b.n 8000434 <__udivmoddi4+0x288>
800047c: 4603 mov r3, r0
800047e: e77d b.n 800037c <__udivmoddi4+0x1d0>
8000480: 46d0 mov r8, sl
8000482: e765 b.n 8000350 <__udivmoddi4+0x1a4>
8000484: 4608 mov r0, r1
8000486: e6fa b.n 800027e <__udivmoddi4+0xd2>
8000488: 443b add r3, r7
800048a: 3a02 subs r2, #2
800048c: e730 b.n 80002f0 <__udivmoddi4+0x144>
800048e: f1ac 0c02 sub.w ip, ip, #2
8000492: 443b add r3, r7
8000494: e719 b.n 80002ca <__udivmoddi4+0x11e>
8000496: 4649 mov r1, r9
8000498: e79a b.n 80003d0 <__udivmoddi4+0x224>
800049a: eba2 0209 sub.w r2, r2, r9
800049e: fbb2 f9fe udiv r9, r2, lr
80004a2: 46c4 mov ip, r8
80004a4: fb09 f804 mul.w r8, r9, r4
80004a8: e7c4 b.n 8000434 <__udivmoddi4+0x288>
80004aa: bf00 nop
080004ac <__aeabi_idiv0>:
80004ac: 4770 bx lr
80004ae: bf00 nop
080004b0 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80004b0: b580 push {r7, lr}
80004b2: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004b4: f000 f9c9 bl 800084a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004b8: f000 f818 bl 80004ec <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004bc: f000 f88e bl 80005dc <MX_GPIO_Init>
MX_USART2_UART_Init();
80004c0: f000 f862 bl 8000588 <MX_USART2_UART_Init>
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
// Code V1 clignote version crade
*((uint32_t *)0x40020014) |= (1 << 5);
80004c4: 4b08 ldr r3, [pc, #32] @ (80004e8 <main+0x38>)
80004c6: 681b ldr r3, [r3, #0]
80004c8: 4a07 ldr r2, [pc, #28] @ (80004e8 <main+0x38>)
80004ca: f043 0320 orr.w r3, r3, #32
80004ce: 6013 str r3, [r2, #0]
HAL_Delay(1000);
80004d0: f44f 707a mov.w r0, #1000 @ 0x3e8
80004d4: f000 fa28 bl 8000928 <HAL_Delay>
*((uint32_t *)0x40020014) &= ~(1 << 5);
80004d8: 4b03 ldr r3, [pc, #12] @ (80004e8 <main+0x38>)
80004da: 681b ldr r3, [r3, #0]
80004dc: 4a02 ldr r2, [pc, #8] @ (80004e8 <main+0x38>)
80004de: f023 0320 bic.w r3, r3, #32
80004e2: 6013 str r3, [r2, #0]
*((uint32_t *)0x40020014) |= (1 << 5);
80004e4: bf00 nop
80004e6: e7ed b.n 80004c4 <main+0x14>
80004e8: 40020014 .word 0x40020014
080004ec <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80004ec: b580 push {r7, lr}
80004ee: b092 sub sp, #72 @ 0x48
80004f0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80004f2: f107 0314 add.w r3, r7, #20
80004f6: 2234 movs r2, #52 @ 0x34
80004f8: 2100 movs r1, #0
80004fa: 4618 mov r0, r3
80004fc: f001 fbec bl 8001cd8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000500: 463b mov r3, r7
8000502: 2200 movs r2, #0
8000504: 601a str r2, [r3, #0]
8000506: 605a str r2, [r3, #4]
8000508: 609a str r2, [r3, #8]
800050a: 60da str r2, [r3, #12]
800050c: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
800050e: 4b1d ldr r3, [pc, #116] @ (8000584 <SystemClock_Config+0x98>)
8000510: 681b ldr r3, [r3, #0]
8000512: f423 53c0 bic.w r3, r3, #6144 @ 0x1800
8000516: 4a1b ldr r2, [pc, #108] @ (8000584 <SystemClock_Config+0x98>)
8000518: f443 6300 orr.w r3, r3, #2048 @ 0x800
800051c: 6013 str r3, [r2, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800051e: 2302 movs r3, #2
8000520: 617b str r3, [r7, #20]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000522: 2301 movs r3, #1
8000524: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000526: 2310 movs r3, #16
8000528: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800052a: 2302 movs r3, #2
800052c: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
800052e: 2300 movs r3, #0
8000530: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
8000532: f44f 2300 mov.w r3, #524288 @ 0x80000
8000536: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
8000538: f44f 0300 mov.w r3, #8388608 @ 0x800000
800053c: 647b str r3, [r7, #68] @ 0x44
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800053e: f107 0314 add.w r3, r7, #20
8000542: 4618 mov r0, r3
8000544: f000 fc9e bl 8000e84 <HAL_RCC_OscConfig>
8000548: 4603 mov r3, r0
800054a: 2b00 cmp r3, #0
800054c: d001 beq.n 8000552 <SystemClock_Config+0x66>
{
Error_Handler();
800054e: f000 f8ab bl 80006a8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000552: 230f movs r3, #15
8000554: 603b str r3, [r7, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000556: 2303 movs r3, #3
8000558: 607b str r3, [r7, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800055a: 2300 movs r3, #0
800055c: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800055e: 2300 movs r3, #0
8000560: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000562: 2300 movs r3, #0
8000564: 613b str r3, [r7, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
8000566: 463b mov r3, r7
8000568: 2101 movs r1, #1
800056a: 4618 mov r0, r3
800056c: f000 ffba bl 80014e4 <HAL_RCC_ClockConfig>
8000570: 4603 mov r3, r0
8000572: 2b00 cmp r3, #0
8000574: d001 beq.n 800057a <SystemClock_Config+0x8e>
{
Error_Handler();
8000576: f000 f897 bl 80006a8 <Error_Handler>
}
}
800057a: bf00 nop
800057c: 3748 adds r7, #72 @ 0x48
800057e: 46bd mov sp, r7
8000580: bd80 pop {r7, pc}
8000582: bf00 nop
8000584: 40007000 .word 0x40007000
08000588 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
8000588: b580 push {r7, lr}
800058a: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
800058c: 4b11 ldr r3, [pc, #68] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
800058e: 4a12 ldr r2, [pc, #72] @ (80005d8 <MX_USART2_UART_Init+0x50>)
8000590: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8000592: 4b10 ldr r3, [pc, #64] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
8000594: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000598: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800059a: 4b0e ldr r3, [pc, #56] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
800059c: 2200 movs r2, #0
800059e: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
80005a0: 4b0c ldr r3, [pc, #48] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
80005a2: 2200 movs r2, #0
80005a4: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
80005a6: 4b0b ldr r3, [pc, #44] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
80005a8: 2200 movs r2, #0
80005aa: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
80005ac: 4b09 ldr r3, [pc, #36] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
80005ae: 220c movs r2, #12
80005b0: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80005b2: 4b08 ldr r3, [pc, #32] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
80005b4: 2200 movs r2, #0
80005b6: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
80005b8: 4b06 ldr r3, [pc, #24] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
80005ba: 2200 movs r2, #0
80005bc: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
80005be: 4805 ldr r0, [pc, #20] @ (80005d4 <MX_USART2_UART_Init+0x4c>)
80005c0: f001 fa56 bl 8001a70 <HAL_UART_Init>
80005c4: 4603 mov r3, r0
80005c6: 2b00 cmp r3, #0
80005c8: d001 beq.n 80005ce <MX_USART2_UART_Init+0x46>
{
Error_Handler();
80005ca: f000 f86d bl 80006a8 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
80005ce: bf00 nop
80005d0: bd80 pop {r7, pc}
80005d2: bf00 nop
80005d4: 20000028 .word 0x20000028
80005d8: 40004400 .word 0x40004400
080005dc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80005dc: b580 push {r7, lr}
80005de: b08a sub sp, #40 @ 0x28
80005e0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80005e2: f107 0314 add.w r3, r7, #20
80005e6: 2200 movs r2, #0
80005e8: 601a str r2, [r3, #0]
80005ea: 605a str r2, [r3, #4]
80005ec: 609a str r2, [r3, #8]
80005ee: 60da str r2, [r3, #12]
80005f0: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80005f2: 4b2a ldr r3, [pc, #168] @ (800069c <MX_GPIO_Init+0xc0>)
80005f4: 69db ldr r3, [r3, #28]
80005f6: 4a29 ldr r2, [pc, #164] @ (800069c <MX_GPIO_Init+0xc0>)
80005f8: f043 0304 orr.w r3, r3, #4
80005fc: 61d3 str r3, [r2, #28]
80005fe: 4b27 ldr r3, [pc, #156] @ (800069c <MX_GPIO_Init+0xc0>)
8000600: 69db ldr r3, [r3, #28]
8000602: f003 0304 and.w r3, r3, #4
8000606: 613b str r3, [r7, #16]
8000608: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
800060a: 4b24 ldr r3, [pc, #144] @ (800069c <MX_GPIO_Init+0xc0>)
800060c: 69db ldr r3, [r3, #28]
800060e: 4a23 ldr r2, [pc, #140] @ (800069c <MX_GPIO_Init+0xc0>)
8000610: f043 0320 orr.w r3, r3, #32
8000614: 61d3 str r3, [r2, #28]
8000616: 4b21 ldr r3, [pc, #132] @ (800069c <MX_GPIO_Init+0xc0>)
8000618: 69db ldr r3, [r3, #28]
800061a: f003 0320 and.w r3, r3, #32
800061e: 60fb str r3, [r7, #12]
8000620: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000622: 4b1e ldr r3, [pc, #120] @ (800069c <MX_GPIO_Init+0xc0>)
8000624: 69db ldr r3, [r3, #28]
8000626: 4a1d ldr r2, [pc, #116] @ (800069c <MX_GPIO_Init+0xc0>)
8000628: f043 0301 orr.w r3, r3, #1
800062c: 61d3 str r3, [r2, #28]
800062e: 4b1b ldr r3, [pc, #108] @ (800069c <MX_GPIO_Init+0xc0>)
8000630: 69db ldr r3, [r3, #28]
8000632: f003 0301 and.w r3, r3, #1
8000636: 60bb str r3, [r7, #8]
8000638: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
800063a: 4b18 ldr r3, [pc, #96] @ (800069c <MX_GPIO_Init+0xc0>)
800063c: 69db ldr r3, [r3, #28]
800063e: 4a17 ldr r2, [pc, #92] @ (800069c <MX_GPIO_Init+0xc0>)
8000640: f043 0302 orr.w r3, r3, #2
8000644: 61d3 str r3, [r2, #28]
8000646: 4b15 ldr r3, [pc, #84] @ (800069c <MX_GPIO_Init+0xc0>)
8000648: 69db ldr r3, [r3, #28]
800064a: f003 0302 and.w r3, r3, #2
800064e: 607b str r3, [r7, #4]
8000650: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000652: 2200 movs r2, #0
8000654: 2120 movs r1, #32
8000656: 4812 ldr r0, [pc, #72] @ (80006a0 <MX_GPIO_Init+0xc4>)
8000658: f000 fbfc bl 8000e54 <HAL_GPIO_WritePin>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
800065c: f44f 5300 mov.w r3, #8192 @ 0x2000
8000660: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8000662: f44f 1388 mov.w r3, #1114112 @ 0x110000
8000666: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000668: 2300 movs r3, #0
800066a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
800066c: f107 0314 add.w r3, r7, #20
8000670: 4619 mov r1, r3
8000672: 480c ldr r0, [pc, #48] @ (80006a4 <MX_GPIO_Init+0xc8>)
8000674: f000 fa5e bl 8000b34 <HAL_GPIO_Init>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
8000678: 2320 movs r3, #32
800067a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800067c: 2301 movs r3, #1
800067e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000680: 2300 movs r3, #0
8000682: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000684: 2300 movs r3, #0
8000686: 623b str r3, [r7, #32]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
8000688: f107 0314 add.w r3, r7, #20
800068c: 4619 mov r1, r3
800068e: 4804 ldr r0, [pc, #16] @ (80006a0 <MX_GPIO_Init+0xc4>)
8000690: f000 fa50 bl 8000b34 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000694: bf00 nop
8000696: 3728 adds r7, #40 @ 0x28
8000698: 46bd mov sp, r7
800069a: bd80 pop {r7, pc}
800069c: 40023800 .word 0x40023800
80006a0: 40020000 .word 0x40020000
80006a4: 40020800 .word 0x40020800
080006a8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80006a8: b480 push {r7}
80006aa: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80006ac: b672 cpsid i
}
80006ae: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80006b0: bf00 nop
80006b2: e7fd b.n 80006b0 <Error_Handler+0x8>
080006b4 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80006b4: b580 push {r7, lr}
80006b6: b084 sub sp, #16
80006b8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_COMP_CLK_ENABLE();
80006ba: 4b15 ldr r3, [pc, #84] @ (8000710 <HAL_MspInit+0x5c>)
80006bc: 6a5b ldr r3, [r3, #36] @ 0x24
80006be: 4a14 ldr r2, [pc, #80] @ (8000710 <HAL_MspInit+0x5c>)
80006c0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
80006c4: 6253 str r3, [r2, #36] @ 0x24
80006c6: 4b12 ldr r3, [pc, #72] @ (8000710 <HAL_MspInit+0x5c>)
80006c8: 6a5b ldr r3, [r3, #36] @ 0x24
80006ca: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80006ce: 60fb str r3, [r7, #12]
80006d0: 68fb ldr r3, [r7, #12]
__HAL_RCC_SYSCFG_CLK_ENABLE();
80006d2: 4b0f ldr r3, [pc, #60] @ (8000710 <HAL_MspInit+0x5c>)
80006d4: 6a1b ldr r3, [r3, #32]
80006d6: 4a0e ldr r2, [pc, #56] @ (8000710 <HAL_MspInit+0x5c>)
80006d8: f043 0301 orr.w r3, r3, #1
80006dc: 6213 str r3, [r2, #32]
80006de: 4b0c ldr r3, [pc, #48] @ (8000710 <HAL_MspInit+0x5c>)
80006e0: 6a1b ldr r3, [r3, #32]
80006e2: f003 0301 and.w r3, r3, #1
80006e6: 60bb str r3, [r7, #8]
80006e8: 68bb ldr r3, [r7, #8]
__HAL_RCC_PWR_CLK_ENABLE();
80006ea: 4b09 ldr r3, [pc, #36] @ (8000710 <HAL_MspInit+0x5c>)
80006ec: 6a5b ldr r3, [r3, #36] @ 0x24
80006ee: 4a08 ldr r2, [pc, #32] @ (8000710 <HAL_MspInit+0x5c>)
80006f0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80006f4: 6253 str r3, [r2, #36] @ 0x24
80006f6: 4b06 ldr r3, [pc, #24] @ (8000710 <HAL_MspInit+0x5c>)
80006f8: 6a5b ldr r3, [r3, #36] @ 0x24
80006fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80006fe: 607b str r3, [r7, #4]
8000700: 687b ldr r3, [r7, #4]
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
8000702: 2007 movs r0, #7
8000704: f000 f9e2 bl 8000acc <HAL_NVIC_SetPriorityGrouping>
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000708: bf00 nop
800070a: 3710 adds r7, #16
800070c: 46bd mov sp, r7
800070e: bd80 pop {r7, pc}
8000710: 40023800 .word 0x40023800
08000714 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000714: b580 push {r7, lr}
8000716: b08a sub sp, #40 @ 0x28
8000718: af00 add r7, sp, #0
800071a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800071c: f107 0314 add.w r3, r7, #20
8000720: 2200 movs r2, #0
8000722: 601a str r2, [r3, #0]
8000724: 605a str r2, [r3, #4]
8000726: 609a str r2, [r3, #8]
8000728: 60da str r2, [r3, #12]
800072a: 611a str r2, [r3, #16]
if(huart->Instance==USART2)
800072c: 687b ldr r3, [r7, #4]
800072e: 681b ldr r3, [r3, #0]
8000730: 4a17 ldr r2, [pc, #92] @ (8000790 <HAL_UART_MspInit+0x7c>)
8000732: 4293 cmp r3, r2
8000734: d127 bne.n 8000786 <HAL_UART_MspInit+0x72>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
8000736: 4b17 ldr r3, [pc, #92] @ (8000794 <HAL_UART_MspInit+0x80>)
8000738: 6a5b ldr r3, [r3, #36] @ 0x24
800073a: 4a16 ldr r2, [pc, #88] @ (8000794 <HAL_UART_MspInit+0x80>)
800073c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8000740: 6253 str r3, [r2, #36] @ 0x24
8000742: 4b14 ldr r3, [pc, #80] @ (8000794 <HAL_UART_MspInit+0x80>)
8000744: 6a5b ldr r3, [r3, #36] @ 0x24
8000746: f403 3300 and.w r3, r3, #131072 @ 0x20000
800074a: 613b str r3, [r7, #16]
800074c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800074e: 4b11 ldr r3, [pc, #68] @ (8000794 <HAL_UART_MspInit+0x80>)
8000750: 69db ldr r3, [r3, #28]
8000752: 4a10 ldr r2, [pc, #64] @ (8000794 <HAL_UART_MspInit+0x80>)
8000754: f043 0301 orr.w r3, r3, #1
8000758: 61d3 str r3, [r2, #28]
800075a: 4b0e ldr r3, [pc, #56] @ (8000794 <HAL_UART_MspInit+0x80>)
800075c: 69db ldr r3, [r3, #28]
800075e: f003 0301 and.w r3, r3, #1
8000762: 60fb str r3, [r7, #12]
8000764: 68fb ldr r3, [r7, #12]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
8000766: 230c movs r3, #12
8000768: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800076a: 2302 movs r3, #2
800076c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800076e: 2300 movs r3, #0
8000770: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000772: 2303 movs r3, #3
8000774: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000776: 2307 movs r3, #7
8000778: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800077a: f107 0314 add.w r3, r7, #20
800077e: 4619 mov r1, r3
8000780: 4805 ldr r0, [pc, #20] @ (8000798 <HAL_UART_MspInit+0x84>)
8000782: f000 f9d7 bl 8000b34 <HAL_GPIO_Init>
/* USER CODE END USART2_MspInit 1 */
}
}
8000786: bf00 nop
8000788: 3728 adds r7, #40 @ 0x28
800078a: 46bd mov sp, r7
800078c: bd80 pop {r7, pc}
800078e: bf00 nop
8000790: 40004400 .word 0x40004400
8000794: 40023800 .word 0x40023800
8000798: 40020000 .word 0x40020000
0800079c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800079c: b480 push {r7}
800079e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80007a0: bf00 nop
80007a2: e7fd b.n 80007a0 <NMI_Handler+0x4>
080007a4 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80007a4: b480 push {r7}
80007a6: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80007a8: bf00 nop
80007aa: e7fd b.n 80007a8 <HardFault_Handler+0x4>
080007ac <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80007ac: b480 push {r7}
80007ae: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80007b0: bf00 nop
80007b2: e7fd b.n 80007b0 <MemManage_Handler+0x4>
080007b4 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80007b4: b480 push {r7}
80007b6: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80007b8: bf00 nop
80007ba: e7fd b.n 80007b8 <BusFault_Handler+0x4>
080007bc <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80007bc: b480 push {r7}
80007be: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80007c0: bf00 nop
80007c2: e7fd b.n 80007c0 <UsageFault_Handler+0x4>
080007c4 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80007c4: b480 push {r7}
80007c6: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
80007c8: bf00 nop
80007ca: 46bd mov sp, r7
80007cc: bc80 pop {r7}
80007ce: 4770 bx lr
080007d0 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80007d0: b480 push {r7}
80007d2: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80007d4: bf00 nop
80007d6: 46bd mov sp, r7
80007d8: bc80 pop {r7}
80007da: 4770 bx lr
080007dc <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80007dc: b480 push {r7}
80007de: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80007e0: bf00 nop
80007e2: 46bd mov sp, r7
80007e4: bc80 pop {r7}
80007e6: 4770 bx lr
080007e8 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80007e8: b580 push {r7, lr}
80007ea: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80007ec: f000 f880 bl 80008f0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80007f0: bf00 nop
80007f2: bd80 pop {r7, pc}
080007f4 <SystemInit>:
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
80007f4: b480 push {r7}
80007f6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
80007f8: bf00 nop
80007fa: 46bd mov sp, r7
80007fc: bc80 pop {r7}
80007fe: 4770 bx lr
08000800 <Reset_Handler>:
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
8000800: f7ff fff8 bl 80007f4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000804: 480b ldr r0, [pc, #44] @ (8000834 <LoopFillZerobss+0xe>)
ldr r1, =_edata
8000806: 490c ldr r1, [pc, #48] @ (8000838 <LoopFillZerobss+0x12>)
ldr r2, =_sidata
8000808: 4a0c ldr r2, [pc, #48] @ (800083c <LoopFillZerobss+0x16>)
movs r3, #0
800080a: 2300 movs r3, #0
b LoopCopyDataInit
800080c: e002 b.n 8000814 <LoopCopyDataInit>
0800080e <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
800080e: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000810: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000812: 3304 adds r3, #4
08000814 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000814: 18c4 adds r4, r0, r3
cmp r4, r1
8000816: 428c cmp r4, r1
bcc CopyDataInit
8000818: d3f9 bcc.n 800080e <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800081a: 4a09 ldr r2, [pc, #36] @ (8000840 <LoopFillZerobss+0x1a>)
ldr r4, =_ebss
800081c: 4c09 ldr r4, [pc, #36] @ (8000844 <LoopFillZerobss+0x1e>)
movs r3, #0
800081e: 2300 movs r3, #0
b LoopFillZerobss
8000820: e001 b.n 8000826 <LoopFillZerobss>
08000822 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000822: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000824: 3204 adds r2, #4
08000826 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000826: 42a2 cmp r2, r4
bcc FillZerobss
8000828: d3fb bcc.n 8000822 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800082a: f001 fa5d bl 8001ce8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800082e: f7ff fe3f bl 80004b0 <main>
bx lr
8000832: 4770 bx lr
ldr r0, =_sdata
8000834: 20000000 .word 0x20000000
ldr r1, =_edata
8000838: 2000000c .word 0x2000000c
ldr r2, =_sidata
800083c: 08001d7c .word 0x08001d7c
ldr r2, =_sbss
8000840: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000844: 20000074 .word 0x20000074
08000848 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000848: e7fe b.n 8000848 <ADC1_IRQHandler>
0800084a <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800084a: b580 push {r7, lr}
800084c: b082 sub sp, #8
800084e: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8000850: 2300 movs r3, #0
8000852: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000854: 2003 movs r0, #3
8000856: f000 f939 bl 8000acc <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
800085a: 2000 movs r0, #0
800085c: f000 f80e bl 800087c <HAL_InitTick>
8000860: 4603 mov r3, r0
8000862: 2b00 cmp r3, #0
8000864: d002 beq.n 800086c <HAL_Init+0x22>
{
status = HAL_ERROR;
8000866: 2301 movs r3, #1
8000868: 71fb strb r3, [r7, #7]
800086a: e001 b.n 8000870 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
800086c: f7ff ff22 bl 80006b4 <HAL_MspInit>
}
/* Return function status */
return status;
8000870: 79fb ldrb r3, [r7, #7]
}
8000872: 4618 mov r0, r3
8000874: 3708 adds r7, #8
8000876: 46bd mov sp, r7
8000878: bd80 pop {r7, pc}
...
0800087c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
800087c: b580 push {r7, lr}
800087e: b084 sub sp, #16
8000880: af00 add r7, sp, #0
8000882: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8000884: 2300 movs r3, #0
8000886: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8000888: 4b16 ldr r3, [pc, #88] @ (80008e4 <HAL_InitTick+0x68>)
800088a: 681b ldr r3, [r3, #0]
800088c: 2b00 cmp r3, #0
800088e: d022 beq.n 80008d6 <HAL_InitTick+0x5a>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8000890: 4b15 ldr r3, [pc, #84] @ (80008e8 <HAL_InitTick+0x6c>)
8000892: 681a ldr r2, [r3, #0]
8000894: 4b13 ldr r3, [pc, #76] @ (80008e4 <HAL_InitTick+0x68>)
8000896: 681b ldr r3, [r3, #0]
8000898: f44f 717a mov.w r1, #1000 @ 0x3e8
800089c: fbb1 f3f3 udiv r3, r1, r3
80008a0: fbb2 f3f3 udiv r3, r2, r3
80008a4: 4618 mov r0, r3
80008a6: f000 f938 bl 8000b1a <HAL_SYSTICK_Config>
80008aa: 4603 mov r3, r0
80008ac: 2b00 cmp r3, #0
80008ae: d10f bne.n 80008d0 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80008b0: 687b ldr r3, [r7, #4]
80008b2: 2b0f cmp r3, #15
80008b4: d809 bhi.n 80008ca <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80008b6: 2200 movs r2, #0
80008b8: 6879 ldr r1, [r7, #4]
80008ba: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
80008be: f000 f910 bl 8000ae2 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80008c2: 4a0a ldr r2, [pc, #40] @ (80008ec <HAL_InitTick+0x70>)
80008c4: 687b ldr r3, [r7, #4]
80008c6: 6013 str r3, [r2, #0]
80008c8: e007 b.n 80008da <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
80008ca: 2301 movs r3, #1
80008cc: 73fb strb r3, [r7, #15]
80008ce: e004 b.n 80008da <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
80008d0: 2301 movs r3, #1
80008d2: 73fb strb r3, [r7, #15]
80008d4: e001 b.n 80008da <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
80008d6: 2301 movs r3, #1
80008d8: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
80008da: 7bfb ldrb r3, [r7, #15]
}
80008dc: 4618 mov r0, r3
80008de: 3710 adds r7, #16
80008e0: 46bd mov sp, r7
80008e2: bd80 pop {r7, pc}
80008e4: 20000008 .word 0x20000008
80008e8: 20000000 .word 0x20000000
80008ec: 20000004 .word 0x20000004
080008f0 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80008f0: b480 push {r7}
80008f2: af00 add r7, sp, #0
uwTick += uwTickFreq;
80008f4: 4b05 ldr r3, [pc, #20] @ (800090c <HAL_IncTick+0x1c>)
80008f6: 681a ldr r2, [r3, #0]
80008f8: 4b05 ldr r3, [pc, #20] @ (8000910 <HAL_IncTick+0x20>)
80008fa: 681b ldr r3, [r3, #0]
80008fc: 4413 add r3, r2
80008fe: 4a03 ldr r2, [pc, #12] @ (800090c <HAL_IncTick+0x1c>)
8000900: 6013 str r3, [r2, #0]
}
8000902: bf00 nop
8000904: 46bd mov sp, r7
8000906: bc80 pop {r7}
8000908: 4770 bx lr
800090a: bf00 nop
800090c: 20000070 .word 0x20000070
8000910: 20000008 .word 0x20000008
08000914 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000914: b480 push {r7}
8000916: af00 add r7, sp, #0
return uwTick;
8000918: 4b02 ldr r3, [pc, #8] @ (8000924 <HAL_GetTick+0x10>)
800091a: 681b ldr r3, [r3, #0]
}
800091c: 4618 mov r0, r3
800091e: 46bd mov sp, r7
8000920: bc80 pop {r7}
8000922: 4770 bx lr
8000924: 20000070 .word 0x20000070
08000928 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000928: b580 push {r7, lr}
800092a: b084 sub sp, #16
800092c: af00 add r7, sp, #0
800092e: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000930: f7ff fff0 bl 8000914 <HAL_GetTick>
8000934: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000936: 687b ldr r3, [r7, #4]
8000938: 60fb str r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
800093a: 68fb ldr r3, [r7, #12]
800093c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8000940: d004 beq.n 800094c <HAL_Delay+0x24>
{
wait += (uint32_t)(uwTickFreq);
8000942: 4b09 ldr r3, [pc, #36] @ (8000968 <HAL_Delay+0x40>)
8000944: 681b ldr r3, [r3, #0]
8000946: 68fa ldr r2, [r7, #12]
8000948: 4413 add r3, r2
800094a: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
800094c: bf00 nop
800094e: f7ff ffe1 bl 8000914 <HAL_GetTick>
8000952: 4602 mov r2, r0
8000954: 68bb ldr r3, [r7, #8]
8000956: 1ad3 subs r3, r2, r3
8000958: 68fa ldr r2, [r7, #12]
800095a: 429a cmp r2, r3
800095c: d8f7 bhi.n 800094e <HAL_Delay+0x26>
{
}
}
800095e: bf00 nop
8000960: bf00 nop
8000962: 3710 adds r7, #16
8000964: 46bd mov sp, r7
8000966: bd80 pop {r7, pc}
8000968: 20000008 .word 0x20000008
0800096c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800096c: b480 push {r7}
800096e: b085 sub sp, #20
8000970: af00 add r7, sp, #0
8000972: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000974: 687b ldr r3, [r7, #4]
8000976: f003 0307 and.w r3, r3, #7
800097a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
800097c: 4b0c ldr r3, [pc, #48] @ (80009b0 <__NVIC_SetPriorityGrouping+0x44>)
800097e: 68db ldr r3, [r3, #12]
8000980: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000982: 68ba ldr r2, [r7, #8]
8000984: f64f 03ff movw r3, #63743 @ 0xf8ff
8000988: 4013 ands r3, r2
800098a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
800098c: 68fb ldr r3, [r7, #12]
800098e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000990: 68bb ldr r3, [r7, #8]
8000992: 4313 orrs r3, r2
reg_value = (reg_value |
8000994: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8000998: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800099c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800099e: 4a04 ldr r2, [pc, #16] @ (80009b0 <__NVIC_SetPriorityGrouping+0x44>)
80009a0: 68bb ldr r3, [r7, #8]
80009a2: 60d3 str r3, [r2, #12]
}
80009a4: bf00 nop
80009a6: 3714 adds r7, #20
80009a8: 46bd mov sp, r7
80009aa: bc80 pop {r7}
80009ac: 4770 bx lr
80009ae: bf00 nop
80009b0: e000ed00 .word 0xe000ed00
080009b4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80009b4: b480 push {r7}
80009b6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80009b8: 4b04 ldr r3, [pc, #16] @ (80009cc <__NVIC_GetPriorityGrouping+0x18>)
80009ba: 68db ldr r3, [r3, #12]
80009bc: 0a1b lsrs r3, r3, #8
80009be: f003 0307 and.w r3, r3, #7
}
80009c2: 4618 mov r0, r3
80009c4: 46bd mov sp, r7
80009c6: bc80 pop {r7}
80009c8: 4770 bx lr
80009ca: bf00 nop
80009cc: e000ed00 .word 0xe000ed00
080009d0 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80009d0: b480 push {r7}
80009d2: b083 sub sp, #12
80009d4: af00 add r7, sp, #0
80009d6: 4603 mov r3, r0
80009d8: 6039 str r1, [r7, #0]
80009da: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80009dc: f997 3007 ldrsb.w r3, [r7, #7]
80009e0: 2b00 cmp r3, #0
80009e2: db0a blt.n 80009fa <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80009e4: 683b ldr r3, [r7, #0]
80009e6: b2da uxtb r2, r3
80009e8: 490c ldr r1, [pc, #48] @ (8000a1c <__NVIC_SetPriority+0x4c>)
80009ea: f997 3007 ldrsb.w r3, [r7, #7]
80009ee: 0112 lsls r2, r2, #4
80009f0: b2d2 uxtb r2, r2
80009f2: 440b add r3, r1
80009f4: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80009f8: e00a b.n 8000a10 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80009fa: 683b ldr r3, [r7, #0]
80009fc: b2da uxtb r2, r3
80009fe: 4908 ldr r1, [pc, #32] @ (8000a20 <__NVIC_SetPriority+0x50>)
8000a00: 79fb ldrb r3, [r7, #7]
8000a02: f003 030f and.w r3, r3, #15
8000a06: 3b04 subs r3, #4
8000a08: 0112 lsls r2, r2, #4
8000a0a: b2d2 uxtb r2, r2
8000a0c: 440b add r3, r1
8000a0e: 761a strb r2, [r3, #24]
}
8000a10: bf00 nop
8000a12: 370c adds r7, #12
8000a14: 46bd mov sp, r7
8000a16: bc80 pop {r7}
8000a18: 4770 bx lr
8000a1a: bf00 nop
8000a1c: e000e100 .word 0xe000e100
8000a20: e000ed00 .word 0xe000ed00
08000a24 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000a24: b480 push {r7}
8000a26: b089 sub sp, #36 @ 0x24
8000a28: af00 add r7, sp, #0
8000a2a: 60f8 str r0, [r7, #12]
8000a2c: 60b9 str r1, [r7, #8]
8000a2e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000a30: 68fb ldr r3, [r7, #12]
8000a32: f003 0307 and.w r3, r3, #7
8000a36: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000a38: 69fb ldr r3, [r7, #28]
8000a3a: f1c3 0307 rsb r3, r3, #7
8000a3e: 2b04 cmp r3, #4
8000a40: bf28 it cs
8000a42: 2304 movcs r3, #4
8000a44: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000a46: 69fb ldr r3, [r7, #28]
8000a48: 3304 adds r3, #4
8000a4a: 2b06 cmp r3, #6
8000a4c: d902 bls.n 8000a54 <NVIC_EncodePriority+0x30>
8000a4e: 69fb ldr r3, [r7, #28]
8000a50: 3b03 subs r3, #3
8000a52: e000 b.n 8000a56 <NVIC_EncodePriority+0x32>
8000a54: 2300 movs r3, #0
8000a56: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000a58: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
8000a5c: 69bb ldr r3, [r7, #24]
8000a5e: fa02 f303 lsl.w r3, r2, r3
8000a62: 43da mvns r2, r3
8000a64: 68bb ldr r3, [r7, #8]
8000a66: 401a ands r2, r3
8000a68: 697b ldr r3, [r7, #20]
8000a6a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000a6c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
8000a70: 697b ldr r3, [r7, #20]
8000a72: fa01 f303 lsl.w r3, r1, r3
8000a76: 43d9 mvns r1, r3
8000a78: 687b ldr r3, [r7, #4]
8000a7a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000a7c: 4313 orrs r3, r2
);
}
8000a7e: 4618 mov r0, r3
8000a80: 3724 adds r7, #36 @ 0x24
8000a82: 46bd mov sp, r7
8000a84: bc80 pop {r7}
8000a86: 4770 bx lr
08000a88 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000a88: b580 push {r7, lr}
8000a8a: b082 sub sp, #8
8000a8c: af00 add r7, sp, #0
8000a8e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000a90: 687b ldr r3, [r7, #4]
8000a92: 3b01 subs r3, #1
8000a94: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8000a98: d301 bcc.n 8000a9e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000a9a: 2301 movs r3, #1
8000a9c: e00f b.n 8000abe <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000a9e: 4a0a ldr r2, [pc, #40] @ (8000ac8 <SysTick_Config+0x40>)
8000aa0: 687b ldr r3, [r7, #4]
8000aa2: 3b01 subs r3, #1
8000aa4: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000aa6: 210f movs r1, #15
8000aa8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
8000aac: f7ff ff90 bl 80009d0 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000ab0: 4b05 ldr r3, [pc, #20] @ (8000ac8 <SysTick_Config+0x40>)
8000ab2: 2200 movs r2, #0
8000ab4: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000ab6: 4b04 ldr r3, [pc, #16] @ (8000ac8 <SysTick_Config+0x40>)
8000ab8: 2207 movs r2, #7
8000aba: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000abc: 2300 movs r3, #0
}
8000abe: 4618 mov r0, r3
8000ac0: 3708 adds r7, #8
8000ac2: 46bd mov sp, r7
8000ac4: bd80 pop {r7, pc}
8000ac6: bf00 nop
8000ac8: e000e010 .word 0xe000e010
08000acc <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000acc: b580 push {r7, lr}
8000ace: b082 sub sp, #8
8000ad0: af00 add r7, sp, #0
8000ad2: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000ad4: 6878 ldr r0, [r7, #4]
8000ad6: f7ff ff49 bl 800096c <__NVIC_SetPriorityGrouping>
}
8000ada: bf00 nop
8000adc: 3708 adds r7, #8
8000ade: 46bd mov sp, r7
8000ae0: bd80 pop {r7, pc}
08000ae2 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000ae2: b580 push {r7, lr}
8000ae4: b086 sub sp, #24
8000ae6: af00 add r7, sp, #0
8000ae8: 4603 mov r3, r0
8000aea: 60b9 str r1, [r7, #8]
8000aec: 607a str r2, [r7, #4]
8000aee: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8000af0: 2300 movs r3, #0
8000af2: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000af4: f7ff ff5e bl 80009b4 <__NVIC_GetPriorityGrouping>
8000af8: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000afa: 687a ldr r2, [r7, #4]
8000afc: 68b9 ldr r1, [r7, #8]
8000afe: 6978 ldr r0, [r7, #20]
8000b00: f7ff ff90 bl 8000a24 <NVIC_EncodePriority>
8000b04: 4602 mov r2, r0
8000b06: f997 300f ldrsb.w r3, [r7, #15]
8000b0a: 4611 mov r1, r2
8000b0c: 4618 mov r0, r3
8000b0e: f7ff ff5f bl 80009d0 <__NVIC_SetPriority>
}
8000b12: bf00 nop
8000b14: 3718 adds r7, #24
8000b16: 46bd mov sp, r7
8000b18: bd80 pop {r7, pc}
08000b1a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000b1a: b580 push {r7, lr}
8000b1c: b082 sub sp, #8
8000b1e: af00 add r7, sp, #0
8000b20: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000b22: 6878 ldr r0, [r7, #4]
8000b24: f7ff ffb0 bl 8000a88 <SysTick_Config>
8000b28: 4603 mov r3, r0
}
8000b2a: 4618 mov r0, r3
8000b2c: 3708 adds r7, #8
8000b2e: 46bd mov sp, r7
8000b30: bd80 pop {r7, pc}
...
08000b34 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000b34: b480 push {r7}
8000b36: b087 sub sp, #28
8000b38: af00 add r7, sp, #0
8000b3a: 6078 str r0, [r7, #4]
8000b3c: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
8000b3e: 2300 movs r3, #0
8000b40: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
8000b42: 2300 movs r3, #0
8000b44: 60fb str r3, [r7, #12]
uint32_t temp = 0x00;
8000b46: 2300 movs r3, #0
8000b48: 613b str r3, [r7, #16]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0)
8000b4a: e160 b.n 8000e0e <HAL_GPIO_Init+0x2da>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
8000b4c: 683b ldr r3, [r7, #0]
8000b4e: 681a ldr r2, [r3, #0]
8000b50: 2101 movs r1, #1
8000b52: 697b ldr r3, [r7, #20]
8000b54: fa01 f303 lsl.w r3, r1, r3
8000b58: 4013 ands r3, r2
8000b5a: 60fb str r3, [r7, #12]
if (iocurrent)
8000b5c: 68fb ldr r3, [r7, #12]
8000b5e: 2b00 cmp r3, #0
8000b60: f000 8152 beq.w 8000e08 <HAL_GPIO_Init+0x2d4>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000b64: 683b ldr r3, [r7, #0]
8000b66: 685b ldr r3, [r3, #4]
8000b68: f003 0303 and.w r3, r3, #3
8000b6c: 2b01 cmp r3, #1
8000b6e: d005 beq.n 8000b7c <HAL_GPIO_Init+0x48>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8000b70: 683b ldr r3, [r7, #0]
8000b72: 685b ldr r3, [r3, #4]
8000b74: f003 0303 and.w r3, r3, #3
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8000b78: 2b02 cmp r3, #2
8000b7a: d130 bne.n 8000bde <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000b7c: 687b ldr r3, [r7, #4]
8000b7e: 689b ldr r3, [r3, #8]
8000b80: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8000b82: 697b ldr r3, [r7, #20]
8000b84: 005b lsls r3, r3, #1
8000b86: 2203 movs r2, #3
8000b88: fa02 f303 lsl.w r3, r2, r3
8000b8c: 43db mvns r3, r3
8000b8e: 693a ldr r2, [r7, #16]
8000b90: 4013 ands r3, r2
8000b92: 613b str r3, [r7, #16]
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
8000b94: 683b ldr r3, [r7, #0]
8000b96: 68da ldr r2, [r3, #12]
8000b98: 697b ldr r3, [r7, #20]
8000b9a: 005b lsls r3, r3, #1
8000b9c: fa02 f303 lsl.w r3, r2, r3
8000ba0: 693a ldr r2, [r7, #16]
8000ba2: 4313 orrs r3, r2
8000ba4: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8000ba6: 687b ldr r3, [r7, #4]
8000ba8: 693a ldr r2, [r7, #16]
8000baa: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000bac: 687b ldr r3, [r7, #4]
8000bae: 685b ldr r3, [r3, #4]
8000bb0: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
8000bb2: 2201 movs r2, #1
8000bb4: 697b ldr r3, [r7, #20]
8000bb6: fa02 f303 lsl.w r3, r2, r3
8000bba: 43db mvns r3, r3
8000bbc: 693a ldr r2, [r7, #16]
8000bbe: 4013 ands r3, r2
8000bc0: 613b str r3, [r7, #16]
SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000bc2: 683b ldr r3, [r7, #0]
8000bc4: 685b ldr r3, [r3, #4]
8000bc6: 091b lsrs r3, r3, #4
8000bc8: f003 0201 and.w r2, r3, #1
8000bcc: 697b ldr r3, [r7, #20]
8000bce: fa02 f303 lsl.w r3, r2, r3
8000bd2: 693a ldr r2, [r7, #16]
8000bd4: 4313 orrs r3, r2
8000bd6: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8000bd8: 687b ldr r3, [r7, #4]
8000bda: 693a ldr r2, [r7, #16]
8000bdc: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000bde: 683b ldr r3, [r7, #0]
8000be0: 685b ldr r3, [r3, #4]
8000be2: f003 0303 and.w r3, r3, #3
8000be6: 2b03 cmp r3, #3
8000be8: d017 beq.n 8000c1a <HAL_GPIO_Init+0xe6>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000bea: 687b ldr r3, [r7, #4]
8000bec: 68db ldr r3, [r3, #12]
8000bee: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
8000bf0: 697b ldr r3, [r7, #20]
8000bf2: 005b lsls r3, r3, #1
8000bf4: 2203 movs r2, #3
8000bf6: fa02 f303 lsl.w r3, r2, r3
8000bfa: 43db mvns r3, r3
8000bfc: 693a ldr r2, [r7, #16]
8000bfe: 4013 ands r3, r2
8000c00: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
8000c02: 683b ldr r3, [r7, #0]
8000c04: 689a ldr r2, [r3, #8]
8000c06: 697b ldr r3, [r7, #20]
8000c08: 005b lsls r3, r3, #1
8000c0a: fa02 f303 lsl.w r3, r2, r3
8000c0e: 693a ldr r2, [r7, #16]
8000c10: 4313 orrs r3, r2
8000c12: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8000c14: 687b ldr r3, [r7, #4]
8000c16: 693a ldr r2, [r7, #16]
8000c18: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000c1a: 683b ldr r3, [r7, #0]
8000c1c: 685b ldr r3, [r3, #4]
8000c1e: f003 0303 and.w r3, r3, #3
8000c22: 2b02 cmp r3, #2
8000c24: d123 bne.n 8000c6e <HAL_GPIO_Init+0x13a>
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
/* Identify AFRL or AFRH register based on IO position*/
temp = GPIOx->AFR[position >> 3];
8000c26: 697b ldr r3, [r7, #20]
8000c28: 08da lsrs r2, r3, #3
8000c2a: 687b ldr r3, [r7, #4]
8000c2c: 3208 adds r2, #8
8000c2e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000c32: 613b str r3, [r7, #16]
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
8000c34: 697b ldr r3, [r7, #20]
8000c36: f003 0307 and.w r3, r3, #7
8000c3a: 009b lsls r3, r3, #2
8000c3c: 220f movs r2, #15
8000c3e: fa02 f303 lsl.w r3, r2, r3
8000c42: 43db mvns r3, r3
8000c44: 693a ldr r2, [r7, #16]
8000c46: 4013 ands r3, r2
8000c48: 613b str r3, [r7, #16]
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
8000c4a: 683b ldr r3, [r7, #0]
8000c4c: 691a ldr r2, [r3, #16]
8000c4e: 697b ldr r3, [r7, #20]
8000c50: f003 0307 and.w r3, r3, #7
8000c54: 009b lsls r3, r3, #2
8000c56: fa02 f303 lsl.w r3, r2, r3
8000c5a: 693a ldr r2, [r7, #16]
8000c5c: 4313 orrs r3, r2
8000c5e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3] = temp;
8000c60: 697b ldr r3, [r7, #20]
8000c62: 08da lsrs r2, r3, #3
8000c64: 687b ldr r3, [r7, #4]
8000c66: 3208 adds r2, #8
8000c68: 6939 ldr r1, [r7, #16]
8000c6a: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000c6e: 687b ldr r3, [r7, #4]
8000c70: 681b ldr r3, [r3, #0]
8000c72: 613b str r3, [r7, #16]
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
8000c74: 697b ldr r3, [r7, #20]
8000c76: 005b lsls r3, r3, #1
8000c78: 2203 movs r2, #3
8000c7a: fa02 f303 lsl.w r3, r2, r3
8000c7e: 43db mvns r3, r3
8000c80: 693a ldr r2, [r7, #16]
8000c82: 4013 ands r3, r2
8000c84: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8000c86: 683b ldr r3, [r7, #0]
8000c88: 685b ldr r3, [r3, #4]
8000c8a: f003 0203 and.w r2, r3, #3
8000c8e: 697b ldr r3, [r7, #20]
8000c90: 005b lsls r3, r3, #1
8000c92: fa02 f303 lsl.w r3, r2, r3
8000c96: 693a ldr r2, [r7, #16]
8000c98: 4313 orrs r3, r2
8000c9a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8000c9c: 687b ldr r3, [r7, #4]
8000c9e: 693a ldr r2, [r7, #16]
8000ca0: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8000ca2: 683b ldr r3, [r7, #0]
8000ca4: 685b ldr r3, [r3, #4]
8000ca6: f403 3340 and.w r3, r3, #196608 @ 0x30000
8000caa: 2b00 cmp r3, #0
8000cac: f000 80ac beq.w 8000e08 <HAL_GPIO_Init+0x2d4>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000cb0: 4b5e ldr r3, [pc, #376] @ (8000e2c <HAL_GPIO_Init+0x2f8>)
8000cb2: 6a1b ldr r3, [r3, #32]
8000cb4: 4a5d ldr r2, [pc, #372] @ (8000e2c <HAL_GPIO_Init+0x2f8>)
8000cb6: f043 0301 orr.w r3, r3, #1
8000cba: 6213 str r3, [r2, #32]
8000cbc: 4b5b ldr r3, [pc, #364] @ (8000e2c <HAL_GPIO_Init+0x2f8>)
8000cbe: 6a1b ldr r3, [r3, #32]
8000cc0: f003 0301 and.w r3, r3, #1
8000cc4: 60bb str r3, [r7, #8]
8000cc6: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2];
8000cc8: 4a59 ldr r2, [pc, #356] @ (8000e30 <HAL_GPIO_Init+0x2fc>)
8000cca: 697b ldr r3, [r7, #20]
8000ccc: 089b lsrs r3, r3, #2
8000cce: 3302 adds r3, #2
8000cd0: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000cd4: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
8000cd6: 697b ldr r3, [r7, #20]
8000cd8: f003 0303 and.w r3, r3, #3
8000cdc: 009b lsls r3, r3, #2
8000cde: 220f movs r2, #15
8000ce0: fa02 f303 lsl.w r3, r2, r3
8000ce4: 43db mvns r3, r3
8000ce6: 693a ldr r2, [r7, #16]
8000ce8: 4013 ands r3, r2
8000cea: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8000cec: 687b ldr r3, [r7, #4]
8000cee: 4a51 ldr r2, [pc, #324] @ (8000e34 <HAL_GPIO_Init+0x300>)
8000cf0: 4293 cmp r3, r2
8000cf2: d025 beq.n 8000d40 <HAL_GPIO_Init+0x20c>
8000cf4: 687b ldr r3, [r7, #4]
8000cf6: 4a50 ldr r2, [pc, #320] @ (8000e38 <HAL_GPIO_Init+0x304>)
8000cf8: 4293 cmp r3, r2
8000cfa: d01f beq.n 8000d3c <HAL_GPIO_Init+0x208>
8000cfc: 687b ldr r3, [r7, #4]
8000cfe: 4a4f ldr r2, [pc, #316] @ (8000e3c <HAL_GPIO_Init+0x308>)
8000d00: 4293 cmp r3, r2
8000d02: d019 beq.n 8000d38 <HAL_GPIO_Init+0x204>
8000d04: 687b ldr r3, [r7, #4]
8000d06: 4a4e ldr r2, [pc, #312] @ (8000e40 <HAL_GPIO_Init+0x30c>)
8000d08: 4293 cmp r3, r2
8000d0a: d013 beq.n 8000d34 <HAL_GPIO_Init+0x200>
8000d0c: 687b ldr r3, [r7, #4]
8000d0e: 4a4d ldr r2, [pc, #308] @ (8000e44 <HAL_GPIO_Init+0x310>)
8000d10: 4293 cmp r3, r2
8000d12: d00d beq.n 8000d30 <HAL_GPIO_Init+0x1fc>
8000d14: 687b ldr r3, [r7, #4]
8000d16: 4a4c ldr r2, [pc, #304] @ (8000e48 <HAL_GPIO_Init+0x314>)
8000d18: 4293 cmp r3, r2
8000d1a: d007 beq.n 8000d2c <HAL_GPIO_Init+0x1f8>
8000d1c: 687b ldr r3, [r7, #4]
8000d1e: 4a4b ldr r2, [pc, #300] @ (8000e4c <HAL_GPIO_Init+0x318>)
8000d20: 4293 cmp r3, r2
8000d22: d101 bne.n 8000d28 <HAL_GPIO_Init+0x1f4>
8000d24: 2306 movs r3, #6
8000d26: e00c b.n 8000d42 <HAL_GPIO_Init+0x20e>
8000d28: 2307 movs r3, #7
8000d2a: e00a b.n 8000d42 <HAL_GPIO_Init+0x20e>
8000d2c: 2305 movs r3, #5
8000d2e: e008 b.n 8000d42 <HAL_GPIO_Init+0x20e>
8000d30: 2304 movs r3, #4
8000d32: e006 b.n 8000d42 <HAL_GPIO_Init+0x20e>
8000d34: 2303 movs r3, #3
8000d36: e004 b.n 8000d42 <HAL_GPIO_Init+0x20e>
8000d38: 2302 movs r3, #2
8000d3a: e002 b.n 8000d42 <HAL_GPIO_Init+0x20e>
8000d3c: 2301 movs r3, #1
8000d3e: e000 b.n 8000d42 <HAL_GPIO_Init+0x20e>
8000d40: 2300 movs r3, #0
8000d42: 697a ldr r2, [r7, #20]
8000d44: f002 0203 and.w r2, r2, #3
8000d48: 0092 lsls r2, r2, #2
8000d4a: 4093 lsls r3, r2
8000d4c: 693a ldr r2, [r7, #16]
8000d4e: 4313 orrs r3, r2
8000d50: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2] = temp;
8000d52: 4937 ldr r1, [pc, #220] @ (8000e30 <HAL_GPIO_Init+0x2fc>)
8000d54: 697b ldr r3, [r7, #20]
8000d56: 089b lsrs r3, r3, #2
8000d58: 3302 adds r3, #2
8000d5a: 693a ldr r2, [r7, #16]
8000d5c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8000d60: 4b3b ldr r3, [pc, #236] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000d62: 689b ldr r3, [r3, #8]
8000d64: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000d66: 68fb ldr r3, [r7, #12]
8000d68: 43db mvns r3, r3
8000d6a: 693a ldr r2, [r7, #16]
8000d6c: 4013 ands r3, r2
8000d6e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8000d70: 683b ldr r3, [r7, #0]
8000d72: 685b ldr r3, [r3, #4]
8000d74: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8000d78: 2b00 cmp r3, #0
8000d7a: d003 beq.n 8000d84 <HAL_GPIO_Init+0x250>
{
SET_BIT(temp, iocurrent);
8000d7c: 693a ldr r2, [r7, #16]
8000d7e: 68fb ldr r3, [r7, #12]
8000d80: 4313 orrs r3, r2
8000d82: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8000d84: 4a32 ldr r2, [pc, #200] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000d86: 693b ldr r3, [r7, #16]
8000d88: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8000d8a: 4b31 ldr r3, [pc, #196] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000d8c: 68db ldr r3, [r3, #12]
8000d8e: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000d90: 68fb ldr r3, [r7, #12]
8000d92: 43db mvns r3, r3
8000d94: 693a ldr r2, [r7, #16]
8000d96: 4013 ands r3, r2
8000d98: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8000d9a: 683b ldr r3, [r7, #0]
8000d9c: 685b ldr r3, [r3, #4]
8000d9e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8000da2: 2b00 cmp r3, #0
8000da4: d003 beq.n 8000dae <HAL_GPIO_Init+0x27a>
{
SET_BIT(temp, iocurrent);
8000da6: 693a ldr r2, [r7, #16]
8000da8: 68fb ldr r3, [r7, #12]
8000daa: 4313 orrs r3, r2
8000dac: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8000dae: 4a28 ldr r2, [pc, #160] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000db0: 693b ldr r3, [r7, #16]
8000db2: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8000db4: 4b26 ldr r3, [pc, #152] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000db6: 685b ldr r3, [r3, #4]
8000db8: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000dba: 68fb ldr r3, [r7, #12]
8000dbc: 43db mvns r3, r3
8000dbe: 693a ldr r2, [r7, #16]
8000dc0: 4013 ands r3, r2
8000dc2: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8000dc4: 683b ldr r3, [r7, #0]
8000dc6: 685b ldr r3, [r3, #4]
8000dc8: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000dcc: 2b00 cmp r3, #0
8000dce: d003 beq.n 8000dd8 <HAL_GPIO_Init+0x2a4>
{
SET_BIT(temp, iocurrent);
8000dd0: 693a ldr r2, [r7, #16]
8000dd2: 68fb ldr r3, [r7, #12]
8000dd4: 4313 orrs r3, r2
8000dd6: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8000dd8: 4a1d ldr r2, [pc, #116] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000dda: 693b ldr r3, [r7, #16]
8000ddc: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8000dde: 4b1c ldr r3, [pc, #112] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000de0: 681b ldr r3, [r3, #0]
8000de2: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (uint32_t)iocurrent);
8000de4: 68fb ldr r3, [r7, #12]
8000de6: 43db mvns r3, r3
8000de8: 693a ldr r2, [r7, #16]
8000dea: 4013 ands r3, r2
8000dec: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8000dee: 683b ldr r3, [r7, #0]
8000df0: 685b ldr r3, [r3, #4]
8000df2: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000df6: 2b00 cmp r3, #0
8000df8: d003 beq.n 8000e02 <HAL_GPIO_Init+0x2ce>
{
SET_BIT(temp, iocurrent);
8000dfa: 693a ldr r2, [r7, #16]
8000dfc: 68fb ldr r3, [r7, #12]
8000dfe: 4313 orrs r3, r2
8000e00: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8000e02: 4a13 ldr r2, [pc, #76] @ (8000e50 <HAL_GPIO_Init+0x31c>)
8000e04: 693b ldr r3, [r7, #16]
8000e06: 6013 str r3, [r2, #0]
}
}
position++;
8000e08: 697b ldr r3, [r7, #20]
8000e0a: 3301 adds r3, #1
8000e0c: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0)
8000e0e: 683b ldr r3, [r7, #0]
8000e10: 681a ldr r2, [r3, #0]
8000e12: 697b ldr r3, [r7, #20]
8000e14: fa22 f303 lsr.w r3, r2, r3
8000e18: 2b00 cmp r3, #0
8000e1a: f47f ae97 bne.w 8000b4c <HAL_GPIO_Init+0x18>
}
}
8000e1e: bf00 nop
8000e20: bf00 nop
8000e22: 371c adds r7, #28
8000e24: 46bd mov sp, r7
8000e26: bc80 pop {r7}
8000e28: 4770 bx lr
8000e2a: bf00 nop
8000e2c: 40023800 .word 0x40023800
8000e30: 40010000 .word 0x40010000
8000e34: 40020000 .word 0x40020000
8000e38: 40020400 .word 0x40020400
8000e3c: 40020800 .word 0x40020800
8000e40: 40020c00 .word 0x40020c00
8000e44: 40021000 .word 0x40021000
8000e48: 40021400 .word 0x40021400
8000e4c: 40021800 .word 0x40021800
8000e50: 40010400 .word 0x40010400
08000e54 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000e54: b480 push {r7}
8000e56: b083 sub sp, #12
8000e58: af00 add r7, sp, #0
8000e5a: 6078 str r0, [r7, #4]
8000e5c: 460b mov r3, r1
8000e5e: 807b strh r3, [r7, #2]
8000e60: 4613 mov r3, r2
8000e62: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8000e64: 787b ldrb r3, [r7, #1]
8000e66: 2b00 cmp r3, #0
8000e68: d003 beq.n 8000e72 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8000e6a: 887a ldrh r2, [r7, #2]
8000e6c: 687b ldr r3, [r7, #4]
8000e6e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
}
}
8000e70: e003 b.n 8000e7a <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
8000e72: 887b ldrh r3, [r7, #2]
8000e74: 041a lsls r2, r3, #16
8000e76: 687b ldr r3, [r7, #4]
8000e78: 619a str r2, [r3, #24]
}
8000e7a: bf00 nop
8000e7c: 370c adds r7, #12
8000e7e: 46bd mov sp, r7
8000e80: bc80 pop {r7}
8000e82: 4770 bx lr
08000e84 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000e84: b580 push {r7, lr}
8000e86: b088 sub sp, #32
8000e88: af00 add r7, sp, #0
8000e8a: 6078 str r0, [r7, #4]
uint32_t tickstart;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check the parameters */
if(RCC_OscInitStruct == NULL)
8000e8c: 687b ldr r3, [r7, #4]
8000e8e: 2b00 cmp r3, #0
8000e90: d101 bne.n 8000e96 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000e92: 2301 movs r3, #1
8000e94: e31d b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
}
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
8000e96: 4b94 ldr r3, [pc, #592] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000e98: 689b ldr r3, [r3, #8]
8000e9a: f003 030c and.w r3, r3, #12
8000e9e: 61bb str r3, [r7, #24]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
8000ea0: 4b91 ldr r3, [pc, #580] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000ea2: 689b ldr r3, [r3, #8]
8000ea4: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000ea8: 617b str r3, [r7, #20]
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000eaa: 687b ldr r3, [r7, #4]
8000eac: 681b ldr r3, [r3, #0]
8000eae: f003 0301 and.w r3, r3, #1
8000eb2: 2b00 cmp r3, #0
8000eb4: d07b beq.n 8000fae <HAL_RCC_OscConfig+0x12a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
8000eb6: 69bb ldr r3, [r7, #24]
8000eb8: 2b08 cmp r3, #8
8000eba: d006 beq.n 8000eca <HAL_RCC_OscConfig+0x46>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
8000ebc: 69bb ldr r3, [r7, #24]
8000ebe: 2b0c cmp r3, #12
8000ec0: d10f bne.n 8000ee2 <HAL_RCC_OscConfig+0x5e>
8000ec2: 697b ldr r3, [r7, #20]
8000ec4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000ec8: d10b bne.n 8000ee2 <HAL_RCC_OscConfig+0x5e>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000eca: 4b87 ldr r3, [pc, #540] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000ecc: 681b ldr r3, [r3, #0]
8000ece: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000ed2: 2b00 cmp r3, #0
8000ed4: d06a beq.n 8000fac <HAL_RCC_OscConfig+0x128>
8000ed6: 687b ldr r3, [r7, #4]
8000ed8: 685b ldr r3, [r3, #4]
8000eda: 2b00 cmp r3, #0
8000edc: d166 bne.n 8000fac <HAL_RCC_OscConfig+0x128>
{
return HAL_ERROR;
8000ede: 2301 movs r3, #1
8000ee0: e2f7 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000ee2: 687b ldr r3, [r7, #4]
8000ee4: 685b ldr r3, [r3, #4]
8000ee6: 2b01 cmp r3, #1
8000ee8: d106 bne.n 8000ef8 <HAL_RCC_OscConfig+0x74>
8000eea: 4b7f ldr r3, [pc, #508] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000eec: 681b ldr r3, [r3, #0]
8000eee: 4a7e ldr r2, [pc, #504] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000ef0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000ef4: 6013 str r3, [r2, #0]
8000ef6: e02d b.n 8000f54 <HAL_RCC_OscConfig+0xd0>
8000ef8: 687b ldr r3, [r7, #4]
8000efa: 685b ldr r3, [r3, #4]
8000efc: 2b00 cmp r3, #0
8000efe: d10c bne.n 8000f1a <HAL_RCC_OscConfig+0x96>
8000f00: 4b79 ldr r3, [pc, #484] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f02: 681b ldr r3, [r3, #0]
8000f04: 4a78 ldr r2, [pc, #480] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f06: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000f0a: 6013 str r3, [r2, #0]
8000f0c: 4b76 ldr r3, [pc, #472] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f0e: 681b ldr r3, [r3, #0]
8000f10: 4a75 ldr r2, [pc, #468] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f12: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000f16: 6013 str r3, [r2, #0]
8000f18: e01c b.n 8000f54 <HAL_RCC_OscConfig+0xd0>
8000f1a: 687b ldr r3, [r7, #4]
8000f1c: 685b ldr r3, [r3, #4]
8000f1e: 2b05 cmp r3, #5
8000f20: d10c bne.n 8000f3c <HAL_RCC_OscConfig+0xb8>
8000f22: 4b71 ldr r3, [pc, #452] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f24: 681b ldr r3, [r3, #0]
8000f26: 4a70 ldr r2, [pc, #448] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f28: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8000f2c: 6013 str r3, [r2, #0]
8000f2e: 4b6e ldr r3, [pc, #440] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f30: 681b ldr r3, [r3, #0]
8000f32: 4a6d ldr r2, [pc, #436] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f34: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000f38: 6013 str r3, [r2, #0]
8000f3a: e00b b.n 8000f54 <HAL_RCC_OscConfig+0xd0>
8000f3c: 4b6a ldr r3, [pc, #424] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f3e: 681b ldr r3, [r3, #0]
8000f40: 4a69 ldr r2, [pc, #420] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f42: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8000f46: 6013 str r3, [r2, #0]
8000f48: 4b67 ldr r3, [pc, #412] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f4a: 681b ldr r3, [r3, #0]
8000f4c: 4a66 ldr r2, [pc, #408] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f4e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8000f52: 6013 str r3, [r2, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8000f54: 687b ldr r3, [r7, #4]
8000f56: 685b ldr r3, [r3, #4]
8000f58: 2b00 cmp r3, #0
8000f5a: d013 beq.n 8000f84 <HAL_RCC_OscConfig+0x100>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f5c: f7ff fcda bl 8000914 <HAL_GetTick>
8000f60: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8000f62: e008 b.n 8000f76 <HAL_RCC_OscConfig+0xf2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000f64: f7ff fcd6 bl 8000914 <HAL_GetTick>
8000f68: 4602 mov r2, r0
8000f6a: 693b ldr r3, [r7, #16]
8000f6c: 1ad3 subs r3, r2, r3
8000f6e: 2b64 cmp r3, #100 @ 0x64
8000f70: d901 bls.n 8000f76 <HAL_RCC_OscConfig+0xf2>
{
return HAL_TIMEOUT;
8000f72: 2303 movs r3, #3
8000f74: e2ad b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8000f76: 4b5c ldr r3, [pc, #368] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000f78: 681b ldr r3, [r3, #0]
8000f7a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000f7e: 2b00 cmp r3, #0
8000f80: d0f0 beq.n 8000f64 <HAL_RCC_OscConfig+0xe0>
8000f82: e014 b.n 8000fae <HAL_RCC_OscConfig+0x12a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000f84: f7ff fcc6 bl 8000914 <HAL_GetTick>
8000f88: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8000f8a: e008 b.n 8000f9e <HAL_RCC_OscConfig+0x11a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000f8c: f7ff fcc2 bl 8000914 <HAL_GetTick>
8000f90: 4602 mov r2, r0
8000f92: 693b ldr r3, [r7, #16]
8000f94: 1ad3 subs r3, r2, r3
8000f96: 2b64 cmp r3, #100 @ 0x64
8000f98: d901 bls.n 8000f9e <HAL_RCC_OscConfig+0x11a>
{
return HAL_TIMEOUT;
8000f9a: 2303 movs r3, #3
8000f9c: e299 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8000f9e: 4b52 ldr r3, [pc, #328] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000fa0: 681b ldr r3, [r3, #0]
8000fa2: f403 3300 and.w r3, r3, #131072 @ 0x20000
8000fa6: 2b00 cmp r3, #0
8000fa8: d1f0 bne.n 8000f8c <HAL_RCC_OscConfig+0x108>
8000faa: e000 b.n 8000fae <HAL_RCC_OscConfig+0x12a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000fac: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8000fae: 687b ldr r3, [r7, #4]
8000fb0: 681b ldr r3, [r3, #0]
8000fb2: f003 0302 and.w r3, r3, #2
8000fb6: 2b00 cmp r3, #0
8000fb8: d05a beq.n 8001070 <HAL_RCC_OscConfig+0x1ec>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
8000fba: 69bb ldr r3, [r7, #24]
8000fbc: 2b04 cmp r3, #4
8000fbe: d005 beq.n 8000fcc <HAL_RCC_OscConfig+0x148>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
8000fc0: 69bb ldr r3, [r7, #24]
8000fc2: 2b0c cmp r3, #12
8000fc4: d119 bne.n 8000ffa <HAL_RCC_OscConfig+0x176>
8000fc6: 697b ldr r3, [r7, #20]
8000fc8: 2b00 cmp r3, #0
8000fca: d116 bne.n 8000ffa <HAL_RCC_OscConfig+0x176>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000fcc: 4b46 ldr r3, [pc, #280] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000fce: 681b ldr r3, [r3, #0]
8000fd0: f003 0302 and.w r3, r3, #2
8000fd4: 2b00 cmp r3, #0
8000fd6: d005 beq.n 8000fe4 <HAL_RCC_OscConfig+0x160>
8000fd8: 687b ldr r3, [r7, #4]
8000fda: 68db ldr r3, [r3, #12]
8000fdc: 2b01 cmp r3, #1
8000fde: d001 beq.n 8000fe4 <HAL_RCC_OscConfig+0x160>
{
return HAL_ERROR;
8000fe0: 2301 movs r3, #1
8000fe2: e276 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8000fe4: 4b40 ldr r3, [pc, #256] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000fe6: 685b ldr r3, [r3, #4]
8000fe8: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8000fec: 687b ldr r3, [r7, #4]
8000fee: 691b ldr r3, [r3, #16]
8000ff0: 021b lsls r3, r3, #8
8000ff2: 493d ldr r1, [pc, #244] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8000ff4: 4313 orrs r3, r2
8000ff6: 604b str r3, [r1, #4]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8000ff8: e03a b.n 8001070 <HAL_RCC_OscConfig+0x1ec>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8000ffa: 687b ldr r3, [r7, #4]
8000ffc: 68db ldr r3, [r3, #12]
8000ffe: 2b00 cmp r3, #0
8001000: d020 beq.n 8001044 <HAL_RCC_OscConfig+0x1c0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001002: 4b3a ldr r3, [pc, #232] @ (80010ec <HAL_RCC_OscConfig+0x268>)
8001004: 2201 movs r2, #1
8001006: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001008: f7ff fc84 bl 8000914 <HAL_GetTick>
800100c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
800100e: e008 b.n 8001022 <HAL_RCC_OscConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001010: f7ff fc80 bl 8000914 <HAL_GetTick>
8001014: 4602 mov r2, r0
8001016: 693b ldr r3, [r7, #16]
8001018: 1ad3 subs r3, r2, r3
800101a: 2b02 cmp r3, #2
800101c: d901 bls.n 8001022 <HAL_RCC_OscConfig+0x19e>
{
return HAL_TIMEOUT;
800101e: 2303 movs r3, #3
8001020: e257 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8001022: 4b31 ldr r3, [pc, #196] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8001024: 681b ldr r3, [r3, #0]
8001026: f003 0302 and.w r3, r3, #2
800102a: 2b00 cmp r3, #0
800102c: d0f0 beq.n 8001010 <HAL_RCC_OscConfig+0x18c>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800102e: 4b2e ldr r3, [pc, #184] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8001030: 685b ldr r3, [r3, #4]
8001032: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8001036: 687b ldr r3, [r7, #4]
8001038: 691b ldr r3, [r3, #16]
800103a: 021b lsls r3, r3, #8
800103c: 492a ldr r1, [pc, #168] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
800103e: 4313 orrs r3, r2
8001040: 604b str r3, [r1, #4]
8001042: e015 b.n 8001070 <HAL_RCC_OscConfig+0x1ec>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001044: 4b29 ldr r3, [pc, #164] @ (80010ec <HAL_RCC_OscConfig+0x268>)
8001046: 2200 movs r2, #0
8001048: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800104a: f7ff fc63 bl 8000914 <HAL_GetTick>
800104e: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001050: e008 b.n 8001064 <HAL_RCC_OscConfig+0x1e0>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001052: f7ff fc5f bl 8000914 <HAL_GetTick>
8001056: 4602 mov r2, r0
8001058: 693b ldr r3, [r7, #16]
800105a: 1ad3 subs r3, r2, r3
800105c: 2b02 cmp r3, #2
800105e: d901 bls.n 8001064 <HAL_RCC_OscConfig+0x1e0>
{
return HAL_TIMEOUT;
8001060: 2303 movs r3, #3
8001062: e236 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
8001064: 4b20 ldr r3, [pc, #128] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8001066: 681b ldr r3, [r3, #0]
8001068: f003 0302 and.w r3, r3, #2
800106c: 2b00 cmp r3, #0
800106e: d1f0 bne.n 8001052 <HAL_RCC_OscConfig+0x1ce>
}
}
}
}
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
8001070: 687b ldr r3, [r7, #4]
8001072: 681b ldr r3, [r3, #0]
8001074: f003 0310 and.w r3, r3, #16
8001078: 2b00 cmp r3, #0
800107a: f000 80b8 beq.w 80011ee <HAL_RCC_OscConfig+0x36a>
{
/* When the MSI is used as system clock it will not be disabled */
if(sysclk_source == RCC_CFGR_SWS_MSI)
800107e: 69bb ldr r3, [r7, #24]
8001080: 2b00 cmp r3, #0
8001082: d170 bne.n 8001166 <HAL_RCC_OscConfig+0x2e2>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
8001084: 4b18 ldr r3, [pc, #96] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
8001086: 681b ldr r3, [r3, #0]
8001088: f403 7300 and.w r3, r3, #512 @ 0x200
800108c: 2b00 cmp r3, #0
800108e: d005 beq.n 800109c <HAL_RCC_OscConfig+0x218>
8001090: 687b ldr r3, [r7, #4]
8001092: 699b ldr r3, [r3, #24]
8001094: 2b00 cmp r3, #0
8001096: d101 bne.n 800109c <HAL_RCC_OscConfig+0x218>
{
return HAL_ERROR;
8001098: 2301 movs r3, #1
800109a: e21a b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
800109c: 687b ldr r3, [r7, #4]
800109e: 6a1a ldr r2, [r3, #32]
80010a0: 4b11 ldr r3, [pc, #68] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
80010a2: 685b ldr r3, [r3, #4]
80010a4: f403 4360 and.w r3, r3, #57344 @ 0xe000
80010a8: 429a cmp r2, r3
80010aa: d921 bls.n 80010f0 <HAL_RCC_OscConfig+0x26c>
{
/* First increase number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
80010ac: 687b ldr r3, [r7, #4]
80010ae: 6a1b ldr r3, [r3, #32]
80010b0: 4618 mov r0, r3
80010b2: f000 fc7d bl 80019b0 <RCC_SetFlashLatencyFromMSIRange>
80010b6: 4603 mov r3, r0
80010b8: 2b00 cmp r3, #0
80010ba: d001 beq.n 80010c0 <HAL_RCC_OscConfig+0x23c>
{
return HAL_ERROR;
80010bc: 2301 movs r3, #1
80010be: e208 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
}
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80010c0: 4b09 ldr r3, [pc, #36] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
80010c2: 685b ldr r3, [r3, #4]
80010c4: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80010c8: 687b ldr r3, [r7, #4]
80010ca: 6a1b ldr r3, [r3, #32]
80010cc: 4906 ldr r1, [pc, #24] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
80010ce: 4313 orrs r3, r2
80010d0: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80010d2: 4b05 ldr r3, [pc, #20] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
80010d4: 685b ldr r3, [r3, #4]
80010d6: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
80010da: 687b ldr r3, [r7, #4]
80010dc: 69db ldr r3, [r3, #28]
80010de: 061b lsls r3, r3, #24
80010e0: 4901 ldr r1, [pc, #4] @ (80010e8 <HAL_RCC_OscConfig+0x264>)
80010e2: 4313 orrs r3, r2
80010e4: 604b str r3, [r1, #4]
80010e6: e020 b.n 800112a <HAL_RCC_OscConfig+0x2a6>
80010e8: 40023800 .word 0x40023800
80010ec: 42470000 .word 0x42470000
}
else
{
/* Else, keep current flash latency while decreasing applies */
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
80010f0: 4b99 ldr r3, [pc, #612] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80010f2: 685b ldr r3, [r3, #4]
80010f4: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80010f8: 687b ldr r3, [r7, #4]
80010fa: 6a1b ldr r3, [r3, #32]
80010fc: 4996 ldr r1, [pc, #600] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80010fe: 4313 orrs r3, r2
8001100: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
8001102: 4b95 ldr r3, [pc, #596] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001104: 685b ldr r3, [r3, #4]
8001106: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
800110a: 687b ldr r3, [r7, #4]
800110c: 69db ldr r3, [r3, #28]
800110e: 061b lsls r3, r3, #24
8001110: 4991 ldr r1, [pc, #580] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001112: 4313 orrs r3, r2
8001114: 604b str r3, [r1, #4]
/* Decrease number of wait states update if necessary */
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
8001116: 687b ldr r3, [r7, #4]
8001118: 6a1b ldr r3, [r3, #32]
800111a: 4618 mov r0, r3
800111c: f000 fc48 bl 80019b0 <RCC_SetFlashLatencyFromMSIRange>
8001120: 4603 mov r3, r0
8001122: 2b00 cmp r3, #0
8001124: d001 beq.n 800112a <HAL_RCC_OscConfig+0x2a6>
{
return HAL_ERROR;
8001126: 2301 movs r3, #1
8001128: e1d3 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
}
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
800112a: 687b ldr r3, [r7, #4]
800112c: 6a1b ldr r3, [r3, #32]
800112e: 0b5b lsrs r3, r3, #13
8001130: 3301 adds r3, #1
8001132: f44f 4200 mov.w r2, #32768 @ 0x8000
8001136: fa02 f303 lsl.w r3, r2, r3
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
800113a: 4a87 ldr r2, [pc, #540] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
800113c: 6892 ldr r2, [r2, #8]
800113e: 0912 lsrs r2, r2, #4
8001140: f002 020f and.w r2, r2, #15
8001144: 4985 ldr r1, [pc, #532] @ (800135c <HAL_RCC_OscConfig+0x4d8>)
8001146: 5c8a ldrb r2, [r1, r2]
8001148: 40d3 lsrs r3, r2
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
800114a: 4a85 ldr r2, [pc, #532] @ (8001360 <HAL_RCC_OscConfig+0x4dc>)
800114c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
800114e: 4b85 ldr r3, [pc, #532] @ (8001364 <HAL_RCC_OscConfig+0x4e0>)
8001150: 681b ldr r3, [r3, #0]
8001152: 4618 mov r0, r3
8001154: f7ff fb92 bl 800087c <HAL_InitTick>
8001158: 4603 mov r3, r0
800115a: 73fb strb r3, [r7, #15]
if(status != HAL_OK)
800115c: 7bfb ldrb r3, [r7, #15]
800115e: 2b00 cmp r3, #0
8001160: d045 beq.n 80011ee <HAL_RCC_OscConfig+0x36a>
{
return status;
8001162: 7bfb ldrb r3, [r7, #15]
8001164: e1b5 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
{
/* Check MSI State */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
8001166: 687b ldr r3, [r7, #4]
8001168: 699b ldr r3, [r3, #24]
800116a: 2b00 cmp r3, #0
800116c: d029 beq.n 80011c2 <HAL_RCC_OscConfig+0x33e>
{
/* Enable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
800116e: 4b7e ldr r3, [pc, #504] @ (8001368 <HAL_RCC_OscConfig+0x4e4>)
8001170: 2201 movs r2, #1
8001172: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001174: f7ff fbce bl 8000914 <HAL_GetTick>
8001178: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800117a: e008 b.n 800118e <HAL_RCC_OscConfig+0x30a>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
800117c: f7ff fbca bl 8000914 <HAL_GetTick>
8001180: 4602 mov r2, r0
8001182: 693b ldr r3, [r7, #16]
8001184: 1ad3 subs r3, r2, r3
8001186: 2b02 cmp r3, #2
8001188: d901 bls.n 800118e <HAL_RCC_OscConfig+0x30a>
{
return HAL_TIMEOUT;
800118a: 2303 movs r3, #3
800118c: e1a1 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
800118e: 4b72 ldr r3, [pc, #456] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001190: 681b ldr r3, [r3, #0]
8001192: f403 7300 and.w r3, r3, #512 @ 0x200
8001196: 2b00 cmp r3, #0
8001198: d0f0 beq.n 800117c <HAL_RCC_OscConfig+0x2f8>
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
800119a: 4b6f ldr r3, [pc, #444] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
800119c: 685b ldr r3, [r3, #4]
800119e: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80011a2: 687b ldr r3, [r7, #4]
80011a4: 6a1b ldr r3, [r3, #32]
80011a6: 496c ldr r1, [pc, #432] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80011a8: 4313 orrs r3, r2
80011aa: 604b str r3, [r1, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
80011ac: 4b6a ldr r3, [pc, #424] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80011ae: 685b ldr r3, [r3, #4]
80011b0: f023 427f bic.w r2, r3, #4278190080 @ 0xff000000
80011b4: 687b ldr r3, [r7, #4]
80011b6: 69db ldr r3, [r3, #28]
80011b8: 061b lsls r3, r3, #24
80011ba: 4967 ldr r1, [pc, #412] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80011bc: 4313 orrs r3, r2
80011be: 604b str r3, [r1, #4]
80011c0: e015 b.n 80011ee <HAL_RCC_OscConfig+0x36a>
}
else
{
/* Disable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
80011c2: 4b69 ldr r3, [pc, #420] @ (8001368 <HAL_RCC_OscConfig+0x4e4>)
80011c4: 2200 movs r2, #0
80011c6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011c8: f7ff fba4 bl 8000914 <HAL_GetTick>
80011cc: 6138 str r0, [r7, #16]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
80011ce: e008 b.n 80011e2 <HAL_RCC_OscConfig+0x35e>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
80011d0: f7ff fba0 bl 8000914 <HAL_GetTick>
80011d4: 4602 mov r2, r0
80011d6: 693b ldr r3, [r7, #16]
80011d8: 1ad3 subs r3, r2, r3
80011da: 2b02 cmp r3, #2
80011dc: d901 bls.n 80011e2 <HAL_RCC_OscConfig+0x35e>
{
return HAL_TIMEOUT;
80011de: 2303 movs r3, #3
80011e0: e177 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
80011e2: 4b5d ldr r3, [pc, #372] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80011e4: 681b ldr r3, [r3, #0]
80011e6: f403 7300 and.w r3, r3, #512 @ 0x200
80011ea: 2b00 cmp r3, #0
80011ec: d1f0 bne.n 80011d0 <HAL_RCC_OscConfig+0x34c>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80011ee: 687b ldr r3, [r7, #4]
80011f0: 681b ldr r3, [r3, #0]
80011f2: f003 0308 and.w r3, r3, #8
80011f6: 2b00 cmp r3, #0
80011f8: d030 beq.n 800125c <HAL_RCC_OscConfig+0x3d8>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80011fa: 687b ldr r3, [r7, #4]
80011fc: 695b ldr r3, [r3, #20]
80011fe: 2b00 cmp r3, #0
8001200: d016 beq.n 8001230 <HAL_RCC_OscConfig+0x3ac>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001202: 4b5a ldr r3, [pc, #360] @ (800136c <HAL_RCC_OscConfig+0x4e8>)
8001204: 2201 movs r2, #1
8001206: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001208: f7ff fb84 bl 8000914 <HAL_GetTick>
800120c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
800120e: e008 b.n 8001222 <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001210: f7ff fb80 bl 8000914 <HAL_GetTick>
8001214: 4602 mov r2, r0
8001216: 693b ldr r3, [r7, #16]
8001218: 1ad3 subs r3, r2, r3
800121a: 2b02 cmp r3, #2
800121c: d901 bls.n 8001222 <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
800121e: 2303 movs r3, #3
8001220: e157 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
8001222: 4b4d ldr r3, [pc, #308] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001224: 6b5b ldr r3, [r3, #52] @ 0x34
8001226: f003 0302 and.w r3, r3, #2
800122a: 2b00 cmp r3, #0
800122c: d0f0 beq.n 8001210 <HAL_RCC_OscConfig+0x38c>
800122e: e015 b.n 800125c <HAL_RCC_OscConfig+0x3d8>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001230: 4b4e ldr r3, [pc, #312] @ (800136c <HAL_RCC_OscConfig+0x4e8>)
8001232: 2200 movs r2, #0
8001234: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001236: f7ff fb6d bl 8000914 <HAL_GetTick>
800123a: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
800123c: e008 b.n 8001250 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800123e: f7ff fb69 bl 8000914 <HAL_GetTick>
8001242: 4602 mov r2, r0
8001244: 693b ldr r3, [r7, #16]
8001246: 1ad3 subs r3, r2, r3
8001248: 2b02 cmp r3, #2
800124a: d901 bls.n 8001250 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
800124c: 2303 movs r3, #3
800124e: e140 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8001250: 4b41 ldr r3, [pc, #260] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001252: 6b5b ldr r3, [r3, #52] @ 0x34
8001254: f003 0302 and.w r3, r3, #2
8001258: 2b00 cmp r3, #0
800125a: d1f0 bne.n 800123e <HAL_RCC_OscConfig+0x3ba>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800125c: 687b ldr r3, [r7, #4]
800125e: 681b ldr r3, [r3, #0]
8001260: f003 0304 and.w r3, r3, #4
8001264: 2b00 cmp r3, #0
8001266: f000 80b5 beq.w 80013d4 <HAL_RCC_OscConfig+0x550>
{
FlagStatus pwrclkchanged = RESET;
800126a: 2300 movs r3, #0
800126c: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800126e: 4b3a ldr r3, [pc, #232] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001270: 6a5b ldr r3, [r3, #36] @ 0x24
8001272: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001276: 2b00 cmp r3, #0
8001278: d10d bne.n 8001296 <HAL_RCC_OscConfig+0x412>
{
__HAL_RCC_PWR_CLK_ENABLE();
800127a: 4b37 ldr r3, [pc, #220] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
800127c: 6a5b ldr r3, [r3, #36] @ 0x24
800127e: 4a36 ldr r2, [pc, #216] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001280: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001284: 6253 str r3, [r2, #36] @ 0x24
8001286: 4b34 ldr r3, [pc, #208] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001288: 6a5b ldr r3, [r3, #36] @ 0x24
800128a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800128e: 60bb str r3, [r7, #8]
8001290: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001292: 2301 movs r3, #1
8001294: 77fb strb r3, [r7, #31]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001296: 4b36 ldr r3, [pc, #216] @ (8001370 <HAL_RCC_OscConfig+0x4ec>)
8001298: 681b ldr r3, [r3, #0]
800129a: f403 7380 and.w r3, r3, #256 @ 0x100
800129e: 2b00 cmp r3, #0
80012a0: d118 bne.n 80012d4 <HAL_RCC_OscConfig+0x450>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80012a2: 4b33 ldr r3, [pc, #204] @ (8001370 <HAL_RCC_OscConfig+0x4ec>)
80012a4: 681b ldr r3, [r3, #0]
80012a6: 4a32 ldr r2, [pc, #200] @ (8001370 <HAL_RCC_OscConfig+0x4ec>)
80012a8: f443 7380 orr.w r3, r3, #256 @ 0x100
80012ac: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80012ae: f7ff fb31 bl 8000914 <HAL_GetTick>
80012b2: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80012b4: e008 b.n 80012c8 <HAL_RCC_OscConfig+0x444>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80012b6: f7ff fb2d bl 8000914 <HAL_GetTick>
80012ba: 4602 mov r2, r0
80012bc: 693b ldr r3, [r7, #16]
80012be: 1ad3 subs r3, r2, r3
80012c0: 2b64 cmp r3, #100 @ 0x64
80012c2: d901 bls.n 80012c8 <HAL_RCC_OscConfig+0x444>
{
return HAL_TIMEOUT;
80012c4: 2303 movs r3, #3
80012c6: e104 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80012c8: 4b29 ldr r3, [pc, #164] @ (8001370 <HAL_RCC_OscConfig+0x4ec>)
80012ca: 681b ldr r3, [r3, #0]
80012cc: f403 7380 and.w r3, r3, #256 @ 0x100
80012d0: 2b00 cmp r3, #0
80012d2: d0f0 beq.n 80012b6 <HAL_RCC_OscConfig+0x432>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80012d4: 687b ldr r3, [r7, #4]
80012d6: 689b ldr r3, [r3, #8]
80012d8: 2b01 cmp r3, #1
80012da: d106 bne.n 80012ea <HAL_RCC_OscConfig+0x466>
80012dc: 4b1e ldr r3, [pc, #120] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80012de: 6b5b ldr r3, [r3, #52] @ 0x34
80012e0: 4a1d ldr r2, [pc, #116] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80012e2: f443 7380 orr.w r3, r3, #256 @ 0x100
80012e6: 6353 str r3, [r2, #52] @ 0x34
80012e8: e02d b.n 8001346 <HAL_RCC_OscConfig+0x4c2>
80012ea: 687b ldr r3, [r7, #4]
80012ec: 689b ldr r3, [r3, #8]
80012ee: 2b00 cmp r3, #0
80012f0: d10c bne.n 800130c <HAL_RCC_OscConfig+0x488>
80012f2: 4b19 ldr r3, [pc, #100] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80012f4: 6b5b ldr r3, [r3, #52] @ 0x34
80012f6: 4a18 ldr r2, [pc, #96] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
80012f8: f423 7380 bic.w r3, r3, #256 @ 0x100
80012fc: 6353 str r3, [r2, #52] @ 0x34
80012fe: 4b16 ldr r3, [pc, #88] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001300: 6b5b ldr r3, [r3, #52] @ 0x34
8001302: 4a15 ldr r2, [pc, #84] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001304: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001308: 6353 str r3, [r2, #52] @ 0x34
800130a: e01c b.n 8001346 <HAL_RCC_OscConfig+0x4c2>
800130c: 687b ldr r3, [r7, #4]
800130e: 689b ldr r3, [r3, #8]
8001310: 2b05 cmp r3, #5
8001312: d10c bne.n 800132e <HAL_RCC_OscConfig+0x4aa>
8001314: 4b10 ldr r3, [pc, #64] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001316: 6b5b ldr r3, [r3, #52] @ 0x34
8001318: 4a0f ldr r2, [pc, #60] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
800131a: f443 6380 orr.w r3, r3, #1024 @ 0x400
800131e: 6353 str r3, [r2, #52] @ 0x34
8001320: 4b0d ldr r3, [pc, #52] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001322: 6b5b ldr r3, [r3, #52] @ 0x34
8001324: 4a0c ldr r2, [pc, #48] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001326: f443 7380 orr.w r3, r3, #256 @ 0x100
800132a: 6353 str r3, [r2, #52] @ 0x34
800132c: e00b b.n 8001346 <HAL_RCC_OscConfig+0x4c2>
800132e: 4b0a ldr r3, [pc, #40] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001330: 6b5b ldr r3, [r3, #52] @ 0x34
8001332: 4a09 ldr r2, [pc, #36] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001334: f423 7380 bic.w r3, r3, #256 @ 0x100
8001338: 6353 str r3, [r2, #52] @ 0x34
800133a: 4b07 ldr r3, [pc, #28] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
800133c: 6b5b ldr r3, [r3, #52] @ 0x34
800133e: 4a06 ldr r2, [pc, #24] @ (8001358 <HAL_RCC_OscConfig+0x4d4>)
8001340: f423 6380 bic.w r3, r3, #1024 @ 0x400
8001344: 6353 str r3, [r2, #52] @ 0x34
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8001346: 687b ldr r3, [r7, #4]
8001348: 689b ldr r3, [r3, #8]
800134a: 2b00 cmp r3, #0
800134c: d024 beq.n 8001398 <HAL_RCC_OscConfig+0x514>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800134e: f7ff fae1 bl 8000914 <HAL_GetTick>
8001352: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8001354: e019 b.n 800138a <HAL_RCC_OscConfig+0x506>
8001356: bf00 nop
8001358: 40023800 .word 0x40023800
800135c: 08001d54 .word 0x08001d54
8001360: 20000000 .word 0x20000000
8001364: 20000004 .word 0x20000004
8001368: 42470020 .word 0x42470020
800136c: 42470680 .word 0x42470680
8001370: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001374: f7ff face bl 8000914 <HAL_GetTick>
8001378: 4602 mov r2, r0
800137a: 693b ldr r3, [r7, #16]
800137c: 1ad3 subs r3, r2, r3
800137e: f241 3288 movw r2, #5000 @ 0x1388
8001382: 4293 cmp r3, r2
8001384: d901 bls.n 800138a <HAL_RCC_OscConfig+0x506>
{
return HAL_TIMEOUT;
8001386: 2303 movs r3, #3
8001388: e0a3 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
800138a: 4b54 ldr r3, [pc, #336] @ (80014dc <HAL_RCC_OscConfig+0x658>)
800138c: 6b5b ldr r3, [r3, #52] @ 0x34
800138e: f403 7300 and.w r3, r3, #512 @ 0x200
8001392: 2b00 cmp r3, #0
8001394: d0ee beq.n 8001374 <HAL_RCC_OscConfig+0x4f0>
8001396: e014 b.n 80013c2 <HAL_RCC_OscConfig+0x53e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001398: f7ff fabc bl 8000914 <HAL_GetTick>
800139c: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
800139e: e00a b.n 80013b6 <HAL_RCC_OscConfig+0x532>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80013a0: f7ff fab8 bl 8000914 <HAL_GetTick>
80013a4: 4602 mov r2, r0
80013a6: 693b ldr r3, [r7, #16]
80013a8: 1ad3 subs r3, r2, r3
80013aa: f241 3288 movw r2, #5000 @ 0x1388
80013ae: 4293 cmp r3, r2
80013b0: d901 bls.n 80013b6 <HAL_RCC_OscConfig+0x532>
{
return HAL_TIMEOUT;
80013b2: 2303 movs r3, #3
80013b4: e08d b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
80013b6: 4b49 ldr r3, [pc, #292] @ (80014dc <HAL_RCC_OscConfig+0x658>)
80013b8: 6b5b ldr r3, [r3, #52] @ 0x34
80013ba: f403 7300 and.w r3, r3, #512 @ 0x200
80013be: 2b00 cmp r3, #0
80013c0: d1ee bne.n 80013a0 <HAL_RCC_OscConfig+0x51c>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
80013c2: 7ffb ldrb r3, [r7, #31]
80013c4: 2b01 cmp r3, #1
80013c6: d105 bne.n 80013d4 <HAL_RCC_OscConfig+0x550>
{
__HAL_RCC_PWR_CLK_DISABLE();
80013c8: 4b44 ldr r3, [pc, #272] @ (80014dc <HAL_RCC_OscConfig+0x658>)
80013ca: 6a5b ldr r3, [r3, #36] @ 0x24
80013cc: 4a43 ldr r2, [pc, #268] @ (80014dc <HAL_RCC_OscConfig+0x658>)
80013ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80013d2: 6253 str r3, [r2, #36] @ 0x24
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80013d4: 687b ldr r3, [r7, #4]
80013d6: 6a5b ldr r3, [r3, #36] @ 0x24
80013d8: 2b00 cmp r3, #0
80013da: d079 beq.n 80014d0 <HAL_RCC_OscConfig+0x64c>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80013dc: 69bb ldr r3, [r7, #24]
80013de: 2b0c cmp r3, #12
80013e0: d056 beq.n 8001490 <HAL_RCC_OscConfig+0x60c>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80013e2: 687b ldr r3, [r7, #4]
80013e4: 6a5b ldr r3, [r3, #36] @ 0x24
80013e6: 2b02 cmp r3, #2
80013e8: d13b bne.n 8001462 <HAL_RCC_OscConfig+0x5de>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80013ea: 4b3d ldr r3, [pc, #244] @ (80014e0 <HAL_RCC_OscConfig+0x65c>)
80013ec: 2200 movs r2, #0
80013ee: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80013f0: f7ff fa90 bl 8000914 <HAL_GetTick>
80013f4: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80013f6: e008 b.n 800140a <HAL_RCC_OscConfig+0x586>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80013f8: f7ff fa8c bl 8000914 <HAL_GetTick>
80013fc: 4602 mov r2, r0
80013fe: 693b ldr r3, [r7, #16]
8001400: 1ad3 subs r3, r2, r3
8001402: 2b02 cmp r3, #2
8001404: d901 bls.n 800140a <HAL_RCC_OscConfig+0x586>
{
return HAL_TIMEOUT;
8001406: 2303 movs r3, #3
8001408: e063 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
800140a: 4b34 ldr r3, [pc, #208] @ (80014dc <HAL_RCC_OscConfig+0x658>)
800140c: 681b ldr r3, [r3, #0]
800140e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8001412: 2b00 cmp r3, #0
8001414: d1f0 bne.n 80013f8 <HAL_RCC_OscConfig+0x574>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8001416: 4b31 ldr r3, [pc, #196] @ (80014dc <HAL_RCC_OscConfig+0x658>)
8001418: 689b ldr r3, [r3, #8]
800141a: f423 027d bic.w r2, r3, #16580608 @ 0xfd0000
800141e: 687b ldr r3, [r7, #4]
8001420: 6a99 ldr r1, [r3, #40] @ 0x28
8001422: 687b ldr r3, [r7, #4]
8001424: 6adb ldr r3, [r3, #44] @ 0x2c
8001426: 4319 orrs r1, r3
8001428: 687b ldr r3, [r7, #4]
800142a: 6b1b ldr r3, [r3, #48] @ 0x30
800142c: 430b orrs r3, r1
800142e: 492b ldr r1, [pc, #172] @ (80014dc <HAL_RCC_OscConfig+0x658>)
8001430: 4313 orrs r3, r2
8001432: 608b str r3, [r1, #8]
RCC_OscInitStruct->PLL.PLLMUL,
RCC_OscInitStruct->PLL.PLLDIV);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001434: 4b2a ldr r3, [pc, #168] @ (80014e0 <HAL_RCC_OscConfig+0x65c>)
8001436: 2201 movs r2, #1
8001438: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800143a: f7ff fa6b bl 8000914 <HAL_GetTick>
800143e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001440: e008 b.n 8001454 <HAL_RCC_OscConfig+0x5d0>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001442: f7ff fa67 bl 8000914 <HAL_GetTick>
8001446: 4602 mov r2, r0
8001448: 693b ldr r3, [r7, #16]
800144a: 1ad3 subs r3, r2, r3
800144c: 2b02 cmp r3, #2
800144e: d901 bls.n 8001454 <HAL_RCC_OscConfig+0x5d0>
{
return HAL_TIMEOUT;
8001450: 2303 movs r3, #3
8001452: e03e b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001454: 4b21 ldr r3, [pc, #132] @ (80014dc <HAL_RCC_OscConfig+0x658>)
8001456: 681b ldr r3, [r3, #0]
8001458: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800145c: 2b00 cmp r3, #0
800145e: d0f0 beq.n 8001442 <HAL_RCC_OscConfig+0x5be>
8001460: e036 b.n 80014d0 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001462: 4b1f ldr r3, [pc, #124] @ (80014e0 <HAL_RCC_OscConfig+0x65c>)
8001464: 2200 movs r2, #0
8001466: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001468: f7ff fa54 bl 8000914 <HAL_GetTick>
800146c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
800146e: e008 b.n 8001482 <HAL_RCC_OscConfig+0x5fe>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001470: f7ff fa50 bl 8000914 <HAL_GetTick>
8001474: 4602 mov r2, r0
8001476: 693b ldr r3, [r7, #16]
8001478: 1ad3 subs r3, r2, r3
800147a: 2b02 cmp r3, #2
800147c: d901 bls.n 8001482 <HAL_RCC_OscConfig+0x5fe>
{
return HAL_TIMEOUT;
800147e: 2303 movs r3, #3
8001480: e027 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
8001482: 4b16 ldr r3, [pc, #88] @ (80014dc <HAL_RCC_OscConfig+0x658>)
8001484: 681b ldr r3, [r3, #0]
8001486: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800148a: 2b00 cmp r3, #0
800148c: d1f0 bne.n 8001470 <HAL_RCC_OscConfig+0x5ec>
800148e: e01f b.n 80014d0 <HAL_RCC_OscConfig+0x64c>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001490: 687b ldr r3, [r7, #4]
8001492: 6a5b ldr r3, [r3, #36] @ 0x24
8001494: 2b01 cmp r3, #1
8001496: d101 bne.n 800149c <HAL_RCC_OscConfig+0x618>
{
return HAL_ERROR;
8001498: 2301 movs r3, #1
800149a: e01a b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
800149c: 4b0f ldr r3, [pc, #60] @ (80014dc <HAL_RCC_OscConfig+0x658>)
800149e: 689b ldr r3, [r3, #8]
80014a0: 617b str r3, [r7, #20]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80014a2: 697b ldr r3, [r7, #20]
80014a4: f403 3280 and.w r2, r3, #65536 @ 0x10000
80014a8: 687b ldr r3, [r7, #4]
80014aa: 6a9b ldr r3, [r3, #40] @ 0x28
80014ac: 429a cmp r2, r3
80014ae: d10d bne.n 80014cc <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
80014b0: 697b ldr r3, [r7, #20]
80014b2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
80014b6: 687b ldr r3, [r7, #4]
80014b8: 6adb ldr r3, [r3, #44] @ 0x2c
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80014ba: 429a cmp r2, r3
80014bc: d106 bne.n 80014cc <HAL_RCC_OscConfig+0x648>
(READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
80014be: 697b ldr r3, [r7, #20]
80014c0: f403 0240 and.w r2, r3, #12582912 @ 0xc00000
80014c4: 687b ldr r3, [r7, #4]
80014c6: 6b1b ldr r3, [r3, #48] @ 0x30
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
80014c8: 429a cmp r2, r3
80014ca: d001 beq.n 80014d0 <HAL_RCC_OscConfig+0x64c>
{
return HAL_ERROR;
80014cc: 2301 movs r3, #1
80014ce: e000 b.n 80014d2 <HAL_RCC_OscConfig+0x64e>
}
}
}
}
return HAL_OK;
80014d0: 2300 movs r3, #0
}
80014d2: 4618 mov r0, r3
80014d4: 3720 adds r7, #32
80014d6: 46bd mov sp, r7
80014d8: bd80 pop {r7, pc}
80014da: bf00 nop
80014dc: 40023800 .word 0x40023800
80014e0: 42470060 .word 0x42470060
080014e4 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80014e4: b580 push {r7, lr}
80014e6: b084 sub sp, #16
80014e8: af00 add r7, sp, #0
80014ea: 6078 str r0, [r7, #4]
80014ec: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status;
/* Check the parameters */
if(RCC_ClkInitStruct == NULL)
80014ee: 687b ldr r3, [r7, #4]
80014f0: 2b00 cmp r3, #0
80014f2: d101 bne.n 80014f8 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80014f4: 2301 movs r3, #1
80014f6: e11a b.n 800172e <HAL_RCC_ClockConfig+0x24a>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80014f8: 4b8f ldr r3, [pc, #572] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
80014fa: 681b ldr r3, [r3, #0]
80014fc: f003 0301 and.w r3, r3, #1
8001500: 683a ldr r2, [r7, #0]
8001502: 429a cmp r2, r3
8001504: d919 bls.n 800153a <HAL_RCC_ClockConfig+0x56>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001506: 683b ldr r3, [r7, #0]
8001508: 2b01 cmp r3, #1
800150a: d105 bne.n 8001518 <HAL_RCC_ClockConfig+0x34>
800150c: 4b8a ldr r3, [pc, #552] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
800150e: 681b ldr r3, [r3, #0]
8001510: 4a89 ldr r2, [pc, #548] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
8001512: f043 0304 orr.w r3, r3, #4
8001516: 6013 str r3, [r2, #0]
8001518: 4b87 ldr r3, [pc, #540] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
800151a: 681b ldr r3, [r3, #0]
800151c: f023 0201 bic.w r2, r3, #1
8001520: 4985 ldr r1, [pc, #532] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
8001522: 683b ldr r3, [r7, #0]
8001524: 4313 orrs r3, r2
8001526: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001528: 4b83 ldr r3, [pc, #524] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
800152a: 681b ldr r3, [r3, #0]
800152c: f003 0301 and.w r3, r3, #1
8001530: 683a ldr r2, [r7, #0]
8001532: 429a cmp r2, r3
8001534: d001 beq.n 800153a <HAL_RCC_ClockConfig+0x56>
{
return HAL_ERROR;
8001536: 2301 movs r3, #1
8001538: e0f9 b.n 800172e <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800153a: 687b ldr r3, [r7, #4]
800153c: 681b ldr r3, [r3, #0]
800153e: f003 0302 and.w r3, r3, #2
8001542: 2b00 cmp r3, #0
8001544: d008 beq.n 8001558 <HAL_RCC_ClockConfig+0x74>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001546: 4b7d ldr r3, [pc, #500] @ (800173c <HAL_RCC_ClockConfig+0x258>)
8001548: 689b ldr r3, [r3, #8]
800154a: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800154e: 687b ldr r3, [r7, #4]
8001550: 689b ldr r3, [r3, #8]
8001552: 497a ldr r1, [pc, #488] @ (800173c <HAL_RCC_ClockConfig+0x258>)
8001554: 4313 orrs r3, r2
8001556: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001558: 687b ldr r3, [r7, #4]
800155a: 681b ldr r3, [r3, #0]
800155c: f003 0301 and.w r3, r3, #1
8001560: 2b00 cmp r3, #0
8001562: f000 808e beq.w 8001682 <HAL_RCC_ClockConfig+0x19e>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001566: 687b ldr r3, [r7, #4]
8001568: 685b ldr r3, [r3, #4]
800156a: 2b02 cmp r3, #2
800156c: d107 bne.n 800157e <HAL_RCC_ClockConfig+0x9a>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
800156e: 4b73 ldr r3, [pc, #460] @ (800173c <HAL_RCC_ClockConfig+0x258>)
8001570: 681b ldr r3, [r3, #0]
8001572: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001576: 2b00 cmp r3, #0
8001578: d121 bne.n 80015be <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
800157a: 2301 movs r3, #1
800157c: e0d7 b.n 800172e <HAL_RCC_ClockConfig+0x24a>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800157e: 687b ldr r3, [r7, #4]
8001580: 685b ldr r3, [r3, #4]
8001582: 2b03 cmp r3, #3
8001584: d107 bne.n 8001596 <HAL_RCC_ClockConfig+0xb2>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
8001586: 4b6d ldr r3, [pc, #436] @ (800173c <HAL_RCC_ClockConfig+0x258>)
8001588: 681b ldr r3, [r3, #0]
800158a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800158e: 2b00 cmp r3, #0
8001590: d115 bne.n 80015be <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
8001592: 2301 movs r3, #1
8001594: e0cb b.n 800172e <HAL_RCC_ClockConfig+0x24a>
}
}
/* HSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8001596: 687b ldr r3, [r7, #4]
8001598: 685b ldr r3, [r3, #4]
800159a: 2b01 cmp r3, #1
800159c: d107 bne.n 80015ae <HAL_RCC_ClockConfig+0xca>
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
800159e: 4b67 ldr r3, [pc, #412] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80015a0: 681b ldr r3, [r3, #0]
80015a2: f003 0302 and.w r3, r3, #2
80015a6: 2b00 cmp r3, #0
80015a8: d109 bne.n 80015be <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
80015aa: 2301 movs r3, #1
80015ac: e0bf b.n 800172e <HAL_RCC_ClockConfig+0x24a>
}
/* MSI is selected as System Clock Source */
else
{
/* Check the MSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
80015ae: 4b63 ldr r3, [pc, #396] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80015b0: 681b ldr r3, [r3, #0]
80015b2: f403 7300 and.w r3, r3, #512 @ 0x200
80015b6: 2b00 cmp r3, #0
80015b8: d101 bne.n 80015be <HAL_RCC_ClockConfig+0xda>
{
return HAL_ERROR;
80015ba: 2301 movs r3, #1
80015bc: e0b7 b.n 800172e <HAL_RCC_ClockConfig+0x24a>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80015be: 4b5f ldr r3, [pc, #380] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80015c0: 689b ldr r3, [r3, #8]
80015c2: f023 0203 bic.w r2, r3, #3
80015c6: 687b ldr r3, [r7, #4]
80015c8: 685b ldr r3, [r3, #4]
80015ca: 495c ldr r1, [pc, #368] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80015cc: 4313 orrs r3, r2
80015ce: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
80015d0: f7ff f9a0 bl 8000914 <HAL_GetTick>
80015d4: 60f8 str r0, [r7, #12]
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80015d6: 687b ldr r3, [r7, #4]
80015d8: 685b ldr r3, [r3, #4]
80015da: 2b02 cmp r3, #2
80015dc: d112 bne.n 8001604 <HAL_RCC_ClockConfig+0x120>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
80015de: e00a b.n 80015f6 <HAL_RCC_ClockConfig+0x112>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
80015e0: f7ff f998 bl 8000914 <HAL_GetTick>
80015e4: 4602 mov r2, r0
80015e6: 68fb ldr r3, [r7, #12]
80015e8: 1ad3 subs r3, r2, r3
80015ea: f241 3288 movw r2, #5000 @ 0x1388
80015ee: 4293 cmp r3, r2
80015f0: d901 bls.n 80015f6 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
80015f2: 2303 movs r3, #3
80015f4: e09b b.n 800172e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
80015f6: 4b51 ldr r3, [pc, #324] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80015f8: 689b ldr r3, [r3, #8]
80015fa: f003 030c and.w r3, r3, #12
80015fe: 2b08 cmp r3, #8
8001600: d1ee bne.n 80015e0 <HAL_RCC_ClockConfig+0xfc>
8001602: e03e b.n 8001682 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8001604: 687b ldr r3, [r7, #4]
8001606: 685b ldr r3, [r3, #4]
8001608: 2b03 cmp r3, #3
800160a: d112 bne.n 8001632 <HAL_RCC_ClockConfig+0x14e>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800160c: e00a b.n 8001624 <HAL_RCC_ClockConfig+0x140>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
800160e: f7ff f981 bl 8000914 <HAL_GetTick>
8001612: 4602 mov r2, r0
8001614: 68fb ldr r3, [r7, #12]
8001616: 1ad3 subs r3, r2, r3
8001618: f241 3288 movw r2, #5000 @ 0x1388
800161c: 4293 cmp r3, r2
800161e: d901 bls.n 8001624 <HAL_RCC_ClockConfig+0x140>
{
return HAL_TIMEOUT;
8001620: 2303 movs r3, #3
8001622: e084 b.n 800172e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8001624: 4b45 ldr r3, [pc, #276] @ (800173c <HAL_RCC_ClockConfig+0x258>)
8001626: 689b ldr r3, [r3, #8]
8001628: f003 030c and.w r3, r3, #12
800162c: 2b0c cmp r3, #12
800162e: d1ee bne.n 800160e <HAL_RCC_ClockConfig+0x12a>
8001630: e027 b.n 8001682 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8001632: 687b ldr r3, [r7, #4]
8001634: 685b ldr r3, [r3, #4]
8001636: 2b01 cmp r3, #1
8001638: d11d bne.n 8001676 <HAL_RCC_ClockConfig+0x192>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
800163a: e00a b.n 8001652 <HAL_RCC_ClockConfig+0x16e>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
800163c: f7ff f96a bl 8000914 <HAL_GetTick>
8001640: 4602 mov r2, r0
8001642: 68fb ldr r3, [r7, #12]
8001644: 1ad3 subs r3, r2, r3
8001646: f241 3288 movw r2, #5000 @ 0x1388
800164a: 4293 cmp r3, r2
800164c: d901 bls.n 8001652 <HAL_RCC_ClockConfig+0x16e>
{
return HAL_TIMEOUT;
800164e: 2303 movs r3, #3
8001650: e06d b.n 800172e <HAL_RCC_ClockConfig+0x24a>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
8001652: 4b3a ldr r3, [pc, #232] @ (800173c <HAL_RCC_ClockConfig+0x258>)
8001654: 689b ldr r3, [r3, #8]
8001656: f003 030c and.w r3, r3, #12
800165a: 2b04 cmp r3, #4
800165c: d1ee bne.n 800163c <HAL_RCC_ClockConfig+0x158>
800165e: e010 b.n 8001682 <HAL_RCC_ClockConfig+0x19e>
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
8001660: f7ff f958 bl 8000914 <HAL_GetTick>
8001664: 4602 mov r2, r0
8001666: 68fb ldr r3, [r7, #12]
8001668: 1ad3 subs r3, r2, r3
800166a: f241 3288 movw r2, #5000 @ 0x1388
800166e: 4293 cmp r3, r2
8001670: d901 bls.n 8001676 <HAL_RCC_ClockConfig+0x192>
{
return HAL_TIMEOUT;
8001672: 2303 movs r3, #3
8001674: e05b b.n 800172e <HAL_RCC_ClockConfig+0x24a>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
8001676: 4b31 ldr r3, [pc, #196] @ (800173c <HAL_RCC_ClockConfig+0x258>)
8001678: 689b ldr r3, [r3, #8]
800167a: f003 030c and.w r3, r3, #12
800167e: 2b00 cmp r3, #0
8001680: d1ee bne.n 8001660 <HAL_RCC_ClockConfig+0x17c>
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001682: 4b2d ldr r3, [pc, #180] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
8001684: 681b ldr r3, [r3, #0]
8001686: f003 0301 and.w r3, r3, #1
800168a: 683a ldr r2, [r7, #0]
800168c: 429a cmp r2, r3
800168e: d219 bcs.n 80016c4 <HAL_RCC_ClockConfig+0x1e0>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001690: 683b ldr r3, [r7, #0]
8001692: 2b01 cmp r3, #1
8001694: d105 bne.n 80016a2 <HAL_RCC_ClockConfig+0x1be>
8001696: 4b28 ldr r3, [pc, #160] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
8001698: 681b ldr r3, [r3, #0]
800169a: 4a27 ldr r2, [pc, #156] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
800169c: f043 0304 orr.w r3, r3, #4
80016a0: 6013 str r3, [r2, #0]
80016a2: 4b25 ldr r3, [pc, #148] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
80016a4: 681b ldr r3, [r3, #0]
80016a6: f023 0201 bic.w r2, r3, #1
80016aa: 4923 ldr r1, [pc, #140] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
80016ac: 683b ldr r3, [r7, #0]
80016ae: 4313 orrs r3, r2
80016b0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80016b2: 4b21 ldr r3, [pc, #132] @ (8001738 <HAL_RCC_ClockConfig+0x254>)
80016b4: 681b ldr r3, [r3, #0]
80016b6: f003 0301 and.w r3, r3, #1
80016ba: 683a ldr r2, [r7, #0]
80016bc: 429a cmp r2, r3
80016be: d001 beq.n 80016c4 <HAL_RCC_ClockConfig+0x1e0>
{
return HAL_ERROR;
80016c0: 2301 movs r3, #1
80016c2: e034 b.n 800172e <HAL_RCC_ClockConfig+0x24a>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80016c4: 687b ldr r3, [r7, #4]
80016c6: 681b ldr r3, [r3, #0]
80016c8: f003 0304 and.w r3, r3, #4
80016cc: 2b00 cmp r3, #0
80016ce: d008 beq.n 80016e2 <HAL_RCC_ClockConfig+0x1fe>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80016d0: 4b1a ldr r3, [pc, #104] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80016d2: 689b ldr r3, [r3, #8]
80016d4: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80016d8: 687b ldr r3, [r7, #4]
80016da: 68db ldr r3, [r3, #12]
80016dc: 4917 ldr r1, [pc, #92] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80016de: 4313 orrs r3, r2
80016e0: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80016e2: 687b ldr r3, [r7, #4]
80016e4: 681b ldr r3, [r3, #0]
80016e6: f003 0308 and.w r3, r3, #8
80016ea: 2b00 cmp r3, #0
80016ec: d009 beq.n 8001702 <HAL_RCC_ClockConfig+0x21e>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80016ee: 4b13 ldr r3, [pc, #76] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80016f0: 689b ldr r3, [r3, #8]
80016f2: f423 5260 bic.w r2, r3, #14336 @ 0x3800
80016f6: 687b ldr r3, [r7, #4]
80016f8: 691b ldr r3, [r3, #16]
80016fa: 00db lsls r3, r3, #3
80016fc: 490f ldr r1, [pc, #60] @ (800173c <HAL_RCC_ClockConfig+0x258>)
80016fe: 4313 orrs r3, r2
8001700: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001702: f000 f823 bl 800174c <HAL_RCC_GetSysClockFreq>
8001706: 4602 mov r2, r0
8001708: 4b0c ldr r3, [pc, #48] @ (800173c <HAL_RCC_ClockConfig+0x258>)
800170a: 689b ldr r3, [r3, #8]
800170c: 091b lsrs r3, r3, #4
800170e: f003 030f and.w r3, r3, #15
8001712: 490b ldr r1, [pc, #44] @ (8001740 <HAL_RCC_ClockConfig+0x25c>)
8001714: 5ccb ldrb r3, [r1, r3]
8001716: fa22 f303 lsr.w r3, r2, r3
800171a: 4a0a ldr r2, [pc, #40] @ (8001744 <HAL_RCC_ClockConfig+0x260>)
800171c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
800171e: 4b0a ldr r3, [pc, #40] @ (8001748 <HAL_RCC_ClockConfig+0x264>)
8001720: 681b ldr r3, [r3, #0]
8001722: 4618 mov r0, r3
8001724: f7ff f8aa bl 800087c <HAL_InitTick>
8001728: 4603 mov r3, r0
800172a: 72fb strb r3, [r7, #11]
return status;
800172c: 7afb ldrb r3, [r7, #11]
}
800172e: 4618 mov r0, r3
8001730: 3710 adds r7, #16
8001732: 46bd mov sp, r7
8001734: bd80 pop {r7, pc}
8001736: bf00 nop
8001738: 40023c00 .word 0x40023c00
800173c: 40023800 .word 0x40023800
8001740: 08001d54 .word 0x08001d54
8001744: 20000000 .word 0x20000000
8001748: 20000004 .word 0x20000004
0800174c <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800174c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001750: b092 sub sp, #72 @ 0x48
8001752: af00 add r7, sp, #0
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
tmpreg = RCC->CFGR;
8001754: 4b79 ldr r3, [pc, #484] @ (800193c <HAL_RCC_GetSysClockFreq+0x1f0>)
8001756: 689b ldr r3, [r3, #8]
8001758: 63fb str r3, [r7, #60] @ 0x3c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
800175a: 6bfb ldr r3, [r7, #60] @ 0x3c
800175c: f003 030c and.w r3, r3, #12
8001760: 2b0c cmp r3, #12
8001762: d00d beq.n 8001780 <HAL_RCC_GetSysClockFreq+0x34>
8001764: 2b0c cmp r3, #12
8001766: f200 80d5 bhi.w 8001914 <HAL_RCC_GetSysClockFreq+0x1c8>
800176a: 2b04 cmp r3, #4
800176c: d002 beq.n 8001774 <HAL_RCC_GetSysClockFreq+0x28>
800176e: 2b08 cmp r3, #8
8001770: d003 beq.n 800177a <HAL_RCC_GetSysClockFreq+0x2e>
8001772: e0cf b.n 8001914 <HAL_RCC_GetSysClockFreq+0x1c8>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001774: 4b72 ldr r3, [pc, #456] @ (8001940 <HAL_RCC_GetSysClockFreq+0x1f4>)
8001776: 643b str r3, [r7, #64] @ 0x40
break;
8001778: e0da b.n 8001930 <HAL_RCC_GetSysClockFreq+0x1e4>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
800177a: 4b72 ldr r3, [pc, #456] @ (8001944 <HAL_RCC_GetSysClockFreq+0x1f8>)
800177c: 643b str r3, [r7, #64] @ 0x40
break;
800177e: e0d7 b.n 8001930 <HAL_RCC_GetSysClockFreq+0x1e4>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
8001780: 6bfb ldr r3, [r7, #60] @ 0x3c
8001782: 0c9b lsrs r3, r3, #18
8001784: f003 020f and.w r2, r3, #15
8001788: 4b6f ldr r3, [pc, #444] @ (8001948 <HAL_RCC_GetSysClockFreq+0x1fc>)
800178a: 5c9b ldrb r3, [r3, r2]
800178c: 63bb str r3, [r7, #56] @ 0x38
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
800178e: 6bfb ldr r3, [r7, #60] @ 0x3c
8001790: 0d9b lsrs r3, r3, #22
8001792: f003 0303 and.w r3, r3, #3
8001796: 3301 adds r3, #1
8001798: 637b str r3, [r7, #52] @ 0x34
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
800179a: 4b68 ldr r3, [pc, #416] @ (800193c <HAL_RCC_GetSysClockFreq+0x1f0>)
800179c: 689b ldr r3, [r3, #8]
800179e: f403 3380 and.w r3, r3, #65536 @ 0x10000
80017a2: 2b00 cmp r3, #0
80017a4: d05d beq.n 8001862 <HAL_RCC_GetSysClockFreq+0x116>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
80017a6: 6bbb ldr r3, [r7, #56] @ 0x38
80017a8: 2200 movs r2, #0
80017aa: 4618 mov r0, r3
80017ac: 4611 mov r1, r2
80017ae: 4604 mov r4, r0
80017b0: 460d mov r5, r1
80017b2: 4622 mov r2, r4
80017b4: 462b mov r3, r5
80017b6: f04f 0000 mov.w r0, #0
80017ba: f04f 0100 mov.w r1, #0
80017be: 0159 lsls r1, r3, #5
80017c0: ea41 61d2 orr.w r1, r1, r2, lsr #27
80017c4: 0150 lsls r0, r2, #5
80017c6: 4602 mov r2, r0
80017c8: 460b mov r3, r1
80017ca: 4621 mov r1, r4
80017cc: 1a51 subs r1, r2, r1
80017ce: 6139 str r1, [r7, #16]
80017d0: 4629 mov r1, r5
80017d2: eb63 0301 sbc.w r3, r3, r1
80017d6: 617b str r3, [r7, #20]
80017d8: f04f 0200 mov.w r2, #0
80017dc: f04f 0300 mov.w r3, #0
80017e0: e9d7 ab04 ldrd sl, fp, [r7, #16]
80017e4: 4659 mov r1, fp
80017e6: 018b lsls r3, r1, #6
80017e8: 4651 mov r1, sl
80017ea: ea43 6391 orr.w r3, r3, r1, lsr #26
80017ee: 4651 mov r1, sl
80017f0: 018a lsls r2, r1, #6
80017f2: 46d4 mov ip, sl
80017f4: ebb2 080c subs.w r8, r2, ip
80017f8: 4659 mov r1, fp
80017fa: eb63 0901 sbc.w r9, r3, r1
80017fe: f04f 0200 mov.w r2, #0
8001802: f04f 0300 mov.w r3, #0
8001806: ea4f 03c9 mov.w r3, r9, lsl #3
800180a: ea43 7358 orr.w r3, r3, r8, lsr #29
800180e: ea4f 02c8 mov.w r2, r8, lsl #3
8001812: 4690 mov r8, r2
8001814: 4699 mov r9, r3
8001816: 4623 mov r3, r4
8001818: eb18 0303 adds.w r3, r8, r3
800181c: 60bb str r3, [r7, #8]
800181e: 462b mov r3, r5
8001820: eb49 0303 adc.w r3, r9, r3
8001824: 60fb str r3, [r7, #12]
8001826: f04f 0200 mov.w r2, #0
800182a: f04f 0300 mov.w r3, #0
800182e: e9d7 4502 ldrd r4, r5, [r7, #8]
8001832: 4629 mov r1, r5
8001834: 024b lsls r3, r1, #9
8001836: 4620 mov r0, r4
8001838: 4629 mov r1, r5
800183a: 4604 mov r4, r0
800183c: ea43 53d4 orr.w r3, r3, r4, lsr #23
8001840: 4601 mov r1, r0
8001842: 024a lsls r2, r1, #9
8001844: 4610 mov r0, r2
8001846: 4619 mov r1, r3
8001848: 6b7b ldr r3, [r7, #52] @ 0x34
800184a: 2200 movs r2, #0
800184c: 62bb str r3, [r7, #40] @ 0x28
800184e: 62fa str r2, [r7, #44] @ 0x2c
8001850: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
8001854: f7fe fc92 bl 800017c <__aeabi_uldivmod>
8001858: 4602 mov r2, r0
800185a: 460b mov r3, r1
800185c: 4613 mov r3, r2
800185e: 647b str r3, [r7, #68] @ 0x44
8001860: e055 b.n 800190e <HAL_RCC_GetSysClockFreq+0x1c2>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
8001862: 6bbb ldr r3, [r7, #56] @ 0x38
8001864: 2200 movs r2, #0
8001866: 623b str r3, [r7, #32]
8001868: 627a str r2, [r7, #36] @ 0x24
800186a: e9d7 8908 ldrd r8, r9, [r7, #32]
800186e: 4642 mov r2, r8
8001870: 464b mov r3, r9
8001872: f04f 0000 mov.w r0, #0
8001876: f04f 0100 mov.w r1, #0
800187a: 0159 lsls r1, r3, #5
800187c: ea41 61d2 orr.w r1, r1, r2, lsr #27
8001880: 0150 lsls r0, r2, #5
8001882: 4602 mov r2, r0
8001884: 460b mov r3, r1
8001886: 46c4 mov ip, r8
8001888: ebb2 0a0c subs.w sl, r2, ip
800188c: 4640 mov r0, r8
800188e: 4649 mov r1, r9
8001890: 468c mov ip, r1
8001892: eb63 0b0c sbc.w fp, r3, ip
8001896: f04f 0200 mov.w r2, #0
800189a: f04f 0300 mov.w r3, #0
800189e: ea4f 138b mov.w r3, fp, lsl #6
80018a2: ea43 639a orr.w r3, r3, sl, lsr #26
80018a6: ea4f 128a mov.w r2, sl, lsl #6
80018aa: ebb2 040a subs.w r4, r2, sl
80018ae: eb63 050b sbc.w r5, r3, fp
80018b2: f04f 0200 mov.w r2, #0
80018b6: f04f 0300 mov.w r3, #0
80018ba: 00eb lsls r3, r5, #3
80018bc: ea43 7354 orr.w r3, r3, r4, lsr #29
80018c0: 00e2 lsls r2, r4, #3
80018c2: 4614 mov r4, r2
80018c4: 461d mov r5, r3
80018c6: 4603 mov r3, r0
80018c8: 18e3 adds r3, r4, r3
80018ca: 603b str r3, [r7, #0]
80018cc: 460b mov r3, r1
80018ce: eb45 0303 adc.w r3, r5, r3
80018d2: 607b str r3, [r7, #4]
80018d4: f04f 0200 mov.w r2, #0
80018d8: f04f 0300 mov.w r3, #0
80018dc: e9d7 4500 ldrd r4, r5, [r7]
80018e0: 4629 mov r1, r5
80018e2: 028b lsls r3, r1, #10
80018e4: 4620 mov r0, r4
80018e6: 4629 mov r1, r5
80018e8: 4604 mov r4, r0
80018ea: ea43 5394 orr.w r3, r3, r4, lsr #22
80018ee: 4601 mov r1, r0
80018f0: 028a lsls r2, r1, #10
80018f2: 4610 mov r0, r2
80018f4: 4619 mov r1, r3
80018f6: 6b7b ldr r3, [r7, #52] @ 0x34
80018f8: 2200 movs r2, #0
80018fa: 61bb str r3, [r7, #24]
80018fc: 61fa str r2, [r7, #28]
80018fe: e9d7 2306 ldrd r2, r3, [r7, #24]
8001902: f7fe fc3b bl 800017c <__aeabi_uldivmod>
8001906: 4602 mov r2, r0
8001908: 460b mov r3, r1
800190a: 4613 mov r3, r2
800190c: 647b str r3, [r7, #68] @ 0x44
}
sysclockfreq = pllvco;
800190e: 6c7b ldr r3, [r7, #68] @ 0x44
8001910: 643b str r3, [r7, #64] @ 0x40
break;
8001912: e00d b.n 8001930 <HAL_RCC_GetSysClockFreq+0x1e4>
}
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
default: /* MSI used as system clock */
{
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
8001914: 4b09 ldr r3, [pc, #36] @ (800193c <HAL_RCC_GetSysClockFreq+0x1f0>)
8001916: 685b ldr r3, [r3, #4]
8001918: 0b5b lsrs r3, r3, #13
800191a: f003 0307 and.w r3, r3, #7
800191e: 633b str r3, [r7, #48] @ 0x30
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
8001920: 6b3b ldr r3, [r7, #48] @ 0x30
8001922: 3301 adds r3, #1
8001924: f44f 4200 mov.w r2, #32768 @ 0x8000
8001928: fa02 f303 lsl.w r3, r2, r3
800192c: 643b str r3, [r7, #64] @ 0x40
break;
800192e: bf00 nop
}
}
return sysclockfreq;
8001930: 6c3b ldr r3, [r7, #64] @ 0x40
}
8001932: 4618 mov r0, r3
8001934: 3748 adds r7, #72 @ 0x48
8001936: 46bd mov sp, r7
8001938: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
800193c: 40023800 .word 0x40023800
8001940: 00f42400 .word 0x00f42400
8001944: 007a1200 .word 0x007a1200
8001948: 08001d48 .word 0x08001d48
0800194c <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
800194c: b480 push {r7}
800194e: af00 add r7, sp, #0
return SystemCoreClock;
8001950: 4b02 ldr r3, [pc, #8] @ (800195c <HAL_RCC_GetHCLKFreq+0x10>)
8001952: 681b ldr r3, [r3, #0]
}
8001954: 4618 mov r0, r3
8001956: 46bd mov sp, r7
8001958: bc80 pop {r7}
800195a: 4770 bx lr
800195c: 20000000 .word 0x20000000
08001960 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001960: b580 push {r7, lr}
8001962: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8001964: f7ff fff2 bl 800194c <HAL_RCC_GetHCLKFreq>
8001968: 4602 mov r2, r0
800196a: 4b05 ldr r3, [pc, #20] @ (8001980 <HAL_RCC_GetPCLK1Freq+0x20>)
800196c: 689b ldr r3, [r3, #8]
800196e: 0a1b lsrs r3, r3, #8
8001970: f003 0307 and.w r3, r3, #7
8001974: 4903 ldr r1, [pc, #12] @ (8001984 <HAL_RCC_GetPCLK1Freq+0x24>)
8001976: 5ccb ldrb r3, [r1, r3]
8001978: fa22 f303 lsr.w r3, r2, r3
}
800197c: 4618 mov r0, r3
800197e: bd80 pop {r7, pc}
8001980: 40023800 .word 0x40023800
8001984: 08001d64 .word 0x08001d64
08001988 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8001988: b580 push {r7, lr}
800198a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
800198c: f7ff ffde bl 800194c <HAL_RCC_GetHCLKFreq>
8001990: 4602 mov r2, r0
8001992: 4b05 ldr r3, [pc, #20] @ (80019a8 <HAL_RCC_GetPCLK2Freq+0x20>)
8001994: 689b ldr r3, [r3, #8]
8001996: 0adb lsrs r3, r3, #11
8001998: f003 0307 and.w r3, r3, #7
800199c: 4903 ldr r1, [pc, #12] @ (80019ac <HAL_RCC_GetPCLK2Freq+0x24>)
800199e: 5ccb ldrb r3, [r1, r3]
80019a0: fa22 f303 lsr.w r3, r2, r3
}
80019a4: 4618 mov r0, r3
80019a6: bd80 pop {r7, pc}
80019a8: 40023800 .word 0x40023800
80019ac: 08001d64 .word 0x08001d64
080019b0 <RCC_SetFlashLatencyFromMSIRange>:
voltage range
* @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
* @retval HAL status
*/
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
80019b0: b480 push {r7}
80019b2: b087 sub sp, #28
80019b4: af00 add r7, sp, #0
80019b6: 6078 str r0, [r7, #4]
uint32_t vos;
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
80019b8: 2300 movs r3, #0
80019ba: 613b str r3, [r7, #16]
/* HCLK can reach 4 MHz only if AHB prescaler = 1 */
if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
80019bc: 4b29 ldr r3, [pc, #164] @ (8001a64 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80019be: 689b ldr r3, [r3, #8]
80019c0: f003 03f0 and.w r3, r3, #240 @ 0xf0
80019c4: 2b00 cmp r3, #0
80019c6: d12c bne.n 8001a22 <RCC_SetFlashLatencyFromMSIRange+0x72>
{
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
80019c8: 4b26 ldr r3, [pc, #152] @ (8001a64 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80019ca: 6a5b ldr r3, [r3, #36] @ 0x24
80019cc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80019d0: 2b00 cmp r3, #0
80019d2: d005 beq.n 80019e0 <RCC_SetFlashLatencyFromMSIRange+0x30>
{
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
80019d4: 4b24 ldr r3, [pc, #144] @ (8001a68 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80019d6: 681b ldr r3, [r3, #0]
80019d8: f403 53c0 and.w r3, r3, #6144 @ 0x1800
80019dc: 617b str r3, [r7, #20]
80019de: e016 b.n 8001a0e <RCC_SetFlashLatencyFromMSIRange+0x5e>
}
else
{
__HAL_RCC_PWR_CLK_ENABLE();
80019e0: 4b20 ldr r3, [pc, #128] @ (8001a64 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80019e2: 6a5b ldr r3, [r3, #36] @ 0x24
80019e4: 4a1f ldr r2, [pc, #124] @ (8001a64 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80019e6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80019ea: 6253 str r3, [r2, #36] @ 0x24
80019ec: 4b1d ldr r3, [pc, #116] @ (8001a64 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
80019ee: 6a5b ldr r3, [r3, #36] @ 0x24
80019f0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80019f4: 60fb str r3, [r7, #12]
80019f6: 68fb ldr r3, [r7, #12]
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
80019f8: 4b1b ldr r3, [pc, #108] @ (8001a68 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
80019fa: 681b ldr r3, [r3, #0]
80019fc: f403 53c0 and.w r3, r3, #6144 @ 0x1800
8001a00: 617b str r3, [r7, #20]
__HAL_RCC_PWR_CLK_DISABLE();
8001a02: 4b18 ldr r3, [pc, #96] @ (8001a64 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001a04: 6a5b ldr r3, [r3, #36] @ 0x24
8001a06: 4a17 ldr r2, [pc, #92] @ (8001a64 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
8001a08: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8001a0c: 6253 str r3, [r2, #36] @ 0x24
}
/* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
8001a0e: 697b ldr r3, [r7, #20]
8001a10: f5b3 5fc0 cmp.w r3, #6144 @ 0x1800
8001a14: d105 bne.n 8001a22 <RCC_SetFlashLatencyFromMSIRange+0x72>
8001a16: 687b ldr r3, [r7, #4]
8001a18: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8001a1c: d101 bne.n 8001a22 <RCC_SetFlashLatencyFromMSIRange+0x72>
{
latency = FLASH_LATENCY_1; /* 1WS */
8001a1e: 2301 movs r3, #1
8001a20: 613b str r3, [r7, #16]
}
}
__HAL_FLASH_SET_LATENCY(latency);
8001a22: 693b ldr r3, [r7, #16]
8001a24: 2b01 cmp r3, #1
8001a26: d105 bne.n 8001a34 <RCC_SetFlashLatencyFromMSIRange+0x84>
8001a28: 4b10 ldr r3, [pc, #64] @ (8001a6c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001a2a: 681b ldr r3, [r3, #0]
8001a2c: 4a0f ldr r2, [pc, #60] @ (8001a6c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001a2e: f043 0304 orr.w r3, r3, #4
8001a32: 6013 str r3, [r2, #0]
8001a34: 4b0d ldr r3, [pc, #52] @ (8001a6c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001a36: 681b ldr r3, [r3, #0]
8001a38: f023 0201 bic.w r2, r3, #1
8001a3c: 490b ldr r1, [pc, #44] @ (8001a6c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001a3e: 693b ldr r3, [r7, #16]
8001a40: 4313 orrs r3, r2
8001a42: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != latency)
8001a44: 4b09 ldr r3, [pc, #36] @ (8001a6c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
8001a46: 681b ldr r3, [r3, #0]
8001a48: f003 0301 and.w r3, r3, #1
8001a4c: 693a ldr r2, [r7, #16]
8001a4e: 429a cmp r2, r3
8001a50: d001 beq.n 8001a56 <RCC_SetFlashLatencyFromMSIRange+0xa6>
{
return HAL_ERROR;
8001a52: 2301 movs r3, #1
8001a54: e000 b.n 8001a58 <RCC_SetFlashLatencyFromMSIRange+0xa8>
}
return HAL_OK;
8001a56: 2300 movs r3, #0
}
8001a58: 4618 mov r0, r3
8001a5a: 371c adds r7, #28
8001a5c: 46bd mov sp, r7
8001a5e: bc80 pop {r7}
8001a60: 4770 bx lr
8001a62: bf00 nop
8001a64: 40023800 .word 0x40023800
8001a68: 40007000 .word 0x40007000
8001a6c: 40023c00 .word 0x40023c00
08001a70 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8001a70: b580 push {r7, lr}
8001a72: b082 sub sp, #8
8001a74: af00 add r7, sp, #0
8001a76: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8001a78: 687b ldr r3, [r7, #4]
8001a7a: 2b00 cmp r3, #0
8001a7c: d101 bne.n 8001a82 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8001a7e: 2301 movs r3, #1
8001a80: e042 b.n 8001b08 <HAL_UART_Init+0x98>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8001a82: 687b ldr r3, [r7, #4]
8001a84: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8001a88: b2db uxtb r3, r3
8001a8a: 2b00 cmp r3, #0
8001a8c: d106 bne.n 8001a9c <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8001a8e: 687b ldr r3, [r7, #4]
8001a90: 2200 movs r2, #0
8001a92: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8001a96: 6878 ldr r0, [r7, #4]
8001a98: f7fe fe3c bl 8000714 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8001a9c: 687b ldr r3, [r7, #4]
8001a9e: 2224 movs r2, #36 @ 0x24
8001aa0: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8001aa4: 687b ldr r3, [r7, #4]
8001aa6: 681b ldr r3, [r3, #0]
8001aa8: 68da ldr r2, [r3, #12]
8001aaa: 687b ldr r3, [r7, #4]
8001aac: 681b ldr r3, [r3, #0]
8001aae: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8001ab2: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8001ab4: 6878 ldr r0, [r7, #4]
8001ab6: f000 f82b bl 8001b10 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8001aba: 687b ldr r3, [r7, #4]
8001abc: 681b ldr r3, [r3, #0]
8001abe: 691a ldr r2, [r3, #16]
8001ac0: 687b ldr r3, [r7, #4]
8001ac2: 681b ldr r3, [r3, #0]
8001ac4: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8001ac8: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8001aca: 687b ldr r3, [r7, #4]
8001acc: 681b ldr r3, [r3, #0]
8001ace: 695a ldr r2, [r3, #20]
8001ad0: 687b ldr r3, [r7, #4]
8001ad2: 681b ldr r3, [r3, #0]
8001ad4: f022 022a bic.w r2, r2, #42 @ 0x2a
8001ad8: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8001ada: 687b ldr r3, [r7, #4]
8001adc: 681b ldr r3, [r3, #0]
8001ade: 68da ldr r2, [r3, #12]
8001ae0: 687b ldr r3, [r7, #4]
8001ae2: 681b ldr r3, [r3, #0]
8001ae4: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8001ae8: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8001aea: 687b ldr r3, [r7, #4]
8001aec: 2200 movs r2, #0
8001aee: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
8001af0: 687b ldr r3, [r7, #4]
8001af2: 2220 movs r2, #32
8001af4: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8001af8: 687b ldr r3, [r7, #4]
8001afa: 2220 movs r2, #32
8001afc: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
8001b00: 687b ldr r3, [r7, #4]
8001b02: 2200 movs r2, #0
8001b04: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8001b06: 2300 movs r3, #0
}
8001b08: 4618 mov r0, r3
8001b0a: 3708 adds r7, #8
8001b0c: 46bd mov sp, r7
8001b0e: bd80 pop {r7, pc}
08001b10 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8001b10: b580 push {r7, lr}
8001b12: b084 sub sp, #16
8001b14: af00 add r7, sp, #0
8001b16: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8001b18: 687b ldr r3, [r7, #4]
8001b1a: 681b ldr r3, [r3, #0]
8001b1c: 691b ldr r3, [r3, #16]
8001b1e: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8001b22: 687b ldr r3, [r7, #4]
8001b24: 68da ldr r2, [r3, #12]
8001b26: 687b ldr r3, [r7, #4]
8001b28: 681b ldr r3, [r3, #0]
8001b2a: 430a orrs r2, r1
8001b2c: 611a str r2, [r3, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8001b2e: 687b ldr r3, [r7, #4]
8001b30: 689a ldr r2, [r3, #8]
8001b32: 687b ldr r3, [r7, #4]
8001b34: 691b ldr r3, [r3, #16]
8001b36: 431a orrs r2, r3
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 695b ldr r3, [r3, #20]
8001b3c: 431a orrs r2, r3
8001b3e: 687b ldr r3, [r7, #4]
8001b40: 69db ldr r3, [r3, #28]
8001b42: 4313 orrs r3, r2
8001b44: 60bb str r3, [r7, #8]
MODIFY_REG(huart->Instance->CR1,
8001b46: 687b ldr r3, [r7, #4]
8001b48: 681b ldr r3, [r3, #0]
8001b4a: 68db ldr r3, [r3, #12]
8001b4c: f423 4316 bic.w r3, r3, #38400 @ 0x9600
8001b50: f023 030c bic.w r3, r3, #12
8001b54: 687a ldr r2, [r7, #4]
8001b56: 6812 ldr r2, [r2, #0]
8001b58: 68b9 ldr r1, [r7, #8]
8001b5a: 430b orrs r3, r1
8001b5c: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8001b5e: 687b ldr r3, [r7, #4]
8001b60: 681b ldr r3, [r3, #0]
8001b62: 695b ldr r3, [r3, #20]
8001b64: f423 7140 bic.w r1, r3, #768 @ 0x300
8001b68: 687b ldr r3, [r7, #4]
8001b6a: 699a ldr r2, [r3, #24]
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 681b ldr r3, [r3, #0]
8001b70: 430a orrs r2, r1
8001b72: 615a str r2, [r3, #20]
if((huart->Instance == USART1))
8001b74: 687b ldr r3, [r7, #4]
8001b76: 681b ldr r3, [r3, #0]
8001b78: 4a55 ldr r2, [pc, #340] @ (8001cd0 <UART_SetConfig+0x1c0>)
8001b7a: 4293 cmp r3, r2
8001b7c: d103 bne.n 8001b86 <UART_SetConfig+0x76>
{
pclk = HAL_RCC_GetPCLK2Freq();
8001b7e: f7ff ff03 bl 8001988 <HAL_RCC_GetPCLK2Freq>
8001b82: 60f8 str r0, [r7, #12]
8001b84: e002 b.n 8001b8c <UART_SetConfig+0x7c>
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8001b86: f7ff feeb bl 8001960 <HAL_RCC_GetPCLK1Freq>
8001b8a: 60f8 str r0, [r7, #12]
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8001b8c: 687b ldr r3, [r7, #4]
8001b8e: 69db ldr r3, [r3, #28]
8001b90: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8001b94: d14c bne.n 8001c30 <UART_SetConfig+0x120>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8001b96: 68fa ldr r2, [r7, #12]
8001b98: 4613 mov r3, r2
8001b9a: 009b lsls r3, r3, #2
8001b9c: 4413 add r3, r2
8001b9e: 009a lsls r2, r3, #2
8001ba0: 441a add r2, r3
8001ba2: 687b ldr r3, [r7, #4]
8001ba4: 685b ldr r3, [r3, #4]
8001ba6: 005b lsls r3, r3, #1
8001ba8: fbb2 f3f3 udiv r3, r2, r3
8001bac: 4a49 ldr r2, [pc, #292] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001bae: fba2 2303 umull r2, r3, r2, r3
8001bb2: 095b lsrs r3, r3, #5
8001bb4: 0119 lsls r1, r3, #4
8001bb6: 68fa ldr r2, [r7, #12]
8001bb8: 4613 mov r3, r2
8001bba: 009b lsls r3, r3, #2
8001bbc: 4413 add r3, r2
8001bbe: 009a lsls r2, r3, #2
8001bc0: 441a add r2, r3
8001bc2: 687b ldr r3, [r7, #4]
8001bc4: 685b ldr r3, [r3, #4]
8001bc6: 005b lsls r3, r3, #1
8001bc8: fbb2 f2f3 udiv r2, r2, r3
8001bcc: 4b41 ldr r3, [pc, #260] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001bce: fba3 0302 umull r0, r3, r3, r2
8001bd2: 095b lsrs r3, r3, #5
8001bd4: 2064 movs r0, #100 @ 0x64
8001bd6: fb00 f303 mul.w r3, r0, r3
8001bda: 1ad3 subs r3, r2, r3
8001bdc: 00db lsls r3, r3, #3
8001bde: 3332 adds r3, #50 @ 0x32
8001be0: 4a3c ldr r2, [pc, #240] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001be2: fba2 2303 umull r2, r3, r2, r3
8001be6: 095b lsrs r3, r3, #5
8001be8: 005b lsls r3, r3, #1
8001bea: f403 73f8 and.w r3, r3, #496 @ 0x1f0
8001bee: 4419 add r1, r3
8001bf0: 68fa ldr r2, [r7, #12]
8001bf2: 4613 mov r3, r2
8001bf4: 009b lsls r3, r3, #2
8001bf6: 4413 add r3, r2
8001bf8: 009a lsls r2, r3, #2
8001bfa: 441a add r2, r3
8001bfc: 687b ldr r3, [r7, #4]
8001bfe: 685b ldr r3, [r3, #4]
8001c00: 005b lsls r3, r3, #1
8001c02: fbb2 f2f3 udiv r2, r2, r3
8001c06: 4b33 ldr r3, [pc, #204] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001c08: fba3 0302 umull r0, r3, r3, r2
8001c0c: 095b lsrs r3, r3, #5
8001c0e: 2064 movs r0, #100 @ 0x64
8001c10: fb00 f303 mul.w r3, r0, r3
8001c14: 1ad3 subs r3, r2, r3
8001c16: 00db lsls r3, r3, #3
8001c18: 3332 adds r3, #50 @ 0x32
8001c1a: 4a2e ldr r2, [pc, #184] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001c1c: fba2 2303 umull r2, r3, r2, r3
8001c20: 095b lsrs r3, r3, #5
8001c22: f003 0207 and.w r2, r3, #7
8001c26: 687b ldr r3, [r7, #4]
8001c28: 681b ldr r3, [r3, #0]
8001c2a: 440a add r2, r1
8001c2c: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8001c2e: e04a b.n 8001cc6 <UART_SetConfig+0x1b6>
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8001c30: 68fa ldr r2, [r7, #12]
8001c32: 4613 mov r3, r2
8001c34: 009b lsls r3, r3, #2
8001c36: 4413 add r3, r2
8001c38: 009a lsls r2, r3, #2
8001c3a: 441a add r2, r3
8001c3c: 687b ldr r3, [r7, #4]
8001c3e: 685b ldr r3, [r3, #4]
8001c40: 009b lsls r3, r3, #2
8001c42: fbb2 f3f3 udiv r3, r2, r3
8001c46: 4a23 ldr r2, [pc, #140] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001c48: fba2 2303 umull r2, r3, r2, r3
8001c4c: 095b lsrs r3, r3, #5
8001c4e: 0119 lsls r1, r3, #4
8001c50: 68fa ldr r2, [r7, #12]
8001c52: 4613 mov r3, r2
8001c54: 009b lsls r3, r3, #2
8001c56: 4413 add r3, r2
8001c58: 009a lsls r2, r3, #2
8001c5a: 441a add r2, r3
8001c5c: 687b ldr r3, [r7, #4]
8001c5e: 685b ldr r3, [r3, #4]
8001c60: 009b lsls r3, r3, #2
8001c62: fbb2 f2f3 udiv r2, r2, r3
8001c66: 4b1b ldr r3, [pc, #108] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001c68: fba3 0302 umull r0, r3, r3, r2
8001c6c: 095b lsrs r3, r3, #5
8001c6e: 2064 movs r0, #100 @ 0x64
8001c70: fb00 f303 mul.w r3, r0, r3
8001c74: 1ad3 subs r3, r2, r3
8001c76: 011b lsls r3, r3, #4
8001c78: 3332 adds r3, #50 @ 0x32
8001c7a: 4a16 ldr r2, [pc, #88] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001c7c: fba2 2303 umull r2, r3, r2, r3
8001c80: 095b lsrs r3, r3, #5
8001c82: f003 03f0 and.w r3, r3, #240 @ 0xf0
8001c86: 4419 add r1, r3
8001c88: 68fa ldr r2, [r7, #12]
8001c8a: 4613 mov r3, r2
8001c8c: 009b lsls r3, r3, #2
8001c8e: 4413 add r3, r2
8001c90: 009a lsls r2, r3, #2
8001c92: 441a add r2, r3
8001c94: 687b ldr r3, [r7, #4]
8001c96: 685b ldr r3, [r3, #4]
8001c98: 009b lsls r3, r3, #2
8001c9a: fbb2 f2f3 udiv r2, r2, r3
8001c9e: 4b0d ldr r3, [pc, #52] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001ca0: fba3 0302 umull r0, r3, r3, r2
8001ca4: 095b lsrs r3, r3, #5
8001ca6: 2064 movs r0, #100 @ 0x64
8001ca8: fb00 f303 mul.w r3, r0, r3
8001cac: 1ad3 subs r3, r2, r3
8001cae: 011b lsls r3, r3, #4
8001cb0: 3332 adds r3, #50 @ 0x32
8001cb2: 4a08 ldr r2, [pc, #32] @ (8001cd4 <UART_SetConfig+0x1c4>)
8001cb4: fba2 2303 umull r2, r3, r2, r3
8001cb8: 095b lsrs r3, r3, #5
8001cba: f003 020f and.w r2, r3, #15
8001cbe: 687b ldr r3, [r7, #4]
8001cc0: 681b ldr r3, [r3, #0]
8001cc2: 440a add r2, r1
8001cc4: 609a str r2, [r3, #8]
}
8001cc6: bf00 nop
8001cc8: 3710 adds r7, #16
8001cca: 46bd mov sp, r7
8001ccc: bd80 pop {r7, pc}
8001cce: bf00 nop
8001cd0: 40013800 .word 0x40013800
8001cd4: 51eb851f .word 0x51eb851f
08001cd8 <memset>:
8001cd8: 4603 mov r3, r0
8001cda: 4402 add r2, r0
8001cdc: 4293 cmp r3, r2
8001cde: d100 bne.n 8001ce2 <memset+0xa>
8001ce0: 4770 bx lr
8001ce2: f803 1b01 strb.w r1, [r3], #1
8001ce6: e7f9 b.n 8001cdc <memset+0x4>
08001ce8 <__libc_init_array>:
8001ce8: b570 push {r4, r5, r6, lr}
8001cea: 2600 movs r6, #0
8001cec: 4d0c ldr r5, [pc, #48] @ (8001d20 <__libc_init_array+0x38>)
8001cee: 4c0d ldr r4, [pc, #52] @ (8001d24 <__libc_init_array+0x3c>)
8001cf0: 1b64 subs r4, r4, r5
8001cf2: 10a4 asrs r4, r4, #2
8001cf4: 42a6 cmp r6, r4
8001cf6: d109 bne.n 8001d0c <__libc_init_array+0x24>
8001cf8: f000 f81a bl 8001d30 <_init>
8001cfc: 2600 movs r6, #0
8001cfe: 4d0a ldr r5, [pc, #40] @ (8001d28 <__libc_init_array+0x40>)
8001d00: 4c0a ldr r4, [pc, #40] @ (8001d2c <__libc_init_array+0x44>)
8001d02: 1b64 subs r4, r4, r5
8001d04: 10a4 asrs r4, r4, #2
8001d06: 42a6 cmp r6, r4
8001d08: d105 bne.n 8001d16 <__libc_init_array+0x2e>
8001d0a: bd70 pop {r4, r5, r6, pc}
8001d0c: f855 3b04 ldr.w r3, [r5], #4
8001d10: 4798 blx r3
8001d12: 3601 adds r6, #1
8001d14: e7ee b.n 8001cf4 <__libc_init_array+0xc>
8001d16: f855 3b04 ldr.w r3, [r5], #4
8001d1a: 4798 blx r3
8001d1c: 3601 adds r6, #1
8001d1e: e7f2 b.n 8001d06 <__libc_init_array+0x1e>
8001d20: 08001d74 .word 0x08001d74
8001d24: 08001d74 .word 0x08001d74
8001d28: 08001d74 .word 0x08001d74
8001d2c: 08001d78 .word 0x08001d78
08001d30 <_init>:
8001d30: b5f8 push {r3, r4, r5, r6, r7, lr}
8001d32: bf00 nop
8001d34: bcf8 pop {r3, r4, r5, r6, r7}
8001d36: bc08 pop {r3}
8001d38: 469e mov lr, r3
8001d3a: 4770 bx lr
08001d3c <_fini>:
8001d3c: b5f8 push {r3, r4, r5, r6, r7, lr}
8001d3e: bf00 nop
8001d40: bcf8 pop {r3, r4, r5, r6, r7}
8001d42: bc08 pop {r3}
8001d44: 469e mov lr, r3
8001d46: 4770 bx lr
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