From 037c03e85aa64cb41bb9779985f87439df9fd998 Mon Sep 17 00:00:00 2001 From: Romain Goyet Date: Wed, 6 May 2015 21:50:01 +0200 Subject: [PATCH] Clean up --- Makefile | 12 ++- arch/stm32f429/registers.h | 3 - .../stm32f429/boot/flash.ld | 0 .../stm32f429/boot}/isr.c | 0 .../stm32f429/boot}/isr.h | 0 platform/stm32f429/registers.h | 3 + {arch => platform}/stm32f429/registers/gpio.c | 2 +- {arch => platform}/stm32f429/registers/gpio.h | 0 {arch => platform}/stm32f429/registers/rcc.c | 0 {arch => platform}/stm32f429/registers/rcc.h | 0 {arch => platform}/stm32f429/registers/spi.c | 2 +- {arch => platform}/stm32f429/registers/spi.h | 5 ++ platform/stm32f429/spi.c | 5 ++ platform/stm32f429/spi.h | 17 ++++ src/lcd_spi.c | 89 +++++++++++++++++-- 15 files changed, 121 insertions(+), 17 deletions(-) delete mode 100644 arch/stm32f429/registers.h rename boot/stm32f429.ld => platform/stm32f429/boot/flash.ld (100%) rename {arch/stm32f429 => platform/stm32f429/boot}/isr.c (100%) rename {arch/stm32f429 => platform/stm32f429/boot}/isr.h (100%) create mode 100644 platform/stm32f429/registers.h rename {arch => platform}/stm32f429/registers/gpio.c (98%) rename {arch => platform}/stm32f429/registers/gpio.h (100%) rename {arch => platform}/stm32f429/registers/rcc.c (100%) rename {arch => platform}/stm32f429/registers/rcc.h (100%) rename {arch => platform}/stm32f429/registers/spi.c (96%) rename {arch => platform}/stm32f429/registers/spi.h (93%) create mode 100644 platform/stm32f429/spi.c create mode 100644 platform/stm32f429/spi.h diff --git a/Makefile b/Makefile index 7263a774b..d7767e24a 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,8 @@ CC=arm-none-eabi-gcc LD=arm-none-eabi-ld.bfd GDB=arm-none-eabi-gdb OBJCOPY=arm-none-eabi-objcopy -CFLAGS = -Iarch/stm32f429 -Iexternal/freertos/include -Iexternal -Iexternal/freertos/portable/GCC/ARM_CM4F -Iexternal/newlib/libc/include +CFLAGS = -I. -Iinclude -Iexternal/freertos/include -Iexternal -Iexternal/freertos/portable/GCC/ARM_CM4F -Iexternal/newlib/libc/include +#CFLAGS = -I. -Iexternal/freertos/include -Iexternal -Iexternal/freertos/portable/GCC/ARM_CM4F -Iexternal/newlib/libc/include -Iinclude #-I/Users/romain/local/arm-none-eabi/include CFLAGS += -std=c99 -g -Wall #CFLAGS += -march=armv7e-m -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 @@ -13,14 +14,17 @@ CFLAGS += -target thumbv7em-unknown-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -ffre #CFLAGS += -Os -fdata-sections -ffunction-sections #LDFLAGS += --gc-sections -objs := boot/crt0.o arch/stm32f429/isr.o arch/stm32f429/registers/rcc.o arch/stm32f429/registers/gpio.o arch/stm32f429/registers/spi.o external/freertos/tasks.o external/freertos/list.o external/freertos/queue.o external/freertos/portable/GCC/ARM_CM4F/port.o external/freertos/portable/MemMang/heap_1.o external/newlib/libc/string/memset.o external/newlib/libc/string/memcpy.o +objs := boot/crt0.o +objs += external/freertos/tasks.o external/freertos/list.o external/freertos/queue.o external/freertos/portable/GCC/ARM_CM4F/port.o external/freertos/portable/MemMang/heap_1.o +objs += external/newlib/libc/string/memset.o external/newlib/libc/string/memcpy.o + +objs += platform/stm32f429/boot/isr.o platform/stm32f429/registers/gpio.o platform/stm32f429/registers/rcc.o platform/stm32f429/registers/spi.o platform/stm32f429/spi.o default: clean boot.elf run: boot.elf $(GDB) -x gdb_script.gdb boot.elf - test: test.elf $(GDB) -x test/gdb_script.gdb test.elf @@ -37,7 +41,7 @@ boot.bin: boot.elf boot.elf: $(objs) src/lcd_spi.o @echo "LD $@" - @$(LD) -T boot/stm32f429.ld $(objs) src/lcd_spi.o -o $@ + @$(LD) -T platform/stm32f429/boot/flash.ld $(objs) src/lcd_spi.o -o $@ %.o: %.c @echo "CC $@" diff --git a/arch/stm32f429/registers.h b/arch/stm32f429/registers.h deleted file mode 100644 index 7c45a7247..000000000 --- a/arch/stm32f429/registers.h +++ /dev/null @@ -1,3 +0,0 @@ -#include -#include -#include diff --git a/boot/stm32f429.ld b/platform/stm32f429/boot/flash.ld similarity index 100% rename from boot/stm32f429.ld rename to platform/stm32f429/boot/flash.ld diff --git a/arch/stm32f429/isr.c b/platform/stm32f429/boot/isr.c similarity index 100% rename from arch/stm32f429/isr.c rename to platform/stm32f429/boot/isr.c diff --git a/arch/stm32f429/isr.h b/platform/stm32f429/boot/isr.h similarity index 100% rename from arch/stm32f429/isr.h rename to platform/stm32f429/boot/isr.h diff --git a/platform/stm32f429/registers.h b/platform/stm32f429/registers.h new file mode 100644 index 000000000..53d567fe8 --- /dev/null +++ b/platform/stm32f429/registers.h @@ -0,0 +1,3 @@ +#include "registers/gpio.h" +#include "registers/rcc.h" +#include "registers/spi.h" diff --git a/arch/stm32f429/registers/gpio.c b/platform/stm32f429/registers/gpio.c similarity index 98% rename from arch/stm32f429/registers/gpio.c rename to platform/stm32f429/registers/gpio.c index c559fc5ff..7d62b2130 100644 --- a/arch/stm32f429/registers/gpio.c +++ b/platform/stm32f429/registers/gpio.c @@ -1,4 +1,4 @@ -#include +#include "gpio.h" #define GPIOA_BASE 0x40020000 #define GPIOB_BASE 0x40020400 diff --git a/arch/stm32f429/registers/gpio.h b/platform/stm32f429/registers/gpio.h similarity index 100% rename from arch/stm32f429/registers/gpio.h rename to platform/stm32f429/registers/gpio.h diff --git a/arch/stm32f429/registers/rcc.c b/platform/stm32f429/registers/rcc.c similarity index 100% rename from arch/stm32f429/registers/rcc.c rename to platform/stm32f429/registers/rcc.c diff --git a/arch/stm32f429/registers/rcc.h b/platform/stm32f429/registers/rcc.h similarity index 100% rename from arch/stm32f429/registers/rcc.h rename to platform/stm32f429/registers/rcc.h diff --git a/arch/stm32f429/registers/spi.c b/platform/stm32f429/registers/spi.c similarity index 96% rename from arch/stm32f429/registers/spi.c rename to platform/stm32f429/registers/spi.c index 376af9e05..2e2f068ec 100644 --- a/arch/stm32f429/registers/spi.c +++ b/platform/stm32f429/registers/spi.c @@ -1,4 +1,4 @@ -#include +#include "spi.h" #define SPI1_BASE 0x40013000 #define SPI2_BASE 0x40003800 diff --git a/arch/stm32f429/registers/spi.h b/platform/stm32f429/registers/spi.h similarity index 93% rename from arch/stm32f429/registers/spi.h rename to platform/stm32f429/registers/spi.h index b331ec22f..96c82880a 100644 --- a/arch/stm32f429/registers/spi.h +++ b/platform/stm32f429/registers/spi.h @@ -1,3 +1,6 @@ +#ifndef STM32F429_REGISTERS_SPI_H +#define STM32F429_REGISTERS_SPI_H 1 + #include typedef enum { @@ -67,3 +70,5 @@ SPI_SR_t * SPI_SR(SPI_t spi); typedef uint16_t SPI_DR_t; SPI_DR_t * SPI_DR(SPI_t spi); + +#endif diff --git a/platform/stm32f429/spi.c b/platform/stm32f429/spi.c new file mode 100644 index 000000000..82b47b7bc --- /dev/null +++ b/platform/stm32f429/spi.c @@ -0,0 +1,5 @@ +#include "spi.h" + +void spi_init(spi_port_t * port) { + // Do shit! +} diff --git a/platform/stm32f429/spi.h b/platform/stm32f429/spi.h new file mode 100644 index 000000000..fdbd0773f --- /dev/null +++ b/platform/stm32f429/spi.h @@ -0,0 +1,17 @@ +#ifndef STM32F429_SPI_H +#define STM32F429_SPI_H 1 + +#include +#include + +struct spi_port { + struct { + SPI_CR1_t controlRegister1; + // SPI_CR2_t controlRegister1; + } config; + struct { + int b; + } state; +}; + +#endif diff --git a/src/lcd_spi.c b/src/lcd_spi.c index cfa98f668..6c80d0dad 100644 --- a/src/lcd_spi.c +++ b/src/lcd_spi.c @@ -1,21 +1,30 @@ -#include #include #include #include #include +#include +#include + /* This code sends data to the onboard LCD over SPI * * The LCD has two interfaces, SPI and direct RGB. * We'll only use SPI in this one. * - * The documentation gives the following mapping - * Pin name - LCD-SPI - * NRST - Reset - * PC2 - CSX // Chip select for LCD - * PD13 - DCX // Data/Command register - * PF7 - SCL // SPI Clock - * PF9 - SDI/SDO // MOSI + * The Discovery board has the IM[0-3] pins of the LCD controller + * connected to low, high, high, low = 0b0110. (UM1670 p. 33). + * This tells the LCD controller to expect data this way: + * "4 wire, 8-bit serial, SDA = In/out" + * See ILI9341 p. 63 + * + * Now how are the LCD pins connected to the MCU ones? + * The Discovery board doc says this: + * MCU pin - LCD-SPI + * NRST - Reset + * PC2 - CSX // Chip select for LCD + * PD13 - DCX // Data/Command register + * PF7 - SCL // SPI Clock + * PF9 - SDI/SDO // MOSI * * See UM1670 p. 19 to 24. */ @@ -46,8 +55,62 @@ void SpiSend(void * pvParameters) { vTaskDelay(100/portTICK_PERIOD_MS); } } +/* +struct spi_port { + // Private data: + .config = { + }, + .state = { + } +}; +// Public API, private impl. +spi_init(); +spi_write(); +*/ int main(int argc, char * argv[]) { + + spi_port_t my_spi_port = { + .config = { + .controlRegister1 = { + .BIDIMODE = 1, + .BIDIOE = 1, + .MSTR = 1, + .DFF = SPI_DFF_16_BITS, + .CPOL = 0, + .BR = SPI_BR_DIV_256, + .SSM = 1, + .SSI = 1, + .SPE = 1 + } + } + }; + spi_init(&my_spi_port); + + /* + // Code we'd like to write: + + spi_port my_spi_port; + spi_init(&my_spi_port); + + ili9431 lcd_panel = { + .port = my_spi_port + }; + + ili9431_init(&lcd_panel); + lcd_panel.clear(); + lcd_panel.setGammaCurve(); + + char * fb = lcd_panel.framebuffer; + + for (int i=0;i<100;i++) { + *fb[i] = 1; + } + +*/ + + + // We'll use GPIO pins F6-F9 to emit SPI data // GPIO are grouped by letter. All GPIO groups live on the "AHB1" bus. // (this is documented in the STM32F4 reference mnual, page 65) @@ -55,6 +118,16 @@ int main(int argc, char * argv[]) { // Step 1 : Enable clock in RCC_AHBxENR RCC_AHB1ENR->GPIOFEN = 1; + // Step 2 : Set the GPIO pin C2 as output + + RCC_AHB1ENR->GPIOCEN = 1; + GPIO_MODER(GPIOC)->MODER2 = GPIO_MODE_OUTPUT; + + RCC_AHB1ENR->GPIOCEN = 1; + GPIO_MODER(GPIOC)->MODER2 = GPIO_MODE_OUTPUT; + // From now on, we'll control pin C2 with + // GPIO_ODR(GPIOC)->ODR2 = desiredValue; + // Step 2 : Configure the GPIO pin to "Alternate function number 5" // This means "SPI5 on pins F6-F9", cf STM32F249 p78 GPIO_MODER(GPIOF)->MODER6 = GPIO_MODE_ALTERNATE_FUNCTION;