From 1e3a1477ebc3ef4e653b7f892b606bb65341bc8c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=89milie=20Feral?= <emilie.feral@numworks.com>
Date: Thu, 4 Apr 2019 13:43:38 +0200
Subject: [PATCH] [ion] N0101: configure MPU for QUASPI

L1 cache can issue speculative reads to any QUADSPI address (among the 256MB).
We configure the cache to prevent such accesses
---
 ion/src/device/n0101/drivers/board.cpp | 42 +++++++++++++++++++++++++-
 ion/src/device/shared/regs/mpu.h       |  1 +
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/ion/src/device/n0101/drivers/board.cpp b/ion/src/device/n0101/drivers/board.cpp
index 9e79fb899..51894eae6 100644
--- a/ion/src/device/n0101/drivers/board.cpp
+++ b/ion/src/device/n0101/drivers/board.cpp
@@ -26,7 +26,18 @@ void initL1Cache() {
 }
 
 void initMPU() {
-  // Configure MPU settings for the FMC memory area
+  // 1. Disable the MPU
+  // 1.1 Memory barrier
+  asm volatile("dmb 0xF":::"memory");
+
+  // 1.2 Disable fault exceptions
+  CM4.SHCRS()->setMEMFAULTENA(false);
+
+  // 1.3 Disable the MPU and clear the control register
+  MPU.CTRL()->setENABLE(false);
+
+  // 2. MPU settings
+  // 2.1 Configure a MPU region for the FMC memory area
   // This is needed for interfacing with the LCD
   MPU.RNR()->setREGION(0x00);
   MPU.RBAR()->setADDR(0x60000000);
@@ -39,8 +50,37 @@ void initMPU() {
   MPU.RASR()->setB(0);
   MPU.RASR()->setENABLE(true);
 
+  // 2.2 Configure MPU regions for the QUADSPI peripheral
+  // TODO: lengthy comment
+  MPU.RNR()->setREGION(0x01);
+  MPU.RBAR()->setADDR(0x90000000);
+  MPU.RASR()->setSIZE(MPU::RASR::RegionSize::_256MB);
+  MPU.RASR()->setAP(MPU::RASR::AccessPermission::NoAccess);
+  MPU.RASR()->setXN(true);
+  MPU.RASR()->setTEX(0);
+  MPU.RASR()->setS(0);
+  MPU.RASR()->setC(0);
+  MPU.RASR()->setB(0);
+  MPU.RASR()->setENABLE(true);
+
+  MPU.RNR()->setREGION(0x02);
+  MPU.RBAR()->setADDR(0x90000000);
+  MPU.RASR()->setSIZE(MPU::RASR::RegionSize::_8MB);
+  MPU.RASR()->setAP(MPU::RASR::AccessPermission::RW);
+  MPU.RASR()->setXN(false);
+  MPU.RASR()->setTEX(0);
+  MPU.RASR()->setS(0);
+  MPU.RASR()->setC(1);
+  MPU.RASR()->setB(0);
+  MPU.RASR()->setENABLE(true);
+
+  // 2.3 Enable MPU
   MPU.CTRL()->setPRIVDEFENA(true);
   MPU.CTRL()->setENABLE(true);
+
+  // 3. Data/instruction synchronisation barriers to ensure that the new MPU configuration is used by subsequent instructions.
+  asm volatile("dsb 0xF":::"memory");
+  asm volatile("isb 0xF":::"memory");
 }
 
 void init() {
diff --git a/ion/src/device/shared/regs/mpu.h b/ion/src/device/shared/regs/mpu.h
index afca991ca..f4f8303b5 100644
--- a/ion/src/device/shared/regs/mpu.h
+++ b/ion/src/device/shared/regs/mpu.h
@@ -63,6 +63,7 @@ public:
       _4MB = 21,
       _8MB = 22,
       _32MB = 24,
+      _256MB = 27,
       _1GB = 0b11101,
       _4GB = 0b11111
     };