mirror of
https://github.com/UpsilonNumworks/Upsilon.git
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[ion/bootloader] Made exam mode work
This commit is contained in:
M4x1m3
@@ -1,20 +1,12 @@
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ion_device_src += $(addprefix ion/src/device/bootloader/drivers/, \
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board.cpp \
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cache.cpp \
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external_flash.cpp \
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led.cpp \
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power.cpp \
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reset.cpp \
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usb.cpp \
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)
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ion_device_src += $(addprefix ion/src/device/bootloader/drivers/, \
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board.cpp \
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cache.cpp \
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external_flash.cpp \
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external_flash_tramp.cpp \
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led.cpp \
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power.cpp \
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reset.cpp \
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trampoline.cpp \
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usb.cpp \
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)
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466
ion/src/device/bootloader/drivers/external_flash_tramp.cpp
Normal file
466
ion/src/device/bootloader/drivers/external_flash_tramp.cpp
Normal file
@@ -0,0 +1,466 @@
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#include <drivers/external_flash.h>
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#include <drivers/cache.h>
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#include <drivers/config/external_flash.h>
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#include <drivers/config/clocks.h>
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#include <drivers/trampoline.h>
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#include <ion/timing.h>
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namespace Ion {
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namespace Device {
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namespace ExternalFlash {
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using namespace Regs;
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/* The external flash and the Quad-SPI peripheral support several operating
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* modes, corresponding to different numbers of signals used to communicate
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* during each phase of the command sequence.
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*
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* Mode name for | Number of signals used during each phase:
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* external flash | Instruction | Address | Alt. bytes | Data
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* ----------------+-------------+---------+------------+------
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* Standard SPI | 1 | 1 | 1 | 1
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* Dual-Output SPI | 1 | 1 | 1 | 2
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* Dual-I/O SPI | 1 | 2 | 2 | 2
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* Quad-Output SPI | 1 | 1 | 1 | 4
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* Quad-I/O SPI | 1 | 4 | 4 | 4
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* QPI | 4 | 4 | 4 | 4
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*
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* The external flash supports clock frequencies up to 104MHz for all
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* instructions, except for Read Data (0x03) which is supported up to 50Mhz.
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*
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*
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* Quad-SPI block diagram
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*
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* +----------------------+ +------------+
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* | Quad-SPI | | |
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* | peripheral | | External |
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* | | read | flash |
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* AHB <-- | data <-- 32-byte | <-- | memory |
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* matrix --> | register --> FIFO | --> | |
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* +----------------------+ write +------------+
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*
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* Any data transmitted to or from the external flash memory go through a
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* 32-byte FIFO.
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*
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* Read or write operations are performed in burst mode, that is, after any data
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* byte is transmitted between the Quad-SPI and the flash memory, the latter
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* automatically increments the specified address and the next byte to read or
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* write is respectively pushed in or popped from the FIFO.
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* And so on, as long as the clock continues.
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*
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* If the FIFO gets full in a read operation or
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* if the FIFO gets empty in a write operation,
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* the operation stalls and CLK stays low until firmware services the FIFO.
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*
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* If the FIFO gets full in a write operation, the operation is stalled until
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* the FIFO has enough space to accept the amount of data being written.
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* If the FIFO does not have as many bytes as requested by the read operation
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* and if BUSY=1, the operation is stalled until enough data is present or until
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* the transfer is complete, whichever happens first. */
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enum class Command : uint8_t {
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WriteStatusRegister = 0x01,
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PageProgram = 0x02, // Program previously erased memory areas as being "0"
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ReadData = 0x03,
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ReadStatusRegister1 = 0x05,
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WriteEnable = 0x06,
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Erase4KbyteBlock = 0x20,
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WriteStatusRegister2 = 0x31,
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QuadPageProgramW25Q64JV = 0x32,
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QuadPageProgramAT25F641 = 0x33,
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ReadStatusRegister2 = 0x35,
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Erase32KbyteBlock = 0x52,
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EnableReset = 0x66,
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Reset = 0x99,
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ReadJEDECID = 0x9F,
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ReleaseDeepPowerDown = 0xAB,
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DeepPowerDown = 0xB9,
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ChipErase = 0xC7, // Erase the whole chip or a 64-Kbyte block as being "1"
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Erase64KbyteBlock = 0xD8,
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FastReadQuadIO = 0xEB
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};
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static constexpr uint8_t NumberOfAddressBitsIn64KbyteBlock = 16;
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static constexpr uint8_t NumberOfAddressBitsIn32KbyteBlock = 15;
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static constexpr uint8_t NumberOfAddressBitsIn4KbyteBlock = 12;
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class ExternalFlashStatusRegister {
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public:
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class StatusRegister1 : public Register8 {
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public:
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using Register8::Register8;
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REGS_BOOL_FIELD_R(BUSY, 0);
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};
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class StatusRegister2 : public Register8 {
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public:
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using Register8::Register8;
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REGS_BOOL_FIELD(QE, 1);
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};
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};
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class OperatingModes {
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public:
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constexpr OperatingModes(
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QUADSPI::CCR::OperatingMode instruction,
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QUADSPI::CCR::OperatingMode address,
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QUADSPI::CCR::OperatingMode data) :
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m_instructionOperatingMode(instruction),
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m_addressOperatingMode(address),
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m_dataOperatingMode(data)
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{}
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QUADSPI::CCR::OperatingMode instructionOperatingMode() const { return m_instructionOperatingMode; }
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QUADSPI::CCR::OperatingMode addressOperatingMode() const { return m_addressOperatingMode; }
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QUADSPI::CCR::OperatingMode dataOperatingMode() const { return m_dataOperatingMode; }
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private:
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QUADSPI::CCR::OperatingMode m_instructionOperatingMode;
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QUADSPI::CCR::OperatingMode m_addressOperatingMode;
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QUADSPI::CCR::OperatingMode m_dataOperatingMode;
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};
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/* W25Q64JV does not implement QPI-4-4-4, so we always send the instructions on
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* one wire only.*/
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static constexpr OperatingModes sOperatingModes100(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::NoData, QUADSPI::CCR::OperatingMode::NoData);
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static constexpr OperatingModes sOperatingModes101(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::NoData, QUADSPI::CCR::OperatingMode::Single);
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static constexpr OperatingModes sOperatingModes110(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::NoData);
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static constexpr OperatingModes sOperatingModes111(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single);
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static constexpr OperatingModes sOperatingModes114(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Quad);
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static constexpr OperatingModes sOperatingModes144(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Quad, QUADSPI::CCR::OperatingMode::Quad);
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static QUADSPI::CCR::OperatingMode sOperatingMode = QUADSPI::CCR::OperatingMode::Single;
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static constexpr int ClockFrequencyDivisor = 2; // F(QUADSPI) = F(AHB) / ClockFrequencyDivisor
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static constexpr int FastReadQuadIODummyCycles = 4; // Must be 4 for W25Q64JV (Fig 24.A page 34) and for AT25F641 (table 7.19 page 28)
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/* According to datasheets, the CS signal should stay high (deselect the device)
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* for t_SHSL = 50ns at least.
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* -> Max of 30ns (see AT25F641 Sections 8.7 and 8.8),
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* 10ns and 50ns (see W25Q64JV Section 9.6). */
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static constexpr float ChipSelectHighTimeInNanoSeconds = 50.0f;
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static void send_command_full(
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QUADSPI::CCR::FunctionalMode functionalMode,
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OperatingModes operatingModes,
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Command c,
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uint8_t * address,
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uint32_t altBytes,
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size_t numberOfAltBytes,
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uint8_t dummyCycles,
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uint8_t * data,
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size_t dataLength);
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static inline void send_command(Command c) {
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectWrite,
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sOperatingModes100,
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c,
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
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0, 0,
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0,
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nullptr, 0);
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}
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static inline void send_write_command(Command c, uint8_t * address, const uint8_t * data, size_t dataLength, OperatingModes operatingModes) {
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectWrite,
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operatingModes,
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c,
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address,
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0, 0,
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0,
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const_cast<uint8_t *>(data), dataLength);
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}
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static inline void send_read_command(Command c, uint8_t * address, uint8_t * data, size_t dataLength) {
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectRead,
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sOperatingModes101,
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c,
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address,
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0, 0,
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0,
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data, dataLength);
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}
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static inline void wait() {
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/* The DSB instruction guarantees the completion of a write operation before
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* polling the status register. */
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Cache::dsb();
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ExternalFlashStatusRegister::StatusRegister1 statusRegister1(0);
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do {
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send_read_command(Command::ReadStatusRegister1, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&statusRegister1), sizeof(statusRegister1));
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} while (statusRegister1.getBUSY());
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}
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static void set_as_memory_mapped() {
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/* In memory-mapped mode, all AHB masters may access the external flash memory as an internal one:
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* the programmed instruction is sent automatically whenever an AHB master reads in the Quad-SPI flash bank area.
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* (The QUADSPI_DLR register has no meaning and any access to QUADSPI_DR returns zero.)
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*
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* To anticipate sequential reads, the nCS signal is maintained low so as to
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* keep the read operation active and prefetch the subsequent bytes in the FIFO.
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*
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* It goes low, only if the low-power timeout counter is enabled.
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* (Flash memories tend to consume more when nCS is held low.) */
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send_command_full(
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QUADSPI::CCR::FunctionalMode::MemoryMapped,
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sOperatingModes144,
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Command::FastReadQuadIO,
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
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0xA0, 1,
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FastReadQuadIODummyCycles,
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nullptr, 0
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);
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}
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static void unset_memory_mapped_mode() {
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/* Reset Continuous Read Mode Bits before issuing normal instructions. */
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uint8_t dummyData;
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectRead,
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sOperatingModes144,
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Command::FastReadQuadIO,
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0,
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~(0xA0), 1,
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FastReadQuadIODummyCycles,
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&dummyData, 1
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);
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}
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static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, OperatingModes operatingModes, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength) {
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/* According to ST's Errata Sheet ES0360, "Wrong data can be read in
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* memory-mapped after an indirect mode operation". This is the workaround. */
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if (functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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QUADSPI::CCR::FunctionalMode previousMode = QUADSPI.CCR()->getFMODE();
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if (previousMode == QUADSPI::CCR::FunctionalMode::IndirectWrite || previousMode == QUADSPI::CCR::FunctionalMode::IndirectRead) {
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// Reset the address register
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QUADSPI.AR()->set(0); // No write to DR should be done after this
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if (previousMode == QUADSPI::CCR::FunctionalMode::IndirectRead) {
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// Make an abort request to stop the reading and clear the busy bit
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QUADSPI.CR()->setABORT(true);
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while (QUADSPI.CR()->getABORT()) {
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}
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}
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}
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} else if (QUADSPI.CCR()->getFMODE() == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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/* "BUSY goes high as soon as the first memory-mapped access occurs. Because
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* of the prefetch operations, BUSY does not fall until there is a timeout,
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* there is an abort, or the peripheral is disabled". (From the Reference
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* Manual)
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* If we are leaving memory-mapped mode, we send an abort to clear BUSY. */
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QUADSPI.CR()->setABORT(true);
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while (QUADSPI.CR()->getABORT()) {
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}
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}
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assert(QUADSPI.CCR()->getFMODE() != QUADSPI::CCR::FunctionalMode::MemoryMapped || QUADSPI.SR()->getBUSY() == 0);
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class QUADSPI::CCR ccr(0);
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ccr.setFMODE(functionalMode);
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if (data != nullptr || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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ccr.setDMODE(operatingModes.dataOperatingMode());
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}
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if (functionalMode != QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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QUADSPI.DLR()->set((dataLength > 0) ? dataLength-1 : 0);
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}
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ccr.setDCYC(dummyCycles);
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if (numberOfAltBytes > 0) {
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ccr.setABMODE(operatingModes.addressOperatingMode()); // Seems to always be the same as address mode
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ccr.setABSIZE(static_cast<QUADSPI::CCR::Size>(numberOfAltBytes - 1));
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QUADSPI.ABR()->set(altBytes);
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}
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if (address != reinterpret_cast<uint8_t *>(FlashAddressSpaceSize) || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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ccr.setADMODE(operatingModes.addressOperatingMode());
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ccr.setADSIZE(QUADSPI::CCR::Size::ThreeBytes);
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}
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ccr.setIMODE(operatingModes.instructionOperatingMode());
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ccr.setINSTRUCTION(static_cast<uint8_t>(c));
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if (functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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ccr.setSIOO(true);
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/* If the SIOO bit is set, the instruction is sent only for the first command following a write to QUADSPI_CCR.
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* Subsequent command sequences skip the instruction phase, until there is a write to QUADSPI_CCR. */
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}
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QUADSPI.CCR()->set(ccr);
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if (address != reinterpret_cast<uint8_t *>(FlashAddressSpaceSize)) {
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QUADSPI.AR()->set(reinterpret_cast<uint32_t>(address));
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}
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if (functionalMode == QUADSPI::CCR::FunctionalMode::IndirectWrite) {
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for (size_t i=0; i<dataLength; i++) {
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QUADSPI.DR()->set(data[i]);
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}
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} else if (functionalMode == QUADSPI::CCR::FunctionalMode::IndirectRead) {
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for (size_t i=0; i<dataLength; i++) {
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data[i] = QUADSPI.DR()->get();
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}
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}
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/* Wait for the command to be sent.
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* "When configured in memory-mapped mode, because of the prefetch operations,
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* BUSY does not fall until there is a timeout, there is an abort, or the
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* peripheral is disabled.", so we do not wait if the device is in
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* memory-mapped mode. */
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if (functionalMode != QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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while (QUADSPI.SR()->getBUSY()) {
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}
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}
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}
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static void initGPIO() {
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for(const AFGPIOPin & p : Config::Pins) {
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p.init();
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}
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}
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static void initQSPI() {
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// Enable QUADSPI AHB3 peripheral clock
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RCC.AHB3ENR()->setQSPIEN(true);
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// Configure controller for target device
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class QUADSPI::DCR dcr(0);
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dcr.setFSIZE(NumberOfAddressBitsInChip - 1);
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constexpr int ChipSelectHighTimeCycles = (ChipSelectHighTimeInNanoSeconds * static_cast<float>(Clocks::Config::AHBFrequency)) / (static_cast<float>(ClockFrequencyDivisor) * 1000.0f) + 1.0f;
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dcr.setCSHT(ChipSelectHighTimeCycles - 1);
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||||
dcr.setCKMODE(true);
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||||
QUADSPI.DCR()->set(dcr);
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class QUADSPI::CR cr(0);
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cr.setPRESCALER(ClockFrequencyDivisor - 1);
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cr.setEN(true);
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QUADSPI.CR()->set(cr);
|
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}
|
||||
|
||||
static void initChip() {
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// Release sleep deep
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send_command(Command::ReleaseDeepPowerDown);
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Timing::usleep(3);
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|
||||
/* The chip initially expects commands in SPI mode. We need to use SPI to tell
|
||||
* it to switch to QuadSPI/QPI. */
|
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if (sOperatingMode == QUADSPI::CCR::OperatingMode::Single) {
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send_command(Command::WriteEnable);
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||||
ExternalFlashStatusRegister::StatusRegister2 statusRegister2(0);
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statusRegister2.setQE(true);
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wait();
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send_write_command(Command::WriteStatusRegister2, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&statusRegister2), sizeof(statusRegister2), sOperatingModes101);
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wait();
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sOperatingMode = QUADSPI::CCR::OperatingMode::Quad;
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}
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set_as_memory_mapped();
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}
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||||
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||||
void init() {
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if (Config::NumberOfSectors == 0) {
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||||
return;
|
||||
}
|
||||
initGPIO();
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||||
initQSPI();
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||||
initChip();
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||||
}
|
||||
|
||||
static void shutdownGPIO() {
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||||
for(const AFGPIOPin & p : Config::Pins) {
|
||||
p.group().OSPEEDR()->setOutputSpeed(p.pin(), GPIO::OSPEEDR::OutputSpeed::Low);
|
||||
p.group().MODER()->setMode(p.pin(), GPIO::MODER::Mode::Analog);
|
||||
p.group().PUPDR()->setPull(p.pin(), GPIO::PUPDR::Pull::None);
|
||||
}
|
||||
}
|
||||
|
||||
static void shutdownChip() {
|
||||
unset_memory_mapped_mode();
|
||||
// Reset
|
||||
send_command(Command::EnableReset);
|
||||
send_command(Command::Reset);
|
||||
sOperatingMode = QUADSPI::CCR::OperatingMode::Single;
|
||||
Timing::usleep(30);
|
||||
|
||||
// Sleep deep
|
||||
send_command(Command::DeepPowerDown);
|
||||
Timing::usleep(3);
|
||||
}
|
||||
|
||||
static void shutdownQSPI() {
|
||||
// Reset the controller
|
||||
RCC.AHB3RSTR()->setQSPIRST(true);
|
||||
RCC.AHB3RSTR()->setQSPIRST(false);
|
||||
|
||||
RCC.AHB3ENR()->setQSPIEN(false); // TODO: move in Device::shutdownClocks
|
||||
}
|
||||
|
||||
void shutdown() {
|
||||
if (Config::NumberOfSectors == 0) {
|
||||
return;
|
||||
}
|
||||
shutdownChip();
|
||||
shutdownQSPI();
|
||||
shutdownGPIO();
|
||||
}
|
||||
|
||||
int SectorAtAddress(uint32_t address) {
|
||||
/* WARNING: this code assumes that the flash sectors are of increasing size:
|
||||
* first all 4K sectors, then all 32K sectors, and finally all 64K sectors. */
|
||||
int i = address >> NumberOfAddressBitsIn64KbyteBlock;
|
||||
if (i > Config::NumberOf64KSectors) {
|
||||
return -1;
|
||||
}
|
||||
if (i >= 1) {
|
||||
return Config::NumberOf4KSectors + Config::NumberOf32KSectors + i - 1;
|
||||
}
|
||||
i = address >> NumberOfAddressBitsIn32KbyteBlock;
|
||||
if (i >= 1) {
|
||||
i = Config::NumberOf4KSectors + i - 1;
|
||||
assert(i >= 0 && i <= Config::NumberOf32KSectors);
|
||||
return i;
|
||||
}
|
||||
i = address >> NumberOfAddressBitsIn4KbyteBlock;
|
||||
assert(i <= Config::NumberOf4KSectors);
|
||||
return i;
|
||||
}
|
||||
|
||||
void unlockFlash() {
|
||||
// Warning: unset_memory_mapped_mode must be called before
|
||||
send_command(Command::WriteEnable);
|
||||
wait();
|
||||
ExternalFlashStatusRegister::StatusRegister1 statusRegister1(0);
|
||||
ExternalFlashStatusRegister::StatusRegister2 statusRegister2(0);
|
||||
ExternalFlashStatusRegister::StatusRegister2 currentStatusRegister2(0);
|
||||
send_read_command(Command::ReadStatusRegister2, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(¤tStatusRegister2), sizeof(currentStatusRegister2));
|
||||
statusRegister2.setQE(currentStatusRegister2.getQE());
|
||||
|
||||
uint8_t registers[] = {statusRegister1.get(), statusRegister2.get()};
|
||||
send_write_command(Command::WriteStatusRegister, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(registers), sizeof(registers), sOperatingModes101);
|
||||
wait();
|
||||
}
|
||||
|
||||
void JDECid(uint8_t * manufacturerID, uint8_t * memoryType, uint8_t * capacityType) {
|
||||
unset_memory_mapped_mode();
|
||||
struct JEDECId {
|
||||
uint8_t manufacturerID;
|
||||
uint8_t memoryType;
|
||||
uint8_t capacityType;
|
||||
};
|
||||
JEDECId id;
|
||||
send_read_command(Command::ReadJEDECID, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&id), sizeof(id));
|
||||
*manufacturerID = id.manufacturerID;
|
||||
*memoryType = id.memoryType;
|
||||
*capacityType = id.capacityType;
|
||||
set_as_memory_mapped();
|
||||
}
|
||||
|
||||
void MassErase() {
|
||||
// Mass erase is not enabled on kernel
|
||||
assert(false);
|
||||
}
|
||||
|
||||
void WriteMemory(uint8_t * destination, const uint8_t * source, size_t length) {
|
||||
asm("cpsid if");
|
||||
reinterpret_cast<void(*)(uint8_t*, const uint8_t*, size_t)>(Ion::Device::Trampoline::address(Ion::Device::Trampoline::ExternalFlashWriteMemory))(destination + ExternalFlash::Config::StartAddress, source, length);
|
||||
asm("cpsie if");
|
||||
}
|
||||
|
||||
void EraseSector(int i) {
|
||||
asm("cpsid if");
|
||||
reinterpret_cast<void(*)(int)>(Ion::Device::Trampoline::address(Ion::Device::Trampoline::ExternalFlashEraseSector))(i);
|
||||
asm("cpsie if");
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
14
ion/src/device/bootloader/drivers/trampoline.cpp
Normal file
14
ion/src/device/bootloader/drivers/trampoline.cpp
Normal file
@@ -0,0 +1,14 @@
|
||||
#include <drivers/trampoline.h>
|
||||
#include <string.h>
|
||||
|
||||
namespace Ion {
|
||||
namespace Device {
|
||||
namespace Trampoline {
|
||||
|
||||
uint32_t address(int index) {
|
||||
return 0x0020E000 + sizeof(void *) * index;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
22
ion/src/device/bootloader/drivers/trampoline.h
Normal file
22
ion/src/device/bootloader/drivers/trampoline.h
Normal file
@@ -0,0 +1,22 @@
|
||||
#ifndef ION_DEVICE_BOOTLOADER_DRIVERS_TRAMPOLINE_H
|
||||
#define ION_DEVICE_BOOTLOADER_DRIVERS_TRAMPOLINE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
namespace Ion {
|
||||
namespace Device {
|
||||
namespace Trampoline {
|
||||
|
||||
constexpr int Suspend = 0;
|
||||
constexpr int ExternalFlashEraseSector = 1;
|
||||
constexpr int ExternalFlashWriteMemory = 2;
|
||||
|
||||
// TODO: Use the other available trampolines instead of liba's functions
|
||||
|
||||
uint32_t address(int index);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user