From 3c173e3219c373aa6c0c2a5dae34c276de370434 Mon Sep 17 00:00:00 2001
From: Romain Goyet <romain@goyet.com>
Date: Mon, 4 May 2015 15:53:00 +0200
Subject: [PATCH] Dedicated isr implementation

---
 arch/stm32f429/isr.c | 32 ++++++++++++++++++++++++++++++++
 arch/stm32f429/isr.h |  8 ++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 arch/stm32f429/isr.c
 create mode 100644 arch/stm32f429/isr.h

diff --git a/arch/stm32f429/isr.c b/arch/stm32f429/isr.c
new file mode 100644
index 000000000..01f75f3a3
--- /dev/null
+++ b/arch/stm32f429/isr.c
@@ -0,0 +1,32 @@
+#include "isr.h"
+
+extern const void * _stack_start;
+
+/* Interrupt Service Routines are void->void functions */
+typedef void(*ISR)(void);
+
+/* Notice: The Cortex-M4 expects all jumps to be made at an odd address when
+ * jumping to Thumb code. For example, if you want to execute Thumb code at
+ * address 0x100, you'll have to jump to 0x101. Luckily, this idiosyncrasy is
+ * properly handled by the C compiler that will generate proper addresses when
+ * using function pointers. */
+
+#define INITIALISATION_VECTOR_SIZE 0x6B
+
+ISR InitialisationVector[INITIALISATION_VECTOR_SIZE]
+  __attribute__((section(".isr_vector_table")))
+  = {
+  (ISR)&_stack_start,
+  _ResetServiceRoutine,
+  _NMIServiceRoutine,
+  _HardFaultServiceRoutine,
+  _MemManageServiceRoutine,
+  _BusFaultServiceRoutine,
+  0, // UsageFault
+  0, // Reserved
+  _SVCallServiceRoutine,
+  0, // Debug Monitor
+  _PendSVServiceRoutine,
+  _SysTickServiceRoutine,
+  0
+};
diff --git a/arch/stm32f429/isr.h b/arch/stm32f429/isr.h
new file mode 100644
index 000000000..bbe49b6bd
--- /dev/null
+++ b/arch/stm32f429/isr.h
@@ -0,0 +1,8 @@
+void _ResetServiceRoutine(void);
+void _NMIServiceRoutine(void);
+void _HardFaultServiceRoutine(void);
+void _MemManageServiceRoutine(void);
+void _BusFaultServiceRoutine(void);
+void _SVCallServiceRoutine(void);
+void _PendSVServiceRoutine(void);
+void _SysTickServiceRoutine(void);