mirror of
https://github.com/UpsilonNumworks/Upsilon.git
synced 2026-03-18 21:30:38 +01:00
Bootloader pre-release
This commit is contained in:
devdl11
@@ -4,9 +4,13 @@
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#include <drivers/config/clocks.h>
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#include <drivers/config/internal_flash.h>
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#include <drivers/external_flash.h>
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#include <drivers/timing.h>
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#include <regs/regs.h>
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#include <ion.h>
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#include <bootloader/drivers/stm32_drivers.h>
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using namespace STM32;
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typedef void(*ISR)(void);
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extern ISR InitialisationVector[];
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@@ -439,6 +443,20 @@ bool pcbVersionIsLocked() {
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return *reinterpret_cast<const uint8_t *>(InternalFlash::Config::OTPLockAddress(k_pcbVersionOTPIndex)) == 0;
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}
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void jumpToInternalBootloader() {
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asm volatile ("cpsie i" : : : "memory");
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STM32::rcc_deinit();
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STM32::hal_deinit();
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STM32::systick_deinit();
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const uint32_t p = (*((uint32_t *) 0x1FF00000));
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asm volatile ("MSR msp, %0" : : "r" (p) : );
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void (*SysMemBootJump)(void);
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SysMemBootJump = (void (*)(void)) (*((uint32_t *) 0x1FF00004));
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SysMemBootJump();
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}
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}
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}
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}
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56
bootloader/drivers/stm32_drivers.cpp
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56
bootloader/drivers/stm32_drivers.cpp
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@@ -0,0 +1,56 @@
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#include "stm32_drivers.h"
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void STM32::rcc_deinit() {
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SET_BIT(STM_32_RCC->CR, (0x1UL << (0U)));
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while (READ_BIT(STM_32_RCC->CR, (0x1UL << (1U))) == 0) {}
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SET_BIT(STM_32_RCC->CR, (0x10UL << (3U)));
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CLEAR_REG(STM_32_RCC->CFGR);
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while (READ_BIT(STM_32_RCC->CFGR, (0x3UL << (2U))) != 0) {}
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CLEAR_BIT(STM_32_RCC->CR, (0x1UL << (16U)) | (0x1UL << (18U)) | (0x1UL << (19U)));
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while (READ_BIT(STM_32_RCC->CR, (0x1UL << (17U))) != 0) {}
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CLEAR_BIT(STM_32_RCC->CR, (0x1UL << (24U)));
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while (READ_BIT(STM_32_RCC->CR, (0x1UL << (25U))) != 0) {}
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CLEAR_BIT(STM_32_RCC->CR, (0x1UL << (26U)));
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while (READ_BIT(STM_32_RCC->CR, (0x1UL << (27U))) != 0) {}
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CLEAR_BIT(STM_32_RCC->CR, (0x1UL << (28U)));
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while (READ_BIT(STM_32_RCC->CR, (0x1UL << (29U))) != 0) {}
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STM_32_RCC->PLLCFGR = ((0x10UL << (0x0U)) | (0x040UL << (6U)) | (0x080UL << (6U)) | (0x4UL << (24U)) | 0x20000000U);
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STM_32_RCC->PLLI2SCFGR = ((0x040UL << (6U)) | (0x080UL << (6U)) | (0x4UL << (24U)) | (0x2UL << (28U)));
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STM_32_RCC->PLLSAICFGR = ((0x040UL << (6U)) | (0x080UL << (6U)) | (0x4UL << (24U)) | 0x20000000U);
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CLEAR_BIT(STM_32_RCC->CIR, ((0x1UL << (8U)) | (0x1UL << (9U)) | (0x1UL << (10U)) | (0x1UL << (11U)) | (0x1UL << (12U)) | (0x1UL << (13U)) | (0x1UL << (14U))));
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SET_BIT(STM_32_RCC->CIR, ((0x1UL << (16U)) | (0x1UL << (17U)) | (0x1UL << (18U)) | (0x1UL << (19U)) | (0x1UL << (20U)) | (0x1UL << (21U)) | (0x1UL << (22U)) | (0x1UL << (23U))));
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CLEAR_BIT(STM_32_RCC->CSR, ((0x1UL << (0U))));
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SET_BIT(STM_32_RCC->CSR, ((0x1UL << (24U))));
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uint32_t sysclock = ((uint32_t)16000000U);
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uint32_t a = ((sysclock / 1000U));
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uint32_t b = 15U;
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STM_32_SysTick->LOAD = (uint32_t)(a - 1UL);
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STM_32_SCB->SHPR[(((uint32_t)(-1))&0xFUL)-4UL] = (uint8_t)((((1UL << 4U)-1UL) << (8U - 4UL)) & (uint32_t)0xFFUL);
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STM_32_SysTick->VAL = 0U;
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STM_32_SysTick->CTRL = (1UL << 2U) | (1UL << 1U) | (1UL);
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uint32_t c = ((uint32_t)((STM_32_SCB->AIRCR & (7UL << 8U)) >> 8U));
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uint32_t d = (c & (uint32_t)0x07UL);
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uint32_t e;
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uint32_t f;
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e = ((7UL - d) > (uint32_t)(4UL)) ? (uint32_t)(4UL) : (7UL - d);
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f = ((d + (uint32_t)(4UL)) < (uint32_t)(7UL)) ? (uint32_t)(0UL) : (uint32_t)((d - 7UL) + (uint32_t)(4UL));
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uint32_t g = (((b & (uint32_t)((1UL << (e)) - 1UL)) << f) | ((0UL & (uint32_t)((1UL << (f)) - 1UL))));
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STM_32_SCB->SHPR[(((uint32_t)(-1))&0xFUL)-4UL] = (uint8_t)((g << (8U - 4UL)) & (uint32_t)0xFFUL);
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}
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void STM32::hal_deinit() {
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STM_32_RCC->APB1RSTR = 0xFFFFFFFFU;
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STM_32_RCC->APB1RSTR = 0x00U;
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STM_32_RCC->APB2RSTR = 0xFFFFFFFFU;
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STM_32_RCC->APB2RSTR = 0x00U;
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STM_32_RCC->AHB1RSTR = 0xFFFFFFFFU;
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STM_32_RCC->AHB1RSTR = 0x00U;
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STM_32_RCC->AHB2RSTR = 0xFFFFFFFFU;
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STM_32_RCC->AHB2RSTR = 0x00U;
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STM_32_RCC->AHB3RSTR = 0xFFFFFFFFU;
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STM_32_RCC->AHB3RSTR = 0x00U;
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}
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void STM32::systick_deinit() {
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STM_32_SysTick->CTRL = STM_32_SysTick->LOAD = STM_32_SysTick->VAL = 0;
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}
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153
bootloader/drivers/stm32_drivers.h
Normal file
153
bootloader/drivers/stm32_drivers.h
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@@ -0,0 +1,153 @@
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#include <stdint.h>
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/*
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Here we implement a very little part of the code from the default stm32 libs because we only need the unload function.
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Now we include the license of the original code as required.
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*/
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/*
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This software component is provided to you as part of a software package and
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applicable license terms are in the Package_license file. If you received this
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software component outside of a package or without applicable license terms,
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the terms of the BSD-3-Clause license shall apply.
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You may obtain a copy of the BSD-3-Clause at:
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https://opensource.org/licenses/BSD-3-Clause
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*/
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namespace STM32 {
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typedef struct
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{
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volatile uint32_t CR;
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volatile uint32_t PLLCFGR;
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volatile uint32_t CFGR;
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volatile uint32_t CIR;
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volatile uint32_t AHB1RSTR;
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volatile uint32_t AHB2RSTR;
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volatile uint32_t AHB3RSTR;
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uint32_t RESERVED0;
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volatile uint32_t APB1RSTR;
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volatile uint32_t APB2RSTR;
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uint32_t RESERVED1[2];
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volatile uint32_t AHB1ENR;
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volatile uint32_t AHB2ENR;
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volatile uint32_t AHB3ENR;
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uint32_t RESERVED2;
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volatile uint32_t APB1ENR;
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volatile uint32_t APB2ENR;
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uint32_t RESERVED3[2];
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volatile uint32_t AHB1LPENR;
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volatile uint32_t AHB2LPENR;
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volatile uint32_t AHB3LPENR;
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uint32_t RESERVED4;
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volatile uint32_t APB1LPENR;
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volatile uint32_t APB2LPENR;
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uint32_t RESERVED5[2];
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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uint32_t RESERVED6[2];
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volatile uint32_t SSCGR;
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volatile uint32_t PLLI2SCFGR;
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volatile uint32_t PLLSAICFGR;
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volatile uint32_t DCKCFGR1;
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volatile uint32_t DCKCFGR2;
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} STM32_RCC_TypeDef;
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typedef struct
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{
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volatile uint32_t CTRL;
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volatile uint32_t LOAD;
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volatile uint32_t VAL;
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volatile const uint32_t CALIB;
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} STM32_SysTick_Type;
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typedef struct
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{
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volatile uint32_t ISER[8U];
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uint32_t RESERVED0[24U];
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volatile uint32_t ICER[8U];
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uint32_t RSERVED1[24U];
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volatile uint32_t ISPR[8U];
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uint32_t RESERVED2[24U];
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volatile uint32_t ICPR[8U];
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uint32_t RESERVED3[24U];
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volatile uint32_t IABR[8U];
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uint32_t RESERVED4[56U];
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volatile uint8_t IP[240U];
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uint32_t RESERVED5[644U];
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volatile uint32_t STIR;
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} STM32_NVIC_Type;
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typedef struct {
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volatile const uint32_t CPUID;
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volatile uint32_t ICSR;
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volatile uint32_t VTOR;
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volatile uint32_t AIRCR;
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volatile uint32_t SCR;
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volatile uint32_t CCR;
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volatile uint8_t SHPR[12U];
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volatile uint32_t SHCSR;
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volatile uint32_t CFSR;
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volatile uint32_t HFSR;
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volatile uint32_t DFSR;
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volatile uint32_t MMFAR;
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volatile uint32_t BFAR;
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volatile uint32_t AFSR;
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volatile const uint32_t ID_PFR[2U];
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volatile const uint32_t ID_DFR;
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volatile const uint32_t ID_AFR;
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volatile const uint32_t ID_MFR[4U];
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volatile const uint32_t ID_ISAR[5U];
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uint32_t RESERVED0[1U];
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volatile const uint32_t CLIDR;
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volatile const uint32_t CTR;
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volatile const uint32_t CCSIDR;
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volatile uint32_t CSSELR;
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volatile uint32_t CPACR;
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uint32_t RESERVED3[93U];
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volatile uint32_t STIR;
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uint32_t RESERVED4[15U];
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volatile const uint32_t MVFR0;
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volatile const uint32_t MVFR1;
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volatile const uint32_t MVFR2;
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uint32_t RESERVED5[1U];
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volatile uint32_t ICIALLU;
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uint32_t RESERVED6[1U];
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volatile uint32_t ICIMVAU;
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volatile uint32_t DCIMVAC;
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volatile uint32_t DCISW;
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volatile uint32_t DCCMVAU;
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volatile uint32_t DCCMVAC;
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volatile uint32_t DCCSW;
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volatile uint32_t DCCIMVAC;
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volatile uint32_t DCCISW;
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uint32_t RESERVED7[6U];
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volatile uint32_t ITCMCR;
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volatile uint32_t DTCMCR;
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volatile uint32_t AHBPCR;
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volatile uint32_t CACR;
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volatile uint32_t AHBSCR;
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uint32_t RESERVED8[1U];
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volatile uint32_t ABFSR;
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} STM32_SCB_Type;
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#define RCC_BASE 0x40023800UL
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#define SysTick_BASE 0xE000E010UL
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#define NVIC_BASE 0xE000E100UL
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#define SCB_BASE 0xE000ED00UL
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define READ_REG(REG) ((REG))
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#define STM_32_RCC ((STM32::STM32_RCC_TypeDef *) RCC_BASE)
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#define STM_32_SysTick ((STM32::STM32_SysTick_Type *) SysTick_BASE)
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#define STM_32_NVIC ((STM32::STM32_NVIC_Type *) NVIC_BASE)
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#define STM_32_SCB ((STM32_SCB_Type *) SCB_BASE)
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extern void rcc_deinit();
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extern void hal_deinit();
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extern void systick_deinit();
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}
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