diff --git a/ion/src/device/boot/isr.c b/ion/src/device/boot/isr.c
index 53495ed27..09c386934 100644
--- a/ion/src/device/boot/isr.c
+++ b/ion/src/device/boot/isr.c
@@ -10,7 +10,7 @@ typedef void(*ISR)(void);
  * properly handled by the C compiler that will generate proper addresses when
  * using function pointers. */
 
-#define INITIALISATION_VECTOR_SIZE 0x6B
+#define INITIALISATION_VECTOR_SIZE 0x71
 
 ISR InitialisationVector[INITIALISATION_VECTOR_SIZE]
   __attribute__((section(".isr_vector_table")))
@@ -45,5 +45,84 @@ ISR InitialisationVector[INITIALISATION_VECTOR_SIZE]
   0, // DMA1Stream3 service routine
   0, // DMA1Stream4 service routine
   0, // DMA1Stream5 service routine
-  0  // DMA1Stream6 service routine
+  0, // DMA1Stream6 service routine
+  0, // ADC1 global interrupt
+  0, // CAN1 TX interrupt
+  0, // CAN1 RX0 interrupt
+  0, // CAN1 RX1 interrupt
+  0, // CAN1 SCE interrupt
+  0, // EXTI Line[9:5] interrupts
+  0, // TIM1 Break interrupt and TIM9 global interrupt
+  0, // TIM1 update interrupt and TIM10 global interrupt
+  0, // TIM1 Trigger & Commutation interrupts and TIM11 global interrupt
+  0, // TIM1 Capture Compare interrupt
+  0, // TIM2 global interrupt
+  0, // TIM3 global interrupt
+  0, // TIM4 global interrupt
+  0, // I2C1 global event interrupt
+  0, // I2C1 global error interrupt
+  0, // I2C2 global event interrupt
+  0, // I2C2 global error interrupt
+  0, // SPI1 global interrupt
+  0, // SPI2 global interrupt
+  0, // USART1 global interrupt
+  0, // USART2 global interrupt
+  0, // USART3 global interrupt
+  0, // EXTI Line[15:10] interrupts
+  0, // EXTI Line 17 interrupt RTC Alarms (A and B) through EXTI line interrupt
+  0, // EXTI Line 18 interrupt / USB On-The-Go FS Wakeup through EXTI line interrupt
+  0, // TIM8 Break interrupt TIM12 global interrupt
+  0, // TIM8 Update interrupt TIM13 global interrupt
+  0, // TIM8 Trigger & Commutation interrupt TIM14 global interrupt
+  0, // TIM8 Cap/Com interrupt
+  0, // DMA1 global interrupt Channel 7
+  0, // FSMC global interrupt
+  0, // SDIO global interrupt
+  0, // TIM5 global interrupt
+  0, // SPI3 global interrupt
+  0, // ?
+  0, // ?
+  0, // TIM6 global interrupt
+  0, // TIM7 global interrupt
+  0, // DMA2 Stream0 global interrupt
+  0, // DMA2 Stream1 global interrupt
+  0, // DMA2 Stream2 global interrupt
+  0, // DMA2 Stream3 global interrupt
+  0, // DMA2 Stream4 global interrupt
+  0, // SD filter0 global interrupt
+  0, // SD filter1 global interrupt
+  0, // CAN2 TX interrupt
+  0, // BXCAN2 RX0 interrupt
+  0, // BXCAN2 RX1 interrupt
+  0, // CAN2 SCE interrupt
+  0, // USB On The Go FS global interrupt
+  0, // DMA2 Stream5 global interrupts
+  0, // DMA2 Stream6 global interrupt
+  0, // DMA2 Stream7 global interrupt
+  0, // USART6 global interrupt
+  0, // I2C3 event interrupt
+  0, // I2C3 error interrupt
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // RNG global interrupt
+  0, // FPU global interrupt
+  0, // ?
+  0, // ?
+  0, // SPI4 global interrupt
+  0, // SPI5 global interrupt
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // ?
+  0, // Quad-SPI global interrupt
+  0, // ?
+  0, // ?
+  0, // I2CFMP1 event interrupt
+  0  // I2CFMP1 error interrupt
 };
diff --git a/ion/src/device/device.cpp b/ion/src/device/device.cpp
index 23daf95f9..1786289c1 100644
--- a/ion/src/device/device.cpp
+++ b/ion/src/device/device.cpp
@@ -105,6 +105,11 @@ void initFPU() {
 void init() {
   initClocks();
 
+  // Ensure right location of interrupt vectors
+  // The bootloader leaves its own after flashing
+  SYSCFG.MEMRMP()->setMEM_MODE(SYSCFG::MEMRMP::MemMode::MainFlashmemory);
+  CM4.VTOR()->setVTOR((void*) 0);
+
   // Put all inputs as Analog Input, No pull-up nor pull-down
   // Except for the SWD port (PB3, PA13, PA14)
   GPIOA.MODER()->set(0xEBFFFFFF);
diff --git a/ion/src/device/regs/cm4.h b/ion/src/device/regs/cm4.h
index 2c9858013..8713566e7 100644
--- a/ion/src/device/regs/cm4.h
+++ b/ion/src/device/regs/cm4.h
@@ -5,6 +5,13 @@
 
 class CM4 {
 public:
+  // Vector table offset register
+  // http://www.st.com/content/ccc/resource/technical/document/programming_manual/6c/3a/cb/e7/e4/ea/44/9b/DM00046982.pdf/files/DM00046982.pdf/jcr:content/translations/en.DM00046982.pdf
+  class VTOR : Register32 {
+  public:
+    void setVTOR(void *address) volatile { set((uint32_t)address); }
+  };
+
   // Coprocessor Access Control Register
   // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BEHBJHIG.html
   class CPACR : public Register32 {
@@ -34,6 +41,7 @@ public:
   };
 
   constexpr CM4() {};
+  REGS_REGISTER_AT(VTOR, 0x08);
   REGS_REGISTER_AT(AIRCR, 0x0C);
   REGS_REGISTER_AT(SCR, 0x10);
   REGS_REGISTER_AT(CPACR, 0x88);
diff --git a/ion/src/device/regs/dma.h b/ion/src/device/regs/dma.h
index 2127a0167..75190d271 100644
--- a/ion/src/device/regs/dma.h
+++ b/ion/src/device/regs/dma.h
@@ -32,7 +32,7 @@ public:
     REGS_FIELD(PSIZE, DataSize, 12, 11);
     REGS_BOOL_FIELD(MINC, 10);
     REGS_BOOL_FIELD(PINC, 9);
-    //REGS_BOOL_FIELD(CIRC, 8);
+    REGS_BOOL_FIELD(CIRC, 8);
     REGS_FIELD(DIR, Direction, 7, 6);
     REGS_BOOL_FIELD(EN, 0);
   };
diff --git a/ion/src/device/regs/exti.h b/ion/src/device/regs/exti.h
index dd4b3568b..46ee8550b 100644
--- a/ion/src/device/regs/exti.h
+++ b/ion/src/device/regs/exti.h
@@ -11,16 +11,18 @@ public:
     void set(int index, bool state) volatile { setBitRange(index, index, state); }
   };
 
-  //class IMR : public MaskRegister { };
+  class IMR : public MaskRegister { };
   class EMR : public MaskRegister { };
   class RTSR : public MaskRegister { };
   class FTSR : public MaskRegister { };
+  class PR : public MaskRegister { };
 
   constexpr EXTI() {};
-  //REGS_REGISTER_AT(IMR, 0x00);
+  REGS_REGISTER_AT(IMR, 0x00);
   REGS_REGISTER_AT(EMR, 0x04);
   REGS_REGISTER_AT(RTSR, 0x08);
   REGS_REGISTER_AT(FTSR, 0x0C);
+  REGS_REGISTER_AT(PR, 0x14);
 private:
   constexpr uint32_t Base() const {
     return 0x40013C00;
diff --git a/ion/src/device/regs/nvic.h b/ion/src/device/regs/nvic.h
new file mode 100644
index 000000000..dd72ea0d5
--- /dev/null
+++ b/ion/src/device/regs/nvic.h
@@ -0,0 +1,37 @@
+#ifndef REGS_NVIC_H
+#define REGS_NVIC_H
+
+#include "register.h"
+
+// http://www.st.com/content/ccc/resource/technical/document/programming_manual/6c/3a/cb/e7/e4/ea/44/9b/DM00046982.pdf/files/DM00046982.pdf/jcr:content/translations/en.DM00046982.pdf
+class NVIC {
+public:
+  class MaskRegister : Register32 {
+  public:
+    bool get(int index) { return (bool)getBitRange(index, index); }
+    void set(int index, bool state) volatile { setBitRange(index, index, state); }
+  };
+
+  class NVIC_ISER0 : public MaskRegister { };
+  class NVIC_ISER1 : public MaskRegister { };
+  class NVIC_ISER2 : public MaskRegister { };
+  class NVIC_ICER0 : public MaskRegister { };
+  class NVIC_ICER1 : public MaskRegister { };
+  class NVIC_ICER2 : public MaskRegister { };
+
+  constexpr NVIC() {};
+  REGS_REGISTER_AT(NVIC_ISER0, 0x00);
+  REGS_REGISTER_AT(NVIC_ISER1, 0x04);
+  REGS_REGISTER_AT(NVIC_ISER2, 0x08);
+  REGS_REGISTER_AT(NVIC_ICER0, 0x80);
+  REGS_REGISTER_AT(NVIC_ICER1, 0x84);
+  REGS_REGISTER_AT(NVIC_ICER2, 0x88);
+private:
+  constexpr uint32_t Base() const {
+    return 0xE000E100;
+  }
+};
+
+constexpr NVIC NVIC;
+
+#endif
diff --git a/ion/src/device/regs/rcc.h b/ion/src/device/regs/rcc.h
index 64ec87472..b76a9f31f 100644
--- a/ion/src/device/regs/rcc.h
+++ b/ion/src/device/regs/rcc.h
@@ -87,6 +87,7 @@ public:
     REGS_BOOL_FIELD(USART1EN, 4);
     REGS_BOOL_FIELD(ADC1EN, 8);
     REGS_BOOL_FIELD(SDIOEN, 11);
+    REGS_BOOL_FIELD(SPI1EN, 12);
     REGS_BOOL_FIELD(SYSCFGEN, 14);
   };
 
diff --git a/ion/src/device/regs/regs.h b/ion/src/device/regs/regs.h
index 175862830..a80db5232 100644
--- a/ion/src/device/regs/regs.h
+++ b/ion/src/device/regs/regs.h
@@ -10,6 +10,7 @@
 #include "fsmc.h"
 #include "gpio.h"
 #include "itm.h"
+#include "nvic.h"
 #include "pwr.h"
 #include "rcc.h"
 #include "rng.h"
diff --git a/ion/src/device/regs/spi.h b/ion/src/device/regs/spi.h
index a817a1371..abe050b97 100644
--- a/ion/src/device/regs/spi.h
+++ b/ion/src/device/regs/spi.h
@@ -7,10 +7,17 @@ class SPI {
 public:
   class CR1 : Register16 {
   public:
+    REGS_BOOL_FIELD(MSTR, 2);
     REGS_BOOL_FIELD(SPE, 6);
     REGS_BOOL_FIELD(LSBFIRST, 7);
     REGS_BOOL_FIELD(SSI, 8);
     REGS_BOOL_FIELD(SSM, 9);
+    REGS_BOOL_FIELD(RXONLY, 10);
+    REGS_BOOL_FIELD(DFF, 11);
+  };
+  class CR2 : Register16 {
+  public:
+    REGS_BOOL_FIELD(RXDMAEN, 0);
   };
   class SR : Register16 {
   public:
@@ -23,6 +30,7 @@ public:
   constexpr SPI(int i) : m_index(i) {}
   constexpr operator int() const { return m_index; }
   REGS_REGISTER_AT(CR1, 0x00);
+  REGS_REGISTER_AT(CR2, 0x04);
   REGS_REGISTER_AT(SR, 0x08);
   REGS_REGISTER_AT(DR, 0x0C);
 private:
@@ -32,4 +40,6 @@ private:
   int m_index;
 };
 
+constexpr SPI SPI1(1);
+
 #endif
diff --git a/ion/src/device/regs/syscfg.h b/ion/src/device/regs/syscfg.h
index d759363e0..d1b1afa29 100644
--- a/ion/src/device/regs/syscfg.h
+++ b/ion/src/device/regs/syscfg.h
@@ -7,16 +7,31 @@
 
 class SYSCFG {
 public:
+  class MEMRMP : Register32 {
+  public:
+    enum class MemMode {
+      MainFlashmemory = 0,
+      SystemFlashmemory = 1,
+      EmbeddedSRAM = 3
+    };
+    REGS_FIELD(MEM_MODE, MemMode, 1, 0);
+  };
   class EXTICR1 : Register32 {
   public:
     void setEXTI(int index, GPIO gpio) volatile { setBitRange(4*index+3, 4*index, (uint32_t)gpio); }
   };
+  class EXTICR2 : Register32 {
+  public:
+    void setEXTI(int index, GPIO gpio) volatile { setBitRange(4*(index-4)+3, 4*(index-4), (uint32_t)gpio); }
+  };
   class EXTICR3 : Register32 {
   public:
     void setEXTI(int index, GPIO gpio) volatile { setBitRange(4*(index-8)+3, 4*(index-8), (uint32_t)gpio); }
   };
   constexpr SYSCFG() {};
+  REGS_REGISTER_AT(MEMRMP, 0x00);
   REGS_REGISTER_AT(EXTICR1, 0x08);
+  REGS_REGISTER_AT(EXTICR2, 0x0C);
   REGS_REGISTER_AT(EXTICR3, 0x10);
 private:
   constexpr uint32_t Base() const {