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https://github.com/UpsilonNumworks/Upsilon.git
synced 2026-01-18 16:27:34 +01:00
[ion/external_flash] Make the AT25SF641B work
Main changes are: - No QPI but QuadSPI - Use 32 command instead of 33 - Better programming of the instruction/address/data modes, according to the 641B spec - Use sOperatingMode instead of DefaultOperatingMode TODO: - Support both QPI and QuadSPI, for both flashs - There is still confusion between sOperatingMode and DefaultOperatingMode -> DefaultOperatingMode should not really be used -> Read and write commands assume quad operation
This commit is contained in:
Léa Saviot
@@ -55,29 +55,24 @@ using namespace Regs;
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* the operation is stalled until enough data is present or until the transfer is complete, whichever happens first. */
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enum class Command : uint8_t {
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ReadStatusRegister1 = 0x05,
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ReadStatusRegister2 = 0x35,
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WriteStatusRegister = 0x01,
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WriteStatusRegister2 = 0x31,
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WriteEnable = 0x06,
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ReadData = 0x03,
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FastRead = 0x0B,
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FastReadQuadIO = 0xEB,
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// Program previously erased memory areas as being "0"
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PageProgram = 0x02,
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QuadPageProgram = 0x33,
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EnableQPI = 0x38,
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EnableReset = 0x66,
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Reset = 0x99,
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// Erase the whole chip or a 64-Kbyte block as being "1"
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ChipErase = 0xC7,
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Erase4KbyteBlock = 0x20,
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Erase32KbyteBlock = 0x52,
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Erase64KbyteBlock = 0xD8,
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SetReadParameters = 0xC0,
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DeepPowerDown = 0xB9,
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ReleaseDeepPowerDown = 0xAB,
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ReadJEDECID = 0x9F
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WriteStatusRegister = 0x01,
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PageProgram = 0x02, // Program previously erased memory areas as being "0"
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ReadData = 0x03,
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ReadStatusRegister1 = 0x05,
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WriteEnable = 0x06,
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Erase4KbyteBlock = 0x20,
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WriteStatusRegister2 = 0x31,
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QuadPageProgram = 0x32, // WARNING! Changed from 33
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ReadStatusRegister2 = 0x35,
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Erase32KbyteBlock = 0x52,
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EnableReset = 0x66,
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Reset = 0x99,
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ReadJEDECID = 0x9F,
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ReleaseDeepPowerDown = 0xAB,
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DeepPowerDown = 0xB9,
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ChipErase = 0xC7, // Erase the whole chip or a 64-Kbyte block as being "1"
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Erase64KbyteBlock = 0xD8,
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FastReadQuadIO = 0xEB
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};
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static constexpr uint8_t NumberOfAddressBitsIn64KbyteBlock = 16;
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@@ -98,53 +93,78 @@ public:
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};
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};
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class OperatingModes {
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public:
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constexpr OperatingModes(QUADSPI::CCR::OperatingMode instruction, QUADSPI::CCR::OperatingMode address, QUADSPI::CCR::OperatingMode data) :
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m_instructionOperatingMode(instruction),
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m_addressOperatingMode(address),
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m_dataOperatingMode(data)
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{}
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QUADSPI::CCR::OperatingMode instructionOperatingMode() const { return m_instructionOperatingMode; }
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QUADSPI::CCR::OperatingMode addressOperatingMode() const { return m_addressOperatingMode; }
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QUADSPI::CCR::OperatingMode dataOperatingMode() const { return m_dataOperatingMode; }
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private:
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QUADSPI::CCR::OperatingMode m_instructionOperatingMode;
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QUADSPI::CCR::OperatingMode m_addressOperatingMode;
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QUADSPI::CCR::OperatingMode m_dataOperatingMode;
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};
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/* TODO LEA 641B has quadSPI-1-*-4, not QPI-4-4-4*/
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static constexpr OperatingModes sOperatingModesNoData(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::NoData, QUADSPI::CCR::OperatingMode::NoData);
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static constexpr OperatingModes sOperatingModesSingle(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single);
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static constexpr OperatingModes sOperatingModes114(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Quad);
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static constexpr OperatingModes sOperatingModes144(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Quad, QUADSPI::CCR::OperatingMode::Quad);
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static constexpr OperatingModes sOperatingModes101(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::NoData, QUADSPI::CCR::OperatingMode::Single);
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static constexpr OperatingModes sOperatingModes110(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::NoData);
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static constexpr OperatingModes sOperatingModes111(QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single, QUADSPI::CCR::OperatingMode::Single);
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static constexpr QUADSPI::CCR::OperatingMode DefaultOperatingMode = QUADSPI::CCR::OperatingMode::Quad;
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static QUADSPI::CCR::OperatingMode sOperatingMode = QUADSPI::CCR::OperatingMode::Single;
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static constexpr int ClockFrequencyDivisor = 2;
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static constexpr bool ajustNumberOfDummyCycles = Clocks::Config::AHBFrequency > (80 * ClockFrequencyDivisor);
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static constexpr int FastReadDummyCycles = (DefaultOperatingMode == QUADSPI::CCR::OperatingMode::Quad && ajustNumberOfDummyCycles) ? 4 : 2;
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static constexpr int QuadIOFastReadDummyCycles = 4;
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static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADSPI::CCR::OperatingMode operatingMode, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength);
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static inline void send_command(Command c, QUADSPI::CCR::OperatingMode operatingMode = DefaultOperatingMode) {
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static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, OperatingModes operatingModes, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength);
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static inline void send_command(Command c) {
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectWrite,
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operatingMode,
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sOperatingModesNoData,
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c,
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
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0, 0,
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0,
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nullptr, 0
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);
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nullptr, 0);
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}
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static inline void send_write_command(Command c, uint8_t * address, const uint8_t * data, size_t dataLength, QUADSPI::CCR::OperatingMode operatingMode = DefaultOperatingMode) {
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static inline void send_write_command(Command c, uint8_t * address, const uint8_t * data, size_t dataLength, OperatingModes operatingModes) {
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectWrite,
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operatingMode,
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operatingModes,
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c,
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address,
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0, 0,
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0,
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const_cast<uint8_t *>(data), dataLength
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);
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const_cast<uint8_t *>(data), dataLength);
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}
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static inline void send_read_command(Command c, uint8_t * address, uint8_t * data, size_t dataLength, QUADSPI::CCR::OperatingMode operatingMode = DefaultOperatingMode) {
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static inline void send_read_command(Command c, uint8_t * address, uint8_t * data, size_t dataLength) {
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectRead,
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operatingMode,
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sOperatingModes101,
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c,
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address,
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0, 0,
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0,
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data, dataLength
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);
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data, dataLength);
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}
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static inline void wait(QUADSPI::CCR::OperatingMode operatingMode = DefaultOperatingMode) {
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static inline void wait() {
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ExternalFlashStatusRegister::StatusRegister1 statusRegister1(0);
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do {
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send_read_command(Command::ReadStatusRegister1, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&statusRegister1), sizeof(statusRegister1), operatingMode);
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send_read_command(Command::ReadStatusRegister1, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&statusRegister1), sizeof(statusRegister1));
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} while (statusRegister1.getBUSY());
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}
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@@ -160,11 +180,11 @@ static void set_as_memory_mapped() {
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* (Flash memories tend to consume more when nCS is held low.) */
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send_command_full(
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QUADSPI::CCR::FunctionalMode::MemoryMapped,
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DefaultOperatingMode,
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sOperatingModes144,
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Command::FastReadQuadIO,
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
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0xA0, 1,
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FastReadDummyCycles,
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QuadIOFastReadDummyCycles,
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nullptr, 0
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);
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}
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@@ -174,16 +194,16 @@ static void unset_memory_mapped_mode() {
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uint8_t dummyData;
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectRead,
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DefaultOperatingMode,
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sOperatingModes144,
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Command::FastReadQuadIO,
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0,
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~(0xA0), 1,
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FastReadDummyCycles,
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QuadIOFastReadDummyCycles,
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&dummyData, 1
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);
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}
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static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADSPI::CCR::OperatingMode operatingMode, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength) {
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static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, OperatingModes operatingModes, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength) {
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/* According to ST's Errata Sheet ES0360, "Wrong data can be read in
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* memory-mapped after an indirect mode operation". This is the workaround. */
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if (functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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@@ -214,22 +234,22 @@ static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADS
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class QUADSPI::CCR ccr(0);
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ccr.setFMODE(functionalMode);
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if (data != nullptr || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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ccr.setDMODE(operatingMode);
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ccr.setDMODE(operatingModes.dataOperatingMode());
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}
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if (functionalMode != QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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QUADSPI.DLR()->set((dataLength > 0) ? dataLength-1 : 0);
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}
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ccr.setDCYC(dummyCycles);
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if (numberOfAltBytes > 0) {
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ccr.setABMODE(operatingMode);
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ccr.setABMODE(operatingModes.addressOperatingMode()); // Seems to always be the same as address mode
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ccr.setABSIZE(static_cast<QUADSPI::CCR::Size>(numberOfAltBytes - 1));
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QUADSPI.ABR()->set(altBytes);
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}
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if (address != reinterpret_cast<uint8_t *>(FlashAddressSpaceSize) || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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ccr.setADMODE(operatingMode);
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ccr.setADMODE(operatingModes.addressOperatingMode());
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ccr.setADSIZE(QUADSPI::CCR::Size::ThreeBytes);
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}
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ccr.setIMODE(operatingMode);
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ccr.setIMODE(operatingModes.instructionOperatingMode());
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ccr.setINSTRUCTION(static_cast<uint8_t>(c));
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if (functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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ccr.setSIOO(true);
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@@ -288,36 +308,20 @@ static void initQSPI() {
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QUADSPI.CR()->set(cr);
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}
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static QUADSPI::CCR::OperatingMode sOperatingMode = QUADSPI::CCR::OperatingMode::Single;
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static void initChip() {
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// Release sleep deep
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send_command(Command::ReleaseDeepPowerDown, sOperatingMode);
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send_command(Command::ReleaseDeepPowerDown);
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Timing::usleep(3);
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/* The chip initially expects commands in SPI mode. We need to use SPI to tell
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* it to switch to QPI. */
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* it to switch to QuadSPI/QPI. */
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if (sOperatingMode == QUADSPI::CCR::OperatingMode::Single && DefaultOperatingMode == QUADSPI::CCR::OperatingMode::Quad) {
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send_command(Command::WriteEnable, QUADSPI::CCR::OperatingMode::Single);
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send_command(Command::WriteEnable);
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ExternalFlashStatusRegister::StatusRegister2 statusRegister2(0);
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statusRegister2.setQE(true);
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wait(QUADSPI::CCR::OperatingMode::Single);
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send_write_command(Command::WriteStatusRegister2, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&statusRegister2), sizeof(statusRegister2), QUADSPI::CCR::OperatingMode::Single);
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wait(QUADSPI::CCR::OperatingMode::Single);
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send_command(Command::EnableQPI, QUADSPI::CCR::OperatingMode::Single);
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wait();
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if (ajustNumberOfDummyCycles) {
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class ReadParameters : Register8 {
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public:
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/* Parameters sent along with SetReadParameters instruction in order
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* to configure the number of dummy cycles for the QPI Read instructions. */
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using Register8::Register8;
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REGS_BOOL_FIELD_W(P5, 5);
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};
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ReadParameters readParameters(0);
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readParameters.setP5(true);
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send_write_command(Command::SetReadParameters, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&readParameters), sizeof(readParameters));
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}
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send_write_command(Command::WriteStatusRegister2, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(&statusRegister2), sizeof(statusRegister2), sOperatingModes101);
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wait();
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sOperatingMode = QUADSPI::CCR::OperatingMode::Quad;
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}
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set_as_memory_mapped();
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@@ -346,10 +350,10 @@ static void shutdownChip() {
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send_command(Command::EnableReset);
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send_command(Command::Reset);
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sOperatingMode = QUADSPI::CCR::OperatingMode::Single;
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Ion::Timing::usleep(30);
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Timing::usleep(30);
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// Sleep deep
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send_command(Command::DeepPowerDown, sOperatingMode);
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send_command(Command::DeepPowerDown);
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Timing::usleep(3);
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}
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@@ -402,7 +406,7 @@ void unlockFlash() {
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statusRegister2.setQE(currentStatusRegister2.getQE());
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uint8_t registers[] = {statusRegister1.get(), statusRegister2.get()};
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send_write_command(Command::WriteStatusRegister, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(registers), sizeof(registers));
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send_write_command(Command::WriteStatusRegister, reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), reinterpret_cast<uint8_t *>(registers), sizeof(registers), sOperatingModes101);
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wait();
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}
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@@ -428,18 +432,18 @@ void __attribute__((noinline)) EraseSector(int i) {
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/* WARNING: this code assumes that the flash sectors are of increasing size:
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* first all 4K sectors, then all 32K sectors, and finally all 64K sectors. */
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if (i < Config::NumberOf4KSectors) {
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send_write_command(Command::Erase4KbyteBlock, reinterpret_cast<uint8_t *>(i << NumberOfAddressBitsIn4KbyteBlock), nullptr, 0);
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send_write_command(Command::Erase4KbyteBlock, reinterpret_cast<uint8_t *>(i << NumberOfAddressBitsIn4KbyteBlock), nullptr, 0, sOperatingModes110);
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} else if (i < Config::NumberOf4KSectors + Config::NumberOf32KSectors) {
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/* If the sector is the number Config::NumberOf4KSectors, we want to write
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* at the address 1 << NumberOfAddressBitsIn32KbyteBlock, hence the formula
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* (i - Config::NumberOf4KSectors + 1). */
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send_write_command(Command::Erase32KbyteBlock, reinterpret_cast<uint8_t *>((i - Config::NumberOf4KSectors + 1) << NumberOfAddressBitsIn32KbyteBlock), nullptr, 0);
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send_write_command(Command::Erase32KbyteBlock, reinterpret_cast<uint8_t *>((i - Config::NumberOf4KSectors + 1) << NumberOfAddressBitsIn32KbyteBlock), nullptr, 0, sOperatingModes110);
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} else {
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/* If the sector is the number
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* Config::NumberOf4KSectors - Config::NumberOf32KSectors, we want to write
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* at the address 1 << NumberOfAddressBitsIn32KbyteBlock, hence the formula
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* (i - Config::NumberOf4KSectors - Config::NumberOf32KSectors + 1). */
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send_write_command(Command::Erase64KbyteBlock, reinterpret_cast<uint8_t *>((i - Config::NumberOf4KSectors - Config::NumberOf32KSectors + 1) << NumberOfAddressBitsIn64KbyteBlock), nullptr, 0);
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send_write_command(Command::Erase64KbyteBlock, reinterpret_cast<uint8_t *>((i - Config::NumberOf4KSectors - Config::NumberOf32KSectors + 1) << NumberOfAddressBitsIn64KbyteBlock), nullptr, 0, sOperatingModes110);
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}
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wait();
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set_as_memory_mapped();
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@@ -455,7 +459,6 @@ void __attribute__((noinline)) WriteMemory(uint8_t * destination, const uint8_t
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* However, when the end of a page is reached, the addressing wraps to the beginning.
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* Hence a Page Program instruction must be issued for each page. */
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static constexpr size_t PageSize = 256;
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constexpr Command pageProgram = (DefaultOperatingMode == QUADSPI::CCR::OperatingMode::Single) ? Command::PageProgram : Command::QuadPageProgram;
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uint8_t offset = reinterpret_cast<uint32_t>(destination) & (PageSize - 1);
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size_t lengthThatFitsInPage = PageSize - offset;
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while (length > 0) {
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@@ -464,7 +467,12 @@ void __attribute__((noinline)) WriteMemory(uint8_t * destination, const uint8_t
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}
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send_command(Command::WriteEnable);
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wait();
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send_write_command(pageProgram, destination, source, lengthThatFitsInPage);
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if (DefaultOperatingMode == QUADSPI::CCR::OperatingMode::Single) {
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send_write_command(Command::PageProgram, destination, source, lengthThatFitsInPage, sOperatingModes111);
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} else {
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assert(DefaultOperatingMode == QUADSPI::CCR::OperatingMode::Quad);
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send_write_command(Command::QuadPageProgram, destination, source, lengthThatFitsInPage, sOperatingModes114);
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}
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length -= lengthThatFitsInPage;
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destination += lengthThatFitsInPage;
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source += lengthThatFitsInPage;
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