diff --git a/boot/device/crt0.c b/boot/device/crt0.c
index e79cb9f20..440262eb2 100644
--- a/boot/device/crt0.c
+++ b/boot/device/crt0.c
@@ -8,6 +8,13 @@ extern char _data_section_end_ram;
 extern char _bss_section_start_ram;
 extern char _bss_section_end_ram;
 
+#define CPACR (*(volatile uint32_t *)(0xE000ED88))
+
+void enable_fpu() {
+  // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BABDBFBJ.html
+  CPACR |= (0xF << 20); // Set the bits 20-23 to enable CP10 and CP11 coprocessors
+}
+
 void abort() {
   // TODO: #ifdef NDEBUG, maybe trigger a reset?
   while (1) {
@@ -31,6 +38,8 @@ void _start(void) {
   size_t bssSectionLength = (&_bss_section_end_ram - &_bss_section_start_ram);
   memset(&_bss_section_start_ram, 0, bssSectionLength);
 
+  enable_fpu();
+
   boot();
 
   abort();