diff --git a/ion/src/device/regs/rcc.h b/ion/src/device/regs/rcc.h
index 805b91341..234c5af93 100644
--- a/ion/src/device/regs/rcc.h
+++ b/ion/src/device/regs/rcc.h
@@ -74,6 +74,7 @@ public:
   class APB1ENR : Register32 {
   public:
     REGS_BOOL_FIELD(TIM3EN, 1);
+    REGS_BOOL_FIELD(SPI3EN, 15);
     REGS_BOOL_FIELD(PWREN, 28);
   };
 
diff --git a/ion/src/device/regs/regs.h b/ion/src/device/regs/regs.h
index 9375e1ed7..5a337cb39 100644
--- a/ion/src/device/regs/regs.h
+++ b/ion/src/device/regs/regs.h
@@ -13,6 +13,7 @@
 #include "rcc.h"
 #include "rng.h"
 #include "sdio.h"
+#include "spi.h"
 #include "syscfg.h"
 #include "tim.h"
 
diff --git a/ion/src/device/regs/spi.h b/ion/src/device/regs/spi.h
new file mode 100644
index 000000000..a817a1371
--- /dev/null
+++ b/ion/src/device/regs/spi.h
@@ -0,0 +1,35 @@
+#ifndef REGS_SPI_H
+#define REGS_SPI_H
+
+#include "register.h"
+
+class SPI {
+public:
+  class CR1 : Register16 {
+  public:
+    REGS_BOOL_FIELD(SPE, 6);
+    REGS_BOOL_FIELD(LSBFIRST, 7);
+    REGS_BOOL_FIELD(SSI, 8);
+    REGS_BOOL_FIELD(SSM, 9);
+  };
+  class SR : Register16 {
+  public:
+    REGS_BOOL_FIELD(RXNE, 0);
+    REGS_BOOL_FIELD(TXE, 1);
+  };
+  class DR : public Register16 {
+  };
+
+  constexpr SPI(int i) : m_index(i) {}
+  constexpr operator int() const { return m_index; }
+  REGS_REGISTER_AT(CR1, 0x00);
+  REGS_REGISTER_AT(SR, 0x08);
+  REGS_REGISTER_AT(DR, 0x0C);
+private:
+  constexpr uint32_t Base() const {
+    return ((uint32_t []){0x40013000, 0x40003800, 0x40003C00})[m_index-1];
+  };
+  int m_index;
+};
+
+#endif