mirror of
https://github.com/UpsilonNumworks/Upsilon.git
synced 2026-01-18 16:27:34 +01:00
339 lines
10 KiB
C++
339 lines
10 KiB
C++
#include <drivers/board.h>
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#include <drivers/cache.h>
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#include <drivers/config/clocks.h>
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#include <regs/regs.h>
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#include <ion.h>
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extern void * InitialisationVector;
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// Public Ion methods
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const char * Ion::fccId() {
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return "2ALWP-N0101";
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}
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// Private Ion::Device methods
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namespace Ion {
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namespace Device {
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namespace Board {
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using namespace Regs;
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void initMPU() {
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// 1. Disable the MPU
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// 1.1 Memory barrier
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Cache::dmb();
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// 1.2 Disable fault exceptions
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CORTEX.SHCRS()->setMEMFAULTENA(false);
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// 1.3 Disable the MPU and clear the control register
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MPU.CTRL()->setENABLE(false);
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// 2. MPU settings
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// 2.1 Configure a MPU region for the FMC memory area
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// This is needed for interfacing with the LCD
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MPU.RNR()->setREGION(0x00);
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MPU.RBAR()->setADDR(0x60000000);
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MPU.RASR()->setSIZE(MPU::RASR::RegionSize::_32MB);
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MPU.RASR()->setXN(true);
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MPU.RASR()->setAP(MPU::RASR::AccessPermission::RW);
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MPU.RASR()->setTEX(2);
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MPU.RASR()->setS(0);
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MPU.RASR()->setC(0);
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MPU.RASR()->setB(0);
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MPU.RASR()->setENABLE(true);
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// 2.2 Configure MPU regions for the QUADSPI peripheral
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/* L1 Cache can issue speculative reads to any memory address. But, when the
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* Quad-SPI is in memory-mapped mode, if an access is made to an address
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* outside of the range defined by FSIZE but still within the 256Mbytes range,
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* then an AHB error is given (AN4760). To prevent this to happen, we
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* configure the MPU to define the whole Quad-SPI addressable space as
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* strongly ordered, non-executable and not accessible. Plus, we define the
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* Quad-SPI region corresponding to the Expternal Chip as executable and
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* fully accessible (AN4861). */
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MPU.RNR()->setREGION(0x01);
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MPU.RBAR()->setADDR(0x90000000);
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MPU.RASR()->setSIZE(MPU::RASR::RegionSize::_256MB);
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MPU.RASR()->setAP(MPU::RASR::AccessPermission::NoAccess);
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MPU.RASR()->setXN(true);
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MPU.RASR()->setTEX(0);
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MPU.RASR()->setS(0);
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MPU.RASR()->setC(0);
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MPU.RASR()->setB(0);
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MPU.RASR()->setENABLE(true);
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MPU.RNR()->setREGION(0x02);
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MPU.RBAR()->setADDR(0x90000000);
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MPU.RASR()->setSIZE(MPU::RASR::RegionSize::_8MB);
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MPU.RASR()->setAP(MPU::RASR::AccessPermission::RW);
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MPU.RASR()->setXN(false);
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MPU.RASR()->setTEX(0);
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MPU.RASR()->setS(0);
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MPU.RASR()->setC(1);
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MPU.RASR()->setB(0);
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MPU.RASR()->setENABLE(true);
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// 2.3 Enable MPU
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MPU.CTRL()->setPRIVDEFENA(true);
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MPU.CTRL()->setENABLE(true);
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// 3. Data/instruction synchronisation barriers to ensure that the new MPU configuration is used by subsequent instructions.
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Cache::dsb();
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Cache::isb();
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}
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void init() {
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initFPU();
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initMPU();
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initClocks();
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// The bootloader leaves its own after flashing
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//SYSCFG.MEMRMP()->setMEM_MODE(SYSCFG::MEMRMP::MemMode::MainFlashmemory);
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// Ensure right location of interrupt vectors
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CORTEX.VTOR()->setVTOR((void*)&InitialisationVector);
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// Put all inputs as Analog Input, No pull-up nor pull-down
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// Except for the SWD port (PB3, PA13, PA14)
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GPIOA.MODER()->set(0xEBFFFFFF);
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GPIOA.PUPDR()->set(0x24000000);
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GPIOB.MODER()->set(0xFFFFFFBF);
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GPIOB.PUPDR()->set(0x00000000);
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for (int g=2; g<5; g++) {
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GPIO(g).MODER()->set(0xFFFFFFFF); // All to "Analog"
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GPIO(g).PUPDR()->set(0x00000000); // All to "None"
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}
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initPeripherals();
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// Initiate L1 cache after initiating the external flash
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Cache::enable();
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// TODO if EPSILON_DEVICE_BENCH, run bench? See n0100
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}
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void initClocks() {
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/* System clock
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* Configure the CPU at 192 MHz and USB at 48 MHz. */
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/* After reset, the device is using the high-speed internal oscillator (HSI)
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* as a clock source, which runs at a fixed 16 MHz frequency. The HSI is not
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* accurate enough for reliable USB operation, so we need to use the external
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* high-speed oscillator (HSE). */
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// Enable the HSI and wait for it to be ready
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RCC.CR()->setHSION(true);
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while(!RCC.CR()->getHSIRDY()) {
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}
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// Enable the HSE and wait for it to be ready
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RCC.CR()->setHSEON(true);
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while(!RCC.CR()->getHSERDY()) {
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}
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// Enable PWR peripheral clock
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RCC.APB1ENR()->setPWREN(true);
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/* Given the crystal used on our device, the HSE will oscillate at 8 MHz. By
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* piping it through a phase-locked loop (PLL) we can derive other frequencies
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* for use in different parts of the system. */
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// Configure the PLL ratios and use HSE as a PLL input
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RCC.PLLCFGR()->setPLLM(Clocks::Config::PLL_M);
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RCC.PLLCFGR()->setPLLN(Clocks::Config::PLL_N);
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RCC.PLLCFGR()->setPLLQ(Clocks::Config::PLL_Q);
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RCC.PLLCFGR()->setPLLSRC(RCC::PLLCFGR::PLLSRC::HSE);
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// Enable the PLL and wait for it to be ready
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RCC.CR()->setPLLON(true);
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// Enable Over-drive
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PWR.CR()->setODEN(true);
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while(!PWR.CSR()->getODRDY()) {
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}
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PWR.CR()->setODSWEN(true);
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while(!PWR.CSR()->getODSWRDY()) {
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}
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// Choose Voltage scale 1
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PWR.CR()->setVOS(PWR::CR::Voltage::Scale1);
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while (!PWR.CSR()->getVOSRDY()) {}
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/* After reset the Flash runs as fast as the CPU. When we clock the CPU faster
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* the flash memory cannot follow and therefore flash memory accesses need to
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* wait a little bit.
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* The spec tells us that at 2.8V and over 210MHz the flash expects 7 WS. */
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FLASH.ACR()->setLATENCY(7);
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/* Enable prefetching flash instructions */
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/* Fetching instructions increases slightly the power consumption but the
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* increase is negligible compared to the screen consumption. */
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FLASH.ACR()->setPRFTEN(true);
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/* Enable the ART */
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FLASH.ACR()->setARTEN(true);
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// 192 MHz is too fast for APB1. Divide it by four to reach 48 MHz
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RCC.CFGR()->setPPRE1(Clocks::Config::APB1PrescalerReg);
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// 192 MHz is too fast for APB2. Divide it by two to reach 96 MHz
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RCC.CFGR()->setPPRE2(Clocks::Config::APB2PrescalerReg);
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while(!RCC.CR()->getPLLRDY()) {
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}
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// Use the PLL output as a SYSCLK source
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RCC.CFGR()->setSW(RCC::CFGR::SW::PLL);
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while (RCC.CFGR()->getSWS() != RCC::CFGR::SW::PLL) {
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}
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// Now that we don't need use it anymore, turn the HSI off
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RCC.CR()->setHSION(false);
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// Peripheral clocks
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// AHB1 bus
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// Our peripherals are using GPIO A, B, C, D and E.
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// We're not using the CRC nor DMA engines.
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class RCC::AHB1ENR ahb1enr(0x00100000); // Reset value
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ahb1enr.setGPIOAEN(true);
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ahb1enr.setGPIOBEN(true);
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ahb1enr.setGPIOCEN(true);
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ahb1enr.setGPIODEN(true);
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ahb1enr.setGPIOEEN(true);
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ahb1enr.setDMA2EN(true);
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RCC.AHB1ENR()->set(ahb1enr);
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// AHB2 bus
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RCC.AHB2ENR()->setOTGFSEN(true);
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// AHB3 bus
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RCC.AHB3ENR()->setFSMCEN(true);
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// APB1 bus
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// We're using TIM3 for the LEDs
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RCC.APB1ENR()->setTIM3EN(true);
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// APB2 bus
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class RCC::APB2ENR apb2enr(0); // Reset value
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apb2enr.setADC1EN(true);
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apb2enr.setSYSCFGEN(true);
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apb2enr.setUSART6EN(true); // TODO if EPSILON_DEVICE_BENCH?
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RCC.APB2ENR()->set(apb2enr);
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// Configure clocks in sleep mode
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// AHB1 peripheral clock enable in low-power mode register
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class RCC::AHB1LPENR ahb1lpenr(0x7EF7B7FF); // Reset value
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ahb1lpenr.setGPIOALPEN(true); // Enable IO port A for Charging/USB plug/Keyboard pins
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ahb1lpenr.setGPIOBLPEN(true); // Enable IO port B for LED pins
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ahb1lpenr.setGPIOCLPEN(true); // Enable IO port C for LED/Keyboard pins
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ahb1lpenr.setGPIODLPEN(false); // Disable IO port D (LCD...)
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ahb1lpenr.setGPIOELPEN(true); // Enable IO port E for Keyboard/Battery pins
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ahb1lpenr.setGPIOFLPEN(false); // Disable IO port F
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ahb1lpenr.setGPIOGLPEN(false); // Disable IO port G
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ahb1lpenr.setGPIOHLPEN(false); // Disable IO port H
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ahb1lpenr.setGPIOILPEN(false); // Disable IO port I
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ahb1lpenr.setCRCLPEN(false);
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ahb1lpenr.setFLITFLPEN(false);
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ahb1lpenr.setSRAM1LPEN(false);
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ahb1lpenr.setDMA1LPEN(false);
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ahb1lpenr.setDMA2LPEN(false);
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ahb1lpenr.setAXILPEN(false);
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ahb1lpenr.setSRAM2LPEN(false);
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ahb1lpenr.setBKPSRAMLPEN(false);
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ahb1lpenr.setDTCMLPEN(false);
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ahb1lpenr.setOTGHSLPEN(false);
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ahb1lpenr.setOTGHSULPILPEN(false);
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RCC.AHB1LPENR()->set(ahb1lpenr);
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// AHB2 peripheral clock enable in low-power mode register
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class RCC::AHB2LPENR ahb2lpenr(0x000000F1); // Reset value
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ahb2lpenr.setOTGFSLPEN(false);
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ahb2lpenr.setRNGLPEN(false);
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ahb2lpenr.setAESLPEN(false);
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RCC.AHB2LPENR()->set(ahb2lpenr);
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// AHB3 peripheral clock enable in low-power mode register
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class RCC::AHB3LPENR ahb3lpenr(0x00000003); // Reset value
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ahb3lpenr.setFMCLPEN(false);
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ahb3lpenr.setQSPILPEN(false);
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RCC.AHB3LPENR()->set(ahb3lpenr);
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// APB1 peripheral clock enable in low-power mode register
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class RCC::APB1LPENR apb1lpenr(0xFFFFCBFF); // Reset value
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apb1lpenr.setTIM2LPEN(false);
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apb1lpenr.setTIM3LPEN(true); // Enable TIM3 in sleep mode for LEDs
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apb1lpenr.setTIM4LPEN(false);
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apb1lpenr.setTIM5LPEN(false);
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apb1lpenr.setTIM6LPEN(false);
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apb1lpenr.setTIM7LPEN(false);
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apb1lpenr.setTIM12LPEN(false);
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apb1lpenr.setTIM13LPEN(false);
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apb1lpenr.setTIM14LPEN(false);
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apb1lpenr.setRTCAPBLPEN(false);
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apb1lpenr.setWWDGLPEN(false);
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apb1lpenr.setSPI2LPEN(false);
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apb1lpenr.setSPI3LPEN(false);
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apb1lpenr.setUSART2LPEN(false);
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apb1lpenr.setUSART3LPEN(false);
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apb1lpenr.setI2C1LPEN(false);
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apb1lpenr.setI2C2LPEN(false);
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apb1lpenr.setI2C3LPEN(false);
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apb1lpenr.setCAN1LPEN(false);
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apb1lpenr.setPWRLPEN(false);
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apb1lpenr.setLPTIM1LPEN(false);
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apb1lpenr.setUSART4LPEN(false);
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apb1lpenr.setUSART5LPEN(false);
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apb1lpenr.setOTGHSLPEN(false);
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apb1lpenr.setOTGHSULPILPEN(false);
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RCC.APB1LPENR()->set(apb1lpenr);
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// APB2 peripheral clock enable in low-power mode register
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class RCC::APB2LPENR apb2lpenr(0x04F77F33); // Reset value
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apb2lpenr.setTIM1LPEN(false);
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apb2lpenr.setTIM8LPEN(false);
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apb2lpenr.setUSART1LPEN(false);
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apb2lpenr.setUSART6LPEN(false);
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apb2lpenr.setADC1LPEN(false);
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apb2lpenr.setSPI1LPEN(false);
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apb2lpenr.setSPI4LPEN(false);
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apb2lpenr.setSYSCFGLPEN(false);
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apb2lpenr.setTIM9LPEN(false);
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apb2lpenr.setTIM10LPEN(false);
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apb2lpenr.setTIM11LPEN(false);
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apb2lpenr.setSPI5LPEN(false);
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apb2lpenr.setSDMMC2LPEN(false);
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apb2lpenr.setADC2LPEN(false);
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apb2lpenr.setADC3LPEN(false);
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apb2lpenr.setSAI1LPEN(false);
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apb2lpenr.setSAI2LPEN(false);
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RCC.APB2LPENR()->set(apb2lpenr);
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}
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void shutdownClocks(bool keepLEDAwake) {
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// APB2 bus
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RCC.APB2ENR()->set(0); // Reset value
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// AHB2 bus
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RCC.AHB2ENR()->set(0); // Reset value
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// AHB3 bus
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RCC.AHB3ENR()->set(0); // Reset value
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// APB1
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class RCC::APB1ENR apb1enr(0); // Reset value
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// AHB1 bus
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class RCC::AHB1ENR ahb1enr(0x00100000); // Reset value
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if (keepLEDAwake) {
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apb1enr.setTIM3EN(true);
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ahb1enr.setGPIOBEN(true);
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}
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RCC.APB1ENR()->set(apb1enr);
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RCC.AHB1ENR()->set(ahb1enr);
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}
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}
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}
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}
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