diff --git a/.cproject b/.cproject index 06907bb..f817501 100644 --- a/.cproject +++ b/.cproject @@ -23,7 +23,7 @@ @@ -58,6 +66,10 @@ + + + + - + + + + + @@ -88,6 +117,8 @@ + + @@ -116,7 +147,7 @@ @@ -146,6 +185,10 @@ - + + + + + @@ -176,6 +236,8 @@ + + diff --git a/.mxproject b/.mxproject index 15d5687..b9d5c02 100644 --- a/.mxproject +++ b/.mxproject @@ -1,25 +1,45 @@ [PreviousLibFiles] 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G4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_bus.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_system.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_utils.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_crs.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ramfunc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_utils.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_exti.c;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_ucpd.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_usart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_lpuart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart_ex.h;Middlewares\ST\STM32_USBPD_Library\Core\inc\usbpd_core.h;Middlewares\ST\STM32_USBPD_Library\Core\inc\usbpd_def.h;Middlewares\ST\STM32_USBPD_Library\Core\inc\usbpd_tcpm.h;Middlewares\ST\STM32_USBPD_Library\Core\inc\usbpd_trace.h;Middlewares\ST\STM32_USBPD_Library\Core\lib\USBPDCORE_PD3_FULL_CM4_wc32.a;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\inc\usbpd_cad_hw_if.h;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\inc\usbpd_hw.h;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\inc\usbpd_hw_if.h;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\inc\usbpd_phy.h;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\inc\usbpd_timersserver.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g491xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; [PreviousUsedCubeIDEFiles] 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-HeaderPath=Drivers\STM32G4xx_HAL_Driver\Inc;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32G4xx\Include;Drivers\CMSIS\Include;Core\Inc; -CDefines=USE_HAL_DRIVER;STM32G491xx;USE_HAL_DRIVER;USE_HAL_DRIVER; +SourceFiles=Core\Src\main.c;USBPD\App\usbpd.c;USBPD\usbpd_dpm_user.c;USBPD\usbpd_pwr_user.c;USBPD\usbpd_pwr_if.c;USBPD\usbpd_vdm_user.c;USBPD\usbpd_dpm_core.c;Core\Src\stm32g4xx_it.c;Core\Src\stm32g4xx_hal_msp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_utils.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_exti.c;Middlewares\ST\STM32_USBPD_Library\Core\lib\USBPDCORE_PD3_FULL_CM4_wc32.a;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_i2c.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_i2c_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_ucpd.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Middlewares\ST\STM32_USBPD_Library\Core\src\usbpd_trace.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_cad_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_hw.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_hw_if_it.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_phy.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_phy_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_pwr_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_timersserver.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_tim.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_utils.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_exti.c;Middlewares\ST\STM32_USBPD_Library\Core\lib\USBPDCORE_PD3_FULL_CM4_wc32.a;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_i2c.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_i2c_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_ucpd.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Middlewares\ST\STM32_USBPD_Library\Core\src\usbpd_trace.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_cad_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_hw.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_hw_if_it.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_phy.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_phy_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_pwr_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_timersserver.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_tim.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;;;Middlewares\ST\STM32_USBPD_Library\Core\lib\USBPDCORE_PD3_FULL_CM4_wc32.a;Middlewares\ST\STM32_USBPD_Library\Core\src\usbpd_trace.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_cad_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_hw.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_hw_if_it.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_phy.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_phy_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_pwr_hw_if.c;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\src\usbpd_timersserver.c; +HeaderPath=Drivers\STM32G4xx_HAL_Driver\Inc;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy;Middlewares\ST\STM32_USBPD_Library\Core\inc;Middlewares\ST\STM32_USBPD_Library\Devices\STM32G4XX\inc;Drivers\CMSIS\Device\ST\STM32G4xx\Include;Drivers\CMSIS\Include;USBPD\App;USBPD;Core\Inc; +CDefines=USE_FULL_LL_DRIVER;USBPD_PORT_COUNT:1;_SRC;USBPDCORE_LIB_PD3_FULL;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32G491xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true -HeaderFileListSize=3 -HeaderFiles#0=..\Core\Inc\stm32g4xx_it.h -HeaderFiles#1=..\Core\Inc\stm32g4xx_hal_conf.h -HeaderFiles#2=..\Core\Inc\main.h -HeaderFolderListSize=1 -HeaderPath#0=..\Core\Inc +HeaderFileListSize=13 +HeaderFiles#0=..\USBPD\App\usbpd.h +HeaderFiles#1=..\USBPD\usbpd_dpm_conf.h +HeaderFiles#2=..\USBPD\usbpd_dpm_user.h +HeaderFiles#3=..\USBPD\usbpd_pwr_user.h +HeaderFiles#4=..\USBPD\usbpd_pdo_defs.h +HeaderFiles#5=..\USBPD\usbpd_pwr_if.h +HeaderFiles#6=..\USBPD\usbpd_vdm_user.h +HeaderFiles#7=..\USBPD\usbpd_dpm_core.h +HeaderFiles#8=..\USBPD\usbpd_devices_conf.h +HeaderFiles#9=..\Core\Inc\stm32g4xx_it.h +HeaderFiles#10=..\Core\Inc\stm32_assert.h +HeaderFiles#11=..\Core\Inc\stm32g4xx_hal_conf.h +HeaderFiles#12=..\Core\Inc\main.h +HeaderFolderListSize=3 +HeaderPath#0=..\USBPD\App +HeaderPath#1=..\USBPD +HeaderPath#2=..\Core\Inc HeaderFiles=; -SourceFileListSize=3 -SourceFiles#0=..\Core\Src\stm32g4xx_it.c -SourceFiles#1=..\Core\Src\stm32g4xx_hal_msp.c -SourceFiles#2=..\Core\Src\main.c -SourceFolderListSize=1 -SourcePath#0=..\Core\Src +SourceFileListSize=9 +SourceFiles#0=..\USBPD\App\usbpd.c +SourceFiles#1=..\USBPD\usbpd_dpm_user.c +SourceFiles#2=..\USBPD\usbpd_pwr_user.c +SourceFiles#3=..\USBPD\usbpd_pwr_if.c +SourceFiles#4=..\USBPD\usbpd_vdm_user.c +SourceFiles#5=..\USBPD\usbpd_dpm_core.c +SourceFiles#6=..\Core\Src\stm32g4xx_it.c +SourceFiles#7=..\Core\Src\stm32g4xx_hal_msp.c +SourceFiles#8=..\Core\Src\main.c +SourceFolderListSize=3 +SourcePath#0=..\USBPD\App +SourcePath#1=..\USBPD +SourcePath#2=..\Core\Src SourceFiles=; diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml index 5049a4b..a329744 100644 --- a/.settings/language.settings.xml +++ b/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/Core/Inc/alim.h b/Core/Inc/alim.h new file mode 100644 index 0000000..f911c79 --- /dev/null +++ b/Core/Inc/alim.h @@ -0,0 +1,34 @@ +/* + * alim.h + * + * Created on: May 11, 2025 + * Author: allan + */ + +#ifndef INC_ALIM_H_ +#define INC_ALIM_H_ + +extern UART_HandleTypeDef huart2; +extern I2C_HandleTypeDef hi2c1; + +typedef enum i2cAdress { + I2C_TEMP = 0x18, + I2C_IN1 = 0x48, + I2C_IN2 = 0x4A, + I2C_OUT5V = 0x43, + I2C_OUT5V1 = 0x40, + I2C_OUT12V = 0x41, + I2C_OUT24V = 0x4B +} i2cAdress; + + +// Prototypes +HAL_StatusTypeDef read_bau_state(int* val); +HAL_StatusTypeDef read_mcp9808_temp(float* val); +HAL_StatusTypeDef ina236_write_reg(i2cAdress address, uint8_t reg, uint16_t value); +HAL_StatusTypeDef ina236_read_reg(i2cAdress address, uint8_t reg, uint16_t *value); +HAL_StatusTypeDef ina236_init(i2cAdress address, float r_shunt, float current_lsb); +HAL_StatusTypeDef read_ina236_voltage(i2cAdress address, float *voltage); +HAL_StatusTypeDef read_ina236_current(i2cAdress address, float currentLSB, float *current); + +#endif /* INC_ALIM_H_ */ diff --git a/Core/Inc/comm.h b/Core/Inc/comm.h new file mode 100644 index 0000000..2c1c233 --- /dev/null +++ b/Core/Inc/comm.h @@ -0,0 +1,20 @@ +/* + * comm.h + * + * Created on: May 12, 2025 + * Author: allan + */ + +#ifndef INC_COMM_H_ +#define INC_COMM_H_ + +#define RX_BUFFER_SIZE 128 + +// Prototypes +void handle_uart_message(const char *msg); +void handle_get(const char *xxx, const char *yyy); +void handle_set(const char *xxx, const char *yyy, const char *val); +void send_set_response(const char *xxx, const char *yyy, int val); +void send_error_response(void); + +#endif /* INC_COMM_H_ */ diff --git a/Core/Inc/main.h b/Core/Inc/main.h index b0a0b10..6612b75 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -29,6 +29,18 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" +#include "stm32g4xx_ll_ucpd.h" +#include "stm32g4xx_ll_bus.h" +#include "stm32g4xx_ll_cortex.h" +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_utils.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_gpio.h" +#include "stm32g4xx_ll_dma.h" + +#include "stm32g4xx_ll_exti.h" + /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -59,6 +71,8 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ +#define TCPP02_EN_Pin GPIO_PIN_9 +#define TCPP02_EN_GPIO_Port GPIOA /* USER CODE BEGIN Private defines */ diff --git a/Core/Inc/stm32_assert.h b/Core/Inc/stm32_assert.h new file mode 100644 index 0000000..61631c4 --- /dev/null +++ b/Core/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + diff --git a/Core/Inc/stm32g4xx_it.h b/Core/Inc/stm32g4xx_it.h index 73c1975..8bdac3b 100644 --- a/Core/Inc/stm32g4xx_it.h +++ b/Core/Inc/stm32g4xx_it.h @@ -56,8 +56,11 @@ void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void EXTI1_IRQHandler(void); +void DMA1_Channel1_IRQHandler(void); +void DMA1_Channel2_IRQHandler(void); void EXTI9_5_IRQHandler(void); void USART2_IRQHandler(void); +void UCPD1_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Src/alim.c b/Core/Src/alim.c new file mode 100644 index 0000000..4770266 --- /dev/null +++ b/Core/Src/alim.c @@ -0,0 +1,87 @@ +#include "main.h" +#include "alim.h" +#include "comm.h" +#include +#include + + +HAL_StatusTypeDef read_bau_state(int* val){ + if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_1) == GPIO_PIN_SET){ + *val = 0; + return HAL_ERROR; + } else { + *val = 1; + return HAL_ERROR; + } + return HAL_OK; +} + +HAL_StatusTypeDef read_mcp9808_temp(float* temp) { + uint8_t reg = 0x05; + uint8_t data[2]; + + if (HAL_I2C_Master_Transmit(&hi2c1, I2C_TEMP << 1, ®, 1, HAL_MAX_DELAY) != HAL_OK){ + return HAL_ERROR; + } + if (HAL_I2C_Master_Receive(&hi2c1, I2C_TEMP << 1, data, 2, HAL_MAX_DELAY) != HAL_OK){ + return HAL_ERROR; + } + + uint16_t raw = (data[0] << 8) | data[1]; + raw &= 0x1FFF; + + *temp = raw & 0x1000 ? (raw - 8192) * 0.0625f : raw * 0.0625f; + return HAL_OK; +} + +HAL_StatusTypeDef ina236_write_reg(i2cAdress address, uint8_t reg, uint16_t value) { + uint8_t data[3]; + data[0] = reg; + data[1] = (value >> 8); + data[2] = (value & 0xFF); + return HAL_I2C_Master_Transmit(&hi2c1, address << 1, data, 3, HAL_MAX_DELAY); +} + +HAL_StatusTypeDef ina236_read_reg(i2cAdress address, uint8_t reg, uint16_t *value) { + uint8_t data[2]; + if (HAL_I2C_Master_Transmit(&hi2c1, address << 1, ®, 1, HAL_MAX_DELAY) != HAL_OK) + return HAL_ERROR; + if (HAL_I2C_Master_Receive(&hi2c1, address << 1, data, 2, HAL_MAX_DELAY) != HAL_OK) + return HAL_ERROR; + + *value = (data[0] << 8) | data[1]; + return HAL_OK; +} + +HAL_StatusTypeDef ina236_init(i2cAdress address, float r_shunt, float current_lsb) { + uint16_t calibration = (uint16_t)(0.00512 / (r_shunt * current_lsb)); + if(ina236_write_reg(address, 0x05, calibration) != HAL_OK){ + return HAL_ERROR; + } + + uint16_t config = 0x4127; // Exemple: moyenne x4, conversion 1.1ms, mode shunt+bus continuous + if(ina236_write_reg(address, 0x00, config) != HAL_OK){ + return HAL_ERROR; + } + return HAL_OK; +} + +HAL_StatusTypeDef read_ina236_voltage(i2cAdress address, float *voltage) { + uint16_t raw; + if (ina236_read_reg(address, 0x02, &raw) != HAL_OK){ + return HAL_ERROR; + } + *voltage = (raw * 1.25f); // 1.25 mV/bit → en mV + return HAL_OK; +} + +HAL_StatusTypeDef read_ina236_current(i2cAdress address, float currentLSB, float *current) { + uint16_t raw; + if (ina236_read_reg(address, 0x04, &raw) != HAL_OK){ + return HAL_ERROR; + } + *current = ((int16_t)raw) * currentLSB * 1000; // en mA + return HAL_OK; +} + + diff --git a/Core/Src/comm.c b/Core/Src/comm.c index b5bc963..022db1a 100644 --- a/Core/Src/comm.c +++ b/Core/Src/comm.c @@ -1,33 +1,17 @@ +#include "comm.h" #include "main.h" +#include "alim.h" #include #include #include +#include #include #include -extern UART_HandleTypeDef huart2; -extern I2C_HandleTypeDef hi2c1; - -typedef enum errorCode { - COMM_SUCCESS, - COMM_ERROR -} errorCode ; - -#define RX_BUFFER_SIZE 128 static char rxBuffer[RX_BUFFER_SIZE]; static uint8_t rxIndex = 0; static char rxChar; -// Prototypes -void handle_uart_message(const char *msg); -void handle_get(const char *xxx, const char *yyy); -void handle_set(const char *xxx, const char *yyy, const char *val); -void send_set_response(const char *xxx, const char *yyy, int val); -void send_error_response(void); -errorCode read_bau_state(int* val); -errorCode read_mcp9808_temp(float* val); - - // Lancer la réception UART void uart_start_reception() { HAL_UART_Receive_IT(&huart2, (uint8_t *)&rxChar, 1); @@ -71,19 +55,94 @@ void handle_uart_message(const char *msg) { void handle_get(const char *xxx, const char *yyy) { if (strcmp(xxx, "BAU") == 0 && strcmp(yyy, "STATE") == 0) { int val = 0; - errorCode res = read_bau_state(&val); - if(res == COMM_SUCCESS){ + HAL_StatusTypeDef res = read_bau_state(&val); + if(res == HAL_OK){ send_set_response(xxx, yyy, val); return; } } else if (strcmp(xxx, "TEMP") == 0 && strcmp(yyy, "CELS") == 0) { float temp = -1000.0f; - errorCode res = read_mcp9808_temp(&temp); - if (res == COMM_SUCCESS) { + HAL_StatusTypeDef res = read_mcp9808_temp(&temp); + if (res == HAL_OK) { int temp_dixieme = (int)(temp * 10.0f + 0.5f); send_set_response(xxx, yyy, temp_dixieme); return; } + } else { + // Concerne les entrees sorties + + i2cAdress address; + float currentLSB; + bool validZone = false; + uint16_t controlPin; + uint16_t validPin; + + // Selection zone mesure + if(strcmp(xxx, "IN1") == 0){ + address = I2C_IN1; + currentLSB = 0.000610f; + validPin = GPIO_PIN_5; + validZone = true; + } else if (strcmp(xxx, "IN2") == 0){ + address = I2C_IN2; + currentLSB = 0.000610f; + validPin = GPIO_PIN_6; + validZone = true; + } else if (strcmp(xxx, "OUT5V") == 0){ + address = I2C_OUT5V; + currentLSB = 0.000185f; + controlPin = GPIO_PIN_0; + validZone = true; + } else if (strcmp(xxx, "OUT5V1") == 0){ + address = I2C_OUT5V1; + currentLSB = 0.000185f; + validZone = true; + } else if (strcmp(xxx, "OUT12V") == 0){ + address = I2C_OUT12V; + currentLSB = 0.000125f; + controlPin = GPIO_PIN_10; + validZone = true; + } else if (strcmp(xxx, "OUT24") == 0){ + address = I2C_OUT24V; + currentLSB = 0.000040f; + controlPin = GPIO_PIN_11; + validZone = true; + } + + // Selection type mesure + if(strcmp(yyy, "VOLT") == 0 && validZone){ + float val = 0.0f; + HAL_StatusTypeDef res = read_ina236_voltage(address, &val); + if (res == HAL_OK) { + send_set_response(xxx, yyy, val); + return; + } + } else if (strcmp(yyy, "AMPS") == 0 && validZone){ + float val = 0.0f; + HAL_StatusTypeDef res = read_ina236_current(address, currentLSB, &val); + if (res == HAL_OK) { + send_set_response(xxx, yyy, val); + return; + } + } else if (strcmp(yyy, "VALID") == 0 && validZone){ + int val = 0; + if((strcmp(xxx, "IN1") == 0) || (strcmp(xxx, "IN2") == 0)){ + val = (HAL_GPIO_ReadPin(GPIOA, validPin) == GPIO_PIN_RESET) ? 1 : 0; + } else { + val = 1; + } + send_set_response(xxx, yyy, val); + return; + } else if (strcmp(yyy, "STATE") == 0 && validZone){ + int val = 0; + if((strcmp(xxx, "OUT5V") == 0) || (strcmp(xxx, "OUT12V") == 0) || (strcmp(xxx, "OUT24V") == 0)){ + val = (HAL_GPIO_ReadPin(GPIOA, controlPin) == GPIO_PIN_RESET) ? 1 : 0; + } else { + val = 1; + } + send_set_response(xxx, yyy, val); + return; + } } send_error_response(); } @@ -97,9 +156,20 @@ void handle_set(const char *xxx, const char *yyy, const char *val) { (strcmp(xxx, "OUT12V") == 0 && strcmp(yyy, "STATE") == 0) || (strcmp(xxx, "OUT24V") == 0 && strcmp(yyy, "STATE") == 0))) { - // Appliquer commande... + GPIO_PinState pin_state = (v == 1) ? GPIO_PIN_RESET : GPIO_PIN_SET; // Niveau actif bas + int success = 0; + + if (strcmp(xxx, "OUT5V") == 0 && strcmp(yyy, "STATE") == 0) { + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, pin_state); + success = 1; + } else if (strcmp(xxx, "OUT12V") == 0 && strcmp(yyy, "STATE") == 0) { + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10, pin_state); + success = 1; + } else if (strcmp(xxx, "OUT24V") == 0 && strcmp(yyy, "STATE") == 0) { + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_11, pin_state); + success = 1; + } - int success = 1; if (success) { char msg[64]; snprintf(msg, sizeof(msg), "OK;%s;%s;%d\n", xxx, yyy, v); @@ -124,33 +194,3 @@ void send_error_response() { const char *msg = "KO;PARSE;ERROR;0\n"; HAL_UART_Transmit(&huart2, (uint8_t *)msg, strlen(msg), HAL_MAX_DELAY); } - -errorCode read_bau_state(int* val){ - if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_1) == GPIO_PIN_SET){ - *val = 0; - return COMM_SUCCESS; - } else { - *val = 1; - return COMM_SUCCESS; - } - return COMM_ERROR; -} - -errorCode read_mcp9808_temp(float* temp) { - uint8_t reg = 0x05; - uint8_t data[2]; - - if (HAL_I2C_Master_Transmit(&hi2c1, 0x18 << 1, ®, 1, HAL_MAX_DELAY) != HAL_OK){ - return COMM_ERROR; - } - if (HAL_I2C_Master_Receive(&hi2c1, 0x18 << 1, data, 2, HAL_MAX_DELAY) != HAL_OK){ - return COMM_ERROR; - } - - uint16_t raw = (data[0] << 8) | data[1]; - raw &= 0x1FFF; - - *temp = raw & 0x1000 ? (raw - 8192) * 0.0625f : raw * 0.0625f; - return COMM_SUCCESS; -} - diff --git a/Core/Src/main.c b/Core/Src/main.c index 9171b3f..ac9e889 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -18,9 +18,11 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" +#include "usbpd.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "alim.h" #include /* USER CODE END Includes */ @@ -53,9 +55,11 @@ UART_HandleTypeDef huart2; /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); static void MX_GPIO_Init(void); +static void MX_DMA_Init(void); static void MX_TIM3_Init(void); static void MX_USART2_UART_Init(void); static void MX_I2C1_Init(void); +static void MX_UCPD1_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -94,20 +98,33 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_DMA_Init(); MX_TIM3_Init(); MX_USART2_UART_Init(); MX_I2C1_Init(); + MX_UCPD1_Init(); /* USER CODE BEGIN 2 */ + if(HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_1) == GPIO_PIN_SET){ BAU_State = 0; }else{ BAU_State = 1; } + ina236_init(I2C_IN1, 0.004f, 0.000610f); // Rshunt = 4 mOhm, currentLSB = 610 uA (maxCurrent = 20A) + ina236_init(I2C_IN2, 0.004f, 0.000610f); // Rshunt = 4 mOhm, currentLSB = 610 uA (maxCurrent = 20A) + ina236_init(I2C_OUT5V, 0.013f, 0.000185f); // Rshunt = 13 mOhm, currentLSB = 185 uA (maxCurrent = 6A) + ina236_init(I2C_OUT5V1, 0.013f, 0.000185f); // Rshunt = 13 mOhm, currentLSB = 185 uA (maxCurrent = 6A) + ina236_init(I2C_OUT12V, 0.020f, 0.000125f); // Rshunt = 20 mOhm, currentLSB = 305 uA (maxCurrent = 4A) + ina236_init(I2C_OUT24V, 0.062f, 0.000040f); // Rshunt = 62 mOhm, currentLSB = 40 uA (maxCurrent = 1A25) + uart_start_reception(); /* USER CODE END 2 */ + /* USBPD initialisation ---------------------------------*/ + MX_USBPD_Init(); + /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) @@ -118,6 +135,7 @@ int main(void) HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); HAL_Delay(500);*/ /* USER CODE END WHILE */ + USBPD_DPM_Run(); /* USER CODE BEGIN 3 */ } @@ -277,6 +295,87 @@ static void MX_TIM3_Init(void) } +/** + * @brief UCPD1 Initialization Function + * @param None + * @retval None + */ +static void MX_UCPD1_Init(void) +{ + + /* USER CODE BEGIN UCPD1_Init 0 */ + + /* USER CODE END UCPD1_Init 0 */ + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1); + + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); + /**UCPD1 GPIO Configuration + PB4 ------> UCPD1_CC2 + PB6 ------> UCPD1_CC1 + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* UCPD1 DMA Init */ + + /* UCPD1_RX Init */ + LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX); + + LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + + LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_LOW); + + LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_NORMAL); + + LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT); + + LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT); + + LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_BYTE); + + LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_BYTE); + + /* UCPD1_TX Init */ + LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_2, LL_DMAMUX_REQ_UCPD1_TX); + + LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_2, LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + + LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PRIORITY_LOW); + + LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MODE_NORMAL); + + LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PERIPH_NOINCREMENT); + + LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MEMORY_INCREMENT); + + LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PDATAALIGN_BYTE); + + LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MDATAALIGN_BYTE); + + /* UCPD1 interrupt Init */ + NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(UCPD1_IRQn); + + /* USER CODE BEGIN UCPD1_Init 1 */ + + /* USER CODE END UCPD1_Init 1 */ + /* USER CODE BEGIN UCPD1_Init 2 */ + + /* USER CODE END UCPD1_Init 2 */ + +} + /** * @brief USART2 Initialization Function * @param None @@ -325,6 +424,26 @@ static void MX_USART2_UART_Init(void) } +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Channel1_IRQn interrupt configuration */ + NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(DMA1_Channel1_IRQn); + /* DMA1_Channel2_IRQn interrupt configuration */ + NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(DMA1_Channel2_IRQn); + +} + /** * @brief GPIO Initialization Function * @param None @@ -340,6 +459,16 @@ static void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0|TCPP02_EN_Pin|GPIO_PIN_10|GPIO_PIN_11, GPIO_PIN_RESET); + + /*Configure GPIO pins : PA0 PA10 PA11 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /*Configure GPIO pin : PA1 */ GPIO_InitStruct.Pin = GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; @@ -352,6 +481,19 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /*Configure GPIO pin : TCPP02_EN_Pin */ + GPIO_InitStruct.Pin = TCPP02_EN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(TCPP02_EN_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : PA12 */ + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /*Configure GPIO pin : PB5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; diff --git a/Core/Src/stm32g4xx_it.c b/Core/Src/stm32g4xx_it.c index 65769b3..62346cc 100644 --- a/Core/Src/stm32g4xx_it.c +++ b/Core/Src/stm32g4xx_it.c @@ -20,6 +20,7 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "stm32g4xx_it.h" +#include "usbpd.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -186,6 +187,7 @@ void SysTick_Handler(void) /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); + USBPD_DPM_TimerCounter(); /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ @@ -212,6 +214,32 @@ void EXTI1_IRQHandler(void) /* USER CODE END EXTI1_IRQn 1 */ } +/** + * @brief This function handles DMA1 channel1 global interrupt. + */ +void DMA1_Channel1_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ + + /* USER CODE END DMA1_Channel1_IRQn 0 */ + /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ + + /* USER CODE END DMA1_Channel1_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 channel2 global interrupt. + */ +void DMA1_Channel2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ + + /* USER CODE END DMA1_Channel2_IRQn 0 */ + /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ + + /* USER CODE END DMA1_Channel2_IRQn 1 */ +} + /** * @brief This function handles EXTI line[9:5] interrupts. */ @@ -240,6 +268,21 @@ void USART2_IRQHandler(void) /* USER CODE END USART2_IRQn 1 */ } +/** + * @brief This function handles UCPD1 interrupt / UCPD1 wake-up interrupt through EXTI line 43. + */ +void UCPD1_IRQHandler(void) +{ + /* USER CODE BEGIN UCPD1_IRQn 0 */ + + /* USER CODE END UCPD1_IRQn 0 */ + USBPD_PORT0_IRQHandler(); + + /* USER CODE BEGIN UCPD1_IRQn 1 */ + + /* USER CODE END UCPD1_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h b/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h new file mode 100644 index 0000000..16d6228 --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h @@ -0,0 +1,1874 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_ucpd.h + * @author MCD Application Team + * @brief Header file of UCPD LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_LL_UCPD_H +#define STM32G4xx_LL_UCPD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx.h" + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ + +#if defined (UCPD1) + +/** @defgroup UCPD_LL UCPD + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure + * @{ + */ + +/** + * @brief UCPD Init structures definition + */ +typedef struct +{ + uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock. + This parameter can be a value of @ref UCPD_LL_EC_PSC. + This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk(). + */ + + uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) + to achieve a legal tTransitionWindow (set according to peripheral clock to define + an interval of between 12 and 20 us). + This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F + This value can be modified afterwards using function @ref LL_UCPD_SetTransWin(). + */ + + uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate + tInterframeGap from the peripheral clock. + This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F + This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap(). + */ + + uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock + e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock : + "UCPD1_CLK". + This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F. + This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv(). + */ + +} LL_UCPD_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants + * @{ + */ + +/** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ucpd_ReadReg function + * @{ + */ +#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */ +#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */ +#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */ +#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */ +#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */ +#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */ +#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */ +#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */ +#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */ +#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */ +#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */ +#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */ +#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */ +#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */ +#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in UCPD register + * @param __INSTANCE__ UCPD Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions + * @{ + */ + +/** @defgroup UCPD_LL_EF_Configuration Configuration + * @{ + */ + +/** @defgroup UCPD_LL_EF_CFG1 CFG1 register + * @{ + */ +/** + * @brief Enable UCPD peripheral + * @rmtoll CFG1 UCPDEN LL_UCPD_Enable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); +} + +/** + * @brief Disable UCPD peripheral + * @note When disabling the UCPD, follow the procedure described in the Reference Manual. + * @rmtoll CFG1 UCPDEN LL_UCPD_Disable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); +} + +/** + * @brief Check if UCPD peripheral is enabled + * @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the receiver ordered set detection enable + * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet + * @param UCPDx UCPD Instance + * @param OrderSet This parameter can be combination of the following values: + * @arg @ref LL_UCPD_ORDERSET_SOP + * @arg @ref LL_UCPD_ORDERSET_SOP1 + * @arg @ref LL_UCPD_ORDERSET_SOP2 + * @arg @ref LL_UCPD_ORDERSET_HARDRST + * @arg @ref LL_UCPD_ORDERSET_CABLERST + * @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG + * @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG + * @arg @ref LL_UCPD_ORDERSET_SOP_EXT1 + * @arg @ref LL_UCPD_ORDERSET_SOP_EXT2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); +} + +/** + * @brief Set the prescaler for ucpd clock + * @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk + * @param UCPDx UCPD Instance + * @param Psc This parameter can be one of the following values: + * @arg @ref LL_UCPD_PSC_DIV1 + * @arg @ref LL_UCPD_PSC_DIV2 + * @arg @ref LL_UCPD_PSC_DIV4 + * @arg @ref LL_UCPD_PSC_DIV8 + * @arg @ref LL_UCPD_PSC_DIV16 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); +} + +/** + * @brief Set the number of cycles (minus 1) of the half bit clock + * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin + * @param UCPDx UCPD Instance + * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); +} + +/** + * @brief Set the clock divider value to generate an interframe gap + * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap + * @param UCPDx UCPD Instance + * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); +} + +/** + * @brief Set the clock divider value to generate an interframe gap + * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv + * @param UCPDx UCPD Instance + * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock) +{ + MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_CFG2 CFG2 register + * @{ + */ + +/** + * @brief Enable the wakeup mode + * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); +} + +/** + * @brief Disable the wakeup mode + * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); +} + +/** + * @brief Force clock enable + * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); +} + +/** + * @brief Force clock disable + * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); +} + +/** + * @brief RxFilter enable + * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); +} + +/** + * @brief RxFilter disable + * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_CR CR register + * @{ + */ +/** + * @brief Type C detector for CC2 enable + * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); +} + +/** + * @brief Type C detector for CC2 disable + * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); +} + +/** + * @brief Type C detector for CC1 enable + * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); +} + +/** + * @brief Type C detector for CC1 disable + * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); +} + +/** + * @brief Source Vconn discharge enable + * @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_RDCH); +} + +/** + * @brief Source Vconn discharge disable + * @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH); +} + +/** + * @brief Signal Fast Role Swap request + * @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_FRSTX); +} + +/** + * @brief Fast Role swap RX detection enable + * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); +} + +/** + * @brief Fast Role swap RX detection disable + * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); +} + +/** + * @brief Set cc enable + * @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable + * @param UCPDx UCPD Instance + * @param CCEnable This parameter can be one of the following values: + * @arg @ref LL_UCPD_CCENABLE_NONE + * @arg @ref LL_UCPD_CCENABLE_CC1 + * @arg @ref LL_UCPD_CCENABLE_CC2 + * @arg @ref LL_UCPD_CCENABLE_CC1CC2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable); +} + +/** + * @brief Set UCPD SNK role + * @rmtoll CR ANAMODE LL_UCPD_SetSNKRole + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE); +} + +/** + * @brief Set UCPD SRC role + * @rmtoll CR ANAMODE LL_UCPD_SetSRCRole + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE); +} + +/** + * @brief Get UCPD Role + * @rmtoll CR ANAMODE LL_UCPD_GetRole + * @param UCPDx UCPD Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_UCPD_ROLE_SNK + * @arg @ref LL_UCPD_ROLE_SRC + */ +__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx) +{ + return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE)); +} + +/** + * @brief Set Rp resistor + * @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor + * @param UCPDx UCPD Instance + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_UCPD_RESISTOR_DEFAULT + * @arg @ref LL_UCPD_RESISTOR_1_5A + * @arg @ref LL_UCPD_RESISTOR_3_0A + * @arg @ref LL_UCPD_RESISTOR_NONE + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor); +} + +/** + * @brief Set CC pin + * @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin + * @param UCPDx UCPD Instance + * @param CCPin This parameter can be one of the following values: + * @arg @ref LL_UCPD_CCPIN_CC1 + * @arg @ref LL_UCPD_CCPIN_CC2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin); +} + +/** + * @brief Rx enable + * @rmtoll CR PHYRXEN LL_UCPD_RxEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN); +} + +/** + * @brief Rx disable + * @rmtoll CR PHYRXEN LL_UCPD_RxDisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN); +} + +/** + * @brief Set Rx mode + * @rmtoll CR RXMODE LL_UCPD_SetRxMode + * @param UCPDx UCPD Instance + * @param RxMode This parameter can be one of the following values: + * @arg @ref LL_UCPD_RXMODE_NORMAL + * @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode); +} + +/** + * @brief Send Hard Reset + * @rmtoll CR TXHRST LL_UCPD_SendHardReset + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_TXHRST); +} + +/** + * @brief Send message + * @rmtoll CR TXSEND LL_UCPD_SendMessage + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CR, UCPD_CR_TXSEND); +} + +/** + * @brief Set Tx mode + * @rmtoll CR TXMODE LL_UCPD_SetTxMode + * @param UCPDx UCPD Instance + * @param TxMode This parameter can be one of the following values: + * @arg @ref LL_UCPD_TXMODE_NORMAL + * @arg @ref LL_UCPD_TXMODE_CABLE_RESET + * @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2 + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode) +{ + MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable FRS interrupt + * @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE); +} + +/** + * @brief Enable type c event on CC2 + * @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE); +} + +/** + * @brief Enable type c event on CC1 + * @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE); +} + +/** + * @brief Enable Rx message end interrupt + * @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE); +} + +/** + * @brief Enable Rx overrun interrupt + * @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE); +} + +/** + * @brief Enable Rx hard reset interrupt + * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE); +} + +/** + * @brief Enable Rx orderset interrupt + * @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE); +} + +/** + * @brief Enable Rx non empty interrupt + * @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE); +} + +/** + * @brief Enable TX underrun interrupt + * @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE); +} + +/** + * @brief Enable hard reset sent interrupt + * @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE); +} + +/** + * @brief Enable hard reset discard interrupt + * @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE); +} + +/** + * @brief Enable Tx message abort interrupt + * @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE); +} + +/** + * @brief Enable Tx message sent interrupt + * @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE); +} + +/** + * @brief Enable Tx message discarded interrupt + * @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE); +} + +/** + * @brief Enable Tx data receive interrupt + * @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE); +} + +/** + * @brief Disable FRS interrupt + * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE); +} + +/** + * @brief Disable type c event on CC2 + * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE); +} + +/** + * @brief Disable type c event on CC1 + * @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE); +} + +/** + * @brief Disable Rx message end interrupt + * @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE); +} + +/** + * @brief Disable Rx overrun interrupt + * @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE); +} + +/** + * @brief Disable Rx hard reset interrupt + * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE); +} + +/** + * @brief Disable Rx orderset interrupt + * @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE); +} + +/** + * @brief Disable Rx non empty interrupt + * @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE); +} + +/** + * @brief Disable TX underrun interrupt + * @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE); +} + +/** + * @brief Disable hard reset sent interrupt + * @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE); +} + +/** + * @brief Disable hard reset discard interrupt + * @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE); +} + +/** + * @brief Disable Tx message abort interrupt + * @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE); +} + +/** + * @brief Disable Tx message sent interrupt + * @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE); +} + +/** + * @brief Disable Tx message discarded interrupt + * @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE); +} + +/** + * @brief Disable Tx data receive interrupt + * @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE); +} + +/** + * @brief Check if FRS interrupt enabled + * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC2 enabled + * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC1 enabled + * @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end interrupt enabled + * @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx overrun interrupt enabled + * @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx hard reset interrupt enabled + * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx orderset interrupt enabled + * @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx non empty interrupt enabled + * @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if TX underrun interrupt enabled + * @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset sent interrupt enabled + * @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset discard interrupt enabled + * @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message abort interrupt enabled + * @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message sent interrupt enabled + * @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message discarded interrupt enabled + * @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx data receive interrupt enabled + * @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear + * @{ + */ + +/** + * @brief Clear FRS interrupt + * @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF); +} + +/** + * @brief Clear type c event on CC2 + * @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF); +} + +/** + * @brief Clear type c event on CC1 + * @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF); +} + +/** + * @brief Clear Rx message end interrupt + * @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF); +} + +/** + * @brief Clear Rx overrun interrupt + * @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF); +} + +/** + * @brief Clear Rx hard reset interrupt + * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF); +} + +/** + * @brief Clear Rx orderset interrupt + * @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF); +} + +/** + * @brief Clear TX underrun interrupt + * @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF); +} + +/** + * @brief Clear hard reset sent interrupt + * @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF); +} + +/** + * @brief Clear hard reset discard interrupt + * @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF); +} + +/** + * @brief Clear Tx message abort interrupt + * @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF); +} + +/** + * @brief Clear Tx message sent interrupt + * @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF); +} + +/** + * @brief Clear Tx message discarded interrupt + * @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if FRS Event Flag is active + * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC2 + * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL); +} + +/** + * @brief Check if type c event on CC1 + * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active + * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx overrun flag is active + * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx hard reset flag is active + * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx orderset flag is active + * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx non empty flag is active + * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL); +} + +/** + * @brief Check if TX underrun flag is active + * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset sent flag is active + * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL); +} + +/** + * @brief Check if hard reset discard flag is active + * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message abort flag is active + * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message sent flag is active + * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx message discarded flag is active + * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx data interrupt flag is active + * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL); +} + +/** + * @brief return the vstate value for CC2 + * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2 + * @param UCPDx UCPD Instance + * @retval val + */ +__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx) +{ + return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2; +} + +/** + * @brief return the vstate value for CC1 + * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1 + * @param UCPDx UCPD Instance + * @retval val + */ +__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx) +{ + return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1; +} + +/** + * @} + */ + + +/** @defgroup UCPD_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Rx DMA Enable + * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); +} + +/** + * @brief Rx DMA Disable + * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); +} + +/** + * @brief Tx DMA Enable + * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx) +{ + SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN); +} + +/** + * @brief Tx DMA Disable + * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable + * @param UCPDx UCPD Instance + * @retval None + */ +__STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx) +{ + CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup UCPD_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief write the orderset for Tx message + * @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet + * @param UCPDx UCPD Instance + * @param TxOrderSet one of the following value + * @arg @ref LL_UCPD_ORDERED_SET_SOP + * @arg @ref LL_UCPD_ORDERED_SET_SOP1 + * @arg @ref LL_UCPD_ORDERED_SET_SOP2 + * @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET + * @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET + * @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG + * @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG + * @retval None + */ +__STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet) +{ + WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet); +} + +/** + * @brief write the Tx paysize + * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize + * @param UCPDx UCPD Instance + * @param TxPaySize + * @retval None. + */ +__STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize) +{ + WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize); +} + +/** + * @brief Write data + * @rmtoll TXDR DR LL_UCPD_WriteData + * @param UCPDx UCPD Instance + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None. + */ +__STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data) +{ + WRITE_REG(UCPDx->TXDR, Data); +} + +/** + * @brief read RX the orderset + * @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet + * @param UCPDx UCPD Instance + * @retval RxOrderSet one of the following value + * @arg @ref LL_UCPD_RXORDSET_SOP + * @arg @ref LL_UCPD_RXORDSET_SOP1 + * @arg @ref LL_UCPD_RXORDSET_SOP2 + * @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG + * @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG + * @arg @ref LL_UCPD_RXORDSET_CABLE_RESET + * @arg @ref LL_UCPD_RXORDSET_SOPEXT1 + * @arg @ref LL_UCPD_RXORDSET_SOPEXT2 + */ +__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx) +{ + return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET); +} + +/** + * @brief Read the Rx paysize + * @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize + * @param UCPDx UCPD Instance + * @retval RXPaysize. + */ +__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) +{ + return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); +} + +/** + * @brief Read data + * @rmtoll RXDR RXDATA LL_UCPD_ReadData + * @param UCPDx UCPD Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx) +{ + return READ_REG(UCPDx->RXDR); +} + +/** + * @brief Set Rx OrderSet Ext1 + * @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1 + * @param UCPDx UCPD Instance + * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt) +{ + WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt); +} + +/** + * @brief Set Rx OrderSet Ext2 + * @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2 + * @param UCPDx UCPD Instance + * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) +{ + WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); +void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +#endif /* defined (UCPD1) */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_LL_UCPD_H */ + diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c new file mode 100644 index 0000000..5a2f75e --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c @@ -0,0 +1,376 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_dma.c + * @author MCD Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) + +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= 115U) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#if defined (DMA1_Channel8) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7) || \ + ((CHANNEL) == LL_DMA_CHANNEL_8))) || \ + (((INSTANCE) == DMA2) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7) || \ + ((CHANNEL) == LL_DMA_CHANNEL_8)))) +#elif defined (DMA1_Channel6) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6))) || \ + (((INSTANCE) == DMA2) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6)))) +#endif /* DMA1_Channel8 */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_ALL + * (*) Not on all G4 devices + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + DMA_Channel_TypeDef *tmp; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); + + if (Channel == LL_DMA_CHANNEL_ALL) + { + if (DMAx == DMA1) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + } + else if (DMAx == DMA2) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + } + else + { + status = ERROR; + } + } + else + { + tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Disable the selected DMAx_Channely */ + CLEAR_BIT(tmp->CCR, DMA_CCR_EN); + + /* Reset DMAx_Channely control register */ + WRITE_REG(tmp->CCR, 0U); + + /* Reset DMAx_Channely remaining bytes register */ + WRITE_REG(tmp->CNDTR, 0U); + + /* Reset DMAx_Channely peripheral address register */ + WRITE_REG(tmp->CPAR, 0U); + + /* Reset DMAx_Channely memory address register */ + WRITE_REG(tmp->CMAR, 0U); + + /* Reset Request register field for DMAx Channel */ + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM); + + if (Channel == LL_DMA_CHANNEL_1) + { + /* Reset interrupt pending bits for DMAx Channel1 */ + LL_DMA_ClearFlag_GI1(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_2) + { + /* Reset interrupt pending bits for DMAx Channel2 */ + LL_DMA_ClearFlag_GI2(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_3) + { + /* Reset interrupt pending bits for DMAx Channel3 */ + LL_DMA_ClearFlag_GI3(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_4) + { + /* Reset interrupt pending bits for DMAx Channel4 */ + LL_DMA_ClearFlag_GI4(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_5) + { + /* Reset interrupt pending bits for DMAx Channel5 */ + LL_DMA_ClearFlag_GI5(DMAx); + } + + else if (Channel == LL_DMA_CHANNEL_6) + { + /* Reset interrupt pending bits for DMAx Channel6 */ + LL_DMA_ClearFlag_GI6(DMAx); + } +#if defined (DMA1_Channel7) + else if (Channel == LL_DMA_CHANNEL_7) + { + /* Reset interrupt pending bits for DMAx Channel7 */ + LL_DMA_ClearFlag_GI7(DMAx); + } +#endif /* DMA1_Channel7 */ +#if defined (DMA1_Channel8) + else if (Channel == LL_DMA_CHANNEL_8) + { + /* Reset interrupt pending bits for DMAx Channel8 */ + LL_DMA_ClearFlag_GI8(DMAx); + } +#endif /* DMA1_Channel8 */ + else + { + status = ERROR; + } + } + + return (uint32_t)status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_8 (*) + * (*) Not on all G4 devices + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + + /*---------------------------- DMAx CCR Configuration ------------------------ + * Configure DMAx_Channely: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits + * - Mode: DMA_CCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits + * - Priority: DMA_CCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority); + + /*-------------------------- DMAx CMAR Configuration ------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx CPAR Configuration ------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx CNDTR Configuration ----------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_CNDTR_NDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); + + /*--------------------------- DMAMUXx CCR Configuration ---------------------- + * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter : + * - PeriphRequest: DMA_CxCR[7:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); + + return (uint32_t)SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = (uint32_t)0x00000000U; + DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c new file mode 100644 index 0000000..d1e1f46 --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c @@ -0,0 +1,296 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) +#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - 0x00: EXTI registers are de-initialized + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ + LL_EXTI_WriteReg(IMR1, 0x1F840000U); + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR1, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR1, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR1, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER1, 0x00000000U); + /* Pending register clear */ + LL_EXTI_WriteReg(PR1, 0x007DFFFFU); + + /* Interrupt mask register 2 set to default reset values */ +#if defined(LL_EXTI_LINE_32) && defined(LL_EXTI_LINE_33) && defined(LL_EXTI_LINE_35) && defined(LL_EXTI_LINE_42) + LL_EXTI_WriteReg(IMR2, 0x0000043CU); +#else + LL_EXTI_WriteReg(IMR2, 0x00000034U); +#endif /* LL_EXTI_LINE_xx */ + /* Event mask register 2 set to default reset values */ + LL_EXTI_WriteReg(EMR2, 0x00000000U); + /* Rising Trigger selection register 2 set to default reset values */ + LL_EXTI_WriteReg(RTSR2, 0x00000000U); + /* Falling Trigger selection register 2 set to default reset values */ + LL_EXTI_WriteReg(FTSR2, 0x00000000U); + /* Software interrupt event register 2 set to default reset values */ + LL_EXTI_WriteReg(SWIER2, 0x00000000U); + /* Pending register 2 clear */ + LL_EXTI_WriteReg(PR2, 0x00000078U); + + return 0x00u; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - 0x00: EXTI registers are initialized + * - any other value : wrong configuration + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t status = 0x00u; + + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Directly Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = 0x01u; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + /* Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status |= 0x02u; + break; + } + } + } + /* Configure EXTI Lines in range from 32 to 63 */ + if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT on provided Lines */ + LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); + /* Directly Enable IT on provided Lines */ + LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); + break; + default: + status |= 0x04u; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + /* Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + /* Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + default: + status |= 0x05u; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure IT EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* De-configure Event EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* De-configure IT EXTI Lines in range from 32 to 63 */ + LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); + /* De-configure Event EXTI Lines in range from 32 to 63 */ + LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + } + + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c new file mode 100644 index 0000000..ca24e5e --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c @@ -0,0 +1,270 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_gpio.h" +#include "stm32g4xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) + +/** @addtogroup GPIO_LL + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * LL_GPIO_Init + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 ) ||\ + ((__VALUE__) == LL_GPIO_AF_8 ) ||\ + ((__VALUE__) == LL_GPIO_AF_9 ) ||\ + ((__VALUE__) == LL_GPIO_AF_10 ) ||\ + ((__VALUE__) == LL_GPIO_AF_11 ) ||\ + ((__VALUE__) == LL_GPIO_AF_12 ) ||\ + ((__VALUE__) == LL_GPIO_AF_13 ) ||\ + ((__VALUE__) == LL_GPIO_AF_14 ) ||\ + ((__VALUE__) == LL_GPIO_AF_15 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC); + } + else if (GPIOx == GPIOD) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD); + } + else if (GPIOx == GPIOE) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE); + } + else if (GPIOx == GPIOF) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF); + } + else if (GPIOx == GPIOG) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos; + uint32_t currentpin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = POSITION_VAL(GPIO_InitStruct->Pin); + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos); + + if (currentpin != 0x00u) + { + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + } + pinpos++; + } + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_pwr.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_pwr.c new file mode 100644 index 0000000..4c900a4 --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_pwr.c @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_pwr.c + * @author MCD Application Team + * @brief PWR LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_bus.h" + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PWR_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the PWR registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PWR registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_PWR_DeInit(void) +{ + /* Force reset of PWR clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); + + /* Release reset of PWR clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); + + return SUCCESS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(PWR) */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c new file mode 100644 index 0000000..7ef1d51 --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c @@ -0,0 +1,1382 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_tim.c + * @author MCD Application Team + * @brief TIM LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_tim.h" +#include "stm32g4xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20) + +/** @addtogroup TIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup TIM_LL_Private_Macros + * @{ + */ +#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + +#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + +#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ + || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) + +#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + +#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + +#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + +#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + +#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + +#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + +#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2)) + +#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) + +#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + +#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_LL_Private_Functions TIM Private Functions + * @{ + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set TIMx registers to their reset values. + * @param TIMx Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: invalid TIMx instance + */ +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + + if (TIMx == TIM1) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + } + else if (TIMx == TIM2) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + } + else if (TIMx == TIM3) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + } + else if (TIMx == TIM4) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + } +#if defined(TIM5) + else if (TIMx == TIM5) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + } +#endif /* TIM5 */ + else if (TIMx == TIM6) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + } + else if (TIMx == TIM7) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + } + else if (TIMx == TIM8) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); + } + else if (TIMx == TIM15) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); + } + else if (TIMx == TIM16) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); + } + else if (TIMx == TIM17) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); + } +#if defined(TIM20) + else if (TIMx == TIM20) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20); + } +#endif /* TIM20 */ + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) + * @retval None + */ +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = (uint16_t)0x0000; + TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM_InitStruct->RepetitionCounter = 0x00000000U; +} + +/** + * @brief Configure the TIMx time base unit. + * @param TIMx Timer Instance + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + + tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + } + + /* Write to TIMx CR1 */ + LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + + /* Set the Autoreload value */ + LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + + /* Set the Prescaler value */ + LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + } + + /* Generate an update event to reload the Prescaler + and the repetition counter value (if applicable) immediately */ + LL_TIM_GenerateEvent_UPDATE(TIMx); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx output channel configuration data + * structure to their default values. + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) + * @retval None + */ +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->CompareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; +} + +/** + * @brief Configure the TIMx output channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = OC1Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = OC2Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = OC3Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = OC4Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH5: + result = OC5Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH6: + result = OC6Config(TIMx, TIM_OC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMx input channel configuration data + * structure to their default values. + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) + * @retval None + */ +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the TIMx input channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = IC1Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = IC2Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = IC3Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = IC4Config(TIMx, TIM_IC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Fills each TIM_EncoderInitStruct field with its default value + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) + * @retval None + */ +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + /* Set the default configuration */ + TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMx Timer Instance + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Configure TI1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + + /* Configure TI2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Set encoder mode */ + LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx Hall sensor interface configuration data + * structure to their default values. + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) + * @retval None + */ +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + /* Set the default configuration */ + TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_HallSensorInitStruct->CommutationDelay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @note TIMx slave mode controller is configured in reset mode. + Selected internal trigger is TI1F_ED. + * @note Channel 1 is configured as input, IC1 is mapped on TRC. + * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + * between 2 changes on the inputs. It gives information about motor speed. + * @note Channel 2 is configured in output PWM 2 mode. + * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + * @note OC2REF is selected as trigger output on TRGO. + * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used + * when TIMx operates in Hall sensor interface mode. + * @param TIMx Timer Instance + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + uint32_t tmpcr2; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx SMCR register value */ + tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcr2 |= TIM_CR2_TI1S; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcr2 |= LL_TIM_TRGO_OC2REF; + + /* Configure the slave mode controller */ + tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + tmpsmcr |= LL_TIM_TS_TI1F_ED; + tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + + /* Configure input channel 1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + + /* Configure input channel 2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx SMCR */ + LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + /* Write to TIMx CCR2 */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + + return SUCCESS; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; + TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * can be necessary to configure all of them during the first write access to + * the TIMx_BDTR register. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); + + if (IS_TIM_BKIN2_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); + assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode)); + + /* Set the BREAK2 input related BDTR bit-fields */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); + } + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_LL_Private_Functions TIM Private Functions + * @brief Private functions + * @{ + */ +/** + * @brief Configure the TIMx output channel 1. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 2. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 3. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 4. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 5. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC5E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); + + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 6. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC6E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 1. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC1P | TIM_CCER_CC1NP), + (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 2. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC2P | TIM_CCER_CC2NP), + ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 3. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 4. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC4E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC4P | TIM_CCER_CC4NP), + ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); + + return SUCCESS; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c new file mode 100644 index 0000000..1d3d841 --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_ucpd.c @@ -0,0 +1,169 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_ucpd.c + * @author MCD Application Team + * @brief UCPD LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_ucpd.h" +#include "stm32g4xx_ll_bus.h" +#include "stm32g4xx_ll_rcc.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ +#if defined (UCPD1) +/** @addtogroup UCPD_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UCPD_LL_Private_Constants UCPD Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UCPD_LL_Private_Macros UCPD Private Macros + * @{ + */ + + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UCPD_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UCPD_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the UCPD registers to their default reset values. + * @param UCPDx ucpd Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ucpd registers are de-initialized + * - ERROR: ucpd registers are not de-initialized + */ +ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); + + LL_UCPD_Disable(UCPDx); + + if (UCPD1 == UCPDx) + { + /* Force reset of ucpd clock */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1); + + /* Release reset of ucpd clock */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1); + + /* Disable ucpd clock */ + LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1); + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct. + * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled + * (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @param UCPDx UCPD Instance + * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains + * the configuration information for the UCPD peripheral. + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct) +{ + /* Check the ucpd Instance UCPDx*/ + assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); + + if (UCPD1 == UCPDx) + { + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1); + } + + + LL_UCPD_Disable(UCPDx); + + /*---------------------------- UCPDx CFG1 Configuration ------------------------*/ + MODIFY_REG(UCPDx->CFG1, + UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV, + UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin << UCPD_CFG1_TRANSWIN_Pos) | + (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_UCPD_InitTypeDef field to default value. + * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct) +{ + /* Set UCPD_InitStruct fields to default values */ + UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2; + UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */ + UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ + UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (UCPD1) */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c new file mode 100644 index 0000000..d971b05 --- /dev/null +++ b/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c @@ -0,0 +1,708 @@ +/** + ****************************************************************************** + * @file stm32g4xx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_utils.h" +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_system.h" +#include "stm32g4xx_ll_pwr.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32G4xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ +#define UTILS_MAX_FREQUENCY_SCALE1 170000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ + +/* Defines used for PLL range */ +#define UTILS_PLLVCO_INPUT_MIN 2660000U /*!< Frequency min for PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */ +#define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */ +#define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to HCLK Frequency */ +#define UTILS_SCALE1_LATENCY1_BOOST_FREQ 34000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_BOOST_FREQ 68000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_BOOST_FREQ 102000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_BOOST_FREQ 136000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_BOOST_FREQ 170000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ + +#define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 normal mode */ +#define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 normal mode */ + +#define UTILS_SCALE2_LATENCY1_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#define UTILS_SCALE2_LATENCY3_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + +#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_16)) + +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) + +#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_8)) + +#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) + +#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + tmpDelay = Delay; + /* Add a period to guaranty minimum wait */ + if(tmpDelay < LL_MAX_DELAY) + { + tmpDelay++; + } + + while (tmpDelay != 0U) + { + if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + tmpDelay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is + 170000000 Hz for STM32G4xx. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + + +----------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |----------------------------------------------------------| + | | voltage range 1 | voltage range 1 | voltage range 2 | + | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | + |-----------------|-------------------|-------------------|------------------| + |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 12 | + |-----------------|-------------------|-------------------|------------------| + |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 24 | + |-----------------|-------------------|-------------------|------------------| + |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | HCLK <= 26 | + |-----------------|-------------------|-------------------|------------------| + |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | + |-----------------|-------------------|-------------------|------------------| + |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | + +----------------------------------------------------------------------------+ + + + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLKFrequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) +{ + uint32_t timeout; + uint32_t getlatency; + ErrorStatus status = SUCCESS; + uint32_t regulatorstatus = LL_PWR_GetRegulVoltageScaling(); + uint32_t regulatorbooststatus = LL_PWR_IsEnabledRange1BoostMode(); + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 or greater than max clock */ + if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY5_BOOST_FREQ)) + { + status = ERROR; + } + else + { + if((regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE1) && (regulatorbooststatus == 1U)) + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY4_BOOST_FREQ) + { + /* 136 < HCLK <= 170 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_BOOST_FREQ) + { + /* 102 < HCLK <= 136 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_BOOST_FREQ) + { + /* 68 < HCLK <= 102 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_BOOST_FREQ) + { + /* 34 < HCLK <= 68 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + /* SCALE1 normal mode*/ + else if(regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + /* SCALE2 */ + else if(regulatorstatus == LL_PWR_REGU_VOLTAGE_SCALE2) + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 24 < HCLK <= 26 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 12 < HCLK <= 24 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + else + { + /* Nothing to do */ + } + + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2U; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0U)); + + if(getlatency != latency) + { + status = ERROR; + } + } + } + + return status; +} + +/** + * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR) + * - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSI frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLR: ensure that max frequency at 170000000 Hz is reach (PLLVCO_output / PLLR) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; + uint32_t pllfreq; + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; + + /* Check if one of the PLL is enabled */ + if(UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if(LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->PLLR); + + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; + } + } + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + + /* Apply definitive AHB prescaler value if necessary */ + if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if (status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } + } + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR) + * - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSE frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLR: ensure that max frequency at 170000000 Hz is reached (PLLVCO_output / PLLR) + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; + uint32_t pllfreq; + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if(UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if(LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if(HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->PLLR); + + /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ + if(pllfreq > 80000000U) + { + if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; + } + } + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + + /* Apply definitive AHB prescaler value if necessary */ + if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if (status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } + } + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ + +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR)); + + /* Check different PLL parameters according to RM */ + /* - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz. */ + pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); + + /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/ + pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + + /* - PLLR: ensure that max frequency at 170000000 Hz is reached */ + pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U); + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if(LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t hclk_frequency; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + + /* Calculate HCLK frequency */ + hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + + /* Increasing the number of wait states because of higher CPU frequency */ + if(SystemCoreClock < hclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update system clock configuration */ + if(status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + LL_RCC_PLL_EnableDomain_SYS(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(SystemCoreClock > hclk_frequency) + { + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update SystemCoreClock variable */ + if(status == SUCCESS) + { + LL_SetSystemCoreClock(hclk_frequency); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Core/LICENSE.txt b/Middlewares/ST/STM32_USBPD_Library/Core/LICENSE.txt new file mode 100644 index 0000000..e66295c --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Core/LICENSE.txt @@ -0,0 +1,86 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the SLA0044 license shall apply and are fully reproduced below: + +SLA0044 Rev5/February 2018 + +Software license agreement + +ULTIMATE LIBERTY SOFTWARE LICENSE AGREEMENT + +BY INSTALLING, COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE +OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS +INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES +(STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON +BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES +TO BE BOUND BY THIS SOFTWARE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights, the redistribution, +reproduction and use in source and binary forms of the software or any part +thereof, with or without modification, are permitted provided that the following +conditions are met: + +1. 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THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS, WHICH ARE +DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL +STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +11. EXCEPT AS EXPRESSLY PERMITTED HEREUNDER, NO LICENSE OR OTHER RIGHTS, WHETHER +EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY +RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. + diff --git a/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_core.h b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_core.h new file mode 100644 index 0000000..443bc47 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_core.h @@ -0,0 +1,1188 @@ +/** + ****************************************************************************** + * @file usbpd_core.h + * @author MCD Application Team + * @brief This file contains the core stack API. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef USBPD_CORE_H_ +#define USBPD_CORE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_def.h" +#if defined(USBPDCORE_TCPM_SUPPORT) +#include "tcpc.h" +#endif /* USBPDCORE_TCPM_SUPPORT */ + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_CORE + * @{ + */ + +/** @addtogroup USBPD_CORE_CAD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USBPD_CORE_CAD_Exported_Types USBPD CORE CAD Exported Types + * @{ + */ + +/** + * @brief function return value @ref USBPD_CORE_CAD + * @{ + */ +typedef enum +{ + USBPD_CAD_OK, /*!< USBPD CAD Status OK */ + USBPD_CAD_INVALID_PORT, /*!< USBPD CAD Status INVALID PORT */ + USBPD_CAD_ERROR, /*!< USBPD CAD Status ERROR */ + USBPD_CAD_MALLOCERROR, /*!< USBPD CAD Status ERROR MALLOC */ + USBPD_CAD_INVALIDRESISTOR /*!< USBPD CAD Status INVALID RESISTOR */ +} +USBPD_CAD_StatusTypeDef; +/** + * @} + */ + +/** + * @brief activation value @ref USBPD_CORE_CAD + * @{ + */ +typedef enum +{ + USBPD_CAD_DISABLE, /*!< USBPD CAD activation status Disable */ + USBPD_CAD_ENABLE /*!< USBPD CAD activation status Enable */ +} USBPD_CAD_activation; +/** + * @} + */ + +/** + * @brief CallBacks exposed by the @ref USBPD_CORE_CAD + */ +typedef struct +{ + /** + * @brief CallBack used to report events to DPM. + * @param PortNum The handle of the port + * @param State CAD state @ref USBPD_CAD_EVENT + * @param Cc The Communication Channel for the USBPD communication @ref CCxPin_TypeDef + * @retval None + */ + void (*USBPD_CAD_CallbackEvent)(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc); + /** + * @brief CallBack to wakeup the CAD. + * @retval None + */ + void (*USBPD_CAD_WakeUp)(void); +} USBPD_CAD_Callbacks; + +/** + * @} + */ + +/** @defgroup USBPD_CORE_CAD_Exported_Functions_Grp1 USBPD CORE CAD Exported Functions + * @{ + */ +/** + * @brief Initialize the CAD module for a specified port. + * @param PortNum Index of current used port + * @param CallbackFunctions CAD port callback function + * @param Settings Pointer on @ref USBPD_SettingsTypeDef structure + * @param Params Pointer on @ref USBPD_ParamsTypeDef structure + * @retval USBPD_CAD status + */ +USBPD_CAD_StatusTypeDef USBPD_CAD_Init(uint8_t PortNum, const USBPD_CAD_Callbacks *CallbackFunctions, + const USBPD_SettingsTypeDef *Settings, USBPD_ParamsTypeDef *Params); + +/** + * @brief function used to process type C state machine detection. + * @retval time (in ms) after which the process must be executed + */ +uint32_t USBPD_CAD_Process(void); + +/** + * @brief Enable or Disable CAD port. + * @param PortNum Index of current used port + * @param State The new state of the port @ref USBPD_CAD_activation + * @retval None + */ +void USBPD_CAD_PortEnable(uint8_t PortNum, USBPD_CAD_activation State); + +/** + * @brief Set the resistor to present a SNK. + * @param PortNum Index of current used port + * @retval None + */ +void USBPD_CAD_AssertRd(uint8_t PortNum); + +/** + * @brief Set the resistor to present a SRC. + * @param PortNum Index of current used port + * @retval None + */ +void USBPD_CAD_AssertRp(uint8_t PortNum); + +/** + * @brief Force type C state machine to enter recovery state + * @param PortNum Index of current used port + * @retval None + */ +void USBPD_CAD_EnterErrorRecovery(uint8_t PortNum); + +#if defined(USBPDCORE_DRP) || defined(USBPDCORE_SRC) +/** + * @brief Set the default Rd resistor (valid for SRC only) + * @param PortNum Index of current used port + * @param RdValue + * @retval USBPD_CAD_OK or USBPD_CAD_INVALIDRESISTOR + */ +USBPD_CAD_StatusTypeDef USBPD_CAD_SRC_SetRpResistor(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RdValue); + +/** @defgroup USBPD_CORE_CAD_Exported_Functions_Legacy USBPD CORE CAD Legacy Function + * @{ + */ +/* Keep for legacy reason */ +USBPD_CAD_StatusTypeDef USBPD_CAD_SetRpResistor(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RdValue); +/** + * @} + */ +#endif /* USBPDCORE_DRP || USBPDCORE_SRC */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USBPD_CORE_TRACE + * @{ + */ + +/** @defgroup USBPD_CORE_TRACE_Exported_Types USBPD CORE TRACE Exported Types + * @{ + */ +typedef enum +{ + USBPD_TRACE_FORMAT_TLV = 0, + USBPD_TRACE_MESSAGE_IN = 1, + USBPD_TRACE_MESSAGE_OUT = 2, + USBPD_TRACE_CADEVENT = 3, + USBPD_TRACE_PE_STATE = 4, + USBPD_TRACE_CAD_LOW = 5, + USBPD_TRACE_DEBUG = 6, + USBPD_TRACE_SRC = 7, + USBPD_TRACE_SNK = 8, + USBPD_TRACE_NOTIF = 9, + USBPD_TRACE_POWER = 10, + USBPD_TRACE_TCPM = 11, + USBPD_TRACE_PRL_STATE = 12, + USBPD_TRACE_PRL_EVENT = 13, + USBPD_TRACE_PHY_NOTFRWD = 14, + USBPD_TRACE_CPU = 15, + USBPD_TRACE_TIMEOUT = 16, + USBPD_TRACE_UCSI = 18 +} +TRACE_EVENT; + +typedef void (*TRACE_ENTRY_POINT)(TRACE_EVENT type, uint8_t port, uint8_t sop, uint8_t *ptr, uint32_t size); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USBPD_CORE_PE + * @{ + */ +/** @defgroup USBPD_CORE_PE_Private_Defines USBPD CORE PE Private Defines + * @brief These defines are used in the stack library. Just provided for information. + * Those timers values are not to be changed by user (changing values on user side, + * will not have any impacts on lib behavior). + * @{ + * + */ + +/* Policy Engine Timers */ +#ifdef USBPDCORE_PPS +#define PE_TPPSREQUEST 9000u /*!< tPPSRequest: Max value set to 10s */ +#define PE_TPPSTIMEOUT 14000u /*!< tPPSTimeout: min 12s to max 15s */ +#endif /* USBPDCORE_PPS */ +#define PE_TPSHARDRESET 27u /*!< tPSHardReset: min 25ms to max 30ms */ +#define PE_SRC_TSRCRECOVER 800u /*!< tSrcRecover for SRC: min 660 ms max 1s */ +#define PE_SNK_TSRCRECOVER 2000u /*!< tSrcRecover for SNK: 2s (less restrictive for SINK tests) */ +#define PE_SRC_TSAFE0V_T2 650u /*!< tSafe0V for SRC: 650 ms */ +#define PE_SNK_TSAFE0V_T2 1000u /*!< tSafe0V for SNK: 1000 ms */ +#define PE_TSRCTURNON_T4 275u /*!< tSrcTurnOn: 275 ms */ +#define PE_TPSSOURCEOFF 900u /*!< tPSSourceOff: min 750ms to max 920ms */ +#define PE_TPSSOURCEON 470u /*!< tPSSourceOn: min 390ms to max 480ms */ + +#define PE_TPSTRANSITION 500u /*!< tPSTransition: min 450ms to max 550ms */ + +#define PE_TSENDERRESPONSE 27u /*!< tSenderResponse: min 24ms to max 30ms */ + +#define PE_TTYPECSINKWAITCAP 500u /*!< tTypeCSinkWaitCap: min 310ms to max 620ms */ + +#define PE_TTYPECSENDSOURCECAPA 150u /*!< tTypeCSendSourceCap: min 100ms to max 200ms */ +#define PE_TSRCTRANSITION 30u /*!< tSrcTransition: min 25ms to max 35ms */ + +#define PE_TSWAPSRCSTART_MIN 20u /*!< tSwapSourceStart: 20 ms */ + +#define PE_TBISTCONTMODE 45u /*!< tBISTContMode: min 30ms to 60 ms */ +#if defined(USBPDCORE_VCONN_SUPPORT) +#define PE_TDISCOVERIDENTITY 45u /*!< tDiscoverIdentity: min 40ms to max 50ms */ +#endif /* USBPDCORE_VCONN_SUPPORT */ + +#define PE_TVDMSENDERRESPONSE 30u /*!< tVDMSenderResponse: min 24ms to max 30ms */ + +#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_ANSWER_DISCOIDENT) +#define PE_TVDMRECEIVERRESPONSE 15u /*!< tVDMReceiverResponse: max 15ms */ +#endif /* USBPDCORE_SVDM || USBPDCORE_ANSWER_DISCOIDENT */ +#if defined(USBPDCORE_SVDM) +#define PE_TVDMENTERMODE 25u /*!< tVDMEnterMode: max 25ms */ +#define PE_TVDMEXITMODE 25u /*!< tVDMExitMode: max 25ms */ +#endif /* USBPDCORE_SVDM */ + +#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_VCONN_SUPPORT) +#define PE_TVDMWAITMODEENTRY 50u /*!< tVDMWaitModeEntry: max 40ms to 50ms */ +#define PE_TVDMWAITMODEEXIT 50u /*!< tVDMWaitModeExit: max 40ms to 50ms */ +#endif /* USBPDCORE_SVDM || USBPDCORE_VCONN_SUPPORT */ + +#ifdef USBPDCORE_VCONN_SUPPORT +#define PE_TVCONNSOURCETIMEOUT 150u /*!< tVCONNSourceTimeout: min 100ms to max 200ms */ +#endif /* USBPDCORE_VCONN_SUPPORT */ + + +#define PE_TVCONNZERO 125u /*!< tVCONNZero :max 125ms */ +#define PE_TVCONNREAPPLIED 10u /*!< tVCONNZero :min 10 max 20ms */ +#define PE_TDATARESETFAIL 300u /*!< tDataResetFail :min 300ms */ +#define PE_TDATARESET 200u /*!< tDataReset :min 200ms 225ms max 250ms */ +/** + * @} + */ + +#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_UVDM) || defined(USBPDCORE_VCONN_SUPPORT) || defined(USBPDCORE_ANSWER_DISCOIDENT) +/** @defgroup USBPD_CORE_VDM_Exported_Callback USBPD CORE VDM Exported Callback + * @{ + */ + +/** + * @brief CallBacks exposed by the @ref USBPD_CORE_PE + * */ +typedef struct +{ +#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_VCONN_SUPPORT) || defined(USBPDCORE_ANSWER_DISCOIDENT) + /** + * @brief VDM Discovery identity callback + * @note Function is called to get Discovery identity information linked to the device and answer + * to SVDM Discovery identity init message sent by port partner + * @param PortNum current port number + * @param pIdentity Pointer on @ref USBPD_DiscoveryIdentity_TypeDef structure + * @retval USBPD status: @ref USBPD_ACK or @ref USBPD_BUSY + */ + USBPD_StatusTypeDef(*USBPD_VDM_DiscoverIdentity)(uint8_t PortNum, USBPD_DiscoveryIdentity_TypeDef *pIdentity); +#endif /* USBPDCORE_SVDM || USBPDCORE_VCONN_SUPPORT || USBPDCORE_ANSWER_DISCOIDENT */ + +#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_VCONN_SUPPORT) + /** + * @brief VDM Discover SVID callback + * @note Function is called to retrieve SVID supported by device and answer + * to SVDM Discovery SVID init message sent by port partner + * @param PortNum current port number + * @param p_SVID_Info Pointer on @ref USBPD_SVIDInfo_TypeDef structure + * @param pNbSVID Pointer on number of SVID + * @retval USBPD status @ref USBPD_BUSY or @ref USBPD_ACK or @ref USBPD_NAK + */ + USBPD_StatusTypeDef(*USBPD_VDM_DiscoverSVIDs)(uint8_t PortNum, uint16_t **p_SVID_Info, uint8_t *pNbSVID); + + /** + * @brief VDM Discover Mode callback (report all the modes supported by SVID) + * @note Function is called to report all the modes supported by selected SVID and answer + * to SVDM Discovery Mode init message sent by port partner + * @param PortNum current port number + * @param SVID SVID value + * @param p_ModeTab Pointer on the mode value + * @param NumberOfMode Number of mode available + * @retval USBPD status + */ + USBPD_StatusTypeDef(*USBPD_VDM_DiscoverModes)(uint8_t PortNum, + uint16_t SVID, uint32_t **p_ModeTab, uint8_t *NumberOfMode); + + /** + * @brief VDM Mode enter callback + * @note Function is called to check if device can enter in the mode received for the selected SVID in the + * SVDM enter mode init message sent by port partner + * @param PortNum current port number + * @param SVID SVID value + * @param ModeIndex Index of the mode to be entered + * @retval USBPD status @ref USBPD_ACK/@ref USBPD_NAK + */ + USBPD_StatusTypeDef(*USBPD_VDM_ModeEnter)(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); + + /** + * @brief VDM Mode exit callback + * @note Function is called to check if device can exit from the mode received for the selected SVID in the + * SVDM exit mode init message sent by port partner + * @param PortNum current port number + * @param SVID SVID value + * @param ModeIndex Index of the mode to be exited + * @retval USBPD status @ref USBPD_ACK/@ref USBPD_NAK + */ + USBPD_StatusTypeDef(*USBPD_VDM_ModeExit)(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); + + /** + * @brief Inform identity callback + * @note Function is called to save Identity information received in Discovery identity from port partner + (answer to SVDM discovery identity sent by device) + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param pIdentity Pointer on the discovery identity information based on @ref USBPD_DiscoveryIdentity_TypeDef + * @retval None + */ + void (*USBPD_VDM_InformIdentity)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_CommandType_Typedef CommandStatus, + USBPD_DiscoveryIdentity_TypeDef *pIdentity); + + /** + * @brief Inform SVID callback + * @note Function is called to save list of SVID received in Discovery SVID from port partner + (answer to SVDM discovery SVID sent by device) + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param pListSVID Pointer of list of SVID based on @ref USBPD_SVIDInfo_TypeDef + * @retval None + */ + void (*USBPD_VDM_InformSVID)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_SVIDInfo_TypeDef *pListSVID); + + /** + * @brief Inform Mode callback ( received in Discovery Modes ACK) + * @note Function is called to save list of modes linked to SVID received in Discovery mode from port partner + (answer to SVDM discovery mode sent by device) + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param pModesInfo Pointer of Modes info based on @ref USBPD_ModeInfo_TypeDef + * @retval None + */ + void (*USBPD_VDM_InformMode)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_ModeInfo_TypeDef *pModesInfo); + + /** + * @brief Inform Mode enter callback + * @note Function is called to inform if port partner accepted or not to enter in the mode + * specified in the SVDM enter mode sent by the device + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param SVID SVID ID + * @param ModeIndex Index of the mode to be entered + * @retval None + */ + void (*USBPD_VDM_InformModeEnter)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); + + /** + * @brief Inform Mode exit callback + * @note Function is called to inform if port partner accepted or not to exit from the mode + * specified in the SVDM exit mode sent by the device + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param SVID SVID ID + * @param ModeIndex Index of the mode to be exited + * @retval None + */ + void (*USBPD_VDM_InformModeExit)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); + + /** + * @brief Send VDM Attention message callback + * @note Function is called when device wants to send a SVDM attention message to port partner + * (for instance DP status can be filled through this function) + * @param PortNum current port number + * @param pNbData Pointer of number of VDO to send + * @param pVDO Pointer of VDO to send + * @retval None + */ + void (*USBPD_VDM_SendAttention)(uint8_t PortNum, uint8_t *pNbData, uint32_t *pVDO); + + /** + * @brief Receive VDM Attention callback + * @note Function is called when a SVDM attention init message has been received from port partner + * (for instance, save DP status data through this function) + * @param PortNum current port number + * @param NbData Number of received VDO + * @param VDO Received VDO + * @retval None + */ + void (*USBPD_VDM_ReceiveAttention)(uint8_t PortNum, uint8_t NbData, uint32_t VDO); + + /** + * @brief VDM Send Specific message callback + * @note Function is called when device wants to send a SVDM specific init message to port partner + * (for instance DP status or DP configure can be filled through this function) + * @param PortNum current port number + * @param SOPType SOP type + * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef + * @param pNbData Pointer of number of VDO to send + * @param pVDO Pointer of VDO to send + * @retval None + */ + void (*USBPD_VDM_SendSpecific)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO); + + /** + * @brief VDM Receive Specific message callback + * @note Function is called to answer to a SVDM specific init message received by port partner. + * (for instance, retrieve DP status or DP configure data through this function) + * @param PortNum Current port number + * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef + * @param pNbData Pointer of number of received VDO and used for the answer + * @param pVDO Pointer of received VDO and use for the answer + * @retval USBPD Status + */ + USBPD_StatusTypeDef(*USBPD_VDM_ReceiveSpecific)(uint8_t PortNum, + USBPD_VDM_Command_Typedef VDMCommand, + uint8_t *pNbData, uint32_t *pVDO); + + /** + * @brief VDM Specific message callback to inform user of reception of VDM specific message + * @note Function is called when answer from SVDM specific init message has been received by the device + * (for instance, save DP status and DP configure data through this function) + * @param PortNum current port number + * @param SOPType SOP type + * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef + * @param pNbData Pointer of number of received VDO + * @param pVDO Pointer of received VDO + * @retval None + */ + void (*USBPD_VDM_InformSpecific)(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO); + +#endif /* USBPDCORE_SVDM || USBPDCORE_VCONN_SUPPORT */ +#if defined(USBPDCORE_UVDM) + /** + * @brief VDM Send Unstructured message callback + * @param PortNum current port number + * @param pUVDM_Header Pointer on UVDM header based on @ref USBPD_UVDMHeader_TypeDef + * @param pNbData Pointer of number of VDO to send + * @param pVDO Pointer of VDO to send + * @retval None + */ + void (*USBPD_VDM_SendUVDM)(uint8_t PortNum, USBPD_UVDMHeader_TypeDef *pUVDM_Header, + uint8_t *pNbData, uint32_t *pVDO); + + /** + * @brief Unstructured VDM message callback to inform user of reception of UVDM message + * @param PortNum current port number + * @param UVDM_Header UVDM header based on @ref USBPD_UVDMHeader_TypeDef + * @param pNbData Pointer of number of received VDO + * @param pVDO Pointer of received VDO + * @retval USBPD Status + */ + USBPD_StatusTypeDef(*USBPD_VDM_ReceiveUVDM)(uint8_t PortNum, + USBPD_UVDMHeader_TypeDef UVDM_Header, uint8_t *pNbData, uint32_t *pVDO); +#endif /* USBPDCORE_UVDM */ +} USBPD_VDM_Callbacks; + +/** + * @} + */ + +#endif /* USBPDCORE_SVDM || USBPDCORE_UVDM || USBPDCORE_VCONN_SUPPORT || USBPDCORE_ANSWER_DISCOIDENT */ + +/** @defgroup USBPD_CORE_PE_Exported_TypesDefinitions USBPD CORE PE Exported Types Definitions + * @{ + */ + +/** @defgroup PE_CallBacks_structure_definition PE CallBacks structure definition + * @brief PE CallBacks exposed by the PE to the DPM + * @{ + */ +typedef struct +{ + /** + * @brief Callback used to request DPM to setup the new power level. + * @note this callback is mandatory for a SRC and DRP. + * @param PortNum Port number + * @retval Returned values are: @ref USBPD_ACCEPT, @ref USBPD_REJECT, @ref USBPD_WAIT + */ + USBPD_StatusTypeDef(*USBPD_PE_RequestSetupNewPower)(uint8_t PortNum); + + /** + * @brief Callback used to inform the DPM about the different HardReset step. + * @param PortNum Port number + * @param Role of the board @ref USBPD_PortPowerRole_TypeDef + * @param Status HR Status @ref USBPD_HR_Status_TypeDef + * @retval None + */ + void (*USBPD_PE_HardReset)(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_HR_Status_TypeDef Status); + + /** + * @brief Callback used to ask application the reply status for a power role swap request. + * @note if the callback is NULL, the request power role swap are automatically rejected. + * @param PortNum Port number + * @retval Returned values are: @ref USBPD_ACCEPT, @ref USBPD_WAIT, @ref USBPD_REJECT + */ + USBPD_StatusTypeDef(*USBPD_PE_EvaluatPRSwap)(uint8_t PortNum); + + /** + * @brief Callback used by the stack to notify an event. + * @note this callback is mandatory + * @param PortNum Port number + * @param EventVal @ref USBPD_NotifyEventValue_TypeDef + * @retval none + */ + void (*USBPD_PE_Notify)(uint8_t PortNum, USBPD_NotifyEventValue_TypeDef EventVal); + + /** + * @brief Callback used by the stack to inform DPM that an extended message has been received. + * @param PortNum port number value + * @param MsgId extended message id @ref USBPD_ExtendedMsg_TypeDef + * @param ptrData pointer on the data + * @param DataSize size of the data + * @retval None + */ + void (*USBPD_PE_ExtendedMessage)(uint8_t PortNum, + USBPD_ExtendedMsg_TypeDef MsgId, uint8_t *ptrData, uint16_t DataSize); + + /** + * @brief Callback used by the stack to get information from DPM or PWR_IF. + * @param PortNum Port number + * @param DataId Type of data to be read from DPM based on @ref USBPD_CORE_DataInfoType_TypeDef + * @param Ptr Pointer on address where DPM data should be written (u8 pointer) + * @param Size Pointer on nb of bytes written by DPM + * @retval None + */ + void (*USBPD_PE_GetDataInfo)(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t *Size); + + /** + * @brief Callback used by the stack to set information inside DPM or PWR_IF. + * @param PortNum Port number + * @param DataId Type of data to be read from DPM based on @ref USBPD_CORE_DataInfoType_TypeDef + * @param Ptr Pointer on address where DPM data to be updated could be read (u8 pointer) + * @param Size Nb of byte to be updated in DPM + * @retval None + */ + void (*USBPD_PE_SetDataInfo)(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t Size); + + /** + * @brief Callback used by a SOURCE to evaluate the SINK request + * @param PortNum Port number + * @param PtrPowerObject Pointer on the power data object + * @retval Returned values are: @ref USBPD_ACCEPT, @ref USBPD_REJECT, @ref USBPD_WAIT, @ref USBPD_GOTOMIN + */ + USBPD_StatusTypeDef(*USBPD_PE_SRC_EvaluateRequest)(uint8_t PortNum, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject); + + /** + * @brief Callback used by a sink to evaluate the Source Capabilities. + * @note the callback is used in the SNK and DRP context. + * @param PortNum Port number + * @param PtrRequestData Pointer on selected request data object + * @param PtrPowerObject Pointer on selected power data object + * @retval None + */ + void (*USBPD_PE_SNK_EvaluateCapabilities)(uint8_t PortNum, uint32_t *RequestData, + USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject); + + /** + * @brief Callback used during the different step of the power role swap + * @note see MSC documentation to get more detail + * @param PortNum Port number + * @param Role of the board @ref USBPD_PortPowerRole_TypeDef + * @param Status HR Status update @ref USBPD_PRS_Status_TypeDef + * @retval None + */ + void (*USBPD_PE_PowerRoleSwap)(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, + USBPD_PRS_Status_TypeDef Status); + + /** + * @brief Callback used to wakeup the current state machine + * @note this function is mandatory but has effect only in RTOS context + * @param PortNum Port number + * @retval None + */ + void (*USBPD_PE_WakeupCallback)(uint8_t PortNum); + + /** + * @brief Callback used to ask application the reply status for a Vconn swap request + * @param PortNum Port number + * @retval Returned values are: @ref USBPD_ACCEPT, @ref USBPD_REJECT, @ref USBPD_WAIT + */ + USBPD_StatusTypeDef(*USBPD_PE_EvaluateVconnSwap)(uint8_t PortNum); + + /** + * @brief Callback used to enable/disable the vconn power + * @note the function is mandatory to manage the VconnPower + * @param PortNum Port number + * @param State Enable or Disable VConn on CC lines + * @retval Returned values are: @ref USBPD_ACCEPT, @ref USBPD_REJECT + */ + USBPD_StatusTypeDef(*USBPD_PE_VconnPwr)(uint8_t PortNum, USBPD_FunctionalState State); + + /** + * @brief Callback used by PE to enter in error recovery state + * @param PortNum Port number + * @retval None + */ + void (*USBPD_PE_EnterErrorRecovery)(uint8_t PortNum); + + /** + * @brief Callback used to ask application the reply status for a DataRoleSwap request + * @note if the callback is not set (ie NULL) the stack will automatically reject the request + * @param PortNum Port number + * @retval Returned values are: + @ref USBPD_ACCEPT if DRS can be accepted + @ref USBPD_REJECT if DRS is not accepted in one data role (DFP or UFP) or in PD2.0 config + @ref USBPD_NOTSUPPORTED if DRS is not supported at all by the application (in both data roles) - P3.0 only + */ + USBPD_StatusTypeDef(*USBPD_PE_DataRoleSwap)(uint8_t PortNum); + + /** + * @brief Callback used to check the VBUS status + * @note this function is mandatory for a SNK port and used inside the hardreset process + * @param PortNum Port number + * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef + * @retval Returned values are: @ref USBPD_DISABLE or @ref USBPD_ENABLE + */ + USBPD_FunctionalState(*USBPD_PE_IsPowerReady)(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe); + + +} USBPD_PE_Callbacks; + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USBPD_CORE_PE_Exported_Functions USBPD CORE PE Exported Functions + * @{ + */ + +/** @defgroup USBPD_CORE_PE_Exported_Functions_Group1 USBPD CORE PE Exported Functions to DPM CORE + * @{ + */ +/** + * @brief Initialize Policy Engine layer for a Port + * @note the value pSettings and pParams shall be presistante because the stack keep there memory location + * @param PortNum Index of current used port + * @param pSettings Pointer on @ref USBPD_SettingsTypeDef structure + * @param pParams Pointer on @ref USBPD_ParamsTypeDef structure + * @param PECallbacks Callback function to be passed to PRL layer + * @retval USBPD status Possible values are + - @ref USBPD_OK + - @ref USBPD_ERROR + - @ref USPD_ERROR_CALLBACKMISSING + - @ref USBPD_INVALID_PORT_NUMBER + - @ref USBPD_MALLOCERROR + */ +USBPD_StatusTypeDef USBPD_PE_Init(uint8_t PortNum, USBPD_SettingsTypeDef *pSettings, USBPD_ParamsTypeDef *pParams, + const USBPD_PE_Callbacks *PECallbacks); + + +/** + * @brief Check coherence between lib selected and the lib include inside the project + * @note This function can be used only during development process to avoid mismatch + * @param LibId Value fix defined with the switch lib. + * @retval if the check is OK @ref USBPD_TRUE else @ref USBPD_FALSE + */ +uint32_t USBPD_PE_CheckLIB(uint32_t LibId); + +/** + * @brief Return the need of the stack in terms of dynamique allocation + * @note the value returned corresponds to the allocation need for 2 ports so if application manages + * only one port the need is be divided by 2 + * @retval Memory size + */ +uint32_t USBPD_PE_GetMemoryConsumption(void); + +/** + * @brief Set the trace pointer and the debug level + * @note the recommended value for debug trace level is 0x3 + * 0x1 : Policy engine state + * 0x2 : Notification + * 0x3 : Policy engine state + Notification + * @param Ptr function on trace + * @param Debug Trace debug level + * @retval None + */ +void USBPD_PE_SetTrace(TRACE_ENTRY_POINT Ptr, uint8_t Debug); + +/** + * @brief Notification function + * @note this function is used by DPM_CORE or the stack to inform the user DPM application + * @param PortNum Index of current used port + * @param EventVal event based on @ref USBPD_NotifyEventValue_TypeDef + * @retval None + */ +void USBPD_PE_Notification(uint8_t PortNum, USBPD_NotifyEventValue_TypeDef EventVal); + + + +#ifdef USBPDCORE_DRP +/** + * @brief Policy Engine DRP state machine + * @param PortNum Index of current used port + * @retval Timing in ms + */ +uint32_t USBPD_PE_StateMachine_DRP(uint8_t PortNum); +#endif /* USBPDCORE_DRP */ + +#if defined(USBPDCORE_VPD) && defined(USBPDCORE_SNK) +/** + * @brief Policy Engine SNK state machine supporting VPD + * @param PortNum Index of current used port + * @retval Timing in ms + */ +uint32_t USBPD_PE_StateMachine_SNKwVPD(uint8_t PortNum); +#endif /* USBPDCORE_VPD && USBPDCORE_SNK */ + +/** + * @brief Function called by DPM to before calling the state machine. + * @param PortNum Index of current used port + * @retval none + */ +void USBPD_PE_StateMachine_Reset(uint8_t PortNum); + +/** + * @brief Function called by DPM to exit the state machine. + * @param PortNum Index of current used port + * @retval none + */ +void USBPD_PE_StateMachine_Stop(uint8_t PortNum); + +/** + * @brief Function called by DPM to set the cable status connected or disconnected. + * @param PortNum Index of current used port + * @param IsConnected Cable connection status: 1 if connected and 0 is disconnected + * @retval USBPD status @ref USBPD_OK + * @note this function is obsolete the connection information are managed at cad level + */ +void USBPD_PE_IsCableConnected(uint8_t PortNum, uint8_t IsConnected); + +/** + * @brief Increment PE Timers tick + * @note This function must be called each elapsed ms + * @param PortNum Index of current used port + * @retval None + */ +void USBPD_PE_TimerCounter(uint8_t PortNum); + +/** + * @brief Update PE Timers tick + * @note This function must be called when exited the low power mode + * @param PortNum Index of current used port + * @param Tick value in ms (can't execed the value 0x.... else the value will not be take into account) + * @retval None + */ +void USBPD_PE_TimerCounteUpdate(uint8_t PortNum, uint16_t Tick); + +/** + * @} + */ + +#if defined(USBPDCORE_SRC) || defined(USBPDCORE_DRP) +/** @defgroup USBPD_CORE_SRC_Exported_Functions_Group1 USBPD CORE PE SRC Exported Functions to DPM CORE + * @{ + */ +/** + * @brief Policy Engine Source state machine + * @param PortNum Index of current used port + * @retval Timing in ms + */ +uint32_t USBPD_PE_StateMachine_SRC(uint8_t PortNum); + +/** + * @} + */ +#endif /* USBPDCORE_SRC || USBPDCORE_DRP */ + +#if defined(USBPDCORE_SNK) || defined(USBPDCORE_DRP) +/** @defgroup USBPD_CORE_PE_SNK_Exported_Functions_Group1 USBPD CORE PE SNK Exported Functions to DPM CORE + * @{ + */ +/** + * @brief Policy Engine Sink state machine + * @param PortNum Index of current used port + * @retval Timing in ms + */ +uint32_t USBPD_PE_StateMachine_SNK(uint8_t PortNum); + +/** + * @} + */ +#endif /* USBPDCORE_SNK || USBPDCORE_DRP */ + +#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_UVDM) || defined(USBPDCORE_VCONN_SUPPORT) || defined(USBPDCORE_ANSWER_DISCOIDENT) +/** @defgroup USBPD_CORE_PE_Exported_Functions_Group2 USBPD CORE PE Exported Functions to VDM USER + * @{ + */ +/** + * @brief Initialize VDM callback functions in PE + * @param PortNum Index of current used port + * @param VDMCallbacks Pointer on VDM callbacks based on @ref USBPD_VDM_Callbacks + * @retval None + */ +void USBPD_PE_InitVDM_Callback(uint8_t PortNum, USBPD_VDM_Callbacks *VDMCallbacks); +/** + * @} + */ +#endif /* USBPDCORE_SVDM || USBPDCORE_UVDM || USBPDCORE_VCONN_SUPPORT || USBPDCORE_ANSWER_DISCOIDENT */ + +/** @defgroup USBPD_CORE_PE_Exported_Functions_Group3 USBPD CORE PE Exported Functions to DPM USER + * @{ + */ + +/** + * @brief This generic function to send a control message + * @param PortNum Index of current used port + * @param CtrlMsg Control message id @ref USBPD_ControlMsg_TypeDef + * @param SOPType SOP Type based on @ref USBPD_SOPType_TypeDef + * @retval status @ref USBPD_OK, @ref USBPD_BUSY, @ref USBPD_ERROR or @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_Request_CtrlMessage(uint8_t PortNum, USBPD_ControlMsg_TypeDef CtrlMsg, + USBPD_SOPType_TypeDef SOPType); + +/** + * @brief This generic function is used to send data message + * @note the parameter pData is used only if DataMsg is equal + to USBPD_DATAMSG_ALERT or USBPD_DATAMSG_GET_COUNTRY_INFO + * @param PortNum Index of current used port + * @param DataMsg Data message id based on @ref USBPD_DataMsg_TypeDef + * @param pData Pointer on the data to send + * @retval status @ref USBPD_OK, @ref USBPD_BUSY, @ref USBPD_ERROR or @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_Request_DataMessage(uint8_t PortNum, USBPD_DataMsg_TypeDef DataMsg, uint32_t *pData); + +/** + * @brief This function is used to force PE to perform an Hard Reset. + * @param PortNum Index of current used port + * @retval status @ref USBPD_OK + */ +USBPD_StatusTypeDef USBPD_PE_Request_HardReset(uint8_t PortNum); + +/** + * @brief Request the PE to send a cable reset. + * @note Only a DFP Shall generate Cable Reset Signaling. + A DFP Shall only generate Cable Reset Signaling within an Explicit Contract. + The DFP has to be supplying VCONN prior to a Cable Reset + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_PE_Request_CableReset(uint8_t PortNum); + +#if defined(USBPDCORE_SNK) || defined(USBPDCORE_DRP) +/** + * @brief This function request PE to send a request message + * @param PortNum Index of current used port + * @param Rdo Requested data object + * @param PWobject Power Object + * @retval status @ref USBPD_OK, @ref USBPD_BUSY, @ref USBPD_ERROR or @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_Send_Request(uint8_t PortNum, uint32_t Rdo, USBPD_CORE_PDO_Type_TypeDef PWobject); +#endif /* USBPDCORE_SNK || USBPDCORE_DRP */ + +#if defined(USBPD_REV30_SUPPORT) +#if defined(USBPDCORE_BATTERY) || defined(USBPDCORE_MANU_INFO) || \ + defined(USBPDCORE_SECURITY_MSG) || defined(USBPDCORE_FWUPD) +/** + * @brief This function send an extended message + * @note The management of chunk or unchunked message is manage inside the + * @param PortNum Port number value + * @param SOPType Message type based on @ref USBPD_SOPType_TypeDef + * @param MessageType Extended Msg type @ref USBPD_ExtendedMsg_TypeDef + * @param Ptrdata Data pointer to PRL layer + * @param DataSize Size of the data (<= 260) + * @retval status @ref USBPD_OK, @ref USBPD_BUSY, @ref USBPD_ERROR or @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_SendExtendedMessage(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_ExtendedMsg_TypeDef MessageType, + uint8_t *Ptrdata, uint16_t DataSize); +#endif /* USBPDCORE_BATTERY || USBPDCORE_MANU_INFO || USBPDCORE_SECURITY_MSG || USBPDCORE_FWUPD */ + +#if defined(USBPDCORE_FASTROLESWAP) +/** + * @brief this function request PE to perform an FRS signalling. + * @param PortNum + * @retval None + */ +void USBPD_PE_ExecFastRoleSwapSignalling(uint8_t PortNum); +#endif /* USBPDCORE_FASTROLESWAP */ +#endif /* USBPD_REV30_SUPPORT */ + +#if defined(USBPDCORE_SVDM) || defined(USBPDCORE_VCONN_SUPPORT) +/** + * @brief Called by DPM to request the PE to perform a VDM identity request. + * @note On PD2.0, SVDM Identity cannot be sent by UFP. + * @param PortNum Index of current used port + * @param SOPType SOP Type (Only SOP or SOP') + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PE_SVDM_RequestIdentity(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); + +/** + * @brief Called by DPM to request the PE to perform a VDM SVID request. + * @param PortNum Index of current used port + * @param SOPType SOP Type (only valid for SOP or SOP') + * @retval USBPD status: @ref USBPD_BUSY, @ref USBPD_OK, @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_SVDM_RequestSVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); + +/** + * @brief Called by DPM to request the PE to perform a VDM Discovery mode message on one SVID. + * @param PortNum Index of current used port + * @param SOPType SOP Type + * @param SVID SVID used for discovery mode message + * @retval USBPD status: @ref USBPD_BUSY, @ref USBPD_OK, @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_SVDM_RequestMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID); + +/** + * @brief Called by DPM to request the PE to perform a VDM Discovery mode message on one SVID. + * @param PortNum Index of current used port + * @param SOPType SOP Type + * @param SVID SVID used for discovery mode message + * @param ModeIndex Index of the mode to be entered + * @retval USBPD status: @ref USBPD_BUSY, @ref USBPD_OK, @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_SVDM_RequestModeEnter(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, + uint8_t ModeIndex); + +/** + * @brief Called by DPM to request the PE to perform a VDM mode exit. + * @param PortNum Index of current used port + * @param SOPType SOP Type + * @param SVID SVID used for discovery mode message + * @param ModeIndex Index of the mode to be exit + * @retval USBPD status: @ref USBPD_BUSY, @ref USBPD_OK, @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_SVDM_RequestModeExit(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, + uint8_t ModeIndex); + +/** + * @brief Called by DPM to request the PE to send a specific SVDM message. + * @param PortNum Index of current used port + * @param SOPType Received message type based on @ref USBPD_SOPType_TypeDef + * @param Command VDM command based on @ref USBPD_VDM_Command_Typedef + * @param SVID Used SVID + * @retval USBPD status: @ref USBPD_BUSY, @ref USBPD_OK, @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_SVDM_RequestSpecific(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, + USBPD_VDM_Command_Typedef Command, uint16_t SVID); +#endif /* USBPDCORE_SVDM || USBPDCORE_VCONN_SUPPORT */ + +#if defined(USBPDCORE_SVDM) +/** + * @brief Called by DPM to request the PE to perform a VDM Attention. + * @param PortNum Index of current used port + * @param SOPType Received message type based on @ref USBPD_SOPType_TypeDef (valid with SOP only) + * @param SVID Used SVID + * @retval USBPD status: @ref USBPD_BUSY, @ref USBPD_OK, @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_SVDM_RequestAttention(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID); +#endif /* USBPDCORE_SVDM */ + +#if defined(USBPDCORE_UVDM) +/** + * @brief Called by DPM to request the PE to send a UVDM message. + * @param PortNum Index of current used port + * @param SOPType Received message type based on @ref USBPD_SOPType_TypeDef + * @retval USBPD status: @ref USBPD_BUSY, @ref USBPD_OK, @ref USBPD_FAIL + */ +USBPD_StatusTypeDef USBPD_PE_UVDM_RequestMessage(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); +#endif /* USBPDCORE_UVDM */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USBPD_CORE_PRL + * @{ + */ + +/** @defgroup USBPD_CORE_PRL_Exported_Functions USBPD CORE PRL Exported Functions + * @{ + */ + +/** @defgroup USBPD_CORE_PRL_Exported_Functions_Group1 USBPD CORE PRL Interface function for timer + * @{ + */ + +/** + * @brief Decrement The PRL Timers values + * @param PortNum port number value + * @retval None + */ +void USBPD_PRL_TimerCounter(uint8_t PortNum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#if defined(USBPDCORE_TCPM_SUPPORT) +/** @addtogroup USBPD_CORE_TCPM + * @{ + */ + +/** @defgroup USBPD_CORE_TCPM_Exported_Functions USBPD CORE TCPM Exported Functions + * @{ + */ + +/** @defgroup USBPD_CORE_TCPM_Exported_Functions_Grp1 USBPD CORE TCPM Exported Functions to DPM and PWR_IF applications + * @{ + */ + +/** + * @brief Initialize TCPC devices + * @param PortNum Port number value + * @param TCPC_ToggleRole Indication if TCPC should perform a role toggle or not + * @param Params Pointer on PE parameters based on @ref USBPD_ParamsTypeDef + * @param CallbackFunctions Pointer on CAD callbacks + * @param TCPC_Driver Pointer on TCPC drivers based on @ref TCPC_DrvTypeDef + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_HWInit(uint8_t PortNum, uint8_t TCPC_ToggleRole, USBPD_ParamsTypeDef *Params, + USBPD_CAD_Callbacks *CallbackFunctions, TCPC_DrvTypeDef *TCPC_Driver); + +/** + * @brief Set CC line for PD connection + * @param PortNum Port number value + * @param Pull Power role can be one of the following values: + * @arg @ref TYPEC_CC_RA + * @arg @ref TYPEC_CC_RP + * @arg @ref TYPEC_CC_RD + * @arg @ref TYPEC_CC_OPEN + * @param State Activation or deactivation of connection + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_set_cc(uint32_t PortNum, TCPC_CC_Pull_TypeDef Pull, USBPD_FunctionalState State); + +/** + * @brief Enable or disable VCONN + * @param PortNum Port number value + * @param State Activation or deactivation of VCONN + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_set_vconn(uint32_t PortNum, USBPD_FunctionalState State); + +/** + * @brief Enable VBUS + * @param PortNum The port handle. + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_VBUS_Enable(uint32_t PortNum); + +/** + * @brief Disable VBUS + * @param PortNum The port handle. + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_VBUS_Disable(uint32_t PortNum); + +/** + * @brief Get VBUS voltage + * @param PortNum The port handle. + * @retval VBUS value in mV + */ +uint16_t USBPD_TCPM_VBUS_GetVoltage(uint32_t PortNum); + +/** + * @brief Retrieve the VBUS VSafe0 status for a specified port. + * @param PortNum The port handle. + * @retval USBPD_StatusTypeDef + */ +USBPD_StatusTypeDef USBPD_TCPM_VBUS_IsVsafe0V(uint32_t PortNum); + +/** + * @brief Retrieve the VBUS Vsafe5V status for a specified port. + * @param PortNum The port handle. + * @retval USBPD_StatusTypeDef + */ +USBPD_StatusTypeDef USBPD_TCPM_VBUS_IsVsafe5V(uint32_t PortNum); + +/** + * @brief Management of ALERT + * @param Event Event reported by application + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_alert(uint32_t Event); + +/** + * @brief Force type C state machine to enter recovery state + * @param PortNum Index of current used port + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_EnterErrorRecovery(uint32_t PortNum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* USBPDCORE_TCPM_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* USBPD_CORE_H_ */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_def.h b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_def.h new file mode 100644 index 0000000..221e82f --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_def.h @@ -0,0 +1,3470 @@ +/** + ****************************************************************************** + * @file usbpd_def.h + * @author MCD Application Team + * @brief Global defines for USB-PD library + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef USBPD_DEF_H_ +#define USBPD_DEF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "cmsis_compiler.h" + +#include +#include + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_CORE + * @{ + */ + +/** @addtogroup USBPD_CORE_DEF + * @{ + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USBPD_CORE_DEF_Exported_Macros USBPD CORE DEF Exported Macros + * @{ + */ +/** + * @brief Compare two variables and return the smallest + * @param __VAR1__ First variable to be compared + * @param __VAR2__ Second variable to be compared + * @retval Returns the smallest variable + */ +#define USBPD_MIN(__VAR1__, __VAR2__) (((__VAR1__) > (__VAR2__))?(__VAR2__):(__VAR1__)) + +/** + * @brief Compare two variables and return the biggest + * @param __VAR1__ First variable to be compared + * @param __VAR2__ Second variable to be compared + * @retval Returns the biggest variable + */ +#define USBPD_MAX(__VAR1__, __VAR2__) (((__VAR1__) < (__VAR2__))?(__VAR2__):(__VAR1__)) + +/** + * @brief Check if the requested voltage is valid + * @param __MV__ Requested voltage in mV units + * @param __MAXMV__ Max Requested voltage in mV units + * @param __MINMV__ Min Requested voltage in mV units + * @retval 1 if valid voltage else 0 + */ +#define USBPD_IS_VALID_VOLTAGE(__MV__, __MAXMV__, __MINMV__) ((((__MV__) <= (__MAXMV__))\ + && ((__MV__) >= (__MINMV__)))? 1U: 0U) + +#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1u)) / (y)) +#define MV2ADC(__X__) ( (__X__*4095) / 3300 ) +#define ADC2MV(__X__) ( (__X__*3300) / 4095 ) + +/* Macros for integer division with various rounding variants default integer + division rounds down. */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) + +#define USBPD_WRITE32(addr,data) \ + do { \ + uint8_t bindex; \ + for(bindex = 0u; bindex < 4u; bindex++) \ + { \ + ((uint8_t *)addr)[bindex] = ((uint8_t)(data >> (8U * bindex)) & 0x000000FFU);\ + } \ + } while(0u); + +#define USPBPD_WRITE32 USBPD_WRITE32 /* For legacy purpose */ + +#define USBPD_LE16(addr) (((uint16_t)(*((uint8_t *)(addr))))\ + + (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define USBPD_LE32(addr) ((((uint32_t)(*(((uint8_t *)(addr)) + 0U))) + \ + (((uint32_t)(*(((uint8_t *)(addr)) + 1U))) << 8U) + \ + (((uint32_t)(*(((uint8_t *)(addr)) + 2U))) << 16U)+ \ + (((uint32_t)(*(((uint8_t *)(addr)) + 3U))) << 24U))) + +/** + * @} + */ + +/* Exported defines --------------------------------------------------------*/ +/** @defgroup USBPD_CORE_DEF_Exported_Defines USBPD CORE DEF Exported Defines + * @{ + */ +#define USBPD_TRUE 1U +#define USBPD_FALSE 0U + +/** @defgroup USBPD_CORE_DEF_Exported_Defines_Swiches USBPD Compilations switches + * @brief List of compilation switches which can be used to reduce size of the CORE library + * @{ + */ +#if defined(USBPDCORE_LIB_PD3_CONFIG_3) +#define USBPDCORE_BIST +#define USBPDCORE_GIVESNKCAP +#define USBPDCORE_GETSRCCAP +#define USBPDCORE_ERROR_RECOVERY +#define USBPDCORE_SNK +#define USBPDCORE_SNK_CAPA_EXT +#define USBPD_REV30_SUPPORT +#define USBPDCORE_PECABLE +#define USBPDCORE_PPS +#define USBPDCORE_SVDM +#define USBPDCORE_UVDM +#elif defined(USBPDCORE_LIB_NO_PD) +#define USBPDCORE_NOPD +#else +/* Default Switch */ +#define USBPDCORE_GOTOMIN +#define USBPDCORE_BIST +#define USBPDCORE_GETSNKCAP +#define USBPDCORE_GETSRCCAP +#define USBPDCORE_GIVESNKCAP +#define USBPDCORE_ERROR_RECOVERY + +#if defined(USBPDCORE_LIB_PD3_FULL) || defined(USBPDCORE_LIB_PD3_CONFIG_1) || defined(USBPD_TCPM_LIB_PD3_FULL) || \ + defined(USBPD_TCPM_LIB_PD3_CONFIG_1) || defined(USBPDCORE_LIB_PD3_CONFIG_MINSRC) || \ + defined(USBPDCORE_LIB_PD3_CONFIG_MINSNK) || defined(USBPDCORE_LIB_PD3_CONFIG_MINDRP) + +/* + USBPDCORE_LIB_PD3_FULL + USBPDCORE_LIB_PD3_CONFIG_1 : NO VDM + USBPDCORE_LIB_PD3_CONFIG_MINSRC : ONLY SRC & VCONN and NO option + USBPDCORE_LIB_PD3_CONFIG_MINSNK : ONLY SNK, and NO option + USBPDCORE_LIB_PD3_CONFIG_MINDRP : SRC + SNK + VCONN, and NO option + USBPD_TCPM_LIB_PD3_FULL : PD3.0 TCPM FULL + USBPD_TCPM_LIB_PD3_CONFIG_1 : PD3.0 TCPM FULL without VDM +*/ +#define USBPD_REV30_SUPPORT + +#if !defined(USBPDCORE_LIB_PD3_CONFIG_MINSNK) +#define USBPDCORE_SRC +#define USBPDCORE_VCONN_SUPPORT +#define USBPDCORE_ANSWER_DISCOIDENT +#endif /* USBPDCORE_LIB_PD3_CONFIG_MINSNK */ + +#if !defined(USBPDCORE_LIB_PD3_CONFIG_MINSRC) +#define USBPDCORE_SNK +#define USBPDCORE_SNK_CAPA_EXT +#endif /* USBPDCORE_LIB_PD3_CONFIG_MINSRC */ + +#if defined(USBPDCORE_LIB_PD3_FULL) || defined(USBPD_TCPM_LIB_PD3_FULL) +#define USBPDCORE_SVDM +#endif /* USBPDCORE_LIB_PD3_FULL || USBPD_TCPM_LIB_PD3_FULL */ + +#if defined(USBPDCORE_LIB_PD3_CONFIG_MINSNK)||defined(USBPDCORE_LIB_PD3_CONFIG_MINSRC) +#else +#define USBPDCORE_DRP +#define USBPDCORE_DATA_SWAP +#if !defined(USBPDCORE_LIB_PD3_CONFIG_MINDRP) +#define USBPDCORE_UVDM +#define USBPDCORE_FASTROLESWAP +#define USBPDCORE_PPS +#define USBPDCORE_ALERT +#define USBPDCORE_SRC_CAPA_EXT +#define USBPDCORE_STATUS +#define USBPDCORE_BATTERY +#define USBPDCORE_MANU_INFO +#define USBPDCORE_SECURITY_MSG +#define USBPDCORE_FWUPD +#define USBPDCORE_COUNTRY_MSG +#define USBPDCORE_PING_SUPPORT +#endif /* !USBPDCORE_LIB_PD3_CONFIG_MINDRP */ +#endif /* USBPDCORE_LIB_PD3_CONFIG_MINSNK || USBPDCORE_LIB_PD3_CONFIG_MINSRC */ + +#if defined(USBPD_TCPM_LIB_PD3_FULL) || defined(USBPD_TCPM_LIB_PD3_CONFIG_1) +#define USBPDCORE_TCPM_SUPPORT +#endif /* TCPM */ + +#endif /* PD3.0 */ + +/* List of compilation switches which can be used to reduce size of the CORE library */ +#if defined(USBPDCORE_LIB_PD2_FULL) || defined(USBPDCORE_LIB_PD2_CONFIG_1) || \ + defined(USBPDCORE_LIB_PD2_CONFIG_MINSRC) || defined(USBPDCORE_LIB_PD2_CONFIG_MINSNK) || \ + defined(USBPD_TCPM_LIB_PD2_FULL) || defined(USBPD_TCPM_LIB_PD2_CONFIG_1) || defined(USBPD_TCPM_LIB_PD2_MINSRC) || \ + defined(USBPD_TCPM_LIB_PD2_MINSNK) +/* + USBPDCORE_LIB_PD2_FULL + USBPDCORE_LIB_PD2_CONFIG_1 : NO VDM + USBPDCORE_LIB_PD2_CONFIG_MINSRC : ONLY SRC & VCONN and NO option + USBPDCORE_LIB_PD2_CONFIG_MINSNK : ONLY SNK, and NO option + USBPD_TCPM_LIB_PD2_FULL : PD2.0 TCPM FULL + USBPD_TCPM_LIB_PD2_CONFIG_1 : PD2.0 TCPM FULL without VDM + USBPD_TCPM_LIB_PD2_MINSRC : PD2.0 TCPM Only SRC + USBPD_TCPM_LIB_PD2_MINSNK : PD2.0 TCPM Only SNK +*/ +#define USBPD_REV20_SUPPORT + +#if !defined(USBPDCORE_LIB_PD2_CONFIG_MINSNK) && !defined(USBPD_TCPM_LIB_PD2_MINSNK) +#define USBPDCORE_SRC +#define USBPDCORE_VCONN_SUPPORT +#endif /* !defined(USBPDCORE_LIB_PD2_CONFIG_MINSNK) && !defined(USBPD_TCPM_LIB_PD2_MINSNK) */ + +#if !defined(USBPDCORE_LIB_PD2_CONFIG_MINSRC) && !defined(USBPD_TCPM_LIB_PD2_MINSRC) +#define USBPDCORE_SNK +#endif /* !defined(USBPDCORE_LIB_PD2_CONFIG_MINSRC) && !defined(USBPD_TCPM_LIB_PD2_MINSRC)*/ + +#if defined(USBPDCORE_LIB_PD2_CONFIG_MINSRC) || defined(USBPDCORE_LIB_PD2_CONFIG_MINSNK) || \ + defined(USBPD_TCPM_LIB_PD2_MINSRC) || defined(USBPD_TCPM_LIB_PD2_MINSNK) +#else +#define USBPDCORE_DRP +#define USBPDCORE_DATA_SWAP +#define USBPDCORE_UVDM +#endif /* USBPDCORE_LIB_PD2_CONFIG_MINSRC || USBPDCORE_LIB_PD2_CONFIG_MINSNK || + USBPD_TCPM_LIB_PD2_MINSRC || USBPD_TCPM_LIB_PD2_MINSNK */ + +#if defined(USBPDCORE_LIB_PD2_FULL) || defined(USBPD_TCPM_LIB_PD2_FULL) +#define USBPDCORE_SVDM +#endif /* USBPDCORE_LIB_PD3_FULL || USBPD_TCPM_LIB_PD2_FULL */ + +#if defined(USBPD_TCPM_LIB_PD2_FULL) || defined(USBPD_TCPM_LIB_PD2_CONFIG_1) || defined(USBPD_TCPM_LIB_PD2_MINSRC) || \ + defined(USBPD_TCPM_LIB_PD2_MINSNK) +#define USBPDCORE_TCPM_SUPPORT +#endif /* TCPM */ + +#endif /* PD2.0 */ + +#if defined(USBPDCORE_LIB_PD3_CONFIG_2) +#undef USBPDCORE_GOTOMIN +#undef USBPDCORE_BIST +#undef USBPDCORE_GETSNKCAP +#undef USBPDCORE_GETSRCCAP +#undef USBPDCORE_GIVESNKCAP +#undef USBPDCORE_SNK_CAPA_EXT + +#define USBPDCORE_SNK +#define USBPD_REV30_SUPPORT +#define USBPDCORE_FWUPD +#define USBPDCORE_UVDM +#endif /* USBPDCORE_LIB_PD3_CONFIG_2 */ + +/* No need to enable USBPDCORE_UNCHUNCKED_MODE + if FW Update et Security messages are not supported by the configuration */ +#if defined(USBPDCORE_SECURITY_MSG) || defined(USBPDCORE_FWUPD) +#define USBPDCORE_UNCHUNCKED_MODE +#endif /* USBPDCORE_SECURITY_MSG || USBPDCORE_FWUPD */ + +#endif /* USBPDCORE_LIB_NO_PD */ + + + +/* _LIB_ID definition */ +/* + _LIB_ID constructs like this: 0xXYVVVWWW + * X: 3 (PD3.0) or 2 (PD2.0) + * Y: 0 (CORE) or 1 (TCPM) + * VVV: Stack version (ex 200 for Stack 2.0.0) + * WWW: 0 (FULL VERSION) or config_x +*/ +/* Defines for PD revision */ +#define LIB_PD_VERSION_POS 28U +#define LIB_PD_VERSION_MSK (0xFU << LIB_PD_VERSION_POS) +#define LIB_PD2 (2U << LIB_PD_VERSION_POS) +#define LIB_PD3 (3U << LIB_PD_VERSION_POS) +/* Defines for CORE or TCPM */ +#define LIB_CORE_TCPM_POS 24U +#define LIB_CORE_TCPM_MSK (0xFU << LIB_CORE_TCPM_POS) +#define LIB_CORE (0U << LIB_CORE_TCPM_POS) +#define LIB_TCPM (1U << LIB_CORE_TCPM_POS) +/* Defines for STACK version */ +#define LIB_STACK_VER_POS 12U +#define LIB_STACK_VER_MSK (0xFFFU << LIB_STACK_VER_POS) +#define LIB_STACK_VER (0x410U << LIB_STACK_VER_POS) +/* Defines for configuration */ +#define LIB_CONFIG_MSK 0xFFFU +#define LIB_FULL 0x000U +#define LIB_CONFIG_1 0x001U +#define LIB_CONFIG_MINSRC 0x002U +#define LIB_CONFIG_MINSNK 0x004U +#define LIB_CONFIG_2 0x010U +#define LIB_CONFIG_NOPD 0x100U +#define LIB_CONFIG_MINDRP 0x200U +#define LIB_CONFIG_3 0x400U + +#define _LIB_ID LIB_ID /* done for CubeMX compatibility purpose */ + +#ifdef USBPDCORE_LIB_PD3_CONFIG_3 +#define LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_3) +#endif /* USBPDCORE_LIB_PD3_CONFIG_3*/ +#ifdef USBPDCORE_LIB_PD3_FULL +#define LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_FULL) +#endif /* USBPDCORE_LIB_PD3_FULL */ +#ifdef USBPDCORE_LIB_PD3_CONFIG_1 +#define LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_1) +#endif /* USBPDCORE_LIB_PD3_CONFIG_1 */ +#ifdef USBPDCORE_LIB_PD2_FULL +#define LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_FULL) +#endif /* USBPDCORE_LIB_PD2_FULL */ +#ifdef USBPDCORE_LIB_PD2_CONFIG_1 +#define LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_1) +#endif /* USBPDCORE_LIB_PD2_CONFIG_1 */ +#ifdef USBPDCORE_LIB_PD2_CONFIG_MINSRC +#define LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_MINSRC) +#endif /* USBPDCORE_LIB_PD2_CONFIG_MINSRC */ +#ifdef USBPDCORE_LIB_PD3_CONFIG_MINSRC +#define LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_MINSRC) +#endif /* USBPDCORE_LIB_PD3_CONFIG_MINSRC */ +#ifdef USBPDCORE_LIB_PD3_CONFIG_MINDRP +#define LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_MINDRP) +#endif /* USBPDCORE_LIB_PD3_CONFIG_MINSRC */ +#ifdef USBPDCORE_LIB_PD2_CONFIG_MINSNK +#define LIB_ID (LIB_PD2 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_MINSNK) +#endif /* USBPDCORE_LIB_PD2_CONFIG_MINSNK */ +#ifdef USBPDCORE_LIB_PD3_CONFIG_MINSNK +#define LIB_ID (LIB_PD3 | LIB_CORE | LIB_STACK_VER | LIB_CONFIG_MINSNK) +#endif /* USBPDCORE_LIB_PD3_CONFIG_MINSNK */ +#ifdef USBPD_TCPM_LIB_PD2_FULL +#define LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_FULL) +#endif /* USBPD_TCPM_LIB_PD2_FULL */ +#ifdef USBPD_TCPM_LIB_PD2_MINSRC +#define LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_MINSRC) +#endif /* USBPD_TCPM_LIB_PD2_MINSRC */ +#ifdef USBPD_TCPM_LIB_PD2_MINSNK +#define LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_MINSNK) +#endif /* USBPD_TCPM_LIB_PD2_MINSNK */ +#ifdef USBPD_TCPM_LIB_PD2_CONFIG_1 +#define LIB_ID (LIB_PD2 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_1) +#endif /* USBPD_TCPM_LIB_PD2_CONFIG_1 */ +#ifdef USBPD_TCPM_LIB_PD3_CONFIG_1 +#define LIB_ID (LIB_PD3 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_1) +#endif /* USBPD_TCPM_LIB_PD3_CONFIG_1 */ +#ifdef USBPD_TCPM_LIB_PD3_FULL +#define LIB_ID (LIB_PD3 | LIB_TCPM | LIB_STACK_VER | LIB_FULL) +#endif /* USBPD_TCPM_LIB_PD3_FULL */ +#if defined(USBPDCORE_LIB_PD3_CONFIG_2) +#define LIB_ID (LIB_PD3 | LIB_TCPM | LIB_STACK_VER | LIB_CONFIG_2) +#endif /* USBPDCORE_LIB_PD3_CONFIG_2 */ +#if defined(USBPDCORE_LIB_NO_PD) +#define LIB_ID (LIB_STACK_VER | LIB_CONFIG_NOPD) +#endif /* USBPDCORE_LIB_NO_PD */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +#define USBPD_PORT_0 (0U) /*!< Port 0 identifier */ +#define USBPD_PORT_1 (1U) /*!< Port 1 identifier */ +#define USBPD_PORT_2 (2U) /*!< Port 2 identifier */ + +#define USBPD_MAX_NB_PDO (7U) /*!< Maximum number of supported Power Data Objects: fix by the Specification */ +#define BIST_CARRIER_MODE_MS (50U) /*!< Time in ms of the BIST signal*/ + +/* + @brief Maximum size of the RX buffer allocated in the stack to receive a PD frame + @note TX buffer size is used internally in the stack (size if available in @ref USBPD_PHY_SendMessage) + */ +#if defined(USBPDCORE_UNCHUNCKED_MODE) +#define USBPD_MAX_RX_BUFFER_SIZE (264U) /*!< Maximum size of Rx buffer used when unchuncked is supported by the stack */ +#else +#define USBPD_MAX_RX_BUFFER_SIZE (30U) /*!< Maximum size of Rx buffer used when unchuncked + is NOT supported by the stack */ +#endif /* USBPDCORE_UNCHUNCKED_MODE */ + +/* + * Maximum size of a Power Delivery packet (in bits on the wire) : + * 16-bit header + 0..7 32-bit data objects (+ 4b5b encoding) + * 64-bit preamble + SOP (4x 5b) + header (16-bit) + message in 4b5b + 32-bit CRC + EOP (1x 5b) + * = 64bit + 4*5bit + 16bit * 5/4 + 7 * 32bit * 5/4 + 32bit * 5/4 + 5 + */ +#define PHY_BIT_LEN ((uint16_t)429U) +#define PHY_MAX_RAW_SIZE ((uint16_t)((PHY_BIT_LEN*2u) + 3U)) +#define PHY_MAX_RAW_BYTE_SIZE ((uint8_t)60U) /*! 70ns (>~7m) for P2.0 or 1000ns (~100m) for P3.0 */ +#if defined(USBPD_REV30_SUPPORT) + , CABLE_LATENCY_2000NS = 9U, /*!< 2000ns (~200m) */ + CABLE_LATENCY_3000NS = 10u /*!< 3000ns (~300m) */ +#endif /* USBPD_REV30_SUPPORT */ +} USBPD_CableLatency; + +/** + * @} + */ + +/** + * @brief Cable maximum VBUS voltage + * @{ + */ +#define VBUS_MAX_20V 0u +#define VBUS_MAX_30V 1u +#define VBUS_MAX_40V 2u +#define VBUS_MAX_50V 3u + +typedef uint32_t USBPD_CableMaxVoltage; + +/** + * @} + */ + +/** + * @brief Cable Termination Type in Active/Passive cable + * @{ + */ +#define CABLE_TERM_BOTH_PASSIVE_NO_VCONN 0u /*!< VCONN not required (PD2.0 only) */ +#define CABLE_TERM_BOTH_PASSIVE_VCONN 1u /*!< VCONN required (PD2.0 only) */ +#if defined(USBPD_REV30_SUPPORT) +#define CABLE_TERM_ONE_EACH_VCONN 2u /*!< One end Active, one end passive, VCONN required */ +#define CABLE_TERM_BOTH_ACTIVE_VCONN 3u /*!< Both ends Active, VCONN required */ +#endif /* USBPD_REV30_SUPPORT */ + +typedef uint32_t USBPD_CableTermType; + +/** + * @} + */ + +#if defined(USBPD_REV30_SUPPORT) +/** + * @brief Maximum Cable VBUS Voltage in Active/Passive cable + * @{ + */ +#define VBUS_20V 0u /*!< Maximum Cable VBUS Voltage 20V */ +#define VBUS_30V 1u /*!< Maximum Cable VBUS Voltage 30V */ +#define VBUS_40V 2u /*!< Maximum Cable VBUS Voltage 40V */ +#define VBUS_50V 3u /*!< Maximum Cable VBUS Voltage 50V */ + +typedef uint32_t USBPD_VBUSMaxVoltage; + +/** + * @} + */ + +/** + * @brief Active cable - SBU Supported + * @{ + */ +#define ACTIVE_CABLE_SBU_NOT_SUPPORTED 0u /*!< SBUs connections not supported */ +#define ACTIVE_CABLE_SBU_SUPPORTED 1u /*!< SBUs connections supported */ + +typedef uint32_t USBPD_ActiveCableSBUSupported; + +/** + * @} + */ + +/** + * @brief Active cable - SBU Type (valid only if SBU Connection is supported @ref ACTIVE_CABLE_SBU_SUPPORTED) + * @{ + */ +#define ACTIVE_CABLE_SBU_TYPE_PASSIVE 0u /*!< SBU is passive */ +#define ACTIVE_CABLE_SBU_TYPE_ACTIVE 1u /*!< SBU is active */ + +typedef uint32_t USBPD_ActiveCableSBUType; + +/** + * @} + */ + +/** + * @brief UFP VDO - Device capability + * @{ + */ +#define DEVICE_CAPABILITY_USB2P0 0u /*!< [USB 2.0] Device Capable */ +#define DEVICE_CAPABILITY_USB2P0_BILLBOARD 1u /*!< [USB 2.0] Device Capable (Billboard only) */ +#define DEVICE_CAPABILITY_USB3P2 2u /*!< [USB 3.2] Device Capable */ +#define DEVICE_CAPABILITY_USB4 3u /*!< [USB4] Device Capable */ + +typedef uint32_t USBPD_VDO_UFP_DeviceCapability; + +/** + * @} + */ + +/** + * @brief UFP VDO - Alternate Modes + * @{ + */ +#define ALTERNATE_MODES_TBT3 0u /*!< Supports [TBT3] Alternate Mode */ +#define ALTERNATE_MODES_RECONFIG_TYPEC_2P0 1u /*!< Supports Alternate Modes that reconfigure the signals + on the [USB Type-C 2.0] connector - except for [TBT3]. */ +#define ALTERNATE_MODES_NO_RECONFIG_TYPEC_2P0 2u /*!< Supports Alternate Modes that do not reconfigure the signals + on the [USB Type-C 2.0] connector */ + +typedef uint32_t USBPD_VDO_UFP_AlternateModes; + +/** + * @} + */ + +/** + * @brief DFP VDO - Host capability + * @{ + */ +#define HOST_CAPABILITY_USB2P0 0u /*!< [USB 2.0] Host Capable */ +#define HOST_CAPABILITY_USB3P2 1u /*!< [USB 3.2] Host Capable */ +#define HOST_CAPABILITY_USB4 2u /*!< [USB4] Host Capable */ + +typedef uint32_t USBPD_VDO_DFP_HostCapability; + +/** + * @} + */ + +#endif /* USBPD_REV30_SUPPORT */ + +/** + * @brief configurability of SS Directionality in Active/Passive cable and AMA VDO (PD2.0 only) + * @{ + */ +#define SS_DIR_FIXED 0u /*!< SSTX Directionality Support Fixed */ +#define SS_DIR_CONFIGURABLE 1u /*!< SSTX Directionality Support Configurable */ + +typedef uint32_t USBPD_SsDirectionality; + +/** + * @} + */ + +/** + * @brief SVDM commands definition + */ +#define SVDM_RESERVEDCOMMAND 0x00u +#define SVDM_DISCOVER_IDENTITY 0x01u +#define SVDM_DISCOVER_SVIDS 0x02u +#define SVDM_DISCOVER_MODES 0x03u +#define SVDM_ENTER_MODE 0x04u +#define SVDM_EXIT_MODE 0x05u +#define SVDM_ATTENTION 0x06u +#define SVDM_SPECIFIC_1 0x10u +#define SVDM_SPECIFIC_2 0x11u +#define SVDM_SPECIFIC_3 0x12u +#define SVDM_SPECIFIC_4 0x13u +#define SVDM_SPECIFIC_5 0x14u +#define SVDM_SPECIFIC_6 0x15u +#define SVDM_SPECIFIC_7 0x16u +#define SVDM_SPECIFIC_8 0x17u +#define SVDM_SPECIFIC_9 0x18u +#define SVDM_SPECIFIC_10 0x19u +#define SVDM_SPECIFIC_11 0x1Au +#define SVDM_SPECIFIC_12 0x1Bu +#define SVDM_SPECIFIC_13 0x1Cu +#define SVDM_SPECIFIC_14 0x1Du +#define SVDM_SPECIFIC_15 0x1Eu +#define SVDM_SPECIFIC_16 0x1Fu + +typedef uint32_t USBPD_VDM_Command_Typedef; + +/** + * @brief VBUS Current Handling Capability in Active/Passive cable VDO + * @{ + */ +#define VBUS_DEFAULT 0u /*!< USB Type-C Default Current */ +#define VBUS_3A 1u /*!< VBUS Current Handling Capability 3A */ +#define VBUS_5A 2u /*!< VBUS Current Handling Capability 5A */ + +typedef uint32_t USBPD_VBUSCurrentHandCap; + +/** + * @} + */ + +/** + * @brief USB Superspeed Signaling Support in Active/Passive cable VDO + * @{ + */ +#define USB2P0_ONLY 0u /*!< [USB 2.0] only, no SuperSpeed support */ +#define USB3P2_GEN1 1u /*!< [USB 3.2] Gen1 */ +#define USB3P2_USB4_GEN2 2u /*!< [USB 3.2]/[USB4] Gen2 */ +#if defined(USBPD_REV30_SUPPORT) +#define USB4_GEN3 3u /*!< [USB4] Gen3 */ +#endif /* USBPD_REV30_SUPPORT */ + +/* Used for legacy */ +#define USB3P1_GEN1 USB3P2_GEN1 /*!< USB3.1 Gen1 and USB2.0 */ +#define USB3P1_GEN1N2 USB3P2_USB4_GEN2 /*!< USB3.1 Gen1, Gen2 and USB2.0*/ + +typedef uint32_t USBPD_UsbSsSupport; +/** + * @} + */ + +/** + * @brief Power needed by adapter for full functionality in AMA VDO header + * @{ + */ +typedef enum +{ + VCONN_1W = 0U, /*!< VCONN power 1W */ + VCONN_1P5W = 1U, /*!< VCONN power 1.5W */ + VCONN_2W = 2U, /*!< VCONN power 2W */ + VCONN_3W = 3U, /*!< VCONN power 3W */ + VCONN_4W = 4U, /*!< VCONN power 4W */ + VCONN_5W = 5U, /*!< VCONN power 5W */ + VCONN_6W = 6U, /*!< VCONN power 6W */ +} USBPD_VConnPower; + +/** + * @} + */ + +/** + * @brief VCONN being required by an adapter in AMA VDO header + * @{ + */ +typedef enum +{ + VCONN_NOT_REQUIRED = 0U, /*!< VCONN not required */ + VCONN_REQUIRED = 1U, /*!< VCONN required */ +} USBPD_VConnRequirement; + +/** + * @} + */ + +/** + * @brief VBUS being required by an adapter in AMA VDO header + * @{ + */ +typedef enum +{ + VBUS_NOT_REQUIRED = 0U, /*!< VBUS not required */ + VBUS_REQUIRED = 1U, /*!< VBUS required */ +} USBPD_VBusRequirement; + +/** + * @} + */ + +#if defined(USBPD_REV30_SUPPORT) +#if defined(USBPDCORE_VPD) +/** + * @brief Vconn Powered USB Device VDO - Charge Through Current Support + * @{ + */ +#define VPD_CHARGE_THROUGH_NOT_SUPPORTED 0u /*!< the VPD does not support Charge Through */ +#define VPD_CHARGE_THROUGH_SUPPORTED 1u /*!< the VPD supports Charge Through */ + +typedef uint32_t USBPD_VDO_VPD_ChargeSupport; +/** + * @} + */ + +/** + * @brief Vconn Powered USB Device VDO - Charge Through Support + * @{ + */ +#define VPD_CHARGE_CURRENT_3A 0u /*!< 3A capable */ +#define VPD_CHARGE_CURRENT_5A 1u /*!< 5A capable */ + +typedef uint32_t USBPD_VDO_VPD_ChargeCurrent; +/** + * @} + */ +#endif /* USBPDCORE_VPD */ +#endif /* USBPD_REV30_SUPPORT */ + +#define SVDM_INITIATOR 0x00u +#define SVDM_RESPONDER_ACK 0x01u +#define SVDM_RESPONDER_NAK 0x02u +#define SVDM_RESPONDER_BUSY 0x03u +#define SVDM_CABLE_TIMEOUT 0x04u /*!< Indication that cable is PD capable but no answer to VDM Discovery identity */ +#define SVDM_CABLE_NO_PD_CAPABLE 0x05u /*!< Indication that cable is not PD capable (no goodCRC to VDM Discovery identity */ + +typedef uint32_t USBPD_VDM_CommandType_Typedef; + +/** + * @brief AMA USB Superspeed Signaling Support in AMA VDO header + * @{ + */ + +#define AMA_USB2P0_ONLY 0u /*!< [USB 2.0] only, no SuperSpeed support */ +#define AMA_USB3P2_GEN1 1u /*!< [USB 3.2] Gen1 and USB 2.0 */ +#define AMA_USB3P2_GEN1N2 2u /*!< [USB 3.2] Gen1, Gen2 and USB 2.0 */ +#define AMA_USB2P0_BILLBOARD 3u /*!< [USB 2.0] billboard only */ + +/* Keep for legacy reasons */ +#define AMA_USB3P1_GEN1 USB3P2_GEN1 /*!< USB3.1 Gen1 and USB2.0 */ +#define AMA_USB3P1_GEN1N2 AMA_USB3P2_GEN1N2 /*!< USB3.1 Gen1, Gen2 and USB2.0 */ + +typedef uint32_t USBPD_AmaUsbSsSupport; + +/** + * @} + */ + +/** + * @} + */ + +#if defined(USBPDCORE_FWUPD) +/** + * @brief USBPD Firmware Update Status Information + * @{ + */ +typedef enum +{ + USBPD_FWUPD_STATUS_OK = 0x00U, /*!< Request completed successfully or delayed */ + USBPD_FWUPD_STATUS_ERR_TARGET = 0x01U, /*!< FW not targeted for this device */ + USBPD_FWUPD_STATUS_ERR_FILE = 0x02U, /*!< Fails vendor-specific verification test */ + USBPD_FWUPD_STATUS_ERR_WRITE = 0x03U, /*!< Unable to write memory */ + USBPD_FWUPD_STATUS_ERR_ERASE = 0x04U, /*!< Memory erase function failed */ + USBPD_FWUPD_STATUS_ERR_CHECK_ERASED = 0x05U, /*!< Memory erase check failed */ + USBPD_FWUPD_STATUS_ERR_PROG = 0x06U, /*!< Program memory function failed */ + USBPD_FWUPD_STATUS_ERR_VERIFY = 0x07U, /*!< Program memory failed verification */ + USBPD_FWUPD_STATUS_ERR_ADDRESS = 0x08U, /*!< Received address is out of range */ + USBPD_FWUPD_STATUS_ERR_NOTDONE = 0x09U, /*!< Received PDFU_DATA Request with a zero length Data + Block, but the PDFU Responder expects more data */ + USBPD_FWUPD_STATUS_ERR_FIRMWARE = 0x0AU, /*!< Device's firmware is corrupt. + It cannot return to normal operations. */ + USBPD_FWUPD_STATUS_ERR_POR = 0x0DU, /*!< Unexpected power on reset */ + USBPD_FWUPD_STATUS_ERR_UNKNOWN = 0x0EU, /*!< Something went wrong */ + USBPD_FWUPD_STATUS_ERR_UNEXPECTED_HARD_RESET = 0x80U, /*!< Used when firmware update starts after a hard reset + (enumeration, etc.) that occurred in the middle + of firmware update */ + USBPD_FWUPD_STATUS_ERR_UNEXPECTED_SOFT_RESET = 0x81U, /*!< Used when firmware update starts after soft reset + (new power contract, etc.) + that occurred in the middle of firmware update */ + USBPD_FWUPD_STATUS_ERR_UNEXPECTED_REQUEST = 0x82U, /*!< PDFU Responder received a request that is not + appropriate for the current Phase */ + USBPD_FWUPD_STATUS_ERR_REJECT_PAUSE = 0x83U, /*!< PDFU Responder is unable or unwilling to pause + a firmware image transfer */ +} USBPD_FWUPD_Status_TypeDef; +/** + * @} + */ +#endif /* USBPDCORE_FWUPD */ + +/** @defgroup USBPD_CORE_DataInfoType_TypeDef USB CORE Data information type + * @brief Data Info types used in PE callbacks (USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) + * @{ + */ +typedef enum +{ + USBPD_CORE_DATATYPE_SRC_PDO = 0x00U, /*!< Handling of port Source PDO (SRC or DRP configuration used only in USBPD_PE_GetDataInfo) */ + USBPD_CORE_DATATYPE_SNK_PDO = 0x01U, /*!< Handling of port Sink PDO, requested by get sink capa (SNK or DRP configuration used only in USBPD_PE_GetDataInfo) */ + USBPD_CORE_DATATYPE_RDO_POSITION = 0x02U, /*!< Reset the PDO position selected by the sink only (used only in USBPD_PE_SetDataInfo) */ + USBPD_CORE_DATATYPE_REQ_VOLTAGE = 0x03U, /*!< Get voltage value requested for BIST tests, expect 5V (used only in USBPD_PE_GetDataInfo) */ + USBPD_CORE_DATATYPE_RCV_SRC_PDO = 0x04U, /*!< Storage of Received Source PDO values (used only in USBPD_PE_SetDataInfo) */ + USBPD_CORE_DATATYPE_RCV_SNK_PDO = 0x05U, /*!< Storage of Received Sink PDO values (used only in USBPD_PE_SetDataInfo) */ + USBPD_CORE_DATATYPE_RCV_REQ_PDO = 0x06U, /*!< Storage of Received Sink Request PDO value (SRC or DRP configuration used in USBPD_PE_SetDataInfo) */ + USBPD_CORE_DATATYPE_REQUEST_DO = 0x07U, /*!< Not used - keep for legacy reason */ + USBPD_CORE_EXTENDED_CAPA = 0x08U, /*!< Source Extended capability message content (used in USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) */ + USBPD_CORE_INFO_STATUS = 0x09U, /*!< Information status message content (used in USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) */ + USBPD_CORE_PPS_STATUS = 0x0AU, /*!< PPS Status message content (used in USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) */ + USBPD_CORE_ALERT, /*!< Storing of received Alert message content (used only in USBPD_PE_SetDataInfo) */ + USBPD_CORE_GET_MANUFACTURER_INFO, /*!< Storing of received Get Manufacturer info message content (used only in USBPD_PE_SetDataInfo) */ + USBPD_CORE_MANUFACTURER_INFO, /*!< Retrieve of Manufacturer info message content (used in USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) */ + USBPD_CORE_GET_BATTERY_STATUS, /*!< Storing of received Get Battery status message content (used only in USBPD_PE_SetDataInfo) */ + USBPD_CORE_BATTERY_STATUS, /*!< Retrieve of Battery status message content (used in USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) */ + USBPD_CORE_GET_BATTERY_CAPABILITY, /*!< Storing of received Get Battery capability message content (used only in USBPD_PE_SetDataInfo) */ + USBPD_CORE_BATTERY_CAPABILITY, /*!< Retrieve of Battery capability message content (used in USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) */ + USBPD_CORE_UNSTRUCTURED_VDM, /*!< Not used - keep for legacy reason */ +#if defined(USBPDCORE_SNK_CAPA_EXT) + USBPD_CORE_SNK_EXTENDED_CAPA, /*!< Storing and retrieve of Sink Extended capability message content (used in USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) */ +#endif /* USBPDCORE_SNK_CAPA_EXT */ +#if defined(USBPDCORE_PECABLE) + USBPD_CORE_CABLE_GETIDENTITY, /*!< get the cable identity information (used in USBPD_PE_GetDataInfo) */ + USBPD_CORE_CABLE_GETSTATUS, /*!< get the cable status information (used in USBPD_PE_GetDataInfo) */ +#endif /* USBPDCORE_PECABLE */ +#if defined(USBPDCORE_USBDATA) + USBPD_CORE_DATATYPE_ENTERUSB, /*!< get info to send an ENTER_USB message */ +#endif /* USBPDCORE_USBDATA */ + USBPD_CORE_REVISION, /*!< get/set revision info */ +} USBPD_CORE_DataInfoType_TypeDef; +/** + * @} + */ +#if defined(USBPDCORE_USBDATA) +/** @defgroup USBPD_CORE_ActionType_TypeDef USB CORE Action type + * @brief Data Info types used in PE callbacks (USBPD_PE_GetDataInfo and USBPD_PE_SetDataInfo) + * @{ + */ +typedef enum +{ + USBPD_ACTION_REPLY_ENTER_USB = 0x01U, /*!< Get DPM reply to a ENTER_USB message */ + USBPD_ACTION_REPLY_DATA_RESET = 0x02U, /*!< Get DPM reply to a DATA_RESET message */ +} USBPD_CORE_ActionType_TypeDef; +#endif /* USBPDCORE_USBDATA */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup USBPD_CORE_DEF_Exported_TypeDef USBPD CORE DEF Exported TypeDef + * @{ + */ + +#if defined(USBPD_REV30_SUPPORT) && defined(USBPDCORE_PPS) +/** + * @brief USB PD Programmable Power Supply APDO Structure definition (same for SRC and SNK) + * + */ +typedef struct +{ + uint32_t MaxCurrentIn50mAunits : 7u; /*!< Maximum Current in 50mA increments */ + uint32_t Reserved1 : 1u; /*!< Reserved - Shall be set to zero */ + uint32_t MinVoltageIn100mV : 8u; /*!< Minimum Voltage in 100mV increments */ + uint32_t Reserved2 : 1u; /*!< Reserved - Shall be set to zero */ + uint32_t MaxVoltageIn100mV : 8u; /*!< Maximum Voltage in 100mV increments */ + uint32_t Reserved3 : 2u; /*!< Reserved - Shall be set to zero */ + uint32_t PPSPowerLimited : 1u; /*!< PPS Power Limited Bit */ + uint32_t ProgrammablePowerSupply: 2u; /*!< 00b - Programmable Power Supply */ + uint32_t PPS_APDO : 2u; /*!< 11b - Augmented Power Data Object (APDO) */ +} USBPD_ProgrammablePowerSupplyAPDO_TypeDef; + +#endif /*_USBPD_REV30_SUPPORT && PPS*/ + +/** + * @brief USB PD Source Fixed Supply Power Data Object Structure definition + * + */ +typedef struct +{ + uint32_t MaxCurrentIn10mAunits : 10u; + uint32_t VoltageIn50mVunits : 10u; + USBPD_CORE_PDO_PeakCurr_TypeDef PeakCurrent : 2u; +#if defined(USBPD_REV30_SUPPORT) + uint32_t Reserved22_23 : 2u; + uint32_t UnchunkedExtendedMessage : 1u; +#else + uint32_t Reserved22_24 : 3u; +#endif /* USBPD_REV30_SUPPORT */ + USBPD_CORE_PDO_DRDataSupport_TypeDef DataRoleSwap : 1u; + USBPD_CORE_PDO_USBCommCapable_TypeDef USBCommunicationsCapable : 1u; + USBPD_CORE_PDO_ExtPowered_TypeDef ExternallyPowered : 1u; + USBPD_CORE_PDO_USBSuspendSupport_TypeDef USBSuspendSupported : 1u; + USBPD_CORE_PDO_DRPowerSupport_TypeDef DualRolePower : 1u; + USBPD_CORE_PDO_Type_TypeDef FixedSupply : 2u; + +} USBPD_SRCFixedSupplyPDO_TypeDef; + +/** + * @brief USB PD Source Variable Supply Power Data Object Structure definition + * + */ +typedef struct +{ +uint32_t MaxCurrentIn10mAunits : + 10u; +uint32_t MinVoltageIn50mVunits : + 10u; +uint32_t MaxVoltageIn50mVunits : + 10u; +uint32_t VariableSupply : + 2u; +} USBPD_SRCVariableSupplyPDO_TypeDef; + +/** + * @brief USB PD Source Battery Supply Power Data Object Structure definition + * + */ +typedef struct +{ +uint32_t MaxAllowablePowerIn250mWunits : + 10u; +uint32_t MinVoltageIn50mVunits : + 10u; +uint32_t MaxVoltageIn50mVunits : + 10u; +uint32_t Battery : + 2u; +} USBPD_SRCBatterySupplyPDO_TypeDef; + +/** + * @brief USB PD Sink Fixed Supply Power Data Object Structure definition + * + */ +typedef struct +{ +uint32_t OperationalCurrentIn10mAunits : + 10u; +uint32_t VoltageIn50mVunits : + 10u; +#if defined(USBPD_REV30_SUPPORT) +uint32_t FastRoleSwapRequiredCurrent : + 2u; +uint32_t Reserved20_22 : + 3u; +#else +uint32_t Reserved20_24 : + 5u; +#endif /* USBPD_REV30_SUPPORT */ +uint32_t DataRoleSwap : + 1u; +uint32_t USBCommunicationsCapable : + 1; +uint32_t ExternallyPowered : + 1u; +uint32_t HigherCapability : + 1u; +uint32_t DualRolePower : + 1u; +uint32_t FixedSupply : + 2u; +} USBPD_SNKFixedSupplyPDO_TypeDef; + +/** + * @brief USB PD Sink Variable Supply Power Data Object Structure definition + * + */ +typedef struct +{ +uint32_t OperationalCurrentIn10mAunits : + 10u; +uint32_t MinVoltageIn50mVunits : + 10u; +uint32_t MaxVoltageIn50mVunits : + 10u; +uint32_t VariableSupply : + 2u; +} USBPD_SNKVariableSupplyPDO_TypeDef; + +/** + * @brief USB PD Sink Battery Supply Power Data Object Structure definition + * + */ +typedef struct +{ +uint32_t OperationalPowerIn250mWunits : + 10u; +uint32_t MinVoltageIn50mVunits : + 10u; +uint32_t MaxVoltageIn50mVunits : + 10u; +uint32_t Battery : + 2u; +} USBPD_SNKBatterySupplyPDO_TypeDef; + +/** + * @brief USB PD Sink Generic Power Data Object Structure definition + * + */ +typedef struct +{ + uint32_t Bits_0_10 : 10u; /*!< Specific Power Capabilities are described by the (A)PDOs in the following sections. */ + uint32_t VoltageIn50mVunits : 10u; /*!< Maximum Voltage in 50mV units valid for all PDO (not APDO) */ + uint32_t Bits_20_29 : 10u; /*!< Specific Power Capabilities are described by the (A)PDOs in the following sections. */ + USBPD_CORE_PDO_Type_TypeDef PowerObject : 2u; /*!< (A) Power Data Object */ +} USBPD_GenericPDO_TypeDef; + +/** + * @brief USB PD Power Data Object Structure definition + * + */ +typedef union +{ + uint32_t d32; + + USBPD_GenericPDO_TypeDef GenericPDO; /*!< Generic Power Data Object Structure */ + + USBPD_SRCFixedSupplyPDO_TypeDef SRCFixedPDO; /*!< Fixed Supply PDO - Source */ + + USBPD_SRCVariableSupplyPDO_TypeDef SRCVariablePDO; /*!< Variable Supply (non-Battery) PDO - Source */ + + USBPD_SRCBatterySupplyPDO_TypeDef SRCBatteryPDO; /*!< Battery Supply PDO - Source */ + + USBPD_SNKFixedSupplyPDO_TypeDef SNKFixedPDO; /*!< Fixed Supply PDO - Sink */ + + USBPD_SNKVariableSupplyPDO_TypeDef SNKVariablePDO; /*!< Variable Supply (non-Battery) PDO - Sink */ + + USBPD_SNKBatterySupplyPDO_TypeDef SNKBatteryPDO; /*!< Battery Supply PDO - Sink */ + +#if defined(USBPD_REV30_SUPPORT) +#ifdef USBPDCORE_PPS + USBPD_ProgrammablePowerSupplyAPDO_TypeDef SRCSNKAPDO;/*!< Programmable Power Supply APDO - Source / Sink */ +#endif /* USBPDCORE_PPS */ +#endif /* USBPD_REV30_SUPPORT */ + +} USBPD_PDO_TypeDef; + +/** + * @brief USB PD Sink Fixed and Variable Request Data Object Structure definition + * + */ +typedef struct +{ +uint32_t MaxOperatingCurrent10mAunits : /*!< Corresponding to min if GiveBackFlag = 1 */ + 10u; +uint32_t OperatingCurrentIn10mAunits : + 10u; +#if defined(USBPD_REV30_SUPPORT) +uint32_t Reserved20_22 : + 3u; +uint32_t UnchunkedExtendedMessage : + 1u; +#else +uint32_t Reserved20_23 : + 4u; +#endif /* USBPD_REV30_SUPPORT */ +uint32_t NoUSBSuspend : + 1u; +uint32_t USBCommunicationsCapable : + 1u; +uint32_t CapabilityMismatch : + 1u; +uint32_t GiveBackFlag : + 1u; +uint32_t ObjectPosition : + 3u; +uint32_t Reserved31 : + 1u; +} USBPD_SNKFixedVariableRDO_TypeDef; + +/** + * @brief USB PD Sink Battery Request Data Object Structure definition + * + */ +typedef struct +{ +uint32_t MaxOperatingPowerIn250mWunits : + 10u; +uint32_t OperatingPowerIn250mWunits : + 10u; +#if defined(USBPD_REV30_SUPPORT) +uint32_t Reserved20_22 : + 3u; +uint32_t UnchunkedExtendedMessage : + 1u; /*!< Unchunked Extended Messages Supported */ +#else +uint32_t Reserved20_23 : + 4u; +#endif /* USBPD_REV30_SUPPORT */ +uint32_t NoUSBSuspend : + 1u; +uint32_t USBCommunicationsCapable : + 1u; +uint32_t CapabilityMismatch : + 1u; +uint32_t GiveBackFlag : + 1u; +uint32_t ObjectPosition : + 3u; +uint32_t Reserved31 : + 1u; +} USBPD_SNKBatteryRDO_TypeDef; + +#if defined(USBPD_REV30_SUPPORT) +/** + * @brief USB PD Sink Programmable Request Data Object Structure definition + * + */ +typedef struct +{ + uint32_t OperatingCurrentIn50mAunits : 7u; /*!< Operating Current 50mA units */ + uint32_t Reserved1 : 2u; /*!< Reserved - Shall be set to zero */ + uint32_t OutputVoltageIn20mV : 11; /*!< Output Voltage in 20mV units */ + uint32_t Reserved2 : 3u; /*!< Reserved - Shall be set to zero */ + uint32_t UnchunkedExtendedMessage : 1u; /*!< Unchunked Extended Messages Supported */ + uint32_t NoUSBSuspend : 1u; /*!< No USB Suspend */ + uint32_t USBCommunicationsCapable : 1u; /*!< USB Communications Capable */ + uint32_t CapabilityMismatch : 1u; /*!< Capability Mismatch */ + uint32_t Reserved3 : 1u; /*!< Reserved - Shall be set to zero */ + uint32_t ObjectPosition : 3u; /*!< Object position (000b is Reserved and Shall Not be used) */ + uint32_t Reserved4 : 1u; /*!< USB Communications Capable */ +} USBPD_SNKProgrammableRDO_TypeDef; +#endif /* USBPD_REV30_SUPPORT */ + + +/** + * @brief USB PD Sink Generic Request Data Object Structure definition + * + */ +typedef struct +{ +#if defined(USBPD_REV30_SUPPORT) + uint32_t Bits_0_22 : 23u; /*!< Bits 0 to 22 of RDO */ + uint32_t UnchunkedExtendedMessage : 1u; /*!< Unchunked Extended Messages Supported */ +#else + uint32_t Bits_0_23 : 24u; /*!< Bits 0 to 23 of RDO */ +#endif /* USBPD_REV30_SUPPORT */ + uint32_t NoUSBSuspend : 1u; /*!< No USB Suspend */ + uint32_t USBCommunicationsCapable : 1u; /*!< USB Communications Capable */ + uint32_t CapabilityMismatch : 1u; /*!< Capability Mismatch */ + uint32_t Bit_27 : 1u; /*!< Reserved - Shall be set to zero */ + uint32_t ObjectPosition : 3u; /*!< Object position (000b is Reserved and Shall Not be used) */ + uint32_t Bit_31 : 1u; /*!< USB Communications Capable */ +} USBPD_SNKGenericRDO_TypeDef; + +/** + * @brief USB PD Sink Request Data Object Structure definition + * + */ +typedef union +{ + uint32_t d32; + + USBPD_SNKGenericRDO_TypeDef GenericRDO; /*!< Generic Request Data Object Structure */ + + USBPD_SNKFixedVariableRDO_TypeDef FixedVariableRDO; /*!< Fixed and Variable Request Data Object Structure */ + + USBPD_SNKBatteryRDO_TypeDef BatteryRDO; /*!< Battery Request Data Object Structure */ + +#if defined(USBPD_REV30_SUPPORT) + USBPD_SNKProgrammableRDO_TypeDef ProgRDO; /*!< Programmable Request Data Object Structure */ +#endif /* USBPD_REV30_SUPPORT */ + +} USBPD_SNKRDO_TypeDef; + +#if defined(USBPD_REV30_SUPPORT) && defined(USBPDCORE_PPS) +/** + * @brief USBPD Port APDO Structure definition + * + */ +typedef struct +{ + uint32_t *ListOfAPDO; /*!< Pointer on Augmented Power Data Objects list, defining + port capabilities */ + uint8_t NumberOfAPDO; /*!< Number of Augmented Power Data Objects defined in ListOfAPDO + This parameter must be set at max to @ref USBPD_MAX_NB_PDO value */ +} USBPD_PortAPDO_TypeDef; +#endif /* USBPD_REV30_SUPPORT && USBPDCORE_PPS */ + +/** + * @brief USB PD BIST Data Object Structure definition + * + */ +typedef union +{ + uint32_t d32; + struct + { +uint32_t BistErrorCounter : + 16u; +uint32_t Reserved16_27 : + 12u; +uint32_t BistMode : + 4u; + } + b; +} USBPD_BISTDataObject_TypeDef; + +/** @brief Sink requested power profile Structure definition + * + */ +typedef struct +{ + uint32_t MaxOperatingCurrentInmAunits; /*!< Sink board Max operating current in mA units */ + uint32_t OperatingVoltageInmVunits; /*!< Sink board operating voltage in mV units */ + uint32_t MaxOperatingVoltageInmVunits; /*!< Sink board Max operating voltage in mV units */ + uint32_t MinOperatingVoltageInmVunits; /*!< Sink board Min operating voltage in mV units */ + uint32_t OperatingPowerInmWunits; /*!< Sink board operating power in mW units */ + uint32_t MaxOperatingPowerInmWunits; /*!< Sink board Max operating power in mW units */ +} USBPD_SNKPowerRequest_TypeDef; + + +/** @defgroup USBPD_CORE_VDM_Exported_Structures USBPD CORE VDM Exported Structures + * @{ + */ + +/** @defgroup USBPD_ProductVdo_TypeDef USB PD VDM Product VDO + * @brief USB PD Product VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { +uint32_t bcdDevice : /*!< Device version */ + 16u; +uint32_t USBProductId : /*!< USB Product ID */ + 16u; + } + b; +} USBPD_ProductVdo_TypeDef; + +/** + * @} + */ + +/** @defgroup USBPD_IDHeaderVDOStructure_definition USB SVDM ID header VDO Structure definition + * @brief USB SVDM ID header VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t VID : 16u; /*!< SVDM Header's SVDM Version */ + uint32_t Reserved : 10u; /*!< Reserved */ + USBPD_ModalOp_TypeDef ModalOperation : 1u; /*!< Modal Operation Supported based on @ref USBPD_ModalOp_TypeDef */ + USBPD_ProductType_TypeDef ProductTypeUFPorCP : 3u; /*!< Product Type (UFP or Cable Plug)based on @ref USBPD_ProductType_TypeDef */ + USBPD_USBCapa_TypeDef USBDevCapability : 1u; /*!< USB Communications Capable as a USB Device based on @ref USBPD_USBCapa_TypeDef */ + USBPD_USBCapa_TypeDef USBHostCapability : 1u; /*!< USB Communications Capable as USB Host based on @ref USBPD_USBCapa_TypeDef */ + } b20; +#if defined(USBPD_REV30_SUPPORT) + struct + { + uint32_t VID : 16u; /*!< SVDM Header's SVDM Version */ + uint32_t Reserved : 5u; /*!< Reserved */ + uint32_t ConnectorType : 2u; /*!< Connector Type based on @ref USBPD_ConnectorType_TypeDef */ + uint32_t ProductTypeDFP : 3u; /*!< Product Type (DFP) based on @ref USBPD_ProductType_TypeDef */ + USBPD_ModalOp_TypeDef ModalOperation : 1u; /*!< Modal Operation Supported based on @ref USBPD_ModalOp_TypeDef */ + USBPD_ProductType_TypeDef ProductTypeUFPorCP : 3u; /*!< Product Type (UFP or Cable Plug)based on @ref USBPD_ProductType_TypeDef */ + USBPD_USBCapa_TypeDef USBDevCapability : 1u; /*!< USB Communications Capable as a USB Device based on @ref USBPD_USBCapa_TypeDef */ + USBPD_USBCapa_TypeDef USBHostCapability : 1u; /*!< USB Communications Capable as USB Host based on @ref USBPD_USBCapa_TypeDef */ + } b30; +#endif /* USBPD_REV30_SUPPORT */ +} USBPD_IDHeaderVDO_TypeDef; +/** + * @} + */ + +typedef union +{ + struct /* PD 2.0*/ + { + USBPD_SsDirectionality SSRX2_DirSupport : 1u; /*!< SSRX2 Directionality Support (PD2.0) */ + USBPD_SsDirectionality SSRX1_DirSupport : 1u; /*!< SSRX1 Directionality Support (PD2.0) */ + USBPD_SsDirectionality SSTX2_DirSupport : 1u; /*!< SSTX2 Directionality Support (PD2.0) */ + USBPD_SsDirectionality SSTX1_DirSupport : 1u; /*!< SSTX1 Directionality Support (PD2.0) */ + } + pd_v20; +#if defined(USBPD_REV30_SUPPORT) + struct /* PD 3.0*/ + { + uint8_t Reserved : 2u; /*!< Reserved */ + USBPD_VBUSMaxVoltage MaxVBUS_Voltage : 2u; /*!< Maximum Cable VBUS Voltage */ + } + pd_v30; +#endif /* USBPD_REV30_SUPPORT */ +} USBPD_CableVdo_Field1TypeDef; + +/** @defgroup USBPD_AttentionInfo_TypeDef USB PD Attention Info object Structure definition + * @brief USB PD Attention Info object Structure definition + * @{ + */ +typedef struct +{ + uint32_t VDO; + uint16_t SVID; + USBPD_VDM_Command_Typedef Command; + uint8_t ModeIndex; +} USBPD_AttentionInfo_TypeDef; + +/** + * @} + */ + +typedef union +{ + struct /* PD 2.0*/ + { + uint8_t Reserved : 4u; /*!< Reserved */ + } + pd_v20; +#if defined(USBPD_REV30_SUPPORT) + struct /* PD 3.0*/ + { + uint8_t VDOVersion : 3u; /*!< Version Number of the VDO */ + uint8_t Reserved : 1u; /*!< Reserved */ + } + pd_v30; +#endif /* USBPD_REV30_SUPPORT */ +} USBPD_CableVdo_Field2TypeDef; + +#define VDM_UNSTRUCTUREDVDM_TYPE 0x0u +#define VDM_STRUCTUREDVDM_TYPE 0x1u + +typedef uint32_t USBPD_VDM_VDMType_Typedef; + +/** @defgroup USBPD_SVDMHeaderStructure_definition USB SVDM Message header Structure definition + * @brief USB SVDM Message header Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { +USBPD_VDM_Command_Typedef Command : /*!< SVDM Header's Command */ + 5u; +uint32_t Reserved5 : /*!< Reserved */ + 1u; +USBPD_VDM_CommandType_Typedef CommandType : /*!< SVDM Header's Command Type */ + 2u; +uint32_t ObjectPosition : /*!< SVDM Header's Object Position */ + 3u; +uint32_t Reserved11 : /*!< Reserved */ + 2u; +uint32_t SVDMVersion : /*!< SVDM Header's SVDM Version */ + 2u; +USBPD_VDM_VDMType_Typedef VDMType : /*!< SVDM Header's VDM Type */ + 1u; +uint32_t SVID : /*!< SVDM Header's SVID */ + 16u; + } + b; +} USBPD_SVDMHeader_TypeDef; + +/** + * @} + */ + +#ifdef USBPDCORE_UVDM +/** @defgroup USBPD_UVDMHeaderStructure_definition USB UVDM Message header Structure definition + * @brief USB UVDM Message header Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t VendorUse : 15u; /*!< Content of this field is defined by the vendor. */ + USBPD_VDM_VDMType_Typedef VDMType : 1u; /*!< VDM Type */ + uint32_t VID : 16u; /*!< Vendor ID (VID) */ + } + b; +} USBPD_UVDMHeader_TypeDef; + +/** + * @} + */ +#endif /* USBPDCORE_UVDM */ + +/** @defgroup USBPD_CableVdo_TypeDef USB PD VDM Passive Cable VDO + * @brief USB PD Passive Cable VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { + USBPD_UsbSsSupport USB_SS_Support : 3u; /*!< USB SuperSpeed Signaling Support */ + uint32_t reserved : 2u; + USBPD_VBUSCurrentHandCap VBUS_CurrentHandCap : 2u; /*!< VBUS Current Handling Capability */ + uint32_t Fields1 : 2u; /*!< Based on @ref USBPD_CableVdo_Field1TypeDef */ + USBPD_CableMaxVoltage CableMaxVoltage : 2u; /*!< Cable maximum voltage */ + USBPD_CableTermType CableTermType : 2u; /*!< Cable Termination Type */ + uint32_t CableLatency : 4u; /*!< Cable Latency */ + uint32_t Reserved : 1u; /*!< Reserved */ + USBPD_CableToType CableToType : 2u; /*!< USB Type-C plug to USB Type-A/B/C/Captive (PD 2.0) + USB Type-C plug to USB Type-C/Captive (PD 3.0) */ + uint32_t Fields2 : 1u; /*!< Based on @ref USBPD_CableVdo_Field2TypeDef */ + USBPD_VDM_VDO_PassiveCable_Version_TypeDef VDO_Version : 3u; /*!< Version number of the VDO */ + uint32_t CableFWVersion : 4u; /*!< Cable FW version number (vendor defined) */ + uint32_t CableHWVersion : 4u; /*!< Cable HW version number (vendor defined) */ + } + b; +} USBPD_CableVdo_TypeDef; + +#if defined(USBPD_REV30_SUPPORT) +/** @defgroup USBPD_ActiveCableVdo1_TypeDef USB PD VDM Active Cable VDO + * @brief USB PD Active Cable VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { + USBPD_UsbSsSupport USB_HighestSpeed : 3u; /*!< USB Highest Speed Support */ + uint32_t SOPSecondControllerPresent : 1u; /*!< SOP'' controller present Support */ + uint32_t VBUS_ThroughCable : 1u; /*!< VBUS Through Cable Support */ + USBPD_VBUSCurrentHandCap VBUS_CurrentHandCap : 2u; /*!< VBUS Current Handling Capability */ + USBPD_ActiveCableSBUType SBUType : 1u; /*!< SBU Type */ + USBPD_ActiveCableSBUSupported SBUSupported : 1u; /*!< SBUs connections supported */ + USBPD_CableMaxVoltage CableMaxVoltage : 2u; /*!< Cable maximum voltage */ + USBPD_CableTermType CableTermType : 2u; /*!< Cable Termination Type (@ref CABLE_TERM_ONE_EACH_VCONN or @ref CABLE_TERM_BOTH_ACTIVE_VCONN */ + uint32_t CableLatency : 4u; /*!< Cable Latency */ + uint32_t : 1u; /*!< B17 Reserved bit */ + USBPD_CableToType ConnectorType : 2u; /*!< Connector Type (@ref CABLE_TO_TYPE_C or @ref CABLE_CAPTIVE) */ + uint32_t : 1u; /*!< B20 Reserved bit */ + USBPD_VDM_VDO_ActiveCable_Version_TypeDef VDO_Version : 3u; /*!< Version number of the Active Cable VDO */ + uint32_t CableFWVersion : 4u; /*!< Cable FW version number (vendor defined) */ + uint32_t CableHWVersion : 4u; /*!< Cable HW version number (vendor defined) */ + } + b; +} USBPD_ActiveCableVdo1_TypeDef; + +/** + * @} + */ +#endif /* USBPD_REV30_SUPPORT */ + +/** @defgroup USBPD_CertStatVdo_TypeDef USB PD VDM Cert stat VDO + * @brief USB PD Cert stat VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { +uint32_t XID : /*!< USB-IF assigned XID */ + 32; + } + b; +} USBPD_CertStatVdo_TypeDef; + +/** + * @} + */ + +/** @defgroup USBPD_AMAVdo_TypeDef USB PD VDM Alternate Mode Adapter VDO (NO MORE USED IN PD3.0) + * @brief USB PD Alternate Mode Adapter VDO Structure definition + * @{ + */ +/* #### Keep for PD2.0 legacy reasons but should NOT more used. #### */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t AMA_USB_SS_Support : 3u; /*!< AMA USB SuperSpeed Signaling Support based on + @ref USBPD_AmaUsbSsSupport */ + uint32_t VBUSRequirement : 1u; /*!< VBUS required based on + @ref USBPD_VBusRequirement */ + uint32_t VCONNRequirement : 1u; /*!< VCONN required based on + @ref USBPD_VConnRequirement */ + uint32_t VCONNPower : 3u; /*!< VCONN power based on + @ref USBPD_VConnPower */ +#if defined(USBPD_REV30_SUPPORT) + uint32_t Reserved : 13; /*!< Reserved */ + uint32_t VDO_Version : 3u; /*!< Version Number of the VDO */ +#else + uint32_t SSRX2_DirSupport : 1u; /*!< SSRX2 Directionality Support (PD2.0) based on + @ref USBPD_SsDirectionality */ + uint32_t SSRX1_DirSupport : 1u; /*!< SSRX1 Directionality Support (PD2.0) based on + @ref USBPD_SsDirectionality */ + uint32_t SSTX2_DirSupport : 1u; /*!< SSTX2 Directionality Support (PD2.0) based on + @ref USBPD_SsDirectionality */ + uint32_t SSTX1_DirSupport : 1u; /*!< SSTX1 Directionality Support (PD2.0) based on + @ref USBPD_SsDirectionality */ + uint32_t Reserved : 12u; /*!< Reserved */ +#endif /* USBPD_REV30_SUPPORT */ + uint32_t AMAFWVersion : 4u; /*!< AMA FW version number (vendor defined) */ + uint32_t AMAHWVersion : 4u; /*!< AMA HW version number (vendor defined) */ + } + b; +} USBPD_AMAVdo_TypeDef; +/* #### Keep for PD2.0 legacy reasons but should NOT more used. #### */ +/** + * @} + */ + +#if defined(USBPD_REV30_SUPPORT) +/** @defgroup USBPD_UFPVdo_TypeDef USB PD VDM UFP VDO + * @brief USB PD UFP VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { + USBPD_UsbSsSupport USB_HighestSpeed : 3u; /*!< USB Highest Speed Support */ + USBPD_VDO_UFP_AlternateModes AlternateModes : 3u; /*!< Alternate Modes based */ + uint32_t : 16u; /*!< B21_6 Reserved bit */ + USBPD_ConnectorType_TypeDef ConnectorType : 2u; /*!< Connector Type */ + USBPD_VDO_UFP_DeviceCapability DeviceCapability : 4u; /*!< Device Capability */ + uint32_t : 1u; /*!< B28 Reserved bit */ + USBPD_VDM_VDO_UFP_Version_TypeDef UFPVDOVersion : 3u; /*!< Version Number of the VDO (should be set to Version1.1) */ + } + b; +} USBPD_UFPVdo_TypeDef; +/** + * @} + */ + +/** @defgroup USBPD_DFPVdo_TypeDef USB PD VDM DFP VDO + * @brief USB PD DFP VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t PortNumber : 5u; /*!< Unique port number to identify a specific port on a multi-port device */ + uint32_t : 17u; /*!< B21-5 Reserved bits */ + USBPD_ConnectorType_TypeDef ConnectorType : 2u; /*!< Connector Type */ + USBPD_VDO_DFP_HostCapability HostCapability : 3u; /*!< Host Capability */ + uint32_t : 2u; /*!< B28-27 Reserved bits */ + USBPD_VDM_VDO_DFP_Version_TypeDef DFPVDOVersion : 3u; /*!< Version Number of the VDO (should be set to Version1.1) */ + } + b; +} USBPD_DFPVdo_TypeDef; +/** + * @} + */ + +#if defined(USBPDCORE_VPD) +/** @defgroup USBPD_VPDVdo_TypeDef USB PD VDM Vconn Powered USB Device VDO + * @brief USB PD Vconn Powered USB Device VDO Structure definition + * @{ + */ +typedef union +{ + uint32_t d32; + struct + { + USBPD_VDO_VPD_ChargeSupport ChargeThroughSupport : 1u; /*!< Charge Through Support */ + uint32_t GroundImpedance : 6u; /*!< Charge Through Support bit = 1b: Ground impedance through the VPD in 1 mOhm increments. + Values less than 10 mOhm are Reserved and Shall Not be used. + Charge Through Support bit = 0b: Reserved, Shall be set to zero */ + uint32_t VBUS_Impedance : 6u; /*!< Charge Through Support bit = 1b: Vbus impedance through the VPD in 2 mOhm increments. + Values less than 10 mOhm are Reserved and Shall Not be used. + Charge Through Support bit = 0b: Reserved, Shall be set to zero */ + uint32_t : 2u; /*!< B14-13 Reserved bit */ + USBPD_VDO_VPD_ChargeCurrent ChargeThroughCurrent : 1u; /*!< Charge Through Current Support */ + USBPD_CableMaxVoltage CableMaxVoltage : 2u; /*!< Cable maximum voltage */ + uint32_t : 4u; /*!< B20-17 Reserved bit */ + USBPD_VDM_VDO_VPD_Version_TypeDef VDO_Version : 3u; /*!< Version number of the VPD VDO */ + uint32_t FWVersion : 4u; /*!< Cable FW version number (vendor defined) */ + uint32_t HWVersion : 4u; /*!< Cable HW version number (vendor defined) */ + } + b; +} USBPD_VPDVdo_TypeDef; +/** + * @} + */ +#endif /* USBPDCORE_VPD */ +#endif /* USBPD_REV30_SUPPORT */ + +/** @defgroup USBPD_DiscoveryIdentity_TypeDef USB PD Discovery identity Structure definition + * @brief Data received from Discover Identity messages + * @{ + */ +typedef struct +{ + USBPD_IDHeaderVDO_TypeDef IDHeader; /*!< ID Header VDO */ + USBPD_CertStatVdo_TypeDef CertStatVDO; /*!< Cert Stat VDO */ + USBPD_ProductVdo_TypeDef ProductVDO; /*!< Product VDO */ +#if defined(USBPDCORE_VCONN_SUPPORT) + USBPD_CableVdo_TypeDef CableVDO; /*!< Passive Cable VDO */ +#endif /* USBPDCORE_VCONN_SUPPORT */ + USBPD_AMAVdo_TypeDef AMA_VDO; /*!< Alternate Mode Adapter VDO */ +#if defined(USBPD_REV30_SUPPORT) +#if defined(USBPDCORE_VCONN_SUPPORT) + USBPD_ActiveCableVdo1_TypeDef ActiveCableVDO1; /*!< Active Cable VDO 1 */ +#endif /* USBPDCORE_VCONN_SUPPORT */ + USBPD_UFPVdo_TypeDef UFP_VDO; /*!< UFP VDO */ + USBPD_DFPVdo_TypeDef DFP_VDO; /*!< DFP VDO */ +#if defined(USBPDCORE_VPD) + USBPD_VPDVdo_TypeDef VPD_VDO; /*!< VPD VDO */ +#endif /* USBPDCORE_VPD */ +#endif /* USBPD_REV30_SUPPORT */ +#if defined(USBPDCORE_VCONN_SUPPORT) + uint8_t CableVDO_Presence : 1U; /*!< Indicate Passive Cable VDO presence or not */ +#endif /* USBPDCORE_VCONN_SUPPORT */ + uint8_t AMA_VDO_Presence : 1U; /*!< Indicate Alternate Mode Adapter VDO presence or not */ +#if defined(USBPD_REV30_SUPPORT) +#if defined(USBPDCORE_VCONN_SUPPORT) + uint8_t ActiveCableVDO1_Presence: 1U; /*!< indicate active cable vdo 1 presence or not */ +#endif /* USBPDCORE_VCONN_SUPPORT */ + uint8_t UFP_VDO_Presence : 1U; /*!< Indicate UFP VDO presence or not */ + uint8_t DFP_VDO_Presence : 1U; /*!< Indicate DFP VDO presence or not */ +#if defined(USBPDCORE_VPD) + uint8_t VPD_VDO_Presence : 1U; /*!< Indicate VPD VDO presence or not */ +#if defined(USBPDCORE_VCONN_SUPPORT) + uint8_t Reserved : 2U; /*!< Reserved bits */ +#else + uint8_t Reserved : 3U; /*!< Reserved bits */ +#endif /* USBPDCORE_VCONN_SUPPORT */ +#else +#if defined(USBPDCORE_VCONN_SUPPORT) + uint8_t Reserved : 3U; /*!< Reserved bits */ +#else + uint8_t Reserved : 4U; /*!< Reserved bits */ +#endif /* USBPDCORE_VCONN_SUPPORT */ +#endif /* USBPDCORE_VPD */ +#else +#if defined(USBPDCORE_VCONN_SUPPORT) + uint8_t Reserved : 6U; /*!< Reserved bits */ +#else + uint8_t Reserved : 7U; /*!< Reserved bits */ +#endif /* USBPDCORE_VCONN_SUPPORT */ +#endif /* USBPD_REV30_SUPPORT */ +} USBPD_DiscoveryIdentity_TypeDef; +/** + * @} + */ + +/** @defgroup USBPD_ModeInfo_TypeDef USB PD Mode Info object Structure definition + * @brief USB PD Mode Info object Structure definition + * @{ + */ +typedef struct +{ + uint32_t NumModes; + uint32_t Modes[MAX_MODES_PER_SVID]; + uint16_t SVID; +} USBPD_ModeInfo_TypeDef; + +/** + * @} + */ + +/** @defgroup USBPD_SVID_TypeDef USB PD Discovery SVID Structure definition + * @brief Data received from Discover Identity messages + * @{ + */ +/* + * Structure to SVID supported by the devices + */ +typedef struct +{ + uint16_t SVIDs[12u]; + uint8_t NumSVIDs; + uint8_t AllSVID_Received; /*!< Flag to indicate that all the SVIDs have been received. + No need to send new SVDM Discovery SVID message */ +} USBPD_SVIDInfo_TypeDef; +/** + * @} + */ + +#if defined(USBPD_REV30_SUPPORT) +/** + * @brief USBPD Alert Data Object Structure definition + * + */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t Reserved : 16u; /*!< Reserved */ + uint32_t HotSwappableBatteries: 4u; /*!< Hot Swappable Batteries is a combination of @ref USBPD_ADO_HOT_SWAP_BATT */ + uint32_t FixedBatteries : 4u; /*!< Fixed Batteries is a combination of @ref USBPD_ADO_FIXED_BATT */ + uint32_t TypeAlert : 8u; /*!< Type of Alert is a combination of @ref USBPD_ADO_TYPE_ALERT */ + } + b; +} USBPD_ADO_TypeDef; + +/** + * @brief USBPD revision Data Object Structure definition + * + */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t :16u; /*!< Reserved */ + uint32_t Version_minor : 4u; /*!< Version minor */ + uint32_t Version_major : 4u; /*!< Version major */ + uint32_t Revision_minor : 4u; /*!< Revision minor */ + uint32_t Revision_major : 4u; /*!< Revision major */ + } + b; +} USBPD_RevisionDO_TypeDef; + + + +/** + * @brief USBPD Battery Status Data Object Structure definition + * + */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t Reserved: 8u; + uint32_t BatteryInfo: 8u; /*!< Based on @ref USBPD_BSDO_BATT_INFO */ + uint32_t BatteryPC: 16u; + } + b; +} USBPD_BSDO_TypeDef; + +/** + * @brief USBPD Source Capabilities Extended Message Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ + uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ + uint32_t XID; /*!< Value provided by the USB-IF assigned to the product */ + uint8_t FW_revision; /*!< Firmware version number */ + uint8_t HW_revision; /*!< Hardware version number */ + uint8_t Voltage_regulation; /*!< Voltage Regulation */ + uint8_t Holdup_time; /*!< Holdup Time */ + uint8_t Compliance; /*!< Compliance */ + uint8_t TouchCurrent; /*!< Touch Current */ + uint16_t PeakCurrent1; /*!< Peak Current1 */ + uint16_t PeakCurrent2; /*!< Peak Current2 */ + uint16_t PeakCurrent3; /*!< Peak Current3 */ + uint8_t Touchtemp; /*!< Touch Temp */ + uint8_t Source_inputs; /*!< Source Inputs */ + uint8_t NbBatteries; /*!< Number of Batteries/Battery Slots */ + uint8_t SourcePDP; /*!< SPR Source PDP rating */ + uint8_t EPRSourcePDP; /*!< EPR Source PDP rating */ +} USBPD_SCEDB_TypeDef; + +#if defined(USBPDCORE_SNK_CAPA_EXT) +/** + * @brief SKEDB - Sink Load Characteristics structure definition + * + */ +typedef union +{ + uint16_t Value; + struct + { + uint16_t PercentOverload : 5u; /*!< Percent overload in 10% increments Values higher than 25 (11001b) are clipped to 250%. + 00000b is the default. */ + uint16_t OverloadPeriod : 6u; /*!< Overload period in 20ms when bits 0-4 non-zero. */ + uint16_t DutyCycle : 4u; /*!< Duty cycle in 5% increments when bits 0-4 are non-zero. */ + uint16_t VBusVoltageDrop : 1u; /*!< Can tolerate VBUS Voltage drop. */ + } b; +} USBPD_SKEDB_SinkLoadCharac_TypeDef; +/** + * @brief USBPD Sink Capabilities Extended Message Structure definition + * + */ +typedef struct USBPD_SKEDB_TypeDef +{ + uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ + uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ + uint32_t XID; /*!< Value provided by the USB-IF assigned to the product */ + uint8_t FW_revision; /*!< Firmware version number */ + uint8_t HW_revision; /*!< Hardware version number */ + uint8_t SKEDB_Version; /*!< SKEDB Version (not the specification Version) based on + @ref USBPD_SKEDB_VERSION */ + uint8_t LoadStep; /*!< Load Step based on @ref USBPD_SKEDB_LOADSTEP */ + USBPD_SKEDB_SinkLoadCharac_TypeDef SinkLoadCharac; /*!< Sink Load Characteristics */ + uint8_t Compliance; /*!< Compliance based on combination of @ref USBPD_SKEDB_COMPLIANCE */ + uint8_t Touchtemp; /*!< Touch Temp based on @ref USBPD_SKEDB_TOUCHTEMP */ + uint8_t BatteryInfo; /*!< Battery info */ + uint8_t SinkModes; /*!< Sink Modes based on combination of @ref USBPD_SKEDB_SINKMODES */ + uint8_t SinkMinimumPDP; /*!< The Minimum PDP required by the Sink to operate without + consuming any power from its Battery(s) should it have one */ + uint8_t SinkOperationalPDP; /*!< The PDP the Sink requires to operate normally. For Sinks with + a Battery, it is the PDP Rating of the charger supplied with + it or recommended for it. */ + uint8_t SinkMaximumPDP; /*!< The Maximum PDP the Sink can consume to operate and + charge its Battery(s) should it have one. */ +} USBPD_SKEDB_TypeDef; +#endif /* USBPDCORE_SNK_CAPA_EXT */ + +/** + * @brief USBPD Source Status Extended Message Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint8_t InternalTemp; /*!< Source or Sink internal temperature in degrees centigrade */ + uint8_t PresentInput; /*!< Present Input based on @ref USBPD_SDB_PRESENT_INPUT */ + uint8_t PresentBatteryInput; /*!< Present Battery Input */ + uint8_t EventFlags; /*!< Event Flags based on @ref USBPD_SDB_EVENT_FLAGS */ + uint8_t TemperatureStatus; /*!< Temperature based on @ref USBPD_SDB_TEMP_STATUS */ + uint8_t PowerStatus; /*!< Power Status based on combination of @ref USBPD_SDB_POWER_STATUS */ + uint8_t PowerStateChange; /*!< The Power state change status byte indicates a power state change + based on @ref USBPD_SDB_PWR_STATE */ +} USBPD_SDB_TypeDef; + +/** + * @brief USBPD Get Battery Capabilities Data Block Extended Message Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint8_t BatteryCapRef; /*!< Number of the Battery indexed from zero */ +} USBPD_GBCDB_TypeDef; + +/** + * @brief USBPD Get Battery Status Data Block Extended Message Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint8_t BatteryStatusRef; /*!< Number of the Battery indexed from zero */ +} USBPD_GBSDB_TypeDef; + +/** + * @brief USBPD Battery Capability Data Block Extended Message Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ + uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ + uint16_t BatteryDesignCapa; /*!< Battery Design Capacity */ + uint16_t BatteryLastFullChargeCapa; /*!< Battery last full charge capacity */ + uint8_t BatteryType; /*!< Battery Type */ +} USBPD_BCDB_TypeDef; + +/** + * @brief USBPD Get Manufacturer Info Info Data Block Extended Message Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint8_t ManufacturerInfoTarget; /*!< Manufacturer Info Target based on @ref USBPD_MANUFINFO_TARGET */ + uint8_t ManufacturerInfoRef; /*!< Manufacturer Info Ref between Min_Data=0 and Max_Data=7 (@ref USBPD_MANUFINFO_REF) */ +} USBPD_GMIDB_TypeDef; + +/** + * @brief USBPD Manufacturer Info Data Block Extended Message Structure definition + * + */ +typedef struct +{ + uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ + uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ + uint8_t ManuString[22]; /*!< Vendor defined byte array */ +} USBPD_MIDB_TypeDef; + +#if defined(USBPDCORE_FWUPD) +/** + * @brief USBPD Firmware Update GET_FW_ID Response Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ + uint16_t VID; /*!< USB-IF assigned Vendor ID */ + uint16_t PID; /*!< USB-IF assigned Product ID */ + uint8_t HWVersion; /*!< Hardware Version */ + uint8_t SiVersion; /*!< Silicon Version */ + uint16_t FWVersion1; /*!< Most significant component of the firmware version */ + uint16_t FWVersion2; /*!< Second-most significant component of the firmware version */ + uint16_t FWVersion3; /*!< Third-most significant component of the firmware version */ + uint16_t FWVersion4; /*!< Least significant component of the firmware version */ + uint8_t ImageBank; /*!< Image bank for which firmware is requested */ + uint8_t Flags1; /*!< Flags1 */ + uint8_t Flags2; /*!< Flags2 */ + uint8_t Flags3; /*!< Flags3 */ + uint8_t Flags4; /*!< Flags4 */ +} USBPD_FWUPD_GetFwIDRspPayload_TypeDef; + +/** + * @brief USBPD Firmware Update PDFU_INITIATE Request Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint16_t FWVersion1; /*!< Most significant component of the firmware version */ + uint16_t FWVersion2; /*!< Second-most significant component of the firmware version */ + uint16_t FWVersion3; /*!< Third-most significant component of the firmware version */ + uint16_t FWVersion4; /*!< Least significant component of the firmware version */ +} USBPD_FWUPD_PdfuInitReqPayload_TypeDef; + +/** + * @brief USBPD Firmware Update PDFU_INITIATE Response Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ + uint8_t WaitTime; /*!< Wait time */ + uint8_t MaxImageSize[3u]; /*!< Max image size */ +} USBPD_FWUPD_PdfuInitRspPayload_TypeDef; + +/** + * @brief USBPD Firmware Update PDFU_DATA Response Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ + uint8_t WaitTime; /*!< Wait time */ + uint8_t NumDataNR; /*!< Number of PDFU_DATA_NR Requests */ + uint16_t DataBlockNum; /*!< Data Block Number of the next PDFU_DATA or PDFU_DATA_NR */ +} USBPD_FWUPD_PdfuDataRspPayload_TypeDef; + +/** + * @brief USBPD Firmware Update PDFU_VALIDATE Response Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ + uint8_t WaitTime; /*!< Wait time */ + uint8_t Flags; /*!< Flags */ +} USBPD_FWUPD_PdfuValidateRspPayload_TypeDef; + +/** + * @brief USBPD Firmware Update PDFU_DATA_PAUSE Response Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ +} USBPD_FWUPD_PdfuDataPauseRspPayload_TypeDef; + +/** + * @brief USBPD Firmware Update VENDOR_SPECIFIC Request Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint16_t VID; /*!< USB-IF assigned Vendor ID */ + uint8_t VendorDefined[256]; /*!< Vendor defined */ +} USBPD_FWUPD_VendorSpecificReqPayload_TypeDef; + +/** + * @brief USBPD Firmware Update VENDOR_SPECIFIC Response Payload Structure definition + * + */ +typedef __PACKED_STRUCT +{ + USBPD_FWUPD_Status_TypeDef Status; /*!< Status Information during Firmware Update */ + uint16_t VID; /*!< USB-IF assigned Vendor ID */ + uint8_t VendorDefined[255]; /*!< Vendor defined */ +} USBPD_FWUPD_VendorSpecificRspPayload_TypeDef; + +/** + * @brief USBPD Firmware Update Request Data Block Extended Message Structure definition + * + */ +typedef __PACKED_STRUCT +{ + uint8_t ProtocolVersion; /*!< Protocol Version (@ref USBPD_FWUPD_PROT_VER) */ + uint8_t MessageType; /*!< Firmware Update Message type (@ref USBPD_FWUPD_MSGTYPE) */ + uint8_t Payload[258]; /*!< Payload */ +} USBPD_FRQDB_TypeDef; + +#endif /* USBPDCORE_FWUPD */ + +#ifdef USBPDCORE_PPS +/** + * @brief USBPD PPS Status Data Block Extended Message Structure definition + * + */ +typedef union +{ + uint32_t d32; + struct + { + uint16_t OutputVoltageIn20mVunits; /*!< Source output voltage in 20mV units. + When set to 0xFFFF, the Source does not support this field. */ + uint8_t OutputCurrentIn50mAunits; /*!< Source output current in 50mA units. + When set to 0xFF, the Source does not support this field. */ + uint8_t RealTimeFlags; /*!< Real Time Flags, combination of @ref USBPD_CORE_DEF_REAL_TIME_FLAGS */ + } fields; +} USBPD_PPSSDB_TypeDef; +#endif /* USBPDCORE_PPS */ + +/** + * @brief USBPD Country Code Data Block Extended Message Structure definition + * + */ +typedef struct +{ + uint32_t Length; /*!< Number of country codes in the message */ + uint16_t *PtrCountryCode; /*!< Pointer of the country codes (1 to n) */ +} USBPD_CCDB_TypeDef; + +/** + * @brief USBPD Country Info Data Block Extended Message Structure definition + * + */ +typedef struct +{ + uint16_t CountryCode; /*!< 1st and 2nd character of the Alpha-2 Country Code defined by [ISO 3166] */ + uint32_t Reserved; /*!< Reserved - Shall be set to 0. */ + uint8_t PtrCountrySpecificData; /*!< Pointer on Content defined by the country authority (0 t 256 bytes). */ +} USBPD_CIDB_TypeDef; + +#endif /* USBPD_REV30_SUPPORT */ + +/** + * @} + */ + +/** @defgroup USBPD_CORE_SETTINGS_Exported_Structures USBPD CORE Settings Exported Structures + * @brief USBPD Settings Structure definition + * @{ + */ +#if defined(USBPD_REV30_SUPPORT) +typedef union +{ + uint16_t PD3_Support; + struct + { + uint16_t PE_UnchunkSupport : 1u; /*!< Unchunked support */ + uint16_t PE_FastRoleSwapSupport : 1u; /*!< Fast role swap support (not yet implemented) */ + uint16_t Is_GetPPSStatus_Supported : 1u; /*!< Get PPS status message supported by PE */ + uint16_t Is_SrcCapaExt_Supported : 1u; /*!< Source_Capabilities_Extended message supported by PE */ + uint16_t Is_Alert_Supported : 1u; /*!< Alert message supported by PE */ + uint16_t Is_GetStatus_Supported : 1u; /*!< Get_Status message supported by PE (Is_Alert_Supported should be enabled) */ + uint16_t Is_GetManufacturerInfo_Supported : 1u; /*!< Manufacturer_Info message supported by PE */ + uint16_t Is_GetCountryCodes_Supported : 1u; /*!< Get_Country_Codes message supported by PE */ + uint16_t Is_GetCountryInfo_Supported : 1u; /*!< Get_Country_Info message supported by PE */ + uint16_t Is_SecurityRequest_Supported : 1u; /*!< Security_Response message supported by PE */ + uint16_t Is_FirmUpdateRequest_Supported : 1u; /*!< Firmware update response message supported by PE */ + uint16_t Reserved2 : 1u; /*!< Reserved bits: old Is_SnkCapaExt_Supported (SNK_CAPA_EXT msg mandatory) */ + uint16_t Is_GetBattery_Supported : 1u; /*!< Get Battery Capabitity and Status messages supported by PE */ + uint16_t reserved : 3u; /*!< Reserved bits */ + } d; +} USBPD_PD3SupportTypeDef; +#endif /* USBPD_REV30_SUPPORT */ + +typedef struct +{ +#if defined(USBPDCORE_LIB_NO_PD) + USBPD_PortPowerRole_TypeDef PE_DefaultRole: 1u; /*!< Default port role based on @ref USBPD_PortPowerRole_TypeDef */ + CAD_RP_Source_Current_Adv_Typedef CAD_DefaultResistor : 2u; /*!< Default RP resistor based on @ref CAD_RP_Source_Current_Adv_Typedef */ + uint8_t : 5u; /*!< Reserved bits */ +#else + USBPD_SupportedSOP_TypeDef PE_SupportedSOP; /*!< Corresponds to the message managed by the stack and this should be set depending if you want discuss with the cable + So if VconnSupport is enabling this field must be set to + @ref USBPD_SUPPORTED_SOP_SOP | + @ref USBPD_SUPPORTED_SOP_SOP1 | + @ref USBPD_SUPPORTED_SOP_SOP2 + else + @ref USBPD_SUPPORTED_SOP_SOP + */ + USBPD_SpecRev_TypeDef PE_SpecRevision : 2u; /*!< Spec revision value based on @ref USBPD_SpecRev_TypeDef */ + USBPD_PortPowerRole_TypeDef PE_DefaultRole: 1u; /*!< Default port role based on @ref USBPD_PortPowerRole_TypeDef */ + uint32_t PE_RoleSwap : 1u; /*!< If enabled, allows the port to have DRP behavior */ +#if defined(USBPDCORE_VPD) + uint32_t VPDSupport : 1u; /*!< support of the CTVPD device */ +#else + uint32_t _empty1 : 1u; /*!< Reserved bit */ +#endif /* USBPDCORE_VPD */ + uint32_t PE_VDMSupport : 1u; /*!< Support VDM: If not enabled any VDM message received is replied "not supported" */ + uint32_t PE_PingSupport : 1u; /*!< support Ping (only for PD3.0): If enabled allows DPM to send ping message */ + uint32_t PE_CapscounterSupport : 1u; /*!< If enabled after an amount of message source capabilities not replied, the stack stop the message send.*/ + uint32_t PE_RespondsToDiscovSOP : 1u; /*!< Can respond successfully to a Discover Identity */ + uint32_t PE_AttemptsDiscovSOP : 1u; /*!< Can send a Discover Identity */ + uint32_t CAD_TryFeature : 2u; /*!< Not yet implemented */ + uint32_t CAD_AccesorySupport : 1u; /*!< Not yet implemented */ + uint32_t CAD_RoleToggle : 1u; /*!< If enabled allows the detection state machine switch Rp/Rd means toggle the presented role between source and sink */ + CAD_RP_Source_Current_Adv_Typedef CAD_DefaultResistor : 2u; /*!< Default RP resistor based on @ref CAD_RP_Source_Current_Adv_Typedef */ + uint32_t CAD_SNKToggleTime : 8u; /*!< Sink toggle time in ms */ + uint32_t CAD_SRCToggleTime : 8u; /*!< Source toggle time in ms */ +#if defined(USBPD_REV30_SUPPORT) + USBPD_PD3SupportTypeDef PE_PD3_Support; /*!< PD3 structure support flags based on @ref USBPD_PD3SupportTypeDef */ +#else + uint16_t reserved : 16u; /*!< Reserved bits */ +#endif /* USBPD_REV30_SUPPORT */ +#endif /*USBPDCORE_LIB_NO_PD*/ +} USBPD_SettingsTypeDef; + +/** + * @} + */ + +/** @defgroup USBPD_CORE_PARAMS_Exported_Structures USBPD CORE Params Exported Structures + * @brief USBPD Params Structure definition + * @{ + */ +typedef struct +{ + USBPD_SpecRev_TypeDef PE_SpecRevision : 2u; /*!< PE Specification revision */ + USBPD_PortPowerRole_TypeDef PE_PowerRole : 1u; /*!< PE Power role */ + USBPD_PortDataRole_TypeDef PE_DataRole : 1u; /*!< PE Data role */ + uint32_t PE_SwapOngoing : 1u; /*!< Power role swap ongoing flag */ + USBPD_VDMVersion_TypeDef VDM_Version : 1u; /*!< VDM version */ + CCxPin_TypeDef ActiveCCIs : 2u; /*!< Active CC line based on @ref CCxPin_TypeDef */ + USBPD_POWER_StateTypedef PE_Power : 3u; /*!< Power status based on @ref USBPD_POWER_StateTypedef */ + uint32_t DPM_Initialized : 1u; /*!< DPM initialized flag */ + uint32_t PE_IsConnected : 1u; /*!< USB-PD PE stack is connected to CC line */ + CCxPin_TypeDef VconnCCIs : 2u; /*!< VConn CC line based on @ref CCxPin_TypeDef */ + uint32_t VconnStatus : 1u; /*!< VConnStatus USBP_TRUE = vconn on USBPD_FALSE = vconn off */ + CAD_RP_Source_Current_Adv_Typedef RpResistor : 2u; /*!< RpResistor presented */ + CAD_SNK_Source_Current_Adv_Typedef SNKExposedRP_AtAttach : 2u; /*!< Exposed resistance from source at attach */ + +#if defined(USBPDCORE_VPD) + uint32_t VPDflag : 1u; /*!< VPD detection flag */ + uint32_t CAD_VPDStatus : 2u; /*!< CAD VPD status used between CAD and PE */ + uint32_t PE_VPDStatus : 2u; /*!< CAD VPD status used between CAD and PE */ +#else + uint32_t Reserved1 : 5u; /*!< Reserved bits */ +#endif /* USBPDCORE_VPD */ + + +#if defined(USBPD_REV30_SUPPORT) && defined(USBPDCORE_UNCHUNCKED_MODE) + uint32_t PE_UnchunkSupport: 1u; /*!< Unchunked support */ +#else + uint32_t Reserved2 : 1u; /*!< Reserved bits */ +#endif /* defined(USBPD_REV30_SUPPORT) && defined(USBPDCORE_UNCHUNCKED_MODE) */ + +#if defined(USBPDCORE_VCONN_SUPPORT) + USBPD_SpecRev_TypeDef CBL_SpecRevision: 2u; /*!< Cable Specification revision */ +#else + uint32_t Reserved3 : 2u; /*!< Reserved bits */ +#endif /* USBPDCORE_VCONN_SUPPORT */ + +#if defined(USBPDCORE_PECABLE) + uint32_t IsCableConnected: 1u; /*!< Is Cable connected */ + uint32_t Reserved4 : 3u; /*!< Reserved bits */ +#else + uint32_t Reserved4 : 4u; /*!< Reserved bits */ +#endif /* USBPDCORE_PECABLE */ +} USBPD_ParamsTypeDef; + +#if defined(USBPDCORE_USBDATA) +/** + * @brief Enter USB Data object + * + */ +typedef union +{ + uint32_t d32; + struct + { + uint32_t Reserved1 :13u; /*!< Reserved - Shall be set to zero */ + uint32_t HostPresent : 1u; /*!< Connected to a Host. */ + uint32_t TBTSupport : 1u; /*!< [TBT3] is supported by the host's USB4 Connection Manager */ + uint32_t DPSupport : 1u; /*!< [USB4] DP tunneling supported by the host */ + uint32_t PCISupport : 1u; /*!< [USB4] PCIe tunneling supported by the hosts */ + uint32_t CableCurrent : 2u; /*!< 00b = VBUS is not supported 01b = Reserved 10b = 3A 11b = 5A */ + uint32_t CableType : 2u; /*!< 00b: Passive, + 01b: Active Re-timer + 10b: Active Re-driver + 11b: Optically Isolatedt */ + uint32_t CableSpeed : 3u; /*!< 000b: [USB 2.0] only, no SuperSpeed support, + 001b: [USB 3.2] Gen1, + 010b: [USB 3.2] Gen2 and [USB4] Gen2 + 011b: [USB4] Gen3 */ + uint32_t Reserved2 : 1u; /*!< Reserved - Shall be set to zero */ + uint32_t USB3DRD : 1u; /*!< 0b: Not capable of operating as a [USB 3.2] Device + 1b: Capable of operating as a [USB 3.2] Device */ + uint32_t USB4DRD : 1u; /*!< 0b: Not capable of operating as a [USB 4] Device + 1b: Capable of operating as a [USB 4] Device */ + uint32_t Reserved3 : 1u; + uint32_t USBMode : 3u; /*!< 000b: [USB 2.0], 001b: [USB 3.2] 010b: [USB4] */ + uint32_t Reserved4 : 1u; + } b; +} USBPD_EnterUSBData_TypeDef; +#endif /* USBPDCORE_USBDATA */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* USBPD_DEF_H_ */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_tcpm.h b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_tcpm.h new file mode 100644 index 0000000..fbdde77 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_tcpm.h @@ -0,0 +1,318 @@ +/** + ****************************************************************************** + * @file usbpd_tcpm.h + * @author MCD Application Team + * @brief Header file containing functions prototypes of USBPD TCPM library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBPD_TCPM_H +#define __USBPD_TCPM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if defined(USBPDCORE_TCPM_SUPPORT) + +#include "string.h" +#include "usbpd_def.h" +#include "tcpc.h" + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_CORE + * @{ + */ + +/** @addtogroup USBPD_CORE_TCPM + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USBPD_CORE_TCPM_Exported_TypesDefinitions USBPD CORE TCPM Exported Types Definitions + * @{ + */ +/** + * @brief CallBacks exposed by the @ref USBPD_CORE_TCPM to the @ref USBPD_CORE_PRL + */ +typedef struct +{ + /** + * @brief Reports that a message has been received on a specified port. + * @param hport: The handle of the port + * @param Type: The type of the message received + * @retval None + * @note Received data are stored inside hport->pRxBuffPtr + */ + void (*USBPD_TCPM_MessageReceived)(uint8_t hport, USBPD_SOPType_TypeDef Type); + + /** + * @brief Reports to the PRL that a Reset received from channel. + * @param hport: The handle of the port + * @param Type: The type of reset performed + * @retval None + */ + void (*USBPD_TCPM_ResetIndication)(uint8_t hport, USBPD_SOPType_TypeDef Type); + + /** + * @brief Reports to the PRL that a Reset operation has been completed. + * @param hport: The handle of the port + * @param Type: The type of reset performed + * @retval None + */ + void (*USBPD_TCPM_ResetCompleted)(uint8_t hport, USBPD_SOPType_TypeDef Type); + + /** + * @brief Reports to the PRL that a Bist operation has been completed. + * @param hport: The handle of the port + * @param Type: The type of Bist performed + * @retval None + */ + void (*USBPD_TCPM_BistCompleted)(uint8_t hport, USBPD_BISTMsg_TypeDef bistmode); + + /** + * @brief USB-PD message sent callback from TCPC + * @param PortNum port number value + * @param Status Status of the transmission + * @retval None + */ + void (*USBPD_TCPM_MessageReceivedTC)(uint8_t PortNum, uint32_t status); + + /** + * @brief Reports to the PRL that an FRS has been detected. + * @param PortNum: The handle of the port + * @retval None + */ + void (*USBPD_PHY_FastRoleSwapReception)(uint8_t PortNum); + +} USBPD_PHY_Callbacks; + +/** + * @brief Initialization structure exposed by the @ref USBPD_CORE_TCPM to the @ref USBPD_CORE_PRL + */ +typedef struct +{ + uint8_t *pRxBuffer; /*!< Pointer to @ref USBPD_CORE_PRL RX Buffer for the current port */ + const USBPD_PHY_Callbacks *pCallbacks; /*!< TCPM Callbacks */ +} USBPD_TCPM_HandleTypeDef; +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USBPD_CORE_TCPM_Exported_Functions + * @{ + */ + +/** @defgroup USBPD_CORE_TCPM_Exported_Functions_Grp2 USBPD CORE TCPM Exported Functions to PRL + * @{ + */ +/** + * @brief Initialize TCPC devices + * @param PortNum Number of the port + * @param pCallbacks TCPM callbacks + * @param pRxBuffer Pointer on the RX buffer + * @param PowerRole Power role can be one of the following values: + * @arg @ref USBPD_PORTPOWERROLE_SNK + * @arg @ref USBPD_PORTPOWERROLE_SRC + * @param SupportedSOP Supported SOP + * @retval HAL status + */ +USBPD_StatusTypeDef USBPD_PHY_Init(uint8_t PortNum, const USBPD_PHY_Callbacks *pCallbacks, uint8_t *pRxBuffer, + USBPD_PortPowerRole_TypeDef PowerRole, uint32_t SupportedSOP); + +/** + * @brief Reset the PHY of a specified port. + * @param PortNum Number of the port. + * @retval None + */ +void USBPD_PHY_Reset(uint8_t PortNum); + +/** + * @brief function to set the supported SOP + * @param PortNum Number of the port. + * @param SOPSupported List of the supported SOP + * @retval None. + */ +void USBPD_PHY_SOPSupported(uint8_t PortNum, uint32_t SOPSupported); + +/** + * @brief De-initialize TCPC devices + * @param PortNum Number of the port + * @retval None + */ +void USBPD_TCPM_DeInit(uint8_t PortNum); + +/** + * @brief Get CC line for PD connection + * @param PortNum Number of the port + * @param CC1_Level Pointer of status of the CC1 line + * @param CC2_Level Pointer of status of the CC2 line + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_get_cc(uint32_t PortNum, uint32_t *CC1_Level, uint32_t *CC2_Level); + +/** + * @brief Set the polarity of the CC lines + * @param PortNum Number of the port + * @param Polarity Polarity + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_set_polarity(uint32_t PortNum, uint32_t Polarity); + +/** + * @brief Set power and data role et PD message header + * @param PortNum Number of the port + * @param PowerRole Power role + * @param DataRole Data role + * @param Specification PD Specification version + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_set_msg_header(uint32_t PortNum, USBPD_PortPowerRole_TypeDef PowerRole, + USBPD_PortDataRole_TypeDef DataRole, + USBPD_SpecRev_TypeDef Specification); + +/** + * @brief Enable or disable PD reception + * @param PortNum Number of the port + * @param Pull Value of the CC pin to configure based on @ref TCPC_CC_Pull_TypeDef + * @param State Activation or deactivation of RX + * @param SupportedSOP Supported SOP by PRL + * @param HardReset Hard reset status based on @ref TCPC_hard_reset + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_set_rx_state(uint32_t PortNum, TCPC_CC_Pull_TypeDef Pull, USBPD_FunctionalState State, + uint32_t SupportedSOP, TCPC_hard_reset HardReset); + +/** + * @brief Retrieve the PD message + * @param PortNum Number of the port + * @param Payload Pointer on the payload + * @param Type Pointer on the message type + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_get_message(uint32_t PortNum, uint8_t *Payload, uint8_t *Type); + +/** + * @brief Transmit the PD message + * @param PortNum Number of the port + * @param Type Message type + * @param pData Pointer on the data message + * @param RetryNumber Number of retry + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_transmit(uint32_t PortNum, USBPD_SOPType_TypeDef Type, const uint8_t *pData, + uint32_t RetryNumber); + +/** + * @brief Send bist pattern. + * @param PortNum Number of the port + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PHY_Send_BIST_Pattern(uint32_t PortNum); + +/** + * @brief Request a Reset on a specified port. + * @param PortNum Number of the port + * @param Type The type of reset (hard or cable reset). + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PHY_ResetRequest(uint8_t PortNum, USBPD_SOPType_TypeDef Type); + +/** + * @brief Request TCPC to enter a specific BIST test mode. + * @param PortNum Number of the port + * @param State Enable BIST carrier mode 2 + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_TCPM_Send_BIST_Pattern(uint8_t PortNum, USBPD_FunctionalState State); + +/** + * @brief function to set the SinkTxNg + * @param PortNum Number of the port. + * @retval none. + */ +void USBPD_PHY_SetResistor_SinkTxNG(uint8_t PortNum); + +/** + * @brief function to set the SinkTxOK + * @param PortNum Number of the port. + * @retval none. + */ +void USBPD_PHY_SetResistor_SinkTxOK(uint8_t PortNum); + +/** + * @brief function to check if SinkTxOK + * @param PortNum Number of the port. + * @retval USBPD_TRUE or USBPD_FALSE + */ +uint8_t USBPD_PHY_IsResistor_SinkTxOk(uint8_t PortNum); + +/** + * @brief Trigger in Fast role swap signalling + * @param PortNum Number of the port. + * @retval None + */ +void USBPD_PHY_FastRoleSwapSignalling(uint8_t PortNum); + +/** + * @brief Enable RX + * @param PortNum Number of the port. + * @retval None + */ +void USBPD_PHY_EnableRX(uint8_t PortNum); + +/** + * @brief Disable RX + * @param PortNum Number of the port. + * @retval None + */ +void USBPD_PHY_DisableRX(uint8_t PortNum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USBPDCORE_TCPM_SUPPORT */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __USBPD_TCPM_H */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_trace.h b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_trace.h new file mode 100644 index 0000000..3878960 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Core/inc/usbpd_trace.h @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file usbpd_trace.h + * @author MCD Application Team + * @brief Header file for usbpd_trace.c + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef USBPD_TRACE_H_ +#define USBPD_TRACE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_core.h" +#ifndef _STDIO +#include "stdio.h" +#endif /* _STDIO */ + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_CORE + * @{ + */ + +/** @addtogroup USBPD_CORE_TRACE + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported define -----------------------------------------------------------*/ +/** @defgroup USBPD_CORE_TRACE_Exported_Defines USBPD CORE TRACE Exported Defines + * @{ + */ +typedef enum +{ + TCPM_TRACE_CORE_ALERT, /*!< ALERT_TASK */ + TCPM_TRACE_ALERT, /*!< USBPD_TCPM_alert */ + TCPM_TRACE_ALERT_CLEAR, /*!< USBPD_TCPM_alert: tcpc_clear_alert */ + TCPM_TRACE_ALERT_GET_POWER_STATUS, /*!< USBPD_TCPM_alert: get_power_status */ + TCPM_TRACE_ALERT_GET_FAULT_STATUS, /*!< USBPD_TCPM_alert: get_fault_status */ + TCPM_TRACE_ALERT_SET_FAULT_STATUS, /*!< USBPD_TCPM_alert: set_fault_status */ + TCPM_TRACE_ALERT_READ_ALERT, /*!< USBPD_TCPM_alert: set_fault_status */ + TCPM_TRACE_HW_INIT, /*!< USBPD_TCPM_HWInit */ + TCPM_TRACE_SET_CC, /*!< USBPD_TCPM_set_cc */ + TCPM_TRACE_VBUS_GET_VOLTAGE, /*!< USBPD_TCPM_VBUS_GetVoltage */ + TCPM_TRACE_VBUS_IS_VSAFE0V, /*!< USBPD_TCPM_VBUS_IsVsafe0V */ + TCPM_TRACE_VBUS_IS_VSAFEEV, /*!< USBPD_TCPM_VBUS_IsVsafe5V */ + TCPM_TRACE_VBUS_ENABLE, /*!< USBPD_TCPM_VBUS_Enable */ + TCPM_TRACE_VBUS_DISABLE, /*!< USBPD_TCPM_VBUS_Disable */ + TCPM_TRACE_INIT, /*USBPD_PHY_Init*/ + TCPM_TRACE_DEINIT, /*USBPD_PHY_Deinit*/ + TCPM_TRACE_RESET, /*USBPD_PHY_Reset*/ + TCPM_TRACE_SOP_SUPPORTED, /*USBPD_PHY_SOPSupported*/ + TCPM_TRACE_GET_CC, /*USBPD_TCPM_get_cc*/ + TCPM_TRACE_SET_POLARITY, /*USBPD_TCPM_set_polarity*/ + TCPM_TRACE_SET_VCONN, /*USBPD_TCPM_set_vconn*/ + TCPM_TRACE_SET_MSG_HEADER, /*USBPD_TCPM_set_msg_header*/ + TCPM_TRACE_SET_RX_STATE, /*USBPD_TCPM_set_rx_state*/ + TCPM_TRACE_SET_GET_MESSAGE, /*USBPD_TCPM_get_message*/ + TCPM_TRACE_TRANSMIT, /*USBPD_TCPM_transmit*/ + TCPM_TRACE_RESET_REQUEST, /*USBPD_PHY_ResetRequest*/ + TCPM_TRACE_SEND_BIST, /*USBPD_PHY_Send_BIST_Pattern*/ + TCPM_TRACE_SEND_BIST_PATTERN, /*USBPD_TCPM_Send_BIST_Pattern*/ + TCPM_TRACE_SINK_TXNG, /*USBPD_PHY_SetResistor_SinkTxNG*/ + TCPM_TRACE_SINK_TXOK, /*USBPD_PHY_SetResistor_SinkTxOK*/ + TCPM_TRACE_SINK_IF_TXOK, /*USBPD_PHY_IsResistor_SinkTxOk*/ + TCPM_TRACE_FAST_ROLE_SWAP, /*USBPD_PHY_FastRoleSwapSignalling*/ + TCPM_TRACE_ENABLE_RX, /* tcpc_EnableRx */ + TCPM_TRACE_DISABLE_RX, /* tcpc_DisableRx */ + TCPM_TRACE_SET_PIN_ROLE, /* tcpc_tcpc_set_cc */ +} USBPD_TCPM_TRACE; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ +/** @defgroup USBPD_CORE_TRACE_Exported_Variables USBPD CORE TRACE Exported Variables + * @{ + */ +extern TRACE_ENTRY_POINT USBPD_Trace; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USBPD_CORE_TRACE_Exported_Functions USBPD CORE TRACE Exported Functions + * @{ + */ +/** + * @brief Initialize the TRACE module + * @retval None + */ +void USBPD_TRACE_Init(void); + +/** + * @brief DeInitialize the TRACE module + * @retval None + */ +void USBPD_TRACE_DeInit(void); + +/** + * @brief Add information in debug trace buffer + * @param Type Trace Type based on @ref TRACE_EVENT + * @param PortNum Port number value + * @param Sop SOP type + * @param Ptr Pointer on the data to send + * @param Size Size of the data to send + * @retval None. + */ +void USBPD_TRACE_Add(TRACE_EVENT Type, uint8_t PortNum, uint8_t Sop, uint8_t *Ptr, uint32_t Size); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* USBPD_CAD_H_ */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a b/Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a new file mode 100644 index 0000000..a0827fd Binary files /dev/null and b/Middlewares/ST/STM32_USBPD_Library/Core/lib/USBPDCORE_PD3_FULL_CM4_wc32.a differ diff --git a/Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c b/Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c new file mode 100644 index 0000000..741216f --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Core/src/usbpd_trace.c @@ -0,0 +1,213 @@ +/** + ****************************************************************************** + * @file usbpd_trace.c + * @author MCD Application Team + * @brief This file contains trace control functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#define USBPD_TRACE_C + +#include "usbpd_def.h" +#include "usbpd_core.h" +#include "usbpd_trace.h" +#ifdef _TRACE +#include "tracer_emb.h" +#endif /* _TRACE */ + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_CORE + * @{ + */ + +/** @addtogroup USBPD_CORE_TRACE + * @{ + */ + +/* Private enums -------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USBPD_CORE_TRACE_Private_Defines USBPD CORE TRACE Private Defines + * @{ + */ + +#define TRACE_SIZE_HEADER_TRACE 9u /* Type + Time x 2 + PortNum + Sop + Size */ + +#define TRACE_PORT_BIT_POSITION 5u /* Bit position of port number in TAG id */ + +#define TLV_SOF (uint8_t)0xFDu +#define TLV_EOF (uint8_t)0xA5u +#define TLV_SIZE_MAX 256u +#define TLV_HEADER_SIZE 3u /* Size of TLV header (TAG(1) + LENGTH(2) */ +#define TLV_SOF_SIZE 4u /* TLV_SOF * 4 */ +#define TLV_EOF_SIZE 4u /* TLV_EOF * 4 */ + +#define DEBUG_STACK_MESSAGE 0x12u +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup USBPD_CORE_TRACE_Private_Macros USBPD CORE TRACE Private Macros + * @{ + */ +#define TRACE_SET_TAG_ID(_PORT_, _TAG_) (((_PORT_) << TRACE_PORT_BIT_POSITION) | (_TAG_)) + +#define TRACER_EMB_WRITE_DATA(_POSITION_,_DATA_) do { \ + TRACER_EMB_WriteData((_POSITION_),(_DATA_));\ + (_POSITION_) = ((_POSITION_) + 1u); \ + } while(0) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USBPD_CORE_TRACE_Private_Variables USBPD CORE TRACE Private Variables + * @{ + */ +extern uint32_t HAL_GetTick(void); +extern void USBPD_DPM_TraceWakeUp(void); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup USBPD_CORE_TRACE_Exported_Functions + * @{ + */ +void USBPD_TRACE_Init(void) +{ +#if defined(_TRACE) + static const uint8_t OverFlow_String[] = + { + TLV_SOF, TLV_SOF, TLV_SOF, TLV_SOF, /* Buffer header */ + 0x32, /* Tag id */ + 0x0, 0x18, /* Length */ + 0x6, /* Type */ + 0x0, 0x0, 0x0, 0x0, /* Time */ + 0x0, /* PortNum */ + 0x0, /* SOP */ + 0x0, 0x0F, /* Size */ + 'T', 'R', 'A', 'C', 'E', ' ', 'O', 'V', 'E', 'R', '_', 'F', 'L', 'O', 'W', /* Data */ + TLV_EOF, TLV_EOF, TLV_EOF, TLV_EOF /* Buffer end */ + }; + + /* initialize tracer module */ + TRACER_EMB_Init(); + + /* Initialize PE trace */ + USBPD_PE_SetTrace(USBPD_TRACE_Add, 3u); + + /* Initialize the overflow detection */ + (void)TRACER_EMB_EnableOverFlow(OverFlow_String, (uint8_t)sizeof(OverFlow_String)); +#else + return; +#endif /* _TRACE */ +} + +void USBPD_TRACE_DeInit(void) +{ + /* Nothing to do */ + return; +} + +void USBPD_TRACE_Add(TRACE_EVENT Type, uint8_t PortNum, uint8_t Sop, uint8_t *Ptr, uint32_t Size) +{ +#if defined(_TRACE) + uint32_t _time; + int32_t _allocation; + uint16_t index; + + /* Get trace timing */ + _time = HAL_GetTick(); + + TRACER_EMB_Lock(); + + /* Data are encapsulate inside a TLV string*/ + /* Allocate buffer Size */ + _allocation = TRACER_EMB_AllocateBufer(Size + TRACE_SIZE_HEADER_TRACE + + TLV_HEADER_SIZE + TLV_SOF_SIZE + TLV_EOF_SIZE); + + /* Check allocation */ + if (_allocation != -1) + { + uint16_t _writepos = (uint16_t)_allocation; + + /* Copy SOF bytes */ + for (index = 0u; index < TLV_SOF_SIZE; index++) + { + TRACER_EMB_WRITE_DATA(_writepos, TLV_SOF); + } + /* Copy the TAG */ + TRACER_EMB_WRITE_DATA(_writepos, TRACE_SET_TAG_ID((PortNum + 1u), DEBUG_STACK_MESSAGE)); + /* Copy the LENGTH */ + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)((Size + TRACE_SIZE_HEADER_TRACE) >> 8u)); + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)(Size + TRACE_SIZE_HEADER_TRACE)); + + /* Trace type */ + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)Type); + + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)_time); + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)(_time >> 8u)); + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)(_time >> 16u)); + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)(_time >> 24u)); + + TRACER_EMB_WRITE_DATA(_writepos, PortNum); + TRACER_EMB_WRITE_DATA(_writepos, Sop); + + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)(Size >> 8u)); + TRACER_EMB_WRITE_DATA(_writepos, (uint8_t)Size); + + /* initialize the Ptr for Read/Write */ + for (index = 0u; index < Size; index++) + { + TRACER_EMB_WRITE_DATA(_writepos, Ptr[index]); + } + + /* Copy EOF bytes */ + for (index = 0u; index < TLV_EOF_SIZE; index++) + { + TRACER_EMB_WRITE_DATA(_writepos, TLV_EOF); + } + } + + TRACER_EMB_UnLock(); + + TRACER_EMB_SendData(); +#else + return; +#endif /* _TRACE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/LICENSE.txt b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/LICENSE.txt new file mode 100644 index 0000000..e66295c --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/LICENSE.txt @@ -0,0 +1,86 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the SLA0044 license shall apply and are fully reproduced below: + +SLA0044 Rev5/February 2018 + +Software license agreement + +ULTIMATE LIBERTY SOFTWARE LICENSE AGREEMENT + +BY INSTALLING, COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE +OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS +INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES +(STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON +BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES +TO BE BOUND BY THIS SOFTWARE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights, the redistribution, +reproduction and use in source and binary forms of the software or any part +thereof, with or without modification, are permitted provided that the following +conditions are met: + +1. Redistribution of source code (modified or not) must retain any copyright +notice, this list of conditions and the disclaimer set forth below as items 10 +and 11. + +2. Redistributions in binary form, except as embedded into microcontroller or +microprocessor device manufactured by or for STMicroelectronics or a software +update for such device, must reproduce any copyright notice provided with the +binary code, this list of conditions, and the disclaimer set forth below as +items 10 and 11, in documentation and/or other materials provided with the +distribution. + +3. Neither the name of STMicroelectronics nor the names of other contributors to +this software may be used to endorse or promote products derived from this +software or part thereof without specific written permission. + +4. This software or any part thereof, including modifications and/or derivative +works of this software, must be used and execute solely and exclusively on or in +combination with a microcontroller or microprocessor device manufactured by or +for STMicroelectronics. + +5. No use, reproduction or redistribution of this software partially or totally +may be done in any manner that would subject this software to any Open Source +Terms. “Open Source Terms” shall mean any open source license which requires as +part of distribution of software that the source code of such software is +distributed therewith or otherwise made available, or open source license that +substantially complies with the Open Source definition specified at +www.opensource.org and any other comparable open source license such as for +example GNU General Public License (GPL), Eclipse Public License (EPL), Apache +Software License, BSD license or MIT license. + +6. STMicroelectronics has no obligation to provide any maintenance, support or +updates for the software. + +7. The software is and will remain the exclusive property of STMicroelectronics +and its licensors. The recipient will not take any action that jeopardizes +STMicroelectronics and its licensors' proprietary rights or acquire any rights +in the software, except the limited rights specified hereunder. + +8. The recipient shall comply with all applicable laws and regulations affecting +the use of the software or any part thereof including any applicable export +control law or regulation. + +9. Redistribution and use of this software or any part thereof other than as +permitted under this license is void and will automatically terminate your +rights under this license. + +10. THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS, WHICH ARE +DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL +STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +11. EXCEPT AS EXPRESSLY PERMITTED HEREUNDER, NO LICENSE OR OTHER RIGHTS, WHETHER +EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY +RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_cad_hw_if.h b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_cad_hw_if.h new file mode 100644 index 0000000..6851051 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_cad_hw_if.h @@ -0,0 +1,90 @@ +/** + ****************************************************************************** + * @file usbpd_cad_hw_if.h + * @author MCD Application Team + * @brief This file contains the headers of usbpd_cad_hw_if.c for Cable Attach-Detach + * controls. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef __USBPD_CAD_HW_IF_H_ +#define __USBPD_CAD_HW_IF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_core.h" + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_DEVICE + * @{ + */ + +/** @addtogroup USBPD_DEVICE_CAD_HW_IF + * @{ + */ + + +/* Exported types ------------------------------------------------------------*/ +/* Exported define -----------------------------------------------------------*/ +#if defined(_LOW_POWER) || defined(USBPDM1_VCC_FEATURE_ENABLED) +#define CAD_DELAY_READ_CC_STATUS (300U) +#endif /* _LOW_POWER || USBPDM1_VCC_FEATURE_ENABLED */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +#if defined(USBPDCORE_DRP) || defined(USBPDCORE_SRC) +/* Keep for legacy */ +uint32_t CAD_Set_ResistorRp(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RpValue); +#endif /* USBPDCORE_DRP || USBPDCORE_SRC */ + +/** @addtogroup USBPD_DEVICE_CAD_HW_IF_Exported_Functions + * @{ + */ +void CAD_Init(uint8_t PortNum, USBPD_SettingsTypeDef *Settings, + USBPD_ParamsTypeDef *Params, void (*PtrWakeUp)(void)); +uint32_t CAD_StateMachine(uint8_t PortNum, USBPD_CAD_EVENT *Event, CCxPin_TypeDef *CCXX); +void CAD_Enter_ErrorRecovery(uint8_t PortNum); +#if defined(USBPDCORE_DRP) || defined(USBPDCORE_SRC) +uint32_t CAD_SRC_Set_ResistorRp(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RpValue); +#endif /* USBPDCORE_DRP || USBPDCORE_SRC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_CAD_HW_IF_H_ */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw.h b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw.h new file mode 100644 index 0000000..73ab9fe --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw.h @@ -0,0 +1,43 @@ +/** + ****************************************************************************** + * @file usbpd_hw.h + * @author MCD Application Team + * @brief This file contains interface hw control. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __USBPD_HW_H_ +#define __USBPD_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Variable containing ADC conversions results */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +UCPD_TypeDef *USBPD_HW_GetUSPDInstance(uint8_t PortNum); +DMA_Channel_TypeDef *USBPD_HW_Init_DMARxInstance(uint8_t PortNum); +void USBPD_HW_DeInit_DMARxInstance(uint8_t PortNum); +DMA_Channel_TypeDef *USBPD_HW_Init_DMATxInstance(uint8_t PortNum); +void USBPD_HW_DeInit_DMATxInstance(uint8_t PortNum); +uint32_t USBPD_HW_GetRpResistorValue(uint8_t Portnum); +void USBPD_HW_SetFRSSignalling(uint8_t Portnum, uint8_t cc); + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_HW_H_ */ diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw_if.h b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw_if.h new file mode 100644 index 0000000..5ecaaa9 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_hw_if.h @@ -0,0 +1,380 @@ +/** + ****************************************************************************** + * @file usbpd_hw_if.h + * @author MCD Application Team + * @brief This file contains the headers of usbpd_hw_if.h for USB-PD Hardware + Interface layer. This file is specific for each device. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __USBPD_HW_IF_H_ +#define __USBPD_HW_IF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_def.h" +#include "usbpd_devices_conf.h" + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_DEVICE + * @{ + */ + +/** @addtogroup USBPD_DEVICE_HW_IF + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +/** @defgroup USBPD_DEVICE_DEVICE_HW_IF_Exported_Types USBPD DEVICE HW_IF Exported Types + * @{ + */ + +/** + * @brief Enum used to get the status of decoding + */ +typedef enum +{ + USBPD_PHY_RX_STATUS_NONE, + USBPD_PHY_RX_STATUS_OK, + USBPD_PHY_RX_STATUS_SOP_DETECTING, + USBPD_PHY_RX_STATUS_DATA, + USBPD_PHY_RX_STATUS_MESSAGE_READY, + USBPD_PHY_RX_STATUS_ERROR, + USBPD_PHY_RX_STATUS_ERROR_UNSUPPORTED_SOP, + USBPD_PHY_RX_STATUS_ERROR_INVALID_SOP, + USBPD_PHY_RX_STATUS_ERROR_INVALID_SYMBOL, + USBPD_PHY_RX_STATUS_ERROR_EOP_NOT_FOUND, + USBPD_PHY_RX_STATUS_ERROR_CRC_FAILED, +} +USBPD_PHY_RX_Status_TypeDef; + +/** + * @brief CallBacks exposed by the HW_IF to the PHY + */ +typedef struct +{ + /** + * @brief The message transfer has been completed + * @param PortNum Port number + * @param Status (0 means OK) + * @retval None + */ + void (*USBPD_HW_IF_TxCompleted)(uint8_t PortNum, uint32_t Status); + + /** + * @brief Bist data sent callback from PHY_HW_IF + * @param PortNum Port number + * @param bistmode: Bist mode + * @retval None + */ + void (*USBPD_HW_IF_BistCompleted)(uint8_t PortNum, USBPD_BISTMsg_TypeDef bistmode); + + /** + * @brief The reception phase of an hard reset is completed notify it. + * @param PortNum Port number + * @param SOPType SOP Message Type based on @ref USBPD_SOPType_TypeDef + * @retval None + */ + void (*USBPD_HW_IF_RX_ResetIndication)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); + + /** + * @brief The reception phase of the current message is completed and notify it. + * @param PortNum Port number + * @param MsgType Message Type + * @retval None + */ + void (*USBPD_HW_IF_RX_Completed)(uint8_t PortNum, uint32_t MsgType); + + /** + * @brief The emission of HRST has been completed. + * @param PortNum Port number + * @retval None + */ + void (*USBPD_HW_IF_TX_HardResetCompleted)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); + + /** + * @brief FRS reception. + * @param PortNum Port number + * @retval None + */ + void (*USBPD_HW_IF_TX_FRSReception)(uint8_t PortNum); + +} USBPD_HW_IF_Callbacks_TypeDef; + +/** @defgroup USBPD_PORT_HandleTypeDef USB PD handle Structure definition for USBPD_PHY_HW_IF + * @brief USBPD PORT handle Structure definition + * @{ + */ +typedef struct +{ + UCPD_TypeDef *husbpd; /*!< UCPD Handle parameters */ + DMA_Channel_TypeDef *hdmatx; /*!< Tx DMA Handle parameters */ + DMA_Channel_TypeDef *hdmarx; /*!< Rx DMA Handle parameters */ + + USBPD_SettingsTypeDef *settings; + USBPD_ParamsTypeDef *params; + USBPD_HW_IF_Callbacks_TypeDef cbs; /*!< USBPD_PHY_HW_IF callbacks */ + + void (*USBPD_CAD_WakeUp)(void); /*!< function used to wakeup cad task */ + + uint8_t *ptr_RxBuff; /*!< Pointer to Raw Rx transfer Buffer */ + + CCxPin_TypeDef CCx; /*!< CC pin used for communication */ + __IO uint8_t RXStatus; /*!< Tracks the reception of a message to forbid any new + TX transaction until message completion */ +} USBPD_PORT_HandleTypeDef; + +extern USBPD_PORT_HandleTypeDef Ports[USBPD_PORT_COUNT]; + +/** + * @} + */ + +/** + * @} + */ + +/* Exported define -----------------------------------------------------------*/ + +/** @defgroup USBPD_DEVICE_DEVICE_HW_IF_Exported_Defines USBPD DEVICE HW_IF Exported Defines + * @{ + */ + +#define SIZE_MAX_PD_TRANSACTION_CHUNK 30u +#define SIZE_MAX_PD_TRANSACTION_UNCHUNK (260u + 4u) + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USBPD_DEVICE_DEVICE_HW_IF_Exported_Functions USBPD DEVICE HW_IF Exported Functions + * @{ + */ + +/** + * @brief Enable the interrupt for the reception. + * @param PortNum The handle of the port. + * @retval None + */ +void USBPDM1_RX_EnableInterrupt(uint8_t PortNum); + +/** + * @brief stop bist carrier mode 2. + * @param PortNum The port handle. + * @retval None + */ +void USBPD_HW_IF_StopBISTMode2(uint8_t PortNum); + +/** + * @brief Initialize specific peripheral for the APP. + * @retval None + */ +void USBPD_HW_IF_GlobalHwInit(void); + +/** + * @brief Send a Buffer . + * @note The data will be converted in bmc and send through the line + * @param PortNum The port handle. + * @param Type SOP Message Type based on @ref USBPD_SOPType_TypeDef + * @param pBuffer Data buffer to be transmitted + * @param Bitsize The number of bits to be transmitted + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_HW_IF_SendBuffer(uint8_t PortNum, USBPD_SOPType_TypeDef Type, uint8_t *pBuffer, + uint32_t Bitsize); + +#if defined(_SRC) || defined(_DRP) +/** + * @brief Enable the VBUS on a specified port. + * @param PortNum The port handle. + * @param State ENABLE or DISABLE. + * @param Cc CC pin based on @ref CCxPin_TypeDef + * @param VconnState VCONN State activation + * @param role The role of the port. + * @retval USBPD status + */ +USBPD_StatusTypeDef HW_IF_PWR_Enable(uint8_t PortNum, USBPD_FunctionalState State, CCxPin_TypeDef Cc, + uint32_t VconnState, USBPD_PortPowerRole_TypeDef role); +#endif /* _SRC || _DRP */ + +/** + * @brief Retrieve the VBUS status for a specified port. + * @param PortNum The port handle. + * @retval FunctionalState + */ +USBPD_FunctionalState HW_IF_PWR_VBUSIsEnabled(uint8_t PortNum); + +/** + * @brief Set the VBUS voltage level on a specified port. + * @param PortNum The port handle. + * @param Voltage voltage value to be set. + * @retval USBPD status + */ +USBPD_StatusTypeDef HW_IF_PWR_SetVoltage(uint8_t PortNum, uint16_t Voltage); + +/** + * @brief Get the voltage level on a specified port. + * @param PortNum The port handle. + * @retval The voltage value + */ +uint16_t HW_IF_PWR_GetVoltage(uint8_t PortNum); + +/** + * @brief Get the current level on a specified port. + * @param PortNum The port handle. + * @retval The current value + */ +int16_t HW_IF_PWR_GetCurrent(uint8_t PortNum); + +/** + * @brief Connect the Rp resistors on the CC lines + * @param PortNum The port handle. + * @retval none + */ +void USBPDM1_AssertRp(uint8_t PortNum); + +/** + * @brief Disconnect the Rp resistors on the CC lines + * @param PortNum The port handle. + * @retval none + */ +void USBPDM1_DeAssertRp(uint8_t PortNum); + +/** + * @brief Connect the Rd resistors on the CC lines + * @param PortNum The port handle. + * @retval none + */ +void USBPDM1_AssertRd(uint8_t PortNum); + +/** + * @brief Disconnect the Rd resistors on the CC lines + * @param PortNum The port handle. + * @retval none + */ +void USBPDM1_DeAssertRd(uint8_t PortNum); + +/** + * @brief Set the CCx pin. + * @param PortNum The port handle. + * @param cc Specify the ccx to be selected. + * @retval None + */ +void USBPDM1_Set_CC(uint8_t PortNum, CCxPin_TypeDef cc); + +/** + * @brief Sends the BIST pattern + * @param PortNum The port handle. + * @retval none + */ +void USBPD_HW_IF_Send_BIST_Pattern(uint8_t PortNum); + +/** + * @brief Sends a detachemnt signal. + * @param PortNum The port handle. + * @retval none + */ +void HW_SignalDetachment(uint8_t PortNum); + +/** + * @brief Sends an Attachment signal. + * @param PortNum The port handle. + * @param cc the PD pin. + * @retval none + */ +void HW_SignalAttachement(uint8_t PortNum, CCxPin_TypeDef cc); + +/** + * @brief Set SinkTxNG resistor. + * @param PortNum The port handle. + * @retval none + */ +void USBPD_HW_IF_SetResistor_SinkTxNG(uint8_t PortNum); + +/** + * @brief Set SinkTxOk resistor. + * @param PortNum The port handle. + * @retval none + */ +void USBPD_HW_IF_SetResistor_SinkTxOK(uint8_t PortNum); + +/** + * @brief Is SinkTxOk resistor. + * @param PortNum The port handle. + * @retval TRUE FALSE + */ +uint8_t USBPD_HW_IF_IsResistor_SinkTxOk(uint8_t PortNum); + +/** + * @brief send a Fast Role swap signalling. + * @param PortNum The port handle. + * @retval None + */ +void USBPD_HW_IF_FastRoleSwapSignalling(uint8_t PortNum); + +/** + * @brief enter in error recovery state. + * @param PortNum The port handle. + * @retval None + */ +void USBPDM1_EnterErrorRecovery(uint8_t PortNum); + + +void USBPD_PORT0_IRQHandler(void); +void USBPD_PORT1_IRQHandler(void); + +/** + * @brief Enable RX + * @param PortNum The port handle. + * @retval None + */ +void USBPD_HW_IF_EnableRX(uint8_t PortNum); + +/** + * @brief Disable RX + * @param PortNum The port handle. + * @retval None + */ +void USBPD_HW_IF_DisableRX(uint8_t PortNum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_HW_IF_H_ */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_phy.h b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_phy.h new file mode 100644 index 0000000..29f95fb --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_phy.h @@ -0,0 +1,153 @@ +/** + ****************************************************************************** + * @file usbpd_phy.h + * @author MCD Application Team + * @brief This file contains the headers of usbpd_phy.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __USBPD_PHY_H_ +#define __USBPD_PHY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_DEVICE + * @{ + */ + +/** @addtogroup USBPD_DEVICE_PHY + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +/** @defgroup USBPD_DEVICE_PHY_Exported_TypeDef USBPD DEVICE PHY Exported TypeDef + * @{ + */ +/** + * @brief CallBacks exposed by the @ref USBPD_DEVICE_PHY to the USBPD_CORE_PRL + */ +typedef struct +{ + /** + * @brief Reports that a message has been received on a specified port. + * @note Received data are stored inside PortNum->pRxBuffPtr + * function called in the interrupt context + * @param PortNum The handle of the port + * @param Type The type of the message received @ref USBPD_SOPType_TypeDef + * @retval None + */ + void (*USBPD_PHY_MessageReceived)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); + + /** + * @brief Reports to the PRL that a Reset received from channel. + * @param PortNum The handle of the port + * @param Type The type of reset performed @ref USBPD_SOPTYPE_HARD_RESET or @ref USBPD_SOPTYPE_CABLE_RESET + * @retval None + */ + void (*USBPD_PHY_ResetIndication)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); + + /** + * @brief Reports to the PRL that a Reset operation has been completed. + * @param PortNum The handle of the port + * @param Type The type of reset performed @ref USBPD_SOPTYPE_HARD_RESET or @ref USBPD_SOPTYPE_CABLE_RESET + * @retval None + */ + void (*USBPD_PHY_ResetCompleted)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); + + /** + * @brief Reports to the PRL that a Bist operation has been completed. + * @param PortNum The handle of the port + * @param Type The type of Bist performed @ref USBPD_BISTMsg_TypeDef + * @retval None + */ + void (*USBPD_PHY_BistCompleted)(uint8_t PortNum, USBPD_BISTMsg_TypeDef bistmode); + + /** + * @brief Reports to the PRL that a tx operation has been completed. + * @param PortNum: The handle of the port + * @param Status: 0 if no error else error + * @retval None + */ + void (*USBPD_PHY_TxCompleted)(uint8_t PortNum, uint32_t Status); + + /** + * @brief Reports to the PRL that an FRS has been detected. + * @param PortNum: The handle of the port + * @retval None + */ + void (*USBPD_PHY_FastRoleSwapReception)(uint8_t PortNum); + +} USBPD_PHY_Callbacks; + +/** + * @} + */ + +/* Exported define -----------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup USBPD_DEVICE_PHY_Exported_Functions + * @{ + */ +USBPD_StatusTypeDef USBPD_PHY_Init(uint8_t PortNum, const USBPD_PHY_Callbacks *cbs, uint8_t *pRxBuffer, + USBPD_PortPowerRole_TypeDef role, uint32_t SupportedSOP); +void USBPD_PHY_Reset(uint8_t PortNum); +uint16_t USBPD_PHY_GetRetryTimerValue(uint8_t PortNum); +uint16_t USBPD_PHY_GetMinGOODCRCTimerValue(uint8_t PortNum); + +USBPD_StatusTypeDef USBPD_PHY_ResetRequest(uint8_t PortNum, USBPD_SOPType_TypeDef Type); +USBPD_StatusTypeDef USBPD_PHY_SendMessage(uint8_t PortNum, USBPD_SOPType_TypeDef Type, uint8_t *pBuffer, uint16_t Size); +USBPD_StatusTypeDef USBPD_PHY_Send_BIST_Pattern(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_PHY_ExitTransmit(uint8_t PortNum, USBPD_SOPType_TypeDef BistType); +void USBPD_PHY_SetResistor_SinkTxNG(uint8_t PortNum); +void USBPD_PHY_SetResistor_SinkTxOK(uint8_t PortNum); +uint8_t USBPD_PHY_IsResistor_SinkTxOk(uint8_t PortNum); +void USBPD_PHY_FastRoleSwapSignalling(uint8_t PortNum); +void USBPD_PHY_SOPSupported(uint8_t PortNum, uint32_t SOPSupported); + +void USBPD_PHY_EnableRX(uint8_t PortNum); +void USBPD_PHY_DisableRX(uint8_t PortNum); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_PHY_H_ */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_timersserver.h b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_timersserver.h new file mode 100644 index 0000000..7ba8747 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc/usbpd_timersserver.h @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file usbpd_timersserver.h + * @author MCD Application Team + * @brief This file contains the headers of usbpd_timerserver.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef __USBPD_TIMERSSERVER_H_ +#define __USBPD_TIMERSSERVER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_DEVICE + * @{ + */ + +/** @addtogroup USBPD_DEVICE_TIMESERVER + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +typedef enum +{ + TIM_PORT0_CRC, + TIM_PORT0_RETRY, + TIM_PORT1_CRC, + TIM_PORT1_RETRY, + TIM_MAX +} +TIM_identifier; + +#define TIM_MAX_TIME 10000u /*time in us, means 10 ms */ +/* Exported types ------------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +void USBPD_TIM_Init(void); +void USBPD_TIM_DeInit(void); +void USBPD_TIM_Start(TIM_identifier Id, uint32_t TimeUs); +uint32_t USBPD_TIM_IsExpired(TIM_identifier Id); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_TIMERSSERVER_H_ */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c new file mode 100644 index 0000000..9fba1de --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_cad_hw_if.c @@ -0,0 +1,1944 @@ +/** + ****************************************************************************** + * @file usbpd_cad_hw_if.c + * @author MCD Application Team + * @brief This file contains power hardware interface cad functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#define USBPD_CAD_HW_IF_C +#include "usbpd_devices_conf.h" +#include "usbpd_hw.h" +#include "usbpd_def.h" +#include "usbpd_cad_hw_if.h" +#include "usbpd_hw_if.h" +#if defined(_TRACE) +#include "usbpd_trace.h" +#endif /* _TRACE*/ +#include "string.h" + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_DEVICE + * @{ + */ + +/** @addtogroup USBPD_DEVICE_CAD_HW_IF + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/** + * @brief CAD State Machine function pointer + * @{ + */ +typedef uint32_t CAD_StateMachinePtr(uint8_t PortNum, USBPD_CAD_EVENT *Event, CCxPin_TypeDef *CCXX); + +/** + * @brief CAD State value @ref USBPD_DEVICE_CAD_HW_IF + * @{ + */ +typedef enum +{ + USBPD_CAD_STATE_RESET = 0U, /*!< USBPD CAD State Reset */ + USBPD_CAD_STATE_DETACHED = 1U, /*!< USBPD CAD State No cable detected */ + USBPD_CAD_STATE_ATTACHED_WAIT = 2U, /*!< USBPD CAD State Port partner detected */ + USBPD_CAD_STATE_ATTACHED = 3U, /*!< USBPD CAD State Port partner attached */ +#if defined(_DRP) || defined(_SRC) + USBPD_CAD_STATE_EMC = 4U, /*!< USBPD CAD State Electronically Marked Cable detected */ + USBPD_CAD_STATE_ATTEMC = 5U, /*!< USBPD CAD State Port Partner detected through EMC */ +#if defined(_ACCESSORY_SRC) + USBPD_CAD_STATE_DEBUG = 7U, /*!< USBPD CAD State Debug detected */ + USBPD_CAD_STATE_ACCESSORY = 6U, /*!< USBPD CAD State Accessory detected */ +#endif /* _ACCESSORY_SRC */ +#endif /* _DRP || _SRC */ + USBPD_CAD_STATE_SWITCH_TO_SRC = 8U, /*!< USBPD CAD State switch to Source */ + USBPD_CAD_STATE_SWITCH_TO_SNK = 9U, /*!< USBPD CAD State switch to Sink */ + USBPD_CAD_STATE_UNKNOW = 10U, /*!< USBPD CAD State unknown */ + USBPD_CAD_STATE_DETACH_SRC = 11U, + USBPD_CAD_STATE_ERRORRECOVERY = 12U, /*!< USBPD CAD State error recovery */ + USBPD_CAD_STATE_ERRORRECOVERY_EXIT = 13U, /*!< USBPD CAD State to exit error recovery */ +#if defined(_SNK) && defined(_ACCESSORY_SNK) + USBPD_CAD_STATE_UNATTACHED_ACCESSORY = 14U, /*!< USBPD CAD State Unattached.Accessory */ + USBPD_CAD_STATE_AUDIO_ACCESSORY = 15U, /*!< USBPD CAD State Wait detached after Accessory detection */ +#endif /* _SNK && _ACCESSORY_SNK */ + USBPD_CAD_STATE_ATTACHED_ACCESSORY_WAIT = 16U, +#if defined(USBPDCORE_VPD) + USBPD_CAD_STATE_POWERED_ACCESSORY = 17U, + USBPD_CAD_STATE_UNSUPPORTED_ACCESSORY = 18U, + USBPD_CAD_STATE_CTVPD_UNATTACHED = 19U, + USBPD_CAD_STATE_CTVPD_ATTACHED = 20U +#endif /* USBPDCORE_VPD */ +} USBPD_CAD_STATE; +/** + * @} + */ + +/** + * @brief USB PD CC lines HW condition + */ +typedef enum +{ + HW_Detachment = 0x00UL, /*!< Nothing attached */ + HW_Attachment = 0x01UL, /*!< Sink attached */ + HW_PwrCable_NoSink_Attachment = 0x02UL, /*!< Powered cable without Sink attached */ + HW_PwrCable_Sink_Attachment = 0x03UL, /*!< Powered cable with Sink or VCONN-powered Accessory attached */ + HW_Debug_Attachment = 0x04UL, /*!< Debug Accessory Mode attached */ + HW_AudioAdapter_Attachment = 0x05UL, /*!< Audio Adapter Accessory Mode attached */ +} CAD_HW_Condition_TypeDef; + +/** + * @brief CAD State value @ref USBPD_DEVICE_CAD_HW_IF + * @{ + */ +typedef struct +{ + CCxPin_TypeDef cc : 2; + CAD_HW_Condition_TypeDef CurrentHWcondition : 3; + uint32_t CAD_tDebounce_flag : 1; + uint32_t CAD_tDebounceAcc_flag : 1; + uint32_t CAD_ErrorRecoveryflag : 1; + uint32_t CAD_ResistorUpdateflag : 1; + USBPD_CAD_STATE cstate : 5; /* Current state */ + uint32_t CAD_Accessory_SRC : 1; + uint32_t CAD_Accessory_SNK : 1; + uint32_t reserved : 1; + USBPD_CAD_STATE pstate : 5; /* Previous state */ +#if defined(USBPDCORE_VPD) + uint32_t CAD_VPD_SRC : 1; + uint32_t CAD_VPD_SNK : 1; + uint32_t reserved2 : 8; +#else + uint32_t reserved2 : 10; +#endif /* USBPDCORE_VPD */ + +#if defined(_DRP) || defined(_ACCESSORY_SNK) + uint32_t CAD_tToggle_start; +#endif /* _DRP */ + uint32_t CAD_tDebounce_start; /* Variable used for attach or detach debounce timers */ + CAD_StateMachinePtr *CAD_PtrStateMachine; +} CAD_HW_HandleTypeDef; +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +#define CAD_TPDDEBOUNCE_THRESHOLD 12u /**< tPDDebounce threshold between 10 to 20ms */ +#define CAD_TCCDEBOUNCE_THRESHOLD 120u /**< tCCDebounce threshold between 100 to 200ms */ +#define CAD_TSRCDISCONNECT_THRESHOLD 2u /**< tSRCDisconnect detach threshold between 0 to 20ms */ +#define CAD_INFINITE_TIME 0xFFFFFFFFu /**< infinite time to wait a new interrupt event */ +#define CAD_TERROR_RECOVERY_TIME 26u /**< tErrorRecovery min 25ms */ +#define CAD_DEFAULT_TIME 2u /**< default transition timing of the state machine */ +#define CAD_ACCESSORY_TOGGLE 40u /**< toggle time for snk accessory detection */ +#define CAD_TVPDDETACH 10u /**< tVPDDetach timing between 10 and 20 ms */ + +#if defined(_DRP) || defined(_SRC) +#define CAD_DETACH_POLLING 40u +#elif defined(_SNK) +#define CAD_DETACH_POLLING 100u +#endif /* _DRP || _SRC */ + +#if defined(_LOW_POWER) +#define CAD_VBUS_POLLING_TIME 38u +#else +#define CAD_VBUS_POLLING_TIME 10u +#endif /* _LOW_POWER */ + +/* Private macro -------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ +/* Handle to manage the detection state machine */ +static CAD_HW_HandleTypeDef CAD_HW_Handles[USBPD_PORT_COUNT]; + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USBPD_DEVICE_CAD_HW_IF_Private_Functions USBPD DEVICE_CAD HW IF Private Functions + * @{ + */ +#if defined(_DRP) || defined(_SRC) +static void CAD_Check_HW_SRC(uint8_t PortNum); +#endif /* _DRP || _SRC */ + +#if defined(_DRP) || defined(_SNK) +static uint32_t ManageStateAttachedWait_SNK(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +static uint32_t ManageStateAttached_SNK(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +static uint32_t ManageStateDetached_SNK(uint8_t PortNum); +static void CAD_Check_HW_SNK(uint8_t PortNum); +#endif /* _DRP || _SNK */ + +#if defined(_DRP) +static uint32_t ManageStateAttachedWait_DRP(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +static uint32_t ManageStateAttached_DRP(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +#endif /* _DRP */ + +#if defined(_DRP) || defined(_SRC) +static uint32_t ManageStateAttachedWait_SRC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +#endif /* _DRP || _SRC || (_ACCESSORY && _SNK) */ + +#if defined(_SRC) || defined(_DRP) +static uint32_t ManageStateDetached_SRC(uint8_t PortNum); +#endif /* _SRC */ + +#if defined(_DRP) || defined(_SRC) +static uint32_t ManageStateEMC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +static uint32_t ManageStateAttached_SRC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +#endif /* _DRP || _SRC */ + +#if defined(_DRP) +static uint32_t ManageStateDetached_DRP(uint8_t PortNum); +#endif /* _DRP */ + + +#if defined(_SNK) +static uint32_t CAD_StateMachine_SNK(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +#endif /* _SNK */ + +#if defined(_SRC) +static uint32_t CAD_StateMachine_SRC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +#endif /* _SRC */ + +#if defined(_DRP) +static uint32_t CAD_StateMachine_DRP(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX); +#endif /* _DRP */ + + +#if defined(TCPP0203_SUPPORT) +void CAD_HW_IF_VBUSDetectCallback(uint32_t PortNum, + USBPD_PWR_VBUSConnectionStatusTypeDef VBUSConnectionStatus); +#endif /* TCPP0203_SUPPORT */ + +/** + * @} + */ + +/** @defgroup USBPD_DEVICE_CAD_HW_IF_Exported_Functions USBPD DEVICE_CAD HW IF Exported Functions + * @{ + */ + +/** + * @brief Function to initialize the cable detection state machine + * @param PortNum Port number + * @param pSettings Pointer on PD settings based on @ref USBPD_SettingsTypeDef + * @param pParams Pointer on PD parameters based on @ref USBPD_ParamsTypeDef + * @param WakeUp Wake-up callback function used for waking up CAD + * @retval None + */ +void CAD_Init(uint8_t PortNum, USBPD_SettingsTypeDef *pSettings, USBPD_ParamsTypeDef *pParams, void (*WakeUp)(void)) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + LL_UCPD_InitTypeDef settings; + + Ports[PortNum].params = pParams; + Ports[PortNum].settings = pSettings; + Ports[PortNum].params->RpResistor = Ports[PortNum].settings->CAD_DefaultResistor; + Ports[PortNum].params->SNKExposedRP_AtAttach = vRd_Undefined; + + /* Reset handle */ + memset(_handle, 0, sizeof(CAD_HW_HandleTypeDef)); + + /* Register CAD wake up callback */ + Ports[PortNum].USBPD_CAD_WakeUp = WakeUp; + + /* Initialize the USBPD_IP */ + Ports[PortNum].husbpd = USBPD_HW_GetUSPDInstance(PortNum); + + /* Initialize UCPD */ + LL_UCPD_StructInit(&settings); + (void)LL_UCPD_Init(Ports[PortNum].husbpd, &settings); + LL_UCPD_SetRxOrderSet(Ports[PortNum].husbpd, + LL_UCPD_ORDERSET_SOP | LL_UCPD_ORDERSET_SOP1 | LL_UCPD_ORDERSET_SOP2 | + LL_UCPD_ORDERSET_CABLERST | LL_UCPD_ORDERSET_HARDRST); + /* Controls whether pull-ups and pull-downs controls related to ANAMODE and ANASUBMODE + should be applied to CC1 and CC2 analog PHYs */ + /* Should be done when UCPDEN is 1 */ + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); + +#ifdef _LOW_POWER + LL_UCPD_WakeUpEnable(Ports[PortNum].husbpd); +#endif /* _LOW_POWER */ + + /* Disable dead battery */ + LL_PWR_DisableUCPDDeadBattery(); /* PWR->CR3 |= (1 << 14); */ + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); /* GPIOB enable RCC->AHB2ENR |= 2; */ + + /* Set by default UCPD1_CC1 & UCPD1_CC2 in analog mode */ + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_6, LL_GPIO_MODE_ANALOG); /* PB6 mode = GP analog => CC1 */ + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_4, LL_GPIO_MODE_ANALOG); /* PB4 mode = GP analog => CC2 */ + + LL_GPIO_SetPinPull(GPIOB, LL_GPIO_PIN_6, LL_GPIO_PULL_NO); + LL_GPIO_SetPinPull(GPIOB, LL_GPIO_PIN_4, LL_GPIO_PULL_NO); + + /* Init power */ + BSP_USBPD_PWR_Init(PortNum); + +#if defined(TCPP0203_SUPPORT) + /* Register VBUS detect callback */ + BSP_USBPD_PWR_RegisterVBUSDetectCallback(PortNum, CAD_HW_IF_VBUSDetectCallback); +#endif /* TCPP0203_SUPPORT */ + + /* Enable USBPD IP */ + LL_UCPD_Enable(Ports[PortNum].husbpd); + +#if defined(_SRC) || defined(_DRP) + /* Initialize usbpd interrupt */ + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + USBPDM1_AssertRp(PortNum); +#if defined(TCPP0203_SUPPORT) + /* Switch to Low Power mode */ + BSP_USBPD_PWR_SetPowerMode(PortNum, USBPD_PWR_MODE_LOWPOWER); +#endif /* TCPP0203_SUPPORT */ + } +#endif /* _SRC || _DRP */ +#if defined(_DRP) + else +#endif /* _DRP */ +#if defined(_SNK) || defined(_DRP) + { + USBPDM1_AssertRd(PortNum); +#if defined(TCPP0203_SUPPORT) + /* Switch to Low Power mode */ + BSP_USBPD_PWR_SetPowerMode(PortNum, USBPD_PWR_MODE_LOWPOWER); +#endif /* TCPP0203_SUPPORT */ + } +#endif /* _SNK || _DRP */ + + /* Set the state machine according the SW configuration */ +#if !defined(USBPDCORE_LIB_NO_PD) +#if defined(_DRP) + if (Ports[PortNum].settings->CAD_RoleToggle == USBPD_TRUE) + { + /* Set current state machine to DRP state machine */ + _handle->CAD_PtrStateMachine = CAD_StateMachine_DRP; + _handle->CAD_Accessory_SRC = Ports[PortNum].settings->CAD_AccesorySupport; +#if defined(USBPDCORE_VPD) + _handle->CAD_VPD_SRC = Ports[PortNum].settings->CAD_VPDSupport; +#endif /* USBPDCORE_VPD */ + } + else +#endif /* _DRP */ + { +#if defined(_SRC) + /* If default role is source */ + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].settings->PE_DefaultRole) + { + /* Set current state machine to SRC state machine */ + _handle->CAD_PtrStateMachine = CAD_StateMachine_SRC; + _handle->CAD_Accessory_SRC = Ports[PortNum].settings->CAD_AccesorySupport; +#if defined(USBPDCORE_VPD) + _handle->CAD_VPD_SRC = Ports[PortNum].settings->CAD_VPDSupport; +#endif /* USBPDCORE_VPD */ + } + else +#endif /* _SRC */ + { +#if defined(_SNK) + /* Set current state machine to SNK state machine */ + _handle->CAD_PtrStateMachine = CAD_StateMachine_SNK; + _handle->CAD_Accessory_SNK = Ports[PortNum].settings->CAD_AccesorySupport; +#if defined(USBPDCORE_VPD) + _handle->CAD_VPD_SNK = Ports[PortNum].settings->VPDSupport; +#endif /* USBPDCORE_VPD */ +#endif /* _SNK */ + } + } +#else /* USBPDCORE_LIB_NO_PD */ +#if defined(_SRC) + /* If default role is source */ + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].settings->PE_DefaultRole) + { + /* Set current state machine to SRC state machine */ + _handle->CAD_PtrStateMachine = CAD_StateMachine_SRC; +#if defined(USBPDCORE_VPD) + _handle->CAD_VPD_SRC = Ports[PortNum].settings->CAD_VPDSupport; +#endif /* USBPDCORE_VPD */ + } + else +#endif /* _SRC */ + { +#if defined(_SNK) + /* Set current state machine to SNK state machine */ + _handle->CAD_PtrStateMachine = CAD_StateMachine_SNK; +#if defined(USBPDCORE_VPD) + _handle->CAD_VPD_SNK = Ports[PortNum].settings->CAD_VPDSupport; +#endif /* USBPDCORE_VPD */ +#endif /* _SNK */ + } +#endif /* USBPDCORE_LIB_NO_PD */ +} + +/** + * @brief Function to force CAD state machine into error recovery state + * @param PortNum Index of current used port + * @retval None + */ +void CAD_Enter_ErrorRecovery(uint8_t PortNum) +{ + /* Remove the ucpd resistor */ + USBPDM1_EnterErrorRecovery(PortNum); + /* Set the error recovery flag to allow the stack to switch into errorRecovery Flag */ + CAD_HW_Handles[PortNum].CAD_ErrorRecoveryflag = USBPD_TRUE; + /* Wake up CAD task */ + Ports[PortNum].USBPD_CAD_WakeUp(); +} + +#if defined(USBPDCORE_DRP) || defined(USBPDCORE_SRC) +/** + * @brief Function to force the value of the RP resistor + * @note Must be called only if you want change the settings value + * @param PortNum Index of current used port + * @param RpValue RP value to set in devices based on @ref CAD_RP_Source_Current_Adv_Typedef + * @retval 0 success else error + */ +uint32_t CAD_SRC_Set_ResistorRp(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RpValue) +{ + /* Update the information about the default resistor value presented in detach mode */ + Ports[PortNum].params->RpResistor = RpValue; + + /* Inform state machine about a resistor update */ + CAD_HW_Handles[PortNum].CAD_ResistorUpdateflag = USBPD_TRUE; + /* Wake up CAD task */ + Ports[PortNum].USBPD_CAD_WakeUp(); + return 0; +} + +/* Keep for legacy */ +uint32_t CAD_Set_ResistorRp(uint8_t PortNum, CAD_RP_Source_Current_Adv_Typedef RpValue) +{ + return CAD_SRC_Set_ResistorRp(PortNum, RpValue); +} +#endif /* USBPDCORE_DRP || USBPDCORE_SRC */ + + +/** + * @brief CAD State machine for sink role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +#if defined(_SNK) +/* Function to handle SNK and SNK + ACCESSORY OPTION */ +uint32_t CAD_StateMachine_SNK(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + +#if defined(USBPDM1_VCC_FEATURE_ENABLED) + BSP_USBPD_PWR_VCCSetState(PortNum, 1); +#endif /* USBPDM1_VCC_FEATURE_ENABLED */ + + /* Check CAD STATE */ + switch (_handle->cstate) + { + case USBPD_CAD_STATE_DETACHED: + { + _timing = ManageStateDetached_SNK(PortNum); + break; + } + + case USBPD_CAD_STATE_ATTACHED_WAIT: + _timing = ManageStateAttachedWait_SNK(PortNum, pEvent, pCCXX); + break; + + case USBPD_CAD_STATE_ATTACHED: + _timing = ManageStateAttached_SNK(PortNum, pEvent, pCCXX); + break; + +#if defined(_ACCESSORY_SNK) + case USBPD_CAD_STATE_UNATTACHED_ACCESSORY: + { + uint32_t cc; + cc = Ports[PortNum].husbpd->SR & (UCPD_SR_TYPEC_VSTATE_CC1 | UCPD_SR_TYPEC_VSTATE_CC2); + + _handle->CAD_tDebounce_flag = USBPD_FALSE; + if ((USBPD_TRUE == _handle->CAD_Accessory_SNK) && (cc == (LL_UCPD_SRC_CC1_VRA | LL_UCPD_SRC_CC2_VRA))) + { + /* Get the time of this event */ + _handle->CAD_tDebounce_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_ATTACHED_ACCESSORY_WAIT; + } +#if defined(USBPDCORE_VPD) + else if ((USBPD_TRUE == _handle->CAD_VPD_SNK) && + ((cc == (LL_UCPD_SRC_CC1_VRD | LL_UCPD_SRC_CC2_VRA) + || ((LL_UCPD_SRC_CC1_VRA | LL_UCPD_SRC_CC2_VRD) == cc))) + ) + { + _handle->CAD_tDebounce_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_ATTACHED_ACCESSORY_WAIT; + } +#endif /* USBPDCORE_VPD */ + else if ( + ((cc == (LL_UCPD_SRC_CC1_VRD | LL_UCPD_SRC_CC2_VRA) + || ((LL_UCPD_SRC_CC1_VRA | LL_UCPD_SRC_CC2_VRD) == cc))) + ) + { + if ((HAL_GetTick() - _handle->CAD_tToggle_start) > 200) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + USBPDM1_AssertRd(PortNum); + } + } + else + { + /* tOnePortToggleConnect between 0 and 80ms */ + if ((HAL_GetTick() - _handle->CAD_tToggle_start) > CAD_ACCESSORY_TOGGLE) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + USBPDM1_AssertRd(PortNum); + } + } + break; + } + + case USBPD_CAD_STATE_ATTACHED_ACCESSORY_WAIT : + { + uint32_t cc; + cc = Ports[PortNum].husbpd->SR & (UCPD_SR_TYPEC_VSTATE_CC1 | UCPD_SR_TYPEC_VSTATE_CC2); + _handle->CAD_tDebounce_flag = USBPD_FALSE; + switch (cc) + { + case LL_UCPD_SRC_CC1_VRA | LL_UCPD_SRC_CC2_VRA : /* Audio accessory */ + { + /* Check if the device is still connected after the debounce timing */ + if (HAL_GetTick() - _handle->CAD_tDebounce_start > CAD_TCCDEBOUNCE_THRESHOLD) + { + _handle->cstate = USBPD_CAD_STATE_AUDIO_ACCESSORY; + *pEvent = USBPD_CAD_EVENT_ACCESSORY; + } + break; + } +#if defined(USBPDCORE_VPD) + case LL_UCPD_SRC_CC1_VRD | LL_UCPD_SRC_CC2_VRA: /* VPD CC1 */ + case LL_UCPD_SRC_CC1_VRA | LL_UCPD_SRC_CC2_VRD: /* VPD CC2 */ + { + if (HAL_GetTick() - _handle->CAD_tDebounce_start > CAD_TCCDEBOUNCE_THRESHOLD) + { + _handle->cstate = USBPD_CAD_STATE_POWERED_ACCESSORY; + *pEvent = USPPD_CAD_EVENT_VPD; + Ports[PortNum].params->PE_VPDStatus = VPD_UNKNOWN; + Ports[PortNum].params->CAD_VPDStatus = VPD_NONE; + if ((LL_UCPD_SRC_CC1_VRD | LL_UCPD_SRC_CC2_VRA) == cc) + { + _handle->cc = CC1; + } + else + { + _handle->cc = CC2; + } + *pCCXX = _handle->cc; + HW_SignalAttachement(PortNum, _handle->cc); + } + break; + } +#endif /* USBPDCORE_VPD */ + default : + { + if ((HAL_GetTick() - _handle->CAD_tDebounce_start) > CAD_TCCDEBOUNCE_THRESHOLD) + { + /* Get the time of this event */ + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + USBPDM1_AssertRd(PortNum); + } + break; + } + } + break; + } + + case USBPD_CAD_STATE_AUDIO_ACCESSORY: + { + /* Check if the device is still connected after the debounce timing */ + if ((LL_UCPD_SRC_CC1_VRA != (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1)) + && (LL_UCPD_SRC_CC2_VRA != (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2))) + { + if (USBPD_FALSE == _handle->CAD_tDebounce_flag) + { + _handle->CAD_tDebounce_start = HAL_GetTick(); + _handle->CAD_tDebounce_flag = USBPD_TRUE; + _timing = CAD_TCCDEBOUNCE_THRESHOLD + 49U; + } + else + { + if ((HAL_GetTick() - _handle->CAD_tDebounce_start) > (CAD_TCCDEBOUNCE_THRESHOLD + 50U)) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->CAD_tDebounce_flag = USBPD_FALSE; + _handle->cstate = USBPD_CAD_STATE_DETACHED; + _handle->cc = CCNONE; + USBPDM1_AssertRd(PortNum); + *pEvent = USBPD_CAD_EVENT_DETACHED; + *pCCXX = CCNONE; + } + } + } + else + { + _handle->CAD_tDebounce_flag = USBPD_FALSE; + _timing = CAD_INFINITE_TIME; + } + break; + } + +#if defined(USBPDCORE_VPD) + case USBPD_CAD_STATE_POWERED_ACCESSORY: + { + uint32_t cc; + cc = Ports[PortNum].husbpd->SR & (UCPD_SR_TYPEC_VSTATE_CC1 | UCPD_SR_TYPEC_VSTATE_CC2); + + /* If SRC.Open detected on the monitored PIN switch to Unattached.SNK */ + if (((CC1 == _handle->cc) && (LL_UCPD_SRC_CC1_OPEN == (cc & UCPD_SR_TYPEC_VSTATE_CC1))) || + ((CC2 == _handle->cc) && (LL_UCPD_SRC_CC2_OPEN == (cc & UCPD_SR_TYPEC_VSTATE_CC2)))) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + Ports[PortNum].params->PE_VPDStatus = VPD_NONE; + *pEvent = USBPD_CAD_EVENT_DETACHED; + USBPDM1_AssertRd(PortNum); + } + else + { + /* if the port is not PD or a SRC it must switch to try.SNK */ + if (VPD_NOPD == Ports[PortNum].params->CAD_VPDStatus) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + *pEvent = USBPD_CAD_EVENT_DETACHED; + USBPDM1_AssertRd(PortNum); + Ports[PortNum].params->PE_VPDStatus = VPD_NONE; + } + /* If the port is PD but doesn't enter Alternate mode within tAMETimeout switch to Unsupported.Accessory */ + else if (VPD_FAILED_ENTER_ALTERNATE == Ports[PortNum].params->CAD_VPDStatus) + { + _handle->cstate = USBPD_CAD_STATE_UNSUPPORTED_ACCESSORY; + } + /* If Powered USB DEvice confirmed transition to CTUnattached.SNK */ + else if (VPD_DETECTED == Ports[PortNum].params->CAD_VPDStatus) + { + _handle->cstate = USBPD_CAD_STATE_CTVPD_UNATTACHED; + } + } + break; + } + + case USBPD_CAD_STATE_UNSUPPORTED_ACCESSORY: + { + uint32_t cc; + cc = Ports[PortNum].husbpd->SR & (UCPD_SR_TYPEC_VSTATE_CC1 | UCPD_SR_TYPEC_VSTATE_CC2); + + /* If SRC.Open detected on the monitored PIN switch to Unattached.SNK */ + if ((LL_UCPD_SRC_CC1_OPEN == (cc | UCPD_SR_TYPEC_VSTATE_CC1)) || + (LL_UCPD_SRC_CC2_OPEN == (cc | UCPD_SR_TYPEC_VSTATE_CC2))) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + *pEvent = USBPD_CAD_EVENT_DETACHED; + USBPDM1_AssertRp(PortNum); + } + break; + } + + case USBPD_CAD_STATE_CTVPD_UNATTACHED: + { + if (USBPD_TRUE == USBPD_PWR_IF_GetVBUSStatus(PortNum, USBPD_PWR_VSAFE5V)) /* Check if Vbus is on */ + { + /* The charger/SRC has been plug */ + _handle->cstate = USBPD_CAD_STATE_CTVPD_ATTACHED; + } + else + { + uint32_t cc; + cc = Ports[PortNum].husbpd->SR & (UCPD_SR_TYPEC_VSTATE_CC1 | UCPD_SR_TYPEC_VSTATE_CC2); + + /* If VBUS is VSafe0V and CC low for tVPDDetach = 10/20ms */ + if (((LL_UCPD_SRC_CC1_OPEN == (cc | UCPD_SR_TYPEC_VSTATE_CC1)) || + (LL_UCPD_SRC_CC2_OPEN == (cc | UCPD_SR_TYPEC_VSTATE_CC2))) && + (USBPD_TRUE == USBPD_PWR_IF_GetVBUSStatus(PortNum, USBPD_PWR_BELOWVSAFE0V))) + { + if (USBPD_TRUE == _handle->CAD_tDebounce_flag) + { + _handle->CAD_tDebounce_start = HAL_GetTick(); + } + else + { + if (HAL_GetTick() - _handle->CAD_tDebounce_start > CAD_TVPDDETACH) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + *pEvent = USBPD_CAD_EVENT_DETACHED; + USBPDM1_AssertRp(PortNum); + } + } + } + else + { + _handle->CAD_tDebounce_flag = USBPD_FALSE; + } + } + break; + } + + case USBPD_CAD_STATE_CTVPD_ATTACHED: + { + /* If VBUS removed */ + if (USBPD_TRUE == USBPD_PWR_IF_GetVBUSStatus(PortNum, USBPD_PWR_SNKDETACH)) + { + /* The charger/SRC has been unplug */ + _handle->cstate = USBPD_CAD_STATE_CTVPD_UNATTACHED; + } + break; + } +#endif /* USBPDCORE_VPD */ +#endif /* _ACCESSORY_SNK */ + + default: + { + break; + } + } + +#if defined(USBPDM1_VCC_FEATURE_ENABLED) + switch (_handle->pstate) + { + case USBPD_CAD_STATE_ATTACHED_WAIT: + case USBPD_CAD_STATE_ATTACHED: + case USBPD_CAD_STATE_ERRORRECOVERY : + case USBPD_CAD_STATE_ERRORRECOVERY_EXIT: + /* Nothing to do, the VCC must stay high */ + break; + default : + BSP_USBPD_PWR_VCCSetState(PortNum, 0); + break; + } +#endif /* USBPDM1_VCC_FEATURE_ENABLED */ + + return _timing; +} +#endif /* _SNK */ + +#if defined(_SRC) +/** + * @brief CAD State machine for source role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +uint32_t CAD_StateMachine_SRC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + /*Check CAD STATE*/ + switch (_handle->cstate) + { + case USBPD_CAD_STATE_DETACH_SRC : + { +#if defined(_VCONN_SUPPORT) + /* DeInitialize Vconn management */ + (void)BSP_USBPD_PWR_VCONNDeInit(PortNum, (Ports[PortNum].CCx == CC1) ? 1u : 2u); +#endif /* _VCONN_SUPPORT */ + /* DeInitialise VBUS power */ + (void)BSP_USBPD_PWR_VBUSDeInit(PortNum); + /* Reset the resistor */ + USBPDM1_AssertRp(PortNum); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + _timing = 0; + break; + } + + case USBPD_CAD_STATE_SWITCH_TO_SNK : + case USBPD_CAD_STATE_DETACHED: + { + _timing = ManageStateDetached_SRC(PortNum); + break; + } + + case USBPD_CAD_STATE_ATTACHED_WAIT: + { + _timing = ManageStateAttachedWait_SRC(PortNum, pEvent, pCCXX); + break; + } + +#if defined(_ACCESSORY_SRC) + case USBPD_CAD_STATE_ACCESSORY: + { + _timing = CAD_INFINITE_TIME; + CAD_Check_HW_SRC(PortNum); + if ((HW_AudioAdapter_Attachment != _handle->CurrentHWcondition) + && (HW_PwrCable_Sink_Attachment != _handle->CurrentHWcondition)) + { + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; + *pCCXX = CCNONE; + _handle->cc = CCNONE; + *pEvent = USBPD_CAD_EVENT_DETACHED; + } + break; + } + + case USBPD_CAD_STATE_DEBUG: + { + _timing = CAD_INFINITE_TIME; + CAD_Check_HW_SRC(PortNum); + if (_handle->CurrentHWcondition != HW_Debug_Attachment) + { + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; + *pCCXX = CCNONE; + _handle->cc = CCNONE; + *pEvent = USBPD_CAD_EVENT_DETACHED; + } + break; + } +#endif /* _ACCESSORY_SRC */ + + case USBPD_CAD_STATE_EMC : + { + _timing = ManageStateEMC(PortNum, pEvent, pCCXX); + break; + } + + /*CAD electronic cable with Sink ATTACHED*/ + case USBPD_CAD_STATE_ATTEMC: + case USBPD_CAD_STATE_ATTACHED: + { + _timing = ManageStateAttached_SRC(PortNum, pEvent, pCCXX); + break; + } + + default : + { + break; + } + } + + return _timing; +} +#endif /* _SRC */ + +#if defined(_DRP) +/** + * @brief CAD State machine for dual role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +uint32_t CAD_StateMachine_DRP(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + /*Check CAD STATE*/ + switch (_handle->cstate) + { + case USBPD_CAD_STATE_DETACH_SRC : + { +#if defined(_VCONN_SUPPORT) + /* DeInitialize Vconn management */ + (void)BSP_USBPD_PWR_VCONNDeInit(PortNum, (Ports[PortNum].CCx == CC1) ? 1u : 2u); +#endif /* _VCONN_SUPPORT */ + /* DeInitialise VBUS power */ + (void)BSP_USBPD_PWR_VBUSDeInit(PortNum); + _timing = 0; + _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; + break; + } + + case USBPD_CAD_STATE_SWITCH_TO_SRC: + case USBPD_CAD_STATE_SWITCH_TO_SNK: + { + LL_UCPD_RxDisable(Ports[PortNum].husbpd); + if (USBPD_CAD_STATE_SWITCH_TO_SRC == _handle->cstate) + { + USBPDM1_AssertRp(PortNum); + Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SRC; + Ports[PortNum].params->PE_DataRole = USBPD_PORTDATAROLE_DFP; + _timing = Ports[PortNum].settings->CAD_SRCToggleTime; + } + if (USBPD_CAD_STATE_SWITCH_TO_SNK == _handle->cstate) + { + USBPDM1_AssertRd(PortNum); + Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SNK; + Ports[PortNum].params->PE_DataRole = USBPD_PORTDATAROLE_UFP; + _timing = Ports[PortNum].settings->CAD_SNKToggleTime; + } + _handle->CAD_tToggle_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_DETACHED; + } + break; + + case USBPD_CAD_STATE_DETACHED: + _timing = ManageStateDetached_DRP(PortNum); + break; + + /*CAD STATE ATTACHED WAIT*/ + case USBPD_CAD_STATE_ATTACHED_WAIT: + _timing = ManageStateAttachedWait_DRP(PortNum, pEvent, pCCXX); + break; + +#if defined(_ACCESSORY_SRC) + case USBPD_CAD_STATE_ACCESSORY: + { + CAD_Check_HW_SRC(PortNum); + if ((HW_AudioAdapter_Attachment != _handle->CurrentHWcondition) + && (HW_PwrCable_Sink_Attachment != _handle->CurrentHWcondition)) + { + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; + *pCCXX = CCNONE; + _handle->cc = CCNONE; + *pEvent = USBPD_CAD_EVENT_DETACHED; + } + else + { + _timing = CAD_INFINITE_TIME; + } + break; + } + + case USBPD_CAD_STATE_DEBUG: + { + _timing = CAD_INFINITE_TIME; + CAD_Check_HW_SRC(PortNum); + if (_handle->CurrentHWcondition != HW_Debug_Attachment) + { + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; + *pCCXX = CCNONE; + _handle->cc = CCNONE; + *pEvent = USBPD_CAD_EVENT_DETACHED; + } + break; + } +#endif /* _ACCESSORY_SRC */ + + /* CAD ELECTRONIC CABLE ATTACHED */ + case USBPD_CAD_STATE_EMC : + _timing = ManageStateEMC(PortNum, pEvent, pCCXX); + break; + + /*CAD electronic cable with Sink ATTACHED*/ + case USBPD_CAD_STATE_ATTEMC: + case USBPD_CAD_STATE_ATTACHED: + _timing = ManageStateAttached_DRP(PortNum, pEvent, pCCXX); + break; + + default : + break; + } + + return _timing; +} +#endif /* _DRP */ + +#if !defined(USBPDCORE_LIB_NO_PD) +/** + * @brief Main CAD State machine + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +uint32_t CAD_StateMachine(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + /* Set by default event to none */ + *pEvent = USBPD_CAD_EVENT_NONE; + + /* If a swap is on going, return default timing */ + if (USBPD_TRUE == Ports[PortNum].params->PE_SwapOngoing) + { + return _timing; + } + + if (_handle->CAD_ErrorRecoveryflag == USBPD_TRUE) + { + /* Force the state error recovery */ + _handle->CAD_ErrorRecoveryflag = USBPD_FALSE; + _handle->cstate = USBPD_CAD_STATE_ERRORRECOVERY; +#if defined(_TRACE) + USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)_handle->cstate, NULL, 0); +#endif /* _TRACE */ + } + + switch (_handle->cstate) + { + case USBPD_CAD_STATE_RESET: + { +#if !defined(_LOW_POWER) && !defined(USBPDM1_VCC_FEATURE_ENABLED) + /* Enable TypeCEvents Interrupts */ + LL_UCPD_EnableIT_TypeCEventCC2(Ports[PortNum].husbpd); + LL_UCPD_EnableIT_TypeCEventCC1(Ports[PortNum].husbpd); +#elif defined(_LOW_POWER) + /* If port role is source */ + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + /* Enable TypeCEvents Interrupts */ + LL_UCPD_EnableIT_TypeCEventCC2(Ports[PortNum].husbpd); + LL_UCPD_EnableIT_TypeCEventCC1(Ports[PortNum].husbpd); + } +#endif /* !_LOW_POWER && !USBPDM1_VCC_FEATURE_ENABLED */ + + /* Enable IRQ */ + UCPD_INSTANCE0_ENABLEIRQ; +#if defined(_DRP) || defined(_ACCESSORY_SNK) + _handle->CAD_tToggle_start = HAL_GetTick(); +#endif /* _DRP || _ACCESSORY_SNK */ + _handle->cstate = USBPD_CAD_STATE_DETACHED; + break; + } + + case USBPD_CAD_STATE_ERRORRECOVERY : + { + /* Remove the resistor */ + /* Enter recovery = Switch to SRC with no resistor */ + USBPDM1_EnterErrorRecovery(PortNum); + + /* Forward detach event to DPM */ + Ports[PortNum].CCx = CCNONE; + *pCCXX = CCNONE; + _handle->cc = CCNONE; + *pEvent = USBPD_CAD_EVENT_DETACHED; + + /* Start tErrorRecovery timeout */ + _handle->CAD_tDebounce_start = HAL_GetTick(); + _timing = CAD_TERROR_RECOVERY_TIME; + _handle->cstate = USBPD_CAD_STATE_ERRORRECOVERY_EXIT; + break; + } + + case USBPD_CAD_STATE_ERRORRECOVERY_EXIT : + { + if ((HAL_GetTick() - _handle->CAD_tDebounce_start) > CAD_TERROR_RECOVERY_TIME) + { + /* Reconfigure the port + port source to src + port snk to snk + port drp to src */ + +#if defined(_SRC) || defined(_DRP) + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + USBPDM1_AssertRp(PortNum); + } +#endif /* _SRC || _DRP */ +#if defined(_DRP) + else +#endif /* _DRP */ +#if defined(_SNK) || defined(_DRP) + { + USBPDM1_AssertRd(PortNum); + } +#endif /* _SNK || _DRP */ + /* Switch to state detach */ +#if defined(_DRP) || defined(_ACCESSORY_SNK) + _handle->CAD_tToggle_start = HAL_GetTick(); +#endif /* _DRP || _ACCESSORY_SNK */ + _handle->cstate = USBPD_CAD_STATE_DETACHED; + } + break; + } + + default: + { + /* Call the state machine corresponding to the port SNK or SRC or DRP */ + _timing = _handle->CAD_PtrStateMachine(PortNum, pEvent, pCCXX); + break; + } + } + +#if defined(_TRACE) + if (_handle->cstate != _handle->pstate) + { + _handle->pstate = _handle->cstate; + USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)_handle->cstate, NULL, 0); +#if defined(CAD_DEBUG_TRACE) + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)(0xC0 | _handle->CurrentHWcondition), NULL, 0); + } + else + { + USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, + (uint8_t)(0x80 | (Ports[PortNum].params->SNKExposedRP_AtAttach << 4) | + _handle->CurrentHWcondition), NULL, 0); + } +#endif /* CAD_DEBUG_TRACE */ + } +#endif /* _TRACE */ + + return _timing; +} + +#else +/* USBPDCORE_LIB_NO_PD */ +/** + * @brief Main CAD State machine + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +uint32_t CAD_StateMachine(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + /* Set by default event to none */ + *pEvent = USBPD_CAD_EVENT_NONE; + + switch (_handle->cstate) + { + case USBPD_CAD_STATE_RESET: + { +#ifndef _LOW_POWER + /* Enable TypeCEvents Interrupts */ + LL_UCPD_EnableIT_TypeCEventCC2(Ports[PortNum].husbpd); + LL_UCPD_EnableIT_TypeCEventCC1(Ports[PortNum].husbpd); +#else + /* If port role is source */ + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + /* Enable TypeCEvents Interrupts */ + LL_UCPD_EnableIT_TypeCEventCC2(Ports[PortNum].husbpd); + LL_UCPD_EnableIT_TypeCEventCC1(Ports[PortNum].husbpd); + } +#endif /* !_LOW_POWER */ + + /* Enable IRQ */ + UCPD_INSTANCE0_ENABLEIRQ; +#if defined(_DRP) || defined(_ACCESSORY_SNK) + _handle->CAD_tToggle_start = HAL_GetTick(); +#endif /* _DRP || _ACCESSORY_SNK */ + _handle->cstate = USBPD_CAD_STATE_DETACHED; + break; + } + + default: + { + /* Call the state machine corresponding to the port SNK or SRC or DRP */ + _timing = _handle->CAD_PtrStateMachine(PortNum, pEvent, pCCXX); + break; + } + } + +#if defined(_TRACE) + if (_handle->cstate != _handle->pstate) + { + _handle->pstate = _handle->cstate; + USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)_handle->cstate, NULL, 0); +#if defined(CAD_DEBUG_TRACE) + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)(0xC0 | _handle->CurrentHWcondition), NULL, 0); + } + else + { + USBPD_TRACE_Add(USBPD_TRACE_CAD_LOW, PortNum, (uint8_t)(0x80 | + (Ports[PortNum].params->SNKExposedRP_AtAttach << 4) | + _handle->CurrentHWcondition), NULL, 0); + } +#endif /* CAD_DEBUG_TRACE */ + } +#endif /* _TRACE */ + + return _timing; +} +#endif /* !USBPDCORE_LIB_NO_PD */ + +/** + * @} + */ + +/** @addtogroup USBPD_DEVICE_CAD_HW_IF_Private_Functions + * @{ + */ + +#if defined(_DRP) || defined(_SNK) +/** + * @brief Check CCx HW condition + * @param PortNum Port + * @retval none + */ +void CAD_Check_HW_SNK(uint8_t PortNum) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + /* Done to prevent code optimization issue with GCC */ + uint32_t CC1_value; + uint32_t CC2_value; + + /* + ---------------------------------------------------------------------------- + | ANAMODE | ANASUBMODE[1:0] | Notes | TYPEC_VSTATE_CCx[1:0] | + | | | | 00 | 01 | 10 | 11 | + ---------------------------------------------------------------------------- + | 0: Source | 00: Disabled |Disabled N/A | NA | + | | 01: Default USB Rp| |vRaDef|vRdDef|vOPENDef| | + | | 10: 1.5A Rp | |vRa1.5|vRd1.5|vOPEN1.5| NA | + | | 11: 3.0A Rp | |vRa3.0|vRd3.0|vOPEN3.0| NA | + ----------------------------------------------------------------------------- + | 1: Sink | | |xx vRa|vRdUSB| vRd1.5 |vRd3.0| + ----------------------------------------------------------------------------- + */ + +#if defined(_LOW_POWER) || defined(USBPDM1_VCC_FEATURE_ENABLED) + /* Enable type C state machine */ + CLEAR_BIT(Ports[PortNum].husbpd->CR, UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS); + + for (int32_t index = 0; index < CAD_DELAY_READ_CC_STATUS; index++) + { + __DSB(); + }; + + /* Read the CC line */ + CC1_value = Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1; + CC2_value = Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2; + + /* Disable the C state machine */ + SET_BIT(Ports[PortNum].husbpd->CR, UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS); +#else + CC1_value = Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1; + CC2_value = Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2; +#endif /* _LOW_POWER || USBPDM1_VCC_FEATURE_ENABLED */ + + _handle->cc = CCNONE; + _handle->CurrentHWcondition = HW_Detachment; + + if ((CC1_value != LL_UCPD_SNK_CC1_VOPEN) && (CC2_value == LL_UCPD_SNK_CC2_VOPEN)) + { + _handle->CurrentHWcondition = HW_Attachment; + _handle->cc = CC1; + Ports[PortNum].params->SNKExposedRP_AtAttach = CC1_value >> UCPD_SR_TYPEC_VSTATE_CC1_Pos; + } + + if ((CC1_value == LL_UCPD_SNK_CC1_VOPEN) && (CC2_value != LL_UCPD_SNK_CC2_VOPEN)) + { + _handle->CurrentHWcondition = HW_Attachment; + _handle->cc = CC2; + Ports[PortNum].params->SNKExposedRP_AtAttach = CC2_value >> UCPD_SR_TYPEC_VSTATE_CC2_Pos;; + } +} +#endif /* _DRP || _SNK */ + +#if defined(_DRP) || defined(_SRC) +/** + * @brief Check CCx HW condition + * @param PortNum Port + * @retval none + */ +void CAD_Check_HW_SRC(uint8_t PortNum) +{ +#if !defined(_RTOS) + uint32_t CC1_value_temp; + uint32_t CC2_value_temp; +#endif /* !_RTOS */ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + /* Done to prevent code optimization issue with GCC */ + uint32_t CC1_value; + uint32_t CC2_value; + + /* + ---------------------------------------------------------------------------- + | ANAMODE | ANASUBMODE[1:0] | Notes | TYPEC_VSTATE_CCx[1:0] | + | | | | 00 | 01 | 10 | 11 | + ---------------------------------------------------------------------------- + | 0: Source | 00: Disabled |Disabled N/A | NA | + | | 01: Default USB Rp| |vRaDef|vRdDef|vOPENDef| | + | | 10: 1.5A Rp | |vRa1.5|vRd1.5|vOPEN1.5| NA | + | | 11: 3.0A Rp | |vRa3.0|vRd3.0|vOPEN3.0| NA | + ----------------------------------------------------------------------------- + | 1: Sink | | |xx vRa|vRdUSB| vRd1.5 |vRd3.0| + ----------------------------------------------------------------------------- + */ +#if defined(_LOW_POWER) || defined(USBPDM1_VCC_FEATURE_ENABLED) + /* Enable type C state machine */ + CLEAR_BIT(Ports[PortNum].husbpd->CR, UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS); + + for (int32_t index = 0; index < CAD_DELAY_READ_CC_STATUS; index++) + { + __DSB(); + }; + + /* Read the CC line */ + CC1_value = (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1) >> UCPD_SR_TYPEC_VSTATE_CC1_Pos; + CC2_value = (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2) >> UCPD_SR_TYPEC_VSTATE_CC2_Pos; + + /* Disable the C state machine */ + SET_BIT(Ports[PortNum].husbpd->CR, UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS); +#else + CC1_value = (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1) >> UCPD_SR_TYPEC_VSTATE_CC1_Pos; + CC2_value = (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2) >> UCPD_SR_TYPEC_VSTATE_CC2_Pos; +#endif /* _LOW_POWER || USBPDM1_VCC_FEATURE_ENABLED */ + +#if !defined(_RTOS) + /* Workaround linked to issue with Ellisys test TD.PC.E5 + - it seems that in NRTOS version, we detect a glitch during DRP transition SNK to SRC */ + CC1_value_temp = (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1) >> UCPD_SR_TYPEC_VSTATE_CC1_Pos; + CC2_value_temp = (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2) >> UCPD_SR_TYPEC_VSTATE_CC2_Pos; + if ((CC1_value_temp != CC1_value) || (CC2_value_temp != CC2_value)) + { + return; + } +#endif /* !_RTOS */ + + const CCxPin_TypeDef table_cc[] = + { + CCNONE, CC2, CC2, + CC1, CCNONE, CC1, + CC1, CC2, CCNONE + }; + + const CAD_HW_Condition_TypeDef table_CurrentHWcondition[] = + { + HW_AudioAdapter_Attachment, HW_PwrCable_Sink_Attachment, HW_PwrCable_NoSink_Attachment, + HW_PwrCable_Sink_Attachment, HW_Debug_Attachment, HW_Attachment, + HW_PwrCable_NoSink_Attachment, HW_Attachment, HW_Detachment + }; + + if (CC1_value * 3 + CC2_value < 9) + { + _handle->cc = table_cc[CC1_value * 3 + CC2_value]; + _handle->CurrentHWcondition = table_CurrentHWcondition[CC1_value * 3 + CC2_value]; + } +} +#endif /* _DRP || _SRC */ + +#if defined(_DRP) || defined(_SNK) +/** + * @brief Manage the detached state for sink role + * @param PortNum Port + * @retval Timeout value + */ +static uint32_t ManageStateDetached_SNK(uint8_t PortNum) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + CAD_Check_HW_SNK(PortNum); + /* Change the status on the basis of the HW event given by CAD_Check_HW() */ + if (_handle->CurrentHWcondition == HW_Detachment) + { +#if defined(_LOW_POWER) + /* Value returned by a SRC or a SINK */ + _timing = CAD_DETACH_POLLING; /* 100ms in the sink cases */ +#elif defined(USBPDM1_VCC_FEATURE_ENABLED) + _timing = CAD_DEFAULT_TIME; +#else + _timing = CAD_INFINITE_TIME; +#endif /* _LOW_POWER */ + +#if defined(_ACCESSORY_SNK) + if ((USBPD_TRUE == _handle->CAD_Accessory_SNK) +#if defined(USBPDCORE_VPD) + || (USBPD_TRUE == _handle->CAD_VPD_SNK) +#endif /* USBPDCORE_VPD */ + ) + { + /* A Sink with Accessory support shall transition to Unattached.Accessory within tDRPTransition + after the state of both the CC1 and CC2 pins is SNK.Open for tDRP - dcSRC.DRP * tDRP, or if directed.*/ + if ((HAL_GetTick() - _handle->CAD_tToggle_start) > CAD_ACCESSORY_TOGGLE) + { + _handle->cstate = USBPD_CAD_STATE_UNATTACHED_ACCESSORY; + _handle->CAD_tToggle_start = HAL_GetTick(); + USBPDM1_AssertRp(PortNum); + } + _timing = CAD_DEFAULT_TIME; + } +#endif /* _ACCESSORY_SNK */ + } + else + { + /* Get the time of this event */ + _handle->CAD_tDebounce_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_ATTACHED_WAIT; + + /* Temporary patch for test TD.PD 4.5.2 + rework for Patch TP.PD.C.E5 */ + HAL_Delay(1); + CAD_Check_HW_SNK(PortNum); + + if (_handle->CurrentHWcondition == HW_Detachment) + { + _handle->cstate = USBPD_CAD_STATE_DETACHED; + } + else + { + BSP_USBPD_PWR_VBUSInit(PortNum); + } + } + return _timing; +} +#endif /* _DRP || _SNK */ + +#if defined(_SRC) || defined(_DRP) +/** + * @brief Manage the detached state for source role + * @param PortNum Port + * @retval Timeout value + */ +static uint32_t ManageStateDetached_SRC(uint8_t PortNum) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + if (_handle->CAD_ResistorUpdateflag == USBPD_TRUE) + { + /* Update the resistor value */ + USBPDM1_AssertRp(PortNum); + _handle->CAD_ResistorUpdateflag = USBPD_FALSE; + + /* Let time to internal state machine update */ + HAL_Delay(1); + } + + CAD_Check_HW_SRC(PortNum); + /* Change the status on the basis of the HW event given by CAD_Check_HW() */ + if (_handle->CurrentHWcondition == HW_Detachment) + { +#if defined(_LOW_POWER) + /* Value returned for a SRC */ + _timing = CAD_DETACH_POLLING; +#else + _timing = CAD_INFINITE_TIME; +#endif /* _LOW_POWER */ + } + else + { + if (_handle->CurrentHWcondition == HW_PwrCable_NoSink_Attachment) + { + _handle->cstate = USBPD_CAD_STATE_EMC; + } + else + { + /* Get the time of this event */ + _handle->CAD_tDebounce_start = HAL_GetTick(); + _handle->cstate = USBPD_CAD_STATE_ATTACHED_WAIT; + + BSP_USBPD_PWR_VBUSInit(PortNum); + } + } + return _timing; +} +#endif /* _SRC || _DRP */ + +#if defined(_DRP) +/** + * @brief Manage the detached state for dual role + * @param PortNum Port + * @retval Timeout value + */ +static uint32_t ManageStateDetached_DRP(uint8_t PortNum) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + ManageStateDetached_SRC(PortNum); + } + else + { + ManageStateDetached_SNK(PortNum); + } + + /* Manage the toggle */ + if (_handle->CurrentHWcondition == HW_Detachment) + { + switch (Ports[PortNum].params->PE_PowerRole) + { + case USBPD_PORTPOWERROLE_SRC : + if ((HAL_GetTick() - _handle->CAD_tToggle_start) > Ports[PortNum].settings->CAD_SRCToggleTime) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SNK; + Ports[PortNum].params->PE_DataRole = USBPD_PORTDATAROLE_UFP; + _timing = Ports[PortNum].settings->CAD_SNKToggleTime; + USBPDM1_AssertRd(PortNum); + } + break; + case USBPD_PORTPOWERROLE_SNK : + if ((HAL_GetTick() - _handle->CAD_tToggle_start) > Ports[PortNum].settings->CAD_SNKToggleTime) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + Ports[PortNum].params->PE_PowerRole = USBPD_PORTPOWERROLE_SRC; + Ports[PortNum].params->PE_DataRole = USBPD_PORTDATAROLE_DFP; + _timing = Ports[PortNum].settings->CAD_SRCToggleTime; + USBPDM1_AssertRp(PortNum); + } + break; + default: + break; + } + } + + return _timing; +} +#endif /* _DRP */ + +#if defined(_DRP) || defined(_SRC) +/** + * @brief Manage the attached wait state for source role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +static uint32_t ManageStateAttachedWait_SRC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + /* Evaluate elapsed time in Attach_Wait state */ + uint32_t CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; + CAD_Check_HW_SRC(PortNum); + + if ((_handle->CurrentHWcondition != HW_Detachment) && (_handle->CurrentHWcondition != HW_PwrCable_NoSink_Attachment)) + { + if (USBPD_FALSE == USBPD_PWR_IF_GetVBUSStatus(PortNum, USBPD_PWR_BELOWVSAFE0V)) + { + /* Reset the timing because VBUS threshold not yet reach */ + _handle->CAD_tDebounce_start = HAL_GetTick(); + return CAD_TCCDEBOUNCE_THRESHOLD; + } + + /* Check tCCDebounce */ + if (CAD_tDebounce > CAD_TCCDEBOUNCE_THRESHOLD) + { + switch (_handle->CurrentHWcondition) + { + case HW_Attachment: + HW_SignalAttachement(PortNum, _handle->cc); + _handle->cstate = USBPD_CAD_STATE_ATTACHED; + *pEvent = USBPD_CAD_EVENT_ATTACHED; + *pCCXX = _handle->cc; + break; + + case HW_PwrCable_Sink_Attachment: + HW_SignalAttachement(PortNum, _handle->cc); + _handle->cstate = USBPD_CAD_STATE_ATTEMC; + *pEvent = USBPD_CAD_EVENT_ATTEMC; + break; + + case HW_PwrCable_NoSink_Attachment: + BSP_USBPD_PWR_VBUSDeInit(PortNum); + _handle->cstate = USBPD_CAD_STATE_EMC; + *pEvent = USBPD_CAD_EVENT_EMC; + *pCCXX = _handle->cc; + break; + +#if defined(_ACCESSORY_SRC) + case HW_Debug_Attachment: + _handle->cstate = USBPD_CAD_STATE_DEBUG; + *pEvent = USBPD_CAD_EVENT_DEBUG; + break; + + case HW_AudioAdapter_Attachment: + _handle->cstate = USBPD_CAD_STATE_ACCESSORY; + *pEvent = USBPD_CAD_EVENT_ACCESSORY; + break; +#endif /* _ACCESSORY_SRC */ + + case HW_Detachment: + default: +#if !defined(_ACCESSORY_SRC) + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; +#endif /* _ACCESSORY_SRC */ + break; + } /* End of switch */ + *pCCXX = _handle->cc; + _timing = CAD_DEFAULT_TIME; + } + /* Reset the flag for CAD_tDebounce */ + _handle->CAD_tDebounce_flag = USBPD_FALSE; + } + else /* CAD_HW_Condition[PortNum] = HW_Detachment */ + { + /* Start counting of CAD_tDebounce */ + if (USBPD_FALSE == _handle->CAD_tDebounce_flag) + { + _handle->CAD_tDebounce_start = HAL_GetTick(); + _handle->CAD_tDebounce_flag = USBPD_TRUE; + _timing = CAD_TSRCDISCONNECT_THRESHOLD; + } + else /* CAD_tDebounce already running */ + { + /* Evaluate CAD_tDebounce */ + CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; + if (CAD_tDebounce > CAD_TSRCDISCONNECT_THRESHOLD) + { + _handle->CAD_tDebounce_flag = USBPD_FALSE; + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; + _timing = 0; + } + } + } + return _timing; +} +#endif /* _DRP || _SRC || (_ACCESSORY && _SNK) */ + +#if defined(_DRP) || defined(_SRC) +static uint32_t ManageStateEMC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + uint32_t _timing = CAD_INFINITE_TIME; + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + + CAD_Check_HW_SRC(PortNum); + /* Change the status on the basis of the HW event given by CAD_Check_HW() */ + switch (_handle->CurrentHWcondition) + { + case HW_Detachment : + _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; + _timing = 1; + break; + case HW_PwrCable_Sink_Attachment: + case HW_Attachment : + _handle->cstate = USBPD_CAD_STATE_ATTACHED_WAIT; + _handle->CAD_tDebounce_start = HAL_GetTick() - 5u; /* This is only to check cable presence */ + BSP_USBPD_PWR_VBUSInit(PortNum); + _timing = CAD_DEFAULT_TIME; + break; + case HW_PwrCable_NoSink_Attachment: + default : + /* Nothing to do still the same status */ +#if defined(_DRP) + if (USBPD_TRUE == Ports[PortNum].settings->CAD_RoleToggle) + { + if ((HAL_GetTick() - _handle->CAD_tToggle_start) > Ports[PortNum].settings->CAD_SRCToggleTime) + { + _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SNK; + } + _timing = 0; + } +#else + _timing = CAD_DEFAULT_TIME; +#endif /* _DRP */ + break; + } + return _timing; +} +#endif /* _DRP || _SRC */ + +#if defined(_DRP) +/** + * @brief Manage the attached state for dual role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +static uint32_t ManageStateAttached_DRP(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + return ManageStateAttached_SRC(PortNum, pEvent, pCCXX); + } + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = ManageStateAttached_SNK(PortNum, pEvent, pCCXX); + + /* Toggle management */ + if (_handle->CurrentHWcondition == HW_Detachment) + { + _handle->cstate = USBPD_CAD_STATE_SWITCH_TO_SRC; + _timing = 0; + } + return _timing; +} +#endif /* _DRP */ + +#if defined(_DRP) || (defined(_ACCESSORY) && defined(_SNK)) +/** + * @brief Manage the attached wait state for dual role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +static uint32_t ManageStateAttachedWait_DRP(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + return ManageStateAttachedWait_SRC(PortNum, pEvent, pCCXX); + } + return ManageStateAttachedWait_SNK(PortNum, pEvent, pCCXX); +} +#endif /* _DRP || (_ACCESSORY && _SNK) */ + +#if defined(_SRC) || defined(_DRP) +/** + * @brief Manage the attached state for source role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +static uint32_t ManageStateAttached_SRC(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ +#if defined(_LOW_POWER) || defined(USBPDM1_VCC_FEATURE_ENABLED) + /* Enable type C state machine */ + CLEAR_BIT(Ports[PortNum].husbpd->CR, UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS); + + for (int32_t index = 0; index < CAD_DELAY_READ_CC_STATUS; index++) + { + __DSB(); + }; +#endif /* _LOW_POWER || USBPDM1_VCC_FEATURE_ENABLED */ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + uint32_t ccx = (Ports[PortNum].CCx == CC1) ? (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1) : + (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2); + uint32_t comp = (Ports[PortNum].CCx == CC1) ? LL_UCPD_SRC_CC1_VRD : LL_UCPD_SRC_CC2_VRD; + + /* Check if CC lines is opened or switch to debug accessory */ + if (comp != ccx) + { + /* Start counting of CAD_tDebounce */ + if (USBPD_FALSE == _handle->CAD_tDebounce_flag) + { + _handle->CAD_tDebounce_flag = USBPD_TRUE; + _handle->CAD_tDebounce_start = HAL_GetTick(); + _timing = CAD_TSRCDISCONNECT_THRESHOLD; + } + else /* CAD_tDebounce already running */ + { + /* Evaluate CAD_tDebounce */ + uint32_t CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; + if (CAD_tDebounce > CAD_TSRCDISCONNECT_THRESHOLD) + { + HW_SignalDetachment(PortNum); +#ifdef _DRP + if (USBPD_TRUE == Ports[PortNum].settings->CAD_RoleToggle) + { + USBPDM1_AssertRd(PortNum); + } +#endif /* _DRP */ + _handle->CAD_tDebounce_flag = USBPD_FALSE; + /* Move inside state DETACH to avoid wrong VCONN level*/ + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; + *pEvent = USBPD_CAD_EVENT_DETACHED; + *pCCXX = CCNONE; + _timing = 0; + } + } + } + else + { + /* Reset tPDDebounce flag*/ + _handle->CAD_tDebounce_flag = USBPD_FALSE; +#if defined(_LOW_POWER) + _timing = CAD_VBUS_POLLING_TIME; +#else + _timing = CAD_INFINITE_TIME; +#endif /* _LOW_POWER */ + } + + return _timing; +} +#endif /* _SRC || _DRP */ + +#if defined(_SNK) || defined(_DRP) +/** + * @brief Manage the attached wait state for sink role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +static uint32_t ManageStateAttachedWait_SNK(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + uint32_t CAD_tDebounce = HAL_GetTick() - _handle->CAD_tDebounce_start; + CAD_Check_HW_SNK(PortNum); + if (_handle->CurrentHWcondition == HW_Attachment) + { + if (CAD_tDebounce > CAD_TCCDEBOUNCE_THRESHOLD) + { + if (USBPD_TRUE == USBPD_PWR_IF_GetVBUSStatus(PortNum, USBPD_PWR_VSAFE5V)) /* Check if Vbus is on */ + { + HW_SignalAttachement(PortNum, _handle->cc); + /* Go to attached state */ + _handle->cstate = USBPD_CAD_STATE_ATTACHED; + *pEvent = USBPD_CAD_EVENT_ATTACHED; + *pCCXX = _handle->cc; + } + } + _handle->CAD_tDebounce_flag = USBPD_FALSE; + } + else + { + /* Start counting of CAD_tDebounce */ + if (USBPD_FALSE == _handle->CAD_tDebounce_flag) + { + _handle->CAD_tDebounce_start = HAL_GetTick(); + _handle->CAD_tDebounce_flag = USBPD_TRUE; + _timing = CAD_TPDDEBOUNCE_THRESHOLD; + } + else /* CAD_tDebounce already running */ + { + /* Evaluate CAD_tDebounce */ + if ((HAL_GetTick() - _handle->CAD_tDebounce_start > CAD_TPDDEBOUNCE_THRESHOLD)) + { + _handle->CAD_tDebounce_flag = USBPD_FALSE; + _handle->cstate = USBPD_CAD_STATE_DETACHED; + BSP_USBPD_PWR_VBUSDeInit(PortNum); +#if defined(_ACCESSORY_SNK) + if (USBPD_TRUE == _handle->CAD_Accessory_SNK) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + } +#endif /* _ACCESSORY_SNK */ + } + } + } + return _timing; +} + +/** + * @brief Manage the attached state for sink role + * @param PortNum Port + * @param pEvent Pointer on CAD event based on @ref USBPD_CAD_EVENT + * @param pCCXX Pointer on CC Pin based on @ref CCxPin_TypeDef + * @retval Timeout value + */ +static uint32_t ManageStateAttached_SNK(uint8_t PortNum, USBPD_CAD_EVENT *pEvent, CCxPin_TypeDef *pCCXX) +{ + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + uint32_t _timing = CAD_DEFAULT_TIME; + + uint32_t ccx; + uint32_t comp = (Ports[PortNum].CCx == CC1) ? LL_UCPD_SNK_CC1_VOPEN : LL_UCPD_SNK_CC2_VOPEN; + +#if defined(_LOW_POWER) || defined(USBPDM1_VCC_FEATURE_ENABLED) + /* Enable type C state machine */ + CLEAR_BIT(Ports[PortNum].husbpd->CR, UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS); + + for (int32_t index = 0; index < CAD_DELAY_READ_CC_STATUS; index++) + { + __DSB(); + }; +#endif /* _LOW_POWER || USBPDM1_VCC_FEATURE_ENABLED */ + + ccx = (Ports[PortNum].CCx == CC1) ? (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1) + : (Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2); + if ((USBPD_TRUE == USBPD_PWR_IF_GetVBUSStatus(PortNum, + USBPD_PWR_SNKDETACH)) /* Check if Vbus is below disconnect threshold */ + && + (comp == ccx) /* Confirm that there is no RP */ + ) + { + HW_SignalDetachment(PortNum); + /* Restart the toggle time */ + _handle->CurrentHWcondition = HW_Detachment; + _handle->cstate = USBPD_CAD_STATE_DETACHED; +#if defined(_ACCESSORY_SNK) + if (USBPD_TRUE == _handle->CAD_Accessory_SNK) + { + _handle->CAD_tToggle_start = HAL_GetTick(); + } +#endif /* _ACCESSORY_SNK */ + *pEvent = USBPD_CAD_EVENT_DETACHED; + *pCCXX = CCNONE; + _timing = 0; + } + else + { + _timing = CAD_VBUS_POLLING_TIME; + } + +#if defined(_LOW_POWER) || defined(USBPDM1_VCC_FEATURE_ENABLED) + /* Disable type C state machine */ + SET_BIT(Ports[PortNum].husbpd->CR, UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS); +#endif /* _LOW_POWER || USBPDM1_VCC_FEATURE_ENABLED */ + + return _timing; +} +#endif /* _SNK || _DRP */ + +#if defined(TCPP0203_SUPPORT) +/** + * @brief VBUS detect callback + * @param PortNum Port + * @param VBUSConnectionStatus VBUS connection status, based on @ref USBPD_PWR_VBUSConnectionStatusTypeDef + * @retval None + */ +void CAD_HW_IF_VBUSDetectCallback(uint32_t PortNum, + USBPD_PWR_VBUSConnectionStatusTypeDef VBUSConnectionStatus) +{ + /* If VBUS is connected */ + if (VBUSConnectionStatus == VBUS_CONNECTED) + { +#if defined(_TRACE) + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, PortNum, 0, + (uint8_t *)"-- USBPD_PWR_VBUSDetectCallback : VBUS_CONNECTED --", 51); +#endif /* _TRACE */ + } + else + { +#if defined(_TRACE) + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, PortNum, 0, + (uint8_t *)"-- USBPD_PWR_VBUSDetectCallback : VBUS_NOT_CONNECTED --", 55); +#endif /* _TRACE */ + + /* VBUS_NOT_CONNECTED indications could be caused by false OCP/OVP errors detected at BSP level. + If reported here, it is assumed that it might be possible to recover from error. + If error could not be recovered, or is assumed to be related to a true safety issue, it will not be notified + by BSP */ +#if defined(USBPDCORE_LIB_NO_PD) + CAD_HW_HandleTypeDef *_handle = &CAD_HW_Handles[PortNum]; + + /* VBUS_NOT_CONNECTED indication management in case of NO_PD configuration */ + if (Ports[PortNum].params->PE_PowerRole == USBPD_PORTPOWERROLE_SRC) + { + /* Current role is SRC when VBUS_NOT_CONNECTED signal is received */ + HW_SignalDetachment(PortNum); + _handle->CAD_tDebounce_flag = USBPD_FALSE; + _handle->cstate = USBPD_CAD_STATE_DETACH_SRC; + } + else + { + /* Current role is SNK when VBUS_NOT_CONNECTED signal is received */ + HW_SignalDetachment(PortNum); + _handle->CurrentHWcondition = HW_Detachment; + _handle->cstate = USBPD_CAD_STATE_DETACHED; + } +#else + /* VBUS_NOT_CONNECTED indication management : Error has to be handled through a Detach/Attach procedure. + Handled using ErrorRecovery mechanism */ + CAD_Enter_ErrorRecovery(PortNum); +#endif /* USBPDCORE_LIB_NO_PD */ + } +} +#endif /* TCPP0203_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c new file mode 100644 index 0000000..8b4769f --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw.c @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file usbpd_phy_hw_if.c + * @author MCD Application Team + * @brief This file contains phy interface control functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#define USBPD_HW_C +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_devices_conf.h" +#include "usbpd_hw.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Variable containing ADC conversions results */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +UCPD_TypeDef *USBPD_HW_GetUSPDInstance(uint8_t PortNum) +{ + return UCPD_INSTANCE0; +} + +#if !defined(USBPDCORE_LIB_NO_PD) +DMA_Channel_TypeDef *USBPD_HW_Init_DMARxInstance(uint8_t PortNum) +{ + LL_DMA_InitTypeDef DMA_InitStruct; + + /* Initialise the DMA */ + LL_DMA_StructInit(&DMA_InitStruct); + DMA_InitStruct.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct.Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; + DMA_InitStruct.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct.NbData = 0; + DMA_InitStruct.MemoryOrM2MDstAddress = 0x0; + DMA_InitStruct.PeriphOrM2MSrcAddress = 0x0; + DMA_InitStruct.Priority = LL_DMA_PRIORITY_HIGH; + + /* Enable the clock */ + UCPDDMA_INSTANCE0_CLOCKENABLE_RX; + + /* Initialise the DMA */ + DMA_InitStruct.PeriphRequest = UCPDDMA_INSTANCE0_REQUEST_RX; + + (void)LL_DMA_Init(UCPDDMA_INSTANCE0_DMA_RX, UCPDDMA_INSTANCE0_LL_CHANNEL_RX, &DMA_InitStruct); + return UCPDDMA_INSTANCE0_CHANNEL_RX; +} + +void USBPD_HW_DeInit_DMARxInstance(uint8_t PortNum) +{ + (void)PortNum; +} + +DMA_Channel_TypeDef *USBPD_HW_Init_DMATxInstance(uint8_t PortNum) +{ + LL_DMA_InitTypeDef DMA_InitStruct; + + /* Initialise the DMA */ + LL_DMA_StructInit(&DMA_InitStruct); + DMA_InitStruct.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; + DMA_InitStruct.Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; + DMA_InitStruct.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct.NbData = 0; + DMA_InitStruct.MemoryOrM2MDstAddress = 0x0; + DMA_InitStruct.PeriphOrM2MSrcAddress = 0x0; + + /* Enable the clock */ + UCPDDMA_INSTANCE0_CLOCKENABLE_TX; + + DMA_InitStruct.PeriphRequest = UCPDDMA_INSTANCE0_REQUEST_TX; + DMA_InitStruct.Priority = LL_DMA_PRIORITY_MEDIUM; + (void)LL_DMA_Init(UCPDDMA_INSTANCE0_DMA_TX, UCPDDMA_INSTANCE0_LL_CHANNEL_TX, &DMA_InitStruct); + return UCPDDMA_INSTANCE0_CHANNEL_TX; +} + +void USBPD_HW_DeInit_DMATxInstance(uint8_t PortNum) +{ + (void)PortNum; +} +#endif /* !USBPDCORE_LIB_NO_PD */ + +uint32_t USBPD_HW_GetRpResistorValue(uint8_t PortNum) +{ + (void)PortNum; + return LL_UCPD_RESISTOR_3_0A; +} + +void USBPD_HW_SetFRSSignalling(uint8_t PortNum, uint8_t cc) +{ + (void)PortNum; + + /* Configure FRSTX GPIO */ + if (1u == cc) + { + /* FRS_TX common */ + UCPDFRS_INSTANCE0_FRSCC1; + } + else + { + /* FRS_TX common */ + UCPDFRS_INSTANCE0_FRSCC2; + } +} + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c new file mode 100644 index 0000000..0cc589b --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_hw_if_it.c @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file usbpd_hw_if_it.c + * @author MCD Application Team + * @brief This file contains HW interface interrupt routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_devices_conf.h" +#include "usbpd_core.h" +#include "usbpd_hw_if.h" +#include "usbpd_trace.h" +#if defined(_LOW_POWER) +#include "usbpd_lowpower.h" +#endif /* _LOW_POWER */ +#if defined(_FRS) +#include "usbpd_timersserver.h" +#endif /* _FRS */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +void PORTx_IRQHandler(uint8_t PortNum); + +void USBPD_PORT0_IRQHandler(void) +{ + PORTx_IRQHandler(USBPD_PORT_0); +} + +void PORTx_IRQHandler(uint8_t PortNum) +{ + UCPD_TypeDef *hucpd = Ports[PortNum].husbpd; + uint32_t _interrupt = LL_UCPD_ReadReg(hucpd, SR); + static uint8_t ovrflag = 0; + + if ((hucpd->IMR & _interrupt) != 0u) + { + /* TXIS no need to enable it all the transfer are done by DMA */ + if (UCPD_SR_TXMSGDISC == (_interrupt & UCPD_SR_TXMSGDISC)) + { + /* Message has been discarded */ + LL_UCPD_ClearFlag_TxMSGDISC(hucpd); + CLEAR_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); + while ((Ports[PortNum].hdmatx->CCR & DMA_CCR_EN) == DMA_CCR_EN); + Ports[PortNum].cbs.USBPD_HW_IF_TxCompleted(PortNum, 1); + return; + } + + if (UCPD_SR_TXMSGSENT == (_interrupt & UCPD_SR_TXMSGSENT)) + { + /* Message has been fully transferred */ + LL_UCPD_ClearFlag_TxMSGSENT(hucpd); + CLEAR_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); + while ((Ports[PortNum].hdmatx->CCR & DMA_CCR_EN) == DMA_CCR_EN); + Ports[PortNum].cbs.USBPD_HW_IF_TxCompleted(PortNum, 0); + +#if defined(_LOW_POWER) + UTIL_LPM_SetStopMode(0 == PortNum ? LPM_PE_0 : LPM_PE_1, UTIL_LPM_ENABLE); +#endif /* _LOW_POWER */ + return; + } + + if (UCPD_SR_TXMSGABT == (_interrupt & UCPD_SR_TXMSGABT)) + { + LL_UCPD_ClearFlag_TxMSGABT(hucpd); + CLEAR_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); + while ((Ports[PortNum].hdmatx->CCR & DMA_CCR_EN) == DMA_CCR_EN); + Ports[PortNum].cbs.USBPD_HW_IF_TxCompleted(PortNum, 2); + return; + } + + /* HRSTDISC : hard reset sending has been discarded */ + if (UCPD_SR_HRSTDISC == (_interrupt & UCPD_SR_HRSTDISC)) + { + LL_UCPD_ClearFlag_TxHRSTDISC(hucpd); + return; + } + + /* TXUND : tx underrun detected */ + if (UCPD_SR_HRSTSENT == (_interrupt & UCPD_SR_HRSTSENT)) + { + /* Answer not expected by the stack */ + LL_UCPD_ClearFlag_TxHRSTSENT(hucpd); + Ports[PortNum].cbs.USBPD_HW_IF_TX_HardResetCompleted(PortNum, USBPD_SOPTYPE_HARD_RESET); + return; + } + + /* TXUND : tx underrun detected */ + if (UCPD_SR_TXUND == (_interrupt & UCPD_SR_TXUND)) + { + /* Nothing to do. + The port partner checks the message integrity with CRC, so PRL will repeat the sending. + Can be used for debugging purpose */ + LL_UCPD_ClearFlag_TxUND(hucpd); + return; + } + + /* RXNE : not needed the stack only perform transfer by DMA */ + /* RXORDDET: not needed so stack will not enabled this interrupt */ + if (UCPD_SR_RXORDDET == (_interrupt & UCPD_SR_RXORDDET)) + { + if (LL_UCPD_RXORDSET_CABLE_RESET == hucpd->RX_ORDSET) + { + /* Cable reset detected */ + Ports[PortNum].cbs.USBPD_HW_IF_RX_ResetIndication(PortNum, USBPD_SOPTYPE_CABLE_RESET); + } + LL_UCPD_ClearFlag_RxOrderSet(hucpd); +#if defined(_LOW_POWER) + UTIL_LPM_SetStopMode(0 == PortNum ? LPM_PE_0 : LPM_PE_1, UTIL_LPM_DISABLE); +#endif /* _LOW_POWER */ + + /* Forbid message sending */ + Ports[PortNum].RXStatus = USBPD_TRUE; + return; + } + + /* Check RXHRSTDET */ + if (UCPD_SR_RXHRSTDET == (_interrupt & UCPD_SR_RXHRSTDET)) + { + Ports[PortNum].cbs.USBPD_HW_IF_RX_ResetIndication(PortNum, USBPD_SOPTYPE_HARD_RESET); + LL_UCPD_ClearFlag_RxHRST(hucpd); + return; + } + + /* Check RXOVR */ + if (UCPD_SR_RXOVR == (_interrupt & UCPD_SR_RXOVR)) + { + /* Nothing to do, the message will be discarded and port Partner will try sending again. */ + ovrflag = 1; + LL_UCPD_ClearFlag_RxOvr(hucpd); + return; + } + + /* Check RXMSGEND an Rx message has been received */ + if (UCPD_SR_RXMSGEND == (_interrupt & UCPD_SR_RXMSGEND)) + { + Ports[PortNum].RXStatus = USBPD_FALSE; + + /* For DMA mode, add a check to ensure the number of data received matches + the number of data received by UCPD */ + LL_UCPD_ClearFlag_RxMsgEnd(hucpd); + + /* Disable DMA */ + CLEAR_BIT(Ports[PortNum].hdmarx->CCR, DMA_CCR_EN); + while ((Ports[PortNum].hdmarx->CCR & DMA_CCR_EN) == DMA_CCR_EN); + + /* Ready for next transaction */ + WRITE_REG(Ports[PortNum].hdmarx->CMAR, (uint32_t)Ports[PortNum].ptr_RxBuff); + WRITE_REG(Ports[PortNum].hdmarx->CNDTR, SIZE_MAX_PD_TRANSACTION_UNCHUNK); + + /* Enable the DMA */ + SET_BIT(Ports[PortNum].hdmarx->CCR, DMA_CCR_EN); +#if defined(_LOW_POWER) + UTIL_LPM_SetStopMode(0 == PortNum ? LPM_PE_0 : LPM_PE_1, UTIL_LPM_ENABLE); +#endif /* _LOW_POWER */ + + if (((_interrupt & UCPD_SR_RXERR) == 0u) && (ovrflag == 0u)) + { + /* Rx message has been received without error */ + Ports[PortNum].cbs.USBPD_HW_IF_RX_Completed(PortNum, hucpd->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET); + } + ovrflag = 0; + return; + } + + /* Check TYPECEVT1IE/TYPECEVT1IE || check TYPECEVT2IE/TYPECEVT2IE */ + if ((UCPD_SR_TYPECEVT1 == (_interrupt & UCPD_SR_TYPECEVT1)) + || (UCPD_SR_TYPECEVT2 == (_interrupt & UCPD_SR_TYPECEVT2))) + { + /* Clear both interrupt */ + LL_UCPD_ClearFlag_TypeCEventCC1(hucpd); + LL_UCPD_ClearFlag_TypeCEventCC2(hucpd); + Ports[PortNum].USBPD_CAD_WakeUp(); + /* Wakeup CAD to check the detection event */ + return; + } + +#if defined(_FRS) + /* Check FRSEVTIE */ + if (UCPD_SR_FRSEVT == (_interrupt & UCPD_SR_FRSEVT)) + { + LL_UCPD_ClearFlag_FRS(hucpd); + if ((USBPD_PORTPOWERROLE_SNK == Ports[PortNum].params->PE_PowerRole) + && (Ports[PortNum].params->PE_SwapOngoing == USBPD_FALSE)) + { + /* Confirm the FRS by checking if an RP is always present on the current CC line. + We should wait for maximum FRS timing */ + USBPD_TIM_Start((TIM_identifier)(2 * PortNum), 150); + while ((USBPD_TIM_IsExpired((TIM_identifier)(2u * PortNum)) == 0u)); + + if ((0 != (hucpd->SR & (UCPD_SR_TYPEC_VSTATE_CC1 | UCPD_SR_TYPEC_VSTATE_CC2))) && + (USBPD_POWER_EXPLICITCONTRACT == Ports[PortNum].params->PE_Power)) + { + /* Switch the power to take the control of VBUS. + When VBUS go under VSAFE5V the sink shall switch ON VBUS in timing < tSrcFRSwap */ + BSP_USBPD_PWR_FRSVBUSEnable(PortNum); + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, PortNum, 0, "FRS received", 12u); + Ports[PortNum].cbs.USBPD_HW_IF_TX_FRSReception(PortNum); + } + } + } +#endif /* _FRS */ + } +} + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c new file mode 100644 index 0000000..16827a2 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy.c @@ -0,0 +1,390 @@ +/** + ****************************************************************************** + * @file usbpd_phy.c + * @author MCD Application Team + * @brief This file contains PHY layer functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_def.h" +#include "usbpd_phy.h" +#include "usbpd_hw_if.h" +#include "usbpd_pwr_if.h" + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_DEVICE + * @{ + */ + +/** @addtogroup USBPD_DEVICE_PHY + * @brief This file contains PHY layer functions. + * @details Receive from PRL a message and create a structured packet (according to the USBPD specifications): + * |SOP|DATA:[HEADER|DATAOBJECTS]|CRC|EOP| + * @{ + */ + +/* Private defines -----------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup USBPD_DEVICE_PHY_Private_typedef USBPD DEVICE PHY Private typedef + * @brief Structures and enums internally used by the PHY layer + * @{ + */ + + +/** + * @brief Handle to support the data of the layer + */ +typedef struct +{ + /** + * @brief Reports that a message has been received on a specified port. + * @note Received data are stored inside PortNum->pRxBuffPtr + * function called in the interrupt context + * @param PortNum The handle of the port + * @param Type The type of the message received @ref USBPD_SOPType_TypeDef + * @retval None + */ + void (*USBPD_PHY_MessageReceived)(uint8_t PortNum, USBPD_SOPType_TypeDef Type); + + uint32_t SupportedSOP; /*!USBPD_PHY_TxCompleted; + Ports[PortNum].cbs.USBPD_HW_IF_BistCompleted = pCallbacks->USBPD_PHY_BistCompleted; + Ports[PortNum].cbs.USBPD_HW_IF_RX_ResetIndication = pCallbacks->USBPD_PHY_ResetIndication; + Ports[PortNum].cbs.USBPD_HW_IF_RX_Completed = PHY_Rx_Completed; + Ports[PortNum].cbs.USBPD_HW_IF_TX_HardResetCompleted = pCallbacks->USBPD_PHY_ResetCompleted; + Ports[PortNum].cbs.USBPD_HW_IF_TX_FRSReception = pCallbacks->USBPD_PHY_FastRoleSwapReception; + /* Initialize the hardware for the port */ + Ports[PortNum].ptr_RxBuff = pRxBuffer; + + /* Initialize port related functionalities inside this layer */ + PHY_Ports[PortNum].SupportedSOP = SupportedSOP; + PHY_Ports[PortNum].USBPD_PHY_MessageReceived = pCallbacks->USBPD_PHY_MessageReceived; + + return USBPD_OK; +} + +/** + * @brief this function return the retry counter value in us. + * @note time used to determine when the protocol layer must re-send a message not acknowledged by a goodCRC + * @param PortNum Number of the port. + * @retval retry counter value in us. + */ +uint16_t USBPD_PHY_GetRetryTimerValue(uint8_t PortNum) +{ + (void)PortNum; + return 905u; +} + +/** + * @brief this function return the min time to wait before sending a goodCRC to ack a message (in us). + * @note time used to guarantee the min time of 26us between two PD message. + * @param PortNum Number of the port. + * @retval value in us. + */ +uint16_t USBPD_PHY_GetMinGOODCRCTimerValue(uint8_t PortNum) +{ + return 30u; +} + +/** + * @brief Reset the PHY of a specified port. + * @param PortNum Number of the port. + * @retval None + */ +void USBPD_PHY_Reset(uint8_t PortNum) +{ + (void)PortNum; + /* Reset PHY layer */ + /* Reset HW_IF layer */ +} + +/** + * @brief Request to send a reset on a port. + * @param PortNum Number of the port + * @param Type Type of reset (hard or cable reset) @ref USBPD_SOPTYPE_HARD_RESET or @ref USBPD_SOPTYPE_CABLE_RESET + * @retval status @ref USBPD_OK + */ +USBPD_StatusTypeDef USBPD_PHY_ResetRequest(uint8_t PortNum, USBPD_SOPType_TypeDef Type) +{ + /* Send the requested reset */ + return USBPD_PHY_SendMessage(PortNum, Type, NULL, 0); +} + +/** + * @brief Send a Message. + * @param PortNum Number of the port + * @param Type Type of the message + * @param pBuffer Pointer to the buffer to be transmitted + * @param Size Size of the buffer (bytes) + * @retval status @ref USBPD_OK + */ +USBPD_StatusTypeDef USBPD_PHY_SendMessage(uint8_t PortNum, USBPD_SOPType_TypeDef Type, uint8_t *pBuffer, uint16_t Size) +{ + /* Trace to track message */ + return USBPD_HW_IF_SendBuffer(PortNum, Type, pBuffer, Size); +} + +/** + * @brief Send BIST pattern. + * @param PortNum Number of the port + * @retval status @ref USBPD_OK + */ +USBPD_StatusTypeDef USBPD_PHY_Send_BIST_Pattern(uint8_t PortNum) +{ + /* Call the low-level function (HW_IF) to accomplish the BIST Carrier Mode Transmission */ + USBPD_HW_IF_Send_BIST_Pattern(PortNum); + return USBPD_OK; +} + +/** + * @brief Request PHY to exit of BIST mode 2 + * @param PortNum port number value + * @param mode SOP BIST MODE 2 + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PHY_ExitTransmit(uint8_t PortNum, USBPD_SOPType_TypeDef mode) +{ + if (USBPD_SOPTYPE_BIST_MODE_2 == mode) + { + USBPD_HW_IF_StopBISTMode2(PortNum); + } + return USBPD_OK; +} + +/** + * @brief Set the SinkTxNg value of the resistor, + * @note used to manage the collision avoidance + * @param PortNum Number of the port + * @retval None + */ +void USBPD_PHY_SetResistor_SinkTxNG(uint8_t PortNum) +{ + USBPD_HW_IF_SetResistor_SinkTxNG(PortNum); +} + +/** + * @brief function to set the SinkTxOK + * @note used to manage the collision avoidance + * @param PortNum Number of the port. + * @retval none. + */ +void USBPD_PHY_SetResistor_SinkTxOK(uint8_t PortNum) +{ + USBPD_HW_IF_SetResistor_SinkTxOK(PortNum); +} + +/** + * @brief function to set the supported SOP + * @param PortNum Number of the port. + * @param SOPSupported List of the supported SOP + * @retval None. + */ +void USBPD_PHY_SOPSupported(uint8_t PortNum, uint32_t SOPSupported) +{ + PHY_Ports[PortNum].SupportedSOP = SOPSupported; +} + +/** + * @brief Check if SinkTxOK is set or not + * @note used to manage the collision avoidance + * @param PortNum Number of the port. + * @retval USBPD_TRUE or USBPD_FALSE + */ +uint8_t USBPD_PHY_IsResistor_SinkTxOk(uint8_t PortNum) +{ + return USBPD_HW_IF_IsResistor_SinkTxOk(PortNum); +} + +/** + * @brief function to generate an FRS signalling + * @param PortNum Number of the port. + * @retval None. + */ +void USBPD_PHY_FastRoleSwapSignalling(uint8_t PortNum) +{ + USBPD_HW_IF_FastRoleSwapSignalling(PortNum); +} + +/** + * @brief function used to enable RX + * @param PortNum Number of the port. + * @retval None + */ +void USBPD_PHY_EnableRX(uint8_t PortNum) +{ + USBPD_HW_IF_EnableRX(PortNum); +} + +/** + * @brief function used to disable RX + * @param PortNum Number of the port. + * @retval None + */ +void USBPD_PHY_DisableRX(uint8_t PortNum) +{ + USBPD_HW_IF_DisableRX(PortNum); +} + +/** + * @} + */ + +/** @addtogroup USBPD_DEVICE_PHY_Private_functions + * @brief PHY internally used functions + * @{ + */ + +/** + * @brief Callback to notify the end of the current reception + * @param PortNum Number of the port. + * @param MsgType SOP Message Type + * @retval None. + */ +void PHY_Rx_Completed(uint8_t PortNum, uint32_t MsgType) +{ + const USBPD_SOPType_TypeDef tab_sop_value[] = + { + USBPD_SOPTYPE_SOP, USBPD_SOPTYPE_SOP1, USBPD_SOPTYPE_SOP2, + USBPD_SOPTYPE_SOP1_DEBUG, USBPD_SOPTYPE_SOP2_DEBUG, USBPD_SOPTYPE_CABLE_RESET + }; + USBPD_SOPType_TypeDef _msgtype; + + _msgtype = tab_sop_value[MsgType]; + + /* Check if the message must be forwarded to usbpd stack */ + switch (_msgtype) + { + case USBPD_SOPTYPE_CABLE_RESET : + if (0x1Eu == (PHY_Ports[PortNum].SupportedSOP & 0x1Eu)) + { + /* Nothing to do the message will be discarded and the port partner retry the send */ + Ports[PortNum].cbs.USBPD_HW_IF_RX_ResetIndication(PortNum, USBPD_SOPTYPE_CABLE_RESET); + } + break; + case USBPD_SOPTYPE_SOP : + case USBPD_SOPTYPE_SOP1 : + case USBPD_SOPTYPE_SOP2 : + case USBPD_SOPTYPE_SOP1_DEBUG : + case USBPD_SOPTYPE_SOP2_DEBUG : + if (!((uint8_t)(0x1u << _msgtype) != (PHY_Ports[PortNum].SupportedSOP & (uint8_t)(0x1u << _msgtype)))) + { + PHY_Ports[PortNum].USBPD_PHY_MessageReceived(PortNum, _msgtype); + } +#if defined(DEBUG_NOTFWD) + else + { + typedef union + { + uint16_t d16; + struct + { + uint16_t MessageType :5; /*!< Message Header's message Type */ + uint16_t PortDataRole :1; /*!< Message Header's Port Data Role */ + uint16_t SpecificationRevision :2; /*!< Message Header's Spec Revision */ + uint16_t PortPowerRole_CablePlug:1; /*!< Message Header's Port Power Role/Cable Plug field */ + uint16_t MessageID :3; /*!< Message Header's message ID */ + uint16_t NumberOfDataObjects :3; /*!< Message Header's Number of data object */ + uint16_t Extended :1; /*!< Reserved */ + } + b; + } USBPD_MsgHeader_TypeDef; + + USBPD_MsgHeader_TypeDef header_rx; + header_rx.d16 = USBPD_LE16(Ports[PortNum].ptr_RxBuff); + USBPD_TRACE_Add(USBPD_TRACE_PHY_NOTFRWD, PortNum, _msgtype, Ports[PortNum].ptr_RxBuff, + 2u + (header_rx.b.NumberOfDataObjects * 4u)); + } +#endif /* DEBUG_NOTFWD */ + break; + default : + break; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c new file mode 100644 index 0000000..909b08f --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_phy_hw_if.c @@ -0,0 +1,509 @@ +/** + ****************************************************************************** + * @file usbpd_phy_hw_if.c + * @author MCD Application Team + * @brief This file contains phy interface control functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#define USBPD_PHY_HW_IF_C + +#include "usbpd_devices_conf.h" +#include "usbpd_hw.h" +#include "usbpd_core.h" +#include "usbpd_hw_if.h" +#if !defined(USBPDCORE_LIB_NO_PD) +#include "usbpd_timersserver.h" +#endif /* !USBPDCORE_LIB_NO_PD */ +#if defined(_LOW_POWER) +#include "usbpd_lowpower.h" +#include "usbpd_cad_hw_if.h" +#endif /* _LOW_POWER */ + +/* Private typedef -----------------------------------------------------------*/ +#define PHY_ENTER_CRITICAL_SECTION() uint32_t primask = __get_PRIMASK(); \ + __disable_irq(); + +#define PHY_LEAVE_CRITICAL_SECTION() __set_PRIMASK(primask); + +/* Private function prototypes -----------------------------------------------*/ +USBPD_PORT_HandleTypeDef Ports[USBPD_PORT_COUNT]; + + +/* Private functions ---------------------------------------------------------*/ + + +void USBPD_HW_IF_GlobalHwInit(void) +{ + /* PWR register access (for disabling dead battery feature) */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC); + +} + +#if !defined(USBPDCORE_LIB_NO_PD) +void USBPD_HW_IF_StopBISTMode2(uint8_t PortNum) +{ + uint32_t _cr = READ_REG(Ports[PortNum].husbpd->CR) & ~(UCPD_CR_TXMODE | UCPD_CR_TXSEND); + + LL_UCPD_Disable(Ports[PortNum].husbpd); + LL_UCPD_Enable(Ports[PortNum].husbpd); + + Ports[PortNum].husbpd->CR = _cr; +} + +USBPD_StatusTypeDef USBPD_HW_IF_SendBuffer(uint8_t PortNum, USBPD_SOPType_TypeDef Type, uint8_t *pBuffer, uint32_t Size) +{ + USBPD_StatusTypeDef _status = USBPD_OK; + + if (USBPD_SOPTYPE_HARD_RESET == Type) + { + LL_UCPD_SendHardReset(Ports[PortNum].husbpd); + } + else + { + PHY_ENTER_CRITICAL_SECTION() + + /* If RX is ongoing or if a DMA transfer is active then discard the buffer sending */ + if ((Ports[PortNum].RXStatus == USBPD_TRUE) || ((Ports[PortNum].hdmatx->CCR & DMA_CCR_EN) == DMA_CCR_EN)) + { + PHY_LEAVE_CRITICAL_SECTION() + _status = USBPD_ERROR; + } + else + { + PHY_LEAVE_CRITICAL_SECTION() + + switch (Type) + { + case USBPD_SOPTYPE_SOP : + { + LL_UCPD_WriteTxOrderSet(Ports[PortNum].husbpd, LL_UCPD_ORDERED_SET_SOP); + LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_NORMAL); + break; + } + case USBPD_SOPTYPE_SOP1 : + { + LL_UCPD_WriteTxOrderSet(Ports[PortNum].husbpd, LL_UCPD_ORDERED_SET_SOP1); + LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_NORMAL); + break; + } + case USBPD_SOPTYPE_SOP2 : + { + LL_UCPD_WriteTxOrderSet(Ports[PortNum].husbpd, LL_UCPD_ORDERED_SET_SOP2); + LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_NORMAL); + break; + } + case USBPD_SOPTYPE_CABLE_RESET : + { + LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_CABLE_RESET); + break; + } + case USBPD_SOPTYPE_BIST_MODE_2 : + { + LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_BIST_CARRIER2); + break; + } + default : + _status = USBPD_ERROR; + break; + } + + if (USBPD_OK == _status) + { +#if defined(_LOW_POWER) + UTIL_LPM_SetStopMode(0 == PortNum ? LPM_PE_0 : LPM_PE_1, UTIL_LPM_DISABLE); +#endif /* _LOW_POWER */ + CLEAR_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); + while ((Ports[PortNum].hdmatx->CCR & DMA_CCR_EN) == DMA_CCR_EN); + + WRITE_REG(Ports[PortNum].hdmatx->CMAR, (uint32_t)pBuffer); + WRITE_REG(Ports[PortNum].hdmatx->CNDTR, Size); + SET_BIT(Ports[PortNum].hdmatx->CCR, DMA_CCR_EN); + + LL_UCPD_WriteTxPaySize(Ports[PortNum].husbpd, Size); + LL_UCPD_SendMessage(Ports[PortNum].husbpd); + } + } + } + return _status; +} + +void USBPD_HW_IF_Send_BIST_Pattern(uint8_t PortNum) +{ + LL_UCPD_SetTxMode(Ports[PortNum].husbpd, LL_UCPD_TXMODE_BIST_CARRIER2); + LL_UCPD_SendMessage(Ports[PortNum].husbpd); +} +#endif /* !USBPDCORE_LIB_NO_PD */ + +/** + * @brief Assert Rp resistors + * @param PortNum Port + * @retval None + */ +void USBPDM1_AssertRp(uint8_t PortNum) +{ + switch (Ports[PortNum].params->RpResistor) + { + case vRp_Default : + LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_DEFAULT); + break; + case vRp_1_5A: + LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_1_5A); + break; + case vRp_3_0A: + LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_3_0A); + break; + default: + break; + } + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_NONE); + LL_UCPD_SetSRCRole(Ports[PortNum].husbpd); + if (CCNONE == Ports[PortNum].CCx) + { + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); + } + else + { + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, + (Ports[PortNum].CCx == CC1) ? LL_UCPD_CCENABLE_CC1 : LL_UCPD_CCENABLE_CC2); + } + +#if defined(TCPP0203_SUPPORT) + BSP_USBPD_PWR_SetRole(PortNum, POWER_ROLE_SOURCE); +#endif /* TCPP0203_SUPPORT */ +} +/** + * @brief De-assert Rp resistors + * @param PortNum Port + * @retval None + */ +void USBPDM1_DeAssertRp(uint8_t PortNum) +{ + /* Not needed on STM32G4xx, so nothing to do, keep only for compatibility */ + UNUSED(PortNum); +} + +/** + * @brief Assert Rd resistors + * @param PortNum Port + * @retval None + */ +void USBPDM1_AssertRd(uint8_t PortNum) +{ + LL_UCPD_TypeCDetectionCC2Disable(Ports[PortNum].husbpd); + LL_UCPD_TypeCDetectionCC1Disable(Ports[PortNum].husbpd); + + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_NONE); + LL_UCPD_SetSNKRole(Ports[PortNum].husbpd); + if (CCNONE == Ports[PortNum].CCx) + { + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); + } + else + { + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, + (Ports[PortNum].CCx == CC1) ? LL_UCPD_CCENABLE_CC1 : LL_UCPD_CCENABLE_CC2); + } + + HAL_Delay(1); + +#ifndef _LOW_POWER + LL_UCPD_TypeCDetectionCC2Enable(Ports[PortNum].husbpd); + LL_UCPD_TypeCDetectionCC1Enable(Ports[PortNum].husbpd); +#endif /* _LOW_POWER */ + +#if defined(TCPP0203_SUPPORT) + BSP_USBPD_PWR_SetRole(PortNum, POWER_ROLE_SINK); +#endif /* TCPP0203_SUPPORT */ +} + +/** + * @brief Assert Rd resistors + * @param PortNum Port + * @retval none + */ +void USBPDM1_DeAssertRd(uint8_t PortNum) +{ + /* Not needed on STM32G4xx, so nothing to do, keep only for compatibility */ + UNUSED(PortNum); +} + +/** + * @brief Enter error recovery + * @param PortNum Port + * @retval None + */ +void USBPDM1_EnterErrorRecovery(uint8_t PortNum) +{ + LL_UCPD_SetSRCRole(Ports[PortNum].husbpd); + LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_NONE); + LL_UCPD_RxDisable(Ports[PortNum].husbpd); + +#if !defined(USBPDCORE_LIB_NO_PD) + if (Ports[PortNum].settings->PE_PD3_Support.d.PE_FastRoleSwapSupport == USBPD_TRUE) + { + /* Set GPIO to disallow the FRS RX handling */ + LL_UCPD_FRSDetectionDisable(Ports[PortNum].husbpd); + } +#endif /* USBPDCORE_LIB_NO_PD */ +} + +/** + * @brief Set the correct CC pin on the comparator + * @param PortNum Port + * @param cc CC pin based on @ref CCxPin_TypeDef + * @retval None + */ +void USBPDM1_Set_CC(uint8_t PortNum, CCxPin_TypeDef cc) +{ + /* Set the correct pin on the comparator */ + Ports[PortNum].CCx = cc; + LL_UCPD_SetCCPin(Ports[PortNum].husbpd, (cc == CC1) ? LL_UCPD_CCPIN_CC1 : LL_UCPD_CCPIN_CC2); +} + +/** + * @brief Enable RX interrupt + * @param PortNum Port + * @retval None + */ +void USBPDM1_RX_EnableInterrupt(uint8_t PortNum) +{ + /* Enable the RX interrupt process */ + MODIFY_REG(Ports[PortNum].husbpd->IMR, + UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE, + UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE); + LL_UCPD_RxDMAEnable(Ports[PortNum].husbpd); +} + +/** + * @brief Enable RX + * @param PortNum Port + * @retval None + */ +void USBPD_HW_IF_EnableRX(uint8_t PortNum) +{ + LL_UCPD_RxEnable(Ports[PortNum].husbpd); +} + +/** + * @brief Disable RX + * @param PortNum Port + * @retval None + */ +void USBPD_HW_IF_DisableRX(uint8_t PortNum) +{ + LL_UCPD_RxDisable(Ports[PortNum].husbpd); +} + +void HW_SignalAttachement(uint8_t PortNum, CCxPin_TypeDef cc) +{ +#if !defined(USBPDCORE_LIB_NO_PD) + uint32_t _temp; + + /* Init timer to detect the reception of goodCRC */ + USBPD_TIM_Init(); + + /* Prepare ucpd to handle PD message + RX message start listen + TX prepare the DMA to be transfer ready + Detection listen only the line corresponding CC=Rd for SRC/SNK */ + Ports[PortNum].hdmatx = USBPD_HW_Init_DMATxInstance(PortNum); + Ports[PortNum].hdmarx = USBPD_HW_Init_DMARxInstance(PortNum); + + /* Set the RX dma to allow reception */ + _temp = (uint32_t)&Ports[PortNum].husbpd->RXDR; + WRITE_REG(Ports[PortNum].hdmarx->CPAR, _temp); + WRITE_REG(Ports[PortNum].hdmarx->CMAR, (uint32_t)Ports[PortNum].ptr_RxBuff); + Ports[PortNum].hdmarx->CNDTR = SIZE_MAX_PD_TRANSACTION_UNCHUNK; + Ports[PortNum].hdmarx->CCR |= DMA_CCR_EN; + + /* Set the TX dma only UCPD address */ + _temp = (uint32_t)&Ports[PortNum].husbpd->TXDR; + Ports[PortNum].hdmatx->CPAR = _temp; + + /* Disabled non Rd line set CC line enable */ +#define INTERRUPT_MASK UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | \ + UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | \ + UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE + + MODIFY_REG(Ports[PortNum].husbpd->IMR, INTERRUPT_MASK, INTERRUPT_MASK); +#endif /* !USBPDCORE_LIB_NO_PD */ + + /* Handle CC enable */ + Ports[PortNum].CCx = cc; + +#if !defined(USBPDCORE_LIB_NO_PD) + /* Set CC pin for PD message */ + LL_UCPD_SetCCPin(Ports[PortNum].husbpd, (Ports[PortNum].CCx == CC1) ? LL_UCPD_CCPIN_CC1 : LL_UCPD_CCPIN_CC2); + + +#if defined(_VCONN_SUPPORT) + /* Initialize Vconn management */ + (void)BSP_USBPD_PWR_VCONNInit(PortNum, (Ports[PortNum].CCx == CC1) ? 1u : 2u); +#endif /* _VCONN_SUPPORT */ + + if (Ports[PortNum].settings->PE_PD3_Support.d.PE_FastRoleSwapSupport == USBPD_TRUE) + { + /* Set GPIO to allow the FRS TX handling */ + USBPD_HW_SetFRSSignalling(PortNum, (Ports[PortNum].CCx == CC1) ? 1u : 2u); + /* Enable FRS RX */ + LL_UCPD_FRSDetectionEnable(Ports[PortNum].husbpd); + Ports[PortNum].husbpd->IMR |= UCPD_IMR_FRSEVTIE; + } + + /* Disable the Resistor on Vconn PIN */ + if (Ports[PortNum].CCx == CC1) + { + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1); + } + else + { + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC2); + } + + /* Prepare the rx processing */ + LL_UCPD_SetRxMode(Ports[PortNum].husbpd, LL_UCPD_RXMODE_NORMAL); + LL_UCPD_RxDMAEnable(Ports[PortNum].husbpd); + LL_UCPD_TxDMAEnable(Ports[PortNum].husbpd); +#endif /* !USBPDCORE_LIB_NO_PD */ +} + + +void HW_SignalDetachment(uint8_t PortNum) +{ +#if !defined(USBPDCORE_LIB_NO_PD) + /* Stop DMA RX/TX */ + LL_UCPD_RxDMADisable(Ports[PortNum].husbpd); + LL_UCPD_TxDMADisable(Ports[PortNum].husbpd); + LL_UCPD_RxDisable(Ports[PortNum].husbpd); + +#if !defined(_LOW_POWER) && !defined(USBPDM1_VCC_FEATURE_ENABLED) + /* Enable only detection interrupt */ + WRITE_REG(Ports[PortNum].husbpd->IMR, UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE); +#elif defined(_LOW_POWER) +#if !defined(_DRP) + if (USBPD_PORTPOWERROLE_SRC == Ports[PortNum].params->PE_PowerRole) + { + /* Enable detection interrupt */ + WRITE_REG(Ports[PortNum].husbpd->IMR, UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE); + } +#endif /* !_DRP */ +#endif /* !_LOW_POWER && !USBPDM1_VCC_FEATURE_ENABLED */ + + USBPD_HW_DeInit_DMATxInstance(PortNum); + USBPD_HW_DeInit_DMARxInstance(PortNum); + + LL_UCPD_SetccEnable(Ports[PortNum].husbpd, LL_UCPD_CCENABLE_CC1CC2); + + if (USBPD_PORTPOWERROLE_SNK == Ports[PortNum].params->PE_PowerRole) + { +#if defined(_VCONN_SUPPORT) + /* DeInitialize Vconn management */ + (void)BSP_USBPD_PWR_VCONNDeInit(PortNum, (Ports[PortNum].CCx == CC1) ? 1u : 2u); +#endif /* _VCONN_SUPPORT */ + /* DeInitialise VBUS power */ + (void)BSP_USBPD_PWR_VBUSDeInit(PortNum); + } + + if (Ports[PortNum].settings->PE_PD3_Support.d.PE_FastRoleSwapSupport == USBPD_TRUE) + { + /* Set GPIO to disallow the FRS RX handling */ + LL_UCPD_FRSDetectionDisable(Ports[PortNum].husbpd); + } + +#endif /* !USBPDCORE_LIB_NO_PD */ + Ports[PortNum].CCx = CCNONE; +#if !defined(USBPDCORE_LIB_NO_PD) + /* DeInit timer to detect the reception of goodCRC */ + USBPD_TIM_DeInit(); +#endif /* !USBPDCORE_LIB_NO_PD */ +} + +/** + * @brief Set resistors to SinkTxNG + * @param PortNum Port + * @retval None + */ +void USBPD_HW_IF_SetResistor_SinkTxNG(uint8_t PortNum) +{ + /* Set the resistor SinkTxNG 1.5A5V */ + LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_1_5A); +} + +/** + * @brief Set resistors to SinkTxOk + * @param PortNum Port + * @retval None + */ +void USBPD_HW_IF_SetResistor_SinkTxOK(uint8_t PortNum) +{ + /* Set the resistor SinkTxNG 3.0A5V */ + LL_UCPD_SetRpResistor(Ports[PortNum].husbpd, LL_UCPD_RESISTOR_3_0A); +} + +/** + * @brief Check if resistors are set to SinkTxOk + * @param PortNum Port + * @retval USBPD_TRUE if resistor is set to SinkTxOk, else USBPD_FALSE + */ +uint8_t USBPD_HW_IF_IsResistor_SinkTxOk(uint8_t PortNum) +{ +#if defined(_LOW_POWER) + /* When in low power mode, the type C state machine is turned off. + To retrieve any potential updates of the SR register, the state machine needs to be re-enabled briefly. */ + + /* Enable type C state machine */ + CLEAR_BIT(Ports[PortNum].husbpd->CR, (UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS)); + + /* Let time for internal state machine to refresh his state */ + for (uint32_t index = 0; index < CAD_DELAY_READ_CC_STATUS; index++) + { + __DSB(); + } + + /* Disable type C state machine */ + SET_BIT(Ports[PortNum].husbpd->CR, (UCPD_CR_CC1TCDIS | UCPD_CR_CC2TCDIS)); +#endif /* _LOW_POWER */ + + switch (Ports[PortNum].CCx) + { + case CC1 : + if ((Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC1) == LL_UCPD_SNK_CC1_VRP30A) + { + return USBPD_TRUE; + } + break; + case CC2 : + if ((Ports[PortNum].husbpd->SR & UCPD_SR_TYPEC_VSTATE_CC2) == LL_UCPD_SNK_CC2_VRP30A) + { + return USBPD_TRUE; + } + break; + default: + break; + } + + return USBPD_FALSE; +} + +/** + * @brief Signal a Fast Role Swap + * @param PortNum Port + * @retval None + */ +void USBPD_HW_IF_FastRoleSwapSignalling(uint8_t PortNum) +{ + LL_UCPD_SignalFRSTX(Ports[PortNum].husbpd); +} diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c new file mode 100644 index 0000000..5f13fc5 --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_pwr_hw_if.c @@ -0,0 +1,106 @@ +/** + ****************************************************************************** + * @file usbpd_pwr_hw_if.c + * @author MCD Application Team + * @brief This file contains power hardware interface functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_hw_if.h" + + +#define _USBPD_POWER_DEBUG +#if defined(_TRACE) +#include "usbpd_core.h" +#include "usbpd_trace.h" +#endif /* _TRACE */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(_TRACE) +#define POWER_DEBUG(__MSG__,__SIZE__) USBPD_TRACE_Add(USBPD_TRACE_DEBUG, PortNum, 0,__MSG__,__SIZE__); +#else +#define POWER_DEBUG(__MSG__,__SIZE__) +#endif /* _TRACE */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +USBPD_StatusTypeDef HW_IF_PWR_SetVoltage(uint8_t PortNum, uint16_t voltage) +{ + UNUSED(PortNum); + UNUSED(voltage); + return USBPD_OK; +} + +uint16_t HW_IF_PWR_GetVoltage(uint8_t PortNum) +{ + uint32_t _voltage; + BSP_USBPD_PWR_VBUSGetVoltage(PortNum, &_voltage); + return (uint16_t)_voltage; +} + +int16_t HW_IF_PWR_GetCurrent(uint8_t PortNum) +{ + int32_t _current; + BSP_USBPD_PWR_VBUSGetCurrent(PortNum, &_current); + return (int16_t)_current; +} + +#if defined(_SRC) || defined(_DRP) +USBPD_StatusTypeDef HW_IF_PWR_Enable(uint8_t PortNum, USBPD_FunctionalState state, CCxPin_TypeDef Cc, + uint32_t VconnState, USBPD_PortPowerRole_TypeDef role) +{ + UNUSED(role); + int32_t status; + if (USBPD_ENABLE == state) + { +#if defined(_VCONN_SUPPORT) + if (USBPD_TRUE == VconnState) + { + POWER_DEBUG((uint8_t *)"VCONN ON", 8); + (void)BSP_USBPD_PWR_VCONNOn(PortNum, Cc); + } +#endif /* _VCONN_SUPPORT */ + POWER_DEBUG((uint8_t *)"VBUS ON", 7); + status = BSP_USBPD_PWR_VBUSOn(PortNum); + } + else + { +#if defined(_VCONN_SUPPORT) + if (VconnState == USBPD_TRUE) + { + POWER_DEBUG((uint8_t *)"VCONN OFF", 9); + (void)BSP_USBPD_PWR_VCONNOff(PortNum, Cc); + } +#endif /* _VCONN_SUPPORT */ + POWER_DEBUG((uint8_t *)"VBUS OFF", 8); + status = BSP_USBPD_PWR_VBUSOff(PortNum); + } + return (status == BSP_ERROR_NONE) ? USBPD_OK : USBPD_FAIL; +} +#endif /* _SRC || _DRP */ + +USBPD_FunctionalState HW_IF_PWR_VBUSIsEnabled(uint8_t PortNum) +{ +#if defined(_SRC)||defined(_DRP) + uint8_t _state; + BSP_USBPD_PWR_VBUSIsOn(PortNum, &_state); + return (_state == BSP_ERROR_NONE) ? USBPD_DISABLE : USBPD_ENABLE; +#else + return USBPD_DISABLE; +#endif /* _SRC || _DRP */ +} + diff --git a/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c new file mode 100644 index 0000000..70ce6fd --- /dev/null +++ b/Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/src/usbpd_timersserver.c @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file usbpd_timersserver.c + * @author MCD Application Team + * @brief This file contains timer server functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_devices_conf.h" +#include "usbpd_timersserver.h" + +/** @addtogroup STM32_USBPD_LIBRARY + * @{ + */ + +/** @addtogroup USBPD_DEVICE + * @{ + */ + +/** @addtogroup USBPD_DEVICE_TIMESERVER + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +int8_t timer_initcounter = 0; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Initialize a timer to manage timing in us + * @retval None + */ +void USBPD_TIM_Init(void) +{ + if (0 == timer_initcounter) + { + TIMX_CLK_ENABLE; + /***************************/ + /* Time base configuration */ + /***************************/ + /* Counter mode: select up-counting mode */ + LL_TIM_SetCounterMode(TIMX, LL_TIM_COUNTERMODE_UP); + +#if defined(TIMX_CLK_FREQ) + /* Set the pre-scaler value to have TIMx counter clock equal to 1 MHz */ + LL_TIM_SetPrescaler(TIMX, __LL_TIM_CALC_PSC(TIMX_CLK_FREQ, 1000000u)); + + /* Set the auto-reload value to have a counter frequency of 100Hz */ + LL_TIM_SetAutoReload(TIMX, __LL_TIM_CALC_ARR(TIMX_CLK_FREQ, LL_TIM_GetPrescaler(TIMX), 100u)); +#else + /* Set the pre-scaler value to have TIMx counter clock equal to 1 MHz */ + LL_TIM_SetPrescaler(TIMX, __LL_TIM_CALC_PSC(SystemCoreClock, 1000000u)); + + /* Set the auto-reload value to have a counter frequency of 100Hz */ + LL_TIM_SetAutoReload(TIMX, __LL_TIM_CALC_ARR(SystemCoreClock, LL_TIM_GetPrescaler(TIMX), 100u)); +#endif /* TIMX_CLK_FREQ */ + + /*********************************/ + /* Output waveform configuration */ + /*********************************/ + /* Set output compare mode: TOGGLE */ + LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH1, LL_TIM_OCMODE_TOGGLE); + LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH2, LL_TIM_OCMODE_TOGGLE); + LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH3, LL_TIM_OCMODE_TOGGLE); + LL_TIM_OC_SetMode(TIMX, TIMX_CHANNEL_CH4, LL_TIM_OCMODE_TOGGLE); + + /* Set output channel polarity: OC is active high */ + LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH1, LL_TIM_OCPOLARITY_HIGH); + LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH2, LL_TIM_OCPOLARITY_HIGH); + LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH3, LL_TIM_OCPOLARITY_HIGH); + LL_TIM_OC_SetPolarity(TIMX, TIMX_CHANNEL_CH4, LL_TIM_OCPOLARITY_HIGH); + + /* Enable counter */ + LL_TIM_EnableCounter(TIMX); + } + + /* Enable the timer counter */ + timer_initcounter++; +} + +/** + * @brief UnInitialize a timer to manage timing in us + * @retval None + */ +void USBPD_TIM_DeInit(void) +{ + timer_initcounter--; + if (0 == timer_initcounter) + { + TIMX_CLK_DISABLE; + } +} + +/** + * @brief start the timer counting + * @param timer id @TIM_identifier + * @param time in us + * @retval None + */ +void USBPD_TIM_Start(TIM_identifier Id, uint32_t TimeUs) +{ + /* Positionne l'evenement pour sa detection */ + switch (Id) + { + case TIM_PORT0_CRC: + TIMX_CHANNEL1_SETEVENT; + break; + case TIM_PORT0_RETRY: + TIMX_CHANNEL2_SETEVENT; + break; + case TIM_PORT1_CRC: + TIMX_CHANNEL3_SETEVENT; + break; + case TIM_PORT1_RETRY: + TIMX_CHANNEL4_SETEVENT; + break; + default: + break; + } +} + +/** + * @brief check timer expiration + * @param timer id @TIM_identifier + * @retval None + */ +uint32_t USBPD_TIM_IsExpired(TIM_identifier Id) +{ + uint32_t _expired = 1u; + switch (Id) + { + case TIM_PORT0_CRC: + _expired = TIMX_CHANNEL1_GETFLAG(TIMX); + break; + case TIM_PORT0_RETRY: + _expired = TIMX_CHANNEL2_GETFLAG(TIMX); + break; + case TIM_PORT1_CRC: + _expired = TIMX_CHANNEL3_GETFLAG(TIMX); + break; + case TIM_PORT1_RETRY: + _expired = TIMX_CHANNEL4_GETFLAG(TIMX); + break; + default: + break; + } + return _expired; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/USBPD/App/usbpd.c b/USBPD/App/usbpd.c new file mode 100644 index 0000000..469f430 --- /dev/null +++ b/USBPD/App/usbpd.c @@ -0,0 +1,79 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app/usbpd.c + * @author MCD Application Team + * @brief This file contains the device define. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd.h" + +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* USER CODE BEGIN 1 */ +/* USER CODE END 1 */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private functions ---------------------------------------------------------*/ + +/* USER CODE BEGIN 2 */ +/* USER CODE END 2 */ +/* USBPD init function */ +void MX_USBPD_Init(void) +{ + + /* Global Init of USBPD HW */ + USBPD_HW_IF_GlobalHwInit(); + + /* Initialize the Device Policy Manager */ + if (USBPD_OK != USBPD_DPM_InitCore()) + { + while(1); + } + + /* Initialise the DPM application */ + if (USBPD_OK != USBPD_DPM_UserInit()) + { + while(1); + } + + /* USER CODE BEGIN 3 */ + /* USER CODE END 3 */ + + if (USBPD_OK != USBPD_DPM_InitOS()) + { + while(1); + } + + /* USER CODE BEGIN EnableIRQ */ + /* Enable IRQ which has been disabled by FreeRTOS services */ + __enable_irq(); + /* USER CODE END EnableIRQ */ + +} + +/* USER CODE BEGIN 4 */ +/* USER CODE END 4 */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/USBPD/App/usbpd.h b/USBPD/App/usbpd.h new file mode 100644 index 0000000..9052fdd --- /dev/null +++ b/USBPD/App/usbpd.h @@ -0,0 +1,59 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app/usbpd.h + * @author MCD Application Team + * @brief This file contains the device define. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __usbpd_H +#define __usbpd_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_core.h" +#include "usbpd_dpm_core.h" +#include "usbpd_dpm_conf.h" +#include "usbpd_hw_if.h" + +/* USER CODE BEGIN 0 */ +/* USER CODE END 0 */ + +/* Global variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ +/* USER CODE END 1 */ + +/* USBPD init function */ +void MX_USBPD_Init(void); + +/* USER CODE BEGIN 2 */ +/* USER CODE END 2 */ + +#ifdef __cplusplus +} +#endif +#endif /*__usbpd_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/USBPD/usbpd_devices_conf.h b/USBPD/usbpd_devices_conf.h new file mode 100644 index 0000000..a33b4e3 --- /dev/null +++ b/USBPD/usbpd_devices_conf.h @@ -0,0 +1,125 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_devices_conf.h + * @author MCD Application Team + * @brief This file contains the device define. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* CubeMX Generated */ +#define CUBEMX_GENERATED + +#ifndef USBPD_DEVICE_CONF_H +#define USBPD_DEVICE_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_ll_bus.h" +#include "stm32g4xx_ll_dma.h" +#include "stm32g4xx_ll_gpio.h" +#include "stm32g4xx_ll_rcc.h" +#include "stm32g4xx_ll_ucpd.h" +#include "stm32g4xx_ll_pwr.h" +#include "stm32g4xx_ll_tim.h" +#include "usbpd_pwr_user.h" +#include "usbpd_pwr_if.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ----------------------------------------------------------------------------- + usbpd_hw.c +-------------------------------------------------------------------------------*/ + +/* defined used to configure function : BSP_USBPD_GetUSPDInstance */ +#define UCPD_INSTANCE0 UCPD1 + +/* defined used to configure function : BSP_USBPD_Init_DMARxInstance,BSP_USBPD_DeInit_DMARxInstance */ +#define UCPDDMA_INSTANCE0_CLOCKENABLE_RX LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) + +#define UCPDDMA_INSTANCE0_DMA_RX DMA1 + +#define UCPDDMA_INSTANCE0_REQUEST_RX DMA_REQUEST_UCPD1_RX + +#define UCPDDMA_INSTANCE0_LL_CHANNEL_RX LL_DMA_CHANNEL_1 + +#define UCPDDMA_INSTANCE0_CHANNEL_RX DMA1_Channel1 + +/* defined used to configure function : BSP_USBPD_Init_DMATxInstance, BSP_USBPD_DeInit_DMATxInstance */ +#define UCPDDMA_INSTANCE0_CLOCKENABLE_TX LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1) + +#define UCPDDMA_INSTANCE0_DMA_TX DMA1 + +#define UCPDDMA_INSTANCE0_REQUEST_TX DMA_REQUEST_UCPD1_TX + +#define UCPDDMA_INSTANCE0_LL_CHANNEL_TX LL_DMA_CHANNEL_2 + +#define UCPDDMA_INSTANCE0_CHANNEL_TX DMA1_Channel2 +/* defined used to configure BSP_USBPD_SetFRSSignalling */ +#define UCPDFRS_INSTANCE0_FRSCC1 +#define UCPDFRS_INSTANCE0_FRSCC2 + +#define UCPD_INSTANCE0_ENABLEIRQ do{ \ + NVIC_SetPriority(UCPD1_IRQn,4); \ + NVIC_EnableIRQ(UCPD1_IRQn); \ + } while(0) + +/* ----------------------------------------------------------------------------- + Definitions for timer service feature +-------------------------------------------------------------------------------*/ + +#define TIMX TIM1 +#define TIMX_CLK_ENABLE LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) +#define TIMX_CLK_DISABLE LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) +#define TIMX_CHANNEL_CH1 LL_TIM_CHANNEL_CH1 +#define TIMX_CHANNEL_CH2 LL_TIM_CHANNEL_CH2 +#define TIMX_CHANNEL_CH3 LL_TIM_CHANNEL_CH3 +#define TIMX_CHANNEL_CH4 LL_TIM_CHANNEL_CH4 +#define TIMX_CHANNEL1_SETEVENT do{ \ + LL_TIM_OC_SetCompareCH1(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ + LL_TIM_ClearFlag_CC1(TIMX); \ + }while(0) +#define TIMX_CHANNEL2_SETEVENT do{ \ + LL_TIM_OC_SetCompareCH2(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ + LL_TIM_ClearFlag_CC2(TIMX); \ + }while(0) +#define TIMX_CHANNEL3_SETEVENT do{ \ + LL_TIM_OC_SetCompareCH3(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ + LL_TIM_ClearFlag_CC3(TIMX); \ + }while(0) +#define TIMX_CHANNEL4_SETEVENT do{ \ + LL_TIM_OC_SetCompareCH4(TIMX, (TimeUs + TIMX->CNT) % TIM_MAX_TIME);\ + LL_TIM_ClearFlag_CC4(TIMX); \ + }while(0) +#define TIMX_CHANNEL1_GETFLAG LL_TIM_IsActiveFlag_CC1 +#define TIMX_CHANNEL2_GETFLAG LL_TIM_IsActiveFlag_CC2 +#define TIMX_CHANNEL3_GETFLAG LL_TIM_IsActiveFlag_CC3 +#define TIMX_CHANNEL4_GETFLAG LL_TIM_IsActiveFlag_CC4 + +#ifdef __cplusplus + } +#endif + +#endif /* USBPD_DEVICE_CONF_H */ + diff --git a/USBPD/usbpd_dpm_conf.h b/USBPD/usbpd_dpm_conf.h new file mode 100644 index 0000000..60250cf --- /dev/null +++ b/USBPD/usbpd_dpm_conf.h @@ -0,0 +1,150 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_dpm_conf.h + * @author MCD Application Team + * @brief Header file for stack/application settings file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __USBPD_DPM_CONF_H_ +#define __USBPD_DPM_CONF_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_pdo_defs.h" +#include "usbpd_dpm_user.h" +#include "usbpd_vdm_user.h" + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ + +/* USER CODE END Includes */ + +/* Define ------------------------------------------------------------------*/ +/* Define VID, PID,... manufacturer parameters */ +#define USBPD_VID (0x0483u) /*!< Vendor ID (assigned by the USB-IF) */ +#define USBPD_PID (0x0002u) /*!< Product ID (assigned by the manufacturer) */ +#define USBPD_XID (0xF0000003u) /*!< Value provided by the USB-IF assigned to the product */ + +/* USER CODE BEGIN Define */ +/* Section where Define can be added */ + +/* USER CODE END Define */ + +/* Exported typedef ----------------------------------------------------------*/ +/* USER CODE BEGIN Typedef */ +/* Section where Typedef can be added */ + +/* USER CODE END Typedef */ + +/* Private variables ---------------------------------------------------------*/ +#ifndef __USBPD_DPM_CORE_C +extern USBPD_SettingsTypeDef DPM_Settings[USBPD_PORT_COUNT]; +extern USBPD_IdSettingsTypeDef DPM_ID_Settings[USBPD_PORT_COUNT]; +extern USBPD_USER_SettingsTypeDef DPM_USER_Settings[USBPD_PORT_COUNT]; +#else /* __USBPD_DPM_CORE_C */ +USBPD_SettingsTypeDef DPM_Settings[USBPD_PORT_COUNT] = +{ + { + .PE_SupportedSOP = USBPD_SUPPORTED_SOP_SOP , /* Supported SOP : SOP, SOP' SOP" SOP'Debug SOP"Debug */ + .PE_SpecRevision = USBPD_SPECIFICATION_REV3,/* spec revision value */ + .PE_DefaultRole = USBPD_PORTPOWERROLE_SRC, /* Default port role */ + .PE_RoleSwap = USBPD_FALSE, /* support port role swap */ + .PE_VDMSupport = USBPD_FALSE, + .PE_RespondsToDiscovSOP = USBPD_FALSE, /*!< Can respond successfully to a Discover Identity */ + .PE_AttemptsDiscovSOP = USBPD_FALSE, /*!< Can send a Discover Identity */ + .PE_PingSupport = USBPD_FALSE, /* support Ping (only for PD3.0) */ + .PE_CapscounterSupport = USBPD_FALSE, /* support caps counter */ + .CAD_RoleToggle = USBPD_FALSE, /* CAD role toggle */ + .CAD_DefaultResistor = 0x00u, + .CAD_TryFeature = 0, /* CAD try feature */ + .CAD_AccesorySupport = USBPD_FALSE, /* CAD accessory support */ + .PE_PD3_Support.d = /*!< PD3 SUPPORT FEATURE */ + { + .PE_UnchunkSupport = USBPD_FALSE, /* support Unchunked mode (valid only spec revision 3.0) */ + .PE_FastRoleSwapSupport = USBPD_FALSE, /* support fast role swap only spec revision 3.0 */ + .Is_GetPPSStatus_Supported = USBPD_FALSE, /*!< PPS message NOT supported by PE stack */ + .Is_SrcCapaExt_Supported = USBPD_FALSE, /*!< Source_Capabilities_Extended message supported or not by DPM */ + .Is_Alert_Supported = USBPD_FALSE, /*!< Alert message supported or not by DPM */ + .Is_GetStatus_Supported = USBPD_FALSE, /*!< Status message supported or not by DPM (Is_Alert_Supported should be enabled) */ + .Is_GetManufacturerInfo_Supported = USBPD_FALSE, /*!< Manufacturer_Info message supported or not by DPM */ + .Is_GetCountryCodes_Supported = USBPD_FALSE, /*!< Country_Codes message supported or not by DPM */ + .Is_GetCountryInfo_Supported = USBPD_FALSE, /*!< Country_Info message supported or not by DPM */ + .Is_SecurityRequest_Supported = USBPD_FALSE, /*!< Security_Response message supported or not by DPM */ + .Is_FirmUpdateRequest_Supported = USBPD_FALSE, /*!< Firmware update response message supported by PE */ + .Is_GetBattery_Supported = USBPD_FALSE, /*!< Get Battery Capabitity and Status messages supported by PE */ + }, + + .CAD_SRCToggleTime = 0, /* uint8_t CAD_SRCToggleTime; */ + .CAD_SNKToggleTime = 0, /* uint8_t CAD_SNKToggleTime; */ + } +}; + +USBPD_IdSettingsTypeDef DPM_ID_Settings[USBPD_PORT_COUNT] = +{ + { + .XID = USBPD_XID, /*!< Value provided by the USB-IF assigned to the product */ + .VID = USBPD_VID, /*!< Vendor ID (assigned by the USB-IF) */ + .PID = USBPD_PID, /*!< Product ID (assigned by the manufacturer) */ + }, +}; + +USBPD_USER_SettingsTypeDef DPM_USER_Settings[USBPD_PORT_COUNT] = +{ + { + .PE_DataSwap = USBPD_FALSE, /* support data swap */ + .PE_VconnSwap = USBPD_FALSE, /* support VCONN swap */ + .PE_DR_Swap_To_DFP = USBPD_TRUE, /* Support of DR Swap to DFP */ + .PE_DR_Swap_To_UFP = USBPD_TRUE, /* Support of DR Swap to UFP */ +#if defined(USBPD_REV30_SUPPORT) +#if _MANU_INFO + .DPM_ManuInfoPort = /*!< Manufacturer information used for the port */ + { + .VID = USBPD_VID, /*!< Vendor ID (assigned by the USB-IF) */ + .PID = USBPD_PID, /*!< Product ID (assigned by the manufacturer) */ + .ManuString = "STMicroelectronics", /*!< Vendor defined byte array */ + }, +#endif /* _MANU_INFO */ +#endif /* USBPD_REV30_SUPPORT */ + }, +}; + +#endif /* !__USBPD_DPM_CORE_C */ + +/* USER CODE BEGIN Variable */ +/* Section where Variable can be added */ + +/* USER CODE END Variable */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN Constant */ +/* Section where Constant can be added */ + +/* USER CODE END Constant */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ +/* Section where Macro can be added */ + +/* USER CODE END Macro */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_DPM_CONF_H_ */ diff --git a/USBPD/usbpd_dpm_core.c b/USBPD/usbpd_dpm_core.c new file mode 100644 index 0000000..5af9b47 --- /dev/null +++ b/USBPD/usbpd_dpm_core.c @@ -0,0 +1,463 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_dpm_core.c + * @author MCD Application Team + * @brief USBPD dpm core file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#define __USBPD_DPM_CORE_C + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_core.h" +#include "usbpd_trace.h" +#include "usbpd_dpm_core.h" +#include "usbpd_dpm_conf.h" +#include "usbpd_dpm_user.h" + +#if defined(USE_STM32_UTILITY_OS) +#include "utilities_conf.h" +#endif /* USE_STM32_UTILITY_OS */ + +/* Generic STM32 prototypes */ +extern uint32_t HAL_GetTick(void); + +/* Private function prototypes -----------------------------------------------*/ + /* !FREERTOS */ +void USBPD_CAD_Task(void); +#if defined(USE_STM32_UTILITY_OS) +void TimerCADfunction(void *); +#endif /* USE_STM32_UTILITY_OS */ +void USBPD_PE_Task_P0(void); +void USBPD_PE_Task_P1(void); +#if defined(USE_STM32_UTILITY_OS) +void TimerPE0function(void *pArg); +void TimerPE1function(void *pArg); +#endif /* USE_STM32_UTILITY_OS */ +void USBPD_TaskUser(void); + +/* Private typedef -----------------------------------------------------------*/ + /* !_RTOS */ +#if defined(USE_STM32_UTILITY_OS) +UTIL_TIMER_Object_t TimerCAD; +UTIL_TIMER_Object_t TimerPE0, TimerPE1; +#endif /* USE_STM32_UTILITY_OS */ + +/* Private define ------------------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +#define CHECK_PE_FUNCTION_CALL(_function_) _retr = _function_; \ + if(USBPD_OK != _retr) {return _retr;} +#define CHECK_CAD_FUNCTION_CALL(_function_) if(USBPD_CAD_OK != _function_) {return USBPD_ERROR;} + +#if defined(_DEBUG_TRACE) +#define DPM_CORE_DEBUG_TRACE(_PORTNUM_, __MESSAGE__) USBPD_TRACE_Add(USBPD_TRACE_DEBUG, _PORTNUM_, 0u, (uint8_t *)(__MESSAGE__), sizeof(__MESSAGE__) - 1u); +#else +#define DPM_CORE_DEBUG_TRACE(_PORTNUM_, __MESSAGE__) +#endif /* _DEBUG_TRACE */ + +/* Private variables ---------------------------------------------------------*/ +#if !defined(USE_STM32_UTILITY_OS) +#define OFFSET_CAD 1U +static uint32_t DPM_Sleep_time[USBPD_PORT_COUNT + OFFSET_CAD]; +static uint32_t DPM_Sleep_start[USBPD_PORT_COUNT + OFFSET_CAD]; +#endif /* !USE_STM32_UTILITY_OS */ + +USBPD_ParamsTypeDef DPM_Params[USBPD_PORT_COUNT]; + +/* Private function prototypes -----------------------------------------------*/ +static void USBPD_PE_TaskWakeUp(uint8_t PortNum); +static void DPM_ManageAttachedState(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc); +void USBPD_DPM_CADCallback(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc); +static void USBPD_DPM_CADTaskWakeUp(void); + +/** + * @brief Initialize the core stack (port power role, PWR_IF, CAD and PE Init procedures) + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_DPM_InitCore(void) +{ + /* variable to get dynamique memory allocated by usbpd stack */ + uint32_t stack_dynamemsize; + USBPD_StatusTypeDef _retr = USBPD_OK; + + static const USBPD_PE_Callbacks dpmCallbacks = + { + USBPD_DPM_SetupNewPower, + USBPD_DPM_HardReset, + NULL, + USBPD_DPM_Notification, + USBPD_DPM_ExtendedMessageReceived, + USBPD_DPM_GetDataInfo, + USBPD_DPM_SetDataInfo, + USBPD_DPM_EvaluateRequest, + NULL, + NULL, + USBPD_PE_TaskWakeUp, +#if defined(_VCONN_SUPPORT) + USBPD_DPM_EvaluateVconnSwap, + USBPD_DPM_PE_VconnPwr, +#else + NULL, + NULL, +#endif /* _VCONN_SUPPORT */ + USBPD_DPM_EnterErrorRecovery, + USBPD_DPM_EvaluateDataRoleSwap, + USBPD_DPM_IsPowerReady + }; + + static const USBPD_CAD_Callbacks CAD_cbs = + { + USBPD_DPM_CADCallback, + USBPD_DPM_CADTaskWakeUp + }; + + /* Check the lib selected */ + if (USBPD_TRUE != USBPD_PE_CheckLIB(_LIB_ID)) + { + return USBPD_ERROR; + } + + /* to get how much memory are dynamically allocated by the stack + the memory return is corresponding to 2 ports so if the application + managed only one port divide the value return by 2 */ + stack_dynamemsize = USBPD_PE_GetMemoryConsumption(); + + /* done to avoid warning */ + (void)stack_dynamemsize; + + for (uint8_t _port_index = 0; _port_index < USBPD_PORT_COUNT; ++_port_index) + { + /* Variable to be sure that DPM is correctly initialized */ + DPM_Params[_port_index].DPM_Initialized = USBPD_FALSE; + + /* check the stack settings */ + DPM_Params[_port_index].PE_SpecRevision = DPM_Settings[_port_index].PE_SpecRevision; + DPM_Params[_port_index].PE_PowerRole = DPM_Settings[_port_index].PE_DefaultRole; + DPM_Params[_port_index].PE_SwapOngoing = USBPD_FALSE; + DPM_Params[_port_index].ActiveCCIs = CCNONE; + DPM_Params[_port_index].VconnCCIs = CCNONE; + DPM_Params[_port_index].VconnStatus = USBPD_FALSE; + + /* CAD SET UP : Port 0 */ + CHECK_CAD_FUNCTION_CALL(USBPD_CAD_Init(_port_index, (USBPD_CAD_Callbacks *)&CAD_cbs, + (USBPD_SettingsTypeDef *)&DPM_Settings[_port_index], &DPM_Params[_port_index])); + + /* PE SET UP : Port 0 */ + CHECK_PE_FUNCTION_CALL(USBPD_PE_Init(_port_index, (USBPD_SettingsTypeDef *)&DPM_Settings[_port_index], + &DPM_Params[_port_index], &dpmCallbacks)); + + /* DPM is correctly initialized */ + DPM_Params[_port_index].DPM_Initialized = USBPD_TRUE; + + /* Enable CAD on Port 0 */ + USBPD_CAD_PortEnable(_port_index, USBPD_CAD_ENABLE); + } + +#if defined(USE_STM32_UTILITY_OS) + /* initialise timer server */ + UTIL_TIMER_Init(); + + /* initialize the sequencer */ + UTIL_SEQ_Init(); +#endif /* USE_STM32_UTILITY_OS */ + + return _retr; +} + +/** + * @brief Initialize the OS parts (task, queue,... ) + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_DPM_InitOS(void) +{ + + return USBPD_OK; +} + +/** + * @brief Initialize the OS parts (port power role, PWR_IF, CAD and PE Init procedures) + * @retval None + */ +#if defined(USE_STM32_UTILITY_OS) +/** + * @brief Task for CAD processing + * @retval None + */ +void USBPD_CAD_Task(void) +{ + UTIL_TIMER_Stop(&TimerCAD); + uint32_t _timing = USBPD_CAD_Process(); + UTIL_TIMER_SetPeriod(&TimerCAD, _timing); + UTIL_TIMER_Start(&TimerCAD); +} + +/** + * @brief timer function to wakeup CAD Task + * @param pArg Pointer on an argument + * @retval None + */ +void TimerCADfunction(void *pArg) +{ + UTIL_SEQ_SetTask(TASK_CAD, 0); +} + +#if !defined(USBPDCORE_LIB_NO_PD) +/** + * @brief timer function to wakeup PE_0 Task + * @param pArg Pointer on an argument + * @retval None + */ +void TimerPE0function(void *pArg) +{ + UTIL_SEQ_SetTask(TASK_PE_0, 0); +} + +/** + * @brief timer function to wakeup PE_1 Task + * @param pArg Pointer on an argument + * @retval None + */ +void TimerPE1function(void *pArg) +{ + UTIL_SEQ_SetTask(TASK_PE_1, 0); +} + +/** + * @brief Task for PE_0 processing + * @retval None + */ +void USBPD_PE_Task_P0(void) +{ + UTIL_TIMER_Stop(&TimerPE0); + uint32_t _timing = + USBPD_PE_StateMachine_SRC(USBPD_PORT_0); + if (_timing != 0xFFFFFFFF) + { + UTIL_TIMER_SetPeriod(&TimerPE0, _timing); + UTIL_TIMER_Start(&TimerPE0); + } +} + +/** + * @brief Task for PE_1 processing + * @retval None + */ +void USBPD_PE_Task_P1(void) +{ + UTIL_TIMER_Stop(&TimerPE1); + uint32_t _timing = + USBPD_PE_StateMachine_SRC(USBPD_PORT_1); + if (_timing != 0xFFFFFFFF) + { + UTIL_TIMER_SetPeriod(&TimerPE1, _timing); + UTIL_TIMER_Start(&TimerPE1); + } +} +#endif /* !USBPDCORE_LIB_NO_PD */ + +/** + * @brief Task for DPM_USER processing + * @retval None + */ +void USBPD_TaskUser(void) +{ + USBPD_DPM_UserExecute(NULL); +} +#endif /* USE_STM32_UTILITY_OS */ + +void USBPD_DPM_Run(void) +{ +#if defined(USE_STM32_UTILITY_OS) + UTIL_SEQ_RegTask(TASK_CAD, 0, USBPD_CAD_Task); + UTIL_SEQ_SetTask(TASK_CAD, 0); + UTIL_TIMER_Create(&TimerCAD, 10, UTIL_TIMER_ONESHOT, TimerCADfunction, NULL); + + UTIL_SEQ_RegTask(TASK_PE_0, 0, USBPD_PE_Task_P0); + UTIL_SEQ_PauseTask(TASK_PE_0); + UTIL_TIMER_Create(&TimerPE0, 10, UTIL_TIMER_ONESHOT, TimerPE0function, NULL); +#if USBPD_PORT_COUNT == 2 + UTIL_SEQ_RegTask(TASK_PE_1, 0, USBPD_PE_Task_P1); + UTIL_SEQ_PauseTask(TASK_PE_1); + UTIL_TIMER_Create(&TimerPE1, 10, UTIL_TIMER_ONESHOT, TimerPE1function, NULL); +#endif /* USBPD_PORT_COUNT == 2 */ + /* !USBPDCORE_LIB_NO_PD */ + + UTIL_SEQ_RegTask(TASK_USER, 0, USBPD_TaskUser); + UTIL_SEQ_SetTask(TASK_USER, 0); + + do + { + UTIL_SEQ_Run(~0); + } while (1u == 1u); +#else /* !USE_STM32_UTILITY_OS */ + do + { + + if ((HAL_GetTick() - DPM_Sleep_start[USBPD_PORT_COUNT]) >= DPM_Sleep_time[USBPD_PORT_COUNT]) + { + DPM_Sleep_time[USBPD_PORT_COUNT] = USBPD_CAD_Process(); + DPM_Sleep_start[USBPD_PORT_COUNT] = HAL_GetTick(); + } + + uint32_t port = 0; + + for (port = 0; port < USBPD_PORT_COUNT; port++) + { + if ((HAL_GetTick() - DPM_Sleep_start[port]) >= DPM_Sleep_time[port]) + { + DPM_Sleep_time[port] = + USBPD_PE_StateMachine_SRC(port); + DPM_Sleep_start[port] = HAL_GetTick(); + } + } + + USBPD_DPM_UserExecute(NULL); + + } while (1u == 1u); +#endif /* USE_STM32_UTILITY_OS */ +} + +/** + * @brief Initialize DPM (port power role, PWR_IF, CAD and PE Init procedures) + * @retval USBPD status + */ +void USBPD_DPM_TimerCounter(void) +{ + /* Call PE/PRL timers functions only if DPM is initialized */ + if (USBPD_TRUE == DPM_Params[USBPD_PORT_0].DPM_Initialized) + { + USBPD_DPM_UserTimerCounter(USBPD_PORT_0); + USBPD_PE_TimerCounter(USBPD_PORT_0); + USBPD_PRL_TimerCounter(USBPD_PORT_0); + } +#if USBPD_PORT_COUNT==2 + if (USBPD_TRUE == DPM_Params[USBPD_PORT_1].DPM_Initialized) + { + USBPD_DPM_UserTimerCounter(USBPD_PORT_1); + USBPD_PE_TimerCounter(USBPD_PORT_1); + USBPD_PRL_TimerCounter(USBPD_PORT_1); + } +#endif /* USBPD_PORT_COUNT == 2 */ + +} + +/** + * @brief WakeUp PE task + * @param PortNum port number + * @retval None + */ +static void USBPD_PE_TaskWakeUp(uint8_t PortNum) +{ +#if defined(USE_STM32_UTILITY_OS) + UTIL_SEQ_SetTask(PortNum == 0 ? TASK_PE_0 : TASK_PE_1, 0); +#else + DPM_Sleep_time[PortNum] = 0; +#endif /* USE_STM32_UTILITY_OS */ +} + +/** + * @brief WakeUp CAD task + * @retval None + */ +static void USBPD_DPM_CADTaskWakeUp(void) +{ +#if defined(USE_STM32_UTILITY_OS) + UTIL_SEQ_SetTask(TASK_CAD, 0); +#else + DPM_Sleep_time[USBPD_PORT_COUNT] = 0; +#endif /* USE_STM32_UTILITY_OS */ +} + +/** + * @brief CallBack reporting events on a specified port from CAD layer. + * @param PortNum The handle of the port + * @param State CAD state + * @param Cc The Communication Channel for the USBPD communication + * @retval None + */ +void USBPD_DPM_CADCallback(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc) +{ + + switch (State) + { + case USBPD_CAD_EVENT_ATTEMC : + { +#ifdef _VCONN_SUPPORT + DPM_Params[PortNum].VconnStatus = USBPD_TRUE; +#endif /* _VCONN_SUPPORT */ + DPM_ManageAttachedState(PortNum, State, Cc); +#ifdef _VCONN_SUPPORT + DPM_CORE_DEBUG_TRACE(PortNum, "Note: VconnStatus=TRUE"); +#endif /* _VCONN_SUPPORT */ + break; + } + case USBPD_CAD_EVENT_ATTACHED : + DPM_ManageAttachedState(PortNum, State, Cc); + break; + case USBPD_CAD_EVENT_DETACHED : + case USBPD_CAD_EVENT_EMC : + { + /* The ufp is detached */ + (void)USBPD_PE_IsCableConnected(PortNum, 0); + /* Terminate PE task */ +#if defined(USE_STM32_UTILITY_OS) + UTIL_SEQ_PauseTask(PortNum == 0 ? TASK_PE_0 : TASK_PE_1); +#else + DPM_Sleep_time[PortNum] = 0xFFFFFFFFU; +#endif /* USE_STM32_UTILITY_OS */ + DPM_Params[PortNum].PE_SwapOngoing = USBPD_FALSE; + DPM_Params[PortNum].ActiveCCIs = CCNONE; + DPM_Params[PortNum].PE_Power = USBPD_POWER_NO; + USBPD_DPM_UserCableDetection(PortNum, State); +#ifdef _VCONN_SUPPORT + DPM_Params[PortNum].VconnCCIs = CCNONE; + DPM_Params[PortNum].VconnStatus = USBPD_FALSE; + DPM_CORE_DEBUG_TRACE(PortNum, "Note: VconnStatus=FALSE"); +#endif /* _VCONN_SUPPORT */ + break; + } + default : + /* nothing to do */ + break; + } +} + +static void DPM_ManageAttachedState(uint8_t PortNum, USBPD_CAD_EVENT State, CCxPin_TypeDef Cc) +{ +#ifdef _VCONN_SUPPORT + if (CC1 == Cc) + { + DPM_Params[PortNum].VconnCCIs = CC2; + } + if (CC2 == Cc) + { + DPM_Params[PortNum].VconnCCIs = CC1; + } +#endif /* _VCONN_SUPPORT */ + DPM_Params[PortNum].ActiveCCIs = Cc; + (void)USBPD_PE_IsCableConnected(PortNum, 1); + + USBPD_DPM_UserCableDetection(PortNum, State); + +#if defined(USE_STM32_UTILITY_OS) + /* Resume the task */ + UTIL_SEQ_ResumeTask(PortNum == 0 ? TASK_PE_0 : TASK_PE_1); + /* Enable task execution */ + UTIL_SEQ_SetTask(PortNum == 0 ? TASK_PE_0 : TASK_PE_1, 0); +#else + DPM_Sleep_time[PortNum] = 0U; +#endif /* USE_STM32_UTILITY_OS */ +} diff --git a/USBPD/usbpd_dpm_core.h b/USBPD/usbpd_dpm_core.h new file mode 100644 index 0000000..ecce9f2 --- /dev/null +++ b/USBPD/usbpd_dpm_core.h @@ -0,0 +1,74 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_dpm_core.h + * @author MCD Application Team + * @brief Header file for usbpd_dpm_core.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __USBPD_DPM_CORE_H_ +#define __USBPD_DPM_CORE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported typedef ----------------------------------------------------------*/ +/* USER CODE BEGIN typedef */ + +/* USER CODE END typedef */ + +/* Exported define -----------------------------------------------------------*/ + +/* USER CODE BEGIN define */ + +/* USER CODE END define */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN constants */ + +/* USER CODE END constants */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN macro */ + +/* USER CODE END macro */ + +/* Exported variables --------------------------------------------------------*/ +extern USBPD_ParamsTypeDef DPM_Params[USBPD_PORT_COUNT]; +/* USER CODE BEGIN variables */ + +/* USER CODE END variables */ + +/* Exported functions --------------------------------------------------------*/ +USBPD_StatusTypeDef USBPD_DPM_InitCore(void); +USBPD_StatusTypeDef USBPD_DPM_InitOS(void); +void USBPD_DPM_Run(void); +void USBPD_DPM_TimerCounter(void); +__WEAK void USBPD_DPM_ErrorHandler(void); +/* USER CODE BEGIN functions */ + +/* USER CODE END functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_DPM_CORE_H_ */ diff --git a/USBPD/usbpd_dpm_user.c b/USBPD/usbpd_dpm_user.c new file mode 100644 index 0000000..c639806 --- /dev/null +++ b/USBPD/usbpd_dpm_user.c @@ -0,0 +1,993 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_dpm_user.c + * @author MCD Application Team + * @brief USBPD DPM user code + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#define USBPD_DPM_USER_C +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "usbpd_core.h" +#include "usbpd_dpm_user.h" +#include "usbpd_pdo_defs.h" +#include "usbpd_dpm_core.h" +#include "usbpd_dpm_conf.h" +#include "usbpd_vdm_user.h" +#include "usbpd_pwr_if.h" +#include "usbpd_pwr_user.h" +#if defined(_TRACE) +#include "usbpd_trace.h" +#include "string.h" +#include "stdio.h" +#endif /* _TRACE */ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/** @addtogroup STM32_USBPD_APPLICATION + * @{ + */ + +/** @addtogroup STM32_USBPD_APPLICATION_DPM_USER + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN Private_Typedef */ + +/* USER CODE END Private_Typedef */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup USBPD_USER_PRIVATE_DEFINES USBPD USER Private Defines + * @{ + */ +/* USER CODE BEGIN Private_Define */ + +/* USER CODE END Private_Define */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup USBPD_USER_PRIVATE_MACROS USBPD USER Private Macros + * @{ + */ +#if defined(_TRACE) +#define DPM_USER_DEBUG_TRACE_SIZE 50u +#define DPM_USER_DEBUG_TRACE(_PORT_, ...) do { \ + char _str[DPM_USER_DEBUG_TRACE_SIZE]; \ + uint8_t _size = snprintf(_str, DPM_USER_DEBUG_TRACE_SIZE, __VA_ARGS__); \ + if (_size < DPM_USER_DEBUG_TRACE_SIZE) \ + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, (uint8_t)(_PORT_), 0, (uint8_t*)_str, strlen(_str)); \ + else \ + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, (uint8_t)(_PORT_), 0, (uint8_t*)_str, DPM_USER_DEBUG_TRACE_SIZE); \ + } while(0) + +#define DPM_USER_ERROR_TRACE(_PORT_, _STATUS_, ...) do { \ + if (USBPD_OK != _STATUS_) { \ + char _str[DPM_USER_DEBUG_TRACE_SIZE]; \ + uint8_t _size = snprintf(_str, DPM_USER_DEBUG_TRACE_SIZE, __VA_ARGS__); \ + if (_size < DPM_USER_DEBUG_TRACE_SIZE) \ + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, (uint8_t)(_PORT_), 0, (uint8_t*)_str, strlen(_str)); \ + else \ + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, (uint8_t)(_PORT_), 0, (uint8_t*)_str, DPM_USER_DEBUG_TRACE_SIZE); \ + } \ + } while(0) +#else +#define DPM_USER_DEBUG_TRACE(_PORT_, ...) +#define DPM_USER_ERROR_TRACE(_PORT_, _STATUS_, ...) +#endif /* _TRACE */ +/* USER CODE BEGIN Private_Macro */ + +/* USER CODE END Private_Macro */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USBPD_USER_PRIVATE_VARIABLES USBPD USER Private Variables + * @{ + */ + +/* USER CODE BEGIN Private_Variables */ + +/* USER CODE END Private_Variables */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USBPD_USER_PRIVATE_FUNCTIONS USBPD USER Private Functions + * @{ + */ +/* USER CODE BEGIN USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ + +/* USER CODE END USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ +/** + * @} + */ + +/* Exported functions ------- ------------------------------------------------*/ +/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS USBPD USER Exported Functions + * @{ + */ +/* USER CODE BEGIN USBPD_USER_EXPORTED_FUNCTIONS */ + +/* USER CODE END USBPD_USER_EXPORTED_FUNCTIONS */ + +/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 USBPD USER Exported Functions called by DPM CORE + * @{ + */ +/* USER CODE BEGIN USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 */ + +/* USER CODE END USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 */ + +/** + * @brief Initialize DPM (port power role, PWR_IF, CAD and PE Init procedures) + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_UserInit(void) +{ +/* USER CODE BEGIN USBPD_DPM_UserInit */ + return USBPD_OK; +/* USER CODE END USBPD_DPM_UserInit */ +} + +/** + * @brief User delay implementation which is OS dependent + * @param Time time in ms + * @retval None + */ +void USBPD_DPM_WaitForTime(uint32_t Time) +{ + HAL_Delay(Time); +} + +/** + * @brief User processing time, it is recommended to avoid blocking task for long time + * @param argument DPM User event + * @retval None + */ +void USBPD_DPM_UserExecute(void const *argument) +{ +/* USER CODE BEGIN USBPD_DPM_UserExecute */ + +/* USER CODE END USBPD_DPM_UserExecute */ +} + +/** + * @brief UserCableDetection reporting events on a specified port from CAD layer. + * @param PortNum The handle of the port + * @param State CAD state + * @retval None + */ +void USBPD_DPM_UserCableDetection(uint8_t PortNum, USBPD_CAD_EVENT State) +{ +/* USER CODE BEGIN USBPD_DPM_UserCableDetection */ +DPM_USER_DEBUG_TRACE(PortNum, "ADVICE: update USBPD_DPM_UserCableDetection"); + switch(State) + { + case USBPD_CAD_EVENT_ATTACHED: + case USBPD_CAD_EVENT_ATTEMC: + { + if (USBPD_OK != USBPD_PWR_IF_VBUSEnable(PortNum)) + { + /* Should not occur */ + HAL_Delay(6000); + NVIC_SystemReset(); + } + break; + } + case USBPD_CAD_EVENT_DETACHED : + case USBPD_CAD_EVENT_EMC : + default : + { + if (USBPD_OK != USBPD_PWR_IF_VBUSDisable(PortNum)) + { + /* Should not occur */ + while(1); + } + break; + } + } +/* USER CODE END USBPD_DPM_UserCableDetection */ +} + +/** + * @brief function used to manage user timer. + * @param PortNum Port number + * @retval None + */ +void USBPD_DPM_UserTimerCounter(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_DPM_UserTimerCounter */ + +/* USER CODE END USBPD_DPM_UserTimerCounter */ +} + +/** + * @} + */ + +/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP2 USBPD USER Exported Callbacks functions called by PE + * @{ + */ + +/** + * @brief Callback function called by PE to inform DPM about PE event. + * @param PortNum The current port number + * @param EventVal @ref USBPD_NotifyEventValue_TypeDef + * @retval None + */ +void USBPD_DPM_Notification(uint8_t PortNum, USBPD_NotifyEventValue_TypeDef EventVal) +{ +/* USER CODE BEGIN USBPD_DPM_Notification */ + /* Manage event notified by the stack? */ + switch(EventVal) + { +// case USBPD_NOTIFY_POWER_EXPLICIT_CONTRACT : +// break; +// case USBPD_NOTIFY_REQUEST_ACCEPTED: +// break; +// case USBPD_NOTIFY_REQUEST_REJECTED: +// case USBPD_NOTIFY_REQUEST_WAIT: +// break; +// case USBPD_NOTIFY_POWER_SWAP_TO_SNK_DONE: +// break; +// case USBPD_NOTIFY_STATE_SNK_READY: +// break; +// case USBPD_NOTIFY_HARDRESET_RX: +// case USBPD_NOTIFY_HARDRESET_TX: +// break; +// case USBPD_NOTIFY_STATE_SRC_DISABLED: +// break; +// case USBPD_NOTIFY_ALERT_RECEIVED : +// break; +// case USBPD_NOTIFY_CABLERESET_REQUESTED : +// break; +// case USBPD_NOTIFY_MSG_NOT_SUPPORTED : +// break; +// case USBPD_NOTIFY_PE_DISABLED : +// break; +// case USBPD_NOTIFY_USBSTACK_START: +// break; +// case USBPD_NOTIFY_USBSTACK_STOP: +// break; +// case USBPD_NOTIFY_DATAROLESWAP_DFP : +// break; +// case USBPD_NOTIFY_DATAROLESWAP_UFP : +// break; + default: + DPM_USER_DEBUG_TRACE(PortNum, "ADVICE: USBPD_DPM_Notification:%d", EventVal); + break; + } +/* USER CODE END USBPD_DPM_Notification */ +} + +/** + * @brief Callback function called by PE layer when HardReset message received from PRL + * @param PortNum The current port number + * @param CurrentRole the current role + * @param Status status on hard reset event + * @retval None + */ +void USBPD_DPM_HardReset(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_HR_Status_TypeDef Status) +{ +/* USER CODE BEGIN USBPD_DPM_HardReset */ + DPM_USER_DEBUG_TRACE(PortNum, "ADVICE: update USBPD_DPM_HardReset"); +/* USER CODE END USBPD_DPM_HardReset */ +} + +/** + * @brief Request the DPM to setup the new power level. + * @param PortNum The current port number + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_DPM_SetupNewPower(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_DPM_SetupNewPower */ + return USBPD_PWR_IF_SetProfile(PortNum); +/* USER CODE END USBPD_DPM_SetupNewPower */ +} + +/** + * @brief DPM callback to allow PE to retrieve information from DPM/PWR_IF. + * @param PortNum Port number + * @param DataId Type of data to be updated in DPM based on @ref USBPD_CORE_DataInfoType_TypeDef + * @param Ptr Pointer on address where DPM data should be written (u8 pointer) + * @param Size Pointer on nb of u8 written by DPM + * @retval None + */ +void USBPD_DPM_GetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t *Size) +{ +/* USER CODE BEGIN USBPD_DPM_GetDataInfo */ + /* Check type of information targeted by request */ + switch(DataId) + { +// case USBPD_CORE_DATATYPE_REQ_VOLTAGE: /*!< Get voltage value requested for BIST tests, expect 5V*/ +// *Size = 4; +// (void)memcpy((uint8_t *)Ptr, (uint8_t *)&DPM_Ports[PortNum].DPM_RequestedVoltage, *Size); + // break; +// case USBPD_CORE_DATATYPE_SRC_PDO: /*!< Handling of port Source PDO */ + // break; +// case USBPD_CORE_PPS_STATUS: /*!< PPS Status message content */ + // break; +// case USBPD_CORE_SNK_EXTENDED_CAPA: /*!< Retrieve of Sink Extended capability message content*/ + // break; +// case USBPD_CORE_INFO_STATUS: /*!< Information status message content */ + // break; +// case USBPD_CORE_MANUFACTURER_INFO: /*!< Retrieve of Manufacturer info message content */ + // break; +// case USBPD_CORE_BATTERY_STATUS: /*!< Retrieve of Battery status message content */ + // break; +// case USBPD_CORE_BATTERY_CAPABILITY: /*!< Retrieve of Battery capability message content */ + // break; + default: + DPM_USER_DEBUG_TRACE(PortNum, "ADVICE: update USBPD_DPM_GetDataInfo:%d", DataId); + break; + } +/* USER CODE END USBPD_DPM_GetDataInfo */ +} + +/** + * @brief DPM callback to allow PE to update information in DPM/PWR_IF. + * @param PortNum Port number + * @param DataId Type of data to be updated in DPM based on @ref USBPD_CORE_DataInfoType_TypeDef + * @param Ptr Pointer on the data + * @param Size Nb of bytes to be updated in DPM + * @retval None + */ +void USBPD_DPM_SetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t Size) +{ +/* USER CODE BEGIN USBPD_DPM_SetDataInfo */ + /* Check type of information targeted by request */ + switch(DataId) + { +// case USBPD_CORE_DATATYPE_RDO_POSITION: /*!< Reset the PDO position selected by the sink only */ + // break; +// case USBPD_CORE_DATATYPE_RCV_SRC_PDO: /*!< Storage of Received Source PDO values */ + // break; +// case USBPD_CORE_DATATYPE_RCV_SNK_PDO: /*!< Storage of Received Sink PDO values */ + // break; + // case USBPD_CORE_DATATYPE_RCV_REQ_PDO : /*!< Storage of Received Sink Request PDO value */ + // if (Size == 4) + // { + // memcpy((uint8_t *)&DPM_Ports[PortNum].DPM_RcvRequestDOMsg, Ptr, 4); + // } + // break; +// case USBPD_CORE_INFO_STATUS: /*!< Information status message content */ + // break; +// case USBPD_CORE_ALERT: /*!< Storing of received Alert message content */ + // break; +// case USBPD_CORE_GET_MANUFACTURER_INFO: /*!< Storing of received Get Manufacturer info message content */ + // break; +// case USBPD_CORE_GET_BATTERY_STATUS: /*!< Storing of received Get Battery status message content */ + // break; +// case USBPD_CORE_GET_BATTERY_CAPABILITY: /*!< Storing of received Get Battery capability message content*/ + // break; +// case USBPD_CORE_SNK_EXTENDED_CAPA: /*!< Storing of Sink Extended capability message content */ + // break; + default: + DPM_USER_DEBUG_TRACE(PortNum, "ADVICE: update USBPD_DPM_SetDataInfo:%d", DataId); + break; + } +/* USER CODE END USBPD_DPM_SetDataInfo */ + +} + +/** + * @brief Evaluate received Request Message from Sink port + * @param PortNum Port number + * @param PtrPowerObject Pointer on the power data object + * @retval USBPD status : USBPD_ACCEPT, USBPD_REJECT, USBPD_WAIT, USBPD_GOTOMIN + */ +USBPD_StatusTypeDef USBPD_DPM_EvaluateRequest(uint8_t PortNum, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject) +{ +/* USER CODE BEGIN USBPD_DPM_EvaluateRequest */ + /* + Set power data object to initialize value. + This parameter is used by the stack to start or not tPPSTimeout + (in case of USBPD_CORE_PDO_TYPE_APDO, stack will wait for periodic request + from the port partner in PPS mode). + */ + *PtrPowerObject = USBPD_CORE_PDO_TYPE_FIXED; + + DPM_USER_DEBUG_TRACE(PortNum, "ADVICE: update USBPD_DPM_EvaluateRequest"); + return USBPD_REJECT; +/* USER CODE END USBPD_DPM_EvaluateRequest */ +} + +/** + * @brief Callback to be used by PE to evaluate a Vconn swap + * @param PortNum Port number + * @retval USBPD_ACCEPT, USBPD_REJECT, USBPD_WAIT + */ +USBPD_StatusTypeDef USBPD_DPM_EvaluateVconnSwap(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_DPM_EvaluateVconnSwap */ + USBPD_StatusTypeDef status = USBPD_REJECT; + if (USBPD_TRUE == DPM_USER_Settings[PortNum].PE_VconnSwap) + { + status = USBPD_ACCEPT; + } + + return status; +/* USER CODE END USBPD_DPM_EvaluateVconnSwap */ +} + +/** + * @brief Callback to be used by PE to manage VConn + * @param PortNum Port number + * @param State Enable or Disable VConn on CC lines + * @retval USBPD_ACCEPT, USBPD_REJECT + */ +USBPD_StatusTypeDef USBPD_DPM_PE_VconnPwr(uint8_t PortNum, USBPD_FunctionalState State) +{ +/* USER CODE BEGIN USBPD_DPM_PE_VconnPwr */ + return USBPD_ERROR; +/* USER CODE END USBPD_DPM_PE_VconnPwr */ +} + +/** + * @brief DPM callback to allow PE to forward extended message information. + * @param PortNum Port number + * @param MsgType Type of message to be handled in DPM + * This parameter can be one of the following values: + * @arg @ref USBPD_EXT_SECURITY_REQUEST Security Request extended message + * @arg @ref USBPD_EXT_SECURITY_RESPONSE Security Response extended message + * @param ptrData Pointer on address Extended Message data could be read (u8 pointer) + * @param DataSize Nb of u8 that compose Extended message + * @retval None + */ +void USBPD_DPM_ExtendedMessageReceived(uint8_t PortNum, USBPD_ExtendedMsg_TypeDef MsgType, uint8_t *ptrData, uint16_t DataSize) +{ +/* USER CODE BEGIN USBPD_DPM_ExtendedMessageReceived */ + +/* USER CODE END USBPD_DPM_ExtendedMessageReceived */ +} + +/** + * @brief DPM callback to allow PE to enter ERROR_RECOVERY state. + * @param PortNum Port number + * @retval None + */ +void USBPD_DPM_EnterErrorRecovery(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_DPM_EnterErrorRecovery */ + /* Inform CAD to enter recovery mode */ + USBPD_CAD_EnterErrorRecovery(PortNum); +/* USER CODE END USBPD_DPM_EnterErrorRecovery */ +} + +/** + * @brief Callback used to ask application the reply status for a DataRoleSwap request + * @note if the callback is not set (ie NULL) the stack will automatically reject the request + * @param PortNum Port number + * @retval Returned values are: + @ref USBPD_ACCEPT if DRS can be accepted + @ref USBPD_REJECT if DRS is not accepted in one data role (DFP or UFP) or in PD2.0 config + @ref USBPD_NOTSUPPORTED if DRS is not supported at all by the application (in both data roles) - P3.0 only + */ +USBPD_StatusTypeDef USBPD_DPM_EvaluateDataRoleSwap(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_DPM_EvaluateDataRoleSwap */ + USBPD_StatusTypeDef status = USBPD_REJECT; + /* Sent NOT_SUPPORTED if DRS is not supported at all by the application (in both data roles) - P3.0 only */ + if ((USBPD_FALSE == DPM_USER_Settings[PortNum].PE_DataSwap) + || ((USBPD_FALSE == DPM_USER_Settings[PortNum].PE_DR_Swap_To_DFP) + && (USBPD_FALSE == DPM_USER_Settings[PortNum].PE_DR_Swap_To_UFP))) + { + status = USBPD_NOTSUPPORTED; + } + else + { + /* ACCEPT DRS if at least supported by 1 data role */ + if (((USBPD_TRUE == DPM_USER_Settings[PortNum].PE_DR_Swap_To_DFP) && (USBPD_PORTDATAROLE_UFP == DPM_Params[PortNum].PE_DataRole)) + || ((USBPD_TRUE == DPM_USER_Settings[PortNum].PE_DR_Swap_To_UFP) && (USBPD_PORTDATAROLE_DFP == DPM_Params[PortNum].PE_DataRole))) + { + status = USBPD_ACCEPT; + } + } + return status; +/* USER CODE END USBPD_DPM_EvaluateDataRoleSwap */ +} + +/** + * @brief Callback to be used by PE to check is VBUS is ready or present + * @param PortNum Port number + * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef + * @retval USBPD_DISABLE or USBPD_ENABLE + */ +USBPD_FunctionalState USBPD_DPM_IsPowerReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe) +{ +/* USER CODE BEGIN USBPD_DPM_IsPowerReady */ + return ((USBPD_OK == USBPD_PWR_IF_SupplyReady(PortNum, Vsafe)) ? USBPD_ENABLE : USBPD_DISABLE); +/* USER CODE END USBPD_DPM_IsPowerReady */ +} + +/** + * @} + */ + +/** @defgroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP3 USBPD USER Functions PD messages requests + * @{ + */ + +/** + * @brief Request the PE to send a hard reset + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestHardReset(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_HardReset(PortNum); + DPM_USER_ERROR_TRACE(PortNum, _status, "HARD RESET not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a cable reset. + * @note Only a DFP Shall generate Cable Reset Signaling. A DFP Shall only generate Cable Reset Signaling within an Explicit Contract. + The DFP has to be supplying VCONN prior to a Cable Reset + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestCableReset(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CableReset(PortNum); + DPM_USER_ERROR_TRACE(PortNum, _status, "CABLE RESET not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a GOTOMIN message + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGotoMin(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_GOTOMIN, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "GOTOMIN not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a PING message + * @note In USB-PD stack, only ping management for P3.0 is implemented. + * If PD2.0 is used, PING timer needs to be implemented on user side. + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestPing(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_PING, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "PING not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a request message. + * @param PortNum The current port number + * @param IndexSrcPDO Index on the selected SRC PDO (value between 1 to 7) + * @param RequestedVoltage Requested voltage (in MV and use mainly for APDO) + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestMessageRequest(uint8_t PortNum, uint8_t IndexSrcPDO, uint16_t RequestedVoltage) +{ + USBPD_StatusTypeDef _status = USBPD_ERROR; +/* USER CODE BEGIN USBPD_DPM_RequestMessageRequest */ + /* To be adapted to call the PE function */ + /* _status = USBPD_PE_Send_Request(PortNum, rdo.d32, pdo_object);*/ + DPM_USER_DEBUG_TRACE(PortNum, "ADVICE: update USBPD_DPM_RequestMessageRequest"); +/* USER CODE END USBPD_DPM_RequestMessageRequest */ + DPM_USER_ERROR_TRACE(PortNum, _status, "REQUEST not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a GET_SRC_CAPA message + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetSourceCapability(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_GET_SRC_CAP, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_SRC_CAPA not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a GET_SNK_CAPA message + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetSinkCapability(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_GET_SNK_CAP, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_SINK_CAPA not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to perform a Data Role Swap. + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestDataRoleSwap(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_DR_SWAP, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "DRS not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to perform a Power Role Swap. + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestPowerRoleSwap(uint8_t PortNum) +{ + DPM_USER_ERROR_TRACE(PortNum, USBPD_ERROR, "PRS not accepted by the stack"); + return USBPD_ERROR; +} + +/** + * @brief Request the PE to perform a VCONN Swap. + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestVconnSwap(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_VCONN_SWAP, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "VCS not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a soft reset + * @param PortNum The current port number + * @param SOPType SOP Type based on @ref USBPD_SOPType_TypeDef + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestSoftReset(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_SOFT_RESET, SOPType); + DPM_USER_ERROR_TRACE(PortNum, _status, "SOFT_RESET not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a Source Capability message. + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestSourceCapability(uint8_t PortNum) +{ + /* PE will directly get the PDO saved in structure @ref PWR_Port_PDO_Storage */ + USBPD_StatusTypeDef _status = USBPD_PE_Request_DataMessage(PortNum, USBPD_DATAMSG_SRC_CAPABILITIES, NULL); + DPM_USER_ERROR_TRACE(PortNum, _status, "SRC_CAPA not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a VDM discovery identity + * @param PortNum The current port number + * @param SOPType SOP Type + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_DiscoveryIdentify(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType) +{ + USBPD_StatusTypeDef _status = USBPD_ERROR; +/* USER CODE BEGIN USBPD_DPM_RequestVDM_DiscoveryIdentify */ + if (USBPD_SOPTYPE_SOP == SOPType) + { + _status = USBPD_PE_SVDM_RequestIdentity(PortNum, SOPType); + } +/* USER CODE END USBPD_DPM_RequestVDM_DiscoveryIdentify */ + DPM_USER_ERROR_TRACE(PortNum, _status, "VDM Discovery Ident not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a VDM discovery SVID + * @param PortNum The current port number + * @param SOPType SOP Type + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_DiscoverySVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType) +{ + USBPD_StatusTypeDef _status = USBPD_PE_SVDM_RequestSVID(PortNum, SOPType); + DPM_USER_ERROR_TRACE(PortNum, _status, "VDM discovery SVID not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to perform a VDM Discovery mode message on one SVID. + * @param PortNum The current port number + * @param SOPType SOP Type + * @param SVID SVID used for discovery mode message + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_DiscoveryMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID) +{ + USBPD_StatusTypeDef _status = USBPD_PE_SVDM_RequestMode(PortNum, SOPType, SVID); + DPM_USER_ERROR_TRACE(PortNum, _status, "VDM Discovery mode not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to perform a VDM mode enter. + * @param PortNum The current port number + * @param SOPType SOP Type + * @param SVID SVID used for discovery mode message + * @param ModeIndex Index of the mode to be entered + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_EnterMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint8_t ModeIndex) +{ + USBPD_StatusTypeDef _status = USBPD_PE_SVDM_RequestModeEnter(PortNum, SOPType, SVID, ModeIndex); + DPM_USER_ERROR_TRACE(PortNum, _status, "VDM mode enter not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to perform a VDM mode exit. + * @param PortNum The current port number + * @param SOPType SOP Type + * @param SVID SVID used for discovery mode message + * @param ModeIndex Index of the mode to be exit + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_ExitMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint8_t ModeIndex) +{ + USBPD_StatusTypeDef _status = USBPD_PE_SVDM_RequestModeExit(PortNum, SOPType, SVID, ModeIndex); + DPM_USER_ERROR_TRACE(PortNum, _status, "VDM mode exit not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a Display Port status + * @param PortNum The current port number + * @param SOPType SOP Type + * @param SVID Used SVID + * @param pDPStatus Pointer on DP Status data (32 bit) + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestDisplayPortStatus(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint32_t *pDPStatus) +{ + USBPD_StatusTypeDef _status; +/* USER CODE BEGIN USBPD_DPM_RequestDisplayPortStatus */ + /*USBPD_VDM_FillDPStatus(PortNum, (USBPD_DPStatus_TypeDef*)pDPStatus);*/ +/* USER CODE END USBPD_DPM_RequestDisplayPortStatus */ + _status = USBPD_PE_SVDM_RequestSpecific(PortNum, SOPType, SVDM_SPECIFIC_1, SVID); + DPM_USER_ERROR_TRACE(PortNum, _status, "Display Port status not accepted by the stack"); + return _status; +} +/** + * @brief Request the PE to send a Display Port Config + * @param PortNum The current port number + * @param SOPType SOP Type + * @param SVID Used SVID + * @param pDPConfig Pointer on DP Config data (32 bit) + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestDisplayPortConfig(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint32_t *pDPConfig) +{ + USBPD_StatusTypeDef _status; +/* USER CODE BEGIN USBPD_DPM_RequestDisplayPortConfig */ + /*USBPD_VDM_FillDPConfig(PortNum, (USBPD_DPConfig_TypeDef*)pDPConfig);*/ +/* USER CODE END USBPD_DPM_RequestDisplayPortConfig */ + _status = USBPD_PE_SVDM_RequestSpecific(PortNum, SOPType, SVDM_SPECIFIC_2, SVID); + DPM_USER_ERROR_TRACE(PortNum, _status, "Display Port Config not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to perform a VDM Attention. + * @param PortNum The current port number + * @param SOPType SOP Type + * @param SVID Used SVID + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestAttention(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID) +{ + USBPD_StatusTypeDef _status = USBPD_PE_SVDM_RequestAttention(PortNum, SOPType, SVID); + DPM_USER_ERROR_TRACE(PortNum, _status, "VDM ATTENTION not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send an ALERT to port partner + * @param PortNum The current port number + * @param Alert Alert based on @ref USBPD_ADO_TypeDef + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestAlert(uint8_t PortNum, USBPD_ADO_TypeDef Alert) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_DataMessage(PortNum, USBPD_DATAMSG_ALERT, (uint32_t*)&Alert.d32); + DPM_USER_ERROR_TRACE(PortNum, _status, "ALERT not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to get a source capability extended + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetSourceCapabilityExt(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_GET_SRC_CAPEXT, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_SRC_CAPA_EXT not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to get a sink capability extended + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetSinkCapabilityExt(uint8_t PortNum) +{ + DPM_USER_ERROR_TRACE(PortNum, USBPD_ERROR, "GET_SINK_CAPA_EXT not accepted by the stack"); + return USBPD_ERROR; +} + +/** + * @brief Request the PE to get a manufacturer info + * @param PortNum The current port number + * @param SOPType SOP Type + * @param pManuInfoData Pointer on manufacturer info based on @ref USBPD_GMIDB_TypeDef + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetManufacturerInfo(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint8_t* pManuInfoData) +{ + USBPD_StatusTypeDef _status = USBPD_ERROR; + if (USBPD_SOPTYPE_SOP == SOPType) + { + _status = USBPD_PE_SendExtendedMessage(PortNum, SOPType, USBPD_EXT_GET_MANUFACTURER_INFO, (uint8_t*)pManuInfoData, sizeof(USBPD_GMIDB_TypeDef)); + } + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_MANU_INFO not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to request a GET_PPS_STATUS + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetPPS_Status(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_GET_PPS_STATUS, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_PPS_STATUS not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to request a GET_STATUS + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetStatus(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_GET_STATUS, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_STATUS not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to perform a Fast Role Swap. + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestFastRoleSwap(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_FR_SWAP, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "FRS not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a GET_COUNTRY_CODES message + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetCountryCodes(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_CtrlMessage(PortNum, USBPD_CONTROLMSG_GET_COUNTRY_CODES, USBPD_SOPTYPE_SOP); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_COUNTRY_CODES not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a GET_COUNTRY_INFO message + * @param PortNum The current port number + * @param CountryCode Country code (1st character and 2nd of the Alpha-2 Country) + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetCountryInfo(uint8_t PortNum, uint16_t CountryCode) +{ + USBPD_StatusTypeDef _status = USBPD_PE_Request_DataMessage(PortNum, USBPD_DATAMSG_GET_COUNTRY_INFO, (uint32_t*)&CountryCode); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_COUNTRY_INFO not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a GET_BATTERY_CAPA + * @param PortNum The current port number + * @param pBatteryCapRef Pointer on the Battery Capability reference + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetBatteryCapability(uint8_t PortNum, uint8_t *pBatteryCapRef) +{ + USBPD_StatusTypeDef _status = USBPD_PE_SendExtendedMessage(PortNum, USBPD_SOPTYPE_SOP, USBPD_EXT_GET_BATTERY_CAP, (uint8_t*)pBatteryCapRef, 1); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_BATTERY_CAPA not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a GET_BATTERY_STATUS + * @param PortNum The current port number + * @param pBatteryStatusRef Pointer on the Battery Status reference + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestGetBatteryStatus(uint8_t PortNum, uint8_t *pBatteryStatusRef) +{ + USBPD_StatusTypeDef _status = USBPD_PE_SendExtendedMessage(PortNum, USBPD_SOPTYPE_SOP, USBPD_EXT_GET_BATTERY_STATUS, (uint8_t*)pBatteryStatusRef, 1); + DPM_USER_ERROR_TRACE(PortNum, _status, "GET_BATTERY_STATUS not accepted by the stack"); + return _status; +} + +/** + * @brief Request the PE to send a SECURITY_REQUEST + * @param PortNum The current port number + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_DPM_RequestSecurityRequest(uint8_t PortNum) +{ + USBPD_StatusTypeDef _status = USBPD_ERROR; + DPM_USER_ERROR_TRACE(PortNum, _status, "SECURITY_REQUEST not accepted by the stack"); + return _status; +} + +/** + * @} + */ + +/** @addtogroup USBPD_USER_PRIVATE_FUNCTIONS + * @{ + */ + +/* USER CODE BEGIN USBPD_USER_PRIVATE_FUNCTIONS */ + +/* USER CODE END USBPD_USER_PRIVATE_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/USBPD/usbpd_dpm_user.h b/USBPD/usbpd_dpm_user.h new file mode 100644 index 0000000..093ed5d --- /dev/null +++ b/USBPD/usbpd_dpm_user.h @@ -0,0 +1,180 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_dpm_user.h + * @author MCD Application Team + * @brief Header file for usbpd_dpm_user.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __USBPD_DPM_USER_H_ +#define __USBPD_DPM_USER_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* USER CODE BEGIN Include */ + +/* USER CODE END Include */ + +/** @addtogroup STM32_USBPD_APPLICATION + * @{ + */ + +/** @addtogroup STM32_USBPD_APPLICATION_DPM_USER + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +typedef struct +{ + uint32_t PE_DataSwap : 1U; /*!< support data swap */ + uint32_t PE_VconnSwap : 1U; /*!< support VCONN swap */ + uint32_t PE_DR_Swap_To_DFP : 1U; /*!< If supported, DR Swap to DFP can be accepted or not by the user else directly rejected */ + uint32_t PE_DR_Swap_To_UFP : 1U; /*!< If supported, DR Swap to UFP can be accepted or not by the user else directly rejected */ + uint32_t Reserved1 :28U; /*!< Reserved bits */ + uint32_t Reserved_ReqPower[6]; /*!< Reserved bits to match with Resquested power information */ + USBPD_MIDB_TypeDef DPM_ManuInfoPort; /*!< Manufacturer information used for the port */ +uint32_t ReservedSnkCapa[6]; /*!< Reserved bits to match with SnkCapaExt information */ + uint16_t ReservedManu; /*!< Reserved bits to match with Manufacturer information */ +} USBPD_USER_SettingsTypeDef; + +typedef struct +{ + uint32_t XID; /*!< Value provided by the USB-IF assigned to the product */ + uint16_t VID; /*!< Vendor ID (assigned by the USB-IF) */ + uint16_t PID; /*!< Product ID (assigned by the manufacturer) */ +} USBPD_IdSettingsTypeDef; +/* USER CODE BEGIN Typedef */ + +/* USER CODE END Typedef */ + +/* Exported define -----------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN Constant */ + +/* USER CODE END Constant */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Exported variables --------------------------------------------------------*/ +/* USER CODE BEGIN Private_Variables */ + +/* USER CODE END Private_Variables */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS + * @{ + */ +/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP1 + * @{ + */ +USBPD_StatusTypeDef USBPD_DPM_UserInit(void); +void USBPD_DPM_WaitForTime(uint32_t Time); +void USBPD_DPM_UserExecute(void const *argument); +void USBPD_DPM_UserCableDetection(uint8_t PortNum, USBPD_CAD_EVENT State); +void USBPD_DPM_UserTimerCounter(uint8_t PortNum); + +/** + * @} + */ + +/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP2 + * @{ + */ +void USBPD_DPM_Notification(uint8_t PortNum, USBPD_NotifyEventValue_TypeDef EventVal); +USBPD_StatusTypeDef USBPD_DPM_SetupNewPower(uint8_t PortNum); +void USBPD_DPM_HardReset(uint8_t PortNum, USBPD_PortPowerRole_TypeDef CurrentRole, USBPD_HR_Status_TypeDef Status); +void USBPD_DPM_ExtendedMessageReceived(uint8_t PortNum, USBPD_ExtendedMsg_TypeDef MsgType, uint8_t *ptrData, uint16_t DataSize); +void USBPD_DPM_GetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId , uint8_t *Ptr, uint32_t *Size); +void USBPD_DPM_SetDataInfo(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId , uint8_t *Ptr, uint32_t Size); +USBPD_StatusTypeDef USBPD_DPM_EvaluateRequest(uint8_t PortNum, USBPD_CORE_PDO_Type_TypeDef *PtrPowerObject); +USBPD_StatusTypeDef USBPD_DPM_EvaluateVconnSwap(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_PE_VconnPwr(uint8_t PortNum, USBPD_FunctionalState State); +void USBPD_DPM_EnterErrorRecovery(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_EvaluateDataRoleSwap(uint8_t PortNum); +USBPD_FunctionalState USBPD_DPM_IsPowerReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe); + +/** + * @} + */ + +/** @addtogroup USBPD_USER_EXPORTED_FUNCTIONS_GROUP3 + * @{ + */ +USBPD_StatusTypeDef USBPD_DPM_RequestHardReset(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestCableReset(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestGotoMin(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestPing(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestMessageRequest(uint8_t PortNum, uint8_t IndexSrcPDO, uint16_t RequestedVoltage); +USBPD_StatusTypeDef USBPD_DPM_RequestGetSourceCapability(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestGetSinkCapability(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestDataRoleSwap(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestPowerRoleSwap(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestVconnSwap(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestSoftReset(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); +USBPD_StatusTypeDef USBPD_DPM_RequestSourceCapability(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_DiscoveryIdentify(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_DiscoverySVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType); +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_DiscoveryMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID); +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_EnterMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint8_t ModeIndex); +USBPD_StatusTypeDef USBPD_DPM_RequestVDM_ExitMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint8_t ModeIndex); +USBPD_StatusTypeDef USBPD_DPM_RequestDisplayPortStatus(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint32_t *pDPStatus); +USBPD_StatusTypeDef USBPD_DPM_RequestDisplayPortConfig(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID, uint32_t *pDPConfig); +USBPD_StatusTypeDef USBPD_DPM_RequestAttention(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint16_t SVID); +USBPD_StatusTypeDef USBPD_DPM_RequestAlert(uint8_t PortNum, USBPD_ADO_TypeDef Alert); +USBPD_StatusTypeDef USBPD_DPM_RequestGetSourceCapabilityExt(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestGetSinkCapabilityExt(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestGetManufacturerInfo(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, uint8_t* pManuInfoData); +USBPD_StatusTypeDef USBPD_DPM_RequestGetStatus(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestFastRoleSwap(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestGetPPS_Status(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestGetCountryCodes(uint8_t PortNum); +USBPD_StatusTypeDef USBPD_DPM_RequestGetCountryInfo(uint8_t PortNum, uint16_t CountryCode); +USBPD_StatusTypeDef USBPD_DPM_RequestGetBatteryCapability(uint8_t PortNum, uint8_t *pBatteryCapRef); +USBPD_StatusTypeDef USBPD_DPM_RequestGetBatteryStatus(uint8_t PortNum, uint8_t *pBatteryStatusRef); +USBPD_StatusTypeDef USBPD_DPM_RequestSecurityRequest(uint8_t PortNum); +/* USER CODE BEGIN Function */ + +/* USER CODE END Function */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_DPM_USER_H_ */ diff --git a/USBPD/usbpd_pdo_defs.h b/USBPD/usbpd_pdo_defs.h new file mode 100644 index 0000000..6fb9c7e --- /dev/null +++ b/USBPD/usbpd_pdo_defs.h @@ -0,0 +1,149 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_pdo_defs.h + * @author MCD Application Team + * @brief Header file for definition of PDO/APDO values for 2 ports(DRP/SNK) configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __USBPD_PDO_DEF_H_ +#define __USBPD_PDO_DEF_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_def.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Define ------------------------------------------------------------------*/ +#define PORT0_NB_SOURCEPDO 1U /* Number of Source PDOs (applicable for port 0) */ +#define PORT0_NB_SINKPDO 0U /* Number of Sink PDOs (applicable for port 0) */ +#define PORT1_NB_SOURCEPDO 0U /* Number of Source PDOs (applicable for port 1) */ +#define PORT1_NB_SINKPDO 0U /* Number of Sink PDOs (applicable for port 1) */ + +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Exported typedef ----------------------------------------------------------*/ + +/* USER CODE BEGIN typedef */ +/** + * @brief USBPD Port PDO Structure definition + * + */ +/* USER CODE END typedef */ + +/* Exported define -----------------------------------------------------------*/ + +/* USER CODE BEGIN Exported_Define */ + +#define USBPD_CORE_PDO_SRC_FIXED_MAX_CURRENT 3 +#define USBPD_CORE_PDO_SNK_FIXED_MAX_CURRENT 1500 + +/* USER CODE END Exported_Define */ + +/* Exported constants --------------------------------------------------------*/ + +/* USER CODE BEGIN constants */ + +/* USER CODE END constants */ + +/* Exported macro ------------------------------------------------------------*/ + +/* USER CODE BEGIN macro */ + +/* USER CODE END macro */ + +/* Exported variables --------------------------------------------------------*/ + +/* USER CODE BEGIN variables */ +/* USER CODE END variables */ + +#ifndef __USBPD_PWR_IF_C +extern uint32_t PORT0_PDO_ListSRC[USBPD_MAX_NB_PDO]; +extern uint32_t PORT0_PDO_ListSNK[USBPD_MAX_NB_PDO]; +#else +/* Definition of Source PDO for Port 0 */ +uint32_t PORT0_PDO_ListSRC[USBPD_MAX_NB_PDO] = +{ + /* PDO 1 */ + ( + USBPD_PDO_TYPE_FIXED | /* Fixed supply PDO */ + + USBPD_PDO_SRC_FIXED_SET_VOLTAGE(5000U) | /* Voltage in mV */ + USBPD_PDO_SRC_FIXED_SET_MAX_CURRENT(5000U) | /* Max current in mA */ + USBPD_PDO_SRC_FIXED_PEAKCURRENT_EQUAL | /* Peak Current info */ + + /* Common definitions applicable to all PDOs, defined only in PDO 1 */ + USBPD_PDO_SRC_FIXED_UNCHUNK_NOT_SUPPORTED | /* Unchunked Extended Messages */ + USBPD_PDO_SRC_FIXED_DRD_SUPPORTED | /* Dual-Role Data */ + USBPD_PDO_SRC_FIXED_USBCOMM_NOT_SUPPORTED | /* USB Communications */ + USBPD_PDO_SRC_FIXED_EXT_POWER_NOT_AVAILABLE | /* External Power */ + USBPD_PDO_SRC_FIXED_USBSUSPEND_NOT_SUPPORTED | /* USB Suspend Supported */ + USBPD_PDO_SRC_FIXED_DRP_NOT_SUPPORTED /* Dual-Role Power */ + ), + + /* PDO 2 */ (0x00000000U), + + /* PDO 3 */ (0x00000000U), + + /* PDO 4 */ (0x00000000U), + + /* PDO 5 */ (0x00000000U), + + /* PDO 6 */ (0x00000000U), + + /* PDO 7 */ (0x00000000U), + +}; + +/* Definition of Sink PDO for Port 0 */ +uint32_t PORT0_PDO_ListSNK[USBPD_MAX_NB_PDO] = +{ + + /* PDO 1 */ (0x00000000U), + + /* PDO 2 */ (0x00000000U), + + /* PDO 3 */ (0x00000000U), + + /* PDO 4 */ (0x00000000U), + + /* PDO 5 */ (0x00000000U), + + /* PDO 6 */ (0x00000000U), + + /* PDO 7 */ (0x00000000U), +}; + +#endif + +/* Exported functions --------------------------------------------------------*/ + +/* USER CODE BEGIN functions */ + +/* USER CODE END functions */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_PDO_DEF_H_ */ diff --git a/USBPD/usbpd_pwr_if.c b/USBPD/usbpd_pwr_if.c new file mode 100644 index 0000000..9c769cf --- /dev/null +++ b/USBPD/usbpd_pwr_if.c @@ -0,0 +1,389 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_pwr_if.c + * @author MCD Application Team + * @brief This file contains power interface control functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#define __USBPD_PWR_IF_C + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_pwr_if.h" +#include "usbpd_hw_if.h" +#include "usbpd_dpm_core.h" +#include "usbpd_dpm_conf.h" +#include "usbpd_pdo_defs.h" +#include "usbpd_core.h" +#if defined(_TRACE) +#include "usbpd_trace.h" +#endif /* _TRACE */ +#include "string.h" +/* USER CODE BEGIN Include */ + +/* USER CODE END Include */ + +/** @addtogroup STM32_USBPD_APPLICATION + * @{ + */ + +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_TypeDef + * @{ + */ +/* USER CODE BEGIN Private_Typedef */ + +/* USER CODE END Private_Typedef */ +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Defines + * @{ + */ +/* USER CODE BEGIN Private_Define */ + +/* USER CODE END Private_Define */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Macros + * @{ + */ +#if defined(_TRACE) +#define PWR_IF_DEBUG_TRACE(_PORT_, __MESSAGE__) USBPD_TRACE_Add(USBPD_TRACE_DEBUG, (_PORT_), 0u, (uint8_t*)(__MESSAGE__), sizeof(__MESSAGE__) - 1u) +#else +#define PWR_IF_DEBUG_TRACE(_PORT_, __MESSAGE__) +#endif /* _TRACE */ +/* USER CODE BEGIN Private_Macro */ + +/* USER CODE END Private_Macro */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Variables + * @{ + */ +/* USER CODE BEGIN Private_Variables */ + +/* USER CODE END Private_Variables */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Functions + * @{ + */ +/* USER CODE BEGIN USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ + +/* USER CODE END USBPD_USER_PRIVATE_FUNCTIONS_Prototypes */ +/** + * @} + */ + +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Exported_Functions + * @{ + */ + +/** + * @brief Initialize structures and variables related to power board profiles + * used by Sink and Source, for all available ports. + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_Init(void) +{ +/* USER CODE BEGIN USBPD_PWR_IF_Init */ + return USBPD_ERROR; +/* USER CODE END USBPD_PWR_IF_Init */ +} + +/** + * @brief Sets the required power profile, now it works only with Fixed ones + * @param PortNum Port number + * @retval USBPD status +*/ +USBPD_StatusTypeDef USBPD_PWR_IF_SetProfile(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_PWR_IF_SetProfile */ + USBPD_StatusTypeDef _status = USBPD_ERROR; + PWR_IF_DEBUG_TRACE(PortNum, "ADVICE: update USBPD_PWR_IF_SetProfile"); +/* if (BSP_ERROR_NONE == BSP_USBPD_PWR_VBUSSetVoltage_Fixed(PortNum, 5000, 3000, 3000)) + { + _status = USBPD_OK; + } + */ + return _status; +/* USER CODE END USBPD_PWR_IF_SetProfile */ +} + +/** + * @brief Checks if the power on a specified port is ready + * @param PortNum Port number + * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_SupplyReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe) +{ +/* USER CODE BEGIN USBPD_PWR_IF_SupplyReady */ + USBPD_StatusTypeDef status = USBPD_ERROR; + uint32_t _voltage; + + /* check for valid port */ + if (!USBPD_PORT_IsValid(PortNum)) + { + return USBPD_ERROR; + } + + BSP_USBPD_PWR_VBUSGetVoltage(PortNum, &_voltage); + if (USBPD_VSAFE_0V == Vsafe) + { + /* Vsafe0V */ + status = ((_voltage < USBPD_PWR_LOW_VBUS_THRESHOLD) ? USBPD_OK : USBPD_ERROR); + } + else + { + /* Vsafe5V */ + status = ((_voltage > USBPD_PWR_HIGH_VBUS_THRESHOLD) ? USBPD_OK : USBPD_ERROR); + } + + return status; +/* USER CODE END USBPD_PWR_IF_SupplyReady */ +} + +/** + * @brief Enables VBUS power on a specified port + * @param PortNum Port number + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_VBUSEnable(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_PWR_IF_VBUSEnable */ + USBPD_StatusTypeDef _status = (USBPD_StatusTypeDef)HW_IF_PWR_Enable(PortNum, USBPD_ENABLE, CCNONE, USBPD_FALSE, USBPD_PORTPOWERROLE_SRC); + return _status; +/* USER CODE END USBPD_PWR_IF_VBUSEnable */ +} + +/** + * @brief Disable VBUS/VCONN the power on a specified port + * @param PortNum Port number + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_VBUSDisable(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_PWR_IF_VBUSDisable */ + USBPD_StatusTypeDef _status = (USBPD_StatusTypeDef)HW_IF_PWR_Enable(PortNum, USBPD_DISABLE, CCNONE, USBPD_FALSE, USBPD_PORTPOWERROLE_SRC); + return _status; +/* USER CODE END USBPD_PWR_IF_VBUSDisable */ +} + +/** + * @brief Checks if the power on a specified port is enabled + * @param PortNum Port number + * @retval USBPD_ENABLE or USBPD_DISABLE + */ +USBPD_FunctionalState USBPD_PWR_IF_VBUSIsEnabled(uint8_t PortNum) +{ + /* Get the Status of the port */ + return USBPD_PORT_IsValid(PortNum) ? (USBPD_FunctionalState)HW_IF_PWR_VBUSIsEnabled(PortNum) : USBPD_DISABLE; +} + +/** + * @brief Reads the voltage and the current on a specified port + * @param PortNum Port number + * @param pVoltage: The Voltage in mV + * @param pCurrent: The Current in mA + * @retval USBPD_ERROR or USBPD_OK + */ +USBPD_StatusTypeDef USBPD_PWR_IF_ReadVA(uint8_t PortNum, uint16_t *pVoltage, uint16_t *pCurrent) +{ +/* USER CODE BEGIN USBPD_PWR_IF_ReadVA */ + return USBPD_ERROR; +/* USER CODE END USBPD_PWR_IF_ReadVA */ +} + +/** + * @brief Enables the VConn on the port. + * @param PortNum Port number + * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_Enable_VConn(uint8_t PortNum, CCxPin_TypeDef CC) +{ +/* USER CODE BEGIN USBPD_PWR_IF_Enable_VConn */ + return USBPD_ERROR; +/* USER CODE END USBPD_PWR_IF_Enable_VConn */ +} + +/** + * @brief Disable the VConn on the port. + * @param PortNum Port number + * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_Disable_VConn(uint8_t PortNum, CCxPin_TypeDef CC) +{ +/* USER CODE BEGIN USBPD_PWR_IF_Disable_VConn */ + return USBPD_ERROR; +/* USER CODE END USBPD_PWR_IF_Disable_VConn */ +} + +/** + * @brief Allow PDO data reading from PWR_IF storage. + * @param PortNum Port number + * @param DataId Type of data to be read from PWR_IF + * This parameter can be one of the following values: + * @arg @ref USBPD_CORE_DATATYPE_SRC_PDO Source PDO reading requested + * @arg @ref USBPD_CORE_DATATYPE_SNK_PDO Sink PDO reading requested + * @param Ptr Pointer on address where PDO values should be written (u8 pointer) + * @param Size Pointer on nb of u32 written by PWR_IF (nb of PDOs) + * @retval None + */ +void USBPD_PWR_IF_GetPortPDOs(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t *Size) +{ + if (DataId == USBPD_CORE_DATATYPE_SRC_PDO) + { + *Size = PORT0_NB_SOURCEPDO; + memcpy(Ptr,PORT0_PDO_ListSRC, sizeof(uint32_t) * PORT0_NB_SOURCEPDO); + } +/* USER CODE BEGIN USBPD_PWR_IF_GetPortPDOs */ + +/* USER CODE END USBPD_PWR_IF_GetPortPDOs */ +} + +/** + * @brief Find out SRC PDO pointed out by a position provided in a Request DO (from Sink). + * @param PortNum Port number + * @param RdoPosition RDO Position in list of provided PDO + * @param Pdo Pointer on PDO value pointed out by RDO position (u32 pointer) + * @retval Status of search + * USBPD_OK : Src PDO found for requested DO position (output Pdo parameter is set) + * USBPD_FAIL : Position is not compliant with current Src PDO for this port (no corresponding PDO value) + */ +USBPD_StatusTypeDef USBPD_PWR_IF_SearchRequestedPDO(uint8_t PortNum, uint32_t RdoPosition, uint32_t *Pdo) +{ +/* USER CODE BEGIN USBPD_PWR_IF_SearchRequestedPDO */ + return USBPD_FAIL; +/* USER CODE END USBPD_PWR_IF_SearchRequestedPDO */ +} + +/** + * @brief Function called in case of critical issue is detected to switch in safety mode. + * @param ErrorType Type of error detected by monitoring (based on @ref USBPD_PWR_IF_ERROR) + * @retval None + */ +void USBPD_PWR_IF_AlarmType(USBPD_PWR_IF_ERROR ErrorType) +{ +/* USER CODE BEGIN USBPD_PWR_IF_AlarmType */ + +/* USER CODE END USBPD_PWR_IF_AlarmType */ +} + +/** + * @brief the function is called in case of critical issue is detected to switch in safety mode. + * @retval None + */ +void USBPD_PWR_IF_Alarm() +{ +/* USER CODE BEGIN USBPD_PWR_IF_Alarm */ + +/* USER CODE END USBPD_PWR_IF_Alarm */ +} + +/** + * @brief Function is called to get VBUS power status. + * @param PortNum Port number + * @param PowerTypeStatus Power type status based on @ref USBPD_VBUSPOWER_STATUS + * @retval UBBPD_TRUE or USBPD_FALSE + */ +uint8_t USBPD_PWR_IF_GetVBUSStatus(uint8_t PortNum, USBPD_VBUSPOWER_STATUS PowerTypeStatus) +{ +/* USER CODE BEGIN USBPD_PWR_IF_GetVBUSStatus */ + uint8_t _status = USBPD_FALSE; + uint32_t _vbus = HW_IF_PWR_GetVoltage(PortNum); + + switch(PowerTypeStatus) + { + case USBPD_PWR_BELOWVSAFE0V : + if (_vbus < USBPD_PWR_LOW_VBUS_THRESHOLD) _status = USBPD_TRUE; + break; + case USBPD_PWR_VSAFE5V : + if (_vbus >= USBPD_PWR_HIGH_VBUS_THRESHOLD) _status = USBPD_TRUE; + break; + case USBPD_PWR_SNKDETACH: + if (_vbus < USBPD_PWR_HIGH_VBUS_THRESHOLD) _status = USBPD_TRUE; + break; + default : + break; + } + return _status; +/* USER CODE END USBPD_PWR_IF_GetVBUSStatus */ +} + +/** + * @brief Function is called to set the VBUS threshold when a request has been accepted. + * @param PortNum Port number + * @retval None + */ +void USBPD_PWR_IF_UpdateVbusThreshold(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_PWR_IF_UpdateVbusThreshold */ +/* USER CODE END USBPD_PWR_IF_UpdateVbusThreshold */ +} + +/** + * @brief Function is called to reset the VBUS threshold when there is a power reset. + * @param PortNum Port number + * @retval None + */ +void USBPD_PWR_IF_ResetVbusThreshold(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_PWR_IF_ResetVbusThreshold */ +/* USER CODE END USBPD_PWR_IF_ResetVbusThreshold */ +} + +/* USER CODE BEGIN USBPD_USER_EXPORTED_FUNCTIONS_Definition */ + +/* USER CODE END USBPD_USER_EXPORTED_FUNCTIONS_Definition */ +/** + * @} + */ + +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF_Private_Functions + * @{ + */ +/* USER CODE BEGIN USBPD_USER_PRIVATE_FUNCTIONS_Definition */ + +/* USER CODE END USBPD_USER_PRIVATE_FUNCTIONS_Definition */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/USBPD/usbpd_pwr_if.h b/USBPD/usbpd_pwr_if.h new file mode 100644 index 0000000..208f481 --- /dev/null +++ b/USBPD/usbpd_pwr_if.h @@ -0,0 +1,362 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_pwr_if.h + * @author MCD Application Team + * @brief This file contains the headers of usbpd_pw_if.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __USBPD_PW_IF_H_ +#define __USBPD_PW_IF_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_def.h" + +/** @addtogroup STM32_USBPD_APPLICATION + * @{ + */ + +/** @addtogroup STM32_USBPD_APPLICATION_POWER_IF + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +/* Exported define -----------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USBPD_USER_PWR_IF_Exported_Macros USBPD PWR IF Exported Macros + * @{ + */ + +/* enumeration of the different power status available for VBUS */ +typedef enum +{ + USBPD_PWR_BELOWVSAFE0V, + USBPD_PWR_VSAFE5V, + USBPD_PWR_SNKDETACH +} USBPD_VBUSPOWER_STATUS; + +/* Enumeration of the different errors detected by power IF */ +typedef enum{ + USBPD_PWR_IF_OTHER = 0U, + USBPD_PWR_IF_NMI = 2U, + USBPD_PWR_IF_HARD_FAULT = 3U, + USBPD_PWR_IF_OVER_CURRENT = 4U, +} USBPD_PWR_IF_ERROR; + +/* Macros used to convert values into PDO representation */ +#define PWR_V_20MV(_V_) ((uint16_t)(( (_V_) * 1000) / 20)) /* From Volt to 20mV multiples */ +#define PWR_V_50MV(_V_) ((uint16_t)(( (_V_) * 1000) / 50)) /* From Volt to 50mV multiples */ +#define PWR_V_100MV(_V_) ((uint16_t)(( (_V_) * 1000) / 100)) /* From Volt to 100mV multiples */ +#define PWR_A_10MA(_A_) ((uint16_t)(( (_A_) * 1000) / 10)) /* From Ampere to 10mA multiples */ +#define PWR_A_50MA(_A_) ((uint16_t)(( (_A_) * 1000) / 50)) /* From Ampere to 50mA multiples */ +#define PWR_W(_W_) ((uint16_t)(( (_W_) * 1000) / 250)) /* From Watt to 250mW multiples */ + +/* Macros used to get values from PDO representation */ +#define PWR_DECODE_50MV(_Value_) ((uint16_t)(((_Value_) * 50))) /* From 50mV multiples to mV */ +#define PWR_DECODE_100MV(_Value_) ((uint16_t)(((_Value_) * 100))) /* From 100mV multiples to mV */ +#define PWR_DECODE_10MA(_Value_) ((uint16_t)(((_Value_) * 10))) /* From 10mA multiples to mA */ +#define PWR_DECODE_50MA(_Value_) ((uint16_t)(((_Value_) * 50))) /* From 50mA multiples to mA */ +#define PWR_DECODE_MW(_Value_) ((uint16_t)(((_Value_) * 250))) /* From 250mW multiples to mW */ + +/* Macros used to describe the parameters in a PDO list */ +/* ---------------------------- FIXED --------------------------- */ + +/* Set voltage in mV in SRC Fixed PDO */ +#define USBPD_PDO_SRC_FIXED_SET_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SRC_FIXED_VOLTAGE_Pos) \ + & (USBPD_PDO_SRC_FIXED_VOLTAGE_Msk)) + +/* Set max current in mA in SRC Fixed PDO */ +#define USBPD_PDO_SRC_FIXED_SET_MAX_CURRENT(_MA_) (((PWR_A_10MA((_MA_) / 1000.0)) \ + << USBPD_PDO_SRC_FIXED_MAX_CURRENT_Pos) \ + & (USBPD_PDO_SRC_FIXED_MAX_CURRENT_Msk)) + +/* Set voltage in mV in SNK Fixed PDO */ +#define USBPD_PDO_SNK_FIXED_SET_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SNK_FIXED_VOLTAGE_Pos) \ + & (USBPD_PDO_SNK_FIXED_VOLTAGE_Msk)) + +/* Set operating current in mA in SNK Fixed PDO */ +#define USBPD_PDO_SNK_FIXED_SET_OP_CURRENT(_MA_) (((PWR_A_10MA((_MA_) / 1000.0)) \ + << USBPD_PDO_SNK_FIXED_OP_CURRENT_Pos) \ + & (USBPD_PDO_SNK_FIXED_OP_CURRENT_Msk)) + +/* ---------------------------- VARIABLE ------------------------ */ + +/* Set max voltage in mV in SRC VARIABLE PDO */ +#define USBPD_PDO_SRC_VARIABLE_SET_MAX_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SRC_VARIABLE_MAX_VOLTAGE_Pos) \ + & (USBPD_PDO_SRC_VARIABLE_MAX_VOLTAGE_Msk)) + +/* Set min voltage in mV in SRC VARIABLE PDO */ +#define USBPD_PDO_SRC_VARIABLE_SET_MIN_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SRC_VARIABLE_MIN_VOLTAGE_Pos) \ + & (USBPD_PDO_SRC_VARIABLE_MIN_VOLTAGE_Msk)) + +/* Set max current in mA in SRC VARIABLE PDO */ +#define USBPD_PDO_SRC_VARIABLE_SET_MAX_CURRENT(_MA_) (((PWR_A_10MA((_MA_) / 1000.0)) \ + << USBPD_PDO_SRC_VARIABLE_MAX_CURRENT_Pos) \ + & (USBPD_PDO_SRC_VARIABLE_MAX_CURRENT_Msk)) + +/* Set max voltage in mV in SNK VARIABLE PDO */ +#define USBPD_PDO_SNK_VARIABLE_SET_MAX_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SNK_VARIABLE_MAX_VOLTAGE_Pos) \ + & (USBPD_PDO_SNK_VARIABLE_MAX_VOLTAGE_Msk)) + +/* Set min voltage in mV in SNK VARIABLE PDO */ +#define USBPD_PDO_SNK_VARIABLE_SET_MIN_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SNK_VARIABLE_MIN_VOLTAGE_Pos) \ + & (USBPD_PDO_SNK_VARIABLE_MIN_VOLTAGE_Msk)) + +/* Set operating current in mA in SNK VARIABLE */ +#define USBPD_PDO_SNK_VARIABLE_SET_OP_CURRENT(_MA_) (((PWR_A_10MA((_MA_) / 1000.0)) \ + << USBPD_PDO_SNK_VARIABLE_OP_CURRENT_Pos) \ + & (USBPD_PDO_SNK_VARIABLE_OP_CURRENT_Msk)) + +/* ---------------------------- BATTERY ------------------------ */ + +/* Set max voltage in mV in SRC BATTERY PDO */ +#define USBPD_PDO_SRC_BATTERY_SET_MAX_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SRC_BATTERY_MAX_VOLTAGE_Pos) \ + & (USBPD_PDO_SRC_BATTERY_MAX_VOLTAGE_Msk)) + +/* Set min voltage in mV in SRC BATTERY PDO */ +#define USBPD_PDO_SRC_BATTERY_SET_MIN_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SRC_BATTERY_MIN_VOLTAGE_Pos) \ + & (USBPD_PDO_SRC_BATTERY_MIN_VOLTAGE_Msk)) + +/* Set max power in mW in SRC BATTERY PDO */ +#define USBPD_PDO_SRC_BATTERY_SET_MAX_POWER(_MA_) (((PWR_W((_MA_) / 1000.0)) \ + << USBPD_PDO_SRC_BATTERY_MAX_POWER_Pos) \ + & (USBPD_PDO_SRC_BATTERY_MAX_POWER_Msk)) + +/* Set max voltage in mV in SNK BATTERY PDO */ +#define USBPD_PDO_SNK_BATTERY_SET_MAX_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SNK_BATTERY_MAX_VOLTAGE_Pos) \ + & (USBPD_PDO_SNK_BATTERY_MAX_VOLTAGE_Msk)) + +/* Set min voltage in mV in SNK BATTERY PDO */ +#define USBPD_PDO_SNK_BATTERY_SET_MIN_VOLTAGE(_MV_) (((PWR_V_50MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SNK_BATTERY_MIN_VOLTAGE_Pos) \ + & (USBPD_PDO_SNK_BATTERY_MIN_VOLTAGE_Msk)) + +/* Set operating power in mW in SNK BATTERY PDO */ +#define USBPD_PDO_SNK_BATTERY_SET_OP_POWER(_MA_) (((PWR_W((_MA_) / 1000.0)) \ + << USBPD_PDO_SNK_BATTERY_OP_POWER_Pos) \ + & (USBPD_PDO_SNK_BATTERY_OP_POWER_Msk)) + +/* ---------------------------- APDO ---------------------------- */ + +/* Set min voltage in mV in SRC APDO */ +#define USBPD_PDO_SRC_APDO_SET_MIN_VOLTAGE(_MV_) (((PWR_V_100MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SRC_APDO_MIN_VOLTAGE_Pos) \ + & (USBPD_PDO_SRC_APDO_MIN_VOLTAGE_Msk)) + +/* Set max voltage in mV in SRC APDO */ +#define USBPD_PDO_SRC_APDO_SET_MAX_VOLTAGE(_MV_) (((PWR_V_100MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SRC_APDO_MAX_VOLTAGE_Pos) \ + & (USBPD_PDO_SRC_APDO_MAX_VOLTAGE_Msk)) + +/* Set max current in mA in SRC APDO */ +#define USBPD_PDO_SRC_APDO_SET_MAX_CURRENT(_MA_) (((PWR_A_50MA((_MA_) / 1000.0)) \ + << USBPD_PDO_SRC_APDO_MAX_CURRENT_Pos) \ + & (USBPD_PDO_SRC_APDO_MAX_CURRENT_Msk)) + +/* Set min voltage in mV in SNK APDO */ +#define USBPD_PDO_SNK_APDO_SET_MIN_VOLTAGE(_MV_) (((PWR_V_100MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SNK_APDO_MIN_VOLTAGE_Pos) \ + & (USBPD_PDO_SNK_APDO_MIN_VOLTAGE_Msk)) + +/* Set max voltage in mV in SNK APDO */ +#define USBPD_PDO_SNK_APDO_SET_MAX_VOLTAGE(_MV_) (((PWR_V_100MV((_MV_) / 1000.0)) \ + << USBPD_PDO_SNK_APDO_MAX_VOLTAGE_Pos) \ + & (USBPD_PDO_SNK_APDO_MAX_VOLTAGE_Msk)) + +/* Set max current in mA in SNK APDO */ +#define USBPD_PDO_SNK_APDO_SET_MAX_CURRENT(_MA_) (((PWR_A_50MA((_MA_) / 1000.0)) \ + << USBPD_PDO_SNK_APDO_MAX_CURRENT_Pos) \ + & (USBPD_PDO_SNK_APDO_MAX_CURRENT_Msk)) + +#define USBPD_PORT_IsValid(__Port__) ((__Port__) < (USBPD_PORT_COUNT)) + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/* USER CODE BEGIN variables */ + +/* USER CODE END variables */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup STM32_USBPD_APPLICATION_POWER_IF_Exported_Functions USBPD PWR IF Exported Functions + * @{ + */ +/** + * @brief Initialize structures and variables related to power board profiles + * used by Sink and Source, for all available ports. + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_Init(void); + +/** + * @brief Sets the required power profile + * @param PortNum Port number + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_SetProfile(uint8_t PortNum); + +/** + * @brief Checks if the power on a specified port is ready + * @param PortNum Port number + * @param Vsafe Vsafe status based on @ref USBPD_VSAFE_StatusTypeDef + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_SupplyReady(uint8_t PortNum, USBPD_VSAFE_StatusTypeDef Vsafe); + +/** + * @brief Enable VBUS power on a specified port + * @param PortNum Port number + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_VBUSEnable(uint8_t PortNum); + +/** + * @brief Disable VBUS power on a specified port + * @param PortNum Port number + * @retval USBPD status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_VBUSDisable(uint8_t PortNum); + +/** + * @brief Checks if the power on a specified port is enabled + * @param PortNum Port number + * @retval ENABLE or DISABLE + */ +USBPD_FunctionalState USBPD_PWR_IF_VBUSIsEnabled(uint8_t PortNum); + +/** + * @brief Reads the voltage and the current on a specified port + * @param PortNum Port number + * @param pVoltage The Voltage in mV + * @param pCurrent The Current in mA + * @retval ENABLE or DISABLE + */ +USBPD_StatusTypeDef USBPD_PWR_IF_ReadVA(uint8_t PortNum, uint16_t *pVoltage, uint16_t *pCurrent); + +/** + * @brief Enables the VConn on the port. + * @param PortNum Port number + * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_Enable_VConn(uint8_t PortNum, CCxPin_TypeDef CC); + +/** + * @brief Disable the VConn on the port. + * @param PortNum Port number + * @param CC Specifies the CCx to be selected based on @ref CCxPin_TypeDef structure + * @retval USBPD Status + */ +USBPD_StatusTypeDef USBPD_PWR_IF_Disable_VConn(uint8_t PortNum, CCxPin_TypeDef CC); + +/** + * @brief Allow PDO data reading from PWR_IF storage. + * @param PortNum Port number + * @param DataId Type of data to be read from PWR_IF + * This parameter can be one of the following values: + * @arg @ref USBPD_CORE_DATATYPE_SRC_PDO Source PDO reading requested + * @arg @ref USBPD_CORE_DATATYPE_SNK_PDO Sink PDO reading requested + * @param Ptr Pointer on address where PDO values should be written (u8 pointer) + * @param Size Pointer on nb of u32 written by PWR_IF (nb of PDOs) + * @retval None + */ +void USBPD_PWR_IF_GetPortPDOs(uint8_t PortNum, USBPD_CORE_DataInfoType_TypeDef DataId, uint8_t *Ptr, uint32_t *Size); + +/** + * @brief Find out SRC PDO pointed out by a position provided in a Request DO (from Sink). + * @param PortNum Port number + * @param RdoPosition RDO Position in list of provided PDO + * @param Pdo Pointer on PDO value pointed out by RDO position (u32 pointer) + * @retval Status of search + * USBPD_OK : Src PDO found for requested DO position (output Pdo parameter is set) + * USBPD_FAIL : Position is not compliant with current Src PDO for this port (no corresponding PDO value) + */ +USBPD_StatusTypeDef USBPD_PWR_IF_SearchRequestedPDO(uint8_t PortNum, uint32_t RdoPosition, uint32_t *Pdo); + +/** + * @brief Function called in case of critical issue is detected to switch in safety mode. + * @param ErrorType Type of error detected by monitoring (based on @ref USBPD_PWR_IF_ERROR) + * @retval None + */ +void USBPD_PWR_IF_AlarmType(USBPD_PWR_IF_ERROR ErrorType); + +/** + * @brief Function called in case of critical issue is detected to switch in safety mode. + * @retval None + */ +void USBPD_PWR_IF_Alarm(void); + +/** + * @brief Function is called to get VBUS power status. + * @param PortNum Port number + * @param PowerTypeStatus Power type status based on @ref USBPD_VBUSPOWER_STATUS + * @retval UBBPD_TRUE or USBPD_FALSE + */ +uint8_t USBPD_PWR_IF_GetVBUSStatus(uint8_t PortNum, USBPD_VBUSPOWER_STATUS PowerTypeStatus); + +/** + * @brief Function is called to set the VBUS threshold when a request has been accepted. + * @param PortNum Port number + * @retval None + */ +void USBPD_PWR_IF_UpdateVbusThreshold(uint8_t PortNum); + +/** + * @brief Function is called to reset the VBUS threshold when there is a power reset. + * @param PortNum Port number + * @retval None + */ +void USBPD_PWR_IF_ResetVbusThreshold(uint8_t PortNum); + +/* USER CODE BEGIN Exported Functions */ + +/* USER CODE END Exported Functions */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_PW_IF_H_ */ + diff --git a/USBPD/usbpd_pwr_user.c b/USBPD/usbpd_pwr_user.c new file mode 100644 index 0000000..6d687c2 --- /dev/null +++ b/USBPD/usbpd_pwr_user.c @@ -0,0 +1,802 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_pwr_user.c + * @author MCD Application Team + * @brief USBPD PWR user code + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_pwr_user.h" +#include "stm32g4xx_hal.h" +#if defined(_TRACE) +#include "usbpd_core.h" +#include "usbpd_trace.h" +#endif /* _TRACE */ + +/* USER CODE BEGIN include */ + +/* USER CODE END include */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup POWER + * @{ + */ +/** @defgroup POWER_Private_Typedef Private Typedef + * @{ + */ +/* USER CODE BEGIN POWER_Private_Typedef */ + +/* USER CODE END POWER_Private_Typedef */ +/** + * @} + */ + +/** @defgroup POWER_Private_Constants Private Constants +* @{ +*/ +/* USER CODE BEGIN POWER_Private_Constants */ +#define TCPP_EN_GPIO_Port GPIOA +#define TCPP_EN_Pin GPIO_PIN_9 +/* USER CODE END POWER_Private_Constants */ +/** + * @} + */ + +/** @defgroup POWER_Private_Macros Private Macros + * @{ + */ +#if defined(_TRACE) +#define PWR_DEBUG_TRACE(_PORT_, __MESSAGE__) USBPD_TRACE_Add(USBPD_TRACE_DEBUG, (_PORT_), 0u, (uint8_t*)(__MESSAGE__), sizeof(__MESSAGE__) - 1u) +#else +#define PWR_DEBUG_TRACE(_PORT_, __MESSAGE__) +#endif /* _TRACE */ +/* USER CODE BEGIN POWER_Private_Macros */ + +/* USER CODE END POWER_Private_Macros */ +/** + * @} + */ + +/** @defgroup POWER_Private_Variables Private Variables + * @{ + */ +/* USER CODE BEGIN POWER_Private_Variables */ + +/* USER CODE END POWER_Private_Variables */ +/** + * @} + */ + +/** @defgroup POWER_Private_Functions Private Functions + * @{ + */ +/* USER CODE BEGIN POWER_Private_Prototypes */ + +/* USER CODE END POWER_Private_Prototypes */ +/** + * @} + */ + +/** @defgroup POWER_Exported_Variables Exported Variables + * @{ + */ +/* USER CODE BEGIN POWER_Exported_Variables */ + +/* USER CODE END POWER_Exported_Variables */ +/** + * @} + */ + +/** @addtogroup POWER_Exported_Functions + * @{ + */ +/** + * @brief Global initialization of PWR resource used by USB-PD + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_Init(uint32_t Instance) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_Init */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_Init */ +} + +/** + * @brief Global de-initialization of PWR resource used by USB-PD + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_Deinit(uint32_t Instance) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_Deinit */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_Deinit"); + } + + return ret; + /* USER CODE END BSP_USBPD_PWR_Deinit */ +} + +/** + * @brief Assign Power role for current Port (Source or Sink) + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param Role Type-C port role + * This parameter can be take one of the following values: + * @arg @ref POWER_ROLE_SOURCE + * @arg @ref POWER_ROLE_SINK + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_SetRole(uint32_t Instance, USBPD_PWR_PowerRoleTypeDef Role) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_SetRole */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_SetRole"); + } + + return ret; + /* USER CODE END BSP_USBPD_PWR_SetRole */ +} + +/** + * @brief Set operating mode of Port regarding power saving constraints + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param PwrMode Type-C port power saving mode + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_MODE_OFF + * @arg @ref USBPD_PWR_MODE_HIBERNATE + * @arg @ref USBPD_PWR_MODE_LOWPOWER + * @arg @ref USBPD_PWR_MODE_NORMAL + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_SetPowerMode(uint32_t Instance, USBPD_PWR_PowerModeTypeDef PwrMode) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_SetPowerMode */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_SetPowerMode"); + } + + return ret; + /* USER CODE END BSP_USBPD_PWR_SetPowerMode */ +} + +/** + * @brief Get operating mode of Port regarding power saving constraints + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param PwrMode Pointer on current Type-C port power saving mode value + * Following values are available : + * @arg @ref USBPD_PWR_MODE_OFF + * @arg @ref USBPD_PWR_MODE_HIBERNATE + * @arg @ref USBPD_PWR_MODE_LOWPOWER + * @arg @ref USBPD_PWR_MODE_NORMAL + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_GetPowerMode(uint32_t Instance, USBPD_PWR_PowerModeTypeDef *PwrMode) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_GetPowerMode */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_GetPowerMode"); + } + return ret; + /* USER CODE END BSP_USBPD_PWR_GetPowerMode */ +} + +/** + * @brief Initialize the hardware resources used by the Type-C power delivery (PD) + * controller. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSInit(uint32_t Instance) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSInit */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_VBUSInit"); + } + + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSInit */ +} + +/** + * @brief Release the hardware resources used by the Type-C power delivery (PD) + * controller. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSDeInit(uint32_t Instance) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSDeInit */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSDeInit */ +} + +/** + * @brief Enable power supply over VBUS. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSOn(uint32_t Instance) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSOn */ + /* Check if instance is valid */ + int32_t ret; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_WritePin(TCPP_EN_GPIO_Port, TCPP_EN_Pin, GPIO_PIN_SET); + return BSP_ERROR_NONE; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSOn */ +} + +/** + * @brief Disable power supply over VBUS. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSOff(uint32_t Instance) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSOff */ + /* Check if instance is valid */ + int32_t ret; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + HAL_GPIO_WritePin(TCPP_EN_GPIO_Port, TCPP_EN_Pin, GPIO_PIN_RESET); + return BSP_ERROR_NONE; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSOff */ +} + +/** + * @brief Set a fixed/variable PDO and manage the power control. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param VbusTargetInmv the vbus Target (in mV) + * @param OperatingCurrent the Operating Current (in mA) + * @param MaxOperatingCurrent the Max Operating Current (in mA) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSSetVoltage_Fixed(uint32_t Instance, + uint32_t VbusTargetInmv, + uint32_t OperatingCurrent, + uint32_t MaxOperatingCurrent) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSSetVoltage_Fixed */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSSetVoltage_Fixed */ +} + +/** + * @brief Set a fixed/variable PDO and manage the power control. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param VbusTargetMinInmv the vbus Target min (in mV) + * @param VbusTargetMaxInmv the vbus Target max (in mV) + * @param OperatingCurrent the Operating Current (in mA) + * @param MaxOperatingCurrent the Max Operating Current (in mA) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSSetVoltage_Variable(uint32_t Instance, + uint32_t VbusTargetMinInmv, + uint32_t VbusTargetMaxInmv, + uint32_t OperatingCurrent, + uint32_t MaxOperatingCurrent) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSSetVoltage_Variable */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSSetVoltage_Variable */ +} + +/** + * @brief Set a Battery PDO and manage the power control. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param VbusTargetMin the vbus Target min (in mV) + * @param VbusTargetMax the vbus Target max (in mV) + * @param OperatingPower the Operating Power (in mW) + * @param MaxOperatingPower the Max Operating Power (in mW) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSSetVoltage_Battery(uint32_t Instance, + uint32_t VbusTargetMin, + uint32_t VbusTargetMax, + uint32_t OperatingPower, + uint32_t MaxOperatingPower) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSSetVoltage_Battery */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSSetVoltage_Battery */ +} + +/** + * @brief Set a APDO and manage the power control. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param VbusTargetInmv the vbus Target (in mV) + * @param OperatingCurrent the Operating current (in mA) + * @param Delta Delta between with previous APDO (in mV), 0 means APDO start + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSSetVoltage_APDO(uint32_t Instance, + uint32_t VbusTargetInmv, + uint32_t OperatingCurrent, + int32_t Delta) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSSetVoltage_APDO */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSSetVoltage_APDO */ +} + +/** + * @brief Get actual voltage level measured on the VBUS line. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param pVoltage Pointer on measured voltage level (in mV) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSGetVoltage(uint32_t Instance, uint32_t *pVoltage) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSGetVoltage */ + /* Check if instance is valid */ + int32_t ret; + uint32_t val = 0U; + + if ((Instance >= USBPD_PWR_INSTANCES_NBR) || (NULL == pVoltage)) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_VBUSGetVoltage"); + } + *pVoltage = val; + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSGetVoltage */ +} + +/** + * @brief Get actual current level measured on the VBUS line. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param pCurrent Pointer on measured current level (in mA) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSGetCurrent(uint32_t Instance, int32_t *pCurrent) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSGetCurrent */ + /* Check if instance is valid */ + int32_t ret; + + if ((Instance >= USBPD_PWR_INSTANCES_NBR) || (NULL == pCurrent)) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + *pCurrent = 0; + ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSGetCurrent */ +} + +/** + * @brief Initialize VCONN sourcing. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param CCPinId Type-C CC pin identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_CC1 + * @arg @ref USBPD_PWR_TYPE_C_CC2 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VCONNInit(uint32_t Instance, + uint32_t CCPinId) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VCONNInit */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VCONNInit */ +} + +/** + * @brief Un-Initialize VCONN sourcing. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param CCPinId Type-C CC pin identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_CC1 + * @arg @ref USBPD_PWR_TYPE_C_CC2 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VCONNDeInit(uint32_t Instance, + uint32_t CCPinId) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VCONNDeInit */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VCONNDeInit */ +} + +/** + * @brief Enable VCONN sourcing. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param CCPinId Type-C CC pin identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_CC1 + * @arg @ref USBPD_PWR_TYPE_C_CC2 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VCONNOn(uint32_t Instance, + uint32_t CCPinId) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VCONNOn */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VCONNOn */ +} + +/** + * @brief Disable VCONN sourcing. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param CCPinId CC pin identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_CC1 + * @arg @ref USBPD_PWR_TYPE_C_CC2 + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VCONNOff(uint32_t Instance, + uint32_t CCPinId) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VCONNOff */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VCONNOff */ +} + +/** + * @brief Get actual VCONN status. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param CCPinId Type-C CC pin identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_CC1 + * @arg @ref USBPD_PWR_TYPE_C_CC2 + * @param pState VCONN status (1: On, 0: Off) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VCONNIsOn(uint32_t Instance, + uint32_t CCPinId, uint8_t *pState) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VCONNIsOn */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + *pState = 0u; + return ret; + /* USER CODE END BSP_USBPD_PWR_VCONNIsOn */ +} + +/** + * @brief Set the VBUS disconnection voltage threshold. + * @note Callback function registered through BSP_USBPD_PWR_RegisterVBUSDetectCallback + * function call is invoked when VBUS falls below programmed threshold. + * @note By default VBUS disconnection threshold is set to 3.3V + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param VoltageThreshold VBUS disconnection voltage threshold (in mV) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_SetVBUSDisconnectionThreshold(uint32_t Instance, + uint32_t VoltageThreshold) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_SetVBUSDisconnectionThreshold */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_SetVBUSDisconnectionThreshold */ +} + +/** + * @brief Register USB Type-C Current callback function. + * @note Callback function invoked when VBUS rises above 4V (VBUS present) or + * when VBUS falls below programmed threshold (VBUS absent). + * @note Callback function is un-registered when callback function pointer + * argument is NULL. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param pfnVBUSDetectCallback callback function pointer + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_RegisterVBUSDetectCallback(uint32_t Instance, + USBPD_PWR_VBUSDetectCallbackFunc *pfnVBUSDetectCallback) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_RegisterVBUSDetectCallback */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + return ret; + /* USER CODE END BSP_USBPD_PWR_RegisterVBUSDetectCallback */ +} + +/** + * @brief Get actual VBUS status. + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param pState VBUS status (1: On, 0: Off) + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VBUSIsOn(uint32_t Instance, uint8_t *pState) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VBUSIsOn */ + /* Check if instance is valid */ + int32_t ret; + uint8_t state = 0U; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_VBUSIsOn"); + } + *pState = state; + return ret; + /* USER CODE END BSP_USBPD_PWR_VBUSIsOn */ +} + +/** + * @brief Set state of VCC (specific functions) + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @param State VCC state + * @retval BSP status + */ +__weak int32_t BSP_USBPD_PWR_VCCSetState(uint32_t Instance, uint32_t State) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_VCCSetState */ + /* Check if instance is valid */ + int32_t ret = BSP_ERROR_NONE; + + if (Instance >= USBPD_PWR_INSTANCES_NBR) + { + ret = BSP_ERROR_WRONG_PARAM; + } + else + { + ret = BSP_ERROR_FEATURE_NOT_SUPPORTED; + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_VCCSetState"); + } + return ret; + /* USER CODE END BSP_USBPD_PWR_VCCSetState */ +} + +/** + * @brief USBPD PWR callback used to notify a asynchronous PWR event. + * (This callback caould be called fromp an IT routine, associated to + * any PWR related event detection mechanism) + * @param Instance Type-C port identifier + * This parameter can be take one of the following values: + * @arg @ref USBPD_PWR_TYPE_C_PORT_1 + * @retval None + */ +__weak void BSP_USBPD_PWR_EventCallback(uint32_t Instance) +{ + /* USER CODE BEGIN BSP_USBPD_PWR_EventCallback */ + PWR_DEBUG_TRACE(Instance, "ADVICE: Update BSP_USBPD_PWR_EventCallback"); + /* USER CODE END BSP_USBPD_PWR_EventCallback */ +} + +/** + * @} + */ + +/** @addtogroup POWER_Private_Functions + * @{ + */ + +/* USER CODE BEGIN POWER_Private_Functions */ + +/* USER CODE END POWER_Private_Functions */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/USBPD/usbpd_pwr_user.h b/USBPD/usbpd_pwr_user.h new file mode 100644 index 0000000..4dca209 --- /dev/null +++ b/USBPD/usbpd_pwr_user.h @@ -0,0 +1,269 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_pwr_user.h + * @author MCD Application Team + * @brief Header file for usbpd_pwr_user.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef USBPD_PWR_USER_H_ +#define USBPD_PWR_USER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup POWER + * @{ + */ + +/** @defgroup POWER_Exported_Types Exported Types + * @{ + */ + +/** + * @brief Power role + */ +typedef enum +{ + POWER_ROLE_SOURCE = 0, + POWER_ROLE_SINK, + POWER_ROLE_DUAL +} USBPD_PWR_PowerRoleTypeDef; + +/** + * @brief Voltage control mode + */ +typedef enum +{ + DCDC_CTRL_MODE_UNKNOWN = 0, + DCDC_CTRL_MODE_GPIO, + DCDC_CTRL_MODE_PWM, +} USBPD_PWR_DCDCCtrlModeTypeDef; + +/** + * @brief Low Power Mode of TypeC ports + */ +typedef enum +{ + USBPD_PWR_MODE_OFF = 0, + USBPD_PWR_MODE_HIBERNATE, + USBPD_PWR_MODE_LOWPOWER, + USBPD_PWR_MODE_NORMAL +} USBPD_PWR_PowerModeTypeDef; + +/** + * @brief VBUS connection status + */ +typedef enum +{ + VBUS_CONNECTED = 0, + VBUS_NOT_CONNECTED +} USBPD_PWR_VBUSConnectionStatusTypeDef; + +/** + * @brief VBUS Detection Callback + */ +typedef void USBPD_PWR_VBUSDetectCallbackFunc(uint32_t Instance, + USBPD_PWR_VBUSConnectionStatusTypeDef VBUSConnectionStatus); + +/** + * @} + */ + +/** @defgroup POWER_Exported_Constants Exported Constants + * @{ + */ +/* Common Error codes */ +#define BSP_ERROR_NONE 0 +#define BSP_ERROR_NO_INIT -1 +#define BSP_ERROR_WRONG_PARAM -2 +#define BSP_ERROR_BUSY -3 +#define BSP_ERROR_PERIPH_FAILURE -4 +#define BSP_ERROR_COMPONENT_FAILURE -5 +#define BSP_ERROR_UNKNOWN_FAILURE -6 +#define BSP_ERROR_UNKNOWN_COMPONENT -7 +#define BSP_ERROR_BUS_FAILURE -8 +#define BSP_ERROR_CLOCK_FAILURE -9 +#define BSP_ERROR_MSP_FAILURE -10 +#define BSP_ERROR_FEATURE_NOT_SUPPORTED -11 + +/** + * @brief Number of TypeC ports + */ +#define USBPD_PWR_INSTANCES_NBR (1U) + +/** + * @brief Type-C port identifier + */ +#define USBPD_PWR_TYPE_C_PORT_1 (0U) + +/** + * @brief CC pin identifier + */ +#define USBPD_PWR_TYPE_C_CC1 (1U) +#define USBPD_PWR_TYPE_C_CC2 (2U) + +/** + * @brief VBUS disconnection threshold values (in mV) + */ +#define USBPD_PWR_HIGH_VBUS_THRESHOLD (2800U) +#define USBPD_PWR_LOW_VBUS_THRESHOLD (750U) +#define USBPD_PWR_VBUS_THRESHOLD_5V (2150U) +#define USBPD_PWR_VBUS_THRESHOLD_9V (7000U) +#define USBPD_PWR_VBUS_THRESHOLD_15V (12500U) +#define USBPD_PWR_VBUS_THRESHOLD_20V (17000U) +#define USBPD_PWR_VBUS_THRESHOLD_APDO (2150U) + +/** + * @brief VBUS discharge parameters + */ +#define USBPD_PWR_DISCHARGE_MARGIN (500U) +#define USBPD_PWR_DISCHARGE_TIME (6U) + +/** + * @brief Calibration settings + */ +#define USBPD_PWR_DCDC_PRECISION (40U) /* DCDC output precision set to 40mV (Noise)*/ +#define USBPD_PWR_CALIBRATION_ENABLED (1U) +#define USBPD_PWR_CALIBRATION_DISABLED (0U) + +/** + * @brief Standard VBUS voltage levels + */ +#define USBPD_PWR_VBUS_5V 5000U +#define USBPD_PWR_VBUS_9V 9000U +#define USBPD_PWR_VBUS_15V 15000U + +/** + * @brief power timeout + */ +#define USBPD_PWR_TIMEOUT_PDO 250U /* Timeout for PDO to PDO or PDO to APDO at 250ms*/ +#define USBPD_PWR_TIMEOUT_APDO 25U /* Timeout for APDO to APDO at 25ms*/ + +/** + * @brief Invalid value set during issue with voltage setting + */ +#define USBPD_PWR_INVALID_VALUE 0xFFFFFFFFU + +/** + * @} + */ + +/** @defgroup POWER_Exported_Functions Exported Functions + * @{ + */ +/* Common functions */ +int32_t BSP_USBPD_PWR_Init(uint32_t Instance); + +int32_t BSP_USBPD_PWR_Deinit(uint32_t Instance); + +int32_t BSP_USBPD_PWR_SetRole(uint32_t Instance, USBPD_PWR_PowerRoleTypeDef Role); + +int32_t BSP_USBPD_PWR_SetPowerMode(uint32_t Instance, USBPD_PWR_PowerModeTypeDef PwrMode); + +int32_t BSP_USBPD_PWR_GetPowerMode(uint32_t Instance, USBPD_PWR_PowerModeTypeDef *PwrMode); + +int32_t BSP_USBPD_PWR_VBUSInit(uint32_t Instance); + +int32_t BSP_USBPD_PWR_VBUSDeInit(uint32_t Instance); + +int32_t BSP_USBPD_PWR_VBUSOn(uint32_t Instance); + +int32_t BSP_USBPD_PWR_VBUSOff(uint32_t Instance); + +int32_t BSP_USBPD_PWR_VBUSSetVoltage_Fixed(uint32_t Instance, + uint32_t VbusTargetInmv, + uint32_t OperatingCurrent, + uint32_t MaxOperatingCurrent); + +int32_t BSP_USBPD_PWR_VBUSSetVoltage_Variable(uint32_t Instance, + uint32_t VbusTargetMaxInmv, + uint32_t VbusTargetMinInmv, + uint32_t OperatingCurrent, + uint32_t MaxOperatingCurrent); + +int32_t BSP_USBPD_PWR_VBUSSetVoltage_Battery(uint32_t Instance, + uint32_t VbusTargetMin, + uint32_t VbusTargetMax, + uint32_t OperatingPower, + uint32_t MaxOperatingPower); + +int32_t BSP_USBPD_PWR_VBUSSetVoltage_APDO(uint32_t Instance, + uint32_t VbusTargetInmv, + uint32_t OperatingCurrent, + int32_t Delta); + +int32_t BSP_USBPD_PWR_VBUSGetVoltage(uint32_t Instance, uint32_t *pVoltage); + +int32_t BSP_USBPD_PWR_VBUSGetCurrent(uint32_t Instance, int32_t *pCurrent); + +int32_t BSP_USBPD_PWR_VCONNInit(uint32_t Instance, + uint32_t CCPinId); + +int32_t BSP_USBPD_PWR_VCONNDeInit(uint32_t Instance, + uint32_t CCPinId); + +int32_t BSP_USBPD_PWR_VCONNOn(uint32_t Instance, + uint32_t CCPinId); + +int32_t BSP_USBPD_PWR_VCONNOff(uint32_t Instance, + uint32_t CCPinId); + +int32_t BSP_USBPD_PWR_SetVBUSDisconnectionThreshold(uint32_t Instance, + uint32_t VoltageThreshold); + +int32_t BSP_USBPD_PWR_RegisterVBUSDetectCallback(uint32_t Instance, + USBPD_PWR_VBUSDetectCallbackFunc *pfnVBUSDetectCallback); + +int32_t BSP_USBPD_PWR_VBUSIsOn(uint32_t Instance, uint8_t *pState); + +int32_t BSP_USBPD_PWR_VCONNIsOn(uint32_t Instance, + uint32_t CCPinId, uint8_t *pState); + +int32_t BSP_USBPD_PWR_VCCSetState(uint32_t Instance, uint32_t State); + +void BSP_USBPD_PWR_EventCallback(uint32_t Instance); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* USBPD_PWR_USER_H_ */ + diff --git a/USBPD/usbpd_vdm_user.c b/USBPD/usbpd_vdm_user.c new file mode 100644 index 0000000..b79a41c --- /dev/null +++ b/USBPD/usbpd_vdm_user.c @@ -0,0 +1,488 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_vdm_user.c + * @author MCD Application Team + * @brief USBPD provider demo file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbpd_core.h" +#include "usbpd_dpm_conf.h" +#include "usbpd_vdm_user.h" +#include "usbpd_dpm_user.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/** @addtogroup STM32_USBPD_APPLICATION + * @{ + */ + +/** @addtogroup STM32_USBPD_APPLICATION_VDM_USER + * @{ + */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Private_define */ + +/* USER CODE END Private_define */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN Private_typedef */ + +/* USER CODE END Private_typedef */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Private_macro */ + +/* USER CODE END Private_macro */ + +/* Private function prototypes -----------------------------------------------*/ +static USBPD_StatusTypeDef USBPD_VDM_DiscoverIdentity(uint8_t PortNum, USBPD_DiscoveryIdentity_TypeDef *pIdentity); +static USBPD_StatusTypeDef USBPD_VDM_DiscoverSVIDs(uint8_t PortNum, uint16_t **p_SVID_Info, uint8_t *nb); +static USBPD_StatusTypeDef USBPD_VDM_DiscoverModes(uint8_t PortNum, uint16_t SVID, uint32_t **p_ModeInfo, uint8_t *nbMode); +static USBPD_StatusTypeDef USBPD_VDM_ModeEnter(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); +static USBPD_StatusTypeDef USBPD_VDM_ModeExit(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex); +static void USBPD_VDM_SendAttention(uint8_t PortNum, uint8_t *NbData, uint32_t *VDO); +static void USBPD_VDM_ReceiveAttention(uint8_t PortNum, uint8_t NbData, uint32_t VDO); +static USBPD_StatusTypeDef USBPD_VDM_ReceiveSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *NbData, uint32_t *VDO); +static void USBPD_VDM_InformIdentity(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_DiscoveryIdentity_TypeDef *pIdentity); +static void USBPD_VDM_InformSVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_SVIDInfo_TypeDef *pListSVID); +static void USBPD_VDM_InformMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_ModeInfo_TypeDef *pModesInfo); +static void USBPD_VDM_InformModeEnter(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); +static void USBPD_VDM_InformModeExit(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex); +static void USBPD_VDM_InformSpecific(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *NbData, uint32_t *VDO); +static void USBPD_VDM_SendSpecific(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *NbData, uint32_t *VDO); +static void USBPD_VDM_SendUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef *pUVDM_Header, uint8_t *pNbData, uint32_t *pVDO); +static USBPD_StatusTypeDef USBPD_VDM_ReceiveUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef UVDM_Header, uint8_t *pNbData, uint32_t *pVDO); + +/* USER CODE BEGIN Private_prototypes */ + +/* USER CODE END Private_prototypes */ + +/* Private variables ---------------------------------------------------------*/ +USBPD_VDM_SettingsTypeDef DPM_VDM_Settings[USBPD_PORT_COUNT] = +{ + { + .VDM_XID_SOP = USBPD_XID, /*!< A decimal number assigned by USB-IF before certification */ + .VDM_USB_VID_SOP = USBPD_VID, /*!< A decimal number assigned by USB-IF before certification */ + .VDM_PID_SOP = USBPD_PID, /*!< A unique number assigned by the Vendor ID holder identifying the product. */ + .VDM_ModalOperation = MODAL_OPERATION_NONSUPP, /*!< Product support Modes based on @ref USBPD_ModalOp_TypeDef */ + .VDM_bcdDevice_SOP = 0xAAAA, /*!< A unique number assigned by the Vendor ID holder containing identity information relevant to the release version of the product. */ + .VDM_USBHostSupport = USB_NOTCAPABLE, /*!< Indicates whether the UUT is capable of enumerating USB Host */ + .VDM_USBDeviceSupport = USB_NOTCAPABLE, /*!< Indicates whether the UUT is capable of enumerating USB Devices */ + .VDM_ProductTypeUFPorCP = PRODUCT_TYPE_UNDEFINED, /*!< Product type UFP or CablePlug of the UUT based on @ref USBPD_ProductType_TypeDef */ + } +}; + +/* USER CODE BEGIN Private_variables */ +const USBPD_VDM_Callbacks vdmCallbacks = +{ + USBPD_VDM_DiscoverIdentity, + USBPD_VDM_DiscoverSVIDs, + USBPD_VDM_DiscoverModes, + USBPD_VDM_ModeEnter, + USBPD_VDM_ModeExit, + USBPD_VDM_InformIdentity, + USBPD_VDM_InformSVID, + USBPD_VDM_InformMode, + USBPD_VDM_InformModeEnter, + USBPD_VDM_InformModeExit, + USBPD_VDM_SendAttention, + USBPD_VDM_ReceiveAttention, + USBPD_VDM_SendSpecific, + USBPD_VDM_ReceiveSpecific, + USBPD_VDM_InformSpecific, + USBPD_VDM_SendUVDM, + USBPD_VDM_ReceiveUVDM, +}; +/* USER CODE END Private_variables */ + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief VDM Discovery identity callback + * @note Function is called to get Discovery identity information linked to the device and answer + * to SVDM Discovery identity init message sent by port partner + * @param PortNum current port number + * @param pIdentity Pointer on @ref USBPD_DiscoveryIdentity_TypeDef structure + * @retval USBPD status: @ref USBPD_ACK or @ref USBPD_BUSY + */ +static USBPD_StatusTypeDef USBPD_VDM_DiscoverIdentity(uint8_t PortNum, USBPD_DiscoveryIdentity_TypeDef *pIdentity) +{ +/* USER CODE BEGIN USBPD_VDM_DiscoverIdentity */ + return USBPD_NAK; +/* USER CODE END USBPD_VDM_DiscoverIdentity */ +} + +/** + * @brief VDM Discover SVID callback + * @note Function is called to retrieve SVID supported by device and answer + * to SVDM Discovery SVID init message sent by port partner + * @param PortNum current port number + * @param p_SVID_Info Pointer on @ref USBPD_SVIDInfo_TypeDef structure + * @param pNbSVID Pointer on number of SVID + * @retval USBPD status @ref USBPD_BUSY or @ref USBPD_ACK or @ref USBPD_NAK + */ +static USBPD_StatusTypeDef USBPD_VDM_DiscoverSVIDs(uint8_t PortNum, uint16_t **p_SVID_Info, uint8_t *pNbSVID) +{ +/* USER CODE BEGIN USBPD_VDM_DiscoverSVIDs */ + return USBPD_NAK; +/* USER CODE END USBPD_VDM_DiscoverSVIDs */ +} + +/** + * @brief VDM Discover Mode callback (report all the modes supported by SVID) + * @note Function is called to report all the modes supported by selected SVID and answer + * to SVDM Discovery Mode init message sent by port partner + * @param PortNum current port number + * @param SVID SVID value + * @param p_ModeTab Pointer on the mode value + * @param NumberOfMode Number of mode available + * @retval USBPD status + */ +static USBPD_StatusTypeDef USBPD_VDM_DiscoverModes(uint8_t PortNum, uint16_t SVID, uint32_t **p_ModeTab, uint8_t *NumberOfMode) +{ +/* USER CODE BEGIN USBPD_VDM_DiscoverModes */ + return USBPD_NAK; +/* USER CODE END USBPD_VDM_DiscoverModes */ +} + +/** + * @brief VDM Mode enter callback + * @note Function is called to check if device can enter in the mode received for the selected SVID in the + * SVDM enter mode init message sent by port partner + * @param PortNum current port number + * @param SVID SVID value + * @param ModeIndex Index of the mode to be entered + * @retval USBPD status @ref USBPD_ACK/@ref USBPD_NAK + */ +static USBPD_StatusTypeDef USBPD_VDM_ModeEnter(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex) +{ +/* USER CODE BEGIN USBPD_VDM_ModeEnter */ + return USBPD_NAK; +/* USER CODE END USBPD_VDM_ModeEnter */ +} + +/** + * @brief VDM Mode exit callback + * @note Function is called to check if device can exit from the mode received for the selected SVID in the + * SVDM exit mode init message sent by port partner + * @param PortNum current port number + * @param SVID SVID value + * @param ModeIndex Index of the mode to be exited + * @retval USBPD status @ref USBPD_ACK/@ref USBPD_NAK + */ +static USBPD_StatusTypeDef USBPD_VDM_ModeExit(uint8_t PortNum, uint16_t SVID, uint32_t ModeIndex) +{ +/* USER CODE BEGIN USBPD_VDM_ModeExit */ + return USBPD_NAK; +/* USER CODE END USBPD_VDM_ModeExit */ +} + +/** + * @brief Send VDM Attention message callback + * @note Function is called when device wants to send a SVDM attention message to port partner + * (for instance DP status can be filled through this function) + * @param PortNum current port number + * @param pNbData Pointer of number of VDO to send + * @param pVDO Pointer of VDO to send + * @retval None + */ +static void USBPD_VDM_SendAttention(uint8_t PortNum, uint8_t *pNbData, uint32_t *pVDO) +{ +/* USER CODE BEGIN USBPD_VDM_SendAttention */ + +/* USER CODE END USBPD_VDM_SendAttention */ +} + +/** + * @brief Receive VDM Attention callback + * @note Function is called when a SVDM attention init message has been received from port partner + * (for instance, save DP status data through this function) + * @param PortNum current port number + * @param NbData Number of received VDO + * @param VDO Received VDO + * @retval None + */ +static void USBPD_VDM_ReceiveAttention(uint8_t PortNum, uint8_t NbData, uint32_t VDO) +{ +/* USER CODE BEGIN USBPD_VDM_ReceiveAttention */ + +/* USER CODE END USBPD_VDM_ReceiveAttention */ +} + +/** + * @brief VDM Receive Specific message callback + * @note Function is called to answer to a SVDM specific init message received by port partner. + * (for instance, retrieve DP status or DP configure data through this function) + * @param PortNum Current port number + * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef + * @param pNbData Pointer of number of received VDO and used for the answer + * @param pVDO Pointer of received VDO and use for the answer + * @retval USBPD Status + */ +static USBPD_StatusTypeDef USBPD_VDM_ReceiveSpecific(uint8_t PortNum, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO) +{ +/* USER CODE BEGIN USBPD_VDM_ReceiveSpecific */ + return USBPD_NAK; +/* USER CODE END USBPD_VDM_ReceiveSpecific */ +} + +/** + * @brief Inform identity callback + * @note Function is called to save Identity information received in Discovery identity from port partner + (answer to SVDM discovery identity sent by device) + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param pIdentity Pointer on the discovery identity information based on @ref USBPD_DiscoveryIdentity_TypeDef + * @retval None +*/ +static void USBPD_VDM_InformIdentity(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_DiscoveryIdentity_TypeDef *pIdentity) +{ +/* USER CODE BEGIN USBPD_VDM_InformIdentity */ + switch(CommandStatus) + { + case SVDM_RESPONDER_ACK : + break; + case SVDM_RESPONDER_NAK : + break; + case SVDM_RESPONDER_BUSY : + break; + default : + break; + } +/* USER CODE END USBPD_VDM_InformIdentity */ +} + +/** + * @brief Inform SVID callback + * @note Function is called to save list of SVID received in Discovery SVID from port partner + (answer to SVDM discovery SVID sent by device) + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param pListSVID Pointer of list of SVID based on @ref USBPD_SVIDInfo_TypeDef + * @retval None + */ +static void USBPD_VDM_InformSVID(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_SVIDInfo_TypeDef *pListSVID) +{ +/* USER CODE BEGIN USBPD_VDM_InformSVID */ + switch(CommandStatus) + { + case SVDM_RESPONDER_ACK : + break; + case SVDM_RESPONDER_NAK : + break; + case SVDM_RESPONDER_BUSY : + break; + default : + break; + } +/* USER CODE END USBPD_VDM_InformSVID */ +} + +/** + * @brief Inform Mode callback ( received in Discovery Modes ACK) + * @note Function is called to save list of modes linked to SVID received in Discovery mode from port partner + (answer to SVDM discovery mode sent by device) + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param pModesInfo Pointer of Modes info based on @ref USBPD_ModeInfo_TypeDef + * @retval None + */ +static void USBPD_VDM_InformMode(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, USBPD_ModeInfo_TypeDef *pModesInfo) +{ +/* USER CODE BEGIN USBPD_VDM_InformMode */ + switch(CommandStatus) + { + case SVDM_RESPONDER_ACK : + break; + case SVDM_RESPONDER_NAK : + break; + case SVDM_RESPONDER_BUSY : + break; + default : + break; + } +/* USER CODE END USBPD_VDM_InformMode */ +} + +/** + * @brief Inform Mode enter callback + * @note Function is called to inform if port partner accepted or not to enter in the mode + * specified in the SVDM enter mode sent by the device + * @param PortNum current port number + * @param SOPType SOP type + * @param CommandStatus Command status based on @ref USBPD_VDM_CommandType_Typedef + * @param SVID SVID ID + * @param ModeIndex Index of the mode to be entered + * @retval None + */ +static void USBPD_VDM_InformModeEnter(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex) +{ +/* USER CODE BEGIN USBPD_VDM_InformModeEnter */ + switch(CommandStatus) + { + case SVDM_RESPONDER_ACK : + break; + case SVDM_RESPONDER_NAK : + break; + case SVDM_RESPONDER_BUSY : + /* retry in 50ms */ + break; + default : + break; + } +/* USER CODE END USBPD_VDM_InformModeEnter */ +} + +/** + * @brief Inform Exit enter callback + * @param PortNum current port number + * @param SVID SVID ID + * @param ModeIndex Index of the mode to be entered + * @retval None + */ +static void USBPD_VDM_InformModeExit(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_CommandType_Typedef CommandStatus, uint16_t SVID, uint32_t ModeIndex) +{ +/* USER CODE BEGIN USBPD_VDM_InformModeExit */ + switch(CommandStatus) + { + case SVDM_RESPONDER_ACK : + break; + case SVDM_RESPONDER_NAK : + break; + case SVDM_RESPONDER_BUSY : + /* retry in 50ms */ + break; + default : + break; + } +/* USER CODE END USBPD_VDM_InformModeExit */ +} + +/** + * @brief VDM Send Specific message callback + * @note Function is called when device wants to send a SVDM specific init message to port partner + * (for instance DP status or DP configure can be filled through this function) + * @param PortNum current port number + * @param SOPType SOP type + * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef + * @param pNbData Pointer of number of VDO to send + * @param pVDO Pointer of VDO to send + * @retval None + */ +static void USBPD_VDM_SendSpecific(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO) +{ +/* USER CODE BEGIN USBPD_VDM_SendSpecific */ + +/* USER CODE END USBPD_VDM_SendSpecific */ +} + +/** + * @brief VDM Specific message callback to inform user of reception of VDM specific message + * @note Function is called when answer from SVDM specific init message has been received by the device + * (for instance, save DP status and DP configure data through this function) + * @param PortNum current port number + * @param SOPType SOP type + * @param VDMCommand VDM command based on @ref USBPD_VDM_Command_Typedef + * @param pNbData Pointer of number of received VDO + * @param pVDO Pointer of received VDO + * @retval None + */ +static void USBPD_VDM_InformSpecific(uint8_t PortNum, USBPD_SOPType_TypeDef SOPType, USBPD_VDM_Command_Typedef VDMCommand, uint8_t *pNbData, uint32_t *pVDO) +{ +/* USER CODE BEGIN USBPD_VDM_InformSpecific */ + +/* USER CODE END USBPD_VDM_InformSpecific */ +} + +/** + * @brief VDM Send Unstructured message callback + * @note Aim of this function is to fill the UVDM message which contains 1 VDM Header + 6 VDO + * This callback will be called when user requests to send a UVDM message thanks + * to USBPD_DPM_RequestUVDMMessage function + * @param PortNum current port number + * @param pUVDM_Header Pointer on UVDM header based on @ref USBPD_UVDMHeader_TypeDef + * @param pNbData Pointer of number of VDO to send (max size must be equal to 6) + * @param pVDO Pointer of VDO to send (up to 6 x uint32_t) + * @retval None + */ +static void USBPD_VDM_SendUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef *pUVDM_Header, uint8_t *pNbData, uint32_t *pVDO) +{ +/* USER CODE BEGIN USBPD_VDM_SendUVDM */ + +/* USER CODE END USBPD_VDM_SendUVDM */ +} + +/** + * @brief Unstructured VDM message callback to inform user of reception of UVDM message + * @param PortNum current port number + * @param UVDM_Header UVDM header based on @ref USBPD_UVDMHeader_TypeDef + * @param pNbData Pointer of number of received VDO + * @param pVDO Pointer of received VDO + * @retval USBPD Status + */ +static USBPD_StatusTypeDef USBPD_VDM_ReceiveUVDM(uint8_t PortNum, USBPD_UVDMHeader_TypeDef UVDM_Header, uint8_t *pNbData, uint32_t *pVDO) +{ +/* USER CODE BEGIN USBPD_VDM_ReceiveUVDM */ + return USBPD_ERROR; +/* USER CODE END USBPD_VDM_ReceiveUVDM */ +} + +/* USER CODE BEGIN Private_functions */ + +/* USER CODE END Private_functions */ + +/* Exported functions ---------------------------------------------------------*/ +/** + * @brief VDM Initialization function + * @param PortNum Index of current used port + * @retval status + */ +USBPD_StatusTypeDef USBPD_VDM_UserInit(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_VDM_UserInit */ + return USBPD_OK; +/* USER CODE END USBPD_VDM_UserInit */ +} + +/** + * @brief VDM Reset function + * @param PortNum Index of current used port + * @retval status + */ +void USBPD_VDM_UserReset(uint8_t PortNum) +{ +/* USER CODE BEGIN USBPD_VDM_UserReset */ + +/* USER CODE END USBPD_VDM_UserReset */ +} + +/* USER CODE BEGIN Exported_functions */ + +/* USER CODE END Exported_functions */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/USBPD/usbpd_vdm_user.h b/USBPD/usbpd_vdm_user.h new file mode 100644 index 0000000..367ac22 --- /dev/null +++ b/USBPD/usbpd_vdm_user.h @@ -0,0 +1,78 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbpd_vdm_user.h + * @author MCD Application Team + * @brief Header file for usbpd_vdm_user.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __USBPD_VDM_USER_H_ +#define __USBPD_VDM_USER_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup STM32_USBPD_APPLICATION + * @{ + */ + +/** @addtogroup STM32_USBPD_APPLICATION_VDM_USER + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ +typedef struct +{ + uint32_t VDM_XID_SOP :32; /*!< A decimal number assigned by USB-IF before certification */ + uint32_t VDM_USB_VID_SOP :16; /*!< A unique 16-bit number, assigned to the Vendor by USB-IF. */ + uint32_t VDM_PID_SOP :16; /*!< A unique number assigned by the Vendor ID holder identifying the product. */ + uint32_t VDM_bcdDevice_SOP :16; /*!< A unique number assigned by the Vendor ID holder containing identity information relevant to the release version of the product. */ + USBPD_ModalOp_TypeDef VDM_ModalOperation : 1; /*!< Product support Modes based on @ref USBPD_ModalOp_TypeDef */ + USBPD_USBCapa_TypeDef VDM_USBHostSupport : 1; /*!< Indicates whether the UUT is capable of enumerating USB Host */ + USBPD_USBCapa_TypeDef VDM_USBDeviceSupport: 1; /*!< Indicates whether the UUT is capable of enumerating USB Devices */ + USBPD_ProductType_TypeDef VDM_ProductTypeUFPorCP : 3; /*!< Product type UFP or CablePlug of the UUT based on @ref USBPD_ProductType_TypeDef */ + USBPD_ProductType_TypeDef VDM_ProductTypeDFP : 3; /*!< Product type DFP of the UUT based on @ref USBPD_ProductType_TypeDef */ + uint32_t Reserved3 : 7; /*!< Reserved bits */ +} USBPD_VDM_SettingsTypeDef; +/* USER CODE BEGIN typedef */ + +/* USER CODE END typedef */ + +/* Exported define -----------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +USBPD_StatusTypeDef USBPD_VDM_UserInit(uint8_t PortNum); +void USBPD_VDM_UserReset(uint8_t PortNum); +/* USER CODE BEGIN Exported functions */ +/* USER CODE END Exported functions */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBPD_VDM_USER_H_ */ + diff --git a/pcb_alim Debug.launch b/pcb_alim Debug.launch index d0ea1b2..c7de6f0 100644 --- a/pcb_alim Debug.launch +++ b/pcb_alim Debug.launch @@ -23,7 +23,7 @@ - + @@ -37,7 +37,7 @@ - + diff --git a/pcb_alim.ioc b/pcb_alim.ioc index 1ed15c8..f1ff6fd 100644 --- a/pcb_alim.ioc +++ b/pcb_alim.ioc @@ -2,6 +2,43 @@ CAD.formats= CAD.pinconfig= CAD.provider= +Dma.Request0=UCPD1_RX +Dma.Request1=UCPD1_TX +Dma.RequestsNb=2 +Dma.UCPD1_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.UCPD1_RX.0.EventEnable=DISABLE +Dma.UCPD1_RX.0.Instance=DMA1_Channel1 +Dma.UCPD1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UCPD1_RX.0.MemInc=DMA_MINC_ENABLE +Dma.UCPD1_RX.0.Mode=DMA_NORMAL +Dma.UCPD1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UCPD1_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.UCPD1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.UCPD1_RX.0.Priority=DMA_PRIORITY_LOW +Dma.UCPD1_RX.0.RequestNumber=1 +Dma.UCPD1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.UCPD1_RX.0.SignalID=NONE +Dma.UCPD1_RX.0.SyncEnable=DISABLE +Dma.UCPD1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.UCPD1_RX.0.SyncRequestNumber=1 +Dma.UCPD1_RX.0.SyncSignalID=NONE +Dma.UCPD1_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.UCPD1_TX.1.EventEnable=DISABLE +Dma.UCPD1_TX.1.Instance=DMA1_Channel2 +Dma.UCPD1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.UCPD1_TX.1.MemInc=DMA_MINC_ENABLE +Dma.UCPD1_TX.1.Mode=DMA_NORMAL +Dma.UCPD1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.UCPD1_TX.1.PeriphInc=DMA_PINC_DISABLE +Dma.UCPD1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.UCPD1_TX.1.Priority=DMA_PRIORITY_LOW +Dma.UCPD1_TX.1.RequestNumber=1 +Dma.UCPD1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.UCPD1_TX.1.SignalID=NONE +Dma.UCPD1_TX.1.SyncEnable=DISABLE +Dma.UCPD1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.UCPD1_TX.1.SyncRequestNumber=1 +Dma.UCPD1_TX.1.SyncSignalID=NONE File.Version=6 GPIO.groupedBy=Group By Peripherals I2C1.IPParameters=Timing @@ -9,35 +46,50 @@ I2C1.Timing=0x10C18DCC KeepUserPlacement=false Mcu.CPN=STM32G491KEU6 Mcu.Family=STM32G4 -Mcu.IP0=I2C1 -Mcu.IP1=NVIC -Mcu.IP2=RCC -Mcu.IP3=SYS -Mcu.IP4=TIM3 -Mcu.IP5=USART2 -Mcu.IPNb=6 +Mcu.IP0=DMA +Mcu.IP1=I2C1 +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SYS +Mcu.IP5=TIM3 +Mcu.IP6=UCPD1 +Mcu.IP7=USART2 +Mcu.IP8=USBPD +Mcu.IPNb=9 Mcu.Name=STM32G491K(C-E)Ux Mcu.Package=UFQFPN32 -Mcu.Pin0=PA1 -Mcu.Pin1=PA2 -Mcu.Pin10=VP_SYS_VS_Systick -Mcu.Pin11=VP_SYS_VS_DBSignals -Mcu.Pin12=VP_TIM3_VS_ClockSourceINT -Mcu.Pin2=PA3 -Mcu.Pin3=PA4 -Mcu.Pin4=PA5 -Mcu.Pin5=PA6 -Mcu.Pin6=PB0 -Mcu.Pin7=PA15 -Mcu.Pin8=PB5 -Mcu.Pin9=PB7 -Mcu.PinsNb=13 +Mcu.Pin0=PA0 +Mcu.Pin1=PA1 +Mcu.Pin10=PA11 +Mcu.Pin11=PA12 +Mcu.Pin12=PA15 +Mcu.Pin13=PB4 +Mcu.Pin14=PB5 +Mcu.Pin15=PB6 +Mcu.Pin16=PB7 +Mcu.Pin17=VP_SYS_VS_Systick +Mcu.Pin18=VP_SYS_VS_DBSignals +Mcu.Pin19=VP_TIM3_VS_ClockSourceINT +Mcu.Pin2=PA2 +Mcu.Pin20=VP_USBPD_VS_USBPD1 +Mcu.Pin21=VP_USBPD_VS_PD3FULL +Mcu.Pin22=VP_USBPD_VS_usbpd_tim1 +Mcu.Pin3=PA3 +Mcu.Pin4=PA4 +Mcu.Pin5=PA5 +Mcu.Pin6=PA6 +Mcu.Pin7=PB0 +Mcu.Pin8=PA9 +Mcu.Pin9=PA10 +Mcu.PinsNb=23 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32G491KEUx MxCube.Version=6.13.0 MxDb.Version=DB.6.0.130 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.EXTI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.EXTI9_5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true @@ -49,12 +101,32 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UCPD1_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:true NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA0.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultOutputPP +PA0.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD +PA0.GPIO_PuPd=GPIO_NOPULL +PA0.Locked=true +PA0.Signal=GPIO_Output PA1.GPIOParameters=GPIO_ModeDefaultEXTI PA1.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING PA1.Locked=true PA1.Signal=GPXTI1 +PA10.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultOutputPP +PA10.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD +PA10.GPIO_PuPd=GPIO_NOPULL +PA10.Locked=true +PA10.Signal=GPIO_Output +PA11.GPIOParameters=GPIO_PuPd,GPIO_ModeDefaultOutputPP +PA11.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD +PA11.GPIO_PuPd=GPIO_NOPULL +PA11.Locked=true +PA11.Signal=GPIO_Output +PA12.GPIOParameters=GPIO_PuPd +PA12.GPIO_PuPd=GPIO_PULLUP +PA12.Locked=true +PA12.Signal=GPIO_Input PA15.Locked=true PA15.Mode=I2C PA15.Signal=I2C1_SCL @@ -70,12 +142,20 @@ PA5.Locked=true PA5.Signal=GPIO_Input PA6.Locked=true PA6.Signal=GPIO_Input +PA9.GPIOParameters=GPIO_Label +PA9.GPIO_Label=TCPP02_EN +PA9.Locked=true +PA9.Signal=GPIO_Output PB0.Locked=true PB0.Signal=S_TIM3_CH3 +PB4.Mode=Source_AllSignals +PB4.Signal=UCPD1_CC2 PB5.GPIOParameters=GPIO_ModeDefaultEXTI PB5.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING PB5.Locked=true PB5.Signal=GPXTI5 +PB6.Mode=Source_AllSignals +PB6.Signal=UCPD1_CC1 PB7.Locked=true PB7.Mode=I2C PB7.Signal=I2C1_SDA @@ -110,7 +190,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM3_Init-TIM3-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_TIM3_Init-TIM3-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_I2C1_Init-I2C1-false-HAL-true,7-MX_UCPD1_Init-UCPD1-false-LL-true,8-MX_USBPD_Init-USBPD-false-HAL-false RCC.ADC12Freq_Value=72000000 RCC.ADC345Freq_Value=72000000 RCC.AHBFreq_Value=72000000 @@ -165,11 +245,19 @@ TIM3.IPParameters=Prescaler,Channel-PWM Generation3 CH3,AutoReloadPreload TIM3.Prescaler=71 USART2.IPParameters=VirtualMode-Asynchronous USART2.VirtualMode-Asynchronous=VM_ASYNC +USBPD.IPParameters=USBPD_PORT0_PDO_SRC_FIXED_SET_MAX_CURRENT_0 +USBPD.USBPD_PORT0_PDO_SRC_FIXED_SET_MAX_CURRENT_0=5000 VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM3_VS_ClockSourceINT.Mode=Internal VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT +VP_USBPD_VS_PD3FULL.Mode=PD3_Full_Stack +VP_USBPD_VS_PD3FULL.Signal=USBPD_VS_PD3FULL +VP_USBPD_VS_USBPD1.Mode=USBPD_P0 +VP_USBPD_VS_USBPD1.Signal=USBPD_VS_USBPD1 +VP_USBPD_VS_usbpd_tim1.Mode=TIM1 +VP_USBPD_VS_usbpd_tim1.Signal=USBPD_VS_usbpd_tim1 board=custom isbadioc=false