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[ion/device] Start implement external flash API
This commit is contained in:
Ruben Dashyan
209
ion/src/device/external_flash.cpp
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209
ion/src/device/external_flash.cpp
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#include "external_flash.h"
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#include <ion/src/device/regs/rcc.h>
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#include <ion/src/device/regs/gpio.h>
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#include <ion/src/device/regs/quadspi.h>
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namespace Ion {
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namespace ExternalFlash {
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namespace Device {
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void waitController() {
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while (QUADSPI.SR()->getBUSY()) {
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}
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}
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static enum DeviceStatusRegister : uint16_t {
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// Status Register 1
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BUSY = 1 << 0, // Erase, Program, Write Status Register in Progress
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WEL = 1 << 1, // Write Enable Latch
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BP0 = 1 << 2, // Block Protect
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BP1 = 1 << 3, // Block Protect
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BP2 = 1 << 4, // Block Protect
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TB = 1 << 5, // Top/Bottom Write Protect
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SEC = 1 << 6, // Sector Protect
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SRP = 1 << 7, // Status Register Protect 0
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// Status Register 2
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SRP1 = 1 << 8, // Status Register Protect 1
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QE = 1 << 9, // Quad-SPI Enable
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// Bits 10, 11, 12, 13 are reserved
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CMP = 1 << 14, //
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SUS = 1 << 15
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};
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/*
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------------------------------------------------------------------------------------------------------------------------------------------------
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Bit Volatile? Reset value Short name Long name
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------------------------------------------------------------------------------------------------------------------------------------------------
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Status Register-1 0 volatile BUSY Erase, Program, Write Status Register in Progress
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Any instruction, except for Read Register, will be ignored while BUSY=1.
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It is recommended to check the BUSY bit before sending a new instruction, after a Program, Erase, Write Status Register operation.
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TODO Status polling instead of while...
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1 volatile WEL Write Enable Latch
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must be set before any Program, Erase or Write Status Register instruction, with the Write Enable instruction.
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is automatically reset write-disable status of “0” after Power‐up and upon completion of any Program, Erase or Write Status Register instruction.
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2 non-volatile BP0 Block Protect
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3 non-volatile BP1 Block Protect
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4 non-volatile BP2 Block Protect
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5 non-volatile TB Top/Bottom Write Protect
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6 non-volatile 0 SEC Sector Protect
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controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array.
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7 non-volatile SRP Status Register Protect 0
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Status Register-2 8 non-volatile SRP1 Status Register Protect 1
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9 non-volatile QE Quad SPI Enable
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14 non-volatile 0 CMP Complement Protect
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CMP=0: a top 4KB sector can be protected while the rest of the array is not
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CMP=1: the top 4KB sector will become unprotected while the rest of the array become read-only.
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15 volatile 0 SUS Suspend Status
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------------------------------------------------------------------------------------------------------------------------------------------------
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*/
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void waitDevice() {
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do {
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ReadStatusRegister1.write();
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} while(QUADSPI.DR()->get() & 1);
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}
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void initGPIO() {
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/* Pin | Role | Mode | Function
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* -----+----------------------+-----------------------+-----------------
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* PB2 | QUADSPI CLK | Alternate Function 9 | QUADSPI CLK
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* PB6 | QUADSPI BK1_NCS | Alternate Function 10 | QUADSPI BK1_NCS
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* PC9 | QUADSPI BK1_IO0/SO | Alternate Function 9 | QUADSPI BK1_IO0
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* PD12 | QUADSPI BK1_IO1/SI | Alternate Function 9 | QUADSPI BK1_IO1
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* PC8 | QUADSPI BK1_IO2/WP | Alternate Function 9 | QUADSPI BK1_IO2
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* PD13 | QUADSPI BK1_IO3/HOLD | Alternate Function 9 | QUADSPI BK1_IO3 */
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// Enable GPIOB, C, D AHB1 peripheral clocks
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RCC.AHB1ENR()->setGPIOBEN(true);
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RCC.AHB1ENR()->setGPIOCEN(true);
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RCC.AHB1ENR()->setGPIODEN(true);
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constexpr static GPIOPin QUADSPIPins[] = {
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GPIOPin(GPIOB, 2),
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GPIOPin(GPIOB, 6),
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GPIOPin(GPIOC, 9),
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GPIOPin(GPIOD,12),
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GPIOPin(GPIOC, 8),
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GPIOPin(GPIOD,13)
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}
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for(const GPIOPin & g : QUADSPIPins) {
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g.group().MODER()->setMode(g.pin(), GPIO::MODER::Mode::AlternateFunction);
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g.group().AFR()->setAlternateFunction(g.pin(), (g == QUADSPIPins[1]) ? GPIO::AFR::AlternateFunction::AF10 : GPIO::AFR::AlternateFunction::AF9);
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}
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}
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void init() {
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initGPIO();
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// Enable QUADSPI AHB3 peripheral clocks
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RCC.AHB3ENR()->setQSPIEN(true);
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// Configure controller for target device
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QUADSPI.DCR()->setFSIZE(22); // 2^(22+1) bytes in device
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/* TODO CKMODE, CSHT
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* Instructions are initiated on the falling edge of CS and are completed on its rising edge.
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* Mode 0: SCK is low when CS is high
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* Mode 3: SCK is high when CS is high
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* Input bits are sampled/latched on the rising edge of SCK.
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* Output bits are shifted out on the falling edge of SCK.
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*
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* The IO pins should be at high impedance prior to the falling edge of the first data out clock.
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* Data bytes are shifted with Most Significant Bit first.
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*
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* Configure and enable QUADSPI peripheral
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* All instructions, except Read Data, supported SPI clock frequencies of up to 104MHz.
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* Read Data supports up to 50Mhz.
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* TODO PRESCALER
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* TODO trade-off ? consumption? */
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QUADSPI.CR()->setPRESCALER(255);
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QUADSPI.CR()->setEN(true);
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}
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class Instruction {
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public:
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using QUADSPI::CCR::OperatingMode;
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using QUADSPI::CCR::Size;
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using QUADSPI::CCR::FunctionalMode;
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constexpr Instruction(
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uint8_t instructionCode, OperatingMode IMode, bool SIOO,
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OperatingMode ADMode,
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uint8_t DCyc,
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OperatingMode DMode, uint32_t DLength,
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FunctionalMode FMode
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) {
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m_ccr = QUADSPI::CCR((uint32_t)0);
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m_ccr.setINSTRUCTION(instructionCode);
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m_ccr.setIMODE (IMode);
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m_ccr.setSIOO (SIOO);
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m_ccr.setADMODE(ADMode);
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m_ccr.setADSIZE(Size::ThreeBytes);
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m_ccr.setDCYC (DCyc);
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m_ccr.setDMODE (DMode);
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m_ccr.setFMODE (FMode);
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// DDR not supported by Adesto
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}
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void setAlternateBytes(OperatingMode ABMode, Size ABSize) {
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m_ccr.setABMODE(ABMode);
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m_ccr.setABSIZE(ABSize);
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}
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void write() {
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QUADSPI.CCR()->set(m_ccr);
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QUADSPI.DLR()->set(0);
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}
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private:
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class QUADSPI::CCR m_ccr;
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uint32_t m_dlr;
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};
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//TODO default ccr
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/* Modes IMODE ADMODE ABMODE DMODE
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* SPIStandard 1-1-1-1
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* SPIDualOutput 1-1-1-2
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* SPIDualIO 1-2-2-2
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* SPIQuadOutput 1-1-1-4
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* SPIQuadIO 1-4-4-4
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* Quad SPI instructions require the QE bit in Status Register-2 to be set.
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* QPI 4-4-4-4
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* Enable/Disable QPI instruction
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* ADSIZE is always ThreeBytes
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* MODE may be NoData*/
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/* All Read instructions can be completed after any clocked bit.
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* However, all Write, Program or Erase instructions must complete on a byte (CS driven high
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* after a full byte has been clocked) otherwise the instruction will be terminated. */
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using QUADSPI::CCR::OperatingMode;
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using QUADSPI::CCR::Size;
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using QUADSPI::CCR::FunctionalMode;
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static enum InstructionSet : Instruction {
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ReadStatusRegister1 = Instruction(0x05, OperatingMode::Single, false, OperatingMode::NoData, 0, OperatingMode::NoData, FunctionalMode::IndirectRead),
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WriteEnable = Instruction(0x06, OperatingMode::Single, false, OperatingMode::NoData, 0, OperatingMode::NoData, FunctionalMode::IndirectWrite),
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// Before any Program, Erase or Write Status Register instruction
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EraseChip = Instruction(0x60, OperatingMode::Single, false, OperatingMode::NoData, 0, OperatingMode::NoData, FunctionalMode::IndirectWrite)
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/*
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ReadStatusRegister2 = Instruction(0x35),
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ReadData = Instruction(0x03),
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Erase4kBlock = Instruction(0x20),
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PageProgram = Instruction(0x02)
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*/
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};
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void eraseChip() {
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WriteEnable.write();
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EraseChip.write();
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waitDevice();
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}
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}
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}
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}
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#endif
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36
ion/src/device/external_flash.h
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36
ion/src/device/external_flash.h
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@@ -0,0 +1,36 @@
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#ifndef ION_DEVICE_EXTERNAL_FLASH_H
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#define ION_DEVICE_EXTERNAL_FLASH_H
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// Quad-SPI on STM32 microcontroller
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// https://www.st.com/resource/en/application_note/dm00227538.pdf
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// Adesto Technologies AT25SF641
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// https://www.adestotech.com/wp-content/uploads/AT25SF641_111.pdf
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/* External Flash Memory map Address space
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* 8MiB chip 0x000000 - 0x7FFFFF
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* 2^7 64KiB blocks 0x..0000 - 0x..FFFF
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* 2^7 * 2 32KiB blocks 0x..0000 - 0x..7FFF or 0x..8000 - 0x..FFFF
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* 2^7 * 2 * 2^3 4KiB blocks 0x...000 - 0x...FFF
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* 2^7 * 2 * 2^3 * 2^4 256B pages 0x....00 - 0x....FF */
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namespace Ion {
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namespace ExternalFlash {
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namespace Device {
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// Read, Erase, Write
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// at the fastest possible speed
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void eraseChip(); //block?
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void program(uint32_t * source, uint32_t * destination, size_t length);
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void read(); // in indirect read mode
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// memory-mapped mode
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}
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}
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}
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#endif
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