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https://github.com/UpsilonNumworks/Upsilon.git
synced 2026-03-23 07:40:42 +01:00
[ion/device] External flash: include alternate bytes in Quad-SPI instructions
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@@ -67,14 +67,17 @@ static constexpr QUADSPI::CCR::OperatingMode DefaultOperatingMode = QUADSPI::CCR
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static constexpr int ClockFrequencyDivisor = 2;
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static constexpr int ChipSelectHighTime = (ClockFrequencyDivisor == 1) ? 3 : (ClockFrequencyDivisor == 2) ? 2 : 1;
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static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADSPI::CCR::OperatingMode operatingMode, Command c, uint8_t * address, uint8_t dummyCycles, uint8_t * data, size_t dataLength);
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static void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADSPI::CCR::OperatingMode operatingMode, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength);
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static inline void send_command(Command c, QUADSPI::CCR::OperatingMode operatingMode = DefaultOperatingMode) {
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send_command_full(
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QUADSPI::CCR::FunctionalMode::IndirectWrite,
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operatingMode,
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c,
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), 0, nullptr, 0
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
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0, 0,
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0,
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nullptr, 0
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);
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}
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@@ -83,7 +86,10 @@ static inline void send_write_command(Command c, uint8_t * address, uint8_t * da
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QUADSPI::CCR::FunctionalMode::IndirectWrite,
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operatingMode,
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c,
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address, 0, data, dataLength
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address,
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0, 0,
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0,
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data, dataLength
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);
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}
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@@ -92,7 +98,10 @@ static inline void send_read_command(Command c, uint8_t * address, uint8_t * dat
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QUADSPI::CCR::FunctionalMode::IndirectRead,
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operatingMode,
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c,
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address, 0, data, dataLength
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address,
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0, 0,
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0,
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data, dataLength
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);
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}
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@@ -118,11 +127,14 @@ static void set_as_memory_mapped() {
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QUADSPI::CCR::FunctionalMode::MemoryMapped,
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DefaultOperatingMode,
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Command::FastRead,
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize), FastReadDummyCycles, nullptr, 0
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reinterpret_cast<uint8_t *>(FlashAddressSpaceSize),
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0, 0,
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FastReadDummyCycles,
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nullptr, 0
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);
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}
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void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADSPI::CCR::OperatingMode operatingMode, Command c, uint8_t * address, uint8_t dummyCycles, uint8_t * data, size_t dataLength) {
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void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADSPI::CCR::OperatingMode operatingMode, Command c, uint8_t * address, uint32_t altBytes, size_t numberOfAltBytes, uint8_t dummyCycles, uint8_t * data, size_t dataLength) {
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class QUADSPI::CCR ccr(0);
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ccr.setFMODE(functionalMode);
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if (data != nullptr || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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@@ -132,6 +144,11 @@ void send_command_full(QUADSPI::CCR::FunctionalMode functionalMode, QUADSPI::CCR
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QUADSPI.DLR()->set((dataLength > 0) ? dataLength-1 : 0);
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}
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ccr.setDCYC(dummyCycles);
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if (numberOfAltBytes > 0) {
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ccr.setABMODE(operatingMode);
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ccr.setABSIZE(static_cast<QUADSPI::CCR::Size>(numberOfAltBytes - 1));
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QUADSPI.ABR()->set(altBytes);
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}
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if (address != reinterpret_cast<uint8_t *>(FlashAddressSpaceSize) || functionalMode == QUADSPI::CCR::FunctionalMode::MemoryMapped) {
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ccr.setADMODE(operatingMode);
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ccr.setADSIZE(QUADSPI::CCR::Size::ThreeBytes);
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@@ -76,7 +76,7 @@ public:
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class AR : public Register32 { // Address register
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};
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class ABR : Register32 { // Alternate bytes register
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class ABR : public Register32 { // Alternate bytes register
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};
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class DR : public Register8 { // Data register
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