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DRC, nettoyage pistes cachées, ajout logos

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This commit is contained in:
Allan Cueff
2023-12-22 16:54:45 +01:00
parent cf7f16e2c9
commit 8c21524dfc
19 changed files with 11715 additions and 6990 deletions
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1
#auto_saved_files#
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@@ -1 +0,0 @@
C:\Users\allan\OneDrive\Documents\KiCad\7.0\projects\pcb_puissance\_autosave-pcb_puissance.kicad_sch

1535
Library.pretty/logo_modelec.kicad_mod Normal file
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Library.pretty/transfo.kicad_mod
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@@ -1,7 +1,7 @@
(footprint "transfo" (version 20221018) (generator pcbnew)
(layer "F.Cu")
(attr through_hole)
(fp_text reference "REF**" (at 0 -2 unlocked) (layer "F.SilkS") hide
(fp_text reference "REF**" (at 26.4 3.05 90 unlocked) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.1)))
(tstamp 4f0c6b17-d1fe-421b-a538-15199455c776)
)

BIN
fabrication.zip
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345
fabrication/pcb_puissance-B_Cu.gbr
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@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,7.0.9*%
%TF.CreationDate,2023-12-22T16:48:57+01:00*%
%TF.CreationDate,2023-12-24T18:11:20+01:00*%
%TF.ProjectId,pcb_puissance,7063625f-7075-4697-9373-616e63652e6b,1.1*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Copper,L2,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.9) date 2023-12-22 16:48:57*
G04 Created by KiCad (PCBNEW 7.0.9) date 2023-12-24 18:11:20*
%MOMM*%
%LPD*%
G01*
@@ -52,25 +52,11 @@ G04 APERTURE LIST*
%TD*%
G04 APERTURE END LIST*
D10*
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%TD*%
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D10*
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%TD*%
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65
fabrication/pcb_puissance-B_Mask.gbr
View File

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4
fabrication/pcb_puissance-B_Paste.gbr
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4
fabrication/pcb_puissance-B_Silkscreen.gbr
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4
fabrication/pcb_puissance-Edge_Cuts.gbr
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1789
fabrication/pcb_puissance-F_Cu.gbr
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File diff suppressed because it is too large Load Diff

65
fabrication/pcb_puissance-F_Mask.gbr
View File

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4
fabrication/pcb_puissance-F_Paste.gbr
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fabrication/pcb_puissance-F_Silkscreen.gbr
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File diff suppressed because it is too large Load Diff

4
fabrication/pcb_puissance-NPTH.drl
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FMAT,2

33
fabrication/pcb_puissance-PTH.drl
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X5.7087Y-2.9528
X5.7087Y-3.1496
X5.7087Y-3.1496
X5.7087Y-3.3465
X5.7087Y-3.5433
T2

4
fabrication/pcb_puissance-User_Drawings.gbr
View File

@@ -1,11 +1,11 @@
%TF.GenerationSoftware,KiCad,Pcbnew,7.0.9*%
%TF.CreationDate,2023-12-22T16:48:57+01:00*%
%TF.CreationDate,2023-12-24T18:11:20+01:00*%
%TF.ProjectId,pcb_puissance,7063625f-7075-4697-9373-616e63652e6b,1.1*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,OtherDrawing,Comment*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.9) date 2023-12-22 16:48:57*
G04 Created by KiCad (PCBNEW 7.0.9) date 2023-12-24 18:11:20*
%MOMM*%
%LPD*%
G01*

4
fabrication/pcb_puissance-job.gbrjob
View File

@@ -5,7 +5,7 @@
"Application": "Pcbnew",
"Version": "7.0.9"
},
"CreationDate": "2023-12-22T16:48:57+01:00"
"CreationDate": "2023-12-24T18:11:20+01:00"
},
"GeneralSpecs": {
"ProjectId": {
@@ -27,7 +27,7 @@
"PadToPad": 0.2,
"PadToTrack": 0.2,
"TrackToTrack": 0.2,
"MinLineWidth": 0.25,
"MinLineWidth": 0.5,
"TrackToRegion": 0.5,
"RegionToRegion": 0.5
}

9839
pcb_puissance.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

6
pcb_puissance.kicad_pro
View File

@@ -105,9 +105,9 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.25,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_copper_edge_clearance": 0.25,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
@@ -117,7 +117,7 @@
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_track_width": 0.5,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_clearance": 0.0,