UpsilonNumworks/Upsilon
1
0
Fork 0
mirror of https://github.com/UpsilonNumworks/Upsilon.git synced 2026-03-18 21:30:38 +01:00
Code Issues Packages Projects Releases Wiki Activity

[ion] N0101: configure MPU for QUASPI

Browse Source 
L1 cache can issue speculative reads to any QUADSPI address (among the 256MB).
We configure the cache to prevent such accesses
This commit is contained in:
Émilie Feral
2019-04-04 13:43:38 +02:00
parent a12bb26d40
commit 1e3a1477eb
2 changed files with 42 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
ion/src/device/n0101/drivers/board.cpp
View File

@@ -26,7 +26,18 @@ void initL1Cache() {
}
void initMPU() {
// Configure MPU settings for the FMC memory area
// 1. Disable the MPU
// 1.1 Memory barrier
asm volatile("dmb 0xF":::"memory");
// 1.2 Disable fault exceptions
CM4.SHCRS()->setMEMFAULTENA(false);
// 1.3 Disable the MPU and clear the control register
MPU.CTRL()->setENABLE(false);
// 2. MPU settings
// 2.1 Configure a MPU region for the FMC memory area
// This is needed for interfacing with the LCD
MPU.RNR()->setREGION(0x00);
MPU.RBAR()->setADDR(0x60000000);
@@ -39,8 +50,37 @@ void initMPU() {
MPU.RASR()->setB(0);
MPU.RASR()->setENABLE(true);
// 2.2 Configure MPU regions for the QUADSPI peripheral
// TODO: lengthy comment
MPU.RNR()->setREGION(0x01);
MPU.RBAR()->setADDR(0x90000000);
MPU.RASR()->setSIZE(MPU::RASR::RegionSize::_256MB);
MPU.RASR()->setAP(MPU::RASR::AccessPermission::NoAccess);
MPU.RASR()->setXN(true);
MPU.RASR()->setTEX(0);
MPU.RASR()->setS(0);
MPU.RASR()->setC(0);
MPU.RASR()->setB(0);
MPU.RASR()->setENABLE(true);
MPU.RNR()->setREGION(0x02);
MPU.RBAR()->setADDR(0x90000000);
MPU.RASR()->setSIZE(MPU::RASR::RegionSize::_8MB);
MPU.RASR()->setAP(MPU::RASR::AccessPermission::RW);
MPU.RASR()->setXN(false);
MPU.RASR()->setTEX(0);
MPU.RASR()->setS(0);
MPU.RASR()->setC(1);
MPU.RASR()->setB(0);
MPU.RASR()->setENABLE(true);
// 2.3 Enable MPU
MPU.CTRL()->setPRIVDEFENA(true);
MPU.CTRL()->setENABLE(true);
// 3. Data/instruction synchronisation barriers to ensure that the new MPU configuration is used by subsequent instructions.
asm volatile("dsb 0xF":::"memory");
asm volatile("isb 0xF":::"memory");
}
void init() {

1
ion/src/device/shared/regs/mpu.h
View File

@@ -63,6 +63,7 @@ public:
_4MB = 21,
_8MB = 22,
_32MB = 24,
_256MB = 27,
_1GB = 0b11101,
_4GB = 0b11111
};