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Unified AFR

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This commit is contained in:
Romain Goyet
2015-05-09 20:52:33 +02:00
parent 7baeb0ce30
commit a646d30b26
3 changed files with 82 additions and 15 deletions
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70
platform/stm32f429/init_lcd.c
View File

@@ -74,8 +74,8 @@ static void init_spi_gpios() {
// More precisely, PF7 and PF9 are doing SPI-SCL and SPI-SDO/SDO.
// This corresponds to Alternate Function 5 using SPI port 5
// (See STM32F429 p78)
REGISTER_SET_VALUE(GPIO_AFRL(GPIOF), AFR(7), 5); // Pin 7 is in the "low" register
REGISTER_SET_VALUE(GPIO_AFRH(GPIOF), AFR(9), 5); // and pin 9 in the "high" one
REGISTER_SET_VALUE(GPIO_AFR(GPIOF, 7), AFR(7), 5);
REGISTER_SET_VALUE(GPIO_AFR(GPIOF, 9), AFR(9), 5);
}
static void init_spi_port() {
@@ -135,11 +135,7 @@ static void init_rgb_gpios() {
// The LTDC is always mapped to AF14
for (int i=0; i<RGB_PIN_COUNT; i++) {
struct gpio_pin * pin = rgb_pins+i;
if (pin->number > 7) {
REGISTER_SET_VALUE(GPIO_AFRL(pin->group), AFR(pin->number), 14);
} else {
REGISTER_SET_VALUE(GPIO_AFRH(pin->group), AFR(pin->number), 14);
}
REGISTER_SET_VALUE(GPIO_AFR(pin->group, pin->number), AFR(pin->number), 14);
}
//FIXME: Apprently DMA should be enabled?
@@ -235,6 +231,66 @@ static void init_rgb_timings() {
// Same for the pixel clock, we don't want it inverted
}
static void init_rgb_layers() {
#if 0
/* STEP 7: Configure the Layer1/2 parameters by programming:
– The Layer window horizontal and vertical position in the LTDC_LxWHPCR and LTDC_WVPCR registers. The layer window must be in the active data area.
– The pixel input format in the LTDC_LxPFCR register
– The color frame buffer start address in the LTDC_LxCFBAR register
– The line length and pitch of the color frame buffer in the LTDC_LxCFBLR register
– The number of lines of the color frame buffer in the LTDC_LxCFBLNR register
– if needed, load the CLUT with the RGB values and its address in the LTDC_LxCLUTWR register
– If needed, configure the default color and the blending factors respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers
*/
long * LTDC_L1WHPCR = (long *)(LCD_TFT_BASE + 0x88); // Window horizontal position config
*LTDC_L1WHPCR = set_bits(*LTDC_L1WHPCR, 11, 0, lcd_panel_hsync+lcd_panel_hbp);
*LTDC_L1WHPCR = set_bits(*LTDC_L1WHPCR, 27, 16, lcd_panel_hsync+lcd_panel_hbp+lcd_panel_hadr);
long * LTDC_L1WVPCR = (long *)(LCD_TFT_BASE + 0x8C); // Window vertical position config
*LTDC_L1WVPCR = set_bits(*LTDC_L1WVPCR, 11, 0, lcd_panel_vsync+lcd_panel_vbp);
*LTDC_L1WVPCR = set_bits(*LTDC_L1WVPCR, 27, 16, lcd_panel_vsync+lcd_panel_vbp+lcd_panel_vadr);
long * LTDC_L1PFCR = (long *)(LCD_TFT_BASE + 0x94); // Frame buffer pixel format
*LTDC_L1PFCR = set_bits(*LTDC_L1PFCR, 2, 0, 0x0); // 0x0 = ARGB8888
long * LTDC_L1CFBAR = (long *)(LCD_TFT_BASE + 0xAC); // Frame buffer address
*LTDC_L1CFBAR = 0x2000000;
long * LTDC_L1CFBLR = (long *)(LCD_TFT_BASE + 0xB0); // Frame buffer length
*LTDC_L1CFBLR = set_bits(*LTDC_L1CFBLR, 28, 16, 960); // Number of bytes per lines in the framebuffer. 240 * 4 (RGBA888)
*LTDC_L1CFBLR = set_bits(*LTDC_L1CFBLR, 12, 0, 963); // The doc says "length + 3". Here goes...
long * LTDC_L1CFBLNR = (long *)(LCD_TFT_BASE + 0xB4);
*LTDC_L1CFBLNR = set_bits(*LTDC_L1CFBLNR, 10, 0, 320); // Number of lines
/*
long * LTDC_L2WHPCR = (long *)(LCD_TFT_BASE + 0x108);
*LTDC_L2WHPCR = set_bits(*LTDC_L2WHPCR, 11, 0, lcd_panel_hsync+lcd_panel_hbp);
*LTDC_L2WHPCR = set_bits(*LTDC_L2WHPCR, 27, 16, lcd_panel_hsync+lcd_panel_hbp+lcd_panel_hadr);
long * LTDC_L2WWPCR = (long *)(LCD_TFT_BASE + 0x10C);
*LTDC_L2WVPCR = set_bits(*LTDC_L2WVPCR, 11, 0, lcd_panel_vsync+lcd_panel_vbp);
*LTDC_L2WVPCR = set_bits(*LTDC_L2WVPCR, 27, 16, lcd_panel_vsync+lcd_panel_vbp+lcd_panel_vadr);
long * LTDC_L2PFCR = (long *)(LCD_TFT_BASE + 0x114);
long * LTDC_L2CFBAR = (long *)(LCD_TFT_BASE + 0x12C);
long * LTDC_L2CFBLNR = (long *)(LCD_TFT_BASE + 0x134);
long * LTDC_L2CR = (long *)(LCD_TFT_BASE + 0x104);
*/
// STEP 8 : Enable layer 1
long * LTDC_L1CR = (long *)(LCD_TFT_BASE + 0x84);
*LTDC_L1CR = set_bits(*LTDC_L1CR, 4, 4, 0x0); // bit 4 = CLUTEN: Disable color look-up table
*LTDC_L1CR = set_bits(*LTDC_L1CR, 1, 1, 0x0); // bit 1 = COLKEN: Color keying, disabledd
*LTDC_L1CR = set_bits(*LTDC_L1CR, 0, 0, 0x1); // bit 1 = LEN, LayerENable: Enable
// STEP 9 : If needed, enable color keing and dithering
// STEP 10: Reload the shadow register
long * LTDC_SRCR = (long *)(LCD_TFT_BASE + 0x24);
*LTDC_SRCR = set_bits(*LTDC_SRCR, 1, 1, 0x1); // Ask for reload on next VBLANK
#endif
}
// Panel
static void spi_5_write(char * data, size_t size);

1
platform/stm32f429/registers/gpio.h
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@@ -53,6 +53,7 @@
#define GPIO_AFRL(gpio_group) GPIO_REGISTER_AT(gpio_group, 0x20)
#define GPIO_AFRH(gpio_group) GPIO_REGISTER_AT(gpio_group, 0x24)
#define GPIO_AFR(gpio_group,pin) GPIO_REGISTER_AT(gpio_group, 0x20+(pin>7?0x4:0x0))
#define LOW_BIT_AFR(v) (4*(v%8))
#define HIGH_BIT_AFR(v) (4*(v%8)+3)

26
platform/stm32f429/registers/ltdc.h
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@@ -68,16 +68,26 @@
#define LTDC_VSPOL (1<<30)
#define LTDC_HSPOL (1<<31)
// LTDC shadow reload configuration register
#define LTDC_SRCR LTDC_REGISTER_AT(0x24)
#define LTDC_IMR (1<<0)
#define LTDC_VBR (1<<1)
// LTDC layer control register
#define LTDC_LAYER1 0
#define LTDC_LAYER2 1
#define LTDC_LCR(layer) LTDC_REGISTER_AT(0x84+(0x80*layer))
#define LTDC_LEN (1<<0)
#define LTDC_COLKEN (1<<1)
#define LTDC_CLUTEN (1<<4)
#if 0
typedef struct {
unsigned int IMR:1;
unsigned int VBR:1;
unsigned int :30;
} LTDC_SRCR_t;
extern LTDC_SRCR_t * LTDC_SRCR;
typedef struct {
unsigned int BCBLUE:8;
unsigned int BCGREEN:8;